From 3f1f6dd77503276c87ce3cbe983db2891df53f23 Mon Sep 17 00:00:00 2001 From: rmsyn Date: Sat, 2 Dec 2023 21:35:52 +0000 Subject: [PATCH] pac: update generated code with `svd2rust` 0.31.2 Updates generated peripheral code using `svd2rust` version `0.31.2`. --- jh7110-vf2-12a-pac/Cargo.toml | 7 +- jh7110-vf2-12a-pac/src/aon_pinctrl.rs | 286 ++- .../aon_iomux_cfgsaif_syscfg100.rs | 12 +- .../aon_iomux_cfgsaif_syscfg104.rs | 12 +- .../aon_iomux_cfgsaif_syscfg108.rs | 12 +- .../aon_iomux_cfgsaif_syscfg112.rs | 12 +- .../aon_iomux_cfgsaif_syscfg116.rs | 12 +- .../aon_iomux_cfgsaif_syscfg120.rs | 12 +- .../aon_iomux_cfgsaif_syscfg124.rs | 12 +- .../aon_iomux_cfgsaif_syscfg128.rs | 12 +- .../aon_iomux_cfgsaif_syscfg132.rs | 12 +- .../aon_iomux_cfgsaif_syscfg136.rs | 12 +- .../aon_iomux_cfgsaif_syscfg140.rs | 12 +- .../aon_iomux_cfgsaif_syscfg144.rs | 12 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs | 12 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs | 48 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs | 48 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs | 48 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs | 48 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs | 18 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs | 12 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs | 12 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs | 12 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs | 12 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs | 12 +- .../aon_iomux_cfgsaif_syscfg_fmux0.rs | 30 +- .../aon_iomux_cfgsaif_syscfg_fmux1.rs | 30 +- .../aon_iomux_cfgsaif_syscfg_fmux2.rs | 54 +- .../aon_iomux_cfgsaif_syscfg_fmux3.rs | 14 +- .../aon_iomux_cfgsaif_syscfg_ioirq10.rs | 6 +- .../aon_iomux_cfgsaif_syscfg_ioirq11.rs | 6 +- .../aon_iomux_cfgsaif_syscfg_ioirq4.rs | 14 +- .../aon_iomux_cfgsaif_syscfg_ioirq5.rs | 14 +- .../aon_iomux_cfgsaif_syscfg_ioirq6.rs | 12 +- .../aon_iomux_cfgsaif_syscfg_ioirq7.rs | 12 +- .../aon_iomux_cfgsaif_syscfg_ioirq8.rs | 14 +- .../aon_iomux_cfgsaif_syscfg_ioirq9.rs | 6 +- jh7110-vf2-12a-pac/src/aon_syscon.rs | 90 +- .../src/aon_syscon/aon_sysconsaif_syscfg0.rs | 12 +- .../src/aon_syscon/aon_sysconsaif_syscfg12.rs | 63 +- .../src/aon_syscon/aon_sysconsaif_syscfg16.rs | 6 +- .../src/aon_syscon/aon_sysconsaif_syscfg20.rs | 6 +- .../src/aon_syscon/aon_sysconsaif_syscfg24.rs | 6 +- .../src/aon_syscon/aon_sysconsaif_syscfg28.rs | 6 +- .../src/aon_syscon/aon_sysconsaif_syscfg32.rs | 6 +- .../src/aon_syscon/aon_sysconsaif_syscfg36.rs | 6 +- .../src/aon_syscon/aon_sysconsaif_syscfg4.rs | 6 +- .../src/aon_syscon/aon_sysconsaif_syscfg40.rs | 18 +- .../src/aon_syscon/aon_sysconsaif_syscfg8.rs | 6 +- jh7110-vf2-12a-pac/src/aoncrg.rs | 130 +- .../src/aoncrg/aoncrg_rst_status.rs | 56 +- .../src/aoncrg/clk_ahb_gmac5.rs | 12 +- jh7110-vf2-12a-pac/src/aoncrg/clk_aon_apb.rs | 12 +- .../src/aoncrg/clk_axi_gmac5.rs | 12 +- .../src/aoncrg/clk_gmac0_rmii_rtx.rs | 12 +- .../src/aoncrg/clk_gmac5_axi64_rx.rs | 12 +- .../src/aoncrg/clk_gmac5_axi64_rxi.rs | 12 +- .../src/aoncrg/clk_gmac5_axi64_tx.rs | 12 +- .../src/aoncrg/clk_gmac5_axi64_txi.rs | 12 +- jh7110-vf2-12a-pac/src/aoncrg/clk_optc_apb.rs | 12 +- jh7110-vf2-12a-pac/src/aoncrg/clk_osc.rs | 12 +- .../src/aoncrg/clk_rtc_hms_apb.rs | 12 +- .../src/aoncrg/clk_rtc_hms_cal.rs | 12 +- .../src/aoncrg/clk_rtc_hms_osc32k.rs | 12 +- .../src/aoncrg/clk_rtc_internal.rs | 12 +- .../src/aoncrg/soft_rst_addr_sel.rs | 56 +- jh7110-vf2-12a-pac/src/clint.rs | 94 +- jh7110-vf2-12a-pac/src/clint/msip_0.rs | 8 +- jh7110-vf2-12a-pac/src/clint/msip_1.rs | 8 +- jh7110-vf2-12a-pac/src/clint/msip_2.rs | 8 +- jh7110-vf2-12a-pac/src/clint/msip_3.rs | 8 +- jh7110-vf2-12a-pac/src/clint/msip_4.rs | 8 +- jh7110-vf2-12a-pac/src/clint/mtime.rs | 8 +- jh7110-vf2-12a-pac/src/clint/mtimecmp_0.rs | 8 +- jh7110-vf2-12a-pac/src/clint/mtimecmp_1.rs | 8 +- jh7110-vf2-12a-pac/src/clint/mtimecmp_2.rs | 8 +- jh7110-vf2-12a-pac/src/clint/mtimecmp_3.rs | 8 +- jh7110-vf2-12a-pac/src/clint/mtimecmp_4.rs | 8 +- jh7110-vf2-12a-pac/src/generic.rs | 177 +- jh7110-vf2-12a-pac/src/generic/raw.rs | 20 +- jh7110-vf2-12a-pac/src/i2c0.rs | 306 ++- jh7110-vf2-12a-pac/src/i2c0/clr_activity.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/clr_gen_call.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/clr_intr.rs | 92 +- jh7110-vf2-12a-pac/src/i2c0/clr_rd_req.rs | 12 +- .../src/i2c0/clr_restart_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/clr_rx_done.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/clr_rx_over.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/clr_rx_under.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/clr_start_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/clr_stop_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/clr_tx_abrt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/clr_tx_over.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/comp_param_1.rs | 6 +- jh7110-vf2-12a-pac/src/i2c0/comp_type.rs | 6 +- jh7110-vf2-12a-pac/src/i2c0/comp_version.rs | 6 +- jh7110-vf2-12a-pac/src/i2c0/con.rs | 68 +- jh7110-vf2-12a-pac/src/i2c0/data_cmd.rs | 36 +- jh7110-vf2-12a-pac/src/i2c0/enable.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/enable_status.rs | 36 +- jh7110-vf2-12a-pac/src/i2c0/fs_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/fs_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/hs_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/hs_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/intr_mask.rs | 92 +- jh7110-vf2-12a-pac/src/i2c0/intr_stat.rs | 6 +- jh7110-vf2-12a-pac/src/i2c0/raw_intr_stat.rs | 6 +- jh7110-vf2-12a-pac/src/i2c0/rx_tl.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/rxflr.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/sar.rs | 18 +- jh7110-vf2-12a-pac/src/i2c0/sda_hold.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/ss_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/ss_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/status.rs | 6 +- jh7110-vf2-12a-pac/src/i2c0/tar.rs | 24 +- jh7110-vf2-12a-pac/src/i2c0/tx_abrt_source.rs | 6 +- jh7110-vf2-12a-pac/src/i2c0/tx_tl.rs | 12 +- jh7110-vf2-12a-pac/src/i2c0/txflr.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1.rs | 306 ++- jh7110-vf2-12a-pac/src/i2c1/clr_activity.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/clr_gen_call.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/clr_intr.rs | 92 +- jh7110-vf2-12a-pac/src/i2c1/clr_rd_req.rs | 12 +- .../src/i2c1/clr_restart_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/clr_rx_done.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/clr_rx_over.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/clr_rx_under.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/clr_start_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/clr_stop_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/clr_tx_abrt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/clr_tx_over.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/comp_param_1.rs | 6 +- jh7110-vf2-12a-pac/src/i2c1/comp_type.rs | 6 +- jh7110-vf2-12a-pac/src/i2c1/comp_version.rs | 6 +- jh7110-vf2-12a-pac/src/i2c1/con.rs | 68 +- jh7110-vf2-12a-pac/src/i2c1/data_cmd.rs | 36 +- jh7110-vf2-12a-pac/src/i2c1/enable.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/enable_status.rs | 36 +- jh7110-vf2-12a-pac/src/i2c1/fs_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/fs_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/hs_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/hs_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/intr_mask.rs | 92 +- jh7110-vf2-12a-pac/src/i2c1/intr_stat.rs | 6 +- jh7110-vf2-12a-pac/src/i2c1/raw_intr_stat.rs | 6 +- jh7110-vf2-12a-pac/src/i2c1/rx_tl.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/rxflr.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/sar.rs | 18 +- jh7110-vf2-12a-pac/src/i2c1/sda_hold.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/ss_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/ss_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/status.rs | 6 +- jh7110-vf2-12a-pac/src/i2c1/tar.rs | 24 +- jh7110-vf2-12a-pac/src/i2c1/tx_abrt_source.rs | 6 +- jh7110-vf2-12a-pac/src/i2c1/tx_tl.rs | 12 +- jh7110-vf2-12a-pac/src/i2c1/txflr.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2.rs | 306 ++- jh7110-vf2-12a-pac/src/i2c2/clr_activity.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/clr_gen_call.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/clr_intr.rs | 92 +- jh7110-vf2-12a-pac/src/i2c2/clr_rd_req.rs | 12 +- .../src/i2c2/clr_restart_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/clr_rx_done.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/clr_rx_over.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/clr_rx_under.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/clr_start_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/clr_stop_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/clr_tx_abrt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/clr_tx_over.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/comp_param_1.rs | 6 +- jh7110-vf2-12a-pac/src/i2c2/comp_type.rs | 6 +- jh7110-vf2-12a-pac/src/i2c2/comp_version.rs | 6 +- jh7110-vf2-12a-pac/src/i2c2/con.rs | 68 +- jh7110-vf2-12a-pac/src/i2c2/data_cmd.rs | 36 +- jh7110-vf2-12a-pac/src/i2c2/enable.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/enable_status.rs | 36 +- jh7110-vf2-12a-pac/src/i2c2/fs_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/fs_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/hs_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/hs_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/intr_mask.rs | 92 +- jh7110-vf2-12a-pac/src/i2c2/intr_stat.rs | 6 +- jh7110-vf2-12a-pac/src/i2c2/raw_intr_stat.rs | 6 +- jh7110-vf2-12a-pac/src/i2c2/rx_tl.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/rxflr.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/sar.rs | 18 +- jh7110-vf2-12a-pac/src/i2c2/sda_hold.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/ss_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/ss_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/status.rs | 6 +- jh7110-vf2-12a-pac/src/i2c2/tar.rs | 24 +- jh7110-vf2-12a-pac/src/i2c2/tx_abrt_source.rs | 6 +- jh7110-vf2-12a-pac/src/i2c2/tx_tl.rs | 12 +- jh7110-vf2-12a-pac/src/i2c2/txflr.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3.rs | 306 ++- jh7110-vf2-12a-pac/src/i2c3/clr_activity.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/clr_gen_call.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/clr_intr.rs | 92 +- jh7110-vf2-12a-pac/src/i2c3/clr_rd_req.rs | 12 +- .../src/i2c3/clr_restart_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/clr_rx_done.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/clr_rx_over.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/clr_rx_under.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/clr_start_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/clr_stop_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/clr_tx_abrt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/clr_tx_over.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/comp_param_1.rs | 6 +- jh7110-vf2-12a-pac/src/i2c3/comp_type.rs | 6 +- jh7110-vf2-12a-pac/src/i2c3/comp_version.rs | 6 +- jh7110-vf2-12a-pac/src/i2c3/con.rs | 68 +- jh7110-vf2-12a-pac/src/i2c3/data_cmd.rs | 36 +- jh7110-vf2-12a-pac/src/i2c3/enable.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/enable_status.rs | 36 +- jh7110-vf2-12a-pac/src/i2c3/fs_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/fs_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/hs_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/hs_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/intr_mask.rs | 92 +- jh7110-vf2-12a-pac/src/i2c3/intr_stat.rs | 6 +- jh7110-vf2-12a-pac/src/i2c3/raw_intr_stat.rs | 6 +- jh7110-vf2-12a-pac/src/i2c3/rx_tl.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/rxflr.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/sar.rs | 18 +- jh7110-vf2-12a-pac/src/i2c3/sda_hold.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/ss_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/ss_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/status.rs | 6 +- jh7110-vf2-12a-pac/src/i2c3/tar.rs | 24 +- jh7110-vf2-12a-pac/src/i2c3/tx_abrt_source.rs | 6 +- jh7110-vf2-12a-pac/src/i2c3/tx_tl.rs | 12 +- jh7110-vf2-12a-pac/src/i2c3/txflr.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4.rs | 306 ++- jh7110-vf2-12a-pac/src/i2c4/clr_activity.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/clr_gen_call.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/clr_intr.rs | 92 +- jh7110-vf2-12a-pac/src/i2c4/clr_rd_req.rs | 12 +- .../src/i2c4/clr_restart_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/clr_rx_done.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/clr_rx_over.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/clr_rx_under.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/clr_start_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/clr_stop_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/clr_tx_abrt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/clr_tx_over.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/comp_param_1.rs | 6 +- jh7110-vf2-12a-pac/src/i2c4/comp_type.rs | 6 +- jh7110-vf2-12a-pac/src/i2c4/comp_version.rs | 6 +- jh7110-vf2-12a-pac/src/i2c4/con.rs | 68 +- jh7110-vf2-12a-pac/src/i2c4/data_cmd.rs | 36 +- jh7110-vf2-12a-pac/src/i2c4/enable.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/enable_status.rs | 36 +- jh7110-vf2-12a-pac/src/i2c4/fs_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/fs_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/hs_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/hs_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/intr_mask.rs | 92 +- jh7110-vf2-12a-pac/src/i2c4/intr_stat.rs | 6 +- jh7110-vf2-12a-pac/src/i2c4/raw_intr_stat.rs | 6 +- jh7110-vf2-12a-pac/src/i2c4/rx_tl.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/rxflr.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/sar.rs | 18 +- jh7110-vf2-12a-pac/src/i2c4/sda_hold.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/ss_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/ss_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/status.rs | 6 +- jh7110-vf2-12a-pac/src/i2c4/tar.rs | 24 +- jh7110-vf2-12a-pac/src/i2c4/tx_abrt_source.rs | 6 +- jh7110-vf2-12a-pac/src/i2c4/tx_tl.rs | 12 +- jh7110-vf2-12a-pac/src/i2c4/txflr.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5.rs | 306 ++- jh7110-vf2-12a-pac/src/i2c5/clr_activity.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/clr_gen_call.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/clr_intr.rs | 92 +- jh7110-vf2-12a-pac/src/i2c5/clr_rd_req.rs | 12 +- .../src/i2c5/clr_restart_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/clr_rx_done.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/clr_rx_over.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/clr_rx_under.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/clr_start_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/clr_stop_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/clr_tx_abrt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/clr_tx_over.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/comp_param_1.rs | 6 +- jh7110-vf2-12a-pac/src/i2c5/comp_type.rs | 6 +- jh7110-vf2-12a-pac/src/i2c5/comp_version.rs | 6 +- jh7110-vf2-12a-pac/src/i2c5/con.rs | 68 +- jh7110-vf2-12a-pac/src/i2c5/data_cmd.rs | 36 +- jh7110-vf2-12a-pac/src/i2c5/enable.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/enable_status.rs | 36 +- jh7110-vf2-12a-pac/src/i2c5/fs_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/fs_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/hs_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/hs_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/intr_mask.rs | 92 +- jh7110-vf2-12a-pac/src/i2c5/intr_stat.rs | 6 +- jh7110-vf2-12a-pac/src/i2c5/raw_intr_stat.rs | 6 +- jh7110-vf2-12a-pac/src/i2c5/rx_tl.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/rxflr.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/sar.rs | 18 +- jh7110-vf2-12a-pac/src/i2c5/sda_hold.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/ss_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/ss_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/status.rs | 6 +- jh7110-vf2-12a-pac/src/i2c5/tar.rs | 24 +- jh7110-vf2-12a-pac/src/i2c5/tx_abrt_source.rs | 6 +- jh7110-vf2-12a-pac/src/i2c5/tx_tl.rs | 12 +- jh7110-vf2-12a-pac/src/i2c5/txflr.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6.rs | 306 ++- jh7110-vf2-12a-pac/src/i2c6/clr_activity.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/clr_gen_call.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/clr_intr.rs | 92 +- jh7110-vf2-12a-pac/src/i2c6/clr_rd_req.rs | 12 +- .../src/i2c6/clr_restart_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/clr_rx_done.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/clr_rx_over.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/clr_rx_under.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/clr_start_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/clr_stop_det.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/clr_tx_abrt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/clr_tx_over.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/comp_param_1.rs | 6 +- jh7110-vf2-12a-pac/src/i2c6/comp_type.rs | 6 +- jh7110-vf2-12a-pac/src/i2c6/comp_version.rs | 6 +- jh7110-vf2-12a-pac/src/i2c6/con.rs | 68 +- jh7110-vf2-12a-pac/src/i2c6/data_cmd.rs | 36 +- jh7110-vf2-12a-pac/src/i2c6/enable.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/enable_status.rs | 36 +- jh7110-vf2-12a-pac/src/i2c6/fs_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/fs_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/hs_scl_hcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/hs_scl_lcnt.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/intr_mask.rs | 92 +- jh7110-vf2-12a-pac/src/i2c6/intr_stat.rs | 6 +- jh7110-vf2-12a-pac/src/i2c6/raw_intr_stat.rs | 6 +- jh7110-vf2-12a-pac/src/i2c6/rx_tl.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/rxflr.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/sar.rs | 18 +- jh7110-vf2-12a-pac/src/i2c6/sda_hold.rs | 12 +- jh7110-vf2-12a-pac/src/i2c6/ss_scl_hcnt.rs | 12 +- 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jh7110-vf2-12a-pac/src/plic/priority_81.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_82.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_83.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_84.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_85.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_86.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_87.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_88.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_89.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_9.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_90.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_91.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_92.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_93.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_94.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_95.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_96.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_97.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_98.rs | 8 +- jh7110-vf2-12a-pac/src/plic/priority_99.rs | 8 +- jh7110-vf2-12a-pac/src/plic/threshold_0.rs | 8 +- jh7110-vf2-12a-pac/src/plic/threshold_1.rs | 8 +- jh7110-vf2-12a-pac/src/plic/threshold_2.rs | 8 +- jh7110-vf2-12a-pac/src/plic/threshold_3.rs | 8 +- jh7110-vf2-12a-pac/src/plic/threshold_4.rs | 8 +- jh7110-vf2-12a-pac/src/pmu.rs | 176 +- .../src/pmu/current_power_mode.rs | 48 +- .../src/pmu/current_seq_state.rs | 6 +- .../src/pmu/encourage_type_crd.rs | 6 +- jh7110-vf2-12a-pac/src/pmu/event_status.rs | 6 +- .../src/pmu/hard_event_turn_on_mask.rs | 72 +- .../src/pmu/hard_turn_on_power_mode.rs | 48 +- jh7110-vf2-12a-pac/src/pmu/hw_event_crd.rs | 6 +- jh7110-vf2-12a-pac/src/pmu/int_status.rs | 6 +- jh7110-vf2-12a-pac/src/pmu/lp_timeout.rs | 12 +- jh7110-vf2-12a-pac/src/pmu/pch_active.rs | 6 +- jh7110-vf2-12a-pac/src/pmu/pch_bypass.rs | 12 +- jh7110-vf2-12a-pac/src/pmu/pch_pstate.rs | 12 +- jh7110-vf2-12a-pac/src/pmu/pch_timeout.rs | 12 +- jh7110-vf2-12a-pac/src/pmu/pdc0.rs | 42 +- jh7110-vf2-12a-pac/src/pmu/pdc1.rs | 42 +- jh7110-vf2-12a-pac/src/pmu/pdc2.rs | 42 +- .../src/pmu/soft_turn_off_power_mode.rs | 48 +- .../src/pmu/soft_turn_on_power_mode.rs | 48 +- jh7110-vf2-12a-pac/src/pmu/sw_encourage.rs | 12 +- jh7110-vf2-12a-pac/src/pmu/tim.rs | 36 +- jh7110-vf2-12a-pac/src/pmu/timeout_seq_thd.rs | 12 +- jh7110-vf2-12a-pac/src/pwm.rs | 34 +- jh7110-vf2-12a-pac/src/pwm/cntr.rs | 12 +- jh7110-vf2-12a-pac/src/pwm/ctrl.rs | 62 +- jh7110-vf2-12a-pac/src/pwm/hrc.rs | 12 +- jh7110-vf2-12a-pac/src/pwm/lrc.rs | 12 +- jh7110-vf2-12a-pac/src/qspi.rs | 262 ++- jh7110-vf2-12a-pac/src/qspi/cmd_address.rs | 12 +- jh7110-vf2-12a-pac/src/qspi/cmd_ctrl.rs | 68 +- .../src/qspi/cmd_read_at_lower.rs | 12 +- .../src/qspi/cmd_read_at_upper.rs | 12 +- .../src/qspi/cmd_write_at_lower.rs | 12 +- .../src/qspi/cmd_write_at_upper.rs | 12 +- jh7110-vf2-12a-pac/src/qspi/config.rs | 62 +- jh7110-vf2-12a-pac/src/qspi/delay.rs | 30 +- jh7110-vf2-12a-pac/src/qspi/dma.rs | 18 +- jh7110-vf2-12a-pac/src/qspi/ext_lower.rs | 24 +- jh7110-vf2-12a-pac/src/qspi/indirect_rd.rs | 24 +- .../src/qspi/indirect_rd_bytes.rs | 12 +- .../src/qspi/indirect_rd_start_addr.rs | 12 +- .../src/qspi/indirect_rd_watermark.rs | 12 +- .../src/qspi/indirect_trigger.rs | 12 +- jh7110-vf2-12a-pac/src/qspi/indirect_wr.rs | 24 +- .../src/qspi/indirect_wr_bytes.rs | 12 +- .../src/qspi/indirect_wr_start_addr.rs | 12 +- .../src/qspi/indirect_wr_watermark.rs | 12 +- jh7110-vf2-12a-pac/src/qspi/irq_mask.rs | 56 +- jh7110-vf2-12a-pac/src/qspi/irq_status.rs | 56 +- jh7110-vf2-12a-pac/src/qspi/mode_bit.rs | 12 +- jh7110-vf2-12a-pac/src/qspi/polling_status.rs | 18 +- jh7110-vf2-12a-pac/src/qspi/rd_instr.rs | 42 +- jh7110-vf2-12a-pac/src/qspi/read_capture.rs | 18 +- jh7110-vf2-12a-pac/src/qspi/remap.rs | 12 +- jh7110-vf2-12a-pac/src/qspi/sdram_level.rs | 6 +- jh7110-vf2-12a-pac/src/qspi/size.rs | 24 +- jh7110-vf2-12a-pac/src/qspi/sram_partition.rs | 12 +- .../src/qspi/wr_completion_ctrl.rs | 12 +- jh7110-vf2-12a-pac/src/qspi/wr_instr.rs | 24 +- jh7110-vf2-12a-pac/src/spi0.rs | 180 +- jh7110-vf2-12a-pac/src/spi0/ssp_cpsr.rs | 12 +- jh7110-vf2-12a-pac/src/spi0/ssp_cr0.rs | 36 +- jh7110-vf2-12a-pac/src/spi0/ssp_cr1.rs | 30 +- jh7110-vf2-12a-pac/src/spi0/ssp_dmacr.rs | 18 +- jh7110-vf2-12a-pac/src/spi0/ssp_dr.rs | 12 +- jh7110-vf2-12a-pac/src/spi0/ssp_icr.rs | 18 +- jh7110-vf2-12a-pac/src/spi0/ssp_imsc.rs | 30 +- jh7110-vf2-12a-pac/src/spi0/ssp_mis.rs | 6 +- jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id0.rs | 6 +- jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id1.rs | 6 +- jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id2.rs | 6 +- jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id3.rs | 6 +- jh7110-vf2-12a-pac/src/spi0/ssp_periph_id0.rs | 6 +- jh7110-vf2-12a-pac/src/spi0/ssp_periph_id1.rs | 6 +- jh7110-vf2-12a-pac/src/spi0/ssp_periph_id2.rs | 6 +- jh7110-vf2-12a-pac/src/spi0/ssp_periph_id3.rs | 6 +- jh7110-vf2-12a-pac/src/spi0/ssp_ris.rs | 6 +- jh7110-vf2-12a-pac/src/spi0/ssp_sr.rs | 6 +- jh7110-vf2-12a-pac/src/spi1.rs | 180 +- jh7110-vf2-12a-pac/src/spi1/ssp_cpsr.rs | 12 +- jh7110-vf2-12a-pac/src/spi1/ssp_cr0.rs | 36 +- jh7110-vf2-12a-pac/src/spi1/ssp_cr1.rs | 30 +- jh7110-vf2-12a-pac/src/spi1/ssp_dmacr.rs | 18 +- jh7110-vf2-12a-pac/src/spi1/ssp_dr.rs | 12 +- jh7110-vf2-12a-pac/src/spi1/ssp_icr.rs | 18 +- jh7110-vf2-12a-pac/src/spi1/ssp_imsc.rs | 30 +- jh7110-vf2-12a-pac/src/spi1/ssp_mis.rs | 6 +- jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id0.rs | 6 +- jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id1.rs | 6 +- jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id2.rs | 6 +- jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id3.rs | 6 +- jh7110-vf2-12a-pac/src/spi1/ssp_periph_id0.rs | 6 +- jh7110-vf2-12a-pac/src/spi1/ssp_periph_id1.rs | 6 +- jh7110-vf2-12a-pac/src/spi1/ssp_periph_id2.rs | 6 +- jh7110-vf2-12a-pac/src/spi1/ssp_periph_id3.rs | 6 +- jh7110-vf2-12a-pac/src/spi1/ssp_ris.rs | 6 +- jh7110-vf2-12a-pac/src/spi1/ssp_sr.rs | 6 +- jh7110-vf2-12a-pac/src/spi2.rs | 180 +- jh7110-vf2-12a-pac/src/spi2/ssp_cpsr.rs | 12 +- jh7110-vf2-12a-pac/src/spi2/ssp_cr0.rs | 36 +- jh7110-vf2-12a-pac/src/spi2/ssp_cr1.rs | 30 +- jh7110-vf2-12a-pac/src/spi2/ssp_dmacr.rs | 18 +- jh7110-vf2-12a-pac/src/spi2/ssp_dr.rs | 12 +- jh7110-vf2-12a-pac/src/spi2/ssp_icr.rs | 18 +- jh7110-vf2-12a-pac/src/spi2/ssp_imsc.rs | 30 +- jh7110-vf2-12a-pac/src/spi2/ssp_mis.rs | 6 +- jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id0.rs | 6 +- jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id1.rs | 6 +- jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id2.rs | 6 +- jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id3.rs | 6 +- jh7110-vf2-12a-pac/src/spi2/ssp_periph_id0.rs | 6 +- jh7110-vf2-12a-pac/src/spi2/ssp_periph_id1.rs | 6 +- jh7110-vf2-12a-pac/src/spi2/ssp_periph_id2.rs | 6 +- jh7110-vf2-12a-pac/src/spi2/ssp_periph_id3.rs | 6 +- jh7110-vf2-12a-pac/src/spi2/ssp_ris.rs | 6 +- jh7110-vf2-12a-pac/src/spi2/ssp_sr.rs | 6 +- jh7110-vf2-12a-pac/src/spi3.rs | 180 +- jh7110-vf2-12a-pac/src/spi3/ssp_cpsr.rs | 12 +- jh7110-vf2-12a-pac/src/spi3/ssp_cr0.rs | 36 +- jh7110-vf2-12a-pac/src/spi3/ssp_cr1.rs | 30 +- jh7110-vf2-12a-pac/src/spi3/ssp_dmacr.rs | 18 +- jh7110-vf2-12a-pac/src/spi3/ssp_dr.rs | 12 +- jh7110-vf2-12a-pac/src/spi3/ssp_icr.rs | 18 +- jh7110-vf2-12a-pac/src/spi3/ssp_imsc.rs | 30 +- jh7110-vf2-12a-pac/src/spi3/ssp_mis.rs | 6 +- jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id0.rs | 6 +- jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id1.rs | 6 +- jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id2.rs | 6 +- jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id3.rs | 6 +- jh7110-vf2-12a-pac/src/spi3/ssp_periph_id0.rs | 6 +- jh7110-vf2-12a-pac/src/spi3/ssp_periph_id1.rs | 6 +- jh7110-vf2-12a-pac/src/spi3/ssp_periph_id2.rs | 6 +- jh7110-vf2-12a-pac/src/spi3/ssp_periph_id3.rs | 6 +- jh7110-vf2-12a-pac/src/spi3/ssp_ris.rs | 6 +- jh7110-vf2-12a-pac/src/spi3/ssp_sr.rs | 6 +- jh7110-vf2-12a-pac/src/spi4.rs | 180 +- jh7110-vf2-12a-pac/src/spi4/ssp_cpsr.rs | 12 +- jh7110-vf2-12a-pac/src/spi4/ssp_cr0.rs | 36 +- jh7110-vf2-12a-pac/src/spi4/ssp_cr1.rs | 30 +- jh7110-vf2-12a-pac/src/spi4/ssp_dmacr.rs | 18 +- jh7110-vf2-12a-pac/src/spi4/ssp_dr.rs | 12 +- jh7110-vf2-12a-pac/src/spi4/ssp_icr.rs | 18 +- jh7110-vf2-12a-pac/src/spi4/ssp_imsc.rs | 30 +- jh7110-vf2-12a-pac/src/spi4/ssp_mis.rs | 6 +- jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id0.rs | 6 +- jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id1.rs | 6 +- jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id2.rs | 6 +- jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id3.rs | 6 +- jh7110-vf2-12a-pac/src/spi4/ssp_periph_id0.rs | 6 +- jh7110-vf2-12a-pac/src/spi4/ssp_periph_id1.rs | 6 +- jh7110-vf2-12a-pac/src/spi4/ssp_periph_id2.rs | 6 +- jh7110-vf2-12a-pac/src/spi4/ssp_periph_id3.rs | 6 +- jh7110-vf2-12a-pac/src/spi4/ssp_ris.rs | 6 +- jh7110-vf2-12a-pac/src/spi4/ssp_sr.rs | 6 +- jh7110-vf2-12a-pac/src/spi5.rs | 180 +- jh7110-vf2-12a-pac/src/spi5/ssp_cpsr.rs | 12 +- jh7110-vf2-12a-pac/src/spi5/ssp_cr0.rs | 36 +- jh7110-vf2-12a-pac/src/spi5/ssp_cr1.rs | 30 +- jh7110-vf2-12a-pac/src/spi5/ssp_dmacr.rs | 18 +- jh7110-vf2-12a-pac/src/spi5/ssp_dr.rs | 12 +- jh7110-vf2-12a-pac/src/spi5/ssp_icr.rs | 18 +- jh7110-vf2-12a-pac/src/spi5/ssp_imsc.rs | 30 +- jh7110-vf2-12a-pac/src/spi5/ssp_mis.rs | 6 +- jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id0.rs | 6 +- jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id1.rs | 6 +- jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id2.rs | 6 +- jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id3.rs | 6 +- jh7110-vf2-12a-pac/src/spi5/ssp_periph_id0.rs | 6 +- jh7110-vf2-12a-pac/src/spi5/ssp_periph_id1.rs | 6 +- jh7110-vf2-12a-pac/src/spi5/ssp_periph_id2.rs | 6 +- jh7110-vf2-12a-pac/src/spi5/ssp_periph_id3.rs | 6 +- jh7110-vf2-12a-pac/src/spi5/ssp_ris.rs | 6 +- jh7110-vf2-12a-pac/src/spi5/ssp_sr.rs | 6 +- jh7110-vf2-12a-pac/src/spi6.rs | 180 +- jh7110-vf2-12a-pac/src/spi6/ssp_cpsr.rs | 12 +- jh7110-vf2-12a-pac/src/spi6/ssp_cr0.rs | 36 +- jh7110-vf2-12a-pac/src/spi6/ssp_cr1.rs | 30 +- jh7110-vf2-12a-pac/src/spi6/ssp_dmacr.rs | 18 +- jh7110-vf2-12a-pac/src/spi6/ssp_dr.rs | 12 +- jh7110-vf2-12a-pac/src/spi6/ssp_icr.rs | 18 +- jh7110-vf2-12a-pac/src/spi6/ssp_imsc.rs | 30 +- jh7110-vf2-12a-pac/src/spi6/ssp_mis.rs | 6 +- jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id0.rs | 6 +- jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id1.rs | 6 +- jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id2.rs | 6 +- jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id3.rs | 6 +- jh7110-vf2-12a-pac/src/spi6/ssp_periph_id0.rs | 6 +- jh7110-vf2-12a-pac/src/spi6/ssp_periph_id1.rs | 6 +- jh7110-vf2-12a-pac/src/spi6/ssp_periph_id2.rs | 6 +- jh7110-vf2-12a-pac/src/spi6/ssp_periph_id3.rs | 6 +- jh7110-vf2-12a-pac/src/spi6/ssp_ris.rs | 6 +- jh7110-vf2-12a-pac/src/spi6/ssp_sr.rs | 6 +- jh7110-vf2-12a-pac/src/stg_syscon.rs | 1868 ++++++++++++----- .../src/stg_syscon/stg_sysconsaif_syscfg0.rs | 76 +- .../stg_syscon/stg_sysconsaif_syscfg100.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg104.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg108.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg112.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg116.rs | 6 +- .../src/stg_syscon/stg_sysconsaif_syscfg12.rs | 73 +- .../stg_syscon/stg_sysconsaif_syscfg120.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg124.rs | 12 +- .../stg_syscon/stg_sysconsaif_syscfg128.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg132.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg136.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg140.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg144.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg148.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg152.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg156.rs | 13 +- .../src/stg_syscon/stg_sysconsaif_syscfg16.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg160.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg164.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg168.rs | 27 +- .../stg_syscon/stg_sysconsaif_syscfg172.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg176.rs | 27 +- .../stg_syscon/stg_sysconsaif_syscfg180.rs | 13 +- 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++- jh7110-vf2-12a-pac/src/stgcrg/clk_dma_ahb.rs | 12 +- jh7110-vf2-12a-pac/src/stgcrg/clk_dma_axi.rs | 12 +- jh7110-vf2-12a-pac/src/stgcrg/clk_e2_core.rs | 12 +- jh7110-vf2-12a-pac/src/stgcrg/clk_e2_dbg.rs | 12 +- jh7110-vf2-12a-pac/src/stgcrg/clk_e2_rtc.rs | 18 +- .../src/stgcrg/clk_hifi4_core.rs | 12 +- .../src/stgcrg/clk_pcie01_slv_dec_main.rs | 12 +- jh7110-vf2-12a-pac/src/stgcrg/clk_sec_hclk.rs | 12 +- .../src/stgcrg/clk_sec_misc_ahb.rs | 12 +- .../src/stgcrg/clk_stg_mtrx_group0_bus.rs | 12 +- .../src/stgcrg/clk_stg_mtrx_group0_main.rs | 12 +- .../src/stgcrg/clk_stg_mtrx_group0_stg.rs | 12 +- .../src/stgcrg/clk_stg_mtrx_group1_bus.rs | 12 +- .../src/stgcrg/clk_stg_mtrx_group1_hifi.rs | 12 +- .../src/stgcrg/clk_stg_mtrx_group1_main.rs | 12 +- .../src/stgcrg/clk_stg_mtrx_group1_stg.rs | 12 +- .../src/stgcrg/clk_u0_pcie_apb.rs | 12 +- .../src/stgcrg/clk_u0_pcie_axi_mst0.rs | 12 +- .../src/stgcrg/clk_u0_pcie_tl.rs | 12 +- .../src/stgcrg/clk_u1_pcie_apb.rs | 12 +- .../src/stgcrg/clk_u1_pcie_axi_mst0.rs | 12 +- .../src/stgcrg/clk_u1_pcie_tl.rs | 12 +- jh7110-vf2-12a-pac/src/stgcrg/clk_usb_apb.rs | 12 +- .../src/stgcrg/clk_usb_app125.rs | 12 +- jh7110-vf2-12a-pac/src/stgcrg/clk_usb_axi.rs | 12 +- jh7110-vf2-12a-pac/src/stgcrg/clk_usb_ipm.rs | 18 +- .../src/stgcrg/clk_usb_refclk.rs | 12 +- jh7110-vf2-12a-pac/src/stgcrg/clk_usb_stb.rs | 18 +- .../src/stgcrg/clk_usb_utmi_apb.rs | 12 +- .../src/stgcrg/soft_rst_addr_sel.rs | 146 +- .../src/stgcrg/stgcrg_rst_stat.rs | 150 +- jh7110-vf2-12a-pac/src/sys_pinctrl.rs | 1398 ++++++++---- .../src/sys_pinctrl/func_sel0.rs | 74 +- .../src/sys_pinctrl/func_sel1.rs | 68 +- .../src/sys_pinctrl/func_sel2.rs | 74 +- .../src/sys_pinctrl/func_sel3.rs | 74 +- .../src/sys_pinctrl/func_sel4.rs | 74 +- .../src/sys_pinctrl/func_sel5.rs | 81 +- .../src/sys_pinctrl/func_sel6.rs | 65 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi0.rs | 31 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi12.rs | 30 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi16.rs | 32 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi20.rs | 33 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi24.rs | 32 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi28.rs | 32 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi32.rs | 36 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi36.rs | 30 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi4.rs | 34 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi40.rs | 30 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi44.rs | 30 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi48.rs | 30 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi52.rs | 30 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi56.rs | 30 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi60.rs | 30 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi64.rs | 30 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi68.rs | 30 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi72.rs | 30 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi76.rs | 30 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi8.rs | 31 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi80.rs | 30 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi84.rs | 30 +- jh7110-vf2-12a-pac/src/sys_pinctrl/gpi88.rs | 24 +- .../src/sys_pinctrl/gpo_doen0.rs | 30 +- .../src/sys_pinctrl/gpo_doen1.rs | 30 +- .../src/sys_pinctrl/gpo_doen10.rs | 30 +- .../src/sys_pinctrl/gpo_doen11.rs | 30 +- .../src/sys_pinctrl/gpo_doen12.rs | 30 +- .../src/sys_pinctrl/gpo_doen13.rs | 30 +- .../src/sys_pinctrl/gpo_doen14.rs | 30 +- .../src/sys_pinctrl/gpo_doen15.rs | 30 +- .../src/sys_pinctrl/gpo_doen2.rs | 30 +- .../src/sys_pinctrl/gpo_doen3.rs | 30 +- .../src/sys_pinctrl/gpo_doen4.rs | 30 +- .../src/sys_pinctrl/gpo_doen5.rs | 30 +- .../src/sys_pinctrl/gpo_doen6.rs | 30 +- .../src/sys_pinctrl/gpo_doen7.rs | 30 +- .../src/sys_pinctrl/gpo_doen8.rs | 30 +- .../src/sys_pinctrl/gpo_doen9.rs | 30 +- .../src/sys_pinctrl/gpo_dout0_3.rs | 30 +- .../src/sys_pinctrl/gpo_dout12_15.rs | 30 +- .../src/sys_pinctrl/gpo_dout16_19.rs | 30 +- .../src/sys_pinctrl/gpo_dout20_23.rs | 30 +- .../src/sys_pinctrl/gpo_dout24_27.rs | 30 +- .../src/sys_pinctrl/gpo_dout28_31.rs | 30 +- .../src/sys_pinctrl/gpo_dout32_35.rs | 30 +- .../src/sys_pinctrl/gpo_dout36_39.rs | 30 +- .../src/sys_pinctrl/gpo_dout40_43.rs | 30 +- .../src/sys_pinctrl/gpo_dout44_47.rs | 30 +- .../src/sys_pinctrl/gpo_dout48_51.rs | 30 +- .../src/sys_pinctrl/gpo_dout4_7.rs | 30 +- .../src/sys_pinctrl/gpo_dout52_55.rs | 30 +- .../src/sys_pinctrl/gpo_dout56_59.rs | 30 +- .../src/sys_pinctrl/gpo_dout60_63.rs | 30 +- .../src/sys_pinctrl/gpo_dout8_11.rs | 30 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq0.rs | 12 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq1.rs | 12 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq10.rs | 12 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq11.rs | 6 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq12.rs | 6 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq13.rs | 6 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq14.rs | 6 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq15.rs | 6 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq16.rs | 6 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq2.rs | 12 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq3.rs | 12 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq4.rs | 12 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq5.rs | 12 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq6.rs | 12 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq7.rs | 12 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq8.rs | 12 +- jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq9.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_mdc_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_mdio_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_rxc_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_rxd0_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_rxd1_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_rxd2_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_rxd3_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_rxdv_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_txc_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_txd0_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_txd1_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_txd2_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_txd3_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_txen_syscon.rs | 12 +- .../src/sys_pinctrl/padcfg_gpio0.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio1.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio10.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio11.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio12.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio13.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio14.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio15.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio16.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio17.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio18.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio19.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio2.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio20.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio21.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio22.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio23.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio24.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio25.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio26.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio27.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio28.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio29.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio3.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio30.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio31.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio32.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio33.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio34.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio35.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio36.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio37.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio38.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio39.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio4.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio40.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio41.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio42.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio43.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio44.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio45.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio46.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio47.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio48.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio49.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio5.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio50.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio51.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio52.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio53.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio54.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio55.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio56.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio57.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio58.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio59.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio6.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio60.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio61.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio62.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio63.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio7.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio8.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio9.rs | 48 +- .../src/sys_pinctrl/padcfg_qspi_csn0.rs | 48 +- .../src/sys_pinctrl/padcfg_qspi_data0.rs | 48 +- .../src/sys_pinctrl/padcfg_qspi_data1.rs | 48 +- .../src/sys_pinctrl/padcfg_qspi_data2.rs | 48 +- .../src/sys_pinctrl/padcfg_qspi_data3.rs | 48 +- .../src/sys_pinctrl/padcfg_qspi_sclk.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_clk.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_cmd.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_data0.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_data1.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_data2.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_data3.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_data4.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_data5.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_data6.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_data7.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_strb.rs | 48 +- jh7110-vf2-12a-pac/src/sys_syscon.rs | 316 ++- .../src/sys_syscon/sys_sysconsaif_syscfg0.rs | 58 +- .../sys_syscon/sys_sysconsaif_syscfg100.rs | 32 +- .../sys_syscon/sys_sysconsaif_syscfg104.rs | 13 +- .../sys_syscon/sys_sysconsaif_syscfg108.rs | 13 +- .../sys_syscon/sys_sysconsaif_syscfg112.rs | 13 +- .../sys_syscon/sys_sysconsaif_syscfg116.rs | 13 +- .../src/sys_syscon/sys_sysconsaif_syscfg12.rs | 30 +- .../sys_syscon/sys_sysconsaif_syscfg120.rs | 13 +- .../sys_syscon/sys_sysconsaif_syscfg124.rs | 13 +- .../sys_syscon/sys_sysconsaif_syscfg128.rs | 13 +- .../sys_syscon/sys_sysconsaif_syscfg136.rs | 90 +- .../sys_syscon/sys_sysconsaif_syscfg140.rs | 61 +- .../sys_syscon/sys_sysconsaif_syscfg144.rs | 12 +- .../sys_syscon/sys_sysconsaif_syscfg148.rs | 6 +- .../sys_syscon/sys_sysconsaif_syscfg152.rs | 6 +- .../sys_syscon/sys_sysconsaif_syscfg156.rs | 40 +- .../src/sys_syscon/sys_sysconsaif_syscfg16.rs | 18 +- .../src/sys_syscon/sys_sysconsaif_syscfg20.rs | 128 +- .../src/sys_syscon/sys_sysconsaif_syscfg24.rs | 123 +- .../src/sys_syscon/sys_sysconsaif_syscfg28.rs | 12 +- .../src/sys_syscon/sys_sysconsaif_syscfg32.rs | 38 +- .../src/sys_syscon/sys_sysconsaif_syscfg36.rs | 56 +- .../src/sys_syscon/sys_sysconsaif_syscfg4.rs | 58 +- .../src/sys_syscon/sys_sysconsaif_syscfg40.rs | 38 +- .../src/sys_syscon/sys_sysconsaif_syscfg44.rs | 56 +- .../src/sys_syscon/sys_sysconsaif_syscfg48.rs | 38 +- .../src/sys_syscon/sys_sysconsaif_syscfg52.rs | 94 +- .../src/sys_syscon/sys_sysconsaif_syscfg56.rs | 57 +- .../src/sys_syscon/sys_sysconsaif_syscfg60.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg64.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg68.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg72.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg76.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg8.rs | 24 +- .../src/sys_syscon/sys_sysconsaif_syscfg80.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg84.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg88.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg92.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg96.rs | 42 +- jh7110-vf2-12a-pac/src/syscrg.rs | 1599 ++++++++++---- jh7110-vf2-12a-pac/src/syscrg/clk_ahb0.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_ahb1.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_apb0.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_apb_bus.rs | 12 +- .../src/syscrg/clk_audio_root.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0.rs | 12 +- .../src/syscrg/clk_axi_cfg0_dec_hifi4.rs | 12 +- .../src/syscrg/clk_axi_cfg0_dec_main.rs | 12 +- .../src/syscrg/clk_axi_cfg0_dec_main_div.rs | 12 +- .../src/syscrg/clk_aximem_128b_axi.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_bus_root.rs | 12 +- .../src/syscrg/clk_codaj12_apb.rs | 12 +- .../src/syscrg/clk_codaj12_axi.rs | 12 +- .../src/syscrg/clk_codaj12_core.rs | 18 +- jh7110-vf2-12a-pac/src/syscrg/clk_cpu_bus.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_cpu_core.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_cpu_root.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_ddr_bus.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_gclk0.rs | 18 +- jh7110-vf2-12a-pac/src/syscrg/clk_gclk1.rs | 18 +- jh7110-vf2-12a-pac/src/syscrg/clk_gclk2.rs | 18 +- .../src/syscrg/clk_gmac0_gtx.rs | 18 +- .../src/syscrg/clk_gmac0_gtxclk.rs | 12 +- .../src/syscrg/clk_gmac0_ptp.rs | 18 +- .../src/syscrg/clk_gmac1_gtx.rs | 12 +- .../src/syscrg/clk_gmac1_gtxclk.rs | 12 +- .../src/syscrg/clk_gmac1_rmii_rtx.rs | 12 +- .../src/syscrg/clk_gmac5_axi64_ahb.rs | 12 +- .../src/syscrg/clk_gmac5_axi64_axi.rs | 12 +- .../src/syscrg/clk_gmac5_axi64_ptp.rs | 18 +- .../src/syscrg/clk_gmac5_axi64_rx.rs | 12 +- .../src/syscrg/clk_gmac5_axi64_rxi.rs | 12 +- .../src/syscrg/clk_gmac5_axi64_tx.rs | 18 +- .../src/syscrg/clk_gmac5_axi64_txi.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_gmac_phy.rs | 18 +- jh7110-vf2-12a-pac/src/syscrg/clk_gmac_src.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_gpu_core.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_gpu_root.rs | 12 +- .../src/syscrg/clk_hifi4_axi.rs | 12 +- .../src/syscrg/clk_hifi4_core.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_i2s_apb.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk.rs | 12 +- .../src/syscrg/clk_i2s_bclk_mst.rs | 18 +- .../src/syscrg/clk_i2s_bclk_mst_inv.rs | 12 +- .../src/syscrg/clk_i2s_bclk_neg.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_i2s_lrck.rs | 12 +- .../src/syscrg/clk_i2s_lrck_mst.rs | 18 +- .../src/syscrg/clk_i2stx0_lrck_mst.rs | 18 +- .../src/syscrg/clk_i2stx1_lrck_mst.rs | 18 +- .../src/syscrg/clk_internal_ctrl_apb.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_isp_2x.rs | 18 +- jh7110-vf2-12a-pac/src/syscrg/clk_isp_axi.rs | 12 +- .../src/syscrg/clk_jpeg_codec_axi.rs | 12 +- .../src/syscrg/clk_jtag_cert_trng.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_mbox_apb.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_mclk.rs | 12 +- .../src/syscrg/clk_mclk_inner.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_mclk_out.rs | 12 +- .../src/syscrg/clk_noc_display_axi.rs | 12 +- .../src/syscrg/clk_noc_stg_axi.rs | 12 +- .../src/syscrg/clk_noc_vdec_axi.rs | 12 +- .../src/syscrg/clk_noc_venc_axi.rs | 12 +- .../src/syscrg/clk_nocstg_bus.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_osc_div2.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_pdm_apb.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_pdm_dmic.rs | 18 +- .../src/syscrg/clk_peripheral_root.rs | 18 +- .../src/syscrg/clk_pll0_div2.rs | 12 +- .../src/syscrg/clk_pll1_div2.rs | 12 +- .../src/syscrg/clk_pll1_div4.rs | 12 +- .../src/syscrg/clk_pll1_div8.rs | 12 +- .../src/syscrg/clk_pll2_div2.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_pwm_apb.rs | 12 +- .../src/syscrg/clk_pwmdac_apb.rs | 12 +- .../src/syscrg/clk_pwmdac_core.rs | 18 +- jh7110-vf2-12a-pac/src/syscrg/clk_qspi_ahb.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_qspi_apb.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_qspi_ref.rs | 18 +- .../src/syscrg/clk_qspi_ref_src.rs | 12 +- .../src/syscrg/clk_spdif_apb.rs | 12 +- .../src/syscrg/clk_spdif_core.rs | 12 +- .../src/syscrg/clk_stg_axiahb.rs | 12 +- .../src/syscrg/clk_sys_iomux_pclk.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_tdm.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_tdm_ahb.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_tdm_apb.rs | 12 +- .../src/syscrg/clk_tdm_internal.rs | 18 +- jh7110-vf2-12a-pac/src/syscrg/clk_tdm_neg.rs | 12 +- .../src/syscrg/clk_temp_sensor.rs | 18 +- .../src/syscrg/clk_temp_sensor_apb.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_tim0.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_tim1.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_tim2.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_tim3.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_tim_apb.rs | 12 +- .../src/syscrg/clk_u0_axi_cfg1_dec_clk_ahb.rs | 12 +- .../syscrg/clk_u0_axi_cfg1_dec_clk_main.rs | 12 +- .../src/syscrg/clk_u0_can_ctrl_apb.rs | 12 +- .../src/syscrg/clk_u0_can_ctrl_can.rs | 18 +- .../src/syscrg/clk_u0_can_ctrl_tim.rs | 18 +- .../src/syscrg/clk_u0_ddr_sft7110_clk_axi.rs | 12 +- ...dom_isp_top_clk_dom_isp_top_clk_isp_axi.rs | 14 +- ..._isp_top_clk_dom_isp_top_clk_ispcore_2x.rs | 14 +- ..._vout_top_clk_dom_vout_top_clk_vout_src.rs | 14 +- .../src/syscrg/clk_u0_gpu_rtc_toggle.rs | 18 +- .../src/syscrg/clk_u0_i2c_apb.rs | 12 +- .../src/syscrg/clk_u0_i2s_tx_apb.rs | 12 +- .../src/syscrg/clk_u0_i2stx_4ch0_bclk_mst.rs | 18 +- .../syscrg/clk_u0_i2stx_4ch0_bclk_mst_inv.rs | 12 +- .../src/syscrg/clk_u0_i2stx_bclk.rs | 12 +- .../src/syscrg/clk_u0_i2stx_bclk_neg.rs | 12 +- .../src/syscrg/clk_u0_i2stx_lrck.rs | 12 +- .../src/syscrg/clk_u0_img_gpu_clk_apb.rs | 12 +- .../src/syscrg/clk_u0_img_gpu_core_clk.rs | 12 +- .../src/syscrg/clk_u0_img_gpu_sys_clk.rs | 12 +- .../src/syscrg/clk_u0_sd_ahb.rs | 12 +- .../src/syscrg/clk_u0_sd_card.rs | 18 +- .../clk_u0_sft7110_noc_bus_clk_axicfg0_axi.rs | 12 +- .../clk_u0_sft7110_noc_bus_clk_cpu_axi.rs | 12 +- .../clk_u0_sft7110_noc_bus_clk_gpu_axi.rs | 12 +- .../clk_u0_sft7110_noc_bux_clk_isp_axi.rs | 12 +- .../src/syscrg/clk_u0_spi_apb.rs | 12 +- .../src/syscrg/clk_u0_uart_apb.rs | 12 +- .../src/syscrg/clk_u0_uart_core.rs | 12 +- .../src/syscrg/clk_u1_can_ctrl_apb.rs | 12 +- .../src/syscrg/clk_u1_can_ctrl_can.rs | 18 +- .../src/syscrg/clk_u1_can_ctrl_tim.rs | 18 +- .../src/syscrg/clk_u1_i2c_apb.rs | 12 +- .../src/syscrg/clk_u1_i2s_tx_apb.rs | 12 +- .../src/syscrg/clk_u1_i2stx_4ch1_bclk_mst.rs | 18 +- .../syscrg/clk_u1_i2stx_4ch1_bclk_mst_inv.rs | 12 +- .../src/syscrg/clk_u1_i2stx_bclk.rs | 12 +- .../src/syscrg/clk_u1_i2stx_bclk_neg.rs | 12 +- .../src/syscrg/clk_u1_i2stx_lrck.rs | 12 +- .../src/syscrg/clk_u1_sd_ahb.rs | 12 +- .../src/syscrg/clk_u1_sd_card.rs | 18 +- .../src/syscrg/clk_u1_spi_apb.rs | 12 +- .../src/syscrg/clk_u1_uart_apb.rs | 12 +- .../src/syscrg/clk_u1_uart_core.rs | 12 +- .../src/syscrg/clk_u2_i2c_apb.rs | 12 +- .../src/syscrg/clk_u2_spi_apb.rs | 12 +- .../src/syscrg/clk_u2_uart_apb.rs | 12 +- .../src/syscrg/clk_u2_uart_core.rs | 12 +- .../src/syscrg/clk_u3_i2c_apb.rs | 12 +- .../src/syscrg/clk_u3_spi_apb.rs | 12 +- .../src/syscrg/clk_u3_uart_apb.rs | 12 +- .../src/syscrg/clk_u3_uart_core.rs | 18 +- .../src/syscrg/clk_u4_i2c_apb.rs | 12 +- .../src/syscrg/clk_u4_spi_apb.rs | 12 +- .../src/syscrg/clk_u4_uart_apb.rs | 12 +- .../src/syscrg/clk_u4_uart_core.rs | 18 +- .../src/syscrg/clk_u5_i2c_apb.rs | 12 +- .../src/syscrg/clk_u5_spi_apb.rs | 12 +- .../src/syscrg/clk_u5_uart_apb.rs | 12 +- .../src/syscrg/clk_u5_uart_core.rs | 18 +- .../src/syscrg/clk_u6_i2c_apb.rs | 12 +- .../src/syscrg/clk_u6_spi_apb.rs | 12 +- .../src/syscrg/clk_u7mc_core0.rs | 12 +- .../src/syscrg/clk_u7mc_core1.rs | 12 +- .../src/syscrg/clk_u7mc_core2.rs | 12 +- .../src/syscrg/clk_u7mc_core3.rs | 12 +- .../src/syscrg/clk_u7mc_core4.rs | 12 +- .../src/syscrg/clk_u7mc_debug.rs | 12 +- .../src/syscrg/clk_u7mc_trace0.rs | 12 +- .../src/syscrg/clk_u7mc_trace1.rs | 12 +- .../src/syscrg/clk_u7mc_trace2.rs | 12 +- .../src/syscrg/clk_u7mc_trace3.rs | 12 +- .../src/syscrg/clk_u7mc_trace4.rs | 12 +- .../src/syscrg/clk_u7mc_trace_com.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_usb_125m.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_vdec_axi.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_venc_axi.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_vout_ahb.rs | 12 +- .../src/syscrg/clk_vout_axi_divcfg.rs | 12 +- .../src/syscrg/clk_vout_axi_icg.rs | 12 +- .../src/syscrg/clk_vout_hdmi_tx0_mclk.rs | 12 +- .../src/syscrg/clk_vout_mipi_phy.rs | 12 +- .../src/syscrg/clk_wave420l_apb.rs | 12 +- .../src/syscrg/clk_wave420l_axi.rs | 12 +- .../src/syscrg/clk_wave420l_bpu.rs | 18 +- .../src/syscrg/clk_wave420l_vce.rs | 18 +- .../src/syscrg/clk_wave511_apb.rs | 12 +- .../src/syscrg/clk_wave511_axi.rs | 12 +- .../src/syscrg/clk_wave511_bpu.rs | 18 +- .../src/syscrg/clk_wave511_jpg_arb.rs | 12 +- .../src/syscrg/clk_wave511_jpg_main.rs | 12 +- .../src/syscrg/clk_wave511_vce.rs | 18 +- jh7110-vf2-12a-pac/src/syscrg/clk_wdt.rs | 12 +- jh7110-vf2-12a-pac/src/syscrg/clk_wdt_apb.rs | 12 +- .../src/syscrg/soft_rst0_addr_sel.rs | 207 +- .../src/syscrg/soft_rst1_addr_sel.rs | 203 +- .../src/syscrg/soft_rst2_addr_sel.rs | 224 +- .../src/syscrg/soft_rst3_addr_sel.rs | 188 +- .../src/syscrg/syscrg_rst0_status.rs | 207 +- .../src/syscrg/syscrg_rst1_status.rs | 203 +- .../src/syscrg/syscrg_rst2_status.rs | 224 +- .../src/syscrg/syscrg_rst3_status.rs | 188 +- .../src/syscrg/u7mc_rtc_toggle.rs | 12 +- jh7110-vf2-12a-pac/src/trng.rs | 134 +- jh7110-vf2-12a-pac/src/trng/auto_age.rs | 12 +- jh7110-vf2-12a-pac/src/trng/auto_rqsts.rs | 12 +- jh7110-vf2-12a-pac/src/trng/ctrl.rs | 24 +- jh7110-vf2-12a-pac/src/trng/ie.rs | 30 +- jh7110-vf2-12a-pac/src/trng/istat.rs | 6 +- jh7110-vf2-12a-pac/src/trng/mode.rs | 12 +- jh7110-vf2-12a-pac/src/trng/rand0.rs | 6 +- jh7110-vf2-12a-pac/src/trng/rand1.rs | 6 +- jh7110-vf2-12a-pac/src/trng/rand2.rs | 6 +- jh7110-vf2-12a-pac/src/trng/rand3.rs | 6 +- jh7110-vf2-12a-pac/src/trng/rand4.rs | 6 +- jh7110-vf2-12a-pac/src/trng/rand5.rs | 6 +- jh7110-vf2-12a-pac/src/trng/rand6.rs | 6 +- jh7110-vf2-12a-pac/src/trng/rand7.rs | 6 +- jh7110-vf2-12a-pac/src/trng/smode.rs | 24 +- jh7110-vf2-12a-pac/src/trng/stat.rs | 6 +- jh7110-vf2-12a-pac/src/uart0.rs | 394 ++-- jh7110-vf2-12a-pac/src/uart0/cpr.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/ctr.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/dlh.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/dll.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/dmasa.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/far.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/fcr.rs | 42 +- jh7110-vf2-12a-pac/src/uart0/htx.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/ier.rs | 36 +- jh7110-vf2-12a-pac/src/uart0/iir.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/lcr.rs | 42 +- jh7110-vf2-12a-pac/src/uart0/lpdlh.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/lpdll.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/lsr.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/mcr.rs | 48 +- jh7110-vf2-12a-pac/src/uart0/msr.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/rbr.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/rfl.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/rfw.rs | 24 +- jh7110-vf2-12a-pac/src/uart0/sbcr.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/scr.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sdmam.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sfe.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/srbr0.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/srbr1.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/srbr10.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/srbr11.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/srbr12.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/srbr13.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/srbr14.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/srbr15.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/srbr2.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/srbr3.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/srbr4.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/srbr5.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/srbr6.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/srbr7.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/srbr8.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/srbr9.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/srr.rs | 24 +- jh7110-vf2-12a-pac/src/uart0/srt.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/srts.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/stet.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sthr0.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sthr1.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sthr10.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sthr11.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sthr12.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sthr13.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sthr14.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sthr15.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sthr2.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sthr3.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sthr4.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sthr5.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sthr6.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sthr7.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sthr8.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/sthr9.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/tfl.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/tfr.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/thr.rs | 12 +- jh7110-vf2-12a-pac/src/uart0/ucv.rs | 6 +- jh7110-vf2-12a-pac/src/uart0/usr.rs | 6 +- jh7110-vf2-12a-pac/src/uart1.rs | 394 ++-- jh7110-vf2-12a-pac/src/uart1/cpr.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/ctr.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/dlh.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/dll.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/dmasa.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/far.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/fcr.rs | 42 +- jh7110-vf2-12a-pac/src/uart1/htx.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/ier.rs | 36 +- jh7110-vf2-12a-pac/src/uart1/iir.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/lcr.rs | 42 +- jh7110-vf2-12a-pac/src/uart1/lpdlh.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/lpdll.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/lsr.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/mcr.rs | 48 +- jh7110-vf2-12a-pac/src/uart1/msr.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/rbr.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/rfl.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/rfw.rs | 24 +- jh7110-vf2-12a-pac/src/uart1/sbcr.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/scr.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sdmam.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sfe.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/srbr0.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/srbr1.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/srbr10.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/srbr11.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/srbr12.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/srbr13.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/srbr14.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/srbr15.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/srbr2.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/srbr3.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/srbr4.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/srbr5.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/srbr6.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/srbr7.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/srbr8.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/srbr9.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/srr.rs | 24 +- jh7110-vf2-12a-pac/src/uart1/srt.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/srts.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/stet.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sthr0.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sthr1.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sthr10.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sthr11.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sthr12.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sthr13.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sthr14.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sthr15.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sthr2.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sthr3.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sthr4.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sthr5.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sthr6.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sthr7.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sthr8.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/sthr9.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/tfl.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/tfr.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/thr.rs | 12 +- jh7110-vf2-12a-pac/src/uart1/ucv.rs | 6 +- jh7110-vf2-12a-pac/src/uart1/usr.rs | 6 +- jh7110-vf2-12a-pac/src/uart2.rs | 394 ++-- jh7110-vf2-12a-pac/src/uart2/cpr.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/ctr.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/dlh.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/dll.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/dmasa.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/far.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/fcr.rs | 42 +- jh7110-vf2-12a-pac/src/uart2/htx.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/ier.rs | 36 +- jh7110-vf2-12a-pac/src/uart2/iir.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/lcr.rs | 42 +- jh7110-vf2-12a-pac/src/uart2/lpdlh.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/lpdll.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/lsr.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/mcr.rs | 48 +- jh7110-vf2-12a-pac/src/uart2/msr.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/rbr.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/rfl.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/rfw.rs | 24 +- jh7110-vf2-12a-pac/src/uart2/sbcr.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/scr.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sdmam.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sfe.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/srbr0.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/srbr1.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/srbr10.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/srbr11.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/srbr12.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/srbr13.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/srbr14.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/srbr15.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/srbr2.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/srbr3.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/srbr4.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/srbr5.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/srbr6.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/srbr7.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/srbr8.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/srbr9.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/srr.rs | 24 +- jh7110-vf2-12a-pac/src/uart2/srt.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/srts.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/stet.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sthr0.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sthr1.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sthr10.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sthr11.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sthr12.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sthr13.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sthr14.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sthr15.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sthr2.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sthr3.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sthr4.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sthr5.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sthr6.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sthr7.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sthr8.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/sthr9.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/tfl.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/tfr.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/thr.rs | 12 +- jh7110-vf2-12a-pac/src/uart2/ucv.rs | 6 +- jh7110-vf2-12a-pac/src/uart2/usr.rs | 6 +- jh7110-vf2-12a-pac/src/uart3.rs | 394 ++-- jh7110-vf2-12a-pac/src/uart3/cpr.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/ctr.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/dlh.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/dll.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/dmasa.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/far.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/fcr.rs | 42 +- jh7110-vf2-12a-pac/src/uart3/htx.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/ier.rs | 36 +- jh7110-vf2-12a-pac/src/uart3/iir.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/lcr.rs | 42 +- jh7110-vf2-12a-pac/src/uart3/lpdlh.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/lpdll.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/lsr.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/mcr.rs | 48 +- jh7110-vf2-12a-pac/src/uart3/msr.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/rbr.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/rfl.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/rfw.rs | 24 +- jh7110-vf2-12a-pac/src/uart3/sbcr.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/scr.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sdmam.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sfe.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/srbr0.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/srbr1.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/srbr10.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/srbr11.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/srbr12.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/srbr13.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/srbr14.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/srbr15.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/srbr2.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/srbr3.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/srbr4.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/srbr5.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/srbr6.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/srbr7.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/srbr8.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/srbr9.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/srr.rs | 24 +- jh7110-vf2-12a-pac/src/uart3/srt.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/srts.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/stet.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sthr0.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sthr1.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sthr10.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sthr11.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sthr12.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sthr13.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sthr14.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sthr15.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sthr2.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sthr3.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sthr4.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sthr5.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sthr6.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sthr7.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sthr8.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/sthr9.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/tfl.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/tfr.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/thr.rs | 12 +- jh7110-vf2-12a-pac/src/uart3/ucv.rs | 6 +- jh7110-vf2-12a-pac/src/uart3/usr.rs | 6 +- jh7110-vf2-12a-pac/src/uart4.rs | 394 ++-- jh7110-vf2-12a-pac/src/uart4/cpr.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/ctr.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/dlh.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/dll.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/dmasa.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/far.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/fcr.rs | 42 +- jh7110-vf2-12a-pac/src/uart4/htx.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/ier.rs | 36 +- jh7110-vf2-12a-pac/src/uart4/iir.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/lcr.rs | 42 +- jh7110-vf2-12a-pac/src/uart4/lpdlh.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/lpdll.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/lsr.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/mcr.rs | 48 +- jh7110-vf2-12a-pac/src/uart4/msr.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/rbr.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/rfl.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/rfw.rs | 24 +- jh7110-vf2-12a-pac/src/uart4/sbcr.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/scr.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sdmam.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sfe.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/srbr0.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/srbr1.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/srbr10.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/srbr11.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/srbr12.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/srbr13.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/srbr14.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/srbr15.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/srbr2.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/srbr3.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/srbr4.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/srbr5.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/srbr6.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/srbr7.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/srbr8.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/srbr9.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/srr.rs | 24 +- jh7110-vf2-12a-pac/src/uart4/srt.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/srts.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/stet.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sthr0.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sthr1.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sthr10.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sthr11.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sthr12.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sthr13.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sthr14.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sthr15.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sthr2.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sthr3.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sthr4.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sthr5.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sthr6.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sthr7.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sthr8.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/sthr9.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/tfl.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/tfr.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/thr.rs | 12 +- jh7110-vf2-12a-pac/src/uart4/ucv.rs | 6 +- jh7110-vf2-12a-pac/src/uart4/usr.rs | 6 +- jh7110-vf2-12a-pac/src/uart5.rs | 394 ++-- jh7110-vf2-12a-pac/src/uart5/cpr.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/ctr.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/dlh.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/dll.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/dmasa.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/far.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/fcr.rs | 42 +- jh7110-vf2-12a-pac/src/uart5/htx.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/ier.rs | 36 +- jh7110-vf2-12a-pac/src/uart5/iir.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/lcr.rs | 42 +- jh7110-vf2-12a-pac/src/uart5/lpdlh.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/lpdll.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/lsr.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/mcr.rs | 48 +- jh7110-vf2-12a-pac/src/uart5/msr.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/rbr.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/rfl.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/rfw.rs | 24 +- jh7110-vf2-12a-pac/src/uart5/sbcr.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/scr.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sdmam.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sfe.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/srbr0.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/srbr1.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/srbr10.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/srbr11.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/srbr12.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/srbr13.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/srbr14.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/srbr15.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/srbr2.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/srbr3.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/srbr4.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/srbr5.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/srbr6.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/srbr7.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/srbr8.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/srbr9.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/srr.rs | 24 +- jh7110-vf2-12a-pac/src/uart5/srt.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/srts.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/stet.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sthr0.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sthr1.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sthr10.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sthr11.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sthr12.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sthr13.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sthr14.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sthr15.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sthr2.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sthr3.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sthr4.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sthr5.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sthr6.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sthr7.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sthr8.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/sthr9.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/tfl.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/tfr.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/thr.rs | 12 +- jh7110-vf2-12a-pac/src/uart5/ucv.rs | 6 +- jh7110-vf2-12a-pac/src/uart5/usr.rs | 6 +- jh7110-vf2-13b-pac/src/aon_pinctrl.rs | 286 ++- .../aon_iomux_cfgsaif_syscfg100.rs | 12 +- .../aon_iomux_cfgsaif_syscfg104.rs | 12 +- .../aon_iomux_cfgsaif_syscfg108.rs | 12 +- .../aon_iomux_cfgsaif_syscfg112.rs | 12 +- .../aon_iomux_cfgsaif_syscfg116.rs | 12 +- .../aon_iomux_cfgsaif_syscfg120.rs | 12 +- .../aon_iomux_cfgsaif_syscfg124.rs | 12 +- .../aon_iomux_cfgsaif_syscfg128.rs | 12 +- .../aon_iomux_cfgsaif_syscfg132.rs | 12 +- .../aon_iomux_cfgsaif_syscfg136.rs | 12 +- .../aon_iomux_cfgsaif_syscfg140.rs | 12 +- .../aon_iomux_cfgsaif_syscfg144.rs | 12 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs | 12 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs | 48 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs | 48 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs | 48 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs | 48 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs | 18 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs | 12 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs | 12 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs | 12 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs | 12 +- .../aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs | 12 +- .../aon_iomux_cfgsaif_syscfg_fmux0.rs | 30 +- .../aon_iomux_cfgsaif_syscfg_fmux1.rs | 30 +- .../aon_iomux_cfgsaif_syscfg_fmux2.rs | 54 +- .../aon_iomux_cfgsaif_syscfg_fmux3.rs | 14 +- .../aon_iomux_cfgsaif_syscfg_ioirq10.rs | 6 +- .../aon_iomux_cfgsaif_syscfg_ioirq11.rs | 6 +- .../aon_iomux_cfgsaif_syscfg_ioirq4.rs | 14 +- .../aon_iomux_cfgsaif_syscfg_ioirq5.rs | 14 +- .../aon_iomux_cfgsaif_syscfg_ioirq6.rs | 12 +- .../aon_iomux_cfgsaif_syscfg_ioirq7.rs | 12 +- .../aon_iomux_cfgsaif_syscfg_ioirq8.rs | 14 +- .../aon_iomux_cfgsaif_syscfg_ioirq9.rs | 6 +- jh7110-vf2-13b-pac/src/aon_syscon.rs | 90 +- .../src/aon_syscon/aon_sysconsaif_syscfg0.rs | 12 +- .../src/aon_syscon/aon_sysconsaif_syscfg12.rs | 63 +- .../src/aon_syscon/aon_sysconsaif_syscfg16.rs | 6 +- .../src/aon_syscon/aon_sysconsaif_syscfg20.rs | 6 +- .../src/aon_syscon/aon_sysconsaif_syscfg24.rs | 6 +- .../src/aon_syscon/aon_sysconsaif_syscfg28.rs | 6 +- .../src/aon_syscon/aon_sysconsaif_syscfg32.rs | 6 +- .../src/aon_syscon/aon_sysconsaif_syscfg36.rs | 6 +- .../src/aon_syscon/aon_sysconsaif_syscfg4.rs | 6 +- .../src/aon_syscon/aon_sysconsaif_syscfg40.rs | 18 +- .../src/aon_syscon/aon_sysconsaif_syscfg8.rs | 6 +- jh7110-vf2-13b-pac/src/aoncrg.rs | 130 +- .../src/aoncrg/aoncrg_rst_status.rs | 56 +- .../src/aoncrg/clk_ahb_gmac5.rs | 12 +- jh7110-vf2-13b-pac/src/aoncrg/clk_aon_apb.rs | 12 +- .../src/aoncrg/clk_axi_gmac5.rs | 12 +- .../src/aoncrg/clk_gmac0_rmii_rtx.rs | 12 +- .../src/aoncrg/clk_gmac5_axi64_rx.rs | 12 +- .../src/aoncrg/clk_gmac5_axi64_rxi.rs | 12 +- .../src/aoncrg/clk_gmac5_axi64_tx.rs | 12 +- .../src/aoncrg/clk_gmac5_axi64_txi.rs | 12 +- jh7110-vf2-13b-pac/src/aoncrg/clk_optc_apb.rs | 12 +- jh7110-vf2-13b-pac/src/aoncrg/clk_osc.rs | 12 +- .../src/aoncrg/clk_rtc_hms_apb.rs | 12 +- .../src/aoncrg/clk_rtc_hms_cal.rs | 12 +- .../src/aoncrg/clk_rtc_hms_osc32k.rs | 12 +- .../src/aoncrg/clk_rtc_internal.rs | 12 +- .../src/aoncrg/soft_rst_addr_sel.rs | 56 +- jh7110-vf2-13b-pac/src/clint.rs | 94 +- jh7110-vf2-13b-pac/src/clint/msip_0.rs | 8 +- jh7110-vf2-13b-pac/src/clint/msip_1.rs | 8 +- jh7110-vf2-13b-pac/src/clint/msip_2.rs | 8 +- jh7110-vf2-13b-pac/src/clint/msip_3.rs | 8 +- jh7110-vf2-13b-pac/src/clint/msip_4.rs | 8 +- jh7110-vf2-13b-pac/src/clint/mtime.rs | 8 +- jh7110-vf2-13b-pac/src/clint/mtimecmp_0.rs | 8 +- jh7110-vf2-13b-pac/src/clint/mtimecmp_1.rs | 8 +- jh7110-vf2-13b-pac/src/clint/mtimecmp_2.rs | 8 +- jh7110-vf2-13b-pac/src/clint/mtimecmp_3.rs | 8 +- jh7110-vf2-13b-pac/src/clint/mtimecmp_4.rs | 8 +- jh7110-vf2-13b-pac/src/generic.rs | 177 +- jh7110-vf2-13b-pac/src/generic/raw.rs | 20 +- jh7110-vf2-13b-pac/src/i2c0.rs | 306 ++- jh7110-vf2-13b-pac/src/i2c0/clr_activity.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/clr_gen_call.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/clr_intr.rs | 92 +- jh7110-vf2-13b-pac/src/i2c0/clr_rd_req.rs | 12 +- .../src/i2c0/clr_restart_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/clr_rx_done.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/clr_rx_over.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/clr_rx_under.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/clr_start_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/clr_stop_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/clr_tx_abrt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/clr_tx_over.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/comp_param_1.rs | 6 +- jh7110-vf2-13b-pac/src/i2c0/comp_type.rs | 6 +- jh7110-vf2-13b-pac/src/i2c0/comp_version.rs | 6 +- jh7110-vf2-13b-pac/src/i2c0/con.rs | 68 +- jh7110-vf2-13b-pac/src/i2c0/data_cmd.rs | 36 +- jh7110-vf2-13b-pac/src/i2c0/enable.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/enable_status.rs | 36 +- jh7110-vf2-13b-pac/src/i2c0/fs_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/fs_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/hs_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/hs_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/intr_mask.rs | 92 +- jh7110-vf2-13b-pac/src/i2c0/intr_stat.rs | 6 +- jh7110-vf2-13b-pac/src/i2c0/raw_intr_stat.rs | 6 +- jh7110-vf2-13b-pac/src/i2c0/rx_tl.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/rxflr.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/sar.rs | 18 +- jh7110-vf2-13b-pac/src/i2c0/sda_hold.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/ss_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/ss_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/status.rs | 6 +- jh7110-vf2-13b-pac/src/i2c0/tar.rs | 24 +- jh7110-vf2-13b-pac/src/i2c0/tx_abrt_source.rs | 6 +- jh7110-vf2-13b-pac/src/i2c0/tx_tl.rs | 12 +- jh7110-vf2-13b-pac/src/i2c0/txflr.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1.rs | 306 ++- jh7110-vf2-13b-pac/src/i2c1/clr_activity.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/clr_gen_call.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/clr_intr.rs | 92 +- jh7110-vf2-13b-pac/src/i2c1/clr_rd_req.rs | 12 +- .../src/i2c1/clr_restart_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/clr_rx_done.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/clr_rx_over.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/clr_rx_under.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/clr_start_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/clr_stop_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/clr_tx_abrt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/clr_tx_over.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/comp_param_1.rs | 6 +- jh7110-vf2-13b-pac/src/i2c1/comp_type.rs | 6 +- jh7110-vf2-13b-pac/src/i2c1/comp_version.rs | 6 +- jh7110-vf2-13b-pac/src/i2c1/con.rs | 68 +- jh7110-vf2-13b-pac/src/i2c1/data_cmd.rs | 36 +- jh7110-vf2-13b-pac/src/i2c1/enable.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/enable_status.rs | 36 +- jh7110-vf2-13b-pac/src/i2c1/fs_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/fs_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/hs_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/hs_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/intr_mask.rs | 92 +- jh7110-vf2-13b-pac/src/i2c1/intr_stat.rs | 6 +- jh7110-vf2-13b-pac/src/i2c1/raw_intr_stat.rs | 6 +- jh7110-vf2-13b-pac/src/i2c1/rx_tl.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/rxflr.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/sar.rs | 18 +- jh7110-vf2-13b-pac/src/i2c1/sda_hold.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/ss_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/ss_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/status.rs | 6 +- jh7110-vf2-13b-pac/src/i2c1/tar.rs | 24 +- jh7110-vf2-13b-pac/src/i2c1/tx_abrt_source.rs | 6 +- jh7110-vf2-13b-pac/src/i2c1/tx_tl.rs | 12 +- jh7110-vf2-13b-pac/src/i2c1/txflr.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2.rs | 306 ++- jh7110-vf2-13b-pac/src/i2c2/clr_activity.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/clr_gen_call.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/clr_intr.rs | 92 +- jh7110-vf2-13b-pac/src/i2c2/clr_rd_req.rs | 12 +- .../src/i2c2/clr_restart_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/clr_rx_done.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/clr_rx_over.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/clr_rx_under.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/clr_start_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/clr_stop_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/clr_tx_abrt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/clr_tx_over.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/comp_param_1.rs | 6 +- jh7110-vf2-13b-pac/src/i2c2/comp_type.rs | 6 +- jh7110-vf2-13b-pac/src/i2c2/comp_version.rs | 6 +- jh7110-vf2-13b-pac/src/i2c2/con.rs | 68 +- jh7110-vf2-13b-pac/src/i2c2/data_cmd.rs | 36 +- jh7110-vf2-13b-pac/src/i2c2/enable.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/enable_status.rs | 36 +- jh7110-vf2-13b-pac/src/i2c2/fs_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/fs_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/hs_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/hs_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/intr_mask.rs | 92 +- jh7110-vf2-13b-pac/src/i2c2/intr_stat.rs | 6 +- jh7110-vf2-13b-pac/src/i2c2/raw_intr_stat.rs | 6 +- jh7110-vf2-13b-pac/src/i2c2/rx_tl.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/rxflr.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/sar.rs | 18 +- jh7110-vf2-13b-pac/src/i2c2/sda_hold.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/ss_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/ss_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/status.rs | 6 +- jh7110-vf2-13b-pac/src/i2c2/tar.rs | 24 +- jh7110-vf2-13b-pac/src/i2c2/tx_abrt_source.rs | 6 +- jh7110-vf2-13b-pac/src/i2c2/tx_tl.rs | 12 +- jh7110-vf2-13b-pac/src/i2c2/txflr.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3.rs | 306 ++- jh7110-vf2-13b-pac/src/i2c3/clr_activity.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/clr_gen_call.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/clr_intr.rs | 92 +- jh7110-vf2-13b-pac/src/i2c3/clr_rd_req.rs | 12 +- .../src/i2c3/clr_restart_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/clr_rx_done.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/clr_rx_over.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/clr_rx_under.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/clr_start_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/clr_stop_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/clr_tx_abrt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/clr_tx_over.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/comp_param_1.rs | 6 +- jh7110-vf2-13b-pac/src/i2c3/comp_type.rs | 6 +- jh7110-vf2-13b-pac/src/i2c3/comp_version.rs | 6 +- jh7110-vf2-13b-pac/src/i2c3/con.rs | 68 +- jh7110-vf2-13b-pac/src/i2c3/data_cmd.rs | 36 +- jh7110-vf2-13b-pac/src/i2c3/enable.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/enable_status.rs | 36 +- jh7110-vf2-13b-pac/src/i2c3/fs_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/fs_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/hs_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/hs_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/intr_mask.rs | 92 +- jh7110-vf2-13b-pac/src/i2c3/intr_stat.rs | 6 +- jh7110-vf2-13b-pac/src/i2c3/raw_intr_stat.rs | 6 +- jh7110-vf2-13b-pac/src/i2c3/rx_tl.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/rxflr.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/sar.rs | 18 +- jh7110-vf2-13b-pac/src/i2c3/sda_hold.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/ss_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/ss_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/status.rs | 6 +- jh7110-vf2-13b-pac/src/i2c3/tar.rs | 24 +- jh7110-vf2-13b-pac/src/i2c3/tx_abrt_source.rs | 6 +- jh7110-vf2-13b-pac/src/i2c3/tx_tl.rs | 12 +- jh7110-vf2-13b-pac/src/i2c3/txflr.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4.rs | 306 ++- jh7110-vf2-13b-pac/src/i2c4/clr_activity.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/clr_gen_call.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/clr_intr.rs | 92 +- jh7110-vf2-13b-pac/src/i2c4/clr_rd_req.rs | 12 +- .../src/i2c4/clr_restart_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/clr_rx_done.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/clr_rx_over.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/clr_rx_under.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/clr_start_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/clr_stop_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/clr_tx_abrt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/clr_tx_over.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/comp_param_1.rs | 6 +- jh7110-vf2-13b-pac/src/i2c4/comp_type.rs | 6 +- jh7110-vf2-13b-pac/src/i2c4/comp_version.rs | 6 +- jh7110-vf2-13b-pac/src/i2c4/con.rs | 68 +- jh7110-vf2-13b-pac/src/i2c4/data_cmd.rs | 36 +- jh7110-vf2-13b-pac/src/i2c4/enable.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/enable_status.rs | 36 +- jh7110-vf2-13b-pac/src/i2c4/fs_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/fs_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/hs_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/hs_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/intr_mask.rs | 92 +- jh7110-vf2-13b-pac/src/i2c4/intr_stat.rs | 6 +- jh7110-vf2-13b-pac/src/i2c4/raw_intr_stat.rs | 6 +- jh7110-vf2-13b-pac/src/i2c4/rx_tl.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/rxflr.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/sar.rs | 18 +- jh7110-vf2-13b-pac/src/i2c4/sda_hold.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/ss_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/ss_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/status.rs | 6 +- jh7110-vf2-13b-pac/src/i2c4/tar.rs | 24 +- jh7110-vf2-13b-pac/src/i2c4/tx_abrt_source.rs | 6 +- jh7110-vf2-13b-pac/src/i2c4/tx_tl.rs | 12 +- jh7110-vf2-13b-pac/src/i2c4/txflr.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5.rs | 306 ++- jh7110-vf2-13b-pac/src/i2c5/clr_activity.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/clr_gen_call.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/clr_intr.rs | 92 +- jh7110-vf2-13b-pac/src/i2c5/clr_rd_req.rs | 12 +- .../src/i2c5/clr_restart_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/clr_rx_done.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/clr_rx_over.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/clr_rx_under.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/clr_start_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/clr_stop_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/clr_tx_abrt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/clr_tx_over.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/comp_param_1.rs | 6 +- jh7110-vf2-13b-pac/src/i2c5/comp_type.rs | 6 +- jh7110-vf2-13b-pac/src/i2c5/comp_version.rs | 6 +- jh7110-vf2-13b-pac/src/i2c5/con.rs | 68 +- jh7110-vf2-13b-pac/src/i2c5/data_cmd.rs | 36 +- jh7110-vf2-13b-pac/src/i2c5/enable.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/enable_status.rs | 36 +- jh7110-vf2-13b-pac/src/i2c5/fs_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/fs_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/hs_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/hs_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/intr_mask.rs | 92 +- jh7110-vf2-13b-pac/src/i2c5/intr_stat.rs | 6 +- jh7110-vf2-13b-pac/src/i2c5/raw_intr_stat.rs | 6 +- jh7110-vf2-13b-pac/src/i2c5/rx_tl.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/rxflr.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/sar.rs | 18 +- jh7110-vf2-13b-pac/src/i2c5/sda_hold.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/ss_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/ss_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/status.rs | 6 +- jh7110-vf2-13b-pac/src/i2c5/tar.rs | 24 +- jh7110-vf2-13b-pac/src/i2c5/tx_abrt_source.rs | 6 +- jh7110-vf2-13b-pac/src/i2c5/tx_tl.rs | 12 +- jh7110-vf2-13b-pac/src/i2c5/txflr.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6.rs | 306 ++- jh7110-vf2-13b-pac/src/i2c6/clr_activity.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/clr_gen_call.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/clr_intr.rs | 92 +- jh7110-vf2-13b-pac/src/i2c6/clr_rd_req.rs | 12 +- .../src/i2c6/clr_restart_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/clr_rx_done.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/clr_rx_over.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/clr_rx_under.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/clr_start_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/clr_stop_det.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/clr_tx_abrt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/clr_tx_over.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/comp_param_1.rs | 6 +- jh7110-vf2-13b-pac/src/i2c6/comp_type.rs | 6 +- jh7110-vf2-13b-pac/src/i2c6/comp_version.rs | 6 +- jh7110-vf2-13b-pac/src/i2c6/con.rs | 68 +- jh7110-vf2-13b-pac/src/i2c6/data_cmd.rs | 36 +- jh7110-vf2-13b-pac/src/i2c6/enable.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/enable_status.rs | 36 +- jh7110-vf2-13b-pac/src/i2c6/fs_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/fs_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/hs_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/hs_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/intr_mask.rs | 92 +- jh7110-vf2-13b-pac/src/i2c6/intr_stat.rs | 6 +- jh7110-vf2-13b-pac/src/i2c6/raw_intr_stat.rs | 6 +- jh7110-vf2-13b-pac/src/i2c6/rx_tl.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/rxflr.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/sar.rs | 18 +- jh7110-vf2-13b-pac/src/i2c6/sda_hold.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/ss_scl_hcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/ss_scl_lcnt.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/status.rs | 6 +- jh7110-vf2-13b-pac/src/i2c6/tar.rs | 24 +- jh7110-vf2-13b-pac/src/i2c6/tx_abrt_source.rs | 6 +- jh7110-vf2-13b-pac/src/i2c6/tx_tl.rs | 12 +- jh7110-vf2-13b-pac/src/i2c6/txflr.rs | 12 +- jh7110-vf2-13b-pac/src/lib.rs | 19 +- jh7110-vf2-13b-pac/src/plic.rs | 1432 +++++++++---- jh7110-vf2-13b-pac/src/plic/claimplete_0.rs | 8 +- jh7110-vf2-13b-pac/src/plic/claimplete_1.rs | 8 +- jh7110-vf2-13b-pac/src/plic/claimplete_2.rs | 8 +- jh7110-vf2-13b-pac/src/plic/claimplete_3.rs | 8 +- jh7110-vf2-13b-pac/src/plic/claimplete_4.rs | 8 +- jh7110-vf2-13b-pac/src/plic/enable_0_0.rs | 8 +- jh7110-vf2-13b-pac/src/plic/enable_0_1.rs | 8 +- jh7110-vf2-13b-pac/src/plic/enable_0_2.rs | 8 +- jh7110-vf2-13b-pac/src/plic/enable_0_3.rs | 8 +- jh7110-vf2-13b-pac/src/plic/enable_0_4.rs | 8 +- jh7110-vf2-13b-pac/src/plic/enable_1_0.rs | 8 +- jh7110-vf2-13b-pac/src/plic/enable_1_1.rs | 8 +- jh7110-vf2-13b-pac/src/plic/enable_1_2.rs | 8 +- jh7110-vf2-13b-pac/src/plic/enable_1_3.rs | 8 +- jh7110-vf2-13b-pac/src/plic/enable_1_4.rs | 8 +- jh7110-vf2-13b-pac/src/plic/enable_2_0.rs | 8 +- jh7110-vf2-13b-pac/src/plic/enable_2_1.rs | 8 +- jh7110-vf2-13b-pac/src/plic/enable_2_2.rs | 8 +- jh7110-vf2-13b-pac/src/plic/enable_2_3.rs | 8 +- jh7110-vf2-13b-pac/src/plic/enable_2_4.rs | 8 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.../src/pmu/current_seq_state.rs | 6 +- .../src/pmu/encourage_type_crd.rs | 6 +- jh7110-vf2-13b-pac/src/pmu/event_status.rs | 6 +- .../src/pmu/hard_event_turn_on_mask.rs | 72 +- .../src/pmu/hard_turn_on_power_mode.rs | 48 +- jh7110-vf2-13b-pac/src/pmu/hw_event_crd.rs | 6 +- jh7110-vf2-13b-pac/src/pmu/int_status.rs | 6 +- jh7110-vf2-13b-pac/src/pmu/lp_timeout.rs | 12 +- jh7110-vf2-13b-pac/src/pmu/pch_active.rs | 6 +- jh7110-vf2-13b-pac/src/pmu/pch_bypass.rs | 12 +- jh7110-vf2-13b-pac/src/pmu/pch_pstate.rs | 12 +- jh7110-vf2-13b-pac/src/pmu/pch_timeout.rs | 12 +- jh7110-vf2-13b-pac/src/pmu/pdc0.rs | 42 +- jh7110-vf2-13b-pac/src/pmu/pdc1.rs | 42 +- jh7110-vf2-13b-pac/src/pmu/pdc2.rs | 42 +- .../src/pmu/soft_turn_off_power_mode.rs | 48 +- .../src/pmu/soft_turn_on_power_mode.rs | 48 +- jh7110-vf2-13b-pac/src/pmu/sw_encourage.rs | 12 +- jh7110-vf2-13b-pac/src/pmu/tim.rs | 36 +- jh7110-vf2-13b-pac/src/pmu/timeout_seq_thd.rs | 12 +- jh7110-vf2-13b-pac/src/qspi.rs | 262 ++- jh7110-vf2-13b-pac/src/qspi/cmd_address.rs | 12 +- jh7110-vf2-13b-pac/src/qspi/cmd_ctrl.rs | 68 +- .../src/qspi/cmd_read_at_lower.rs | 12 +- .../src/qspi/cmd_read_at_upper.rs | 12 +- .../src/qspi/cmd_write_at_lower.rs | 12 +- .../src/qspi/cmd_write_at_upper.rs | 12 +- jh7110-vf2-13b-pac/src/qspi/config.rs | 62 +- jh7110-vf2-13b-pac/src/qspi/delay.rs | 30 +- jh7110-vf2-13b-pac/src/qspi/dma.rs | 18 +- jh7110-vf2-13b-pac/src/qspi/ext_lower.rs | 24 +- jh7110-vf2-13b-pac/src/qspi/indirect_rd.rs | 24 +- .../src/qspi/indirect_rd_bytes.rs | 12 +- .../src/qspi/indirect_rd_start_addr.rs | 12 +- .../src/qspi/indirect_rd_watermark.rs | 12 +- .../src/qspi/indirect_trigger.rs | 12 +- jh7110-vf2-13b-pac/src/qspi/indirect_wr.rs | 24 +- .../src/qspi/indirect_wr_bytes.rs | 12 +- .../src/qspi/indirect_wr_start_addr.rs | 12 +- .../src/qspi/indirect_wr_watermark.rs | 12 +- jh7110-vf2-13b-pac/src/qspi/irq_mask.rs | 56 +- jh7110-vf2-13b-pac/src/qspi/irq_status.rs | 56 +- jh7110-vf2-13b-pac/src/qspi/mode_bit.rs | 12 +- jh7110-vf2-13b-pac/src/qspi/polling_status.rs | 18 +- jh7110-vf2-13b-pac/src/qspi/rd_instr.rs | 42 +- jh7110-vf2-13b-pac/src/qspi/read_capture.rs | 18 +- jh7110-vf2-13b-pac/src/qspi/remap.rs | 12 +- jh7110-vf2-13b-pac/src/qspi/sdram_level.rs | 6 +- jh7110-vf2-13b-pac/src/qspi/size.rs | 24 +- jh7110-vf2-13b-pac/src/qspi/sram_partition.rs | 12 +- .../src/qspi/wr_completion_ctrl.rs | 12 +- jh7110-vf2-13b-pac/src/qspi/wr_instr.rs | 24 +- jh7110-vf2-13b-pac/src/spi0.rs | 180 +- jh7110-vf2-13b-pac/src/spi0/ssp_cpsr.rs | 12 +- jh7110-vf2-13b-pac/src/spi0/ssp_cr0.rs | 36 +- jh7110-vf2-13b-pac/src/spi0/ssp_cr1.rs | 30 +- jh7110-vf2-13b-pac/src/spi0/ssp_dmacr.rs | 18 +- jh7110-vf2-13b-pac/src/spi0/ssp_dr.rs | 12 +- jh7110-vf2-13b-pac/src/spi0/ssp_icr.rs | 18 +- jh7110-vf2-13b-pac/src/spi0/ssp_imsc.rs | 30 +- jh7110-vf2-13b-pac/src/spi0/ssp_mis.rs | 6 +- jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id0.rs | 6 +- jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id1.rs | 6 +- jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id2.rs | 6 +- jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id3.rs | 6 +- jh7110-vf2-13b-pac/src/spi0/ssp_periph_id0.rs | 6 +- jh7110-vf2-13b-pac/src/spi0/ssp_periph_id1.rs | 6 +- jh7110-vf2-13b-pac/src/spi0/ssp_periph_id2.rs | 6 +- jh7110-vf2-13b-pac/src/spi0/ssp_periph_id3.rs | 6 +- jh7110-vf2-13b-pac/src/spi0/ssp_ris.rs | 6 +- jh7110-vf2-13b-pac/src/spi0/ssp_sr.rs | 6 +- jh7110-vf2-13b-pac/src/spi1.rs | 180 +- jh7110-vf2-13b-pac/src/spi1/ssp_cpsr.rs | 12 +- jh7110-vf2-13b-pac/src/spi1/ssp_cr0.rs | 36 +- jh7110-vf2-13b-pac/src/spi1/ssp_cr1.rs | 30 +- jh7110-vf2-13b-pac/src/spi1/ssp_dmacr.rs | 18 +- jh7110-vf2-13b-pac/src/spi1/ssp_dr.rs | 12 +- jh7110-vf2-13b-pac/src/spi1/ssp_icr.rs | 18 +- jh7110-vf2-13b-pac/src/spi1/ssp_imsc.rs | 30 +- jh7110-vf2-13b-pac/src/spi1/ssp_mis.rs | 6 +- jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id0.rs | 6 +- jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id1.rs | 6 +- jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id2.rs | 6 +- jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id3.rs | 6 +- jh7110-vf2-13b-pac/src/spi1/ssp_periph_id0.rs | 6 +- jh7110-vf2-13b-pac/src/spi1/ssp_periph_id1.rs | 6 +- jh7110-vf2-13b-pac/src/spi1/ssp_periph_id2.rs | 6 +- jh7110-vf2-13b-pac/src/spi1/ssp_periph_id3.rs | 6 +- jh7110-vf2-13b-pac/src/spi1/ssp_ris.rs | 6 +- jh7110-vf2-13b-pac/src/spi1/ssp_sr.rs | 6 +- jh7110-vf2-13b-pac/src/spi2.rs | 180 +- jh7110-vf2-13b-pac/src/spi2/ssp_cpsr.rs | 12 +- jh7110-vf2-13b-pac/src/spi2/ssp_cr0.rs | 36 +- jh7110-vf2-13b-pac/src/spi2/ssp_cr1.rs | 30 +- jh7110-vf2-13b-pac/src/spi2/ssp_dmacr.rs | 18 +- jh7110-vf2-13b-pac/src/spi2/ssp_dr.rs | 12 +- jh7110-vf2-13b-pac/src/spi2/ssp_icr.rs | 18 +- jh7110-vf2-13b-pac/src/spi2/ssp_imsc.rs | 30 +- jh7110-vf2-13b-pac/src/spi2/ssp_mis.rs | 6 +- jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id0.rs | 6 +- jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id1.rs | 6 +- jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id2.rs | 6 +- jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id3.rs | 6 +- jh7110-vf2-13b-pac/src/spi2/ssp_periph_id0.rs | 6 +- jh7110-vf2-13b-pac/src/spi2/ssp_periph_id1.rs | 6 +- jh7110-vf2-13b-pac/src/spi2/ssp_periph_id2.rs | 6 +- jh7110-vf2-13b-pac/src/spi2/ssp_periph_id3.rs | 6 +- jh7110-vf2-13b-pac/src/spi2/ssp_ris.rs | 6 +- jh7110-vf2-13b-pac/src/spi2/ssp_sr.rs | 6 +- jh7110-vf2-13b-pac/src/spi3.rs | 180 +- jh7110-vf2-13b-pac/src/spi3/ssp_cpsr.rs | 12 +- jh7110-vf2-13b-pac/src/spi3/ssp_cr0.rs | 36 +- jh7110-vf2-13b-pac/src/spi3/ssp_cr1.rs | 30 +- jh7110-vf2-13b-pac/src/spi3/ssp_dmacr.rs | 18 +- jh7110-vf2-13b-pac/src/spi3/ssp_dr.rs | 12 +- jh7110-vf2-13b-pac/src/spi3/ssp_icr.rs | 18 +- jh7110-vf2-13b-pac/src/spi3/ssp_imsc.rs | 30 +- jh7110-vf2-13b-pac/src/spi3/ssp_mis.rs | 6 +- jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id0.rs | 6 +- jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id1.rs | 6 +- jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id2.rs | 6 +- jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id3.rs | 6 +- jh7110-vf2-13b-pac/src/spi3/ssp_periph_id0.rs | 6 +- jh7110-vf2-13b-pac/src/spi3/ssp_periph_id1.rs | 6 +- jh7110-vf2-13b-pac/src/spi3/ssp_periph_id2.rs | 6 +- jh7110-vf2-13b-pac/src/spi3/ssp_periph_id3.rs | 6 +- jh7110-vf2-13b-pac/src/spi3/ssp_ris.rs | 6 +- jh7110-vf2-13b-pac/src/spi3/ssp_sr.rs | 6 +- jh7110-vf2-13b-pac/src/spi4.rs | 180 +- jh7110-vf2-13b-pac/src/spi4/ssp_cpsr.rs | 12 +- jh7110-vf2-13b-pac/src/spi4/ssp_cr0.rs | 36 +- jh7110-vf2-13b-pac/src/spi4/ssp_cr1.rs | 30 +- jh7110-vf2-13b-pac/src/spi4/ssp_dmacr.rs | 18 +- jh7110-vf2-13b-pac/src/spi4/ssp_dr.rs | 12 +- jh7110-vf2-13b-pac/src/spi4/ssp_icr.rs | 18 +- jh7110-vf2-13b-pac/src/spi4/ssp_imsc.rs | 30 +- jh7110-vf2-13b-pac/src/spi4/ssp_mis.rs | 6 +- jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id0.rs | 6 +- jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id1.rs | 6 +- jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id2.rs | 6 +- jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id3.rs | 6 +- jh7110-vf2-13b-pac/src/spi4/ssp_periph_id0.rs | 6 +- jh7110-vf2-13b-pac/src/spi4/ssp_periph_id1.rs | 6 +- jh7110-vf2-13b-pac/src/spi4/ssp_periph_id2.rs | 6 +- jh7110-vf2-13b-pac/src/spi4/ssp_periph_id3.rs | 6 +- jh7110-vf2-13b-pac/src/spi4/ssp_ris.rs | 6 +- jh7110-vf2-13b-pac/src/spi4/ssp_sr.rs | 6 +- jh7110-vf2-13b-pac/src/spi5.rs | 180 +- jh7110-vf2-13b-pac/src/spi5/ssp_cpsr.rs | 12 +- jh7110-vf2-13b-pac/src/spi5/ssp_cr0.rs | 36 +- jh7110-vf2-13b-pac/src/spi5/ssp_cr1.rs | 30 +- jh7110-vf2-13b-pac/src/spi5/ssp_dmacr.rs | 18 +- jh7110-vf2-13b-pac/src/spi5/ssp_dr.rs | 12 +- jh7110-vf2-13b-pac/src/spi5/ssp_icr.rs | 18 +- jh7110-vf2-13b-pac/src/spi5/ssp_imsc.rs | 30 +- jh7110-vf2-13b-pac/src/spi5/ssp_mis.rs | 6 +- jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id0.rs | 6 +- jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id1.rs | 6 +- jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id2.rs | 6 +- jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id3.rs | 6 +- jh7110-vf2-13b-pac/src/spi5/ssp_periph_id0.rs | 6 +- jh7110-vf2-13b-pac/src/spi5/ssp_periph_id1.rs | 6 +- jh7110-vf2-13b-pac/src/spi5/ssp_periph_id2.rs | 6 +- jh7110-vf2-13b-pac/src/spi5/ssp_periph_id3.rs | 6 +- jh7110-vf2-13b-pac/src/spi5/ssp_ris.rs | 6 +- jh7110-vf2-13b-pac/src/spi5/ssp_sr.rs | 6 +- jh7110-vf2-13b-pac/src/spi6.rs | 180 +- jh7110-vf2-13b-pac/src/spi6/ssp_cpsr.rs | 12 +- jh7110-vf2-13b-pac/src/spi6/ssp_cr0.rs | 36 +- jh7110-vf2-13b-pac/src/spi6/ssp_cr1.rs | 30 +- jh7110-vf2-13b-pac/src/spi6/ssp_dmacr.rs | 18 +- jh7110-vf2-13b-pac/src/spi6/ssp_dr.rs | 12 +- jh7110-vf2-13b-pac/src/spi6/ssp_icr.rs | 18 +- jh7110-vf2-13b-pac/src/spi6/ssp_imsc.rs | 30 +- jh7110-vf2-13b-pac/src/spi6/ssp_mis.rs | 6 +- jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id0.rs | 6 +- jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id1.rs | 6 +- jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id2.rs | 6 +- jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id3.rs | 6 +- jh7110-vf2-13b-pac/src/spi6/ssp_periph_id0.rs | 6 +- jh7110-vf2-13b-pac/src/spi6/ssp_periph_id1.rs | 6 +- jh7110-vf2-13b-pac/src/spi6/ssp_periph_id2.rs | 6 +- jh7110-vf2-13b-pac/src/spi6/ssp_periph_id3.rs | 6 +- jh7110-vf2-13b-pac/src/spi6/ssp_ris.rs | 6 +- jh7110-vf2-13b-pac/src/spi6/ssp_sr.rs | 6 +- jh7110-vf2-13b-pac/src/stg_syscon.rs | 1868 ++++++++++++----- .../src/stg_syscon/stg_sysconsaif_syscfg0.rs | 76 +- .../stg_syscon/stg_sysconsaif_syscfg100.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg104.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg108.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg112.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg116.rs | 6 +- .../src/stg_syscon/stg_sysconsaif_syscfg12.rs | 73 +- .../stg_syscon/stg_sysconsaif_syscfg120.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg124.rs | 12 +- .../stg_syscon/stg_sysconsaif_syscfg128.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg132.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg136.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg140.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg144.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg148.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg152.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg156.rs | 13 +- .../src/stg_syscon/stg_sysconsaif_syscfg16.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg160.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg164.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg168.rs | 27 +- .../stg_syscon/stg_sysconsaif_syscfg172.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg176.rs | 27 +- .../stg_syscon/stg_sysconsaif_syscfg180.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg184.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg188.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg192.rs | 12 +- .../stg_syscon/stg_sysconsaif_syscfg196.rs | 39 +- .../src/stg_syscon/stg_sysconsaif_syscfg20.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg200.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg204.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg208.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg212.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg216.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg220.rs | 13 +- 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| 6 +- .../stg_syscon/stg_sysconsaif_syscfg432.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg436.rs | 6 +- .../src/stg_syscon/stg_sysconsaif_syscfg44.rs | 14 +- .../stg_syscon/stg_sysconsaif_syscfg440.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg444.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg448.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg452.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg456.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg460.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg464.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg468.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg472.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg476.rs | 6 +- .../src/stg_syscon/stg_sysconsaif_syscfg48.rs | 26 +- .../stg_syscon/stg_sysconsaif_syscfg480.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg484.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg488.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg492.rs | 19 +- .../stg_syscon/stg_sysconsaif_syscfg500.rs | 92 +- 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| 6 +- .../src/stg_syscon/stg_sysconsaif_syscfg92.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg920.rs | 6 +- .../stg_syscon/stg_sysconsaif_syscfg924.rs | 19 +- .../stg_syscon/stg_sysconsaif_syscfg928.rs | 13 +- .../stg_syscon/stg_sysconsaif_syscfg932.rs | 42 +- .../src/stg_syscon/stg_sysconsaif_syscfg96.rs | 6 +- jh7110-vf2-13b-pac/src/stgcrg.rs | 250 ++- jh7110-vf2-13b-pac/src/stgcrg/clk_dma_ahb.rs | 12 +- jh7110-vf2-13b-pac/src/stgcrg/clk_dma_axi.rs | 12 +- jh7110-vf2-13b-pac/src/stgcrg/clk_e2_core.rs | 12 +- jh7110-vf2-13b-pac/src/stgcrg/clk_e2_dbg.rs | 12 +- jh7110-vf2-13b-pac/src/stgcrg/clk_e2_rtc.rs | 18 +- .../src/stgcrg/clk_hifi4_core.rs | 12 +- .../src/stgcrg/clk_pcie01_slv_dec_main.rs | 12 +- jh7110-vf2-13b-pac/src/stgcrg/clk_sec_hclk.rs | 12 +- .../src/stgcrg/clk_sec_misc_ahb.rs | 12 +- .../src/stgcrg/clk_stg_mtrx_group0_bus.rs | 12 +- .../src/stgcrg/clk_stg_mtrx_group0_main.rs | 12 +- .../src/stgcrg/clk_stg_mtrx_group0_stg.rs | 12 +- .../src/stgcrg/clk_stg_mtrx_group1_bus.rs | 12 +- .../src/stgcrg/clk_stg_mtrx_group1_hifi.rs | 12 +- .../src/stgcrg/clk_stg_mtrx_group1_main.rs | 12 +- .../src/stgcrg/clk_stg_mtrx_group1_stg.rs | 12 +- .../src/stgcrg/clk_u0_pcie_apb.rs | 12 +- .../src/stgcrg/clk_u0_pcie_axi_mst0.rs | 12 +- .../src/stgcrg/clk_u0_pcie_tl.rs | 12 +- .../src/stgcrg/clk_u1_pcie_apb.rs | 12 +- .../src/stgcrg/clk_u1_pcie_axi_mst0.rs | 12 +- .../src/stgcrg/clk_u1_pcie_tl.rs | 12 +- jh7110-vf2-13b-pac/src/stgcrg/clk_usb_apb.rs | 12 +- .../src/stgcrg/clk_usb_app125.rs | 12 +- jh7110-vf2-13b-pac/src/stgcrg/clk_usb_axi.rs | 12 +- jh7110-vf2-13b-pac/src/stgcrg/clk_usb_ipm.rs | 18 +- .../src/stgcrg/clk_usb_refclk.rs | 12 +- jh7110-vf2-13b-pac/src/stgcrg/clk_usb_stb.rs | 18 +- .../src/stgcrg/clk_usb_utmi_apb.rs | 12 +- .../src/stgcrg/soft_rst_addr_sel.rs | 146 +- .../src/stgcrg/stgcrg_rst_stat.rs | 150 +- jh7110-vf2-13b-pac/src/sys_pinctrl.rs | 1398 ++++++++---- .../src/sys_pinctrl/func_sel0.rs | 74 +- .../src/sys_pinctrl/func_sel1.rs | 68 +- .../src/sys_pinctrl/func_sel2.rs | 74 +- .../src/sys_pinctrl/func_sel3.rs | 74 +- .../src/sys_pinctrl/func_sel4.rs | 74 +- .../src/sys_pinctrl/func_sel5.rs | 81 +- .../src/sys_pinctrl/func_sel6.rs | 65 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi0.rs | 31 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi12.rs | 30 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi16.rs | 32 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi20.rs | 33 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi24.rs | 32 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi28.rs | 32 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi32.rs | 36 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi36.rs | 30 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi4.rs | 34 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi40.rs | 30 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi44.rs | 30 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi48.rs | 30 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi52.rs | 30 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi56.rs | 30 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi60.rs | 30 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi64.rs | 30 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi68.rs | 30 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi72.rs | 30 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi76.rs | 30 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi8.rs | 31 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi80.rs | 30 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi84.rs | 30 +- jh7110-vf2-13b-pac/src/sys_pinctrl/gpi88.rs | 24 +- .../src/sys_pinctrl/gpo_doen0.rs | 30 +- .../src/sys_pinctrl/gpo_doen1.rs | 30 +- .../src/sys_pinctrl/gpo_doen10.rs | 30 +- .../src/sys_pinctrl/gpo_doen11.rs | 30 +- .../src/sys_pinctrl/gpo_doen12.rs | 30 +- .../src/sys_pinctrl/gpo_doen13.rs | 30 +- .../src/sys_pinctrl/gpo_doen14.rs | 30 +- .../src/sys_pinctrl/gpo_doen15.rs | 30 +- .../src/sys_pinctrl/gpo_doen2.rs | 30 +- .../src/sys_pinctrl/gpo_doen3.rs | 30 +- .../src/sys_pinctrl/gpo_doen4.rs | 30 +- .../src/sys_pinctrl/gpo_doen5.rs | 30 +- .../src/sys_pinctrl/gpo_doen6.rs | 30 +- .../src/sys_pinctrl/gpo_doen7.rs | 30 +- .../src/sys_pinctrl/gpo_doen8.rs | 30 +- .../src/sys_pinctrl/gpo_doen9.rs | 30 +- .../src/sys_pinctrl/gpo_dout0_3.rs | 30 +- .../src/sys_pinctrl/gpo_dout12_15.rs | 30 +- .../src/sys_pinctrl/gpo_dout16_19.rs | 30 +- .../src/sys_pinctrl/gpo_dout20_23.rs | 30 +- .../src/sys_pinctrl/gpo_dout24_27.rs | 30 +- .../src/sys_pinctrl/gpo_dout28_31.rs | 30 +- .../src/sys_pinctrl/gpo_dout32_35.rs | 30 +- .../src/sys_pinctrl/gpo_dout36_39.rs | 30 +- .../src/sys_pinctrl/gpo_dout40_43.rs | 30 +- .../src/sys_pinctrl/gpo_dout44_47.rs | 30 +- .../src/sys_pinctrl/gpo_dout48_51.rs | 30 +- .../src/sys_pinctrl/gpo_dout4_7.rs | 30 +- .../src/sys_pinctrl/gpo_dout52_55.rs | 30 +- .../src/sys_pinctrl/gpo_dout56_59.rs | 30 +- .../src/sys_pinctrl/gpo_dout60_63.rs | 30 +- .../src/sys_pinctrl/gpo_dout8_11.rs | 30 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq0.rs | 12 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq1.rs | 12 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq10.rs | 12 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq11.rs | 6 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq12.rs | 6 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq13.rs | 6 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq14.rs | 6 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq15.rs | 6 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq16.rs | 6 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq2.rs | 12 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq3.rs | 12 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq4.rs | 12 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq5.rs | 12 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq6.rs | 12 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq7.rs | 12 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq8.rs | 12 +- jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq9.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_mdc_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_mdio_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_rxc_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_rxd0_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_rxd1_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_rxd2_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_rxd3_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_rxdv_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_txc_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_txd0_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_txd1_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_txd2_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_txd3_syscon.rs | 12 +- .../sys_pinctrl/padcfg_gmac1_txen_syscon.rs | 12 +- .../src/sys_pinctrl/padcfg_gpio0.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio1.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio10.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio11.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio12.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio13.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio14.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio15.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio16.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio17.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio18.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio19.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio2.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio20.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio21.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio22.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio23.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio24.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio25.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio26.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio27.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio28.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio29.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio3.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio30.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio31.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio32.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio33.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio34.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio35.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio36.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio37.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio38.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio39.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio4.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio40.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio41.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio42.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio43.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio44.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio45.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio46.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio47.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio48.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio49.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio5.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio50.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio51.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio52.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio53.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio54.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio55.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio56.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio57.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio58.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio59.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio6.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio60.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio61.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio62.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio63.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio7.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio8.rs | 48 +- .../src/sys_pinctrl/padcfg_gpio9.rs | 48 +- .../src/sys_pinctrl/padcfg_qspi_csn0.rs | 48 +- .../src/sys_pinctrl/padcfg_qspi_data0.rs | 48 +- .../src/sys_pinctrl/padcfg_qspi_data1.rs | 48 +- .../src/sys_pinctrl/padcfg_qspi_data2.rs | 48 +- .../src/sys_pinctrl/padcfg_qspi_data3.rs | 48 +- .../src/sys_pinctrl/padcfg_qspi_sclk.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_clk.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_cmd.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_data0.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_data1.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_data2.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_data3.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_data4.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_data5.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_data6.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_data7.rs | 48 +- .../src/sys_pinctrl/padcfg_sd0_strb.rs | 48 +- jh7110-vf2-13b-pac/src/sys_syscon.rs | 316 ++- .../src/sys_syscon/sys_sysconsaif_syscfg0.rs | 58 +- .../sys_syscon/sys_sysconsaif_syscfg100.rs | 32 +- .../sys_syscon/sys_sysconsaif_syscfg104.rs | 13 +- .../sys_syscon/sys_sysconsaif_syscfg108.rs | 13 +- .../sys_syscon/sys_sysconsaif_syscfg112.rs | 13 +- .../sys_syscon/sys_sysconsaif_syscfg116.rs | 13 +- .../src/sys_syscon/sys_sysconsaif_syscfg12.rs | 30 +- .../sys_syscon/sys_sysconsaif_syscfg120.rs | 13 +- .../sys_syscon/sys_sysconsaif_syscfg124.rs | 13 +- .../sys_syscon/sys_sysconsaif_syscfg128.rs | 13 +- .../sys_syscon/sys_sysconsaif_syscfg136.rs | 90 +- .../sys_syscon/sys_sysconsaif_syscfg140.rs | 61 +- .../sys_syscon/sys_sysconsaif_syscfg144.rs | 12 +- .../sys_syscon/sys_sysconsaif_syscfg148.rs | 6 +- .../sys_syscon/sys_sysconsaif_syscfg152.rs | 6 +- .../sys_syscon/sys_sysconsaif_syscfg156.rs | 40 +- .../src/sys_syscon/sys_sysconsaif_syscfg16.rs | 18 +- .../src/sys_syscon/sys_sysconsaif_syscfg20.rs | 128 +- .../src/sys_syscon/sys_sysconsaif_syscfg24.rs | 123 +- .../src/sys_syscon/sys_sysconsaif_syscfg28.rs | 12 +- .../src/sys_syscon/sys_sysconsaif_syscfg32.rs | 38 +- .../src/sys_syscon/sys_sysconsaif_syscfg36.rs | 56 +- .../src/sys_syscon/sys_sysconsaif_syscfg4.rs | 58 +- .../src/sys_syscon/sys_sysconsaif_syscfg40.rs | 38 +- .../src/sys_syscon/sys_sysconsaif_syscfg44.rs | 56 +- .../src/sys_syscon/sys_sysconsaif_syscfg48.rs | 38 +- .../src/sys_syscon/sys_sysconsaif_syscfg52.rs | 94 +- .../src/sys_syscon/sys_sysconsaif_syscfg56.rs | 57 +- .../src/sys_syscon/sys_sysconsaif_syscfg60.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg64.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg68.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg72.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg76.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg8.rs | 24 +- .../src/sys_syscon/sys_sysconsaif_syscfg80.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg84.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg88.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg92.rs | 14 +- .../src/sys_syscon/sys_sysconsaif_syscfg96.rs | 42 +- jh7110-vf2-13b-pac/src/syscrg.rs | 1599 ++++++++++---- jh7110-vf2-13b-pac/src/syscrg/clk_ahb0.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_ahb1.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_apb0.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_apb_bus.rs | 12 +- .../src/syscrg/clk_audio_root.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0.rs | 12 +- .../src/syscrg/clk_axi_cfg0_dec_hifi4.rs | 12 +- .../src/syscrg/clk_axi_cfg0_dec_main.rs | 12 +- .../src/syscrg/clk_axi_cfg0_dec_main_div.rs | 12 +- .../src/syscrg/clk_aximem_128b_axi.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_bus_root.rs | 12 +- .../src/syscrg/clk_codaj12_apb.rs | 12 +- .../src/syscrg/clk_codaj12_axi.rs | 12 +- .../src/syscrg/clk_codaj12_core.rs | 18 +- jh7110-vf2-13b-pac/src/syscrg/clk_cpu_bus.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_cpu_core.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_cpu_root.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_ddr_bus.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_gclk0.rs | 18 +- jh7110-vf2-13b-pac/src/syscrg/clk_gclk1.rs | 18 +- jh7110-vf2-13b-pac/src/syscrg/clk_gclk2.rs | 18 +- .../src/syscrg/clk_gmac0_gtx.rs | 18 +- .../src/syscrg/clk_gmac0_gtxclk.rs | 12 +- .../src/syscrg/clk_gmac0_ptp.rs | 18 +- .../src/syscrg/clk_gmac1_gtx.rs | 12 +- .../src/syscrg/clk_gmac1_gtxclk.rs | 12 +- .../src/syscrg/clk_gmac1_rmii_rtx.rs | 12 +- .../src/syscrg/clk_gmac5_axi64_ahb.rs | 12 +- .../src/syscrg/clk_gmac5_axi64_axi.rs | 12 +- .../src/syscrg/clk_gmac5_axi64_ptp.rs | 18 +- .../src/syscrg/clk_gmac5_axi64_rx.rs | 12 +- .../src/syscrg/clk_gmac5_axi64_rxi.rs | 12 +- .../src/syscrg/clk_gmac5_axi64_tx.rs | 18 +- .../src/syscrg/clk_gmac5_axi64_txi.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_gmac_phy.rs | 18 +- jh7110-vf2-13b-pac/src/syscrg/clk_gmac_src.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_gpu_core.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_gpu_root.rs | 12 +- .../src/syscrg/clk_hifi4_axi.rs | 12 +- .../src/syscrg/clk_hifi4_core.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_i2s_apb.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk.rs | 12 +- .../src/syscrg/clk_i2s_bclk_mst.rs | 18 +- .../src/syscrg/clk_i2s_bclk_mst_inv.rs | 12 +- .../src/syscrg/clk_i2s_bclk_neg.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_i2s_lrck.rs | 12 +- .../src/syscrg/clk_i2s_lrck_mst.rs | 18 +- .../src/syscrg/clk_i2stx0_lrck_mst.rs | 18 +- .../src/syscrg/clk_i2stx1_lrck_mst.rs | 18 +- .../src/syscrg/clk_internal_ctrl_apb.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_isp_2x.rs | 18 +- jh7110-vf2-13b-pac/src/syscrg/clk_isp_axi.rs | 12 +- .../src/syscrg/clk_jpeg_codec_axi.rs | 12 +- .../src/syscrg/clk_jtag_cert_trng.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_mbox_apb.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_mclk.rs | 12 +- .../src/syscrg/clk_mclk_inner.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_mclk_out.rs | 12 +- .../src/syscrg/clk_noc_display_axi.rs | 12 +- .../src/syscrg/clk_noc_stg_axi.rs | 12 +- .../src/syscrg/clk_noc_vdec_axi.rs | 12 +- .../src/syscrg/clk_noc_venc_axi.rs | 12 +- .../src/syscrg/clk_nocstg_bus.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_osc_div2.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_pdm_apb.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_pdm_dmic.rs | 18 +- .../src/syscrg/clk_peripheral_root.rs | 18 +- .../src/syscrg/clk_pll0_div2.rs | 12 +- .../src/syscrg/clk_pll1_div2.rs | 12 +- .../src/syscrg/clk_pll1_div4.rs | 12 +- .../src/syscrg/clk_pll1_div8.rs | 12 +- .../src/syscrg/clk_pll2_div2.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_pwm_apb.rs | 12 +- .../src/syscrg/clk_pwmdac_apb.rs | 12 +- .../src/syscrg/clk_pwmdac_core.rs | 18 +- jh7110-vf2-13b-pac/src/syscrg/clk_qspi_ahb.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_qspi_apb.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_qspi_ref.rs | 18 +- .../src/syscrg/clk_qspi_ref_src.rs | 12 +- .../src/syscrg/clk_spdif_apb.rs | 12 +- .../src/syscrg/clk_spdif_core.rs | 12 +- .../src/syscrg/clk_stg_axiahb.rs | 12 +- .../src/syscrg/clk_sys_iomux_pclk.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_tdm.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_tdm_ahb.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_tdm_apb.rs | 12 +- .../src/syscrg/clk_tdm_internal.rs | 18 +- jh7110-vf2-13b-pac/src/syscrg/clk_tdm_neg.rs | 12 +- .../src/syscrg/clk_temp_sensor.rs | 18 +- .../src/syscrg/clk_temp_sensor_apb.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_tim0.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_tim1.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_tim2.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_tim3.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_tim_apb.rs | 12 +- .../src/syscrg/clk_u0_axi_cfg1_dec_clk_ahb.rs | 12 +- .../syscrg/clk_u0_axi_cfg1_dec_clk_main.rs | 12 +- .../src/syscrg/clk_u0_can_ctrl_apb.rs | 12 +- .../src/syscrg/clk_u0_can_ctrl_can.rs | 18 +- .../src/syscrg/clk_u0_can_ctrl_tim.rs | 18 +- .../src/syscrg/clk_u0_ddr_sft7110_clk_axi.rs | 12 +- ...dom_isp_top_clk_dom_isp_top_clk_isp_axi.rs | 14 +- ..._isp_top_clk_dom_isp_top_clk_ispcore_2x.rs | 14 +- ..._vout_top_clk_dom_vout_top_clk_vout_src.rs | 14 +- .../src/syscrg/clk_u0_gpu_rtc_toggle.rs | 18 +- .../src/syscrg/clk_u0_i2c_apb.rs | 12 +- .../src/syscrg/clk_u0_i2s_tx_apb.rs | 12 +- .../src/syscrg/clk_u0_i2stx_4ch0_bclk_mst.rs | 18 +- .../syscrg/clk_u0_i2stx_4ch0_bclk_mst_inv.rs | 12 +- .../src/syscrg/clk_u0_i2stx_bclk.rs | 12 +- .../src/syscrg/clk_u0_i2stx_bclk_neg.rs | 12 +- .../src/syscrg/clk_u0_i2stx_lrck.rs | 12 +- .../src/syscrg/clk_u0_img_gpu_clk_apb.rs | 12 +- .../src/syscrg/clk_u0_img_gpu_core_clk.rs | 12 +- .../src/syscrg/clk_u0_img_gpu_sys_clk.rs | 12 +- .../src/syscrg/clk_u0_sd_ahb.rs | 12 +- .../src/syscrg/clk_u0_sd_card.rs | 18 +- .../clk_u0_sft7110_noc_bus_clk_axicfg0_axi.rs | 12 +- .../clk_u0_sft7110_noc_bus_clk_cpu_axi.rs | 12 +- .../clk_u0_sft7110_noc_bus_clk_gpu_axi.rs | 12 +- .../clk_u0_sft7110_noc_bux_clk_isp_axi.rs | 12 +- .../src/syscrg/clk_u0_spi_apb.rs | 12 +- .../src/syscrg/clk_u0_uart_apb.rs | 12 +- .../src/syscrg/clk_u0_uart_core.rs | 12 +- .../src/syscrg/clk_u1_can_ctrl_apb.rs | 12 +- .../src/syscrg/clk_u1_can_ctrl_can.rs | 18 +- .../src/syscrg/clk_u1_can_ctrl_tim.rs | 18 +- .../src/syscrg/clk_u1_i2c_apb.rs | 12 +- .../src/syscrg/clk_u1_i2s_tx_apb.rs | 12 +- .../src/syscrg/clk_u1_i2stx_4ch1_bclk_mst.rs | 18 +- .../syscrg/clk_u1_i2stx_4ch1_bclk_mst_inv.rs | 12 +- .../src/syscrg/clk_u1_i2stx_bclk.rs | 12 +- .../src/syscrg/clk_u1_i2stx_bclk_neg.rs | 12 +- .../src/syscrg/clk_u1_i2stx_lrck.rs | 12 +- .../src/syscrg/clk_u1_sd_ahb.rs | 12 +- .../src/syscrg/clk_u1_sd_card.rs | 18 +- .../src/syscrg/clk_u1_spi_apb.rs | 12 +- .../src/syscrg/clk_u1_uart_apb.rs | 12 +- .../src/syscrg/clk_u1_uart_core.rs | 12 +- .../src/syscrg/clk_u2_i2c_apb.rs | 12 +- .../src/syscrg/clk_u2_spi_apb.rs | 12 +- .../src/syscrg/clk_u2_uart_apb.rs | 12 +- .../src/syscrg/clk_u2_uart_core.rs | 12 +- .../src/syscrg/clk_u3_i2c_apb.rs | 12 +- .../src/syscrg/clk_u3_spi_apb.rs | 12 +- .../src/syscrg/clk_u3_uart_apb.rs | 12 +- .../src/syscrg/clk_u3_uart_core.rs | 18 +- .../src/syscrg/clk_u4_i2c_apb.rs | 12 +- .../src/syscrg/clk_u4_spi_apb.rs | 12 +- .../src/syscrg/clk_u4_uart_apb.rs | 12 +- .../src/syscrg/clk_u4_uart_core.rs | 18 +- .../src/syscrg/clk_u5_i2c_apb.rs | 12 +- .../src/syscrg/clk_u5_spi_apb.rs | 12 +- .../src/syscrg/clk_u5_uart_apb.rs | 12 +- .../src/syscrg/clk_u5_uart_core.rs | 18 +- .../src/syscrg/clk_u6_i2c_apb.rs | 12 +- .../src/syscrg/clk_u6_spi_apb.rs | 12 +- .../src/syscrg/clk_u7mc_core0.rs | 12 +- .../src/syscrg/clk_u7mc_core1.rs | 12 +- .../src/syscrg/clk_u7mc_core2.rs | 12 +- .../src/syscrg/clk_u7mc_core3.rs | 12 +- .../src/syscrg/clk_u7mc_core4.rs | 12 +- .../src/syscrg/clk_u7mc_debug.rs | 12 +- .../src/syscrg/clk_u7mc_trace0.rs | 12 +- .../src/syscrg/clk_u7mc_trace1.rs | 12 +- .../src/syscrg/clk_u7mc_trace2.rs | 12 +- .../src/syscrg/clk_u7mc_trace3.rs | 12 +- .../src/syscrg/clk_u7mc_trace4.rs | 12 +- .../src/syscrg/clk_u7mc_trace_com.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_usb_125m.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_vdec_axi.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_venc_axi.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_vout_ahb.rs | 12 +- .../src/syscrg/clk_vout_axi_divcfg.rs | 12 +- .../src/syscrg/clk_vout_axi_icg.rs | 12 +- .../src/syscrg/clk_vout_hdmi_tx0_mclk.rs | 12 +- .../src/syscrg/clk_vout_mipi_phy.rs | 12 +- .../src/syscrg/clk_wave420l_apb.rs | 12 +- .../src/syscrg/clk_wave420l_axi.rs | 12 +- .../src/syscrg/clk_wave420l_bpu.rs | 18 +- .../src/syscrg/clk_wave420l_vce.rs | 18 +- .../src/syscrg/clk_wave511_apb.rs | 12 +- .../src/syscrg/clk_wave511_axi.rs | 12 +- .../src/syscrg/clk_wave511_bpu.rs | 18 +- .../src/syscrg/clk_wave511_jpg_arb.rs | 12 +- .../src/syscrg/clk_wave511_jpg_main.rs | 12 +- .../src/syscrg/clk_wave511_vce.rs | 18 +- jh7110-vf2-13b-pac/src/syscrg/clk_wdt.rs | 12 +- jh7110-vf2-13b-pac/src/syscrg/clk_wdt_apb.rs | 12 +- .../src/syscrg/soft_rst0_addr_sel.rs | 207 +- .../src/syscrg/soft_rst1_addr_sel.rs | 203 +- .../src/syscrg/soft_rst2_addr_sel.rs | 224 +- .../src/syscrg/soft_rst3_addr_sel.rs | 188 +- .../src/syscrg/syscrg_rst0_status.rs | 207 +- .../src/syscrg/syscrg_rst1_status.rs | 203 +- .../src/syscrg/syscrg_rst2_status.rs | 224 +- .../src/syscrg/syscrg_rst3_status.rs | 188 +- .../src/syscrg/u7mc_rtc_toggle.rs | 12 +- jh7110-vf2-13b-pac/src/trng.rs | 134 +- jh7110-vf2-13b-pac/src/trng/auto_age.rs | 12 +- jh7110-vf2-13b-pac/src/trng/auto_rqsts.rs | 12 +- jh7110-vf2-13b-pac/src/trng/ctrl.rs | 24 +- jh7110-vf2-13b-pac/src/trng/ie.rs | 30 +- jh7110-vf2-13b-pac/src/trng/istat.rs | 6 +- jh7110-vf2-13b-pac/src/trng/mode.rs | 12 +- jh7110-vf2-13b-pac/src/trng/rand0.rs | 6 +- jh7110-vf2-13b-pac/src/trng/rand1.rs | 6 +- jh7110-vf2-13b-pac/src/trng/rand2.rs | 6 +- jh7110-vf2-13b-pac/src/trng/rand3.rs | 6 +- jh7110-vf2-13b-pac/src/trng/rand4.rs | 6 +- jh7110-vf2-13b-pac/src/trng/rand5.rs | 6 +- jh7110-vf2-13b-pac/src/trng/rand6.rs | 6 +- jh7110-vf2-13b-pac/src/trng/rand7.rs | 6 +- jh7110-vf2-13b-pac/src/trng/smode.rs | 24 +- jh7110-vf2-13b-pac/src/trng/stat.rs | 6 +- jh7110-vf2-13b-pac/src/uart0.rs | 394 ++-- jh7110-vf2-13b-pac/src/uart0/cpr.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/ctr.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/dlh.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/dll.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/dmasa.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/far.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/fcr.rs | 42 +- jh7110-vf2-13b-pac/src/uart0/htx.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/ier.rs | 36 +- jh7110-vf2-13b-pac/src/uart0/iir.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/lcr.rs | 42 +- jh7110-vf2-13b-pac/src/uart0/lpdlh.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/lpdll.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/lsr.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/mcr.rs | 48 +- jh7110-vf2-13b-pac/src/uart0/msr.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/rbr.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/rfl.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/rfw.rs | 24 +- jh7110-vf2-13b-pac/src/uart0/sbcr.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/scr.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sdmam.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sfe.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/srbr0.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/srbr1.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/srbr10.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/srbr11.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/srbr12.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/srbr13.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/srbr14.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/srbr15.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/srbr2.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/srbr3.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/srbr4.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/srbr5.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/srbr6.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/srbr7.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/srbr8.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/srbr9.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/srr.rs | 24 +- jh7110-vf2-13b-pac/src/uart0/srt.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/srts.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/stet.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sthr0.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sthr1.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sthr10.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sthr11.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sthr12.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sthr13.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sthr14.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sthr15.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sthr2.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sthr3.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sthr4.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sthr5.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sthr6.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sthr7.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sthr8.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/sthr9.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/tfl.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/tfr.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/thr.rs | 12 +- jh7110-vf2-13b-pac/src/uart0/ucv.rs | 6 +- jh7110-vf2-13b-pac/src/uart0/usr.rs | 6 +- jh7110-vf2-13b-pac/src/uart1.rs | 394 ++-- jh7110-vf2-13b-pac/src/uart1/cpr.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/ctr.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/dlh.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/dll.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/dmasa.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/far.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/fcr.rs | 42 +- jh7110-vf2-13b-pac/src/uart1/htx.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/ier.rs | 36 +- jh7110-vf2-13b-pac/src/uart1/iir.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/lcr.rs | 42 +- jh7110-vf2-13b-pac/src/uart1/lpdlh.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/lpdll.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/lsr.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/mcr.rs | 48 +- jh7110-vf2-13b-pac/src/uart1/msr.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/rbr.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/rfl.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/rfw.rs | 24 +- jh7110-vf2-13b-pac/src/uart1/sbcr.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/scr.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sdmam.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sfe.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/srbr0.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/srbr1.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/srbr10.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/srbr11.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/srbr12.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/srbr13.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/srbr14.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/srbr15.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/srbr2.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/srbr3.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/srbr4.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/srbr5.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/srbr6.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/srbr7.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/srbr8.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/srbr9.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/srr.rs | 24 +- jh7110-vf2-13b-pac/src/uart1/srt.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/srts.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/stet.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sthr0.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sthr1.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sthr10.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sthr11.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sthr12.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sthr13.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sthr14.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sthr15.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sthr2.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sthr3.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sthr4.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sthr5.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sthr6.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sthr7.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sthr8.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/sthr9.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/tfl.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/tfr.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/thr.rs | 12 +- jh7110-vf2-13b-pac/src/uart1/ucv.rs | 6 +- jh7110-vf2-13b-pac/src/uart1/usr.rs | 6 +- jh7110-vf2-13b-pac/src/uart2.rs | 394 ++-- jh7110-vf2-13b-pac/src/uart2/cpr.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/ctr.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/dlh.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/dll.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/dmasa.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/far.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/fcr.rs | 42 +- jh7110-vf2-13b-pac/src/uart2/htx.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/ier.rs | 36 +- jh7110-vf2-13b-pac/src/uart2/iir.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/lcr.rs | 42 +- jh7110-vf2-13b-pac/src/uart2/lpdlh.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/lpdll.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/lsr.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/mcr.rs | 48 +- jh7110-vf2-13b-pac/src/uart2/msr.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/rbr.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/rfl.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/rfw.rs | 24 +- jh7110-vf2-13b-pac/src/uart2/sbcr.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/scr.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sdmam.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sfe.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/srbr0.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/srbr1.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/srbr10.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/srbr11.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/srbr12.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/srbr13.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/srbr14.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/srbr15.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/srbr2.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/srbr3.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/srbr4.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/srbr5.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/srbr6.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/srbr7.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/srbr8.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/srbr9.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/srr.rs | 24 +- jh7110-vf2-13b-pac/src/uart2/srt.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/srts.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/stet.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sthr0.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sthr1.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sthr10.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sthr11.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sthr12.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sthr13.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sthr14.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sthr15.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sthr2.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sthr3.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sthr4.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sthr5.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sthr6.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sthr7.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sthr8.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/sthr9.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/tfl.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/tfr.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/thr.rs | 12 +- jh7110-vf2-13b-pac/src/uart2/ucv.rs | 6 +- jh7110-vf2-13b-pac/src/uart2/usr.rs | 6 +- jh7110-vf2-13b-pac/src/uart3.rs | 394 ++-- jh7110-vf2-13b-pac/src/uart3/cpr.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/ctr.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/dlh.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/dll.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/dmasa.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/far.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/fcr.rs | 42 +- jh7110-vf2-13b-pac/src/uart3/htx.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/ier.rs | 36 +- jh7110-vf2-13b-pac/src/uart3/iir.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/lcr.rs | 42 +- jh7110-vf2-13b-pac/src/uart3/lpdlh.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/lpdll.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/lsr.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/mcr.rs | 48 +- jh7110-vf2-13b-pac/src/uart3/msr.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/rbr.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/rfl.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/rfw.rs | 24 +- jh7110-vf2-13b-pac/src/uart3/sbcr.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/scr.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sdmam.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sfe.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/srbr0.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/srbr1.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/srbr10.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/srbr11.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/srbr12.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/srbr13.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/srbr14.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/srbr15.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/srbr2.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/srbr3.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/srbr4.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/srbr5.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/srbr6.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/srbr7.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/srbr8.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/srbr9.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/srr.rs | 24 +- jh7110-vf2-13b-pac/src/uart3/srt.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/srts.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/stet.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sthr0.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sthr1.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sthr10.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sthr11.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sthr12.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sthr13.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sthr14.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sthr15.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sthr2.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sthr3.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sthr4.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sthr5.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sthr6.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sthr7.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sthr8.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/sthr9.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/tfl.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/tfr.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/thr.rs | 12 +- jh7110-vf2-13b-pac/src/uart3/ucv.rs | 6 +- jh7110-vf2-13b-pac/src/uart3/usr.rs | 6 +- jh7110-vf2-13b-pac/src/uart4.rs | 394 ++-- jh7110-vf2-13b-pac/src/uart4/cpr.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/ctr.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/dlh.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/dll.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/dmasa.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/far.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/fcr.rs | 42 +- jh7110-vf2-13b-pac/src/uart4/htx.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/ier.rs | 36 +- jh7110-vf2-13b-pac/src/uart4/iir.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/lcr.rs | 42 +- jh7110-vf2-13b-pac/src/uart4/lpdlh.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/lpdll.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/lsr.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/mcr.rs | 48 +- jh7110-vf2-13b-pac/src/uart4/msr.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/rbr.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/rfl.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/rfw.rs | 24 +- jh7110-vf2-13b-pac/src/uart4/sbcr.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/scr.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sdmam.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sfe.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/srbr0.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/srbr1.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/srbr10.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/srbr11.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/srbr12.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/srbr13.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/srbr14.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/srbr15.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/srbr2.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/srbr3.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/srbr4.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/srbr5.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/srbr6.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/srbr7.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/srbr8.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/srbr9.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/srr.rs | 24 +- jh7110-vf2-13b-pac/src/uart4/srt.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/srts.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/stet.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sthr0.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sthr1.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sthr10.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sthr11.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sthr12.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sthr13.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sthr14.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sthr15.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sthr2.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sthr3.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sthr4.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sthr5.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sthr6.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sthr7.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sthr8.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/sthr9.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/tfl.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/tfr.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/thr.rs | 12 +- jh7110-vf2-13b-pac/src/uart4/ucv.rs | 6 +- jh7110-vf2-13b-pac/src/uart4/usr.rs | 6 +- jh7110-vf2-13b-pac/src/uart5.rs | 394 ++-- jh7110-vf2-13b-pac/src/uart5/cpr.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/ctr.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/dlh.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/dll.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/dmasa.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/far.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/fcr.rs | 42 +- jh7110-vf2-13b-pac/src/uart5/htx.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/ier.rs | 36 +- jh7110-vf2-13b-pac/src/uart5/iir.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/lcr.rs | 42 +- jh7110-vf2-13b-pac/src/uart5/lpdlh.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/lpdll.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/lsr.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/mcr.rs | 48 +- jh7110-vf2-13b-pac/src/uart5/msr.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/rbr.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/rfl.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/rfw.rs | 24 +- jh7110-vf2-13b-pac/src/uart5/sbcr.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/scr.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sdmam.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sfe.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/srbr0.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/srbr1.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/srbr10.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/srbr11.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/srbr12.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/srbr13.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/srbr14.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/srbr15.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/srbr2.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/srbr3.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/srbr4.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/srbr5.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/srbr6.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/srbr7.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/srbr8.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/srbr9.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/srr.rs | 24 +- jh7110-vf2-13b-pac/src/uart5/srt.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/srts.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/stet.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sthr0.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sthr1.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sthr10.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sthr11.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sthr12.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sthr13.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sthr14.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sthr15.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sthr2.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sthr3.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sthr4.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sthr5.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sthr6.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sthr7.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sthr8.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/sthr9.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/tfl.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/tfr.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/thr.rs | 12 +- jh7110-vf2-13b-pac/src/uart5/ucv.rs | 6 +- jh7110-vf2-13b-pac/src/uart5/usr.rs | 6 +- 3600 files changed, 57103 insertions(+), 31944 deletions(-) diff --git a/jh7110-vf2-12a-pac/Cargo.toml b/jh7110-vf2-12a-pac/Cargo.toml index c285c39..ca38ccd 100644 --- a/jh7110-vf2-12a-pac/Cargo.toml +++ b/jh7110-vf2-12a-pac/Cargo.toml @@ -12,9 +12,14 @@ license = "GPL-3.0-only" [dependencies] critical-section = { version = "1.1.2", optional = true } riscv = "0.10.1" -riscv-rt = { version = "0.11.0", optional = true } vcell = "0.1.3" + +[dependencies.riscv-rt] +version = "0.11.0" +git = "https://github.com/rust-embedded/riscv-rt" +optional = true + [features] default = ["critical-section"] critical-section = ["dep:critical-section"] diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl.rs index 705b41d..665a4ad 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl.rs @@ -1,284 +1,426 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + aon_iomux_cfgsaif_syscfg_fmux0: AON_IOMUX_CFGSAIF_SYSCFG_FMUX0, + aon_iomux_cfgsaif_syscfg_fmux1: AON_IOMUX_CFGSAIF_SYSCFG_FMUX1, + aon_iomux_cfgsaif_syscfg_fmux2: AON_IOMUX_CFGSAIF_SYSCFG_FMUX2, + aon_iomux_cfgsaif_syscfg_fmux3: AON_IOMUX_CFGSAIF_SYSCFG_FMUX3, + aon_iomux_cfgsaif_syscfg_ioirq4: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4, + aon_iomux_cfgsaif_syscfg_ioirq5: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5, + aon_iomux_cfgsaif_syscfg_ioirq6: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6, + aon_iomux_cfgsaif_syscfg_ioirq7: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7, + aon_iomux_cfgsaif_syscfg_ioirq8: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8, + aon_iomux_cfgsaif_syscfg_ioirq9: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9, + aon_iomux_cfgsaif_syscfg_ioirq10: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10, + aon_iomux_cfgsaif_syscfg_ioirq11: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11, + aon_iomux_cfgsaif_syscfg48: AON_IOMUX_CFGSAIF_SYSCFG48, + aon_iomux_cfgsaif_syscfg52: AON_IOMUX_CFGSAIF_SYSCFG52, + aon_iomux_cfgsaif_syscfg56: AON_IOMUX_CFGSAIF_SYSCFG56, + aon_iomux_cfgsaif_syscfg60: AON_IOMUX_CFGSAIF_SYSCFG60, + aon_iomux_cfgsaif_syscfg64: AON_IOMUX_CFGSAIF_SYSCFG64, + aon_iomux_cfgsaif_syscfg68: AON_IOMUX_CFGSAIF_SYSCFG68, + _reserved18: [u8; 0x04], + aon_iomux_cfgsaif_syscfg76: AON_IOMUX_CFGSAIF_SYSCFG76, + _reserved19: [u8; 0x04], + aon_iomux_cfgsaif_syscfg84: AON_IOMUX_CFGSAIF_SYSCFG84, + aon_iomux_cfgsaif_syscfg88: AON_IOMUX_CFGSAIF_SYSCFG88, + aon_iomux_cfgsaif_syscfg92: AON_IOMUX_CFGSAIF_SYSCFG92, + aon_iomux_cfgsaif_syscfg96: AON_IOMUX_CFGSAIF_SYSCFG96, + aon_iomux_cfgsaif_syscfg100: AON_IOMUX_CFGSAIF_SYSCFG100, + aon_iomux_cfgsaif_syscfg104: AON_IOMUX_CFGSAIF_SYSCFG104, + aon_iomux_cfgsaif_syscfg108: AON_IOMUX_CFGSAIF_SYSCFG108, + aon_iomux_cfgsaif_syscfg112: AON_IOMUX_CFGSAIF_SYSCFG112, + aon_iomux_cfgsaif_syscfg116: AON_IOMUX_CFGSAIF_SYSCFG116, + aon_iomux_cfgsaif_syscfg120: AON_IOMUX_CFGSAIF_SYSCFG120, + aon_iomux_cfgsaif_syscfg124: AON_IOMUX_CFGSAIF_SYSCFG124, + aon_iomux_cfgsaif_syscfg128: AON_IOMUX_CFGSAIF_SYSCFG128, + aon_iomux_cfgsaif_syscfg132: AON_IOMUX_CFGSAIF_SYSCFG132, + aon_iomux_cfgsaif_syscfg136: AON_IOMUX_CFGSAIF_SYSCFG136, + aon_iomux_cfgsaif_syscfg140: AON_IOMUX_CFGSAIF_SYSCFG140, + aon_iomux_cfgsaif_syscfg144: AON_IOMUX_CFGSAIF_SYSCFG144, +} +impl RegisterBlock { #[doc = "0x00 - AON IOMUX CFG SAIF SYSCFG FMUX 0"] - pub aon_iomux_cfgsaif_syscfg_fmux0: AON_IOMUX_CFGSAIF_SYSCFG_FMUX0, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_fmux0(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_FMUX0 { + &self.aon_iomux_cfgsaif_syscfg_fmux0 + } #[doc = "0x04 - AON IOMUX CFG SAIF SYSCFG FMUX 1"] - pub aon_iomux_cfgsaif_syscfg_fmux1: AON_IOMUX_CFGSAIF_SYSCFG_FMUX1, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_fmux1(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_FMUX1 { + &self.aon_iomux_cfgsaif_syscfg_fmux1 + } #[doc = "0x08 - AON IOMUX CFG SAIF SYSCFG FMUX 2"] - pub aon_iomux_cfgsaif_syscfg_fmux2: AON_IOMUX_CFGSAIF_SYSCFG_FMUX2, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_fmux2(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_FMUX2 { + &self.aon_iomux_cfgsaif_syscfg_fmux2 + } #[doc = "0x0c - AON IOMUX CFG SAIF SYSCFG FMUX 3"] - pub aon_iomux_cfgsaif_syscfg_fmux3: AON_IOMUX_CFGSAIF_SYSCFG_FMUX3, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_fmux3(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_FMUX3 { + &self.aon_iomux_cfgsaif_syscfg_fmux3 + } #[doc = "0x10 - AON IOMUX CFG SAIF SYSCFG IOIRQ 4"] - pub aon_iomux_cfgsaif_syscfg_ioirq4: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_ioirq4(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4 { + &self.aon_iomux_cfgsaif_syscfg_ioirq4 + } #[doc = "0x14 - AON IOMUX CFG SAIF SYSCFG IOIRQ 5"] - pub aon_iomux_cfgsaif_syscfg_ioirq5: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_ioirq5(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5 { + &self.aon_iomux_cfgsaif_syscfg_ioirq5 + } #[doc = "0x18 - AON IOMUX CFG SAIF SYSCFG IOIRQ 6"] - pub aon_iomux_cfgsaif_syscfg_ioirq6: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_ioirq6(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6 { + &self.aon_iomux_cfgsaif_syscfg_ioirq6 + } #[doc = "0x1c - AON IOMUX CFG SAIF SYSCFG IOIRQ 7"] - pub aon_iomux_cfgsaif_syscfg_ioirq7: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_ioirq7(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7 { + &self.aon_iomux_cfgsaif_syscfg_ioirq7 + } #[doc = "0x20 - AON IOMUX CFG SAIF SYSCFG IOIRQ 8"] - pub aon_iomux_cfgsaif_syscfg_ioirq8: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_ioirq8(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8 { + &self.aon_iomux_cfgsaif_syscfg_ioirq8 + } #[doc = "0x24 - AON IOMUX CFG SAIF SYSCFG IOIRQ 9"] - pub aon_iomux_cfgsaif_syscfg_ioirq9: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_ioirq9(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9 { + &self.aon_iomux_cfgsaif_syscfg_ioirq9 + } #[doc = "0x28 - AON IOMUX CFG SAIF SYSCFG IOIRQ 10"] - pub aon_iomux_cfgsaif_syscfg_ioirq10: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_ioirq10(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10 { + &self.aon_iomux_cfgsaif_syscfg_ioirq10 + } #[doc = "0x2c - AON IOMUX CFG SAIF SYSCFG IOIRQ 11"] - pub aon_iomux_cfgsaif_syscfg_ioirq11: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_ioirq11(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11 { + &self.aon_iomux_cfgsaif_syscfg_ioirq11 + } #[doc = "0x30 - AON IOMUX CFG SAIF SYSCFG 48"] - pub aon_iomux_cfgsaif_syscfg48: AON_IOMUX_CFGSAIF_SYSCFG48, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg48(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG48 { + &self.aon_iomux_cfgsaif_syscfg48 + } #[doc = "0x34 - AON IOMUX CFG SAIF SYSCFG 52"] - pub aon_iomux_cfgsaif_syscfg52: AON_IOMUX_CFGSAIF_SYSCFG52, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg52(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG52 { + &self.aon_iomux_cfgsaif_syscfg52 + } #[doc = "0x38 - AON IOMUX CFG SAIF SYSCFG 56"] - pub aon_iomux_cfgsaif_syscfg56: AON_IOMUX_CFGSAIF_SYSCFG56, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg56(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG56 { + &self.aon_iomux_cfgsaif_syscfg56 + } #[doc = "0x3c - AON IOMUX CFG SAIF SYSCFG 60"] - pub aon_iomux_cfgsaif_syscfg60: AON_IOMUX_CFGSAIF_SYSCFG60, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg60(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG60 { + &self.aon_iomux_cfgsaif_syscfg60 + } #[doc = "0x40 - AON IOMUX CFG SAIF SYSCFG 64"] - pub aon_iomux_cfgsaif_syscfg64: AON_IOMUX_CFGSAIF_SYSCFG64, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg64(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG64 { + &self.aon_iomux_cfgsaif_syscfg64 + } #[doc = "0x44 - AON IOMUX CFG SAIF SYSCFG 68"] - pub aon_iomux_cfgsaif_syscfg68: AON_IOMUX_CFGSAIF_SYSCFG68, - _reserved18: [u8; 0x04], + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg68(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG68 { + &self.aon_iomux_cfgsaif_syscfg68 + } #[doc = "0x4c - AON IOMUX CFG SAIF SYSCFG 76"] - pub aon_iomux_cfgsaif_syscfg76: AON_IOMUX_CFGSAIF_SYSCFG76, - _reserved19: [u8; 0x04], + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg76(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG76 { + &self.aon_iomux_cfgsaif_syscfg76 + } #[doc = "0x54 - AON IOMUX CFG SAIF SYSCFG 84"] - pub aon_iomux_cfgsaif_syscfg84: AON_IOMUX_CFGSAIF_SYSCFG84, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg84(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG84 { + &self.aon_iomux_cfgsaif_syscfg84 + } #[doc = "0x58 - AON IOMUX CFG SAIF SYSCFG 88"] - pub aon_iomux_cfgsaif_syscfg88: AON_IOMUX_CFGSAIF_SYSCFG88, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg88(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG88 { + &self.aon_iomux_cfgsaif_syscfg88 + } #[doc = "0x5c - AON IOMUX CFG SAIF SYSCFG 92"] - pub aon_iomux_cfgsaif_syscfg92: AON_IOMUX_CFGSAIF_SYSCFG92, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg92(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG92 { + &self.aon_iomux_cfgsaif_syscfg92 + } #[doc = "0x60 - AON IOMUX CFG SAIF SYSCFG 96"] - pub aon_iomux_cfgsaif_syscfg96: AON_IOMUX_CFGSAIF_SYSCFG96, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg96(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG96 { + &self.aon_iomux_cfgsaif_syscfg96 + } #[doc = "0x64 - AON IOMUX CFG SAIF SYSCFG 100"] - pub aon_iomux_cfgsaif_syscfg100: AON_IOMUX_CFGSAIF_SYSCFG100, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg100(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG100 { + &self.aon_iomux_cfgsaif_syscfg100 + } #[doc = "0x68 - AON IOMUX CFG SAIF SYSCFG 104"] - pub aon_iomux_cfgsaif_syscfg104: AON_IOMUX_CFGSAIF_SYSCFG104, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg104(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG104 { + &self.aon_iomux_cfgsaif_syscfg104 + } #[doc = "0x6c - AON IOMUX CFG SAIF SYSCFG 108"] - pub aon_iomux_cfgsaif_syscfg108: AON_IOMUX_CFGSAIF_SYSCFG108, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg108(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG108 { + &self.aon_iomux_cfgsaif_syscfg108 + } #[doc = "0x70 - AON IOMUX CFG SAIF SYSCFG 112"] - pub aon_iomux_cfgsaif_syscfg112: AON_IOMUX_CFGSAIF_SYSCFG112, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg112(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG112 { + &self.aon_iomux_cfgsaif_syscfg112 + } #[doc = "0x74 - AON IOMUX CFG SAIF SYSCFG 116"] - pub aon_iomux_cfgsaif_syscfg116: AON_IOMUX_CFGSAIF_SYSCFG116, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg116(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG116 { + &self.aon_iomux_cfgsaif_syscfg116 + } #[doc = "0x78 - AON IOMUX CFG SAIF SYSCFG 120"] - pub aon_iomux_cfgsaif_syscfg120: AON_IOMUX_CFGSAIF_SYSCFG120, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg120(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG120 { + &self.aon_iomux_cfgsaif_syscfg120 + } #[doc = "0x7c - AON IOMUX CFG SAIF SYSCFG 124"] - pub aon_iomux_cfgsaif_syscfg124: AON_IOMUX_CFGSAIF_SYSCFG124, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg124(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG124 { + &self.aon_iomux_cfgsaif_syscfg124 + } #[doc = "0x80 - AON IOMUX CFG SAIF SYSCFG 128"] - pub aon_iomux_cfgsaif_syscfg128: AON_IOMUX_CFGSAIF_SYSCFG128, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg128(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG128 { + &self.aon_iomux_cfgsaif_syscfg128 + } #[doc = "0x84 - AON IOMUX CFG SAIF SYSCFG 132"] - pub aon_iomux_cfgsaif_syscfg132: AON_IOMUX_CFGSAIF_SYSCFG132, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg132(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG132 { + &self.aon_iomux_cfgsaif_syscfg132 + } #[doc = "0x88 - AON IOMUX CFG SAIF SYSCFG 136"] - pub aon_iomux_cfgsaif_syscfg136: AON_IOMUX_CFGSAIF_SYSCFG136, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg136(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG136 { + &self.aon_iomux_cfgsaif_syscfg136 + } #[doc = "0x8c - AON IOMUX CFG SAIF SYSCFG 140"] - pub aon_iomux_cfgsaif_syscfg140: AON_IOMUX_CFGSAIF_SYSCFG140, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg140(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG140 { + &self.aon_iomux_cfgsaif_syscfg140 + } #[doc = "0x90 - AON IOMUX CFG SAIF SYSCFG 144"] - pub aon_iomux_cfgsaif_syscfg144: AON_IOMUX_CFGSAIF_SYSCFG144, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg144(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG144 { + &self.aon_iomux_cfgsaif_syscfg144 + } } -#[doc = "aon_iomux_cfgsaif_syscfg_fmux0 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_fmux0`] +#[doc = "aon_iomux_cfgsaif_syscfg_fmux0 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_fmux0`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_FMUX0 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 0"] pub mod aon_iomux_cfgsaif_syscfg_fmux0; -#[doc = "aon_iomux_cfgsaif_syscfg_fmux1 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_fmux1`] +#[doc = "aon_iomux_cfgsaif_syscfg_fmux1 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_fmux1`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_FMUX1 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 1"] pub mod aon_iomux_cfgsaif_syscfg_fmux1; -#[doc = "aon_iomux_cfgsaif_syscfg_fmux2 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_fmux2`] +#[doc = "aon_iomux_cfgsaif_syscfg_fmux2 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_fmux2`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_FMUX2 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 2"] pub mod aon_iomux_cfgsaif_syscfg_fmux2; -#[doc = "aon_iomux_cfgsaif_syscfg_fmux3 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_fmux3`] +#[doc = "aon_iomux_cfgsaif_syscfg_fmux3 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_fmux3`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_FMUX3 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 3"] pub mod aon_iomux_cfgsaif_syscfg_fmux3; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq4 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_ioirq4`] +#[doc = "aon_iomux_cfgsaif_syscfg_ioirq4 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq4`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 4"] pub mod aon_iomux_cfgsaif_syscfg_ioirq4; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq5 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_ioirq5`] +#[doc = "aon_iomux_cfgsaif_syscfg_ioirq5 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq5`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 5"] pub mod aon_iomux_cfgsaif_syscfg_ioirq5; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq6 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq6::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_ioirq6`] +#[doc = "aon_iomux_cfgsaif_syscfg_ioirq6 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq6::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq6`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 6"] pub mod aon_iomux_cfgsaif_syscfg_ioirq6; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq7 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq7::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_ioirq7`] +#[doc = "aon_iomux_cfgsaif_syscfg_ioirq7 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq7::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq7`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 7"] pub mod aon_iomux_cfgsaif_syscfg_ioirq7; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq8 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_ioirq8`] +#[doc = "aon_iomux_cfgsaif_syscfg_ioirq8 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq8`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 8"] pub mod aon_iomux_cfgsaif_syscfg_ioirq8; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq9 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq9::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_ioirq9`] +#[doc = "aon_iomux_cfgsaif_syscfg_ioirq9 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq9::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq9`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 9"] pub mod aon_iomux_cfgsaif_syscfg_ioirq9; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq10 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq10::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_ioirq10`] +#[doc = "aon_iomux_cfgsaif_syscfg_ioirq10 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq10::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq10`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 10"] pub mod aon_iomux_cfgsaif_syscfg_ioirq10; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq11 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq11::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_ioirq11`] +#[doc = "aon_iomux_cfgsaif_syscfg_ioirq11 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq11::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq11`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 11"] pub mod aon_iomux_cfgsaif_syscfg_ioirq11; -#[doc = "aon_iomux_cfgsaif_syscfg48 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg48`] +#[doc = "aon_iomux_cfgsaif_syscfg48 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg48`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG48 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 48"] pub mod aon_iomux_cfgsaif_syscfg48; -#[doc = "aon_iomux_cfgsaif_syscfg52 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg52`] +#[doc = "aon_iomux_cfgsaif_syscfg52 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg52`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG52 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 52"] pub mod aon_iomux_cfgsaif_syscfg52; -#[doc = "aon_iomux_cfgsaif_syscfg56 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg56`] +#[doc = "aon_iomux_cfgsaif_syscfg56 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg56`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG56 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 56"] pub mod aon_iomux_cfgsaif_syscfg56; -#[doc = "aon_iomux_cfgsaif_syscfg60 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg60`] +#[doc = "aon_iomux_cfgsaif_syscfg60 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg60`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG60 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 60"] pub mod aon_iomux_cfgsaif_syscfg60; -#[doc = "aon_iomux_cfgsaif_syscfg64 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg64`] +#[doc = "aon_iomux_cfgsaif_syscfg64 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg64`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG64 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 64"] pub mod aon_iomux_cfgsaif_syscfg64; -#[doc = "aon_iomux_cfgsaif_syscfg68 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg68`] +#[doc = "aon_iomux_cfgsaif_syscfg68 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg68`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG68 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 68"] pub mod aon_iomux_cfgsaif_syscfg68; -#[doc = "aon_iomux_cfgsaif_syscfg76 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg76`] +#[doc = "aon_iomux_cfgsaif_syscfg76 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg76`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG76 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 76"] pub mod aon_iomux_cfgsaif_syscfg76; -#[doc = "aon_iomux_cfgsaif_syscfg84 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg84`] +#[doc = "aon_iomux_cfgsaif_syscfg84 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg84`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG84 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 84"] pub mod aon_iomux_cfgsaif_syscfg84; -#[doc = "aon_iomux_cfgsaif_syscfg88 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg88`] +#[doc = "aon_iomux_cfgsaif_syscfg88 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg88`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG88 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 88"] pub mod aon_iomux_cfgsaif_syscfg88; -#[doc = "aon_iomux_cfgsaif_syscfg92 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg92`] +#[doc = "aon_iomux_cfgsaif_syscfg92 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg92`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG92 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 92"] pub mod aon_iomux_cfgsaif_syscfg92; -#[doc = "aon_iomux_cfgsaif_syscfg96 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg96`] +#[doc = "aon_iomux_cfgsaif_syscfg96 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg96`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG96 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 96"] pub mod aon_iomux_cfgsaif_syscfg96; -#[doc = "aon_iomux_cfgsaif_syscfg100 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg100`] +#[doc = "aon_iomux_cfgsaif_syscfg100 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg100`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG100 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 100"] pub mod aon_iomux_cfgsaif_syscfg100; -#[doc = "aon_iomux_cfgsaif_syscfg104 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg104`] +#[doc = "aon_iomux_cfgsaif_syscfg104 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg104`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG104 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 104"] pub mod aon_iomux_cfgsaif_syscfg104; -#[doc = "aon_iomux_cfgsaif_syscfg108 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg108`] +#[doc = "aon_iomux_cfgsaif_syscfg108 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg108`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG108 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 108"] pub mod aon_iomux_cfgsaif_syscfg108; -#[doc = "aon_iomux_cfgsaif_syscfg112 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg112`] +#[doc = "aon_iomux_cfgsaif_syscfg112 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg112`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG112 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 112"] pub mod aon_iomux_cfgsaif_syscfg112; -#[doc = "aon_iomux_cfgsaif_syscfg116 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg116`] +#[doc = "aon_iomux_cfgsaif_syscfg116 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg116`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG116 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 116"] pub mod aon_iomux_cfgsaif_syscfg116; -#[doc = "aon_iomux_cfgsaif_syscfg120 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg120`] +#[doc = "aon_iomux_cfgsaif_syscfg120 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg120`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG120 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 120"] pub mod aon_iomux_cfgsaif_syscfg120; -#[doc = "aon_iomux_cfgsaif_syscfg124 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg124`] +#[doc = "aon_iomux_cfgsaif_syscfg124 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg124`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG124 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 124"] pub mod aon_iomux_cfgsaif_syscfg124; -#[doc = "aon_iomux_cfgsaif_syscfg128 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg128`] +#[doc = "aon_iomux_cfgsaif_syscfg128 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg128`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG128 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 128"] pub mod aon_iomux_cfgsaif_syscfg128; -#[doc = "aon_iomux_cfgsaif_syscfg132 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg132::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg132::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg132`] +#[doc = "aon_iomux_cfgsaif_syscfg132 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg132::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg132::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg132`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG132 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 132"] pub mod aon_iomux_cfgsaif_syscfg132; -#[doc = "aon_iomux_cfgsaif_syscfg136 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg136`] +#[doc = "aon_iomux_cfgsaif_syscfg136 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg136`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG136 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 136"] pub mod aon_iomux_cfgsaif_syscfg136; -#[doc = "aon_iomux_cfgsaif_syscfg140 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg140::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg140::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg140`] +#[doc = "aon_iomux_cfgsaif_syscfg140 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg140::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg140::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg140`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG140 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 140"] pub mod aon_iomux_cfgsaif_syscfg140; -#[doc = "aon_iomux_cfgsaif_syscfg144 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg144::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg144::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg144`] +#[doc = "aon_iomux_cfgsaif_syscfg144 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg144::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg144::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg144`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG144 = crate::Reg; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg100.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg100.rs index cc40d71..7a6eb49 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg100.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg100.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_rxd1_syscon` reader - padcfg_pad_gmac0_rxd1_syscon"] pub type PADCFG_PAD_GMAC0_RXD1_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_rxd1_syscon` writer - padcfg_pad_gmac0_rxd1_syscon"] -pub type PADCFG_PAD_GMAC0_RXD1_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_RXD1_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd1_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_rxd1_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_RXD1_SYSCON_W { - PADCFG_PAD_GMAC0_RXD1_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_RXD1_SYSCON_W { + PADCFG_PAD_GMAC0_RXD1_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg104.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg104.rs index 708564a..c7f5618 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg104.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg104.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_rxd2_syscon` reader - padcfg_pad_gmac0_rxd2_syscon"] pub type PADCFG_PAD_GMAC0_RXD2_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_rxd2_syscon` writer - padcfg_pad_gmac0_rxd2_syscon"] -pub type PADCFG_PAD_GMAC0_RXD2_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_RXD2_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd2_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_rxd2_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_RXD2_SYSCON_W { - PADCFG_PAD_GMAC0_RXD2_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_RXD2_SYSCON_W { + PADCFG_PAD_GMAC0_RXD2_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg108.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg108.rs index 1498c6f..31aaf9e 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg108.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg108.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_rxd3_syscon` reader - padcfg_pad_gmac0_rxd3_syscon"] pub type PADCFG_PAD_GMAC0_RXD3_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_rxd3_syscon` writer - padcfg_pad_gmac0_rxd3_syscon"] -pub type PADCFG_PAD_GMAC0_RXD3_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_RXD3_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd3_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_rxd3_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_RXD3_SYSCON_W { - PADCFG_PAD_GMAC0_RXD3_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_RXD3_SYSCON_W { + PADCFG_PAD_GMAC0_RXD3_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg112.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg112.rs index db26577..7b68d46 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg112.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg112.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_rxdv_syscon` reader - padcfg_pad_gmac0_rxdv_syscon"] pub type PADCFG_PAD_GMAC0_RXDV_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_rxdv_syscon` writer - padcfg_pad_gmac0_rxdv_syscon"] -pub type PADCFG_PAD_GMAC0_RXDV_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_RXDV_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxdv_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_rxdv_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_RXDV_SYSCON_W { - PADCFG_PAD_GMAC0_RXDV_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_RXDV_SYSCON_W { + PADCFG_PAD_GMAC0_RXDV_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg116.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg116.rs index 76cd0ed..5a9c872 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg116.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg116.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_rxc_syscon` reader - padcfg_pad_gmac0_rxc_syscon"] pub type PADCFG_PAD_GMAC0_RXC_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_rxc_syscon` writer - padcfg_pad_gmac0_rxc_syscon"] -pub type PADCFG_PAD_GMAC0_RXC_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_RXC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxc_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_rxc_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_RXC_SYSCON_W { - PADCFG_PAD_GMAC0_RXC_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_RXC_SYSCON_W { + PADCFG_PAD_GMAC0_RXC_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg120.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg120.rs index f0a90d5..71a2e97 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg120.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg120.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_txd0_syscon` reader - padcfg_pad_gmac0_txd0_syscon"] pub type PADCFG_PAD_GMAC0_TXD0_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_txd0_syscon` writer - padcfg_pad_gmac0_txd0_syscon"] -pub type PADCFG_PAD_GMAC0_TXD0_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_TXD0_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd0_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_txd0_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_TXD0_SYSCON_W { - PADCFG_PAD_GMAC0_TXD0_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_TXD0_SYSCON_W { + PADCFG_PAD_GMAC0_TXD0_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg124.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg124.rs index 475164a..dda00ba 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg124.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg124.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_txd1_syscon` reader - padcfg_pad_gmac0_txd1_syscon"] pub type PADCFG_PAD_GMAC0_TXD1_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_txd1_syscon` writer - padcfg_pad_gmac0_txd1_syscon"] -pub type PADCFG_PAD_GMAC0_TXD1_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_TXD1_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd1_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_txd1_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_TXD1_SYSCON_W { - PADCFG_PAD_GMAC0_TXD1_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_TXD1_SYSCON_W { + PADCFG_PAD_GMAC0_TXD1_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg128.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg128.rs index 4ae5c62..18bc4c0 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg128.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg128.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_txd2_syscon` reader - padcfg_pad_gmac0_txd2_syscon"] pub type PADCFG_PAD_GMAC0_TXD2_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_txd2_syscon` writer - padcfg_pad_gmac0_txd2_syscon"] -pub type PADCFG_PAD_GMAC0_TXD2_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_TXD2_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd2_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_txd2_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_TXD2_SYSCON_W { - PADCFG_PAD_GMAC0_TXD2_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_TXD2_SYSCON_W { + PADCFG_PAD_GMAC0_TXD2_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg132.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg132.rs index 403cd3e..b8888c2 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg132.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg132.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_txd3_syscon` reader - padcfg_pad_gmac0_txd3_syscon"] pub type PADCFG_PAD_GMAC0_TXD3_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_txd3_syscon` writer - padcfg_pad_gmac0_txd3_syscon"] -pub type PADCFG_PAD_GMAC0_TXD3_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_TXD3_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd3_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_txd3_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_TXD3_SYSCON_W { - PADCFG_PAD_GMAC0_TXD3_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_TXD3_SYSCON_W { + PADCFG_PAD_GMAC0_TXD3_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg136.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg136.rs index 157b06f..1423c0e 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg136.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg136.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_txen_syscon` reader - padcfg_pad_gmac0_txen_syscon"] pub type PADCFG_PAD_GMAC0_TXEN_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_txen_syscon` writer - padcfg_pad_gmac0_txen_syscon"] -pub type PADCFG_PAD_GMAC0_TXEN_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_TXEN_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_txen_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_txen_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_TXEN_SYSCON_W { - PADCFG_PAD_GMAC0_TXEN_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_TXEN_SYSCON_W { + PADCFG_PAD_GMAC0_TXEN_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg140.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg140.rs index 1986c87..3328694 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg140.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg140.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_txc_syscon` reader - padcfg_pad_gmac0_txc_syscon"] pub type PADCFG_PAD_GMAC0_TXC_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_txc_syscon` writer - padcfg_pad_gmac0_txc_syscon"] -pub type PADCFG_PAD_GMAC0_TXC_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_TXC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_txc_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_txc_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_TXC_SYSCON_W { - PADCFG_PAD_GMAC0_TXC_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_TXC_SYSCON_W { + PADCFG_PAD_GMAC0_TXC_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg144.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg144.rs index 6db0a97..4e9cfe6 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg144.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg144.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `pad_gmac0_rxc_func_sel` reader - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] pub type PAD_GMAC0_RXC_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gmac0_rxc_func_sel` writer - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] -pub type PAD_GMAC0_RXC_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PAD_GMAC0_RXC_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn pad_gmac0_rxc_func_sel( &mut self, - ) -> PAD_GMAC0_RXC_FUNC_SEL_W { - PAD_GMAC0_RXC_FUNC_SEL_W::new(self) + ) -> PAD_GMAC0_RXC_FUNC_SEL_W { + PAD_GMAC0_RXC_FUNC_SEL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs index b321542..6e37db2 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_testen_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type PADCFG_PAD_TESTEN_POS_R = crate::BitReader; #[doc = "Field `padcfg_pad_testen_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_TESTEN_POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_TESTEN_POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_testen_pos( &mut self, - ) -> PADCFG_PAD_TESTEN_POS_W { - PADCFG_PAD_TESTEN_POS_W::new(self) + ) -> PADCFG_PAD_TESTEN_POS_W { + PADCFG_PAD_TESTEN_POS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs index 8ef1a98..e6eee84 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_rgpio0_ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type PADCFG_PAD_RGPIO0_IE_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio0_ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO0_IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO0_IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio0_ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type PADCFG_PAD_RGPIO0_DS_R = crate::FieldReader; #[doc = "Field `padcfg_pad_rgpio0_ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO0_DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_RGPIO0_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `padcfg_pad_rgpio0_pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PADCFG_PAD_RGPIO0_PU_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio0_pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO0_PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO0_PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio0_pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PADCFG_PAD_RGPIO0_PD_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio0_pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO0_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO0_PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio0_slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type PADCFG_PAD_RGPIO0_SLEW_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio0_slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO0_SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO0_SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio0_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type PADCFG_PAD_RGPIO0_SMT_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio0_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO0_SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO0_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio0_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type PADCFG_PAD_RGPIO0_POS_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio0_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO0_POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO0_POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -73,58 +73,62 @@ impl W { #[must_use] pub fn padcfg_pad_rgpio0_ie( &mut self, - ) -> PADCFG_PAD_RGPIO0_IE_W { - PADCFG_PAD_RGPIO0_IE_W::new(self) + ) -> PADCFG_PAD_RGPIO0_IE_W { + PADCFG_PAD_RGPIO0_IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio0_ds( &mut self, - ) -> PADCFG_PAD_RGPIO0_DS_W { - PADCFG_PAD_RGPIO0_DS_W::new(self) + ) -> PADCFG_PAD_RGPIO0_DS_W { + PADCFG_PAD_RGPIO0_DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio0_pu( &mut self, - ) -> PADCFG_PAD_RGPIO0_PU_W { - PADCFG_PAD_RGPIO0_PU_W::new(self) + ) -> PADCFG_PAD_RGPIO0_PU_W { + PADCFG_PAD_RGPIO0_PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio0_pd( &mut self, - ) -> PADCFG_PAD_RGPIO0_PD_W { - PADCFG_PAD_RGPIO0_PD_W::new(self) + ) -> PADCFG_PAD_RGPIO0_PD_W { + PADCFG_PAD_RGPIO0_PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio0_slew( &mut self, - ) -> PADCFG_PAD_RGPIO0_SLEW_W { - PADCFG_PAD_RGPIO0_SLEW_W::new(self) + ) -> PADCFG_PAD_RGPIO0_SLEW_W { + PADCFG_PAD_RGPIO0_SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio0_smt( &mut self, - ) -> PADCFG_PAD_RGPIO0_SMT_W { - PADCFG_PAD_RGPIO0_SMT_W::new(self) + ) -> PADCFG_PAD_RGPIO0_SMT_W { + PADCFG_PAD_RGPIO0_SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio0_pos( &mut self, - ) -> PADCFG_PAD_RGPIO0_POS_W { - PADCFG_PAD_RGPIO0_POS_W::new(self) + ) -> PADCFG_PAD_RGPIO0_POS_W { + PADCFG_PAD_RGPIO0_POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs index 47270f1..e4df2d1 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_rgpio1_ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type PADCFG_PAD_RGPIO1_IE_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio1_ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO1_IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO1_IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio1_ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type PADCFG_PAD_RGPIO1_DS_R = crate::FieldReader; #[doc = "Field `padcfg_pad_rgpio1_ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO1_DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_RGPIO1_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `padcfg_pad_rgpio1_pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PADCFG_PAD_RGPIO1_PU_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio1_pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO1_PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO1_PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio1_pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PADCFG_PAD_RGPIO1_PD_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio1_pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO1_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO1_PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio1_slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type PADCFG_PAD_RGPIO1_SLEW_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio1_slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO1_SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO1_SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio1_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type PADCFG_PAD_RGPIO1_SMT_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio1_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO1_SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO1_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio1_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type PADCFG_PAD_RGPIO1_POS_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio1_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO1_POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO1_POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -73,58 +73,62 @@ impl W { #[must_use] pub fn padcfg_pad_rgpio1_ie( &mut self, - ) -> PADCFG_PAD_RGPIO1_IE_W { - PADCFG_PAD_RGPIO1_IE_W::new(self) + ) -> PADCFG_PAD_RGPIO1_IE_W { + PADCFG_PAD_RGPIO1_IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio1_ds( &mut self, - ) -> PADCFG_PAD_RGPIO1_DS_W { - PADCFG_PAD_RGPIO1_DS_W::new(self) + ) -> PADCFG_PAD_RGPIO1_DS_W { + PADCFG_PAD_RGPIO1_DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio1_pu( &mut self, - ) -> PADCFG_PAD_RGPIO1_PU_W { - PADCFG_PAD_RGPIO1_PU_W::new(self) + ) -> PADCFG_PAD_RGPIO1_PU_W { + PADCFG_PAD_RGPIO1_PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio1_pd( &mut self, - ) -> PADCFG_PAD_RGPIO1_PD_W { - PADCFG_PAD_RGPIO1_PD_W::new(self) + ) -> PADCFG_PAD_RGPIO1_PD_W { + PADCFG_PAD_RGPIO1_PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio1_slew( &mut self, - ) -> PADCFG_PAD_RGPIO1_SLEW_W { - PADCFG_PAD_RGPIO1_SLEW_W::new(self) + ) -> PADCFG_PAD_RGPIO1_SLEW_W { + PADCFG_PAD_RGPIO1_SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio1_smt( &mut self, - ) -> PADCFG_PAD_RGPIO1_SMT_W { - PADCFG_PAD_RGPIO1_SMT_W::new(self) + ) -> PADCFG_PAD_RGPIO1_SMT_W { + PADCFG_PAD_RGPIO1_SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio1_pos( &mut self, - ) -> PADCFG_PAD_RGPIO1_POS_W { - PADCFG_PAD_RGPIO1_POS_W::new(self) + ) -> PADCFG_PAD_RGPIO1_POS_W { + PADCFG_PAD_RGPIO1_POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs index 0017ce6..5a6586e 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_rgpio2_ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type PADCFG_PAD_RGPIO2_IE_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio2_ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO2_IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO2_IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio2_ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type PADCFG_PAD_RGPIO2_DS_R = crate::FieldReader; #[doc = "Field `padcfg_pad_rgpio2_ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO2_DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_RGPIO2_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `padcfg_pad_rgpio2_pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PADCFG_PAD_RGPIO2_PU_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio2_pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO2_PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO2_PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio2_pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PADCFG_PAD_RGPIO2_PD_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio2_pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO2_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO2_PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio2_slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type PADCFG_PAD_RGPIO2_SLEW_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio2_slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO2_SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO2_SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio2_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type PADCFG_PAD_RGPIO2_SMT_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio2_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO2_SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO2_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio2_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type PADCFG_PAD_RGPIO2_POS_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio2_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO2_POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO2_POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -73,58 +73,62 @@ impl W { #[must_use] pub fn padcfg_pad_rgpio2_ie( &mut self, - ) -> PADCFG_PAD_RGPIO2_IE_W { - PADCFG_PAD_RGPIO2_IE_W::new(self) + ) -> PADCFG_PAD_RGPIO2_IE_W { + PADCFG_PAD_RGPIO2_IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio2_ds( &mut self, - ) -> PADCFG_PAD_RGPIO2_DS_W { - PADCFG_PAD_RGPIO2_DS_W::new(self) + ) -> PADCFG_PAD_RGPIO2_DS_W { + PADCFG_PAD_RGPIO2_DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio2_pu( &mut self, - ) -> PADCFG_PAD_RGPIO2_PU_W { - PADCFG_PAD_RGPIO2_PU_W::new(self) + ) -> PADCFG_PAD_RGPIO2_PU_W { + PADCFG_PAD_RGPIO2_PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio2_pd( &mut self, - ) -> PADCFG_PAD_RGPIO2_PD_W { - PADCFG_PAD_RGPIO2_PD_W::new(self) + ) -> PADCFG_PAD_RGPIO2_PD_W { + PADCFG_PAD_RGPIO2_PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio2_slew( &mut self, - ) -> PADCFG_PAD_RGPIO2_SLEW_W { - PADCFG_PAD_RGPIO2_SLEW_W::new(self) + ) -> PADCFG_PAD_RGPIO2_SLEW_W { + PADCFG_PAD_RGPIO2_SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio2_smt( &mut self, - ) -> PADCFG_PAD_RGPIO2_SMT_W { - PADCFG_PAD_RGPIO2_SMT_W::new(self) + ) -> PADCFG_PAD_RGPIO2_SMT_W { + PADCFG_PAD_RGPIO2_SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio2_pos( &mut self, - ) -> PADCFG_PAD_RGPIO2_POS_W { - PADCFG_PAD_RGPIO2_POS_W::new(self) + ) -> PADCFG_PAD_RGPIO2_POS_W { + PADCFG_PAD_RGPIO2_POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs index 9c5e498..8dfbee5 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_rgpio3_ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type PADCFG_PAD_RGPIO3_IE_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio3_ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO3_IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO3_IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio3_ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type PADCFG_PAD_RGPIO3_DS_R = crate::FieldReader; #[doc = "Field `padcfg_pad_rgpio3_ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO3_DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_RGPIO3_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `padcfg_pad_rgpio3_pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PADCFG_PAD_RGPIO3_PU_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio3_pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO3_PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO3_PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio3_pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PADCFG_PAD_RGPIO3_PD_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio3_pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO3_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO3_PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio3_slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type PADCFG_PAD_RGPIO3_SLEW_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio3_slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO3_SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO3_SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio3_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type PADCFG_PAD_RGPIO3_SMT_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio3_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO3_SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO3_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio3_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type PADCFG_PAD_RGPIO3_POS_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio3_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO3_POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO3_POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -73,58 +73,62 @@ impl W { #[must_use] pub fn padcfg_pad_rgpio3_ie( &mut self, - ) -> PADCFG_PAD_RGPIO3_IE_W { - PADCFG_PAD_RGPIO3_IE_W::new(self) + ) -> PADCFG_PAD_RGPIO3_IE_W { + PADCFG_PAD_RGPIO3_IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio3_ds( &mut self, - ) -> PADCFG_PAD_RGPIO3_DS_W { - PADCFG_PAD_RGPIO3_DS_W::new(self) + ) -> PADCFG_PAD_RGPIO3_DS_W { + PADCFG_PAD_RGPIO3_DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio3_pu( &mut self, - ) -> PADCFG_PAD_RGPIO3_PU_W { - PADCFG_PAD_RGPIO3_PU_W::new(self) + ) -> PADCFG_PAD_RGPIO3_PU_W { + PADCFG_PAD_RGPIO3_PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio3_pd( &mut self, - ) -> PADCFG_PAD_RGPIO3_PD_W { - PADCFG_PAD_RGPIO3_PD_W::new(self) + ) -> PADCFG_PAD_RGPIO3_PD_W { + PADCFG_PAD_RGPIO3_PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio3_slew( &mut self, - ) -> PADCFG_PAD_RGPIO3_SLEW_W { - PADCFG_PAD_RGPIO3_SLEW_W::new(self) + ) -> PADCFG_PAD_RGPIO3_SLEW_W { + PADCFG_PAD_RGPIO3_SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio3_smt( &mut self, - ) -> PADCFG_PAD_RGPIO3_SMT_W { - PADCFG_PAD_RGPIO3_SMT_W::new(self) + ) -> PADCFG_PAD_RGPIO3_SMT_W { + PADCFG_PAD_RGPIO3_SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio3_pos( &mut self, - ) -> PADCFG_PAD_RGPIO3_POS_W { - PADCFG_PAD_RGPIO3_POS_W::new(self) + ) -> PADCFG_PAD_RGPIO3_POS_W { + PADCFG_PAD_RGPIO3_POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs index aee1a8b..6c5a65b 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_rstn_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] pub type PADCFG_PAD_RSTN_SMT_R = crate::BitReader; #[doc = "Field `padcfg_pad_rstn_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] -pub type PADCFG_PAD_RSTN_SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RSTN_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rstn_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] pub type PADCFG_PAD_RSTN_POS_R = crate::BitReader; #[doc = "Field `padcfg_pad_rstn_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RSTN_POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RSTN_POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] #[inline(always)] @@ -28,18 +28,22 @@ impl W { #[must_use] pub fn padcfg_pad_rstn_smt( &mut self, - ) -> PADCFG_PAD_RSTN_SMT_W { - PADCFG_PAD_RSTN_SMT_W::new(self) + ) -> PADCFG_PAD_RSTN_SMT_W { + PADCFG_PAD_RSTN_SMT_W::new(self, 0) } #[doc = "Bit 1 - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rstn_pos( &mut self, - ) -> PADCFG_PAD_RSTN_POS_W { - PADCFG_PAD_RSTN_POS_W::new(self) + ) -> PADCFG_PAD_RSTN_POS_W { + PADCFG_PAD_RSTN_POS_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs index b528e85..452613c 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_rtc_ds` reader - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] pub type PADCFG_PAD_RTC_DS_R = crate::FieldReader; #[doc = "Field `padcfg_pad_rtc_ds` writer - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] -pub type PADCFG_PAD_RTC_DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_RTC_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] #[inline(always)] #[must_use] - pub fn padcfg_pad_rtc_ds(&mut self) -> PADCFG_PAD_RTC_DS_W { - PADCFG_PAD_RTC_DS_W::new(self) + pub fn padcfg_pad_rtc_ds(&mut self) -> PADCFG_PAD_RTC_DS_W { + PADCFG_PAD_RTC_DS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs index 4a8e766..067aebb 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_osc_ds` reader - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] pub type PADCFG_PAD_OSC_DS_R = crate::FieldReader; #[doc = "Field `padcfg_pad_osc_ds` writer - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] -pub type PADCFG_PAD_OSC_DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_OSC_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] #[inline(always)] #[must_use] - pub fn padcfg_pad_osc_ds(&mut self) -> PADCFG_PAD_OSC_DS_W { - PADCFG_PAD_OSC_DS_W::new(self) + pub fn padcfg_pad_osc_ds(&mut self) -> PADCFG_PAD_OSC_DS_W { + PADCFG_PAD_OSC_DS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs index bf3a970..f744712 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_mdc_syscon` reader - padcfg_pad_gmac0_mdc_syscon"] pub type PADCFG_PAD_GMAC0_MDC_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_mdc_syscon` writer - padcfg_pad_gmac0_mdc_syscon"] -pub type PADCFG_PAD_GMAC0_MDC_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_MDC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_mdc_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_mdc_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_MDC_SYSCON_W { - PADCFG_PAD_GMAC0_MDC_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_MDC_SYSCON_W { + PADCFG_PAD_GMAC0_MDC_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs index 2e1d110..fd12b7e 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_mdio_syscon` reader - padcfg_pad_gmac0_mdio_syscon"] pub type PADCFG_PAD_GMAC0_MDIO_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_mdio_syscon` writer - padcfg_pad_gmac0_mdio_syscon"] -pub type PADCFG_PAD_GMAC0_MDIO_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_MDIO_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_mdio_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_mdio_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_MDIO_SYSCON_W { - PADCFG_PAD_GMAC0_MDIO_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_MDIO_SYSCON_W { + PADCFG_PAD_GMAC0_MDIO_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs index ba8ef45..3f8dabd 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_rxd0_syscon` reader - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] pub type PADCFG_PAD_GMAC0_RXD0_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_rxd0_syscon` writer - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] -pub type PADCFG_PAD_GMAC0_RXD0_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_RXD0_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_rxd0_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_RXD0_SYSCON_W { - PADCFG_PAD_GMAC0_RXD0_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_RXD0_SYSCON_W { + PADCFG_PAD_GMAC0_RXD0_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux0.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux0.rs index 731dd39..1bb9c0c 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux0.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux0.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `aon_iomux_gpo0_doen_cfg` reader - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] pub type AON_IOMUX_GPO0_DOEN_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpo0_doen_cfg` writer - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO0_DOEN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type AON_IOMUX_GPO0_DOEN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `aon_iomux_gpo1_doen_cfg` reader - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] pub type AON_IOMUX_GPO1_DOEN_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpo1_doen_cfg` writer - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO1_DOEN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type AON_IOMUX_GPO1_DOEN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `aon_iomux_gpo2_doen_cfg` reader - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] pub type AON_IOMUX_GPO2_DOEN_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpo2_doen_cfg` writer - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO2_DOEN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type AON_IOMUX_GPO2_DOEN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `aon_iomux_gpo3_doen_cfg` reader - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] pub type AON_IOMUX_GPO3_DOEN_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpo3_doen_cfg` writer - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO3_DOEN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type AON_IOMUX_GPO3_DOEN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:2 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] #[inline(always)] @@ -46,34 +46,38 @@ impl W { #[must_use] pub fn aon_iomux_gpo0_doen_cfg( &mut self, - ) -> AON_IOMUX_GPO0_DOEN_CFG_W { - AON_IOMUX_GPO0_DOEN_CFG_W::new(self) + ) -> AON_IOMUX_GPO0_DOEN_CFG_W { + AON_IOMUX_GPO0_DOEN_CFG_W::new(self, 0) } #[doc = "Bits 8:10 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] #[inline(always)] #[must_use] pub fn aon_iomux_gpo1_doen_cfg( &mut self, - ) -> AON_IOMUX_GPO1_DOEN_CFG_W { - AON_IOMUX_GPO1_DOEN_CFG_W::new(self) + ) -> AON_IOMUX_GPO1_DOEN_CFG_W { + AON_IOMUX_GPO1_DOEN_CFG_W::new(self, 8) } #[doc = "Bits 16:18 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] #[inline(always)] #[must_use] pub fn aon_iomux_gpo2_doen_cfg( &mut self, - ) -> AON_IOMUX_GPO2_DOEN_CFG_W { - AON_IOMUX_GPO2_DOEN_CFG_W::new(self) + ) -> AON_IOMUX_GPO2_DOEN_CFG_W { + AON_IOMUX_GPO2_DOEN_CFG_W::new(self, 16) } #[doc = "Bits 24:26 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] #[inline(always)] #[must_use] pub fn aon_iomux_gpo3_doen_cfg( &mut self, - ) -> AON_IOMUX_GPO3_DOEN_CFG_W { - AON_IOMUX_GPO3_DOEN_CFG_W::new(self) + ) -> AON_IOMUX_GPO3_DOEN_CFG_W { + AON_IOMUX_GPO3_DOEN_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux1.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux1.rs index 6b079d8..045b180 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux1.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `aon_iomux_gpo0_dout_cfg` reader - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] pub type AON_IOMUX_GPO0_DOUT_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpo0_dout_cfg` writer - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO0_DOUT_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_IOMUX_GPO0_DOUT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `aon_iomux_gpo1_dout_cfg` reader - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] pub type AON_IOMUX_GPO1_DOUT_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpo1_dout_cfg` writer - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO1_DOUT_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_IOMUX_GPO1_DOUT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `aon_iomux_gpo2_dout_cfg` reader - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] pub type AON_IOMUX_GPO2_DOUT_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpo2_dout_cfg` writer - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO2_DOUT_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_IOMUX_GPO2_DOUT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `aon_iomux_gpo3_dout_cfg` reader - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] pub type AON_IOMUX_GPO3_DOUT_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpo3_dout_cfg` writer - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO3_DOUT_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_IOMUX_GPO3_DOUT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] #[inline(always)] @@ -46,34 +46,38 @@ impl W { #[must_use] pub fn aon_iomux_gpo0_dout_cfg( &mut self, - ) -> AON_IOMUX_GPO0_DOUT_CFG_W { - AON_IOMUX_GPO0_DOUT_CFG_W::new(self) + ) -> AON_IOMUX_GPO0_DOUT_CFG_W { + AON_IOMUX_GPO0_DOUT_CFG_W::new(self, 0) } #[doc = "Bits 8:11 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] #[inline(always)] #[must_use] pub fn aon_iomux_gpo1_dout_cfg( &mut self, - ) -> AON_IOMUX_GPO1_DOUT_CFG_W { - AON_IOMUX_GPO1_DOUT_CFG_W::new(self) + ) -> AON_IOMUX_GPO1_DOUT_CFG_W { + AON_IOMUX_GPO1_DOUT_CFG_W::new(self, 8) } #[doc = "Bits 16:19 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] #[inline(always)] #[must_use] pub fn aon_iomux_gpo2_dout_cfg( &mut self, - ) -> AON_IOMUX_GPO2_DOUT_CFG_W { - AON_IOMUX_GPO2_DOUT_CFG_W::new(self) + ) -> AON_IOMUX_GPO2_DOUT_CFG_W { + AON_IOMUX_GPO2_DOUT_CFG_W::new(self, 16) } #[doc = "Bits 24:27 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] #[inline(always)] #[must_use] pub fn aon_iomux_gpo3_dout_cfg( &mut self, - ) -> AON_IOMUX_GPO3_DOUT_CFG_W { - AON_IOMUX_GPO3_DOUT_CFG_W::new(self) + ) -> AON_IOMUX_GPO3_DOUT_CFG_W { + AON_IOMUX_GPO3_DOUT_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux2.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux2.rs index efe3a61..a8f9ba4 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux2.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux2.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W<'a, REG> = + crate::FieldWriter<'a, REG, 3>; #[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W<'a, REG> = + crate::FieldWriter<'a, REG, 3>; #[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W<'a, REG> = + crate::FieldWriter<'a, REG, 3>; #[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W<'a, REG> = + crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:2 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -58,46 +58,42 @@ impl W { #[must_use] pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg( &mut self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W< - AON_IOMUX_CFGSAIF_SYSCFG_FMUX2_SPEC, - 0, - > { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W::new(self) + ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W + { + AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W::new(self, 0) } #[doc = "Bits 8:10 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg( &mut self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W< - AON_IOMUX_CFGSAIF_SYSCFG_FMUX2_SPEC, - 8, - > { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W::new(self) + ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W + { + AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W::new(self, 8) } #[doc = "Bits 16:18 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg( &mut self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W< - AON_IOMUX_CFGSAIF_SYSCFG_FMUX2_SPEC, - 16, - > { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W::new(self) + ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W + { + AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W::new(self, 16) } #[doc = "Bits 24:26 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg( &mut self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W< - AON_IOMUX_CFGSAIF_SYSCFG_FMUX2_SPEC, - 24, - > { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W::new(self) + ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W + { + AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux3.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux3.rs index 03bd0c4..94cc018 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux3.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux3.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `aon_gpioen_0_reg` reader - Enable GPIO IRQ function."] pub type AON_GPIOEN_0_REG_R = crate::BitReader; #[doc = "Field `aon_gpioen_0_reg` writer - Enable GPIO IRQ function."] -pub type AON_GPIOEN_0_REG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AON_GPIOEN_0_REG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable GPIO IRQ function."] #[inline(always)] @@ -17,12 +17,14 @@ impl W { #[doc = "Bit 0 - Enable GPIO IRQ function."] #[inline(always)] #[must_use] - pub fn aon_gpioen_0_reg( - &mut self, - ) -> AON_GPIOEN_0_REG_W { - AON_GPIOEN_0_REG_W::new(self) + pub fn aon_gpioen_0_reg(&mut self) -> AON_GPIOEN_0_REG_W { + AON_GPIOEN_0_REG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq10.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq10.rs index 2b3b623..71d7011 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq10.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq10.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq11.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq11.rs index 2fb0443..6e7f217 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq11.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq11.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq4.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq4.rs index 8e55dcc..f984d07 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq4.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq4.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `aon_gpiois_0_reg` reader - 1: Edge trigger, 0: Level trigger"] pub type AON_GPIOIS_0_REG_R = crate::FieldReader; #[doc = "Field `aon_gpiois_0_reg` writer - 1: Edge trigger, 0: Level trigger"] -pub type AON_GPIOIS_0_REG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_GPIOIS_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - 1: Edge trigger, 0: Level trigger"] #[inline(always)] @@ -17,12 +17,14 @@ impl W { #[doc = "Bits 0:3 - 1: Edge trigger, 0: Level trigger"] #[inline(always)] #[must_use] - pub fn aon_gpiois_0_reg( - &mut self, - ) -> AON_GPIOIS_0_REG_W { - AON_GPIOIS_0_REG_W::new(self) + pub fn aon_gpiois_0_reg(&mut self) -> AON_GPIOIS_0_REG_W { + AON_GPIOIS_0_REG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq5.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq5.rs index 4fded86..91bc1c3 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq5.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq5.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `aon_gpioic_0_reg` reader - 1: Do not clear the register, 0: Clear the register"] pub type AON_GPIOIC_0_REG_R = crate::FieldReader; #[doc = "Field `aon_gpioic_0_reg` writer - 1: Do not clear the register, 0: Clear the register"] -pub type AON_GPIOIC_0_REG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_GPIOIC_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - 1: Do not clear the register, 0: Clear the register"] #[inline(always)] @@ -17,12 +17,14 @@ impl W { #[doc = "Bits 0:3 - 1: Do not clear the register, 0: Clear the register"] #[inline(always)] #[must_use] - pub fn aon_gpioic_0_reg( - &mut self, - ) -> AON_GPIOIC_0_REG_W { - AON_GPIOIC_0_REG_W::new(self) + pub fn aon_gpioic_0_reg(&mut self) -> AON_GPIOIC_0_REG_W { + AON_GPIOIC_0_REG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq6.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq6.rs index df0a298..925eb89 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq6.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq6.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `aon_gpioibe_0_reg` reader - 1: Trigger on both edges, 0: Trigger on a single edge"] pub type AON_GPIOIBE_0_REG_R = crate::FieldReader; #[doc = "Field `aon_gpioibe_0_reg` writer - 1: Trigger on both edges, 0: Trigger on a single edge"] -pub type AON_GPIOIBE_0_REG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_GPIOIBE_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - 1: Trigger on both edges, 0: Trigger on a single edge"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn aon_gpioibe_0_reg( &mut self, - ) -> AON_GPIOIBE_0_REG_W { - AON_GPIOIBE_0_REG_W::new(self) + ) -> AON_GPIOIBE_0_REG_W { + AON_GPIOIBE_0_REG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq7.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq7.rs index 51e5fde..353765a 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq7.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq7.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `aon_gpioiev_0_reg` reader - 1: Positive/Low, 0: Negative/High"] pub type AON_GPIOIEV_0_REG_R = crate::FieldReader; #[doc = "Field `aon_gpioiev_0_reg` writer - 1: Positive/Low, 0: Negative/High"] -pub type AON_GPIOIEV_0_REG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_GPIOIEV_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - 1: Positive/Low, 0: Negative/High"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn aon_gpioiev_0_reg( &mut self, - ) -> AON_GPIOIEV_0_REG_W { - AON_GPIOIEV_0_REG_W::new(self) + ) -> AON_GPIOIEV_0_REG_W { + AON_GPIOIEV_0_REG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq8.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq8.rs index b296bb3..cd46c19 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq8.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq8.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `aon_gpioie_0_reg` reader - 1: Unmask, 0: Mask"] pub type AON_GPIOIE_0_REG_R = crate::FieldReader; #[doc = "Field `aon_gpioie_0_reg` writer - 1: Unmask, 0: Mask"] -pub type AON_GPIOIE_0_REG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_GPIOIE_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - 1: Unmask, 0: Mask"] #[inline(always)] @@ -17,12 +17,14 @@ impl W { #[doc = "Bits 0:3 - 1: Unmask, 0: Mask"] #[inline(always)] #[must_use] - pub fn aon_gpioie_0_reg( - &mut self, - ) -> AON_GPIOIE_0_REG_W { - AON_GPIOIE_0_REG_W::new(self) + pub fn aon_gpioie_0_reg(&mut self) -> AON_GPIOIE_0_REG_W { + AON_GPIOIE_0_REG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq9.rs b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq9.rs index e2b4528..72caae7 100644 --- a/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq9.rs +++ b/jh7110-vf2-12a-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq9.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_syscon.rs b/jh7110-vf2-12a-pac/src/aon_syscon.rs index b79c8a8..6b80cee 100644 --- a/jh7110-vf2-12a-pac/src/aon_syscon.rs +++ b/jh7110-vf2-12a-pac/src/aon_syscon.rs @@ -1,87 +1,133 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + aon_sysconsaif_syscfg0: AON_SYSCONSAIF_SYSCFG0, + aon_sysconsaif_syscfg4: AON_SYSCONSAIF_SYSCFG4, + aon_sysconsaif_syscfg8: AON_SYSCONSAIF_SYSCFG8, + aon_sysconsaif_syscfg12: AON_SYSCONSAIF_SYSCFG12, + aon_sysconsaif_syscfg16: AON_SYSCONSAIF_SYSCFG16, + aon_sysconsaif_syscfg20: AON_SYSCONSAIF_SYSCFG20, + aon_sysconsaif_syscfg24: AON_SYSCONSAIF_SYSCFG24, + aon_sysconsaif_syscfg28: AON_SYSCONSAIF_SYSCFG28, + aon_sysconsaif_syscfg32: AON_SYSCONSAIF_SYSCFG32, + aon_sysconsaif_syscfg36: AON_SYSCONSAIF_SYSCFG36, + aon_sysconsaif_syscfg40: AON_SYSCONSAIF_SYSCFG40, +} +impl RegisterBlock { #[doc = "0x00 - AON SYSCONSAIF SYSCFG 0"] - pub aon_sysconsaif_syscfg0: AON_SYSCONSAIF_SYSCFG0, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg0(&self) -> &AON_SYSCONSAIF_SYSCFG0 { + &self.aon_sysconsaif_syscfg0 + } #[doc = "0x04 - AON SYSCONSAIF SYSCFG 4"] - pub aon_sysconsaif_syscfg4: AON_SYSCONSAIF_SYSCFG4, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg4(&self) -> &AON_SYSCONSAIF_SYSCFG4 { + &self.aon_sysconsaif_syscfg4 + } #[doc = "0x08 - AON SYSCONSAIF SYSCFG 8"] - pub aon_sysconsaif_syscfg8: AON_SYSCONSAIF_SYSCFG8, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg8(&self) -> &AON_SYSCONSAIF_SYSCFG8 { + &self.aon_sysconsaif_syscfg8 + } #[doc = "0x0c - AON SYSCONSAIF SYSCFG 12"] - pub aon_sysconsaif_syscfg12: AON_SYSCONSAIF_SYSCFG12, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg12(&self) -> &AON_SYSCONSAIF_SYSCFG12 { + &self.aon_sysconsaif_syscfg12 + } #[doc = "0x10 - AON SYSCONSAIF SYSCFG 16"] - pub aon_sysconsaif_syscfg16: AON_SYSCONSAIF_SYSCFG16, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg16(&self) -> &AON_SYSCONSAIF_SYSCFG16 { + &self.aon_sysconsaif_syscfg16 + } #[doc = "0x14 - AON SYSCONSAIF SYSCFG 20"] - pub aon_sysconsaif_syscfg20: AON_SYSCONSAIF_SYSCFG20, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg20(&self) -> &AON_SYSCONSAIF_SYSCFG20 { + &self.aon_sysconsaif_syscfg20 + } #[doc = "0x18 - AON SYSCONSAIF SYSCFG 24"] - pub aon_sysconsaif_syscfg24: AON_SYSCONSAIF_SYSCFG24, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg24(&self) -> &AON_SYSCONSAIF_SYSCFG24 { + &self.aon_sysconsaif_syscfg24 + } #[doc = "0x1c - AON SYSCONSAIF SYSCFG 28"] - pub aon_sysconsaif_syscfg28: AON_SYSCONSAIF_SYSCFG28, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg28(&self) -> &AON_SYSCONSAIF_SYSCFG28 { + &self.aon_sysconsaif_syscfg28 + } #[doc = "0x20 - AON SYSCONSAIF SYSCFG 32"] - pub aon_sysconsaif_syscfg32: AON_SYSCONSAIF_SYSCFG32, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg32(&self) -> &AON_SYSCONSAIF_SYSCFG32 { + &self.aon_sysconsaif_syscfg32 + } #[doc = "0x24 - AON SYSCONSAIF SYSCFG 36"] - pub aon_sysconsaif_syscfg36: AON_SYSCONSAIF_SYSCFG36, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg36(&self) -> &AON_SYSCONSAIF_SYSCFG36 { + &self.aon_sysconsaif_syscfg36 + } #[doc = "0x28 - AON SYSCONSAIF SYSCFG 40"] - pub aon_sysconsaif_syscfg40: AON_SYSCONSAIF_SYSCFG40, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg40(&self) -> &AON_SYSCONSAIF_SYSCFG40 { + &self.aon_sysconsaif_syscfg40 + } } -#[doc = "aon_sysconsaif_syscfg0 (rw) register accessor: AON SYSCONSAIF SYSCFG 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg0`] +#[doc = "aon_sysconsaif_syscfg0 (rw) register accessor: AON SYSCONSAIF SYSCFG 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg0`] module"] pub type AON_SYSCONSAIF_SYSCFG0 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 0"] pub mod aon_sysconsaif_syscfg0; -#[doc = "aon_sysconsaif_syscfg4 (rw) register accessor: AON SYSCONSAIF SYSCFG 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg4`] +#[doc = "aon_sysconsaif_syscfg4 (rw) register accessor: AON SYSCONSAIF SYSCFG 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg4`] module"] pub type AON_SYSCONSAIF_SYSCFG4 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 4"] pub mod aon_sysconsaif_syscfg4; -#[doc = "aon_sysconsaif_syscfg8 (rw) register accessor: AON SYSCONSAIF SYSCFG 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg8`] +#[doc = "aon_sysconsaif_syscfg8 (rw) register accessor: AON SYSCONSAIF SYSCFG 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg8`] module"] pub type AON_SYSCONSAIF_SYSCFG8 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 8"] pub mod aon_sysconsaif_syscfg8; -#[doc = "aon_sysconsaif_syscfg12 (rw) register accessor: AON SYSCONSAIF SYSCFG 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg12::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg12`] +#[doc = "aon_sysconsaif_syscfg12 (rw) register accessor: AON SYSCONSAIF SYSCFG 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg12::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg12`] module"] pub type AON_SYSCONSAIF_SYSCFG12 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 12"] pub mod aon_sysconsaif_syscfg12; -#[doc = "aon_sysconsaif_syscfg16 (rw) register accessor: AON SYSCONSAIF SYSCFG 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg16::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg16`] +#[doc = "aon_sysconsaif_syscfg16 (rw) register accessor: AON SYSCONSAIF SYSCFG 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg16::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg16`] module"] pub type AON_SYSCONSAIF_SYSCFG16 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 16"] pub mod aon_sysconsaif_syscfg16; -#[doc = "aon_sysconsaif_syscfg20 (rw) register accessor: AON SYSCONSAIF SYSCFG 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg20::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg20`] +#[doc = "aon_sysconsaif_syscfg20 (rw) register accessor: AON SYSCONSAIF SYSCFG 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg20::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg20`] module"] pub type AON_SYSCONSAIF_SYSCFG20 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 20"] pub mod aon_sysconsaif_syscfg20; -#[doc = "aon_sysconsaif_syscfg24 (rw) register accessor: AON SYSCONSAIF SYSCFG 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg24::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg24`] +#[doc = "aon_sysconsaif_syscfg24 (rw) register accessor: AON SYSCONSAIF SYSCFG 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg24::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg24`] module"] pub type AON_SYSCONSAIF_SYSCFG24 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 24"] pub mod aon_sysconsaif_syscfg24; -#[doc = "aon_sysconsaif_syscfg28 (rw) register accessor: AON SYSCONSAIF SYSCFG 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg28::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg28`] +#[doc = "aon_sysconsaif_syscfg28 (rw) register accessor: AON SYSCONSAIF SYSCFG 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg28::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg28`] module"] pub type AON_SYSCONSAIF_SYSCFG28 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 28"] pub mod aon_sysconsaif_syscfg28; -#[doc = "aon_sysconsaif_syscfg32 (rw) register accessor: AON SYSCONSAIF SYSCFG 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg32::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg32`] +#[doc = "aon_sysconsaif_syscfg32 (rw) register accessor: AON SYSCONSAIF SYSCFG 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg32::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg32`] module"] pub type AON_SYSCONSAIF_SYSCFG32 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 32"] pub mod aon_sysconsaif_syscfg32; -#[doc = "aon_sysconsaif_syscfg36 (rw) register accessor: AON SYSCONSAIF SYSCFG 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg36::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg36`] +#[doc = "aon_sysconsaif_syscfg36 (rw) register accessor: AON SYSCONSAIF SYSCFG 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg36::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg36`] module"] pub type AON_SYSCONSAIF_SYSCFG36 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 36"] pub mod aon_sysconsaif_syscfg36; -#[doc = "aon_sysconsaif_syscfg40 (rw) register accessor: AON SYSCONSAIF SYSCFG 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg40::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg40`] +#[doc = "aon_sysconsaif_syscfg40 (rw) register accessor: AON SYSCONSAIF SYSCFG 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg40::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg40`] module"] pub type AON_SYSCONSAIF_SYSCFG40 = crate::Reg; diff --git a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg0.rs b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg0.rs index 6f1c6ca..185bc30 100644 --- a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg0.rs +++ b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `aon_gp_reg` reader - aon_gp_reg"] pub type AON_GP_REG_R = crate::FieldReader; #[doc = "Field `aon_gp_reg` writer - aon_gp_reg"] -pub type AON_GP_REG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type AON_GP_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - aon_gp_reg"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - aon_gp_reg"] #[inline(always)] #[must_use] - pub fn aon_gp_reg(&mut self) -> AON_GP_REG_W { - AON_GP_REG_W::new(self) + pub fn aon_gp_reg(&mut self) -> AON_GP_REG_W { + AON_GP_REG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg12.rs b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg12.rs index b10ae91..3be4f38 100644 --- a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg12.rs +++ b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg12.rs @@ -7,42 +7,41 @@ pub type U0_BOOT_CTRL_BOOT_VECTOR_35_32_R = crate::FieldReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] pub type GMAC5_AXI64_SCFG_RAM_CFG_SLP_R = crate::BitReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] -pub type GMAC5_AXI64_SCFG_RAM_CFG_SLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GMAC5_AXI64_SCFG_RAM_CFG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] pub type GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_R = crate::BitReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] -pub type GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] pub type GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_R = crate::FieldReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] -pub type GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] pub type GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_R = crate::FieldReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] -pub type GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] pub type GMAC5_AXI64_SCFG_RAM_CFG_TRB_R = crate::FieldReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] -pub type GMAC5_AXI64_SCFG_RAM_CFG_TRB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type GMAC5_AXI64_SCFG_RAM_CFG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] pub type GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_R = crate::FieldReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] -pub type GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] pub type GMAC5_AXI64_SCFG_RAM_CFG_VS_R = crate::BitReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] -pub type GMAC5_AXI64_SCFG_RAM_CFG_VS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GMAC5_AXI64_SCFG_RAM_CFG_VS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] pub type GMAC5_AXI64_SCFG_RAM_CFG_VG_R = crate::BitReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] -pub type GMAC5_AXI64_SCFG_RAM_CFG_VG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GMAC5_AXI64_SCFG_RAM_CFG_VG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gmac5_axi64_mac_speed_o` reader - gmac5_axi64_mac_speed_o"] pub type GMAC5_AXI64_MAC_SPEED_O_R = crate::FieldReader; #[doc = "Field `gmac5_axi64_phy_intf_sel_i` reader - Active PHY Selected. When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. Values: 0x0 - GMII or MII, 0x1 - RGMII, 0x2 - SGMII, 0x3 - TBI, 0x4 - RMII, 0x5 - RTBI, 0x6 - SMII, 0x7 - REVMII"] pub type GMAC5_AXI64_PHY_INTF_SEL_I_R = crate::FieldReader; #[doc = "Field `gmac5_axi64_phy_intf_sel_i` writer - Active PHY Selected. When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. Values: 0x0 - GMII or MII, 0x1 - RGMII, 0x2 - SGMII, 0x3 - TBI, 0x4 - RMII, 0x5 - RTBI, 0x6 - SMII, 0x7 - REVMII"] -pub type GMAC5_AXI64_PHY_INTF_SEL_I_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type GMAC5_AXI64_PHY_INTF_SEL_I_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:3 - u0_boot_ctrl_boot_vector_35_32"] #[inline(always)] @@ -108,74 +107,78 @@ impl W { #[must_use] pub fn gmac5_axi64_scfg_ram_cfg_slp( &mut self, - ) -> GMAC5_AXI64_SCFG_RAM_CFG_SLP_W { - GMAC5_AXI64_SCFG_RAM_CFG_SLP_W::new(self) + ) -> GMAC5_AXI64_SCFG_RAM_CFG_SLP_W { + GMAC5_AXI64_SCFG_RAM_CFG_SLP_W::new(self, 4) } #[doc = "Bit 5 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] #[inline(always)] #[must_use] pub fn gmac5_axi64_scfg_ram_cfg_sram_config_sd( &mut self, - ) -> GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W { - GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W::new(self) + ) -> GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W { + GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W::new(self, 5) } #[doc = "Bits 6:7 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn gmac5_axi64_scfg_ram_cfg_rtsel( &mut self, - ) -> GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W { - GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W::new(self) + ) -> GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W { + GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W::new(self, 6) } #[doc = "Bits 8:9 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn gmac5_axi64_scfg_ram_cfg_ptsel( &mut self, - ) -> GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W { - GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W::new(self) + ) -> GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W { + GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W::new(self, 8) } #[doc = "Bits 10:11 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn gmac5_axi64_scfg_ram_cfg_trb( &mut self, - ) -> GMAC5_AXI64_SCFG_RAM_CFG_TRB_W { - GMAC5_AXI64_SCFG_RAM_CFG_TRB_W::new(self) + ) -> GMAC5_AXI64_SCFG_RAM_CFG_TRB_W { + GMAC5_AXI64_SCFG_RAM_CFG_TRB_W::new(self, 10) } #[doc = "Bits 12:13 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn gmac5_axi64_scfg_ram_cfg_wtsel( &mut self, - ) -> GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W { - GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W::new(self) + ) -> GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W { + GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W::new(self, 12) } #[doc = "Bit 14 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn gmac5_axi64_scfg_ram_cfg_vs( &mut self, - ) -> GMAC5_AXI64_SCFG_RAM_CFG_VS_W { - GMAC5_AXI64_SCFG_RAM_CFG_VS_W::new(self) + ) -> GMAC5_AXI64_SCFG_RAM_CFG_VS_W { + GMAC5_AXI64_SCFG_RAM_CFG_VS_W::new(self, 14) } #[doc = "Bit 15 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn gmac5_axi64_scfg_ram_cfg_vg( &mut self, - ) -> GMAC5_AXI64_SCFG_RAM_CFG_VG_W { - GMAC5_AXI64_SCFG_RAM_CFG_VG_W::new(self) + ) -> GMAC5_AXI64_SCFG_RAM_CFG_VG_W { + GMAC5_AXI64_SCFG_RAM_CFG_VG_W::new(self, 15) } #[doc = "Bits 18:20 - Active PHY Selected. When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. Values: 0x0 - GMII or MII, 0x1 - RGMII, 0x2 - SGMII, 0x3 - TBI, 0x4 - RMII, 0x5 - RTBI, 0x6 - SMII, 0x7 - REVMII"] #[inline(always)] #[must_use] pub fn gmac5_axi64_phy_intf_sel_i( &mut self, - ) -> GMAC5_AXI64_PHY_INTF_SEL_I_W { - GMAC5_AXI64_PHY_INTF_SEL_I_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> GMAC5_AXI64_PHY_INTF_SEL_I_W { + GMAC5_AXI64_PHY_INTF_SEL_I_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg16.rs b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg16.rs index 03874e4..757d797 100644 --- a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg16.rs +++ b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg16.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg20.rs b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg20.rs index de6a843..51d904d 100644 --- a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg20.rs +++ b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg20.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg24.rs b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg24.rs index 2ff7519..b2d392d 100644 --- a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg24.rs +++ b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg24.rs @@ -26,7 +26,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg28.rs b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg28.rs index 0960490..bb8bbfd 100644 --- a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg28.rs +++ b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg28.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg32.rs b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg32.rs index f84ba2b..92cfdb9 100644 --- a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg32.rs +++ b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg32.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg36.rs b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg36.rs index ce2a854..6627170 100644 --- a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg36.rs +++ b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg36.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg4.rs b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg4.rs index e47a8e5..679a461 100644 --- a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg4.rs +++ b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg4.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg40.rs b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg40.rs index 801573e..0c34ef1 100644 --- a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg40.rs +++ b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg40.rs @@ -11,13 +11,13 @@ pub type U0_OTPC_LOAD_BUSY_R = crate::BitReader; #[doc = "Field `u0_reset_ctrl_clr_reset_status` reader - u0_reset_ctrl_clr_reset_status"] pub type U0_RESET_CTRL_CLR_RESET_STATUS_R = crate::BitReader; #[doc = "Field `u0_reset_ctrl_clr_reset_status` writer - u0_reset_ctrl_clr_reset_status"] -pub type U0_RESET_CTRL_CLR_RESET_STATUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_RESET_CTRL_CLR_RESET_STATUS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_reset_ctrl_pll_timecnt_finish` reader - u0_reset_ctrl_pll_timecnt_finish"] pub type U0_RESET_CTRL_PLL_TIMECNT_FINISH_R = crate::BitReader; #[doc = "Field `u0_reset_ctrl_rstn_sw` reader - u0_reset_ctrl_rstn_sw"] pub type U0_RESET_CTRL_RSTN_SW_R = crate::BitReader; #[doc = "Field `u0_reset_ctrl_rstn_sw` writer - u0_reset_ctrl_rstn_sw"] -pub type U0_RESET_CTRL_RSTN_SW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_RESET_CTRL_RSTN_SW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_reset_ctrl_sys_reset_status` reader - u0_reset_ctrl_sys_reset_status"] pub type U0_RESET_CTRL_SYS_RESET_STATUS_R = crate::FieldReader; impl R { @@ -63,18 +63,22 @@ impl W { #[must_use] pub fn u0_reset_ctrl_clr_reset_status( &mut self, - ) -> U0_RESET_CTRL_CLR_RESET_STATUS_W { - U0_RESET_CTRL_CLR_RESET_STATUS_W::new(self) + ) -> U0_RESET_CTRL_CLR_RESET_STATUS_W { + U0_RESET_CTRL_CLR_RESET_STATUS_W::new(self, 3) } #[doc = "Bit 5 - u0_reset_ctrl_rstn_sw"] #[inline(always)] #[must_use] pub fn u0_reset_ctrl_rstn_sw( &mut self, - ) -> U0_RESET_CTRL_RSTN_SW_W { - U0_RESET_CTRL_RSTN_SW_W::new(self) + ) -> U0_RESET_CTRL_RSTN_SW_W { + U0_RESET_CTRL_RSTN_SW_W::new(self, 5) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg8.rs b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg8.rs index 526e1ae..cbffe58 100644 --- a/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg8.rs +++ b/jh7110-vf2-12a-pac/src/aon_syscon/aon_sysconsaif_syscfg8.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aoncrg.rs b/jh7110-vf2-12a-pac/src/aoncrg.rs index cf238c3..96a0761 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg.rs @@ -1,115 +1,181 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + clk_osc: CLK_OSC, + clk_aon_apb: CLK_AON_APB, + clk_ahb_gmac5: CLK_AHB_GMAC5, + clk_axi_gmac5: CLK_AXI_GMAC5, + clk_gmac0_rmii_rtx: CLK_GMAC0_RMII_RTX, + clk_gmac5_axi64_tx: CLK_GMAC5_AXI64_TX, + clk_gmac5_axi64_txi: CLK_GMAC5_AXI64_TXI, + clk_gmac5_axi64_rx: CLK_GMAC5_AXI64_RX, + clk_gmac5_axi64_rxi: CLK_GMAC5_AXI64_RXI, + clk_optc_apb: CLK_OPTC_APB, + clk_rtc_hms_apb: CLK_RTC_HMS_APB, + clk_rtc_internal: CLK_RTC_INTERNAL, + clk_rtc_hms_osc32k: CLK_RTC_HMS_OSC32K, + clk_rtc_hms_cal: CLK_RTC_HMS_CAL, + soft_rst_addr_sel: SOFT_RST_ADDR_SEL, + aoncrg_rst_status: AONCRG_RST_STATUS, +} +impl RegisterBlock { #[doc = "0x00 - Oscillator Clock"] - pub clk_osc: CLK_OSC, + #[inline(always)] + pub const fn clk_osc(&self) -> &CLK_OSC { + &self.clk_osc + } #[doc = "0x04 - AON APB Function Clock"] - pub clk_aon_apb: CLK_AON_APB, + #[inline(always)] + pub const fn clk_aon_apb(&self) -> &CLK_AON_APB { + &self.clk_aon_apb + } #[doc = "0x08 - AHB GMAC5 Clock"] - pub clk_ahb_gmac5: CLK_AHB_GMAC5, + #[inline(always)] + pub const fn clk_ahb_gmac5(&self) -> &CLK_AHB_GMAC5 { + &self.clk_ahb_gmac5 + } #[doc = "0x0c - AXI GMAC5 Clock"] - pub clk_axi_gmac5: CLK_AXI_GMAC5, + #[inline(always)] + pub const fn clk_axi_gmac5(&self) -> &CLK_AXI_GMAC5 { + &self.clk_axi_gmac5 + } #[doc = "0x10 - GMAC0 RMII RTX Clock"] - pub clk_gmac0_rmii_rtx: CLK_GMAC0_RMII_RTX, + #[inline(always)] + pub const fn clk_gmac0_rmii_rtx(&self) -> &CLK_GMAC0_RMII_RTX { + &self.clk_gmac0_rmii_rtx + } #[doc = "0x14 - GMAC5 AXI64 Clock Transmitter"] - pub clk_gmac5_axi64_tx: CLK_GMAC5_AXI64_TX, + #[inline(always)] + pub const fn clk_gmac5_axi64_tx(&self) -> &CLK_GMAC5_AXI64_TX { + &self.clk_gmac5_axi64_tx + } #[doc = "0x18 - GMAC5 AXI64 Clock Transmission Inverter"] - pub clk_gmac5_axi64_txi: CLK_GMAC5_AXI64_TXI, + #[inline(always)] + pub const fn clk_gmac5_axi64_txi(&self) -> &CLK_GMAC5_AXI64_TXI { + &self.clk_gmac5_axi64_txi + } #[doc = "0x1c - GMAC5 AXI64 Clock Receiver"] - pub clk_gmac5_axi64_rx: CLK_GMAC5_AXI64_RX, + #[inline(always)] + pub const fn clk_gmac5_axi64_rx(&self) -> &CLK_GMAC5_AXI64_RX { + &self.clk_gmac5_axi64_rx + } #[doc = "0x20 - GMAC5 AXI64 Clock Receiving Inverter"] - pub clk_gmac5_axi64_rxi: CLK_GMAC5_AXI64_RXI, + #[inline(always)] + pub const fn clk_gmac5_axi64_rxi(&self) -> &CLK_GMAC5_AXI64_RXI { + &self.clk_gmac5_axi64_rxi + } #[doc = "0x24 - OPTC APB Clock"] - pub clk_optc_apb: CLK_OPTC_APB, + #[inline(always)] + pub const fn clk_optc_apb(&self) -> &CLK_OPTC_APB { + &self.clk_optc_apb + } #[doc = "0x28 - RTC HMS APB Clock"] - pub clk_rtc_hms_apb: CLK_RTC_HMS_APB, + #[inline(always)] + pub const fn clk_rtc_hms_apb(&self) -> &CLK_RTC_HMS_APB { + &self.clk_rtc_hms_apb + } #[doc = "0x2c - RTC Internal Clock"] - pub clk_rtc_internal: CLK_RTC_INTERNAL, + #[inline(always)] + pub const fn clk_rtc_internal(&self) -> &CLK_RTC_INTERNAL { + &self.clk_rtc_internal + } #[doc = "0x30 - RTC HMS Clock Oscillator 32K"] - pub clk_rtc_hms_osc32k: CLK_RTC_HMS_OSC32K, + #[inline(always)] + pub const fn clk_rtc_hms_osc32k(&self) -> &CLK_RTC_HMS_OSC32K { + &self.clk_rtc_hms_osc32k + } #[doc = "0x34 - RTC HMS Clock Calculator"] - pub clk_rtc_hms_cal: CLK_RTC_HMS_CAL, + #[inline(always)] + pub const fn clk_rtc_hms_cal(&self) -> &CLK_RTC_HMS_CAL { + &self.clk_rtc_hms_cal + } #[doc = "0x38 - Software RESET Address Selector"] - pub soft_rst_addr_sel: SOFT_RST_ADDR_SEL, + #[inline(always)] + pub const fn soft_rst_addr_sel(&self) -> &SOFT_RST_ADDR_SEL { + &self.soft_rst_addr_sel + } #[doc = "0x3c - AONCRG RESET Status"] - pub aoncrg_rst_status: AONCRG_RST_STATUS, + #[inline(always)] + pub const fn aoncrg_rst_status(&self) -> &AONCRG_RST_STATUS { + &self.aoncrg_rst_status + } } -#[doc = "clk_osc (rw) register accessor: Oscillator Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_osc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_osc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_osc`] +#[doc = "clk_osc (rw) register accessor: Oscillator Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_osc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_osc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_osc`] module"] pub type CLK_OSC = crate::Reg; #[doc = "Oscillator Clock"] pub mod clk_osc; -#[doc = "clk_aon_apb (rw) register accessor: AON APB Function Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_aon_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_aon_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_aon_apb`] +#[doc = "clk_aon_apb (rw) register accessor: AON APB Function Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_aon_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_aon_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_aon_apb`] module"] pub type CLK_AON_APB = crate::Reg; #[doc = "AON APB Function Clock"] pub mod clk_aon_apb; -#[doc = "clk_ahb_gmac5 (rw) register accessor: AHB GMAC5 Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ahb_gmac5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ahb_gmac5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_ahb_gmac5`] +#[doc = "clk_ahb_gmac5 (rw) register accessor: AHB GMAC5 Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ahb_gmac5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ahb_gmac5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_ahb_gmac5`] module"] pub type CLK_AHB_GMAC5 = crate::Reg; #[doc = "AHB GMAC5 Clock"] pub mod clk_ahb_gmac5; -#[doc = "clk_axi_gmac5 (rw) register accessor: AXI GMAC5 Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_gmac5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_gmac5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_axi_gmac5`] +#[doc = "clk_axi_gmac5 (rw) register accessor: AXI GMAC5 Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_gmac5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_gmac5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_axi_gmac5`] module"] pub type CLK_AXI_GMAC5 = crate::Reg; #[doc = "AXI GMAC5 Clock"] pub mod clk_axi_gmac5; -#[doc = "clk_gmac0_rmii_rtx (rw) register accessor: GMAC0 RMII RTX Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac0_rmii_rtx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac0_rmii_rtx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac0_rmii_rtx`] +#[doc = "clk_gmac0_rmii_rtx (rw) register accessor: GMAC0 RMII RTX Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac0_rmii_rtx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac0_rmii_rtx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac0_rmii_rtx`] module"] pub type CLK_GMAC0_RMII_RTX = crate::Reg; #[doc = "GMAC0 RMII RTX Clock"] pub mod clk_gmac0_rmii_rtx; -#[doc = "clk_gmac5_axi64_tx (rw) register accessor: GMAC5 AXI64 Clock Transmitter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_tx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_tx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_tx`] +#[doc = "clk_gmac5_axi64_tx (rw) register accessor: GMAC5 AXI64 Clock Transmitter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_tx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_tx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_tx`] module"] pub type CLK_GMAC5_AXI64_TX = crate::Reg; #[doc = "GMAC5 AXI64 Clock Transmitter"] pub mod clk_gmac5_axi64_tx; -#[doc = "clk_gmac5_axi64_txi (rw) register accessor: GMAC5 AXI64 Clock Transmission Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_txi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_txi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_txi`] +#[doc = "clk_gmac5_axi64_txi (rw) register accessor: GMAC5 AXI64 Clock Transmission Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_txi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_txi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_txi`] module"] pub type CLK_GMAC5_AXI64_TXI = crate::Reg; #[doc = "GMAC5 AXI64 Clock Transmission Inverter"] pub mod clk_gmac5_axi64_txi; -#[doc = "clk_gmac5_axi64_rx (rw) register accessor: GMAC5 AXI64 Clock Receiver\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_rx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_rx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_rx`] +#[doc = "clk_gmac5_axi64_rx (rw) register accessor: GMAC5 AXI64 Clock Receiver\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_rx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_rx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_rx`] module"] pub type CLK_GMAC5_AXI64_RX = crate::Reg; #[doc = "GMAC5 AXI64 Clock Receiver"] pub mod clk_gmac5_axi64_rx; -#[doc = "clk_gmac5_axi64_rxi (rw) register accessor: GMAC5 AXI64 Clock Receiving Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_rxi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_rxi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_rxi`] +#[doc = "clk_gmac5_axi64_rxi (rw) register accessor: GMAC5 AXI64 Clock Receiving Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_rxi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_rxi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_rxi`] module"] pub type CLK_GMAC5_AXI64_RXI = crate::Reg; #[doc = "GMAC5 AXI64 Clock Receiving Inverter"] pub mod clk_gmac5_axi64_rxi; -#[doc = "clk_optc_apb (rw) register accessor: OPTC APB Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_optc_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_optc_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_optc_apb`] +#[doc = "clk_optc_apb (rw) register accessor: OPTC APB Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_optc_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_optc_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_optc_apb`] module"] pub type CLK_OPTC_APB = crate::Reg; #[doc = "OPTC APB Clock"] pub mod clk_optc_apb; -#[doc = "clk_rtc_hms_apb (rw) register accessor: RTC HMS APB Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_hms_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_hms_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_rtc_hms_apb`] +#[doc = "clk_rtc_hms_apb (rw) register accessor: RTC HMS APB Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_hms_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_hms_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_rtc_hms_apb`] module"] pub type CLK_RTC_HMS_APB = crate::Reg; #[doc = "RTC HMS APB Clock"] pub mod clk_rtc_hms_apb; -#[doc = "clk_rtc_internal (rw) register accessor: RTC Internal Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_internal::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_internal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_rtc_internal`] +#[doc = "clk_rtc_internal (rw) register accessor: RTC Internal Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_internal::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_internal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_rtc_internal`] module"] pub type CLK_RTC_INTERNAL = crate::Reg; #[doc = "RTC Internal Clock"] pub mod clk_rtc_internal; -#[doc = "clk_rtc_hms_osc32k (rw) register accessor: RTC HMS Clock Oscillator 32K\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_hms_osc32k::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_hms_osc32k::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_rtc_hms_osc32k`] +#[doc = "clk_rtc_hms_osc32k (rw) register accessor: RTC HMS Clock Oscillator 32K\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_hms_osc32k::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_hms_osc32k::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_rtc_hms_osc32k`] module"] pub type CLK_RTC_HMS_OSC32K = crate::Reg; #[doc = "RTC HMS Clock Oscillator 32K"] pub mod clk_rtc_hms_osc32k; -#[doc = "clk_rtc_hms_cal (rw) register accessor: RTC HMS Clock Calculator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_hms_cal::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_hms_cal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_rtc_hms_cal`] +#[doc = "clk_rtc_hms_cal (rw) register accessor: RTC HMS Clock Calculator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_hms_cal::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_hms_cal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_rtc_hms_cal`] module"] pub type CLK_RTC_HMS_CAL = crate::Reg; #[doc = "RTC HMS Clock Calculator"] pub mod clk_rtc_hms_cal; -#[doc = "soft_rst_addr_sel (rw) register accessor: Software RESET Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_rst_addr_sel`] +#[doc = "soft_rst_addr_sel (rw) register accessor: Software RESET Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_rst_addr_sel`] module"] pub type SOFT_RST_ADDR_SEL = crate::Reg; #[doc = "Software RESET Address Selector"] pub mod soft_rst_addr_sel; -#[doc = "aoncrg_rst_status (rw) register accessor: AONCRG RESET Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aoncrg_rst_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aoncrg_rst_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aoncrg_rst_status`] +#[doc = "aoncrg_rst_status (rw) register accessor: AONCRG RESET Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aoncrg_rst_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aoncrg_rst_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aoncrg_rst_status`] module"] pub type AONCRG_RST_STATUS = crate::Reg; #[doc = "AONCRG RESET Status"] diff --git a/jh7110-vf2-12a-pac/src/aoncrg/aoncrg_rst_status.rs b/jh7110-vf2-12a-pac/src/aoncrg/aoncrg_rst_status.rs index 073f3fb..83ffda5 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg/aoncrg_rst_status.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg/aoncrg_rst_status.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `gmac5_axi64_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type GMAC5_AXI64_RSTN_AXI_R = crate::BitReader; #[doc = "Field `gmac5_axi64_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type GMAC5_AXI64_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GMAC5_AXI64_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gmac5_axi64_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type GMAC5_AXI64_RSTN_AHB_R = crate::BitReader; #[doc = "Field `gmac5_axi64_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type GMAC5_AXI64_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GMAC5_AXI64_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `aon_iomux_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type AON_IOMUX_PRESETN_R = crate::BitReader; #[doc = "Field `aon_iomux_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type AON_IOMUX_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AON_IOMUX_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pmu_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type PMU_RSTN_APB_R = crate::BitReader; #[doc = "Field `pmu_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type PMU_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PMU_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pmu_rstn_wkup` reader - 1: Assert reset, 0: De-assert reset"] pub type PMU_RSTN_WKUP_R = crate::BitReader; #[doc = "Field `pmu_rstn_wkup` writer - 1: Assert reset, 0: De-assert reset"] -pub type PMU_RSTN_WKUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PMU_RSTN_WKUP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtc_hms_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RTC_HMS_RSTN_APB_R = crate::BitReader; #[doc = "Field `rtc_hms_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RTC_HMS_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTC_HMS_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtc_hms_rstn_cal` reader - 1: Assert reset, 0: De-assert reset"] pub type RTC_HMS_RSTN_CAL_R = crate::BitReader; #[doc = "Field `rtc_hms_rstn_cal` writer - 1: Assert reset, 0: De-assert reset"] -pub type RTC_HMS_RSTN_CAL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTC_HMS_RSTN_CAL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtc_hms_rstn_osc32k` reader - 1: Assert reset, 0: De-assert reset"] pub type RTC_HMS_RSTN_OSC32K_R = crate::BitReader; #[doc = "Field `rtc_hms_rstn_osc32k` writer - 1: Assert reset, 0: De-assert reset"] -pub type RTC_HMS_RSTN_OSC32K_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTC_HMS_RSTN_OSC32K_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -80,52 +80,56 @@ impl W { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn gmac5_axi64_rstn_axi(&mut self) -> GMAC5_AXI64_RSTN_AXI_W { - GMAC5_AXI64_RSTN_AXI_W::new(self) + pub fn gmac5_axi64_rstn_axi(&mut self) -> GMAC5_AXI64_RSTN_AXI_W { + GMAC5_AXI64_RSTN_AXI_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn gmac5_axi64_rstn_ahb(&mut self) -> GMAC5_AXI64_RSTN_AHB_W { - GMAC5_AXI64_RSTN_AHB_W::new(self) + pub fn gmac5_axi64_rstn_ahb(&mut self) -> GMAC5_AXI64_RSTN_AHB_W { + GMAC5_AXI64_RSTN_AHB_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn aon_iomux_presetn(&mut self) -> AON_IOMUX_PRESETN_W { - AON_IOMUX_PRESETN_W::new(self) + pub fn aon_iomux_presetn(&mut self) -> AON_IOMUX_PRESETN_W { + AON_IOMUX_PRESETN_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn pmu_rstn_apb(&mut self) -> PMU_RSTN_APB_W { - PMU_RSTN_APB_W::new(self) + pub fn pmu_rstn_apb(&mut self) -> PMU_RSTN_APB_W { + PMU_RSTN_APB_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn pmu_rstn_wkup(&mut self) -> PMU_RSTN_WKUP_W { - PMU_RSTN_WKUP_W::new(self) + pub fn pmu_rstn_wkup(&mut self) -> PMU_RSTN_WKUP_W { + PMU_RSTN_WKUP_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rtc_hms_rstn_apb(&mut self) -> RTC_HMS_RSTN_APB_W { - RTC_HMS_RSTN_APB_W::new(self) + pub fn rtc_hms_rstn_apb(&mut self) -> RTC_HMS_RSTN_APB_W { + RTC_HMS_RSTN_APB_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rtc_hms_rstn_cal(&mut self) -> RTC_HMS_RSTN_CAL_W { - RTC_HMS_RSTN_CAL_W::new(self) + pub fn rtc_hms_rstn_cal(&mut self) -> RTC_HMS_RSTN_CAL_W { + RTC_HMS_RSTN_CAL_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rtc_hms_rstn_osc32k(&mut self) -> RTC_HMS_RSTN_OSC32K_W { - RTC_HMS_RSTN_OSC32K_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn rtc_hms_rstn_osc32k(&mut self) -> RTC_HMS_RSTN_OSC32K_W { + RTC_HMS_RSTN_OSC32K_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aoncrg/clk_ahb_gmac5.rs b/jh7110-vf2-12a-pac/src/aoncrg/clk_ahb_gmac5.rs index b031301..1a81926 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg/clk_ahb_gmac5.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg/clk_ahb_gmac5.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aoncrg/clk_aon_apb.rs b/jh7110-vf2-12a-pac/src/aoncrg/clk_aon_apb.rs index bbd5215..95bf754 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg/clk_aon_apb.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg/clk_aon_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_osc_div4, clk_osc"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_osc_div4, clk_osc"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc_div4, clk_osc"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc_div4, clk_osc"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aoncrg/clk_axi_gmac5.rs b/jh7110-vf2-12a-pac/src/aoncrg/clk_axi_gmac5.rs index 00d7b78..beff06a 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg/clk_axi_gmac5.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg/clk_axi_gmac5.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac0_rmii_rtx.rs b/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac0_rmii_rtx.rs index 310e0da..17a7a00 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac0_rmii_rtx.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac0_rmii_rtx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac5_axi64_rx.rs b/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac5_axi64_rx.rs index df8a3f3..287e146 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac5_axi64_rx.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac5_axi64_rx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `dly_chain_sel` reader - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] pub type DLY_CHAIN_SEL_R = crate::FieldReader; #[doc = "Field `dly_chain_sel` writer - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] -pub type DLY_CHAIN_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type DLY_CHAIN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] #[inline(always)] #[must_use] - pub fn dly_chain_sel(&mut self) -> DLY_CHAIN_SEL_W { - DLY_CHAIN_SEL_W::new(self) + pub fn dly_chain_sel(&mut self) -> DLY_CHAIN_SEL_W { + DLY_CHAIN_SEL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac5_axi64_rxi.rs b/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac5_axi64_rxi.rs index 67e5cc8..d1370fb 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac5_axi64_rxi.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac5_axi64_rxi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac5_axi64_tx.rs b/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac5_axi64_tx.rs index ebe5f21..c148a40 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac5_axi64_tx.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac5_axi64_tx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: u0_sys_crg_clk_gmac0_gtxclk, clk_gmac0_rmii_rtx"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: u0_sys_crg_clk_gmac0_gtxclk, clk_gmac0_rmii_rtx"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: u0_sys_crg_clk_gmac0_gtxclk, clk_gmac0_rmii_rtx"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: u0_sys_crg_clk_gmac0_gtxclk, clk_gmac0_rmii_rtx"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac5_axi64_txi.rs b/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac5_axi64_txi.rs index 9bb5777..ee093f4 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac5_axi64_txi.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg/clk_gmac5_axi64_txi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aoncrg/clk_optc_apb.rs b/jh7110-vf2-12a-pac/src/aoncrg/clk_optc_apb.rs index aae9f3b..95f2d7d 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg/clk_optc_apb.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg/clk_optc_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aoncrg/clk_osc.rs b/jh7110-vf2-12a-pac/src/aoncrg/clk_osc.rs index 97a9a1e..c1533ef 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg/clk_osc.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg/clk_osc.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aoncrg/clk_rtc_hms_apb.rs b/jh7110-vf2-12a-pac/src/aoncrg/clk_rtc_hms_apb.rs index 8d5536a..963f47b 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg/clk_rtc_hms_apb.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg/clk_rtc_hms_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aoncrg/clk_rtc_hms_cal.rs b/jh7110-vf2-12a-pac/src/aoncrg/clk_rtc_hms_cal.rs index ceca8e2..e759a1f 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg/clk_rtc_hms_cal.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg/clk_rtc_hms_cal.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aoncrg/clk_rtc_hms_osc32k.rs b/jh7110-vf2-12a-pac/src/aoncrg/clk_rtc_hms_osc32k.rs index b45692e..324c4f2 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg/clk_rtc_hms_osc32k.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg/clk_rtc_hms_osc32k.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_rtc, clk_rtc_internal"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_rtc, clk_rtc_internal"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_rtc, clk_rtc_internal"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_rtc, clk_rtc_internal"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aoncrg/clk_rtc_internal.rs b/jh7110-vf2-12a-pac/src/aoncrg/clk_rtc_internal.rs index 7b7e065..f537c6b 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg/clk_rtc_internal.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg/clk_rtc_internal.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=1022, Default=750, Min=750, Typical=750"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=1022, Default=750, Min=750, Typical=750"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=1022, Default=750, Min=750, Typical=750"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=1022, Default=750, Min=750, Typical=750"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/aoncrg/soft_rst_addr_sel.rs b/jh7110-vf2-12a-pac/src/aoncrg/soft_rst_addr_sel.rs index ac4416a..78952e8 100644 --- a/jh7110-vf2-12a-pac/src/aoncrg/soft_rst_addr_sel.rs +++ b/jh7110-vf2-12a-pac/src/aoncrg/soft_rst_addr_sel.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `gmac5_axi64_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type GMAC5_AXI64_RSTN_AXI_R = crate::BitReader; #[doc = "Field `gmac5_axi64_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type GMAC5_AXI64_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GMAC5_AXI64_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gmac5_axi64_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type GMAC5_AXI64_RSTN_AHB_R = crate::BitReader; #[doc = "Field `gmac5_axi64_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type GMAC5_AXI64_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GMAC5_AXI64_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `aon_iomux_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type AON_IOMUX_PRESETN_R = crate::BitReader; #[doc = "Field `aon_iomux_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type AON_IOMUX_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AON_IOMUX_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pmu_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type PMU_RSTN_APB_R = crate::BitReader; #[doc = "Field `pmu_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type PMU_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PMU_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pmu_rstn_wkup` reader - 1: Assert reset, 0: De-assert reset"] pub type PMU_RSTN_WKUP_R = crate::BitReader; #[doc = "Field `pmu_rstn_wkup` writer - 1: Assert reset, 0: De-assert reset"] -pub type PMU_RSTN_WKUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PMU_RSTN_WKUP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtc_hms_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RTC_HMS_RSTN_APB_R = crate::BitReader; #[doc = "Field `rtc_hms_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RTC_HMS_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTC_HMS_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtc_hms_rstn_cal` reader - 1: Assert reset, 0: De-assert reset"] pub type RTC_HMS_RSTN_CAL_R = crate::BitReader; #[doc = "Field `rtc_hms_rstn_cal` writer - 1: Assert reset, 0: De-assert reset"] -pub type RTC_HMS_RSTN_CAL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTC_HMS_RSTN_CAL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtc_hms_rstn_osc32k` reader - 1: Assert reset, 0: De-assert reset"] pub type RTC_HMS_RSTN_OSC32K_R = crate::BitReader; #[doc = "Field `rtc_hms_rstn_osc32k` writer - 1: Assert reset, 0: De-assert reset"] -pub type RTC_HMS_RSTN_OSC32K_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTC_HMS_RSTN_OSC32K_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -80,52 +80,56 @@ impl W { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn gmac5_axi64_rstn_axi(&mut self) -> GMAC5_AXI64_RSTN_AXI_W { - GMAC5_AXI64_RSTN_AXI_W::new(self) + pub fn gmac5_axi64_rstn_axi(&mut self) -> GMAC5_AXI64_RSTN_AXI_W { + GMAC5_AXI64_RSTN_AXI_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn gmac5_axi64_rstn_ahb(&mut self) -> GMAC5_AXI64_RSTN_AHB_W { - GMAC5_AXI64_RSTN_AHB_W::new(self) + pub fn gmac5_axi64_rstn_ahb(&mut self) -> GMAC5_AXI64_RSTN_AHB_W { + GMAC5_AXI64_RSTN_AHB_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn aon_iomux_presetn(&mut self) -> AON_IOMUX_PRESETN_W { - AON_IOMUX_PRESETN_W::new(self) + pub fn aon_iomux_presetn(&mut self) -> AON_IOMUX_PRESETN_W { + AON_IOMUX_PRESETN_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn pmu_rstn_apb(&mut self) -> PMU_RSTN_APB_W { - PMU_RSTN_APB_W::new(self) + pub fn pmu_rstn_apb(&mut self) -> PMU_RSTN_APB_W { + PMU_RSTN_APB_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn pmu_rstn_wkup(&mut self) -> PMU_RSTN_WKUP_W { - PMU_RSTN_WKUP_W::new(self) + pub fn pmu_rstn_wkup(&mut self) -> PMU_RSTN_WKUP_W { + PMU_RSTN_WKUP_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rtc_hms_rstn_apb(&mut self) -> RTC_HMS_RSTN_APB_W { - RTC_HMS_RSTN_APB_W::new(self) + pub fn rtc_hms_rstn_apb(&mut self) -> RTC_HMS_RSTN_APB_W { + RTC_HMS_RSTN_APB_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rtc_hms_rstn_cal(&mut self) -> RTC_HMS_RSTN_CAL_W { - RTC_HMS_RSTN_CAL_W::new(self) + pub fn rtc_hms_rstn_cal(&mut self) -> RTC_HMS_RSTN_CAL_W { + RTC_HMS_RSTN_CAL_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rtc_hms_rstn_osc32k(&mut self) -> RTC_HMS_RSTN_OSC32K_W { - RTC_HMS_RSTN_OSC32K_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn rtc_hms_rstn_osc32k(&mut self) -> RTC_HMS_RSTN_OSC32K_W { + RTC_HMS_RSTN_OSC32K_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/clint.rs b/jh7110-vf2-12a-pac/src/clint.rs index 42c26c7..f3f4b70 100644 --- a/jh7110-vf2-12a-pac/src/clint.rs +++ b/jh7110-vf2-12a-pac/src/clint.rs @@ -1,82 +1,128 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + msip_0: MSIP_0, + msip_1: MSIP_1, + msip_2: MSIP_2, + msip_3: MSIP_3, + msip_4: MSIP_4, + _reserved5: [u8; 0x3fec], + mtimecmp_0: MTIMECMP_0, + mtimecmp_1: MTIMECMP_1, + mtimecmp_2: MTIMECMP_2, + mtimecmp_3: MTIMECMP_3, + mtimecmp_4: MTIMECMP_4, + _reserved10: [u8; 0x7fd0], + mtime: MTIME, +} +impl RegisterBlock { #[doc = "0x00 - MSIP Register for hart 0"] - pub msip_0: MSIP_0, + #[inline(always)] + pub const fn msip_0(&self) -> &MSIP_0 { + &self.msip_0 + } #[doc = "0x04 - MSIP Register for hart 1"] - pub msip_1: MSIP_1, + #[inline(always)] + pub const fn msip_1(&self) -> &MSIP_1 { + &self.msip_1 + } #[doc = "0x08 - MSIP Register for hart 2"] - pub msip_2: MSIP_2, + #[inline(always)] + pub const fn msip_2(&self) -> &MSIP_2 { + &self.msip_2 + } #[doc = "0x0c - MSIP Register for hart 3"] - pub msip_3: MSIP_3, + #[inline(always)] + pub const fn msip_3(&self) -> &MSIP_3 { + &self.msip_3 + } #[doc = "0x10 - MSIP Register for hart 4"] - pub msip_4: MSIP_4, - _reserved5: [u8; 0x3fec], + #[inline(always)] + pub const fn msip_4(&self) -> &MSIP_4 { + &self.msip_4 + } #[doc = "0x4000..0x4008 - MTIMECMP Register for hart 0"] - pub mtimecmp_0: MTIMECMP_0, + #[inline(always)] + pub const fn mtimecmp_0(&self) -> &MTIMECMP_0 { + &self.mtimecmp_0 + } #[doc = "0x4008..0x4010 - MTIMECMP Register for hart 1"] - pub mtimecmp_1: MTIMECMP_1, + #[inline(always)] + pub const fn mtimecmp_1(&self) -> &MTIMECMP_1 { + &self.mtimecmp_1 + } #[doc = "0x4010..0x4018 - MTIMECMP Register for hart 2"] - pub mtimecmp_2: MTIMECMP_2, + #[inline(always)] + pub const fn mtimecmp_2(&self) -> &MTIMECMP_2 { + &self.mtimecmp_2 + } #[doc = "0x4018..0x4020 - MTIMECMP Register for hart 3"] - pub mtimecmp_3: MTIMECMP_3, + #[inline(always)] + pub const fn mtimecmp_3(&self) -> &MTIMECMP_3 { + &self.mtimecmp_3 + } #[doc = "0x4020..0x4028 - MTIMECMP Register for hart 4"] - pub mtimecmp_4: MTIMECMP_4, - _reserved10: [u8; 0x7fd0], + #[inline(always)] + pub const fn mtimecmp_4(&self) -> &MTIMECMP_4 { + &self.mtimecmp_4 + } #[doc = "0xbff8..0xc000 - MTIME Register"] - pub mtime: MTIME, + #[inline(always)] + pub const fn mtime(&self) -> &MTIME { + &self.mtime + } } -#[doc = "msip_0 (rw) register accessor: MSIP Register for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msip_0`] +#[doc = "msip_0 (rw) register accessor: MSIP Register for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msip_0`] module"] pub type MSIP_0 = crate::Reg; #[doc = "MSIP Register for hart 0"] pub mod msip_0; -#[doc = "msip_1 (rw) register accessor: MSIP Register for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msip_1`] +#[doc = "msip_1 (rw) register accessor: MSIP Register for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msip_1`] module"] pub type MSIP_1 = crate::Reg; #[doc = "MSIP Register for hart 1"] pub mod msip_1; -#[doc = "msip_2 (rw) register accessor: MSIP Register for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msip_2`] +#[doc = "msip_2 (rw) register accessor: MSIP Register for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msip_2`] module"] pub type MSIP_2 = crate::Reg; #[doc = "MSIP Register for hart 2"] pub mod msip_2; -#[doc = "msip_3 (rw) register accessor: MSIP Register for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msip_3`] +#[doc = "msip_3 (rw) register accessor: MSIP Register for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msip_3`] module"] pub type MSIP_3 = crate::Reg; #[doc = "MSIP Register for hart 3"] pub mod msip_3; -#[doc = "msip_4 (rw) register accessor: MSIP Register for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msip_4`] +#[doc = "msip_4 (rw) register accessor: MSIP Register for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msip_4`] module"] pub type MSIP_4 = crate::Reg; #[doc = "MSIP Register for hart 4"] pub mod msip_4; -#[doc = "mtimecmp_0 (rw) register accessor: MTIMECMP Register for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mtimecmp_0`] +#[doc = "mtimecmp_0 (rw) register accessor: MTIMECMP Register for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimecmp_0`] module"] pub type MTIMECMP_0 = crate::Reg; #[doc = "MTIMECMP Register for hart 0"] pub mod mtimecmp_0; -#[doc = "mtimecmp_1 (rw) register accessor: MTIMECMP Register for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mtimecmp_1`] +#[doc = "mtimecmp_1 (rw) register accessor: MTIMECMP Register for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimecmp_1`] module"] pub type MTIMECMP_1 = crate::Reg; #[doc = "MTIMECMP Register for hart 1"] pub mod mtimecmp_1; -#[doc = "mtimecmp_2 (rw) register accessor: MTIMECMP Register for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mtimecmp_2`] +#[doc = "mtimecmp_2 (rw) register accessor: MTIMECMP Register for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimecmp_2`] module"] pub type MTIMECMP_2 = crate::Reg; #[doc = "MTIMECMP Register for hart 2"] pub mod mtimecmp_2; -#[doc = "mtimecmp_3 (rw) register accessor: MTIMECMP Register for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mtimecmp_3`] +#[doc = "mtimecmp_3 (rw) register accessor: MTIMECMP Register for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimecmp_3`] module"] pub type MTIMECMP_3 = crate::Reg; #[doc = "MTIMECMP Register for hart 3"] pub mod mtimecmp_3; -#[doc = "mtimecmp_4 (rw) register accessor: MTIMECMP Register for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mtimecmp_4`] +#[doc = "mtimecmp_4 (rw) register accessor: MTIMECMP Register for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimecmp_4`] module"] pub type MTIMECMP_4 = crate::Reg; #[doc = "MTIMECMP Register for hart 4"] pub mod mtimecmp_4; -#[doc = "mtime (rw) register accessor: MTIME Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtime::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtime::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mtime`] +#[doc = "mtime (rw) register accessor: MTIME Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtime::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtime::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtime`] module"] pub type MTIME = crate::Reg; #[doc = "MTIME Register"] diff --git a/jh7110-vf2-12a-pac/src/clint/msip_0.rs b/jh7110-vf2-12a-pac/src/clint/msip_0.rs index 0b60c42..a61378a 100644 --- a/jh7110-vf2-12a-pac/src/clint/msip_0.rs +++ b/jh7110-vf2-12a-pac/src/clint/msip_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/clint/msip_1.rs b/jh7110-vf2-12a-pac/src/clint/msip_1.rs index 66fc898..6fa7e52 100644 --- a/jh7110-vf2-12a-pac/src/clint/msip_1.rs +++ b/jh7110-vf2-12a-pac/src/clint/msip_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/clint/msip_2.rs b/jh7110-vf2-12a-pac/src/clint/msip_2.rs index 51fa11e..a089709 100644 --- a/jh7110-vf2-12a-pac/src/clint/msip_2.rs +++ b/jh7110-vf2-12a-pac/src/clint/msip_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/clint/msip_3.rs b/jh7110-vf2-12a-pac/src/clint/msip_3.rs index f1a6a08..3a389fe 100644 --- a/jh7110-vf2-12a-pac/src/clint/msip_3.rs +++ b/jh7110-vf2-12a-pac/src/clint/msip_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/clint/msip_4.rs b/jh7110-vf2-12a-pac/src/clint/msip_4.rs index 23015f8..7ec7c2c 100644 --- a/jh7110-vf2-12a-pac/src/clint/msip_4.rs +++ b/jh7110-vf2-12a-pac/src/clint/msip_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/clint/mtime.rs b/jh7110-vf2-12a-pac/src/clint/mtime.rs index c5a3aa2..3e976b3 100644 --- a/jh7110-vf2-12a-pac/src/clint/mtime.rs +++ b/jh7110-vf2-12a-pac/src/clint/mtime.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u64) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/clint/mtimecmp_0.rs b/jh7110-vf2-12a-pac/src/clint/mtimecmp_0.rs index 611f411..9a1b9eb 100644 --- a/jh7110-vf2-12a-pac/src/clint/mtimecmp_0.rs +++ b/jh7110-vf2-12a-pac/src/clint/mtimecmp_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u64) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/clint/mtimecmp_1.rs b/jh7110-vf2-12a-pac/src/clint/mtimecmp_1.rs index 176bbf9..c12b004 100644 --- a/jh7110-vf2-12a-pac/src/clint/mtimecmp_1.rs +++ b/jh7110-vf2-12a-pac/src/clint/mtimecmp_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u64) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/clint/mtimecmp_2.rs b/jh7110-vf2-12a-pac/src/clint/mtimecmp_2.rs index bbb635b..5595999 100644 --- a/jh7110-vf2-12a-pac/src/clint/mtimecmp_2.rs +++ b/jh7110-vf2-12a-pac/src/clint/mtimecmp_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u64) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/clint/mtimecmp_3.rs b/jh7110-vf2-12a-pac/src/clint/mtimecmp_3.rs index 4fac76a..e646879 100644 --- a/jh7110-vf2-12a-pac/src/clint/mtimecmp_3.rs +++ b/jh7110-vf2-12a-pac/src/clint/mtimecmp_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u64) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/clint/mtimecmp_4.rs b/jh7110-vf2-12a-pac/src/clint/mtimecmp_4.rs index 5db21c3..483d6bf 100644 --- a/jh7110-vf2-12a-pac/src/clint/mtimecmp_4.rs +++ b/jh7110-vf2-12a-pac/src/clint/mtimecmp_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u64) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/generic.rs b/jh7110-vf2-12a-pac/src/generic.rs index 551a0ae..59c8e74 100644 --- a/jh7110-vf2-12a-pac/src/generic.rs +++ b/jh7110-vf2-12a-pac/src/generic.rs @@ -243,7 +243,7 @@ pub type R = raw::R; impl R { #[doc = " Reads raw bits from register."] #[inline(always)] - pub fn bits(&self) -> REG::Ux { + pub const fn bits(&self) -> REG::Ux { self.bits } } @@ -271,7 +271,7 @@ pub type BitReader = raw::BitReader; impl FieldReader { #[doc = " Reads raw bits from field."] #[inline(always)] - pub fn bits(&self) -> FI::Ux { + pub const fn bits(&self) -> FI::Ux { self.bits } } @@ -297,17 +297,17 @@ where impl BitReader { #[doc = " Value of the field as raw bits."] #[inline(always)] - pub fn bit(&self) -> bool { + pub const fn bit(&self) -> bool { self.bits } #[doc = " Returns `true` if the bit is clear (0)."] #[inline(always)] - pub fn bit_is_clear(&self) -> bool { + pub const fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = " Returns `true` if the bit is set (1)."] #[inline(always)] - pub fn bit_is_set(&self) -> bool { + pub const fn bit_is_set(&self) -> bool { self.bit() } } @@ -316,55 +316,103 @@ pub struct Safe; #[doc(hidden)] pub struct Unsafe; #[doc = " Write field Proxy with unsafe `bits`"] -pub type FieldWriter<'a, REG, const WI: u8, const O: u8, FI = u8> = - raw::FieldWriter<'a, REG, WI, O, FI, Unsafe>; +pub type FieldWriter<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Unsafe>; #[doc = " Write field Proxy with safe `bits`"] -pub type FieldWriterSafe<'a, REG, const WI: u8, const O: u8, FI = u8> = - raw::FieldWriter<'a, REG, WI, O, FI, Safe>; -impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriter<'a, REG, WI, OF, FI> +pub type FieldWriterSafe<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Safe>; +impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI> where REG: Writable + RegisterSpec, FI: FieldSpec, + REG::Ux: From, { #[doc = " Field width"] pub const WIDTH: u8 = WI; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + WI + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + unsafe { self.bits(FI::Ux::from(variant)) } + } } -impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriterSafe<'a, REG, WI, OF, FI> +impl<'a, REG, const WI: u8, FI> FieldWriterSafe<'a, REG, WI, FI> where REG: Writable + RegisterSpec, FI: FieldSpec, + REG::Ux: From, { #[doc = " Field width"] pub const WIDTH: u8 = WI; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + WI + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + self.bits(FI::Ux::from(variant)) + } } macro_rules! bit_proxy { ($ writer : ident , $ mwv : ident) => { #[doc(hidden)] pub struct $mwv; #[doc = " Bit-wise write field proxy"] - pub type $writer<'a, REG, const O: u8, FI = bool> = raw::BitWriter<'a, REG, O, FI, $mwv>; - impl<'a, REG, const OF: u8, FI> $writer<'a, REG, OF, FI> + pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>; + impl<'a, REG, FI> $writer<'a, REG, FI> where REG: Writable + RegisterSpec, bool: From, { #[doc = " Field width"] pub const WIDTH: u8 = 1; - } - }; -} -macro_rules! impl_bit_proxy { - ($ writer : ident) => { - impl<'a, REG, const OF: u8, FI> $writer<'a, REG, OF, FI> - where - REG: Writable + RegisterSpec, - bool: From, - { + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + Self::WIDTH + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } #[doc = " Writes bit to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << OF); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << OF; + self.w.bits &= !(REG::Ux::one() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o; self.w } #[doc = " Writes `variant` to the field"] @@ -382,56 +430,7 @@ bit_proxy!(BitWriter1C, Bit1C); bit_proxy!(BitWriter0S, Bit0S); bit_proxy!(BitWriter1T, Bit1T); bit_proxy!(BitWriter0T, Bit0T); -impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriter<'a, REG, WI, OF, FI> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, -{ - #[doc = " Writes raw bits to the field"] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { - self.w.bits &= !(REG::Ux::mask::() << OF); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut W { - unsafe { self.bits(FI::Ux::from(variant)) } - } -} -impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriterSafe<'a, REG, WI, OF, FI> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, -{ - #[doc = " Writes raw bits to the field"] - #[inline(always)] - pub fn bits(self, value: FI::Ux) -> &'a mut W { - self.w.bits &= !(REG::Ux::mask::() << OF); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut W { - self.bits(FI::Ux::from(variant)) - } -} -impl_bit_proxy!(BitWriter); -impl_bit_proxy!(BitWriter1S); -impl_bit_proxy!(BitWriter0C); -impl_bit_proxy!(BitWriter1C); -impl_bit_proxy!(BitWriter0S); -impl_bit_proxy!(BitWriter1T); -impl_bit_proxy!(BitWriter0T); -impl<'a, REG, const OF: u8, FI> BitWriter<'a, REG, OF, FI> +impl<'a, REG, FI> BitWriter<'a, REG, FI> where REG: Writable + RegisterSpec, bool: From, @@ -439,17 +438,17 @@ where #[doc = " Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { - self.w.bits |= REG::Ux::one() << OF; + self.w.bits |= REG::Ux::one() << self.o; self.w } #[doc = " Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << OF); + self.w.bits &= !(REG::Ux::one() << self.o); self.w } } -impl<'a, REG, const OF: u8, FI> BitWriter1S<'a, REG, OF, FI> +impl<'a, REG, FI> BitWriter1S<'a, REG, FI> where REG: Writable + RegisterSpec, bool: From, @@ -457,11 +456,11 @@ where #[doc = " Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { - self.w.bits |= REG::Ux::one() << OF; + self.w.bits |= REG::Ux::one() << self.o; self.w } } -impl<'a, REG, const OF: u8, FI> BitWriter0C<'a, REG, OF, FI> +impl<'a, REG, FI> BitWriter0C<'a, REG, FI> where REG: Writable + RegisterSpec, bool: From, @@ -469,11 +468,11 @@ where #[doc = " Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << OF); + self.w.bits &= !(REG::Ux::one() << self.o); self.w } } -impl<'a, REG, const OF: u8, FI> BitWriter1C<'a, REG, OF, FI> +impl<'a, REG, FI> BitWriter1C<'a, REG, FI> where REG: Writable + RegisterSpec, bool: From, @@ -481,11 +480,11 @@ where #[doc = "Clears the field bit by passing one"] #[inline(always)] pub fn clear_bit_by_one(self) -> &'a mut W { - self.w.bits |= REG::Ux::one() << OF; + self.w.bits |= REG::Ux::one() << self.o; self.w } } -impl<'a, REG, const OF: u8, FI> BitWriter0S<'a, REG, OF, FI> +impl<'a, REG, FI> BitWriter0S<'a, REG, FI> where REG: Writable + RegisterSpec, bool: From, @@ -493,11 +492,11 @@ where #[doc = "Sets the field bit by passing zero"] #[inline(always)] pub fn set_bit_by_zero(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << OF); + self.w.bits &= !(REG::Ux::one() << self.o); self.w } } -impl<'a, REG, const OF: u8, FI> BitWriter1T<'a, REG, OF, FI> +impl<'a, REG, FI> BitWriter1T<'a, REG, FI> where REG: Writable + RegisterSpec, bool: From, @@ -505,11 +504,11 @@ where #[doc = "Toggle the field bit by passing one"] #[inline(always)] pub fn toggle_bit(self) -> &'a mut W { - self.w.bits |= REG::Ux::one() << OF; + self.w.bits |= REG::Ux::one() << self.o; self.w } } -impl<'a, REG, const OF: u8, FI> BitWriter0T<'a, REG, OF, FI> +impl<'a, REG, FI> BitWriter0T<'a, REG, FI> where REG: Writable + RegisterSpec, bool: From, @@ -517,7 +516,7 @@ where #[doc = "Toggle the field bit by passing zero"] #[inline(always)] pub fn toggle_bit(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << OF); + self.w.bits &= !(REG::Ux::one() << self.o); self.w } } diff --git a/jh7110-vf2-12a-pac/src/generic/raw.rs b/jh7110-vf2-12a-pac/src/generic/raw.rs index 74e7752..81f5779 100644 --- a/jh7110-vf2-12a-pac/src/generic/raw.rs +++ b/jh7110-vf2-12a-pac/src/generic/raw.rs @@ -19,7 +19,7 @@ impl FieldReader { #[doc = " Creates a new instance of the reader."] #[allow(unused)] #[inline(always)] - pub(crate) fn new(bits: FI::Ux) -> Self { + pub(crate) const fn new(bits: FI::Ux) -> Self { Self { bits, _reg: marker::PhantomData, @@ -34,22 +34,23 @@ impl BitReader { #[doc = " Creates a new instance of the reader."] #[allow(unused)] #[inline(always)] - pub(crate) fn new(bits: bool) -> Self { + pub(crate) const fn new(bits: bool) -> Self { Self { bits, _reg: marker::PhantomData, } } } -pub struct FieldWriter<'a, REG, const WI: u8, const O: u8, FI = u8, Safety = Unsafe> +pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> where REG: Writable + RegisterSpec, FI: FieldSpec, { pub(crate) w: &'a mut W, + pub(crate) o: u8, _field: marker::PhantomData<(FI, Safety)>, } -impl<'a, REG, const WI: u8, const O: u8, FI, Safety> FieldWriter<'a, REG, WI, O, FI, Safety> +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> where REG: Writable + RegisterSpec, FI: FieldSpec, @@ -57,22 +58,24 @@ where #[doc = " Creates a new instance of the writer"] #[allow(unused)] #[inline(always)] - pub(crate) fn new(w: &'a mut W) -> Self { + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { Self { w, + o, _field: marker::PhantomData, } } } -pub struct BitWriter<'a, REG, const O: u8, FI = bool, M = BitM> +pub struct BitWriter<'a, REG, FI = bool, M = BitM> where REG: Writable + RegisterSpec, bool: From, { pub(crate) w: &'a mut W, + pub(crate) o: u8, _field: marker::PhantomData<(FI, M)>, } -impl<'a, REG, const O: u8, FI, M> BitWriter<'a, REG, O, FI, M> +impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M> where REG: Writable + RegisterSpec, bool: From, @@ -80,9 +83,10 @@ where #[doc = " Creates a new instance of the writer"] #[allow(unused)] #[inline(always)] - pub(crate) fn new(w: &'a mut W) -> Self { + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { Self { w, + o, _field: marker::PhantomData, } } diff --git a/jh7110-vf2-12a-pac/src/i2c0.rs b/jh7110-vf2-12a-pac/src/i2c0.rs index d0fe76a..fdffe28 100644 --- a/jh7110-vf2-12a-pac/src/i2c0.rs +++ b/jh7110-vf2-12a-pac/src/i2c0.rs @@ -1,266 +1,416 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + con: CON, + tar: TAR, + sar: SAR, + _reserved3: [u8; 0x04], + data_cmd: DATA_CMD, + ss_scl_hcnt: SS_SCL_HCNT, + ss_scl_lcnt: SS_SCL_LCNT, + fs_scl_hcnt: FS_SCL_HCNT, + fs_scl_lcnt: FS_SCL_LCNT, + hs_scl_hcnt: HS_SCL_HCNT, + hs_scl_lcnt: HS_SCL_LCNT, + intr_stat: INTR_STAT, + intr_mask: INTR_MASK, + raw_intr_stat: RAW_INTR_STAT, + rx_tl: RX_TL, + tx_tl: TX_TL, + clr_intr: CLR_INTR, + clr_rx_under: CLR_RX_UNDER, + clr_rx_over: CLR_RX_OVER, + clr_tx_over: CLR_TX_OVER, + clr_rd_req: CLR_RD_REQ, + clr_tx_abrt: CLR_TX_ABRT, + clr_rx_done: CLR_RX_DONE, + clr_activity: CLR_ACTIVITY, + clr_stop_det: CLR_STOP_DET, + clr_start_det: CLR_START_DET, + clr_gen_call: CLR_GEN_CALL, + enable: ENABLE, + status: STATUS, + txflr: TXFLR, + rxflr: RXFLR, + sda_hold: SDA_HOLD, + tx_abrt_source: TX_ABRT_SOURCE, + _reserved32: [u8; 0x18], + enable_status: ENABLE_STATUS, + _reserved33: [u8; 0x08], + clr_restart_det: CLR_RESTART_DET, + _reserved34: [u8; 0x48], + comp_param_1: COMP_PARAM_1, + comp_version: COMP_VERSION, + comp_type: COMP_TYPE, +} +impl RegisterBlock { #[doc = "0x00 - DesignWare I2C CON"] - pub con: CON, + #[inline(always)] + pub const fn con(&self) -> &CON { + &self.con + } #[doc = "0x04 - DesignWare I2C TAR"] - pub tar: TAR, + #[inline(always)] + pub const fn tar(&self) -> &TAR { + &self.tar + } #[doc = "0x08 - DesignWare I2C SAR"] - pub sar: SAR, - _reserved3: [u8; 0x04], + #[inline(always)] + pub const fn sar(&self) -> &SAR { + &self.sar + } #[doc = "0x10 - DesignWare I2C Data Command"] - pub data_cmd: DATA_CMD, + #[inline(always)] + pub const fn data_cmd(&self) -> &DATA_CMD { + &self.data_cmd + } #[doc = "0x14 - DesignWare I2C SS SCL HCNT"] - pub ss_scl_hcnt: SS_SCL_HCNT, + #[inline(always)] + pub const fn ss_scl_hcnt(&self) -> &SS_SCL_HCNT { + &self.ss_scl_hcnt + } #[doc = "0x18 - DesignWare I2C SS SCL LCNT"] - pub ss_scl_lcnt: SS_SCL_LCNT, + #[inline(always)] + pub const fn ss_scl_lcnt(&self) -> &SS_SCL_LCNT { + &self.ss_scl_lcnt + } #[doc = "0x1c - DesignWare I2C FS SCL HCNT"] - pub fs_scl_hcnt: FS_SCL_HCNT, + #[inline(always)] + pub const fn fs_scl_hcnt(&self) -> &FS_SCL_HCNT { + &self.fs_scl_hcnt + } #[doc = "0x20 - DesignWare I2C FS SCL LCNT"] - pub fs_scl_lcnt: FS_SCL_LCNT, + #[inline(always)] + pub const fn fs_scl_lcnt(&self) -> &FS_SCL_LCNT { + &self.fs_scl_lcnt + } #[doc = "0x24 - DesignWare I2C HS SCL HCNT"] - pub hs_scl_hcnt: HS_SCL_HCNT, + #[inline(always)] + pub const fn hs_scl_hcnt(&self) -> &HS_SCL_HCNT { + &self.hs_scl_hcnt + } #[doc = "0x28 - DesignWare I2C HS SCL LCNT"] - pub hs_scl_lcnt: HS_SCL_LCNT, + #[inline(always)] + pub const fn hs_scl_lcnt(&self) -> &HS_SCL_LCNT { + &self.hs_scl_lcnt + } #[doc = "0x2c - DesignWare I2C Interrupt Status"] - pub intr_stat: INTR_STAT, + #[inline(always)] + pub const fn intr_stat(&self) -> &INTR_STAT { + &self.intr_stat + } #[doc = "0x30 - DesignWare I2C Interrupt Mask"] - pub intr_mask: INTR_MASK, + #[inline(always)] + pub const fn intr_mask(&self) -> &INTR_MASK { + &self.intr_mask + } #[doc = "0x34 - DesignWare I2C Raw Interrupt Status"] - pub raw_intr_stat: RAW_INTR_STAT, + #[inline(always)] + pub const fn raw_intr_stat(&self) -> &RAW_INTR_STAT { + &self.raw_intr_stat + } #[doc = "0x38 - DesignWare I2C RX TL"] - pub rx_tl: RX_TL, + #[inline(always)] + pub const fn rx_tl(&self) -> &RX_TL { + &self.rx_tl + } #[doc = "0x3c - DesignWare I2C TX TL"] - pub tx_tl: TX_TL, + #[inline(always)] + pub const fn tx_tl(&self) -> &TX_TL { + &self.tx_tl + } #[doc = "0x40 - DesignWare I2C Clear Interrrupt"] - pub clr_intr: CLR_INTR, + #[inline(always)] + pub const fn clr_intr(&self) -> &CLR_INTR { + &self.clr_intr + } #[doc = "0x44 - DesignWare I2C Clear RX Underrun"] - pub clr_rx_under: CLR_RX_UNDER, + #[inline(always)] + pub const fn clr_rx_under(&self) -> &CLR_RX_UNDER { + &self.clr_rx_under + } #[doc = "0x48 - DesignWare I2C Clear RX Overrun"] - pub clr_rx_over: CLR_RX_OVER, + #[inline(always)] + pub const fn clr_rx_over(&self) -> &CLR_RX_OVER { + &self.clr_rx_over + } #[doc = "0x4c - DesignWare I2C Clear TX Overrun"] - pub clr_tx_over: CLR_TX_OVER, + #[inline(always)] + pub const fn clr_tx_over(&self) -> &CLR_TX_OVER { + &self.clr_tx_over + } #[doc = "0x50 - DesignWare I2C Clear Read Request"] - pub clr_rd_req: CLR_RD_REQ, + #[inline(always)] + pub const fn clr_rd_req(&self) -> &CLR_RD_REQ { + &self.clr_rd_req + } #[doc = "0x54 - DesignWare I2C Clear TX Abort"] - pub clr_tx_abrt: CLR_TX_ABRT, + #[inline(always)] + pub const fn clr_tx_abrt(&self) -> &CLR_TX_ABRT { + &self.clr_tx_abrt + } #[doc = "0x58 - DesignWare I2C Clear RX Done"] - pub clr_rx_done: CLR_RX_DONE, + #[inline(always)] + pub const fn clr_rx_done(&self) -> &CLR_RX_DONE { + &self.clr_rx_done + } #[doc = "0x5c - DesignWare I2C Clear Activity"] - pub clr_activity: CLR_ACTIVITY, + #[inline(always)] + pub const fn clr_activity(&self) -> &CLR_ACTIVITY { + &self.clr_activity + } #[doc = "0x60 - DesignWare I2C Clear Stop DET"] - pub clr_stop_det: CLR_STOP_DET, + #[inline(always)] + pub const fn clr_stop_det(&self) -> &CLR_STOP_DET { + &self.clr_stop_det + } #[doc = "0x64 - DesignWare I2C Clear Start DET"] - pub clr_start_det: CLR_START_DET, + #[inline(always)] + pub const fn clr_start_det(&self) -> &CLR_START_DET { + &self.clr_start_det + } #[doc = "0x68 - DesignWare I2C Clear General Call"] - pub clr_gen_call: CLR_GEN_CALL, + #[inline(always)] + pub const fn clr_gen_call(&self) -> &CLR_GEN_CALL { + &self.clr_gen_call + } #[doc = "0x6c - DesignWare I2C Enable"] - pub enable: ENABLE, + #[inline(always)] + pub const fn enable(&self) -> &ENABLE { + &self.enable + } #[doc = "0x70 - DesignWare I2C Status"] - pub status: STATUS, + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } #[doc = "0x74 - DesignWare I2C TX Failure"] - pub txflr: TXFLR, + #[inline(always)] + pub const fn txflr(&self) -> &TXFLR { + &self.txflr + } #[doc = "0x78 - DesignWare I2C RX Failure"] - pub rxflr: RXFLR, + #[inline(always)] + pub const fn rxflr(&self) -> &RXFLR { + &self.rxflr + } #[doc = "0x7c - DesignWare I2C SDA Hold"] - pub sda_hold: SDA_HOLD, + #[inline(always)] + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold + } #[doc = "0x80 - DesignWare I2C TX Abort Source"] - pub tx_abrt_source: TX_ABRT_SOURCE, - _reserved32: [u8; 0x18], + #[inline(always)] + pub const fn tx_abrt_source(&self) -> &TX_ABRT_SOURCE { + &self.tx_abrt_source + } #[doc = "0x9c - DesignWare I2C Enable Status"] - pub enable_status: ENABLE_STATUS, - _reserved33: [u8; 0x08], + #[inline(always)] + pub const fn enable_status(&self) -> &ENABLE_STATUS { + &self.enable_status + } #[doc = "0xa8 - DesignWare I2C Clear Restart DET"] - pub clr_restart_det: CLR_RESTART_DET, - _reserved34: [u8; 0x48], + #[inline(always)] + pub const fn clr_restart_det(&self) -> &CLR_RESTART_DET { + &self.clr_restart_det + } #[doc = "0xf4 - DesignWare I2C Compatibility Parameter 1"] - pub comp_param_1: COMP_PARAM_1, + #[inline(always)] + pub const fn comp_param_1(&self) -> &COMP_PARAM_1 { + &self.comp_param_1 + } #[doc = "0xf8 - DesignWare I2C Compatibility Version"] - pub comp_version: COMP_VERSION, + #[inline(always)] + pub const fn comp_version(&self) -> &COMP_VERSION { + &self.comp_version + } #[doc = "0xfc - DesignWare I2C Compatibility Type"] - pub comp_type: COMP_TYPE, + #[inline(always)] + pub const fn comp_type(&self) -> &COMP_TYPE { + &self.comp_type + } } -#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`con`] +#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@con`] module"] pub type CON = crate::Reg; #[doc = "DesignWare I2C CON"] pub mod con; -#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tar`] +#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar`] module"] pub type TAR = crate::Reg; #[doc = "DesignWare I2C TAR"] pub mod tar; -#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sar`] +#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`] module"] pub type SAR = crate::Reg; #[doc = "DesignWare I2C SAR"] pub mod sar; -#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`data_cmd`] +#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_cmd`] module"] pub type DATA_CMD = crate::Reg; #[doc = "DesignWare I2C Data Command"] pub mod data_cmd; -#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_hcnt`] +#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_hcnt`] module"] pub type SS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL HCNT"] pub mod ss_scl_hcnt; -#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_lcnt`] +#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_lcnt`] module"] pub type SS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL LCNT"] pub mod ss_scl_lcnt; -#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_hcnt`] +#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_hcnt`] module"] pub type FS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL HCNT"] pub mod fs_scl_hcnt; -#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_lcnt`] +#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_lcnt`] module"] pub type FS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL LCNT"] pub mod fs_scl_lcnt; -#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_hcnt`] +#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_hcnt`] module"] pub type HS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL HCNT"] pub mod hs_scl_hcnt; -#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_lcnt`] +#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_lcnt`] module"] pub type HS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL LCNT"] pub mod hs_scl_lcnt; -#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_stat`] +#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"] pub type INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Interrupt Status"] pub mod intr_stat; -#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_mask`] +#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mask`] module"] pub type INTR_MASK = crate::Reg; #[doc = "DesignWare I2C Interrupt Mask"] pub mod intr_mask; -#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`raw_intr_stat`] +#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"] pub type RAW_INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Raw Interrupt Status"] pub mod raw_intr_stat; -#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rx_tl`] +#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tl`] module"] pub type RX_TL = crate::Reg; #[doc = "DesignWare I2C RX TL"] pub mod rx_tl; -#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_tl`] +#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_tl`] module"] pub type TX_TL = crate::Reg; #[doc = "DesignWare I2C TX TL"] pub mod tx_tl; -#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_intr`] +#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_intr`] module"] pub type CLR_INTR = crate::Reg; #[doc = "DesignWare I2C Clear Interrrupt"] pub mod clr_intr; -#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_under`] +#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_under`] module"] pub type CLR_RX_UNDER = crate::Reg; #[doc = "DesignWare I2C Clear RX Underrun"] pub mod clr_rx_under; -#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_over`] +#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_over`] module"] pub type CLR_RX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear RX Overrun"] pub mod clr_rx_over; -#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_over`] +#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_over`] module"] pub type CLR_TX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear TX Overrun"] pub mod clr_tx_over; -#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rd_req`] +#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rd_req`] module"] pub type CLR_RD_REQ = crate::Reg; #[doc = "DesignWare I2C Clear Read Request"] pub mod clr_rd_req; -#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_abrt`] +#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_abrt`] module"] pub type CLR_TX_ABRT = crate::Reg; #[doc = "DesignWare I2C Clear TX Abort"] pub mod clr_tx_abrt; -#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_done`] +#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_done`] module"] pub type CLR_RX_DONE = crate::Reg; #[doc = "DesignWare I2C Clear RX Done"] pub mod clr_rx_done; -#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_activity`] +#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_activity`] module"] pub type CLR_ACTIVITY = crate::Reg; #[doc = "DesignWare I2C Clear Activity"] pub mod clr_activity; -#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_stop_det`] +#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_stop_det`] module"] pub type CLR_STOP_DET = crate::Reg; #[doc = "DesignWare I2C Clear Stop DET"] pub mod clr_stop_det; -#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_start_det`] +#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_start_det`] module"] pub type CLR_START_DET = crate::Reg; #[doc = "DesignWare I2C Clear Start DET"] pub mod clr_start_det; -#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_gen_call`] +#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_gen_call`] module"] pub type CLR_GEN_CALL = crate::Reg; #[doc = "DesignWare I2C Clear General Call"] pub mod clr_gen_call; -#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable`] +#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] pub type ENABLE = crate::Reg; #[doc = "DesignWare I2C Enable"] pub mod enable; -#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`status`] +#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] pub type STATUS = crate::Reg; #[doc = "DesignWare I2C Status"] pub mod status; -#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txflr`] +#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txflr`] module"] pub type TXFLR = crate::Reg; #[doc = "DesignWare I2C TX Failure"] pub mod txflr; -#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxflr`] +#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxflr`] module"] pub type RXFLR = crate::Reg; #[doc = "DesignWare I2C RX Failure"] pub mod rxflr; -#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sda_hold`] +#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] pub type SDA_HOLD = crate::Reg; #[doc = "DesignWare I2C SDA Hold"] pub mod sda_hold; -#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_abrt_source`] +#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_abrt_source`] module"] pub type TX_ABRT_SOURCE = crate::Reg; #[doc = "DesignWare I2C TX Abort Source"] pub mod tx_abrt_source; -#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_status`] +#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_status`] module"] pub type ENABLE_STATUS = crate::Reg; #[doc = "DesignWare I2C Enable Status"] pub mod enable_status; -#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_restart_det`] +#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_restart_det`] module"] pub type CLR_RESTART_DET = crate::Reg; #[doc = "DesignWare I2C Clear Restart DET"] pub mod clr_restart_det; -#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_param_1`] +#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_param_1`] module"] pub type COMP_PARAM_1 = crate::Reg; #[doc = "DesignWare I2C Compatibility Parameter 1"] pub mod comp_param_1; -#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_version`] +#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_version`] module"] pub type COMP_VERSION = crate::Reg; #[doc = "DesignWare I2C Compatibility Version"] pub mod comp_version; -#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_type`] +#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_type`] module"] pub type COMP_TYPE = crate::Reg; #[doc = "DesignWare I2C Compatibility Type"] diff --git a/jh7110-vf2-12a-pac/src/i2c0/clr_activity.rs b/jh7110-vf2-12a-pac/src/i2c0/clr_activity.rs index d26bb80..1ee2297 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/clr_activity.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/clr_activity.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_activity` reader - clr_activity"] pub type CLR_ACTIVITY_R = crate::FieldReader; #[doc = "Field `clr_activity` writer - clr_activity"] -pub type CLR_ACTIVITY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_ACTIVITY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] #[must_use] - pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { - CLR_ACTIVITY_W::new(self) + pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { + CLR_ACTIVITY_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/clr_gen_call.rs b/jh7110-vf2-12a-pac/src/i2c0/clr_gen_call.rs index a9ea5af..4a7c5ba 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/clr_gen_call.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/clr_gen_call.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_gen_call` reader - clr_gen_call"] pub type CLR_GEN_CALL_R = crate::FieldReader; #[doc = "Field `clr_gen_call` writer - clr_gen_call"] -pub type CLR_GEN_CALL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_GEN_CALL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] #[must_use] - pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { - CLR_GEN_CALL_W::new(self) + pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { + CLR_GEN_CALL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/clr_intr.rs b/jh7110-vf2-12a-pac/src/i2c0/clr_intr.rs index a7daf57..cf57b09 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/clr_intr.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/clr_intr.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/clr_rd_req.rs b/jh7110-vf2-12a-pac/src/i2c0/clr_rd_req.rs index e275da1..4beae9d 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/clr_rd_req.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/clr_rd_req.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rd_req` reader - clr_rd_req"] pub type CLR_RD_REQ_R = crate::FieldReader; #[doc = "Field `clr_rd_req` writer - clr_rd_req"] -pub type CLR_RD_REQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RD_REQ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] #[must_use] - pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { - CLR_RD_REQ_W::new(self) + pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { + CLR_RD_REQ_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/clr_restart_det.rs b/jh7110-vf2-12a-pac/src/i2c0/clr_restart_det.rs index 5be7f5d..88d193c 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/clr_restart_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/clr_restart_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_restart_det` reader - clr_restart_det"] pub type CLR_RESTART_DET_R = crate::FieldReader; #[doc = "Field `clr_restart_det` writer - clr_restart_det"] -pub type CLR_RESTART_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RESTART_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] #[must_use] - pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { - CLR_RESTART_DET_W::new(self) + pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { + CLR_RESTART_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/clr_rx_done.rs b/jh7110-vf2-12a-pac/src/i2c0/clr_rx_done.rs index 02d83c5..7e14a3f 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/clr_rx_done.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/clr_rx_done.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_done` reader - clr_rx_done"] pub type CLR_RX_DONE_R = crate::FieldReader; #[doc = "Field `clr_rx_done` writer - clr_rx_done"] -pub type CLR_RX_DONE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_DONE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] #[must_use] - pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { - CLR_RX_DONE_W::new(self) + pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { + CLR_RX_DONE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/clr_rx_over.rs b/jh7110-vf2-12a-pac/src/i2c0/clr_rx_over.rs index 6d7ff4e..2302921 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/clr_rx_over.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/clr_rx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_over` reader - clr_rx_over"] pub type CLR_RX_OVER_R = crate::FieldReader; #[doc = "Field `clr_rx_over` writer - clr_rx_over"] -pub type CLR_RX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] #[must_use] - pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { - CLR_RX_OVER_W::new(self) + pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { + CLR_RX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/clr_rx_under.rs b/jh7110-vf2-12a-pac/src/i2c0/clr_rx_under.rs index 4a24f7c..35e15bd 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/clr_rx_under.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/clr_rx_under.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_under` reader - clr_rx_under"] pub type CLR_RX_UNDER_R = crate::FieldReader; #[doc = "Field `clr_rx_under` writer - clr_rx_under"] -pub type CLR_RX_UNDER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_UNDER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] #[must_use] - pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { - CLR_RX_UNDER_W::new(self) + pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { + CLR_RX_UNDER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/clr_start_det.rs b/jh7110-vf2-12a-pac/src/i2c0/clr_start_det.rs index cebc4bc..2314f65 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/clr_start_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/clr_start_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_start_det` reader - clr_start_det"] pub type CLR_START_DET_R = crate::FieldReader; #[doc = "Field `clr_start_det` writer - clr_start_det"] -pub type CLR_START_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_START_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] #[must_use] - pub fn clr_start_det(&mut self) -> CLR_START_DET_W { - CLR_START_DET_W::new(self) + pub fn clr_start_det(&mut self) -> CLR_START_DET_W { + CLR_START_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/clr_stop_det.rs b/jh7110-vf2-12a-pac/src/i2c0/clr_stop_det.rs index 44f39f3..49abcac 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/clr_stop_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/clr_stop_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_stop_det` reader - clr_stop_det"] pub type CLR_STOP_DET_R = crate::FieldReader; #[doc = "Field `clr_stop_det` writer - clr_stop_det"] -pub type CLR_STOP_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_STOP_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] #[must_use] - pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { - CLR_STOP_DET_W::new(self) + pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { + CLR_STOP_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/clr_tx_abrt.rs b/jh7110-vf2-12a-pac/src/i2c0/clr_tx_abrt.rs index 6ac441c..3bc0f6f 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/clr_tx_abrt.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/clr_tx_abrt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_abrt` reader - clr_tx_abrt"] pub type CLR_TX_ABRT_R = crate::FieldReader; #[doc = "Field `clr_tx_abrt` writer - clr_tx_abrt"] -pub type CLR_TX_ABRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_ABRT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] #[must_use] - pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { - CLR_TX_ABRT_W::new(self) + pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { + CLR_TX_ABRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/clr_tx_over.rs b/jh7110-vf2-12a-pac/src/i2c0/clr_tx_over.rs index 2b32b52..a5b6933 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/clr_tx_over.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/clr_tx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_over` reader - clr_tx_over"] pub type CLR_TX_OVER_R = crate::FieldReader; #[doc = "Field `clr_tx_over` writer - clr_tx_over"] -pub type CLR_TX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] #[must_use] - pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { - CLR_TX_OVER_W::new(self) + pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { + CLR_TX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/comp_param_1.rs b/jh7110-vf2-12a-pac/src/i2c0/comp_param_1.rs index 24a22e1..95c5002 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/comp_param_1.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/comp_param_1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/comp_type.rs b/jh7110-vf2-12a-pac/src/i2c0/comp_type.rs index ac916b5..1336c43 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/comp_type.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/comp_type.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/comp_version.rs b/jh7110-vf2-12a-pac/src/i2c0/comp_version.rs index 4be31fa..e8309c8 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/comp_version.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/comp_version.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/con.rs b/jh7110-vf2-12a-pac/src/i2c0/con.rs index 873c534..28aa865 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/con.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/con.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `master` reader - I2C Master Connection - 0: Slave, 1: Master"] pub type MASTER_R = crate::BitReader; #[doc = "Field `master` writer - I2C Master Connection - 0: Slave, 1: Master"] -pub type MASTER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `speed` reader - I2C Speed - 01: Standard, 10: Fast, 11: High"] pub type SPEED_R = crate::FieldReader; #[doc = "Field `speed` writer - I2C Speed - 01: Standard, 10: Fast, 11: High"] -pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `slave_10bitaddr` reader - I2C Slave 10-bit Address - 0: False, 1: True"] pub type SLAVE_10BITADDR_R = crate::BitReader; #[doc = "Field `slave_10bitaddr` writer - I2C Slave 10-bit Address - 0: False, 1: True"] -pub type SLAVE_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_10bitaddr` reader - I2C Master 10-bit Address - 0: False, 1: True"] pub type MASTER_10BITADDR_R = crate::BitReader; #[doc = "Field `master_10bitaddr` writer - I2C Master 10-bit Address - 0: False, 1: True"] -pub type MASTER_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_en` reader - I2C Restart Enable - 0: False, 1: True"] pub type RESTART_EN_R = crate::BitReader; #[doc = "Field `restart_en` writer - I2C Restart Enable - 0: False, 1: True"] -pub type RESTART_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_disable` reader - I2C Slave Disable - 0: False, 1: True"] pub type SLAVE_DISABLE_R = crate::BitReader; #[doc = "Field `slave_disable` writer - I2C Slave Disable - 0: False, 1: True"] -pub type SLAVE_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det_ifaddressed` reader - I2C Stop DET If Addressed - 0: False, 1: True"] pub type STOP_DET_IFADDRESSED_R = crate::BitReader; #[doc = "Field `stop_det_ifaddressed` writer - I2C Stop DET If Addressed - 0: False, 1: True"] -pub type STOP_DET_IFADDRESSED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty_ctrl` reader - I2C TX Empty Control - 0: False, 1: True"] pub type TX_EMPTY_CTRL_R = crate::BitReader; #[doc = "Field `tx_empty_ctrl` writer - I2C TX Empty Control - 0: False, 1: True"] -pub type TX_EMPTY_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_fifo_full_hld_ctrl` reader - I2C RX FIFO Full Hold Control - 0: False, 1: True"] pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; #[doc = "Field `rx_fifo_full_hld_ctrl` writer - I2C RX FIFO Full Hold Control - 0: False, 1: True"] -pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bus_clear_ctrl` reader - I2C Bus Clear Control - 0: False, 1: True"] pub type BUS_CLEAR_CTRL_R = crate::BitReader; #[doc = "Field `bus_clear_ctrl` writer - I2C Bus Clear Control - 0: False, 1: True"] -pub type BUS_CLEAR_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BUS_CLEAR_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] #[must_use] - pub fn master(&mut self) -> MASTER_W { - MASTER_W::new(self) + pub fn master(&mut self) -> MASTER_W { + MASTER_W::new(self, 0) } #[doc = "Bits 1:2 - I2C Speed - 01: Standard, 10: Fast, 11: High"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W { - SPEED_W::new(self) + pub fn speed(&mut self) -> SPEED_W { + SPEED_W::new(self, 1) } #[doc = "Bit 3 - I2C Slave 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { - SLAVE_10BITADDR_W::new(self) + pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { + SLAVE_10BITADDR_W::new(self, 3) } #[doc = "Bit 4 - I2C Master 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { - MASTER_10BITADDR_W::new(self) + pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { + MASTER_10BITADDR_W::new(self, 4) } #[doc = "Bit 5 - I2C Restart Enable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn restart_en(&mut self) -> RESTART_EN_W { - RESTART_EN_W::new(self) + pub fn restart_en(&mut self) -> RESTART_EN_W { + RESTART_EN_W::new(self, 5) } #[doc = "Bit 6 - I2C Slave Disable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { - SLAVE_DISABLE_W::new(self) + pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { + SLAVE_DISABLE_W::new(self, 6) } #[doc = "Bit 7 - I2C Stop DET If Addressed - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { - STOP_DET_IFADDRESSED_W::new(self) + pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { + STOP_DET_IFADDRESSED_W::new(self, 7) } #[doc = "Bit 8 - I2C TX Empty Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { - TX_EMPTY_CTRL_W::new(self) + pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { + TX_EMPTY_CTRL_W::new(self, 8) } #[doc = "Bit 9 - I2C RX FIFO Full Hold Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { - RX_FIFO_FULL_HLD_CTRL_W::new(self) + pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { + RX_FIFO_FULL_HLD_CTRL_W::new(self, 9) } #[doc = "Bit 11 - I2C Bus Clear Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { - BUS_CLEAR_CTRL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { + BUS_CLEAR_CTRL_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/data_cmd.rs b/jh7110-vf2-12a-pac/src/i2c0/data_cmd.rs index cf36408..2b320d4 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/data_cmd.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/data_cmd.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `dat` reader - Data Command Data Byte"] pub type DAT_R = crate::FieldReader; #[doc = "Field `dat` writer - Data Command Data Byte"] -pub type DAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `read` reader - Data Command READ Bit - 0: Write, 1: Read"] pub type READ_R = crate::BitReader; #[doc = "Field `read` writer - Data Command READ Bit - 0: Write, 1: Read"] -pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop` reader - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart` reader - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] pub type RESTART_R = crate::BitReader; #[doc = "Field `restart` writer - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] -pub type RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `first_data_byte` reader - Data Command First Data Byte - 0: False, 1: True"] pub type FIRST_DATA_BYTE_R = crate::BitReader; #[doc = "Field `first_data_byte` writer - Data Command First Data Byte - 0: False, 1: True"] -pub type FIRST_DATA_BYTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIRST_DATA_BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] #[must_use] - pub fn dat(&mut self) -> DAT_W { - DAT_W::new(self) + pub fn dat(&mut self) -> DAT_W { + DAT_W::new(self, 0) } #[doc = "Bit 8 - Data Command READ Bit - 0: Write, 1: Read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W { - READ_W::new(self) + pub fn read(&mut self) -> READ_W { + READ_W::new(self, 8) } #[doc = "Bit 9 - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 9) } #[doc = "Bit 10 - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] #[inline(always)] #[must_use] - pub fn restart(&mut self) -> RESTART_W { - RESTART_W::new(self) + pub fn restart(&mut self) -> RESTART_W { + RESTART_W::new(self, 10) } #[doc = "Bit 11 - Data Command First Data Byte - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { - FIRST_DATA_BYTE_W::new(self) + pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { + FIRST_DATA_BYTE_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/enable.rs b/jh7110-vf2-12a-pac/src/i2c0/enable.rs index c5ca9d7..3629f6b 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/enable.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/enable.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `abort` reader - abort"] pub type ABORT_R = crate::BitReader; #[doc = "Field `abort` writer - abort"] -pub type ABORT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 1 - abort"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 1 - abort"] #[inline(always)] #[must_use] - pub fn abort(&mut self) -> ABORT_W { - ABORT_W::new(self) + pub fn abort(&mut self) -> ABORT_W { + ABORT_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/enable_status.rs b/jh7110-vf2-12a-pac/src/i2c0/enable_status.rs index 2c102a6..8b9b7d3 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/enable_status.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/enable_status.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `activity` reader - activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tfe` reader - tfe"] pub type TFE_R = crate::BitReader; #[doc = "Field `tfe` writer - tfe"] -pub type TFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TFE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfne` reader - rfne"] pub type RFNE_R = crate::BitReader; #[doc = "Field `rfne` writer - rfne"] -pub type RFNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFNE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_activity` reader - master_activity"] pub type MASTER_ACTIVITY_R = crate::BitReader; #[doc = "Field `master_activity` writer - master_activity"] -pub type MASTER_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_activity` reader - slave_activity"] pub type SLAVE_ACTIVITY_R = crate::BitReader; #[doc = "Field `slave_activity` writer - slave_activity"] -pub type SLAVE_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - activity"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 0) } #[doc = "Bit 2 - tfe"] #[inline(always)] #[must_use] - pub fn tfe(&mut self) -> TFE_W { - TFE_W::new(self) + pub fn tfe(&mut self) -> TFE_W { + TFE_W::new(self, 2) } #[doc = "Bit 3 - rfne"] #[inline(always)] #[must_use] - pub fn rfne(&mut self) -> RFNE_W { - RFNE_W::new(self) + pub fn rfne(&mut self) -> RFNE_W { + RFNE_W::new(self, 3) } #[doc = "Bit 5 - master_activity"] #[inline(always)] #[must_use] - pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { - MASTER_ACTIVITY_W::new(self) + pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { + MASTER_ACTIVITY_W::new(self, 5) } #[doc = "Bit 6 - slave_activity"] #[inline(always)] #[must_use] - pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { - SLAVE_ACTIVITY_W::new(self) + pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { + SLAVE_ACTIVITY_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/fs_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c0/fs_scl_hcnt.rs index 9a9fd72..8a4f6d1 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/fs_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/fs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_hcnt` reader - fs_scl_hcnt"] pub type FS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_hcnt` writer - fs_scl_hcnt"] -pub type FS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { - FS_SCL_HCNT_W::new(self) + pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { + FS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/fs_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c0/fs_scl_lcnt.rs index 5e41cd1..4b4dd6b 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/fs_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/fs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_lcnt` reader - fs_scl_lcnt"] pub type FS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_lcnt` writer - fs_scl_lcnt"] -pub type FS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { - FS_SCL_LCNT_W::new(self) + pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { + FS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/hs_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c0/hs_scl_hcnt.rs index fba7f13..9b0a71c 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/hs_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/hs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_hcnt` reader - hs_scl_hcnt"] pub type HS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_hcnt` writer - hs_scl_hcnt"] -pub type HS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { - HS_SCL_HCNT_W::new(self) + pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { + HS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/hs_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c0/hs_scl_lcnt.rs index 9fca7a5..a715282 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/hs_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/hs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_lcnt` reader - hs_scl_lcnt"] pub type HS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_lcnt` writer - hs_scl_lcnt"] -pub type HS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { - HS_SCL_LCNT_W::new(self) + pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { + HS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/intr_mask.rs b/jh7110-vf2-12a-pac/src/i2c0/intr_mask.rs index 20a334f..769b629 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/intr_mask.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/intr_mask.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/intr_stat.rs b/jh7110-vf2-12a-pac/src/i2c0/intr_stat.rs index 2c2ba34..f376c26 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/intr_stat.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/raw_intr_stat.rs b/jh7110-vf2-12a-pac/src/i2c0/raw_intr_stat.rs index af97981..dd5e8e0 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/raw_intr_stat.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/raw_intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/rx_tl.rs b/jh7110-vf2-12a-pac/src/i2c0/rx_tl.rs index 1455a10..f3f39f4 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/rx_tl.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/rx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rx_tl` reader - rx_tl"] pub type RX_TL_R = crate::FieldReader; #[doc = "Field `rx_tl` writer - rx_tl"] -pub type RX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] #[must_use] - pub fn rx_tl(&mut self) -> RX_TL_W { - RX_TL_W::new(self) + pub fn rx_tl(&mut self) -> RX_TL_W { + RX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/rxflr.rs b/jh7110-vf2-12a-pac/src/i2c0/rxflr.rs index 910e254..4dccf5e 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/rxflr.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/rxflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rxflr` reader - rxflr"] pub type RXFLR_R = crate::FieldReader; #[doc = "Field `rxflr` writer - rxflr"] -pub type RXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] #[must_use] - pub fn rxflr(&mut self) -> RXFLR_W { - RXFLR_W::new(self) + pub fn rxflr(&mut self) -> RXFLR_W { + RXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/sar.rs b/jh7110-vf2-12a-pac/src/i2c0/sar.rs index d272e7a..1af6273 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/sar.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/sar.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Slave address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Slave address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Slave address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Slave address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; impl R { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Slave address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/sda_hold.rs b/jh7110-vf2-12a-pac/src/i2c0/sda_hold.rs index 82ceac5..d5d7512 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/sda_hold.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/sda_hold.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sda_hold` reader - sda_hold"] pub type SDA_HOLD_R = crate::FieldReader; #[doc = "Field `sda_hold` writer - sda_hold"] -pub type SDA_HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SDA_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] #[must_use] - pub fn sda_hold(&mut self) -> SDA_HOLD_W { - SDA_HOLD_W::new(self) + pub fn sda_hold(&mut self) -> SDA_HOLD_W { + SDA_HOLD_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/ss_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c0/ss_scl_hcnt.rs index 33736c7..77d7ea0 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/ss_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/ss_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_hcnt` reader - ss_scl_hcnt"] pub type SS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_hcnt` writer - ss_scl_hcnt"] -pub type SS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { - SS_SCL_HCNT_W::new(self) + pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { + SS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/ss_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c0/ss_scl_lcnt.rs index ce22b5d..8208747 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/ss_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/ss_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_lcnt` reader - ss_scl_lcnt"] pub type SS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_lcnt` writer - ss_scl_lcnt"] -pub type SS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { - SS_SCL_LCNT_W::new(self) + pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { + SS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/status.rs b/jh7110-vf2-12a-pac/src/i2c0/status.rs index 9489e49..1b7ab67 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/status.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/tar.rs b/jh7110-vf2-12a-pac/src/i2c0/tar.rs index 9fedc71..3044a8c 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/tar.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/tar.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Target address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Target address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Target address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Target address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; #[doc = "Field `mode` reader - Target addressing mode - 0: 7-bit, 1: 10-bit"] pub type MODE_R = crate::BitReader; #[doc = "Field `mode` writer - Target addressing mode - 0: 7-bit, 1: 10-bit"] -pub type MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Target address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } #[doc = "Bit 12 - Target addressing mode - 0: 7-bit, 1: 10-bit"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W { - MODE_W::new(self) + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 12) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/tx_abrt_source.rs b/jh7110-vf2-12a-pac/src/i2c0/tx_abrt_source.rs index 6f31813..c4fdf1a 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/tx_abrt_source.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/tx_abrt_source.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/tx_tl.rs b/jh7110-vf2-12a-pac/src/i2c0/tx_tl.rs index 84a1734..b0e6c64 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/tx_tl.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/tx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `tx_tl` reader - tx_tl"] pub type TX_TL_R = crate::FieldReader; #[doc = "Field `tx_tl` writer - tx_tl"] -pub type TX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] #[must_use] - pub fn tx_tl(&mut self) -> TX_TL_W { - TX_TL_W::new(self) + pub fn tx_tl(&mut self) -> TX_TL_W { + TX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c0/txflr.rs b/jh7110-vf2-12a-pac/src/i2c0/txflr.rs index b8e5fdd..5ca351d 100644 --- a/jh7110-vf2-12a-pac/src/i2c0/txflr.rs +++ b/jh7110-vf2-12a-pac/src/i2c0/txflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `txflr` reader - txflr"] pub type TXFLR_R = crate::FieldReader; #[doc = "Field `txflr` writer - txflr"] -pub type TXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - txflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - txflr"] #[inline(always)] #[must_use] - pub fn txflr(&mut self) -> TXFLR_W { - TXFLR_W::new(self) + pub fn txflr(&mut self) -> TXFLR_W { + TXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1.rs b/jh7110-vf2-12a-pac/src/i2c1.rs index d0fe76a..fdffe28 100644 --- a/jh7110-vf2-12a-pac/src/i2c1.rs +++ b/jh7110-vf2-12a-pac/src/i2c1.rs @@ -1,266 +1,416 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + con: CON, + tar: TAR, + sar: SAR, + _reserved3: [u8; 0x04], + data_cmd: DATA_CMD, + ss_scl_hcnt: SS_SCL_HCNT, + ss_scl_lcnt: SS_SCL_LCNT, + fs_scl_hcnt: FS_SCL_HCNT, + fs_scl_lcnt: FS_SCL_LCNT, + hs_scl_hcnt: HS_SCL_HCNT, + hs_scl_lcnt: HS_SCL_LCNT, + intr_stat: INTR_STAT, + intr_mask: INTR_MASK, + raw_intr_stat: RAW_INTR_STAT, + rx_tl: RX_TL, + tx_tl: TX_TL, + clr_intr: CLR_INTR, + clr_rx_under: CLR_RX_UNDER, + clr_rx_over: CLR_RX_OVER, + clr_tx_over: CLR_TX_OVER, + clr_rd_req: CLR_RD_REQ, + clr_tx_abrt: CLR_TX_ABRT, + clr_rx_done: CLR_RX_DONE, + clr_activity: CLR_ACTIVITY, + clr_stop_det: CLR_STOP_DET, + clr_start_det: CLR_START_DET, + clr_gen_call: CLR_GEN_CALL, + enable: ENABLE, + status: STATUS, + txflr: TXFLR, + rxflr: RXFLR, + sda_hold: SDA_HOLD, + tx_abrt_source: TX_ABRT_SOURCE, + _reserved32: [u8; 0x18], + enable_status: ENABLE_STATUS, + _reserved33: [u8; 0x08], + clr_restart_det: CLR_RESTART_DET, + _reserved34: [u8; 0x48], + comp_param_1: COMP_PARAM_1, + comp_version: COMP_VERSION, + comp_type: COMP_TYPE, +} +impl RegisterBlock { #[doc = "0x00 - DesignWare I2C CON"] - pub con: CON, + #[inline(always)] + pub const fn con(&self) -> &CON { + &self.con + } #[doc = "0x04 - DesignWare I2C TAR"] - pub tar: TAR, + #[inline(always)] + pub const fn tar(&self) -> &TAR { + &self.tar + } #[doc = "0x08 - DesignWare I2C SAR"] - pub sar: SAR, - _reserved3: [u8; 0x04], + #[inline(always)] + pub const fn sar(&self) -> &SAR { + &self.sar + } #[doc = "0x10 - DesignWare I2C Data Command"] - pub data_cmd: DATA_CMD, + #[inline(always)] + pub const fn data_cmd(&self) -> &DATA_CMD { + &self.data_cmd + } #[doc = "0x14 - DesignWare I2C SS SCL HCNT"] - pub ss_scl_hcnt: SS_SCL_HCNT, + #[inline(always)] + pub const fn ss_scl_hcnt(&self) -> &SS_SCL_HCNT { + &self.ss_scl_hcnt + } #[doc = "0x18 - DesignWare I2C SS SCL LCNT"] - pub ss_scl_lcnt: SS_SCL_LCNT, + #[inline(always)] + pub const fn ss_scl_lcnt(&self) -> &SS_SCL_LCNT { + &self.ss_scl_lcnt + } #[doc = "0x1c - DesignWare I2C FS SCL HCNT"] - pub fs_scl_hcnt: FS_SCL_HCNT, + #[inline(always)] + pub const fn fs_scl_hcnt(&self) -> &FS_SCL_HCNT { + &self.fs_scl_hcnt + } #[doc = "0x20 - DesignWare I2C FS SCL LCNT"] - pub fs_scl_lcnt: FS_SCL_LCNT, + #[inline(always)] + pub const fn fs_scl_lcnt(&self) -> &FS_SCL_LCNT { + &self.fs_scl_lcnt + } #[doc = "0x24 - DesignWare I2C HS SCL HCNT"] - pub hs_scl_hcnt: HS_SCL_HCNT, + #[inline(always)] + pub const fn hs_scl_hcnt(&self) -> &HS_SCL_HCNT { + &self.hs_scl_hcnt + } #[doc = "0x28 - DesignWare I2C HS SCL LCNT"] - pub hs_scl_lcnt: HS_SCL_LCNT, + #[inline(always)] + pub const fn hs_scl_lcnt(&self) -> &HS_SCL_LCNT { + &self.hs_scl_lcnt + } #[doc = "0x2c - DesignWare I2C Interrupt Status"] - pub intr_stat: INTR_STAT, + #[inline(always)] + pub const fn intr_stat(&self) -> &INTR_STAT { + &self.intr_stat + } #[doc = "0x30 - DesignWare I2C Interrupt Mask"] - pub intr_mask: INTR_MASK, + #[inline(always)] + pub const fn intr_mask(&self) -> &INTR_MASK { + &self.intr_mask + } #[doc = "0x34 - DesignWare I2C Raw Interrupt Status"] - pub raw_intr_stat: RAW_INTR_STAT, + #[inline(always)] + pub const fn raw_intr_stat(&self) -> &RAW_INTR_STAT { + &self.raw_intr_stat + } #[doc = "0x38 - DesignWare I2C RX TL"] - pub rx_tl: RX_TL, + #[inline(always)] + pub const fn rx_tl(&self) -> &RX_TL { + &self.rx_tl + } #[doc = "0x3c - DesignWare I2C TX TL"] - pub tx_tl: TX_TL, + #[inline(always)] + pub const fn tx_tl(&self) -> &TX_TL { + &self.tx_tl + } #[doc = "0x40 - DesignWare I2C Clear Interrrupt"] - pub clr_intr: CLR_INTR, + #[inline(always)] + pub const fn clr_intr(&self) -> &CLR_INTR { + &self.clr_intr + } #[doc = "0x44 - DesignWare I2C Clear RX Underrun"] - pub clr_rx_under: CLR_RX_UNDER, + #[inline(always)] + pub const fn clr_rx_under(&self) -> &CLR_RX_UNDER { + &self.clr_rx_under + } #[doc = "0x48 - DesignWare I2C Clear RX Overrun"] - pub clr_rx_over: CLR_RX_OVER, + #[inline(always)] + pub const fn clr_rx_over(&self) -> &CLR_RX_OVER { + &self.clr_rx_over + } #[doc = "0x4c - DesignWare I2C Clear TX Overrun"] - pub clr_tx_over: CLR_TX_OVER, + #[inline(always)] + pub const fn clr_tx_over(&self) -> &CLR_TX_OVER { + &self.clr_tx_over + } #[doc = "0x50 - DesignWare I2C Clear Read Request"] - pub clr_rd_req: CLR_RD_REQ, + #[inline(always)] + pub const fn clr_rd_req(&self) -> &CLR_RD_REQ { + &self.clr_rd_req + } #[doc = "0x54 - DesignWare I2C Clear TX Abort"] - pub clr_tx_abrt: CLR_TX_ABRT, + #[inline(always)] + pub const fn clr_tx_abrt(&self) -> &CLR_TX_ABRT { + &self.clr_tx_abrt + } #[doc = "0x58 - DesignWare I2C Clear RX Done"] - pub clr_rx_done: CLR_RX_DONE, + #[inline(always)] + pub const fn clr_rx_done(&self) -> &CLR_RX_DONE { + &self.clr_rx_done + } #[doc = "0x5c - DesignWare I2C Clear Activity"] - pub clr_activity: CLR_ACTIVITY, + #[inline(always)] + pub const fn clr_activity(&self) -> &CLR_ACTIVITY { + &self.clr_activity + } #[doc = "0x60 - DesignWare I2C Clear Stop DET"] - pub clr_stop_det: CLR_STOP_DET, + #[inline(always)] + pub const fn clr_stop_det(&self) -> &CLR_STOP_DET { + &self.clr_stop_det + } #[doc = "0x64 - DesignWare I2C Clear Start DET"] - pub clr_start_det: CLR_START_DET, + #[inline(always)] + pub const fn clr_start_det(&self) -> &CLR_START_DET { + &self.clr_start_det + } #[doc = "0x68 - DesignWare I2C Clear General Call"] - pub clr_gen_call: CLR_GEN_CALL, + #[inline(always)] + pub const fn clr_gen_call(&self) -> &CLR_GEN_CALL { + &self.clr_gen_call + } #[doc = "0x6c - DesignWare I2C Enable"] - pub enable: ENABLE, + #[inline(always)] + pub const fn enable(&self) -> &ENABLE { + &self.enable + } #[doc = "0x70 - DesignWare I2C Status"] - pub status: STATUS, + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } #[doc = "0x74 - DesignWare I2C TX Failure"] - pub txflr: TXFLR, + #[inline(always)] + pub const fn txflr(&self) -> &TXFLR { + &self.txflr + } #[doc = "0x78 - DesignWare I2C RX Failure"] - pub rxflr: RXFLR, + #[inline(always)] + pub const fn rxflr(&self) -> &RXFLR { + &self.rxflr + } #[doc = "0x7c - DesignWare I2C SDA Hold"] - pub sda_hold: SDA_HOLD, + #[inline(always)] + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold + } #[doc = "0x80 - DesignWare I2C TX Abort Source"] - pub tx_abrt_source: TX_ABRT_SOURCE, - _reserved32: [u8; 0x18], + #[inline(always)] + pub const fn tx_abrt_source(&self) -> &TX_ABRT_SOURCE { + &self.tx_abrt_source + } #[doc = "0x9c - DesignWare I2C Enable Status"] - pub enable_status: ENABLE_STATUS, - _reserved33: [u8; 0x08], + #[inline(always)] + pub const fn enable_status(&self) -> &ENABLE_STATUS { + &self.enable_status + } #[doc = "0xa8 - DesignWare I2C Clear Restart DET"] - pub clr_restart_det: CLR_RESTART_DET, - _reserved34: [u8; 0x48], + #[inline(always)] + pub const fn clr_restart_det(&self) -> &CLR_RESTART_DET { + &self.clr_restart_det + } #[doc = "0xf4 - DesignWare I2C Compatibility Parameter 1"] - pub comp_param_1: COMP_PARAM_1, + #[inline(always)] + pub const fn comp_param_1(&self) -> &COMP_PARAM_1 { + &self.comp_param_1 + } #[doc = "0xf8 - DesignWare I2C Compatibility Version"] - pub comp_version: COMP_VERSION, + #[inline(always)] + pub const fn comp_version(&self) -> &COMP_VERSION { + &self.comp_version + } #[doc = "0xfc - DesignWare I2C Compatibility Type"] - pub comp_type: COMP_TYPE, + #[inline(always)] + pub const fn comp_type(&self) -> &COMP_TYPE { + &self.comp_type + } } -#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`con`] +#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@con`] module"] pub type CON = crate::Reg; #[doc = "DesignWare I2C CON"] pub mod con; -#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tar`] +#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar`] module"] pub type TAR = crate::Reg; #[doc = "DesignWare I2C TAR"] pub mod tar; -#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sar`] +#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`] module"] pub type SAR = crate::Reg; #[doc = "DesignWare I2C SAR"] pub mod sar; -#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`data_cmd`] +#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_cmd`] module"] pub type DATA_CMD = crate::Reg; #[doc = "DesignWare I2C Data Command"] pub mod data_cmd; -#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_hcnt`] +#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_hcnt`] module"] pub type SS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL HCNT"] pub mod ss_scl_hcnt; -#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_lcnt`] +#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_lcnt`] module"] pub type SS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL LCNT"] pub mod ss_scl_lcnt; -#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_hcnt`] +#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_hcnt`] module"] pub type FS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL HCNT"] pub mod fs_scl_hcnt; -#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_lcnt`] +#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_lcnt`] module"] pub type FS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL LCNT"] pub mod fs_scl_lcnt; -#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_hcnt`] +#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_hcnt`] module"] pub type HS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL HCNT"] pub mod hs_scl_hcnt; -#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_lcnt`] +#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_lcnt`] module"] pub type HS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL LCNT"] pub mod hs_scl_lcnt; -#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_stat`] +#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"] pub type INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Interrupt Status"] pub mod intr_stat; -#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_mask`] +#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mask`] module"] pub type INTR_MASK = crate::Reg; #[doc = "DesignWare I2C Interrupt Mask"] pub mod intr_mask; -#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`raw_intr_stat`] +#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"] pub type RAW_INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Raw Interrupt Status"] pub mod raw_intr_stat; -#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rx_tl`] +#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tl`] module"] pub type RX_TL = crate::Reg; #[doc = "DesignWare I2C RX TL"] pub mod rx_tl; -#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_tl`] +#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_tl`] module"] pub type TX_TL = crate::Reg; #[doc = "DesignWare I2C TX TL"] pub mod tx_tl; -#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_intr`] +#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_intr`] module"] pub type CLR_INTR = crate::Reg; #[doc = "DesignWare I2C Clear Interrrupt"] pub mod clr_intr; -#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_under`] +#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_under`] module"] pub type CLR_RX_UNDER = crate::Reg; #[doc = "DesignWare I2C Clear RX Underrun"] pub mod clr_rx_under; -#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_over`] +#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_over`] module"] pub type CLR_RX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear RX Overrun"] pub mod clr_rx_over; -#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_over`] +#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_over`] module"] pub type CLR_TX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear TX Overrun"] pub mod clr_tx_over; -#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rd_req`] +#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rd_req`] module"] pub type CLR_RD_REQ = crate::Reg; #[doc = "DesignWare I2C Clear Read Request"] pub mod clr_rd_req; -#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_abrt`] +#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_abrt`] module"] pub type CLR_TX_ABRT = crate::Reg; #[doc = "DesignWare I2C Clear TX Abort"] pub mod clr_tx_abrt; -#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_done`] +#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_done`] module"] pub type CLR_RX_DONE = crate::Reg; #[doc = "DesignWare I2C Clear RX Done"] pub mod clr_rx_done; -#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_activity`] +#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_activity`] module"] pub type CLR_ACTIVITY = crate::Reg; #[doc = "DesignWare I2C Clear Activity"] pub mod clr_activity; -#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_stop_det`] +#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_stop_det`] module"] pub type CLR_STOP_DET = crate::Reg; #[doc = "DesignWare I2C Clear Stop DET"] pub mod clr_stop_det; -#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_start_det`] +#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_start_det`] module"] pub type CLR_START_DET = crate::Reg; #[doc = "DesignWare I2C Clear Start DET"] pub mod clr_start_det; -#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_gen_call`] +#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_gen_call`] module"] pub type CLR_GEN_CALL = crate::Reg; #[doc = "DesignWare I2C Clear General Call"] pub mod clr_gen_call; -#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable`] +#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] pub type ENABLE = crate::Reg; #[doc = "DesignWare I2C Enable"] pub mod enable; -#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`status`] +#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] pub type STATUS = crate::Reg; #[doc = "DesignWare I2C Status"] pub mod status; -#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txflr`] +#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txflr`] module"] pub type TXFLR = crate::Reg; #[doc = "DesignWare I2C TX Failure"] pub mod txflr; -#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxflr`] +#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxflr`] module"] pub type RXFLR = crate::Reg; #[doc = "DesignWare I2C RX Failure"] pub mod rxflr; -#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sda_hold`] +#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] pub type SDA_HOLD = crate::Reg; #[doc = "DesignWare I2C SDA Hold"] pub mod sda_hold; -#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_abrt_source`] +#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_abrt_source`] module"] pub type TX_ABRT_SOURCE = crate::Reg; #[doc = "DesignWare I2C TX Abort Source"] pub mod tx_abrt_source; -#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_status`] +#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_status`] module"] pub type ENABLE_STATUS = crate::Reg; #[doc = "DesignWare I2C Enable Status"] pub mod enable_status; -#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_restart_det`] +#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_restart_det`] module"] pub type CLR_RESTART_DET = crate::Reg; #[doc = "DesignWare I2C Clear Restart DET"] pub mod clr_restart_det; -#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_param_1`] +#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_param_1`] module"] pub type COMP_PARAM_1 = crate::Reg; #[doc = "DesignWare I2C Compatibility Parameter 1"] pub mod comp_param_1; -#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_version`] +#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_version`] module"] pub type COMP_VERSION = crate::Reg; #[doc = "DesignWare I2C Compatibility Version"] pub mod comp_version; -#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_type`] +#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_type`] module"] pub type COMP_TYPE = crate::Reg; #[doc = "DesignWare I2C Compatibility Type"] diff --git a/jh7110-vf2-12a-pac/src/i2c1/clr_activity.rs b/jh7110-vf2-12a-pac/src/i2c1/clr_activity.rs index d26bb80..1ee2297 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/clr_activity.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/clr_activity.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_activity` reader - clr_activity"] pub type CLR_ACTIVITY_R = crate::FieldReader; #[doc = "Field `clr_activity` writer - clr_activity"] -pub type CLR_ACTIVITY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_ACTIVITY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] #[must_use] - pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { - CLR_ACTIVITY_W::new(self) + pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { + CLR_ACTIVITY_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/clr_gen_call.rs b/jh7110-vf2-12a-pac/src/i2c1/clr_gen_call.rs index a9ea5af..4a7c5ba 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/clr_gen_call.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/clr_gen_call.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_gen_call` reader - clr_gen_call"] pub type CLR_GEN_CALL_R = crate::FieldReader; #[doc = "Field `clr_gen_call` writer - clr_gen_call"] -pub type CLR_GEN_CALL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_GEN_CALL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] #[must_use] - pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { - CLR_GEN_CALL_W::new(self) + pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { + CLR_GEN_CALL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/clr_intr.rs b/jh7110-vf2-12a-pac/src/i2c1/clr_intr.rs index a7daf57..cf57b09 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/clr_intr.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/clr_intr.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/clr_rd_req.rs b/jh7110-vf2-12a-pac/src/i2c1/clr_rd_req.rs index e275da1..4beae9d 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/clr_rd_req.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/clr_rd_req.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rd_req` reader - clr_rd_req"] pub type CLR_RD_REQ_R = crate::FieldReader; #[doc = "Field `clr_rd_req` writer - clr_rd_req"] -pub type CLR_RD_REQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RD_REQ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] #[must_use] - pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { - CLR_RD_REQ_W::new(self) + pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { + CLR_RD_REQ_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/clr_restart_det.rs b/jh7110-vf2-12a-pac/src/i2c1/clr_restart_det.rs index 5be7f5d..88d193c 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/clr_restart_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/clr_restart_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_restart_det` reader - clr_restart_det"] pub type CLR_RESTART_DET_R = crate::FieldReader; #[doc = "Field `clr_restart_det` writer - clr_restart_det"] -pub type CLR_RESTART_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RESTART_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] #[must_use] - pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { - CLR_RESTART_DET_W::new(self) + pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { + CLR_RESTART_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/clr_rx_done.rs b/jh7110-vf2-12a-pac/src/i2c1/clr_rx_done.rs index 02d83c5..7e14a3f 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/clr_rx_done.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/clr_rx_done.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_done` reader - clr_rx_done"] pub type CLR_RX_DONE_R = crate::FieldReader; #[doc = "Field `clr_rx_done` writer - clr_rx_done"] -pub type CLR_RX_DONE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_DONE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] #[must_use] - pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { - CLR_RX_DONE_W::new(self) + pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { + CLR_RX_DONE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/clr_rx_over.rs b/jh7110-vf2-12a-pac/src/i2c1/clr_rx_over.rs index 6d7ff4e..2302921 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/clr_rx_over.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/clr_rx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_over` reader - clr_rx_over"] pub type CLR_RX_OVER_R = crate::FieldReader; #[doc = "Field `clr_rx_over` writer - clr_rx_over"] -pub type CLR_RX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] #[must_use] - pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { - CLR_RX_OVER_W::new(self) + pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { + CLR_RX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/clr_rx_under.rs b/jh7110-vf2-12a-pac/src/i2c1/clr_rx_under.rs index 4a24f7c..35e15bd 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/clr_rx_under.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/clr_rx_under.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_under` reader - clr_rx_under"] pub type CLR_RX_UNDER_R = crate::FieldReader; #[doc = "Field `clr_rx_under` writer - clr_rx_under"] -pub type CLR_RX_UNDER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_UNDER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] #[must_use] - pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { - CLR_RX_UNDER_W::new(self) + pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { + CLR_RX_UNDER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/clr_start_det.rs b/jh7110-vf2-12a-pac/src/i2c1/clr_start_det.rs index cebc4bc..2314f65 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/clr_start_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/clr_start_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_start_det` reader - clr_start_det"] pub type CLR_START_DET_R = crate::FieldReader; #[doc = "Field `clr_start_det` writer - clr_start_det"] -pub type CLR_START_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_START_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] #[must_use] - pub fn clr_start_det(&mut self) -> CLR_START_DET_W { - CLR_START_DET_W::new(self) + pub fn clr_start_det(&mut self) -> CLR_START_DET_W { + CLR_START_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/clr_stop_det.rs b/jh7110-vf2-12a-pac/src/i2c1/clr_stop_det.rs index 44f39f3..49abcac 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/clr_stop_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/clr_stop_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_stop_det` reader - clr_stop_det"] pub type CLR_STOP_DET_R = crate::FieldReader; #[doc = "Field `clr_stop_det` writer - clr_stop_det"] -pub type CLR_STOP_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_STOP_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] #[must_use] - pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { - CLR_STOP_DET_W::new(self) + pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { + CLR_STOP_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/clr_tx_abrt.rs b/jh7110-vf2-12a-pac/src/i2c1/clr_tx_abrt.rs index 6ac441c..3bc0f6f 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/clr_tx_abrt.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/clr_tx_abrt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_abrt` reader - clr_tx_abrt"] pub type CLR_TX_ABRT_R = crate::FieldReader; #[doc = "Field `clr_tx_abrt` writer - clr_tx_abrt"] -pub type CLR_TX_ABRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_ABRT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] #[must_use] - pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { - CLR_TX_ABRT_W::new(self) + pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { + CLR_TX_ABRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/clr_tx_over.rs b/jh7110-vf2-12a-pac/src/i2c1/clr_tx_over.rs index 2b32b52..a5b6933 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/clr_tx_over.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/clr_tx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_over` reader - clr_tx_over"] pub type CLR_TX_OVER_R = crate::FieldReader; #[doc = "Field `clr_tx_over` writer - clr_tx_over"] -pub type CLR_TX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] #[must_use] - pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { - CLR_TX_OVER_W::new(self) + pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { + CLR_TX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/comp_param_1.rs b/jh7110-vf2-12a-pac/src/i2c1/comp_param_1.rs index 24a22e1..95c5002 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/comp_param_1.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/comp_param_1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/comp_type.rs b/jh7110-vf2-12a-pac/src/i2c1/comp_type.rs index ac916b5..1336c43 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/comp_type.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/comp_type.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/comp_version.rs b/jh7110-vf2-12a-pac/src/i2c1/comp_version.rs index 4be31fa..e8309c8 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/comp_version.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/comp_version.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/con.rs b/jh7110-vf2-12a-pac/src/i2c1/con.rs index 873c534..28aa865 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/con.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/con.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `master` reader - I2C Master Connection - 0: Slave, 1: Master"] pub type MASTER_R = crate::BitReader; #[doc = "Field `master` writer - I2C Master Connection - 0: Slave, 1: Master"] -pub type MASTER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `speed` reader - I2C Speed - 01: Standard, 10: Fast, 11: High"] pub type SPEED_R = crate::FieldReader; #[doc = "Field `speed` writer - I2C Speed - 01: Standard, 10: Fast, 11: High"] -pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `slave_10bitaddr` reader - I2C Slave 10-bit Address - 0: False, 1: True"] pub type SLAVE_10BITADDR_R = crate::BitReader; #[doc = "Field `slave_10bitaddr` writer - I2C Slave 10-bit Address - 0: False, 1: True"] -pub type SLAVE_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_10bitaddr` reader - I2C Master 10-bit Address - 0: False, 1: True"] pub type MASTER_10BITADDR_R = crate::BitReader; #[doc = "Field `master_10bitaddr` writer - I2C Master 10-bit Address - 0: False, 1: True"] -pub type MASTER_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_en` reader - I2C Restart Enable - 0: False, 1: True"] pub type RESTART_EN_R = crate::BitReader; #[doc = "Field `restart_en` writer - I2C Restart Enable - 0: False, 1: True"] -pub type RESTART_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_disable` reader - I2C Slave Disable - 0: False, 1: True"] pub type SLAVE_DISABLE_R = crate::BitReader; #[doc = "Field `slave_disable` writer - I2C Slave Disable - 0: False, 1: True"] -pub type SLAVE_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det_ifaddressed` reader - I2C Stop DET If Addressed - 0: False, 1: True"] pub type STOP_DET_IFADDRESSED_R = crate::BitReader; #[doc = "Field `stop_det_ifaddressed` writer - I2C Stop DET If Addressed - 0: False, 1: True"] -pub type STOP_DET_IFADDRESSED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty_ctrl` reader - I2C TX Empty Control - 0: False, 1: True"] pub type TX_EMPTY_CTRL_R = crate::BitReader; #[doc = "Field `tx_empty_ctrl` writer - I2C TX Empty Control - 0: False, 1: True"] -pub type TX_EMPTY_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_fifo_full_hld_ctrl` reader - I2C RX FIFO Full Hold Control - 0: False, 1: True"] pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; #[doc = "Field `rx_fifo_full_hld_ctrl` writer - I2C RX FIFO Full Hold Control - 0: False, 1: True"] -pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bus_clear_ctrl` reader - I2C Bus Clear Control - 0: False, 1: True"] pub type BUS_CLEAR_CTRL_R = crate::BitReader; #[doc = "Field `bus_clear_ctrl` writer - I2C Bus Clear Control - 0: False, 1: True"] -pub type BUS_CLEAR_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BUS_CLEAR_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] #[must_use] - pub fn master(&mut self) -> MASTER_W { - MASTER_W::new(self) + pub fn master(&mut self) -> MASTER_W { + MASTER_W::new(self, 0) } #[doc = "Bits 1:2 - I2C Speed - 01: Standard, 10: Fast, 11: High"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W { - SPEED_W::new(self) + pub fn speed(&mut self) -> SPEED_W { + SPEED_W::new(self, 1) } #[doc = "Bit 3 - I2C Slave 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { - SLAVE_10BITADDR_W::new(self) + pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { + SLAVE_10BITADDR_W::new(self, 3) } #[doc = "Bit 4 - I2C Master 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { - MASTER_10BITADDR_W::new(self) + pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { + MASTER_10BITADDR_W::new(self, 4) } #[doc = "Bit 5 - I2C Restart Enable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn restart_en(&mut self) -> RESTART_EN_W { - RESTART_EN_W::new(self) + pub fn restart_en(&mut self) -> RESTART_EN_W { + RESTART_EN_W::new(self, 5) } #[doc = "Bit 6 - I2C Slave Disable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { - SLAVE_DISABLE_W::new(self) + pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { + SLAVE_DISABLE_W::new(self, 6) } #[doc = "Bit 7 - I2C Stop DET If Addressed - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { - STOP_DET_IFADDRESSED_W::new(self) + pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { + STOP_DET_IFADDRESSED_W::new(self, 7) } #[doc = "Bit 8 - I2C TX Empty Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { - TX_EMPTY_CTRL_W::new(self) + pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { + TX_EMPTY_CTRL_W::new(self, 8) } #[doc = "Bit 9 - I2C RX FIFO Full Hold Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { - RX_FIFO_FULL_HLD_CTRL_W::new(self) + pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { + RX_FIFO_FULL_HLD_CTRL_W::new(self, 9) } #[doc = "Bit 11 - I2C Bus Clear Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { - BUS_CLEAR_CTRL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { + BUS_CLEAR_CTRL_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/data_cmd.rs b/jh7110-vf2-12a-pac/src/i2c1/data_cmd.rs index cf36408..2b320d4 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/data_cmd.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/data_cmd.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `dat` reader - Data Command Data Byte"] pub type DAT_R = crate::FieldReader; #[doc = "Field `dat` writer - Data Command Data Byte"] -pub type DAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `read` reader - Data Command READ Bit - 0: Write, 1: Read"] pub type READ_R = crate::BitReader; #[doc = "Field `read` writer - Data Command READ Bit - 0: Write, 1: Read"] -pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop` reader - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart` reader - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] pub type RESTART_R = crate::BitReader; #[doc = "Field `restart` writer - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] -pub type RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `first_data_byte` reader - Data Command First Data Byte - 0: False, 1: True"] pub type FIRST_DATA_BYTE_R = crate::BitReader; #[doc = "Field `first_data_byte` writer - Data Command First Data Byte - 0: False, 1: True"] -pub type FIRST_DATA_BYTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIRST_DATA_BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] #[must_use] - pub fn dat(&mut self) -> DAT_W { - DAT_W::new(self) + pub fn dat(&mut self) -> DAT_W { + DAT_W::new(self, 0) } #[doc = "Bit 8 - Data Command READ Bit - 0: Write, 1: Read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W { - READ_W::new(self) + pub fn read(&mut self) -> READ_W { + READ_W::new(self, 8) } #[doc = "Bit 9 - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 9) } #[doc = "Bit 10 - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] #[inline(always)] #[must_use] - pub fn restart(&mut self) -> RESTART_W { - RESTART_W::new(self) + pub fn restart(&mut self) -> RESTART_W { + RESTART_W::new(self, 10) } #[doc = "Bit 11 - Data Command First Data Byte - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { - FIRST_DATA_BYTE_W::new(self) + pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { + FIRST_DATA_BYTE_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/enable.rs b/jh7110-vf2-12a-pac/src/i2c1/enable.rs index c5ca9d7..3629f6b 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/enable.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/enable.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `abort` reader - abort"] pub type ABORT_R = crate::BitReader; #[doc = "Field `abort` writer - abort"] -pub type ABORT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 1 - abort"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 1 - abort"] #[inline(always)] #[must_use] - pub fn abort(&mut self) -> ABORT_W { - ABORT_W::new(self) + pub fn abort(&mut self) -> ABORT_W { + ABORT_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/enable_status.rs b/jh7110-vf2-12a-pac/src/i2c1/enable_status.rs index 2c102a6..8b9b7d3 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/enable_status.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/enable_status.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `activity` reader - activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tfe` reader - tfe"] pub type TFE_R = crate::BitReader; #[doc = "Field `tfe` writer - tfe"] -pub type TFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TFE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfne` reader - rfne"] pub type RFNE_R = crate::BitReader; #[doc = "Field `rfne` writer - rfne"] -pub type RFNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFNE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_activity` reader - master_activity"] pub type MASTER_ACTIVITY_R = crate::BitReader; #[doc = "Field `master_activity` writer - master_activity"] -pub type MASTER_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_activity` reader - slave_activity"] pub type SLAVE_ACTIVITY_R = crate::BitReader; #[doc = "Field `slave_activity` writer - slave_activity"] -pub type SLAVE_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - activity"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 0) } #[doc = "Bit 2 - tfe"] #[inline(always)] #[must_use] - pub fn tfe(&mut self) -> TFE_W { - TFE_W::new(self) + pub fn tfe(&mut self) -> TFE_W { + TFE_W::new(self, 2) } #[doc = "Bit 3 - rfne"] #[inline(always)] #[must_use] - pub fn rfne(&mut self) -> RFNE_W { - RFNE_W::new(self) + pub fn rfne(&mut self) -> RFNE_W { + RFNE_W::new(self, 3) } #[doc = "Bit 5 - master_activity"] #[inline(always)] #[must_use] - pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { - MASTER_ACTIVITY_W::new(self) + pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { + MASTER_ACTIVITY_W::new(self, 5) } #[doc = "Bit 6 - slave_activity"] #[inline(always)] #[must_use] - pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { - SLAVE_ACTIVITY_W::new(self) + pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { + SLAVE_ACTIVITY_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/fs_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c1/fs_scl_hcnt.rs index 9a9fd72..8a4f6d1 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/fs_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/fs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_hcnt` reader - fs_scl_hcnt"] pub type FS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_hcnt` writer - fs_scl_hcnt"] -pub type FS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { - FS_SCL_HCNT_W::new(self) + pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { + FS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/fs_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c1/fs_scl_lcnt.rs index 5e41cd1..4b4dd6b 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/fs_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/fs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_lcnt` reader - fs_scl_lcnt"] pub type FS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_lcnt` writer - fs_scl_lcnt"] -pub type FS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { - FS_SCL_LCNT_W::new(self) + pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { + FS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/hs_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c1/hs_scl_hcnt.rs index fba7f13..9b0a71c 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/hs_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/hs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_hcnt` reader - hs_scl_hcnt"] pub type HS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_hcnt` writer - hs_scl_hcnt"] -pub type HS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { - HS_SCL_HCNT_W::new(self) + pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { + HS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/hs_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c1/hs_scl_lcnt.rs index 9fca7a5..a715282 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/hs_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/hs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_lcnt` reader - hs_scl_lcnt"] pub type HS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_lcnt` writer - hs_scl_lcnt"] -pub type HS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { - HS_SCL_LCNT_W::new(self) + pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { + HS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/intr_mask.rs b/jh7110-vf2-12a-pac/src/i2c1/intr_mask.rs index 20a334f..769b629 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/intr_mask.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/intr_mask.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/intr_stat.rs b/jh7110-vf2-12a-pac/src/i2c1/intr_stat.rs index 2c2ba34..f376c26 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/intr_stat.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/raw_intr_stat.rs b/jh7110-vf2-12a-pac/src/i2c1/raw_intr_stat.rs index af97981..dd5e8e0 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/raw_intr_stat.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/raw_intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/rx_tl.rs b/jh7110-vf2-12a-pac/src/i2c1/rx_tl.rs index 1455a10..f3f39f4 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/rx_tl.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/rx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rx_tl` reader - rx_tl"] pub type RX_TL_R = crate::FieldReader; #[doc = "Field `rx_tl` writer - rx_tl"] -pub type RX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] #[must_use] - pub fn rx_tl(&mut self) -> RX_TL_W { - RX_TL_W::new(self) + pub fn rx_tl(&mut self) -> RX_TL_W { + RX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/rxflr.rs b/jh7110-vf2-12a-pac/src/i2c1/rxflr.rs index 910e254..4dccf5e 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/rxflr.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/rxflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rxflr` reader - rxflr"] pub type RXFLR_R = crate::FieldReader; #[doc = "Field `rxflr` writer - rxflr"] -pub type RXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] #[must_use] - pub fn rxflr(&mut self) -> RXFLR_W { - RXFLR_W::new(self) + pub fn rxflr(&mut self) -> RXFLR_W { + RXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/sar.rs b/jh7110-vf2-12a-pac/src/i2c1/sar.rs index d272e7a..1af6273 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/sar.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/sar.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Slave address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Slave address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Slave address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Slave address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; impl R { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Slave address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/sda_hold.rs b/jh7110-vf2-12a-pac/src/i2c1/sda_hold.rs index 82ceac5..d5d7512 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/sda_hold.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/sda_hold.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sda_hold` reader - sda_hold"] pub type SDA_HOLD_R = crate::FieldReader; #[doc = "Field `sda_hold` writer - sda_hold"] -pub type SDA_HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SDA_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] #[must_use] - pub fn sda_hold(&mut self) -> SDA_HOLD_W { - SDA_HOLD_W::new(self) + pub fn sda_hold(&mut self) -> SDA_HOLD_W { + SDA_HOLD_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/ss_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c1/ss_scl_hcnt.rs index 33736c7..77d7ea0 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/ss_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/ss_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_hcnt` reader - ss_scl_hcnt"] pub type SS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_hcnt` writer - ss_scl_hcnt"] -pub type SS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { - SS_SCL_HCNT_W::new(self) + pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { + SS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/ss_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c1/ss_scl_lcnt.rs index ce22b5d..8208747 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/ss_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/ss_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_lcnt` reader - ss_scl_lcnt"] pub type SS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_lcnt` writer - ss_scl_lcnt"] -pub type SS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { - SS_SCL_LCNT_W::new(self) + pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { + SS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/status.rs b/jh7110-vf2-12a-pac/src/i2c1/status.rs index 9489e49..1b7ab67 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/status.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/tar.rs b/jh7110-vf2-12a-pac/src/i2c1/tar.rs index 9fedc71..3044a8c 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/tar.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/tar.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Target address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Target address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Target address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Target address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; #[doc = "Field `mode` reader - Target addressing mode - 0: 7-bit, 1: 10-bit"] pub type MODE_R = crate::BitReader; #[doc = "Field `mode` writer - Target addressing mode - 0: 7-bit, 1: 10-bit"] -pub type MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Target address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } #[doc = "Bit 12 - Target addressing mode - 0: 7-bit, 1: 10-bit"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W { - MODE_W::new(self) + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 12) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/tx_abrt_source.rs b/jh7110-vf2-12a-pac/src/i2c1/tx_abrt_source.rs index 6f31813..c4fdf1a 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/tx_abrt_source.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/tx_abrt_source.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/tx_tl.rs b/jh7110-vf2-12a-pac/src/i2c1/tx_tl.rs index 84a1734..b0e6c64 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/tx_tl.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/tx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `tx_tl` reader - tx_tl"] pub type TX_TL_R = crate::FieldReader; #[doc = "Field `tx_tl` writer - tx_tl"] -pub type TX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] #[must_use] - pub fn tx_tl(&mut self) -> TX_TL_W { - TX_TL_W::new(self) + pub fn tx_tl(&mut self) -> TX_TL_W { + TX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c1/txflr.rs b/jh7110-vf2-12a-pac/src/i2c1/txflr.rs index b8e5fdd..5ca351d 100644 --- a/jh7110-vf2-12a-pac/src/i2c1/txflr.rs +++ b/jh7110-vf2-12a-pac/src/i2c1/txflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `txflr` reader - txflr"] pub type TXFLR_R = crate::FieldReader; #[doc = "Field `txflr` writer - txflr"] -pub type TXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - txflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - txflr"] #[inline(always)] #[must_use] - pub fn txflr(&mut self) -> TXFLR_W { - TXFLR_W::new(self) + pub fn txflr(&mut self) -> TXFLR_W { + TXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2.rs b/jh7110-vf2-12a-pac/src/i2c2.rs index d0fe76a..fdffe28 100644 --- a/jh7110-vf2-12a-pac/src/i2c2.rs +++ b/jh7110-vf2-12a-pac/src/i2c2.rs @@ -1,266 +1,416 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + con: CON, + tar: TAR, + sar: SAR, + _reserved3: [u8; 0x04], + data_cmd: DATA_CMD, + ss_scl_hcnt: SS_SCL_HCNT, + ss_scl_lcnt: SS_SCL_LCNT, + fs_scl_hcnt: FS_SCL_HCNT, + fs_scl_lcnt: FS_SCL_LCNT, + hs_scl_hcnt: HS_SCL_HCNT, + hs_scl_lcnt: HS_SCL_LCNT, + intr_stat: INTR_STAT, + intr_mask: INTR_MASK, + raw_intr_stat: RAW_INTR_STAT, + rx_tl: RX_TL, + tx_tl: TX_TL, + clr_intr: CLR_INTR, + clr_rx_under: CLR_RX_UNDER, + clr_rx_over: CLR_RX_OVER, + clr_tx_over: CLR_TX_OVER, + clr_rd_req: CLR_RD_REQ, + clr_tx_abrt: CLR_TX_ABRT, + clr_rx_done: CLR_RX_DONE, + clr_activity: CLR_ACTIVITY, + clr_stop_det: CLR_STOP_DET, + clr_start_det: CLR_START_DET, + clr_gen_call: CLR_GEN_CALL, + enable: ENABLE, + status: STATUS, + txflr: TXFLR, + rxflr: RXFLR, + sda_hold: SDA_HOLD, + tx_abrt_source: TX_ABRT_SOURCE, + _reserved32: [u8; 0x18], + enable_status: ENABLE_STATUS, + _reserved33: [u8; 0x08], + clr_restart_det: CLR_RESTART_DET, + _reserved34: [u8; 0x48], + comp_param_1: COMP_PARAM_1, + comp_version: COMP_VERSION, + comp_type: COMP_TYPE, +} +impl RegisterBlock { #[doc = "0x00 - DesignWare I2C CON"] - pub con: CON, + #[inline(always)] + pub const fn con(&self) -> &CON { + &self.con + } #[doc = "0x04 - DesignWare I2C TAR"] - pub tar: TAR, + #[inline(always)] + pub const fn tar(&self) -> &TAR { + &self.tar + } #[doc = "0x08 - DesignWare I2C SAR"] - pub sar: SAR, - _reserved3: [u8; 0x04], + #[inline(always)] + pub const fn sar(&self) -> &SAR { + &self.sar + } #[doc = "0x10 - DesignWare I2C Data Command"] - pub data_cmd: DATA_CMD, + #[inline(always)] + pub const fn data_cmd(&self) -> &DATA_CMD { + &self.data_cmd + } #[doc = "0x14 - DesignWare I2C SS SCL HCNT"] - pub ss_scl_hcnt: SS_SCL_HCNT, + #[inline(always)] + pub const fn ss_scl_hcnt(&self) -> &SS_SCL_HCNT { + &self.ss_scl_hcnt + } #[doc = "0x18 - DesignWare I2C SS SCL LCNT"] - pub ss_scl_lcnt: SS_SCL_LCNT, + #[inline(always)] + pub const fn ss_scl_lcnt(&self) -> &SS_SCL_LCNT { + &self.ss_scl_lcnt + } #[doc = "0x1c - DesignWare I2C FS SCL HCNT"] - pub fs_scl_hcnt: FS_SCL_HCNT, + #[inline(always)] + pub const fn fs_scl_hcnt(&self) -> &FS_SCL_HCNT { + &self.fs_scl_hcnt + } #[doc = "0x20 - DesignWare I2C FS SCL LCNT"] - pub fs_scl_lcnt: FS_SCL_LCNT, + #[inline(always)] + pub const fn fs_scl_lcnt(&self) -> &FS_SCL_LCNT { + &self.fs_scl_lcnt + } #[doc = "0x24 - DesignWare I2C HS SCL HCNT"] - pub hs_scl_hcnt: HS_SCL_HCNT, + #[inline(always)] + pub const fn hs_scl_hcnt(&self) -> &HS_SCL_HCNT { + &self.hs_scl_hcnt + } #[doc = "0x28 - DesignWare I2C HS SCL LCNT"] - pub hs_scl_lcnt: HS_SCL_LCNT, + #[inline(always)] + pub const fn hs_scl_lcnt(&self) -> &HS_SCL_LCNT { + &self.hs_scl_lcnt + } #[doc = "0x2c - DesignWare I2C Interrupt Status"] - pub intr_stat: INTR_STAT, + #[inline(always)] + pub const fn intr_stat(&self) -> &INTR_STAT { + &self.intr_stat + } #[doc = "0x30 - DesignWare I2C Interrupt Mask"] - pub intr_mask: INTR_MASK, + #[inline(always)] + pub const fn intr_mask(&self) -> &INTR_MASK { + &self.intr_mask + } #[doc = "0x34 - DesignWare I2C Raw Interrupt Status"] - pub raw_intr_stat: RAW_INTR_STAT, + #[inline(always)] + pub const fn raw_intr_stat(&self) -> &RAW_INTR_STAT { + &self.raw_intr_stat + } #[doc = "0x38 - DesignWare I2C RX TL"] - pub rx_tl: RX_TL, + #[inline(always)] + pub const fn rx_tl(&self) -> &RX_TL { + &self.rx_tl + } #[doc = "0x3c - DesignWare I2C TX TL"] - pub tx_tl: TX_TL, + #[inline(always)] + pub const fn tx_tl(&self) -> &TX_TL { + &self.tx_tl + } #[doc = "0x40 - DesignWare I2C Clear Interrrupt"] - pub clr_intr: CLR_INTR, + #[inline(always)] + pub const fn clr_intr(&self) -> &CLR_INTR { + &self.clr_intr + } #[doc = "0x44 - DesignWare I2C Clear RX Underrun"] - pub clr_rx_under: CLR_RX_UNDER, + #[inline(always)] + pub const fn clr_rx_under(&self) -> &CLR_RX_UNDER { + &self.clr_rx_under + } #[doc = "0x48 - DesignWare I2C Clear RX Overrun"] - pub clr_rx_over: CLR_RX_OVER, + #[inline(always)] + pub const fn clr_rx_over(&self) -> &CLR_RX_OVER { + &self.clr_rx_over + } #[doc = "0x4c - DesignWare I2C Clear TX Overrun"] - pub clr_tx_over: CLR_TX_OVER, + #[inline(always)] + pub const fn clr_tx_over(&self) -> &CLR_TX_OVER { + &self.clr_tx_over + } #[doc = "0x50 - DesignWare I2C Clear Read Request"] - pub clr_rd_req: CLR_RD_REQ, + #[inline(always)] + pub const fn clr_rd_req(&self) -> &CLR_RD_REQ { + &self.clr_rd_req + } #[doc = "0x54 - DesignWare I2C Clear TX Abort"] - pub clr_tx_abrt: CLR_TX_ABRT, + #[inline(always)] + pub const fn clr_tx_abrt(&self) -> &CLR_TX_ABRT { + &self.clr_tx_abrt + } #[doc = "0x58 - DesignWare I2C Clear RX Done"] - pub clr_rx_done: CLR_RX_DONE, + #[inline(always)] + pub const fn clr_rx_done(&self) -> &CLR_RX_DONE { + &self.clr_rx_done + } #[doc = "0x5c - DesignWare I2C Clear Activity"] - pub clr_activity: CLR_ACTIVITY, + #[inline(always)] + pub const fn clr_activity(&self) -> &CLR_ACTIVITY { + &self.clr_activity + } #[doc = "0x60 - DesignWare I2C Clear Stop DET"] - pub clr_stop_det: CLR_STOP_DET, + #[inline(always)] + pub const fn clr_stop_det(&self) -> &CLR_STOP_DET { + &self.clr_stop_det + } #[doc = "0x64 - DesignWare I2C Clear Start DET"] - pub clr_start_det: CLR_START_DET, + #[inline(always)] + pub const fn clr_start_det(&self) -> &CLR_START_DET { + &self.clr_start_det + } #[doc = "0x68 - DesignWare I2C Clear General Call"] - pub clr_gen_call: CLR_GEN_CALL, + #[inline(always)] + pub const fn clr_gen_call(&self) -> &CLR_GEN_CALL { + &self.clr_gen_call + } #[doc = "0x6c - DesignWare I2C Enable"] - pub enable: ENABLE, + #[inline(always)] + pub const fn enable(&self) -> &ENABLE { + &self.enable + } #[doc = "0x70 - DesignWare I2C Status"] - pub status: STATUS, + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } #[doc = "0x74 - DesignWare I2C TX Failure"] - pub txflr: TXFLR, + #[inline(always)] + pub const fn txflr(&self) -> &TXFLR { + &self.txflr + } #[doc = "0x78 - DesignWare I2C RX Failure"] - pub rxflr: RXFLR, + #[inline(always)] + pub const fn rxflr(&self) -> &RXFLR { + &self.rxflr + } #[doc = "0x7c - DesignWare I2C SDA Hold"] - pub sda_hold: SDA_HOLD, + #[inline(always)] + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold + } #[doc = "0x80 - DesignWare I2C TX Abort Source"] - pub tx_abrt_source: TX_ABRT_SOURCE, - _reserved32: [u8; 0x18], + #[inline(always)] + pub const fn tx_abrt_source(&self) -> &TX_ABRT_SOURCE { + &self.tx_abrt_source + } #[doc = "0x9c - DesignWare I2C Enable Status"] - pub enable_status: ENABLE_STATUS, - _reserved33: [u8; 0x08], + #[inline(always)] + pub const fn enable_status(&self) -> &ENABLE_STATUS { + &self.enable_status + } #[doc = "0xa8 - DesignWare I2C Clear Restart DET"] - pub clr_restart_det: CLR_RESTART_DET, - _reserved34: [u8; 0x48], + #[inline(always)] + pub const fn clr_restart_det(&self) -> &CLR_RESTART_DET { + &self.clr_restart_det + } #[doc = "0xf4 - DesignWare I2C Compatibility Parameter 1"] - pub comp_param_1: COMP_PARAM_1, + #[inline(always)] + pub const fn comp_param_1(&self) -> &COMP_PARAM_1 { + &self.comp_param_1 + } #[doc = "0xf8 - DesignWare I2C Compatibility Version"] - pub comp_version: COMP_VERSION, + #[inline(always)] + pub const fn comp_version(&self) -> &COMP_VERSION { + &self.comp_version + } #[doc = "0xfc - DesignWare I2C Compatibility Type"] - pub comp_type: COMP_TYPE, + #[inline(always)] + pub const fn comp_type(&self) -> &COMP_TYPE { + &self.comp_type + } } -#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`con`] +#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@con`] module"] pub type CON = crate::Reg; #[doc = "DesignWare I2C CON"] pub mod con; -#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tar`] +#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar`] module"] pub type TAR = crate::Reg; #[doc = "DesignWare I2C TAR"] pub mod tar; -#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sar`] +#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`] module"] pub type SAR = crate::Reg; #[doc = "DesignWare I2C SAR"] pub mod sar; -#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`data_cmd`] +#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_cmd`] module"] pub type DATA_CMD = crate::Reg; #[doc = "DesignWare I2C Data Command"] pub mod data_cmd; -#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_hcnt`] +#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_hcnt`] module"] pub type SS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL HCNT"] pub mod ss_scl_hcnt; -#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_lcnt`] +#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_lcnt`] module"] pub type SS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL LCNT"] pub mod ss_scl_lcnt; -#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_hcnt`] +#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_hcnt`] module"] pub type FS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL HCNT"] pub mod fs_scl_hcnt; -#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_lcnt`] +#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_lcnt`] module"] pub type FS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL LCNT"] pub mod fs_scl_lcnt; -#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_hcnt`] +#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_hcnt`] module"] pub type HS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL HCNT"] pub mod hs_scl_hcnt; -#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_lcnt`] +#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_lcnt`] module"] pub type HS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL LCNT"] pub mod hs_scl_lcnt; -#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_stat`] +#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"] pub type INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Interrupt Status"] pub mod intr_stat; -#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_mask`] +#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mask`] module"] pub type INTR_MASK = crate::Reg; #[doc = "DesignWare I2C Interrupt Mask"] pub mod intr_mask; -#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`raw_intr_stat`] +#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"] pub type RAW_INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Raw Interrupt Status"] pub mod raw_intr_stat; -#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rx_tl`] +#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tl`] module"] pub type RX_TL = crate::Reg; #[doc = "DesignWare I2C RX TL"] pub mod rx_tl; -#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_tl`] +#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_tl`] module"] pub type TX_TL = crate::Reg; #[doc = "DesignWare I2C TX TL"] pub mod tx_tl; -#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_intr`] +#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_intr`] module"] pub type CLR_INTR = crate::Reg; #[doc = "DesignWare I2C Clear Interrrupt"] pub mod clr_intr; -#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_under`] +#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_under`] module"] pub type CLR_RX_UNDER = crate::Reg; #[doc = "DesignWare I2C Clear RX Underrun"] pub mod clr_rx_under; -#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_over`] +#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_over`] module"] pub type CLR_RX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear RX Overrun"] pub mod clr_rx_over; -#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_over`] +#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_over`] module"] pub type CLR_TX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear TX Overrun"] pub mod clr_tx_over; -#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rd_req`] +#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rd_req`] module"] pub type CLR_RD_REQ = crate::Reg; #[doc = "DesignWare I2C Clear Read Request"] pub mod clr_rd_req; -#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_abrt`] +#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_abrt`] module"] pub type CLR_TX_ABRT = crate::Reg; #[doc = "DesignWare I2C Clear TX Abort"] pub mod clr_tx_abrt; -#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_done`] +#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_done`] module"] pub type CLR_RX_DONE = crate::Reg; #[doc = "DesignWare I2C Clear RX Done"] pub mod clr_rx_done; -#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_activity`] +#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_activity`] module"] pub type CLR_ACTIVITY = crate::Reg; #[doc = "DesignWare I2C Clear Activity"] pub mod clr_activity; -#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_stop_det`] +#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_stop_det`] module"] pub type CLR_STOP_DET = crate::Reg; #[doc = "DesignWare I2C Clear Stop DET"] pub mod clr_stop_det; -#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_start_det`] +#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_start_det`] module"] pub type CLR_START_DET = crate::Reg; #[doc = "DesignWare I2C Clear Start DET"] pub mod clr_start_det; -#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_gen_call`] +#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_gen_call`] module"] pub type CLR_GEN_CALL = crate::Reg; #[doc = "DesignWare I2C Clear General Call"] pub mod clr_gen_call; -#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable`] +#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] pub type ENABLE = crate::Reg; #[doc = "DesignWare I2C Enable"] pub mod enable; -#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`status`] +#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] pub type STATUS = crate::Reg; #[doc = "DesignWare I2C Status"] pub mod status; -#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txflr`] +#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txflr`] module"] pub type TXFLR = crate::Reg; #[doc = "DesignWare I2C TX Failure"] pub mod txflr; -#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxflr`] +#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxflr`] module"] pub type RXFLR = crate::Reg; #[doc = "DesignWare I2C RX Failure"] pub mod rxflr; -#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sda_hold`] +#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] pub type SDA_HOLD = crate::Reg; #[doc = "DesignWare I2C SDA Hold"] pub mod sda_hold; -#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_abrt_source`] +#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_abrt_source`] module"] pub type TX_ABRT_SOURCE = crate::Reg; #[doc = "DesignWare I2C TX Abort Source"] pub mod tx_abrt_source; -#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_status`] +#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_status`] module"] pub type ENABLE_STATUS = crate::Reg; #[doc = "DesignWare I2C Enable Status"] pub mod enable_status; -#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_restart_det`] +#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_restart_det`] module"] pub type CLR_RESTART_DET = crate::Reg; #[doc = "DesignWare I2C Clear Restart DET"] pub mod clr_restart_det; -#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_param_1`] +#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_param_1`] module"] pub type COMP_PARAM_1 = crate::Reg; #[doc = "DesignWare I2C Compatibility Parameter 1"] pub mod comp_param_1; -#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_version`] +#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_version`] module"] pub type COMP_VERSION = crate::Reg; #[doc = "DesignWare I2C Compatibility Version"] pub mod comp_version; -#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_type`] +#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_type`] module"] pub type COMP_TYPE = crate::Reg; #[doc = "DesignWare I2C Compatibility Type"] diff --git a/jh7110-vf2-12a-pac/src/i2c2/clr_activity.rs b/jh7110-vf2-12a-pac/src/i2c2/clr_activity.rs index d26bb80..1ee2297 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/clr_activity.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/clr_activity.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_activity` reader - clr_activity"] pub type CLR_ACTIVITY_R = crate::FieldReader; #[doc = "Field `clr_activity` writer - clr_activity"] -pub type CLR_ACTIVITY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_ACTIVITY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] #[must_use] - pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { - CLR_ACTIVITY_W::new(self) + pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { + CLR_ACTIVITY_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/clr_gen_call.rs b/jh7110-vf2-12a-pac/src/i2c2/clr_gen_call.rs index a9ea5af..4a7c5ba 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/clr_gen_call.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/clr_gen_call.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_gen_call` reader - clr_gen_call"] pub type CLR_GEN_CALL_R = crate::FieldReader; #[doc = "Field `clr_gen_call` writer - clr_gen_call"] -pub type CLR_GEN_CALL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_GEN_CALL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] #[must_use] - pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { - CLR_GEN_CALL_W::new(self) + pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { + CLR_GEN_CALL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/clr_intr.rs b/jh7110-vf2-12a-pac/src/i2c2/clr_intr.rs index a7daf57..cf57b09 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/clr_intr.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/clr_intr.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/clr_rd_req.rs b/jh7110-vf2-12a-pac/src/i2c2/clr_rd_req.rs index e275da1..4beae9d 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/clr_rd_req.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/clr_rd_req.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rd_req` reader - clr_rd_req"] pub type CLR_RD_REQ_R = crate::FieldReader; #[doc = "Field `clr_rd_req` writer - clr_rd_req"] -pub type CLR_RD_REQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RD_REQ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] #[must_use] - pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { - CLR_RD_REQ_W::new(self) + pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { + CLR_RD_REQ_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/clr_restart_det.rs b/jh7110-vf2-12a-pac/src/i2c2/clr_restart_det.rs index 5be7f5d..88d193c 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/clr_restart_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/clr_restart_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_restart_det` reader - clr_restart_det"] pub type CLR_RESTART_DET_R = crate::FieldReader; #[doc = "Field `clr_restart_det` writer - clr_restart_det"] -pub type CLR_RESTART_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RESTART_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] #[must_use] - pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { - CLR_RESTART_DET_W::new(self) + pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { + CLR_RESTART_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/clr_rx_done.rs b/jh7110-vf2-12a-pac/src/i2c2/clr_rx_done.rs index 02d83c5..7e14a3f 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/clr_rx_done.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/clr_rx_done.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_done` reader - clr_rx_done"] pub type CLR_RX_DONE_R = crate::FieldReader; #[doc = "Field `clr_rx_done` writer - clr_rx_done"] -pub type CLR_RX_DONE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_DONE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] #[must_use] - pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { - CLR_RX_DONE_W::new(self) + pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { + CLR_RX_DONE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/clr_rx_over.rs b/jh7110-vf2-12a-pac/src/i2c2/clr_rx_over.rs index 6d7ff4e..2302921 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/clr_rx_over.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/clr_rx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_over` reader - clr_rx_over"] pub type CLR_RX_OVER_R = crate::FieldReader; #[doc = "Field `clr_rx_over` writer - clr_rx_over"] -pub type CLR_RX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] #[must_use] - pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { - CLR_RX_OVER_W::new(self) + pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { + CLR_RX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/clr_rx_under.rs b/jh7110-vf2-12a-pac/src/i2c2/clr_rx_under.rs index 4a24f7c..35e15bd 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/clr_rx_under.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/clr_rx_under.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_under` reader - clr_rx_under"] pub type CLR_RX_UNDER_R = crate::FieldReader; #[doc = "Field `clr_rx_under` writer - clr_rx_under"] -pub type CLR_RX_UNDER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_UNDER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] #[must_use] - pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { - CLR_RX_UNDER_W::new(self) + pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { + CLR_RX_UNDER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/clr_start_det.rs b/jh7110-vf2-12a-pac/src/i2c2/clr_start_det.rs index cebc4bc..2314f65 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/clr_start_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/clr_start_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_start_det` reader - clr_start_det"] pub type CLR_START_DET_R = crate::FieldReader; #[doc = "Field `clr_start_det` writer - clr_start_det"] -pub type CLR_START_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_START_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] #[must_use] - pub fn clr_start_det(&mut self) -> CLR_START_DET_W { - CLR_START_DET_W::new(self) + pub fn clr_start_det(&mut self) -> CLR_START_DET_W { + CLR_START_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/clr_stop_det.rs b/jh7110-vf2-12a-pac/src/i2c2/clr_stop_det.rs index 44f39f3..49abcac 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/clr_stop_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/clr_stop_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_stop_det` reader - clr_stop_det"] pub type CLR_STOP_DET_R = crate::FieldReader; #[doc = "Field `clr_stop_det` writer - clr_stop_det"] -pub type CLR_STOP_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_STOP_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] #[must_use] - pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { - CLR_STOP_DET_W::new(self) + pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { + CLR_STOP_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/clr_tx_abrt.rs b/jh7110-vf2-12a-pac/src/i2c2/clr_tx_abrt.rs index 6ac441c..3bc0f6f 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/clr_tx_abrt.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/clr_tx_abrt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_abrt` reader - clr_tx_abrt"] pub type CLR_TX_ABRT_R = crate::FieldReader; #[doc = "Field `clr_tx_abrt` writer - clr_tx_abrt"] -pub type CLR_TX_ABRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_ABRT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] #[must_use] - pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { - CLR_TX_ABRT_W::new(self) + pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { + CLR_TX_ABRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/clr_tx_over.rs b/jh7110-vf2-12a-pac/src/i2c2/clr_tx_over.rs index 2b32b52..a5b6933 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/clr_tx_over.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/clr_tx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_over` reader - clr_tx_over"] pub type CLR_TX_OVER_R = crate::FieldReader; #[doc = "Field `clr_tx_over` writer - clr_tx_over"] -pub type CLR_TX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] #[must_use] - pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { - CLR_TX_OVER_W::new(self) + pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { + CLR_TX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/comp_param_1.rs b/jh7110-vf2-12a-pac/src/i2c2/comp_param_1.rs index 24a22e1..95c5002 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/comp_param_1.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/comp_param_1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/comp_type.rs b/jh7110-vf2-12a-pac/src/i2c2/comp_type.rs index ac916b5..1336c43 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/comp_type.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/comp_type.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/comp_version.rs b/jh7110-vf2-12a-pac/src/i2c2/comp_version.rs index 4be31fa..e8309c8 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/comp_version.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/comp_version.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/con.rs b/jh7110-vf2-12a-pac/src/i2c2/con.rs index 873c534..28aa865 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/con.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/con.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `master` reader - I2C Master Connection - 0: Slave, 1: Master"] pub type MASTER_R = crate::BitReader; #[doc = "Field `master` writer - I2C Master Connection - 0: Slave, 1: Master"] -pub type MASTER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `speed` reader - I2C Speed - 01: Standard, 10: Fast, 11: High"] pub type SPEED_R = crate::FieldReader; #[doc = "Field `speed` writer - I2C Speed - 01: Standard, 10: Fast, 11: High"] -pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `slave_10bitaddr` reader - I2C Slave 10-bit Address - 0: False, 1: True"] pub type SLAVE_10BITADDR_R = crate::BitReader; #[doc = "Field `slave_10bitaddr` writer - I2C Slave 10-bit Address - 0: False, 1: True"] -pub type SLAVE_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_10bitaddr` reader - I2C Master 10-bit Address - 0: False, 1: True"] pub type MASTER_10BITADDR_R = crate::BitReader; #[doc = "Field `master_10bitaddr` writer - I2C Master 10-bit Address - 0: False, 1: True"] -pub type MASTER_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_en` reader - I2C Restart Enable - 0: False, 1: True"] pub type RESTART_EN_R = crate::BitReader; #[doc = "Field `restart_en` writer - I2C Restart Enable - 0: False, 1: True"] -pub type RESTART_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_disable` reader - I2C Slave Disable - 0: False, 1: True"] pub type SLAVE_DISABLE_R = crate::BitReader; #[doc = "Field `slave_disable` writer - I2C Slave Disable - 0: False, 1: True"] -pub type SLAVE_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det_ifaddressed` reader - I2C Stop DET If Addressed - 0: False, 1: True"] pub type STOP_DET_IFADDRESSED_R = crate::BitReader; #[doc = "Field `stop_det_ifaddressed` writer - I2C Stop DET If Addressed - 0: False, 1: True"] -pub type STOP_DET_IFADDRESSED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty_ctrl` reader - I2C TX Empty Control - 0: False, 1: True"] pub type TX_EMPTY_CTRL_R = crate::BitReader; #[doc = "Field `tx_empty_ctrl` writer - I2C TX Empty Control - 0: False, 1: True"] -pub type TX_EMPTY_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_fifo_full_hld_ctrl` reader - I2C RX FIFO Full Hold Control - 0: False, 1: True"] pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; #[doc = "Field `rx_fifo_full_hld_ctrl` writer - I2C RX FIFO Full Hold Control - 0: False, 1: True"] -pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bus_clear_ctrl` reader - I2C Bus Clear Control - 0: False, 1: True"] pub type BUS_CLEAR_CTRL_R = crate::BitReader; #[doc = "Field `bus_clear_ctrl` writer - I2C Bus Clear Control - 0: False, 1: True"] -pub type BUS_CLEAR_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BUS_CLEAR_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] #[must_use] - pub fn master(&mut self) -> MASTER_W { - MASTER_W::new(self) + pub fn master(&mut self) -> MASTER_W { + MASTER_W::new(self, 0) } #[doc = "Bits 1:2 - I2C Speed - 01: Standard, 10: Fast, 11: High"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W { - SPEED_W::new(self) + pub fn speed(&mut self) -> SPEED_W { + SPEED_W::new(self, 1) } #[doc = "Bit 3 - I2C Slave 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { - SLAVE_10BITADDR_W::new(self) + pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { + SLAVE_10BITADDR_W::new(self, 3) } #[doc = "Bit 4 - I2C Master 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { - MASTER_10BITADDR_W::new(self) + pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { + MASTER_10BITADDR_W::new(self, 4) } #[doc = "Bit 5 - I2C Restart Enable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn restart_en(&mut self) -> RESTART_EN_W { - RESTART_EN_W::new(self) + pub fn restart_en(&mut self) -> RESTART_EN_W { + RESTART_EN_W::new(self, 5) } #[doc = "Bit 6 - I2C Slave Disable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { - SLAVE_DISABLE_W::new(self) + pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { + SLAVE_DISABLE_W::new(self, 6) } #[doc = "Bit 7 - I2C Stop DET If Addressed - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { - STOP_DET_IFADDRESSED_W::new(self) + pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { + STOP_DET_IFADDRESSED_W::new(self, 7) } #[doc = "Bit 8 - I2C TX Empty Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { - TX_EMPTY_CTRL_W::new(self) + pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { + TX_EMPTY_CTRL_W::new(self, 8) } #[doc = "Bit 9 - I2C RX FIFO Full Hold Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { - RX_FIFO_FULL_HLD_CTRL_W::new(self) + pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { + RX_FIFO_FULL_HLD_CTRL_W::new(self, 9) } #[doc = "Bit 11 - I2C Bus Clear Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { - BUS_CLEAR_CTRL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { + BUS_CLEAR_CTRL_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/data_cmd.rs b/jh7110-vf2-12a-pac/src/i2c2/data_cmd.rs index cf36408..2b320d4 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/data_cmd.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/data_cmd.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `dat` reader - Data Command Data Byte"] pub type DAT_R = crate::FieldReader; #[doc = "Field `dat` writer - Data Command Data Byte"] -pub type DAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `read` reader - Data Command READ Bit - 0: Write, 1: Read"] pub type READ_R = crate::BitReader; #[doc = "Field `read` writer - Data Command READ Bit - 0: Write, 1: Read"] -pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop` reader - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart` reader - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] pub type RESTART_R = crate::BitReader; #[doc = "Field `restart` writer - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] -pub type RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `first_data_byte` reader - Data Command First Data Byte - 0: False, 1: True"] pub type FIRST_DATA_BYTE_R = crate::BitReader; #[doc = "Field `first_data_byte` writer - Data Command First Data Byte - 0: False, 1: True"] -pub type FIRST_DATA_BYTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIRST_DATA_BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] #[must_use] - pub fn dat(&mut self) -> DAT_W { - DAT_W::new(self) + pub fn dat(&mut self) -> DAT_W { + DAT_W::new(self, 0) } #[doc = "Bit 8 - Data Command READ Bit - 0: Write, 1: Read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W { - READ_W::new(self) + pub fn read(&mut self) -> READ_W { + READ_W::new(self, 8) } #[doc = "Bit 9 - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 9) } #[doc = "Bit 10 - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] #[inline(always)] #[must_use] - pub fn restart(&mut self) -> RESTART_W { - RESTART_W::new(self) + pub fn restart(&mut self) -> RESTART_W { + RESTART_W::new(self, 10) } #[doc = "Bit 11 - Data Command First Data Byte - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { - FIRST_DATA_BYTE_W::new(self) + pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { + FIRST_DATA_BYTE_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/enable.rs b/jh7110-vf2-12a-pac/src/i2c2/enable.rs index c5ca9d7..3629f6b 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/enable.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/enable.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `abort` reader - abort"] pub type ABORT_R = crate::BitReader; #[doc = "Field `abort` writer - abort"] -pub type ABORT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 1 - abort"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 1 - abort"] #[inline(always)] #[must_use] - pub fn abort(&mut self) -> ABORT_W { - ABORT_W::new(self) + pub fn abort(&mut self) -> ABORT_W { + ABORT_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/enable_status.rs b/jh7110-vf2-12a-pac/src/i2c2/enable_status.rs index 2c102a6..8b9b7d3 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/enable_status.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/enable_status.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `activity` reader - activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tfe` reader - tfe"] pub type TFE_R = crate::BitReader; #[doc = "Field `tfe` writer - tfe"] -pub type TFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TFE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfne` reader - rfne"] pub type RFNE_R = crate::BitReader; #[doc = "Field `rfne` writer - rfne"] -pub type RFNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFNE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_activity` reader - master_activity"] pub type MASTER_ACTIVITY_R = crate::BitReader; #[doc = "Field `master_activity` writer - master_activity"] -pub type MASTER_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_activity` reader - slave_activity"] pub type SLAVE_ACTIVITY_R = crate::BitReader; #[doc = "Field `slave_activity` writer - slave_activity"] -pub type SLAVE_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - activity"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 0) } #[doc = "Bit 2 - tfe"] #[inline(always)] #[must_use] - pub fn tfe(&mut self) -> TFE_W { - TFE_W::new(self) + pub fn tfe(&mut self) -> TFE_W { + TFE_W::new(self, 2) } #[doc = "Bit 3 - rfne"] #[inline(always)] #[must_use] - pub fn rfne(&mut self) -> RFNE_W { - RFNE_W::new(self) + pub fn rfne(&mut self) -> RFNE_W { + RFNE_W::new(self, 3) } #[doc = "Bit 5 - master_activity"] #[inline(always)] #[must_use] - pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { - MASTER_ACTIVITY_W::new(self) + pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { + MASTER_ACTIVITY_W::new(self, 5) } #[doc = "Bit 6 - slave_activity"] #[inline(always)] #[must_use] - pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { - SLAVE_ACTIVITY_W::new(self) + pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { + SLAVE_ACTIVITY_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/fs_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c2/fs_scl_hcnt.rs index 9a9fd72..8a4f6d1 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/fs_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/fs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_hcnt` reader - fs_scl_hcnt"] pub type FS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_hcnt` writer - fs_scl_hcnt"] -pub type FS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { - FS_SCL_HCNT_W::new(self) + pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { + FS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/fs_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c2/fs_scl_lcnt.rs index 5e41cd1..4b4dd6b 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/fs_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/fs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_lcnt` reader - fs_scl_lcnt"] pub type FS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_lcnt` writer - fs_scl_lcnt"] -pub type FS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { - FS_SCL_LCNT_W::new(self) + pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { + FS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/hs_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c2/hs_scl_hcnt.rs index fba7f13..9b0a71c 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/hs_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/hs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_hcnt` reader - hs_scl_hcnt"] pub type HS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_hcnt` writer - hs_scl_hcnt"] -pub type HS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { - HS_SCL_HCNT_W::new(self) + pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { + HS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/hs_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c2/hs_scl_lcnt.rs index 9fca7a5..a715282 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/hs_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/hs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_lcnt` reader - hs_scl_lcnt"] pub type HS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_lcnt` writer - hs_scl_lcnt"] -pub type HS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { - HS_SCL_LCNT_W::new(self) + pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { + HS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/intr_mask.rs b/jh7110-vf2-12a-pac/src/i2c2/intr_mask.rs index 20a334f..769b629 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/intr_mask.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/intr_mask.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/intr_stat.rs b/jh7110-vf2-12a-pac/src/i2c2/intr_stat.rs index 2c2ba34..f376c26 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/intr_stat.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/raw_intr_stat.rs b/jh7110-vf2-12a-pac/src/i2c2/raw_intr_stat.rs index af97981..dd5e8e0 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/raw_intr_stat.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/raw_intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/rx_tl.rs b/jh7110-vf2-12a-pac/src/i2c2/rx_tl.rs index 1455a10..f3f39f4 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/rx_tl.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/rx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rx_tl` reader - rx_tl"] pub type RX_TL_R = crate::FieldReader; #[doc = "Field `rx_tl` writer - rx_tl"] -pub type RX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] #[must_use] - pub fn rx_tl(&mut self) -> RX_TL_W { - RX_TL_W::new(self) + pub fn rx_tl(&mut self) -> RX_TL_W { + RX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/rxflr.rs b/jh7110-vf2-12a-pac/src/i2c2/rxflr.rs index 910e254..4dccf5e 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/rxflr.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/rxflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rxflr` reader - rxflr"] pub type RXFLR_R = crate::FieldReader; #[doc = "Field `rxflr` writer - rxflr"] -pub type RXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] #[must_use] - pub fn rxflr(&mut self) -> RXFLR_W { - RXFLR_W::new(self) + pub fn rxflr(&mut self) -> RXFLR_W { + RXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/sar.rs b/jh7110-vf2-12a-pac/src/i2c2/sar.rs index d272e7a..1af6273 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/sar.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/sar.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Slave address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Slave address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Slave address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Slave address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; impl R { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Slave address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/sda_hold.rs b/jh7110-vf2-12a-pac/src/i2c2/sda_hold.rs index 82ceac5..d5d7512 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/sda_hold.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/sda_hold.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sda_hold` reader - sda_hold"] pub type SDA_HOLD_R = crate::FieldReader; #[doc = "Field `sda_hold` writer - sda_hold"] -pub type SDA_HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SDA_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] #[must_use] - pub fn sda_hold(&mut self) -> SDA_HOLD_W { - SDA_HOLD_W::new(self) + pub fn sda_hold(&mut self) -> SDA_HOLD_W { + SDA_HOLD_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/ss_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c2/ss_scl_hcnt.rs index 33736c7..77d7ea0 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/ss_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/ss_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_hcnt` reader - ss_scl_hcnt"] pub type SS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_hcnt` writer - ss_scl_hcnt"] -pub type SS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { - SS_SCL_HCNT_W::new(self) + pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { + SS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/ss_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c2/ss_scl_lcnt.rs index ce22b5d..8208747 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/ss_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/ss_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_lcnt` reader - ss_scl_lcnt"] pub type SS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_lcnt` writer - ss_scl_lcnt"] -pub type SS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { - SS_SCL_LCNT_W::new(self) + pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { + SS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/status.rs b/jh7110-vf2-12a-pac/src/i2c2/status.rs index 9489e49..1b7ab67 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/status.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/tar.rs b/jh7110-vf2-12a-pac/src/i2c2/tar.rs index 9fedc71..3044a8c 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/tar.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/tar.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Target address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Target address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Target address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Target address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; #[doc = "Field `mode` reader - Target addressing mode - 0: 7-bit, 1: 10-bit"] pub type MODE_R = crate::BitReader; #[doc = "Field `mode` writer - Target addressing mode - 0: 7-bit, 1: 10-bit"] -pub type MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Target address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } #[doc = "Bit 12 - Target addressing mode - 0: 7-bit, 1: 10-bit"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W { - MODE_W::new(self) + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 12) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/tx_abrt_source.rs b/jh7110-vf2-12a-pac/src/i2c2/tx_abrt_source.rs index 6f31813..c4fdf1a 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/tx_abrt_source.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/tx_abrt_source.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/tx_tl.rs b/jh7110-vf2-12a-pac/src/i2c2/tx_tl.rs index 84a1734..b0e6c64 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/tx_tl.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/tx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `tx_tl` reader - tx_tl"] pub type TX_TL_R = crate::FieldReader; #[doc = "Field `tx_tl` writer - tx_tl"] -pub type TX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] #[must_use] - pub fn tx_tl(&mut self) -> TX_TL_W { - TX_TL_W::new(self) + pub fn tx_tl(&mut self) -> TX_TL_W { + TX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c2/txflr.rs b/jh7110-vf2-12a-pac/src/i2c2/txflr.rs index b8e5fdd..5ca351d 100644 --- a/jh7110-vf2-12a-pac/src/i2c2/txflr.rs +++ b/jh7110-vf2-12a-pac/src/i2c2/txflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `txflr` reader - txflr"] pub type TXFLR_R = crate::FieldReader; #[doc = "Field `txflr` writer - txflr"] -pub type TXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - txflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - txflr"] #[inline(always)] #[must_use] - pub fn txflr(&mut self) -> TXFLR_W { - TXFLR_W::new(self) + pub fn txflr(&mut self) -> TXFLR_W { + TXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3.rs b/jh7110-vf2-12a-pac/src/i2c3.rs index d0fe76a..fdffe28 100644 --- a/jh7110-vf2-12a-pac/src/i2c3.rs +++ b/jh7110-vf2-12a-pac/src/i2c3.rs @@ -1,266 +1,416 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + con: CON, + tar: TAR, + sar: SAR, + _reserved3: [u8; 0x04], + data_cmd: DATA_CMD, + ss_scl_hcnt: SS_SCL_HCNT, + ss_scl_lcnt: SS_SCL_LCNT, + fs_scl_hcnt: FS_SCL_HCNT, + fs_scl_lcnt: FS_SCL_LCNT, + hs_scl_hcnt: HS_SCL_HCNT, + hs_scl_lcnt: HS_SCL_LCNT, + intr_stat: INTR_STAT, + intr_mask: INTR_MASK, + raw_intr_stat: RAW_INTR_STAT, + rx_tl: RX_TL, + tx_tl: TX_TL, + clr_intr: CLR_INTR, + clr_rx_under: CLR_RX_UNDER, + clr_rx_over: CLR_RX_OVER, + clr_tx_over: CLR_TX_OVER, + clr_rd_req: CLR_RD_REQ, + clr_tx_abrt: CLR_TX_ABRT, + clr_rx_done: CLR_RX_DONE, + clr_activity: CLR_ACTIVITY, + clr_stop_det: CLR_STOP_DET, + clr_start_det: CLR_START_DET, + clr_gen_call: CLR_GEN_CALL, + enable: ENABLE, + status: STATUS, + txflr: TXFLR, + rxflr: RXFLR, + sda_hold: SDA_HOLD, + tx_abrt_source: TX_ABRT_SOURCE, + _reserved32: [u8; 0x18], + enable_status: ENABLE_STATUS, + _reserved33: [u8; 0x08], + clr_restart_det: CLR_RESTART_DET, + _reserved34: [u8; 0x48], + comp_param_1: COMP_PARAM_1, + comp_version: COMP_VERSION, + comp_type: COMP_TYPE, +} +impl RegisterBlock { #[doc = "0x00 - DesignWare I2C CON"] - pub con: CON, + #[inline(always)] + pub const fn con(&self) -> &CON { + &self.con + } #[doc = "0x04 - DesignWare I2C TAR"] - pub tar: TAR, + #[inline(always)] + pub const fn tar(&self) -> &TAR { + &self.tar + } #[doc = "0x08 - DesignWare I2C SAR"] - pub sar: SAR, - _reserved3: [u8; 0x04], + #[inline(always)] + pub const fn sar(&self) -> &SAR { + &self.sar + } #[doc = "0x10 - DesignWare I2C Data Command"] - pub data_cmd: DATA_CMD, + #[inline(always)] + pub const fn data_cmd(&self) -> &DATA_CMD { + &self.data_cmd + } #[doc = "0x14 - DesignWare I2C SS SCL HCNT"] - pub ss_scl_hcnt: SS_SCL_HCNT, + #[inline(always)] + pub const fn ss_scl_hcnt(&self) -> &SS_SCL_HCNT { + &self.ss_scl_hcnt + } #[doc = "0x18 - DesignWare I2C SS SCL LCNT"] - pub ss_scl_lcnt: SS_SCL_LCNT, + #[inline(always)] + pub const fn ss_scl_lcnt(&self) -> &SS_SCL_LCNT { + &self.ss_scl_lcnt + } #[doc = "0x1c - DesignWare I2C FS SCL HCNT"] - pub fs_scl_hcnt: FS_SCL_HCNT, + #[inline(always)] + pub const fn fs_scl_hcnt(&self) -> &FS_SCL_HCNT { + &self.fs_scl_hcnt + } #[doc = "0x20 - DesignWare I2C FS SCL LCNT"] - pub fs_scl_lcnt: FS_SCL_LCNT, + #[inline(always)] + pub const fn fs_scl_lcnt(&self) -> &FS_SCL_LCNT { + &self.fs_scl_lcnt + } #[doc = "0x24 - DesignWare I2C HS SCL HCNT"] - pub hs_scl_hcnt: HS_SCL_HCNT, + #[inline(always)] + pub const fn hs_scl_hcnt(&self) -> &HS_SCL_HCNT { + &self.hs_scl_hcnt + } #[doc = "0x28 - DesignWare I2C HS SCL LCNT"] - pub hs_scl_lcnt: HS_SCL_LCNT, + #[inline(always)] + pub const fn hs_scl_lcnt(&self) -> &HS_SCL_LCNT { + &self.hs_scl_lcnt + } #[doc = "0x2c - DesignWare I2C Interrupt Status"] - pub intr_stat: INTR_STAT, + #[inline(always)] + pub const fn intr_stat(&self) -> &INTR_STAT { + &self.intr_stat + } #[doc = "0x30 - DesignWare I2C Interrupt Mask"] - pub intr_mask: INTR_MASK, + #[inline(always)] + pub const fn intr_mask(&self) -> &INTR_MASK { + &self.intr_mask + } #[doc = "0x34 - DesignWare I2C Raw Interrupt Status"] - pub raw_intr_stat: RAW_INTR_STAT, + #[inline(always)] + pub const fn raw_intr_stat(&self) -> &RAW_INTR_STAT { + &self.raw_intr_stat + } #[doc = "0x38 - DesignWare I2C RX TL"] - pub rx_tl: RX_TL, + #[inline(always)] + pub const fn rx_tl(&self) -> &RX_TL { + &self.rx_tl + } #[doc = "0x3c - DesignWare I2C TX TL"] - pub tx_tl: TX_TL, + #[inline(always)] + pub const fn tx_tl(&self) -> &TX_TL { + &self.tx_tl + } #[doc = "0x40 - DesignWare I2C Clear Interrrupt"] - pub clr_intr: CLR_INTR, + #[inline(always)] + pub const fn clr_intr(&self) -> &CLR_INTR { + &self.clr_intr + } #[doc = "0x44 - DesignWare I2C Clear RX Underrun"] - pub clr_rx_under: CLR_RX_UNDER, + #[inline(always)] + pub const fn clr_rx_under(&self) -> &CLR_RX_UNDER { + &self.clr_rx_under + } #[doc = "0x48 - DesignWare I2C Clear RX Overrun"] - pub clr_rx_over: CLR_RX_OVER, + #[inline(always)] + pub const fn clr_rx_over(&self) -> &CLR_RX_OVER { + &self.clr_rx_over + } #[doc = "0x4c - DesignWare I2C Clear TX Overrun"] - pub clr_tx_over: CLR_TX_OVER, + #[inline(always)] + pub const fn clr_tx_over(&self) -> &CLR_TX_OVER { + &self.clr_tx_over + } #[doc = "0x50 - DesignWare I2C Clear Read Request"] - pub clr_rd_req: CLR_RD_REQ, + #[inline(always)] + pub const fn clr_rd_req(&self) -> &CLR_RD_REQ { + &self.clr_rd_req + } #[doc = "0x54 - DesignWare I2C Clear TX Abort"] - pub clr_tx_abrt: CLR_TX_ABRT, + #[inline(always)] + pub const fn clr_tx_abrt(&self) -> &CLR_TX_ABRT { + &self.clr_tx_abrt + } #[doc = "0x58 - DesignWare I2C Clear RX Done"] - pub clr_rx_done: CLR_RX_DONE, + #[inline(always)] + pub const fn clr_rx_done(&self) -> &CLR_RX_DONE { + &self.clr_rx_done + } #[doc = "0x5c - DesignWare I2C Clear Activity"] - pub clr_activity: CLR_ACTIVITY, + #[inline(always)] + pub const fn clr_activity(&self) -> &CLR_ACTIVITY { + &self.clr_activity + } #[doc = "0x60 - DesignWare I2C Clear Stop DET"] - pub clr_stop_det: CLR_STOP_DET, + #[inline(always)] + pub const fn clr_stop_det(&self) -> &CLR_STOP_DET { + &self.clr_stop_det + } #[doc = "0x64 - DesignWare I2C Clear Start DET"] - pub clr_start_det: CLR_START_DET, + #[inline(always)] + pub const fn clr_start_det(&self) -> &CLR_START_DET { + &self.clr_start_det + } #[doc = "0x68 - DesignWare I2C Clear General Call"] - pub clr_gen_call: CLR_GEN_CALL, + #[inline(always)] + pub const fn clr_gen_call(&self) -> &CLR_GEN_CALL { + &self.clr_gen_call + } #[doc = "0x6c - DesignWare I2C Enable"] - pub enable: ENABLE, + #[inline(always)] + pub const fn enable(&self) -> &ENABLE { + &self.enable + } #[doc = "0x70 - DesignWare I2C Status"] - pub status: STATUS, + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } #[doc = "0x74 - DesignWare I2C TX Failure"] - pub txflr: TXFLR, + #[inline(always)] + pub const fn txflr(&self) -> &TXFLR { + &self.txflr + } #[doc = "0x78 - DesignWare I2C RX Failure"] - pub rxflr: RXFLR, + #[inline(always)] + pub const fn rxflr(&self) -> &RXFLR { + &self.rxflr + } #[doc = "0x7c - DesignWare I2C SDA Hold"] - pub sda_hold: SDA_HOLD, + #[inline(always)] + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold + } #[doc = "0x80 - DesignWare I2C TX Abort Source"] - pub tx_abrt_source: TX_ABRT_SOURCE, - _reserved32: [u8; 0x18], + #[inline(always)] + pub const fn tx_abrt_source(&self) -> &TX_ABRT_SOURCE { + &self.tx_abrt_source + } #[doc = "0x9c - DesignWare I2C Enable Status"] - pub enable_status: ENABLE_STATUS, - _reserved33: [u8; 0x08], + #[inline(always)] + pub const fn enable_status(&self) -> &ENABLE_STATUS { + &self.enable_status + } #[doc = "0xa8 - DesignWare I2C Clear Restart DET"] - pub clr_restart_det: CLR_RESTART_DET, - _reserved34: [u8; 0x48], + #[inline(always)] + pub const fn clr_restart_det(&self) -> &CLR_RESTART_DET { + &self.clr_restart_det + } #[doc = "0xf4 - DesignWare I2C Compatibility Parameter 1"] - pub comp_param_1: COMP_PARAM_1, + #[inline(always)] + pub const fn comp_param_1(&self) -> &COMP_PARAM_1 { + &self.comp_param_1 + } #[doc = "0xf8 - DesignWare I2C Compatibility Version"] - pub comp_version: COMP_VERSION, + #[inline(always)] + pub const fn comp_version(&self) -> &COMP_VERSION { + &self.comp_version + } #[doc = "0xfc - DesignWare I2C Compatibility Type"] - pub comp_type: COMP_TYPE, + #[inline(always)] + pub const fn comp_type(&self) -> &COMP_TYPE { + &self.comp_type + } } -#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`con`] +#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@con`] module"] pub type CON = crate::Reg; #[doc = "DesignWare I2C CON"] pub mod con; -#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tar`] +#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar`] module"] pub type TAR = crate::Reg; #[doc = "DesignWare I2C TAR"] pub mod tar; -#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sar`] +#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`] module"] pub type SAR = crate::Reg; #[doc = "DesignWare I2C SAR"] pub mod sar; -#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`data_cmd`] +#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_cmd`] module"] pub type DATA_CMD = crate::Reg; #[doc = "DesignWare I2C Data Command"] pub mod data_cmd; -#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_hcnt`] +#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_hcnt`] module"] pub type SS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL HCNT"] pub mod ss_scl_hcnt; -#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_lcnt`] +#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_lcnt`] module"] pub type SS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL LCNT"] pub mod ss_scl_lcnt; -#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_hcnt`] +#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_hcnt`] module"] pub type FS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL HCNT"] pub mod fs_scl_hcnt; -#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_lcnt`] +#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_lcnt`] module"] pub type FS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL LCNT"] pub mod fs_scl_lcnt; -#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_hcnt`] +#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_hcnt`] module"] pub type HS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL HCNT"] pub mod hs_scl_hcnt; -#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_lcnt`] +#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_lcnt`] module"] pub type HS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL LCNT"] pub mod hs_scl_lcnt; -#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_stat`] +#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"] pub type INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Interrupt Status"] pub mod intr_stat; -#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_mask`] +#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mask`] module"] pub type INTR_MASK = crate::Reg; #[doc = "DesignWare I2C Interrupt Mask"] pub mod intr_mask; -#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`raw_intr_stat`] +#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"] pub type RAW_INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Raw Interrupt Status"] pub mod raw_intr_stat; -#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rx_tl`] +#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tl`] module"] pub type RX_TL = crate::Reg; #[doc = "DesignWare I2C RX TL"] pub mod rx_tl; -#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_tl`] +#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_tl`] module"] pub type TX_TL = crate::Reg; #[doc = "DesignWare I2C TX TL"] pub mod tx_tl; -#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_intr`] +#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_intr`] module"] pub type CLR_INTR = crate::Reg; #[doc = "DesignWare I2C Clear Interrrupt"] pub mod clr_intr; -#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_under`] +#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_under`] module"] pub type CLR_RX_UNDER = crate::Reg; #[doc = "DesignWare I2C Clear RX Underrun"] pub mod clr_rx_under; -#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_over`] +#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_over`] module"] pub type CLR_RX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear RX Overrun"] pub mod clr_rx_over; -#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_over`] +#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_over`] module"] pub type CLR_TX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear TX Overrun"] pub mod clr_tx_over; -#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rd_req`] +#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rd_req`] module"] pub type CLR_RD_REQ = crate::Reg; #[doc = "DesignWare I2C Clear Read Request"] pub mod clr_rd_req; -#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_abrt`] +#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_abrt`] module"] pub type CLR_TX_ABRT = crate::Reg; #[doc = "DesignWare I2C Clear TX Abort"] pub mod clr_tx_abrt; -#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_done`] +#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_done`] module"] pub type CLR_RX_DONE = crate::Reg; #[doc = "DesignWare I2C Clear RX Done"] pub mod clr_rx_done; -#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_activity`] +#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_activity`] module"] pub type CLR_ACTIVITY = crate::Reg; #[doc = "DesignWare I2C Clear Activity"] pub mod clr_activity; -#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_stop_det`] +#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_stop_det`] module"] pub type CLR_STOP_DET = crate::Reg; #[doc = "DesignWare I2C Clear Stop DET"] pub mod clr_stop_det; -#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_start_det`] +#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_start_det`] module"] pub type CLR_START_DET = crate::Reg; #[doc = "DesignWare I2C Clear Start DET"] pub mod clr_start_det; -#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_gen_call`] +#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_gen_call`] module"] pub type CLR_GEN_CALL = crate::Reg; #[doc = "DesignWare I2C Clear General Call"] pub mod clr_gen_call; -#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable`] +#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] pub type ENABLE = crate::Reg; #[doc = "DesignWare I2C Enable"] pub mod enable; -#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`status`] +#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] pub type STATUS = crate::Reg; #[doc = "DesignWare I2C Status"] pub mod status; -#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txflr`] +#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txflr`] module"] pub type TXFLR = crate::Reg; #[doc = "DesignWare I2C TX Failure"] pub mod txflr; -#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxflr`] +#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxflr`] module"] pub type RXFLR = crate::Reg; #[doc = "DesignWare I2C RX Failure"] pub mod rxflr; -#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sda_hold`] +#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] pub type SDA_HOLD = crate::Reg; #[doc = "DesignWare I2C SDA Hold"] pub mod sda_hold; -#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_abrt_source`] +#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_abrt_source`] module"] pub type TX_ABRT_SOURCE = crate::Reg; #[doc = "DesignWare I2C TX Abort Source"] pub mod tx_abrt_source; -#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_status`] +#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_status`] module"] pub type ENABLE_STATUS = crate::Reg; #[doc = "DesignWare I2C Enable Status"] pub mod enable_status; -#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_restart_det`] +#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_restart_det`] module"] pub type CLR_RESTART_DET = crate::Reg; #[doc = "DesignWare I2C Clear Restart DET"] pub mod clr_restart_det; -#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_param_1`] +#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_param_1`] module"] pub type COMP_PARAM_1 = crate::Reg; #[doc = "DesignWare I2C Compatibility Parameter 1"] pub mod comp_param_1; -#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_version`] +#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_version`] module"] pub type COMP_VERSION = crate::Reg; #[doc = "DesignWare I2C Compatibility Version"] pub mod comp_version; -#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_type`] +#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_type`] module"] pub type COMP_TYPE = crate::Reg; #[doc = "DesignWare I2C Compatibility Type"] diff --git a/jh7110-vf2-12a-pac/src/i2c3/clr_activity.rs b/jh7110-vf2-12a-pac/src/i2c3/clr_activity.rs index d26bb80..1ee2297 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/clr_activity.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/clr_activity.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_activity` reader - clr_activity"] pub type CLR_ACTIVITY_R = crate::FieldReader; #[doc = "Field `clr_activity` writer - clr_activity"] -pub type CLR_ACTIVITY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_ACTIVITY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] #[must_use] - pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { - CLR_ACTIVITY_W::new(self) + pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { + CLR_ACTIVITY_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/clr_gen_call.rs b/jh7110-vf2-12a-pac/src/i2c3/clr_gen_call.rs index a9ea5af..4a7c5ba 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/clr_gen_call.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/clr_gen_call.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_gen_call` reader - clr_gen_call"] pub type CLR_GEN_CALL_R = crate::FieldReader; #[doc = "Field `clr_gen_call` writer - clr_gen_call"] -pub type CLR_GEN_CALL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_GEN_CALL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] #[must_use] - pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { - CLR_GEN_CALL_W::new(self) + pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { + CLR_GEN_CALL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/clr_intr.rs b/jh7110-vf2-12a-pac/src/i2c3/clr_intr.rs index a7daf57..cf57b09 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/clr_intr.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/clr_intr.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/clr_rd_req.rs b/jh7110-vf2-12a-pac/src/i2c3/clr_rd_req.rs index e275da1..4beae9d 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/clr_rd_req.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/clr_rd_req.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rd_req` reader - clr_rd_req"] pub type CLR_RD_REQ_R = crate::FieldReader; #[doc = "Field `clr_rd_req` writer - clr_rd_req"] -pub type CLR_RD_REQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RD_REQ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] #[must_use] - pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { - CLR_RD_REQ_W::new(self) + pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { + CLR_RD_REQ_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/clr_restart_det.rs b/jh7110-vf2-12a-pac/src/i2c3/clr_restart_det.rs index 5be7f5d..88d193c 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/clr_restart_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/clr_restart_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_restart_det` reader - clr_restart_det"] pub type CLR_RESTART_DET_R = crate::FieldReader; #[doc = "Field `clr_restart_det` writer - clr_restart_det"] -pub type CLR_RESTART_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RESTART_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] #[must_use] - pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { - CLR_RESTART_DET_W::new(self) + pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { + CLR_RESTART_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/clr_rx_done.rs b/jh7110-vf2-12a-pac/src/i2c3/clr_rx_done.rs index 02d83c5..7e14a3f 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/clr_rx_done.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/clr_rx_done.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_done` reader - clr_rx_done"] pub type CLR_RX_DONE_R = crate::FieldReader; #[doc = "Field `clr_rx_done` writer - clr_rx_done"] -pub type CLR_RX_DONE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_DONE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] #[must_use] - pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { - CLR_RX_DONE_W::new(self) + pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { + CLR_RX_DONE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/clr_rx_over.rs b/jh7110-vf2-12a-pac/src/i2c3/clr_rx_over.rs index 6d7ff4e..2302921 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/clr_rx_over.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/clr_rx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_over` reader - clr_rx_over"] pub type CLR_RX_OVER_R = crate::FieldReader; #[doc = "Field `clr_rx_over` writer - clr_rx_over"] -pub type CLR_RX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] #[must_use] - pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { - CLR_RX_OVER_W::new(self) + pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { + CLR_RX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/clr_rx_under.rs b/jh7110-vf2-12a-pac/src/i2c3/clr_rx_under.rs index 4a24f7c..35e15bd 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/clr_rx_under.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/clr_rx_under.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_under` reader - clr_rx_under"] pub type CLR_RX_UNDER_R = crate::FieldReader; #[doc = "Field `clr_rx_under` writer - clr_rx_under"] -pub type CLR_RX_UNDER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_UNDER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] #[must_use] - pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { - CLR_RX_UNDER_W::new(self) + pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { + CLR_RX_UNDER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/clr_start_det.rs b/jh7110-vf2-12a-pac/src/i2c3/clr_start_det.rs index cebc4bc..2314f65 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/clr_start_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/clr_start_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_start_det` reader - clr_start_det"] pub type CLR_START_DET_R = crate::FieldReader; #[doc = "Field `clr_start_det` writer - clr_start_det"] -pub type CLR_START_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_START_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] #[must_use] - pub fn clr_start_det(&mut self) -> CLR_START_DET_W { - CLR_START_DET_W::new(self) + pub fn clr_start_det(&mut self) -> CLR_START_DET_W { + CLR_START_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/clr_stop_det.rs b/jh7110-vf2-12a-pac/src/i2c3/clr_stop_det.rs index 44f39f3..49abcac 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/clr_stop_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/clr_stop_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_stop_det` reader - clr_stop_det"] pub type CLR_STOP_DET_R = crate::FieldReader; #[doc = "Field `clr_stop_det` writer - clr_stop_det"] -pub type CLR_STOP_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_STOP_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] #[must_use] - pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { - CLR_STOP_DET_W::new(self) + pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { + CLR_STOP_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/clr_tx_abrt.rs b/jh7110-vf2-12a-pac/src/i2c3/clr_tx_abrt.rs index 6ac441c..3bc0f6f 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/clr_tx_abrt.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/clr_tx_abrt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_abrt` reader - clr_tx_abrt"] pub type CLR_TX_ABRT_R = crate::FieldReader; #[doc = "Field `clr_tx_abrt` writer - clr_tx_abrt"] -pub type CLR_TX_ABRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_ABRT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] #[must_use] - pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { - CLR_TX_ABRT_W::new(self) + pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { + CLR_TX_ABRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/clr_tx_over.rs b/jh7110-vf2-12a-pac/src/i2c3/clr_tx_over.rs index 2b32b52..a5b6933 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/clr_tx_over.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/clr_tx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_over` reader - clr_tx_over"] pub type CLR_TX_OVER_R = crate::FieldReader; #[doc = "Field `clr_tx_over` writer - clr_tx_over"] -pub type CLR_TX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] #[must_use] - pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { - CLR_TX_OVER_W::new(self) + pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { + CLR_TX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/comp_param_1.rs b/jh7110-vf2-12a-pac/src/i2c3/comp_param_1.rs index 24a22e1..95c5002 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/comp_param_1.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/comp_param_1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/comp_type.rs b/jh7110-vf2-12a-pac/src/i2c3/comp_type.rs index ac916b5..1336c43 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/comp_type.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/comp_type.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/comp_version.rs b/jh7110-vf2-12a-pac/src/i2c3/comp_version.rs index 4be31fa..e8309c8 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/comp_version.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/comp_version.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/con.rs b/jh7110-vf2-12a-pac/src/i2c3/con.rs index 873c534..28aa865 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/con.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/con.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `master` reader - I2C Master Connection - 0: Slave, 1: Master"] pub type MASTER_R = crate::BitReader; #[doc = "Field `master` writer - I2C Master Connection - 0: Slave, 1: Master"] -pub type MASTER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `speed` reader - I2C Speed - 01: Standard, 10: Fast, 11: High"] pub type SPEED_R = crate::FieldReader; #[doc = "Field `speed` writer - I2C Speed - 01: Standard, 10: Fast, 11: High"] -pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `slave_10bitaddr` reader - I2C Slave 10-bit Address - 0: False, 1: True"] pub type SLAVE_10BITADDR_R = crate::BitReader; #[doc = "Field `slave_10bitaddr` writer - I2C Slave 10-bit Address - 0: False, 1: True"] -pub type SLAVE_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_10bitaddr` reader - I2C Master 10-bit Address - 0: False, 1: True"] pub type MASTER_10BITADDR_R = crate::BitReader; #[doc = "Field `master_10bitaddr` writer - I2C Master 10-bit Address - 0: False, 1: True"] -pub type MASTER_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_en` reader - I2C Restart Enable - 0: False, 1: True"] pub type RESTART_EN_R = crate::BitReader; #[doc = "Field `restart_en` writer - I2C Restart Enable - 0: False, 1: True"] -pub type RESTART_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_disable` reader - I2C Slave Disable - 0: False, 1: True"] pub type SLAVE_DISABLE_R = crate::BitReader; #[doc = "Field `slave_disable` writer - I2C Slave Disable - 0: False, 1: True"] -pub type SLAVE_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det_ifaddressed` reader - I2C Stop DET If Addressed - 0: False, 1: True"] pub type STOP_DET_IFADDRESSED_R = crate::BitReader; #[doc = "Field `stop_det_ifaddressed` writer - I2C Stop DET If Addressed - 0: False, 1: True"] -pub type STOP_DET_IFADDRESSED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty_ctrl` reader - I2C TX Empty Control - 0: False, 1: True"] pub type TX_EMPTY_CTRL_R = crate::BitReader; #[doc = "Field `tx_empty_ctrl` writer - I2C TX Empty Control - 0: False, 1: True"] -pub type TX_EMPTY_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_fifo_full_hld_ctrl` reader - I2C RX FIFO Full Hold Control - 0: False, 1: True"] pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; #[doc = "Field `rx_fifo_full_hld_ctrl` writer - I2C RX FIFO Full Hold Control - 0: False, 1: True"] -pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bus_clear_ctrl` reader - I2C Bus Clear Control - 0: False, 1: True"] pub type BUS_CLEAR_CTRL_R = crate::BitReader; #[doc = "Field `bus_clear_ctrl` writer - I2C Bus Clear Control - 0: False, 1: True"] -pub type BUS_CLEAR_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BUS_CLEAR_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] #[must_use] - pub fn master(&mut self) -> MASTER_W { - MASTER_W::new(self) + pub fn master(&mut self) -> MASTER_W { + MASTER_W::new(self, 0) } #[doc = "Bits 1:2 - I2C Speed - 01: Standard, 10: Fast, 11: High"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W { - SPEED_W::new(self) + pub fn speed(&mut self) -> SPEED_W { + SPEED_W::new(self, 1) } #[doc = "Bit 3 - I2C Slave 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { - SLAVE_10BITADDR_W::new(self) + pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { + SLAVE_10BITADDR_W::new(self, 3) } #[doc = "Bit 4 - I2C Master 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { - MASTER_10BITADDR_W::new(self) + pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { + MASTER_10BITADDR_W::new(self, 4) } #[doc = "Bit 5 - I2C Restart Enable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn restart_en(&mut self) -> RESTART_EN_W { - RESTART_EN_W::new(self) + pub fn restart_en(&mut self) -> RESTART_EN_W { + RESTART_EN_W::new(self, 5) } #[doc = "Bit 6 - I2C Slave Disable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { - SLAVE_DISABLE_W::new(self) + pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { + SLAVE_DISABLE_W::new(self, 6) } #[doc = "Bit 7 - I2C Stop DET If Addressed - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { - STOP_DET_IFADDRESSED_W::new(self) + pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { + STOP_DET_IFADDRESSED_W::new(self, 7) } #[doc = "Bit 8 - I2C TX Empty Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { - TX_EMPTY_CTRL_W::new(self) + pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { + TX_EMPTY_CTRL_W::new(self, 8) } #[doc = "Bit 9 - I2C RX FIFO Full Hold Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { - RX_FIFO_FULL_HLD_CTRL_W::new(self) + pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { + RX_FIFO_FULL_HLD_CTRL_W::new(self, 9) } #[doc = "Bit 11 - I2C Bus Clear Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { - BUS_CLEAR_CTRL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { + BUS_CLEAR_CTRL_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/data_cmd.rs b/jh7110-vf2-12a-pac/src/i2c3/data_cmd.rs index cf36408..2b320d4 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/data_cmd.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/data_cmd.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `dat` reader - Data Command Data Byte"] pub type DAT_R = crate::FieldReader; #[doc = "Field `dat` writer - Data Command Data Byte"] -pub type DAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `read` reader - Data Command READ Bit - 0: Write, 1: Read"] pub type READ_R = crate::BitReader; #[doc = "Field `read` writer - Data Command READ Bit - 0: Write, 1: Read"] -pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop` reader - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart` reader - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] pub type RESTART_R = crate::BitReader; #[doc = "Field `restart` writer - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] -pub type RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `first_data_byte` reader - Data Command First Data Byte - 0: False, 1: True"] pub type FIRST_DATA_BYTE_R = crate::BitReader; #[doc = "Field `first_data_byte` writer - Data Command First Data Byte - 0: False, 1: True"] -pub type FIRST_DATA_BYTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIRST_DATA_BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] #[must_use] - pub fn dat(&mut self) -> DAT_W { - DAT_W::new(self) + pub fn dat(&mut self) -> DAT_W { + DAT_W::new(self, 0) } #[doc = "Bit 8 - Data Command READ Bit - 0: Write, 1: Read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W { - READ_W::new(self) + pub fn read(&mut self) -> READ_W { + READ_W::new(self, 8) } #[doc = "Bit 9 - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 9) } #[doc = "Bit 10 - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] #[inline(always)] #[must_use] - pub fn restart(&mut self) -> RESTART_W { - RESTART_W::new(self) + pub fn restart(&mut self) -> RESTART_W { + RESTART_W::new(self, 10) } #[doc = "Bit 11 - Data Command First Data Byte - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { - FIRST_DATA_BYTE_W::new(self) + pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { + FIRST_DATA_BYTE_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/enable.rs b/jh7110-vf2-12a-pac/src/i2c3/enable.rs index c5ca9d7..3629f6b 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/enable.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/enable.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `abort` reader - abort"] pub type ABORT_R = crate::BitReader; #[doc = "Field `abort` writer - abort"] -pub type ABORT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 1 - abort"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 1 - abort"] #[inline(always)] #[must_use] - pub fn abort(&mut self) -> ABORT_W { - ABORT_W::new(self) + pub fn abort(&mut self) -> ABORT_W { + ABORT_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/enable_status.rs b/jh7110-vf2-12a-pac/src/i2c3/enable_status.rs index 2c102a6..8b9b7d3 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/enable_status.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/enable_status.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `activity` reader - activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tfe` reader - tfe"] pub type TFE_R = crate::BitReader; #[doc = "Field `tfe` writer - tfe"] -pub type TFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TFE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfne` reader - rfne"] pub type RFNE_R = crate::BitReader; #[doc = "Field `rfne` writer - rfne"] -pub type RFNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFNE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_activity` reader - master_activity"] pub type MASTER_ACTIVITY_R = crate::BitReader; #[doc = "Field `master_activity` writer - master_activity"] -pub type MASTER_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_activity` reader - slave_activity"] pub type SLAVE_ACTIVITY_R = crate::BitReader; #[doc = "Field `slave_activity` writer - slave_activity"] -pub type SLAVE_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - activity"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 0) } #[doc = "Bit 2 - tfe"] #[inline(always)] #[must_use] - pub fn tfe(&mut self) -> TFE_W { - TFE_W::new(self) + pub fn tfe(&mut self) -> TFE_W { + TFE_W::new(self, 2) } #[doc = "Bit 3 - rfne"] #[inline(always)] #[must_use] - pub fn rfne(&mut self) -> RFNE_W { - RFNE_W::new(self) + pub fn rfne(&mut self) -> RFNE_W { + RFNE_W::new(self, 3) } #[doc = "Bit 5 - master_activity"] #[inline(always)] #[must_use] - pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { - MASTER_ACTIVITY_W::new(self) + pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { + MASTER_ACTIVITY_W::new(self, 5) } #[doc = "Bit 6 - slave_activity"] #[inline(always)] #[must_use] - pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { - SLAVE_ACTIVITY_W::new(self) + pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { + SLAVE_ACTIVITY_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/fs_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c3/fs_scl_hcnt.rs index 9a9fd72..8a4f6d1 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/fs_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/fs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_hcnt` reader - fs_scl_hcnt"] pub type FS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_hcnt` writer - fs_scl_hcnt"] -pub type FS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { - FS_SCL_HCNT_W::new(self) + pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { + FS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/fs_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c3/fs_scl_lcnt.rs index 5e41cd1..4b4dd6b 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/fs_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/fs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_lcnt` reader - fs_scl_lcnt"] pub type FS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_lcnt` writer - fs_scl_lcnt"] -pub type FS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { - FS_SCL_LCNT_W::new(self) + pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { + FS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/hs_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c3/hs_scl_hcnt.rs index fba7f13..9b0a71c 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/hs_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/hs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_hcnt` reader - hs_scl_hcnt"] pub type HS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_hcnt` writer - hs_scl_hcnt"] -pub type HS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { - HS_SCL_HCNT_W::new(self) + pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { + HS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/hs_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c3/hs_scl_lcnt.rs index 9fca7a5..a715282 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/hs_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/hs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_lcnt` reader - hs_scl_lcnt"] pub type HS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_lcnt` writer - hs_scl_lcnt"] -pub type HS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { - HS_SCL_LCNT_W::new(self) + pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { + HS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/intr_mask.rs b/jh7110-vf2-12a-pac/src/i2c3/intr_mask.rs index 20a334f..769b629 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/intr_mask.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/intr_mask.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/intr_stat.rs b/jh7110-vf2-12a-pac/src/i2c3/intr_stat.rs index 2c2ba34..f376c26 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/intr_stat.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/raw_intr_stat.rs b/jh7110-vf2-12a-pac/src/i2c3/raw_intr_stat.rs index af97981..dd5e8e0 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/raw_intr_stat.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/raw_intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/rx_tl.rs b/jh7110-vf2-12a-pac/src/i2c3/rx_tl.rs index 1455a10..f3f39f4 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/rx_tl.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/rx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rx_tl` reader - rx_tl"] pub type RX_TL_R = crate::FieldReader; #[doc = "Field `rx_tl` writer - rx_tl"] -pub type RX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] #[must_use] - pub fn rx_tl(&mut self) -> RX_TL_W { - RX_TL_W::new(self) + pub fn rx_tl(&mut self) -> RX_TL_W { + RX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/rxflr.rs b/jh7110-vf2-12a-pac/src/i2c3/rxflr.rs index 910e254..4dccf5e 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/rxflr.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/rxflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rxflr` reader - rxflr"] pub type RXFLR_R = crate::FieldReader; #[doc = "Field `rxflr` writer - rxflr"] -pub type RXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] #[must_use] - pub fn rxflr(&mut self) -> RXFLR_W { - RXFLR_W::new(self) + pub fn rxflr(&mut self) -> RXFLR_W { + RXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/sar.rs b/jh7110-vf2-12a-pac/src/i2c3/sar.rs index d272e7a..1af6273 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/sar.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/sar.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Slave address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Slave address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Slave address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Slave address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; impl R { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Slave address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/sda_hold.rs b/jh7110-vf2-12a-pac/src/i2c3/sda_hold.rs index 82ceac5..d5d7512 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/sda_hold.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/sda_hold.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sda_hold` reader - sda_hold"] pub type SDA_HOLD_R = crate::FieldReader; #[doc = "Field `sda_hold` writer - sda_hold"] -pub type SDA_HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SDA_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] #[must_use] - pub fn sda_hold(&mut self) -> SDA_HOLD_W { - SDA_HOLD_W::new(self) + pub fn sda_hold(&mut self) -> SDA_HOLD_W { + SDA_HOLD_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/ss_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c3/ss_scl_hcnt.rs index 33736c7..77d7ea0 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/ss_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/ss_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_hcnt` reader - ss_scl_hcnt"] pub type SS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_hcnt` writer - ss_scl_hcnt"] -pub type SS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { - SS_SCL_HCNT_W::new(self) + pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { + SS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/ss_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c3/ss_scl_lcnt.rs index ce22b5d..8208747 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/ss_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/ss_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_lcnt` reader - ss_scl_lcnt"] pub type SS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_lcnt` writer - ss_scl_lcnt"] -pub type SS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { - SS_SCL_LCNT_W::new(self) + pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { + SS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/status.rs b/jh7110-vf2-12a-pac/src/i2c3/status.rs index 9489e49..1b7ab67 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/status.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/tar.rs b/jh7110-vf2-12a-pac/src/i2c3/tar.rs index 9fedc71..3044a8c 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/tar.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/tar.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Target address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Target address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Target address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Target address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; #[doc = "Field `mode` reader - Target addressing mode - 0: 7-bit, 1: 10-bit"] pub type MODE_R = crate::BitReader; #[doc = "Field `mode` writer - Target addressing mode - 0: 7-bit, 1: 10-bit"] -pub type MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Target address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } #[doc = "Bit 12 - Target addressing mode - 0: 7-bit, 1: 10-bit"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W { - MODE_W::new(self) + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 12) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/tx_abrt_source.rs b/jh7110-vf2-12a-pac/src/i2c3/tx_abrt_source.rs index 6f31813..c4fdf1a 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/tx_abrt_source.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/tx_abrt_source.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/tx_tl.rs b/jh7110-vf2-12a-pac/src/i2c3/tx_tl.rs index 84a1734..b0e6c64 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/tx_tl.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/tx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `tx_tl` reader - tx_tl"] pub type TX_TL_R = crate::FieldReader; #[doc = "Field `tx_tl` writer - tx_tl"] -pub type TX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] #[must_use] - pub fn tx_tl(&mut self) -> TX_TL_W { - TX_TL_W::new(self) + pub fn tx_tl(&mut self) -> TX_TL_W { + TX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c3/txflr.rs b/jh7110-vf2-12a-pac/src/i2c3/txflr.rs index b8e5fdd..5ca351d 100644 --- a/jh7110-vf2-12a-pac/src/i2c3/txflr.rs +++ b/jh7110-vf2-12a-pac/src/i2c3/txflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `txflr` reader - txflr"] pub type TXFLR_R = crate::FieldReader; #[doc = "Field `txflr` writer - txflr"] -pub type TXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - txflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - txflr"] #[inline(always)] #[must_use] - pub fn txflr(&mut self) -> TXFLR_W { - TXFLR_W::new(self) + pub fn txflr(&mut self) -> TXFLR_W { + TXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4.rs b/jh7110-vf2-12a-pac/src/i2c4.rs index d0fe76a..fdffe28 100644 --- a/jh7110-vf2-12a-pac/src/i2c4.rs +++ b/jh7110-vf2-12a-pac/src/i2c4.rs @@ -1,266 +1,416 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + con: CON, + tar: TAR, + sar: SAR, + _reserved3: [u8; 0x04], + data_cmd: DATA_CMD, + ss_scl_hcnt: SS_SCL_HCNT, + ss_scl_lcnt: SS_SCL_LCNT, + fs_scl_hcnt: FS_SCL_HCNT, + fs_scl_lcnt: FS_SCL_LCNT, + hs_scl_hcnt: HS_SCL_HCNT, + hs_scl_lcnt: HS_SCL_LCNT, + intr_stat: INTR_STAT, + intr_mask: INTR_MASK, + raw_intr_stat: RAW_INTR_STAT, + rx_tl: RX_TL, + tx_tl: TX_TL, + clr_intr: CLR_INTR, + clr_rx_under: CLR_RX_UNDER, + clr_rx_over: CLR_RX_OVER, + clr_tx_over: CLR_TX_OVER, + clr_rd_req: CLR_RD_REQ, + clr_tx_abrt: CLR_TX_ABRT, + clr_rx_done: CLR_RX_DONE, + clr_activity: CLR_ACTIVITY, + clr_stop_det: CLR_STOP_DET, + clr_start_det: CLR_START_DET, + clr_gen_call: CLR_GEN_CALL, + enable: ENABLE, + status: STATUS, + txflr: TXFLR, + rxflr: RXFLR, + sda_hold: SDA_HOLD, + tx_abrt_source: TX_ABRT_SOURCE, + _reserved32: [u8; 0x18], + enable_status: ENABLE_STATUS, + _reserved33: [u8; 0x08], + clr_restart_det: CLR_RESTART_DET, + _reserved34: [u8; 0x48], + comp_param_1: COMP_PARAM_1, + comp_version: COMP_VERSION, + comp_type: COMP_TYPE, +} +impl RegisterBlock { #[doc = "0x00 - DesignWare I2C CON"] - pub con: CON, + #[inline(always)] + pub const fn con(&self) -> &CON { + &self.con + } #[doc = "0x04 - DesignWare I2C TAR"] - pub tar: TAR, + #[inline(always)] + pub const fn tar(&self) -> &TAR { + &self.tar + } #[doc = "0x08 - DesignWare I2C SAR"] - pub sar: SAR, - _reserved3: [u8; 0x04], + #[inline(always)] + pub const fn sar(&self) -> &SAR { + &self.sar + } #[doc = "0x10 - DesignWare I2C Data Command"] - pub data_cmd: DATA_CMD, + #[inline(always)] + pub const fn data_cmd(&self) -> &DATA_CMD { + &self.data_cmd + } #[doc = "0x14 - DesignWare I2C SS SCL HCNT"] - pub ss_scl_hcnt: SS_SCL_HCNT, + #[inline(always)] + pub const fn ss_scl_hcnt(&self) -> &SS_SCL_HCNT { + &self.ss_scl_hcnt + } #[doc = "0x18 - DesignWare I2C SS SCL LCNT"] - pub ss_scl_lcnt: SS_SCL_LCNT, + #[inline(always)] + pub const fn ss_scl_lcnt(&self) -> &SS_SCL_LCNT { + &self.ss_scl_lcnt + } #[doc = "0x1c - DesignWare I2C FS SCL HCNT"] - pub fs_scl_hcnt: FS_SCL_HCNT, + #[inline(always)] + pub const fn fs_scl_hcnt(&self) -> &FS_SCL_HCNT { + &self.fs_scl_hcnt + } #[doc = "0x20 - DesignWare I2C FS SCL LCNT"] - pub fs_scl_lcnt: FS_SCL_LCNT, + #[inline(always)] + pub const fn fs_scl_lcnt(&self) -> &FS_SCL_LCNT { + &self.fs_scl_lcnt + } #[doc = "0x24 - DesignWare I2C HS SCL HCNT"] - pub hs_scl_hcnt: HS_SCL_HCNT, + #[inline(always)] + pub const fn hs_scl_hcnt(&self) -> &HS_SCL_HCNT { + &self.hs_scl_hcnt + } #[doc = "0x28 - DesignWare I2C HS SCL LCNT"] - pub hs_scl_lcnt: HS_SCL_LCNT, + #[inline(always)] + pub const fn hs_scl_lcnt(&self) -> &HS_SCL_LCNT { + &self.hs_scl_lcnt + } #[doc = "0x2c - DesignWare I2C Interrupt Status"] - pub intr_stat: INTR_STAT, + #[inline(always)] + pub const fn intr_stat(&self) -> &INTR_STAT { + &self.intr_stat + } #[doc = "0x30 - DesignWare I2C Interrupt Mask"] - pub intr_mask: INTR_MASK, + #[inline(always)] + pub const fn intr_mask(&self) -> &INTR_MASK { + &self.intr_mask + } #[doc = "0x34 - DesignWare I2C Raw Interrupt Status"] - pub raw_intr_stat: RAW_INTR_STAT, + #[inline(always)] + pub const fn raw_intr_stat(&self) -> &RAW_INTR_STAT { + &self.raw_intr_stat + } #[doc = "0x38 - DesignWare I2C RX TL"] - pub rx_tl: RX_TL, + #[inline(always)] + pub const fn rx_tl(&self) -> &RX_TL { + &self.rx_tl + } #[doc = "0x3c - DesignWare I2C TX TL"] - pub tx_tl: TX_TL, + #[inline(always)] + pub const fn tx_tl(&self) -> &TX_TL { + &self.tx_tl + } #[doc = "0x40 - DesignWare I2C Clear Interrrupt"] - pub clr_intr: CLR_INTR, + #[inline(always)] + pub const fn clr_intr(&self) -> &CLR_INTR { + &self.clr_intr + } #[doc = "0x44 - DesignWare I2C Clear RX Underrun"] - pub clr_rx_under: CLR_RX_UNDER, + #[inline(always)] + pub const fn clr_rx_under(&self) -> &CLR_RX_UNDER { + &self.clr_rx_under + } #[doc = "0x48 - DesignWare I2C Clear RX Overrun"] - pub clr_rx_over: CLR_RX_OVER, + #[inline(always)] + pub const fn clr_rx_over(&self) -> &CLR_RX_OVER { + &self.clr_rx_over + } #[doc = "0x4c - DesignWare I2C Clear TX Overrun"] - pub clr_tx_over: CLR_TX_OVER, + #[inline(always)] + pub const fn clr_tx_over(&self) -> &CLR_TX_OVER { + &self.clr_tx_over + } #[doc = "0x50 - DesignWare I2C Clear Read Request"] - pub clr_rd_req: CLR_RD_REQ, + #[inline(always)] + pub const fn clr_rd_req(&self) -> &CLR_RD_REQ { + &self.clr_rd_req + } #[doc = "0x54 - DesignWare I2C Clear TX Abort"] - pub clr_tx_abrt: CLR_TX_ABRT, + #[inline(always)] + pub const fn clr_tx_abrt(&self) -> &CLR_TX_ABRT { + &self.clr_tx_abrt + } #[doc = "0x58 - DesignWare I2C Clear RX Done"] - pub clr_rx_done: CLR_RX_DONE, + #[inline(always)] + pub const fn clr_rx_done(&self) -> &CLR_RX_DONE { + &self.clr_rx_done + } #[doc = "0x5c - DesignWare I2C Clear Activity"] - pub clr_activity: CLR_ACTIVITY, + #[inline(always)] + pub const fn clr_activity(&self) -> &CLR_ACTIVITY { + &self.clr_activity + } #[doc = "0x60 - DesignWare I2C Clear Stop DET"] - pub clr_stop_det: CLR_STOP_DET, + #[inline(always)] + pub const fn clr_stop_det(&self) -> &CLR_STOP_DET { + &self.clr_stop_det + } #[doc = "0x64 - DesignWare I2C Clear Start DET"] - pub clr_start_det: CLR_START_DET, + #[inline(always)] + pub const fn clr_start_det(&self) -> &CLR_START_DET { + &self.clr_start_det + } #[doc = "0x68 - DesignWare I2C Clear General Call"] - pub clr_gen_call: CLR_GEN_CALL, + #[inline(always)] + pub const fn clr_gen_call(&self) -> &CLR_GEN_CALL { + &self.clr_gen_call + } #[doc = "0x6c - DesignWare I2C Enable"] - pub enable: ENABLE, + #[inline(always)] + pub const fn enable(&self) -> &ENABLE { + &self.enable + } #[doc = "0x70 - DesignWare I2C Status"] - pub status: STATUS, + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } #[doc = "0x74 - DesignWare I2C TX Failure"] - pub txflr: TXFLR, + #[inline(always)] + pub const fn txflr(&self) -> &TXFLR { + &self.txflr + } #[doc = "0x78 - DesignWare I2C RX Failure"] - pub rxflr: RXFLR, + #[inline(always)] + pub const fn rxflr(&self) -> &RXFLR { + &self.rxflr + } #[doc = "0x7c - DesignWare I2C SDA Hold"] - pub sda_hold: SDA_HOLD, + #[inline(always)] + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold + } #[doc = "0x80 - DesignWare I2C TX Abort Source"] - pub tx_abrt_source: TX_ABRT_SOURCE, - _reserved32: [u8; 0x18], + #[inline(always)] + pub const fn tx_abrt_source(&self) -> &TX_ABRT_SOURCE { + &self.tx_abrt_source + } #[doc = "0x9c - DesignWare I2C Enable Status"] - pub enable_status: ENABLE_STATUS, - _reserved33: [u8; 0x08], + #[inline(always)] + pub const fn enable_status(&self) -> &ENABLE_STATUS { + &self.enable_status + } #[doc = "0xa8 - DesignWare I2C Clear Restart DET"] - pub clr_restart_det: CLR_RESTART_DET, - _reserved34: [u8; 0x48], + #[inline(always)] + pub const fn clr_restart_det(&self) -> &CLR_RESTART_DET { + &self.clr_restart_det + } #[doc = "0xf4 - DesignWare I2C Compatibility Parameter 1"] - pub comp_param_1: COMP_PARAM_1, + #[inline(always)] + pub const fn comp_param_1(&self) -> &COMP_PARAM_1 { + &self.comp_param_1 + } #[doc = "0xf8 - DesignWare I2C Compatibility Version"] - pub comp_version: COMP_VERSION, + #[inline(always)] + pub const fn comp_version(&self) -> &COMP_VERSION { + &self.comp_version + } #[doc = "0xfc - DesignWare I2C Compatibility Type"] - pub comp_type: COMP_TYPE, + #[inline(always)] + pub const fn comp_type(&self) -> &COMP_TYPE { + &self.comp_type + } } -#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`con`] +#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@con`] module"] pub type CON = crate::Reg; #[doc = "DesignWare I2C CON"] pub mod con; -#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tar`] +#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar`] module"] pub type TAR = crate::Reg; #[doc = "DesignWare I2C TAR"] pub mod tar; -#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sar`] +#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`] module"] pub type SAR = crate::Reg; #[doc = "DesignWare I2C SAR"] pub mod sar; -#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`data_cmd`] +#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_cmd`] module"] pub type DATA_CMD = crate::Reg; #[doc = "DesignWare I2C Data Command"] pub mod data_cmd; -#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_hcnt`] +#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_hcnt`] module"] pub type SS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL HCNT"] pub mod ss_scl_hcnt; -#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_lcnt`] +#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_lcnt`] module"] pub type SS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL LCNT"] pub mod ss_scl_lcnt; -#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_hcnt`] +#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_hcnt`] module"] pub type FS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL HCNT"] pub mod fs_scl_hcnt; -#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_lcnt`] +#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_lcnt`] module"] pub type FS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL LCNT"] pub mod fs_scl_lcnt; -#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_hcnt`] +#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_hcnt`] module"] pub type HS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL HCNT"] pub mod hs_scl_hcnt; -#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_lcnt`] +#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_lcnt`] module"] pub type HS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL LCNT"] pub mod hs_scl_lcnt; -#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_stat`] +#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"] pub type INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Interrupt Status"] pub mod intr_stat; -#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_mask`] +#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mask`] module"] pub type INTR_MASK = crate::Reg; #[doc = "DesignWare I2C Interrupt Mask"] pub mod intr_mask; -#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`raw_intr_stat`] +#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"] pub type RAW_INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Raw Interrupt Status"] pub mod raw_intr_stat; -#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rx_tl`] +#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tl`] module"] pub type RX_TL = crate::Reg; #[doc = "DesignWare I2C RX TL"] pub mod rx_tl; -#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_tl`] +#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_tl`] module"] pub type TX_TL = crate::Reg; #[doc = "DesignWare I2C TX TL"] pub mod tx_tl; -#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_intr`] +#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_intr`] module"] pub type CLR_INTR = crate::Reg; #[doc = "DesignWare I2C Clear Interrrupt"] pub mod clr_intr; -#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_under`] +#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_under`] module"] pub type CLR_RX_UNDER = crate::Reg; #[doc = "DesignWare I2C Clear RX Underrun"] pub mod clr_rx_under; -#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_over`] +#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_over`] module"] pub type CLR_RX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear RX Overrun"] pub mod clr_rx_over; -#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_over`] +#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_over`] module"] pub type CLR_TX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear TX Overrun"] pub mod clr_tx_over; -#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rd_req`] +#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rd_req`] module"] pub type CLR_RD_REQ = crate::Reg; #[doc = "DesignWare I2C Clear Read Request"] pub mod clr_rd_req; -#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_abrt`] +#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_abrt`] module"] pub type CLR_TX_ABRT = crate::Reg; #[doc = "DesignWare I2C Clear TX Abort"] pub mod clr_tx_abrt; -#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_done`] +#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_done`] module"] pub type CLR_RX_DONE = crate::Reg; #[doc = "DesignWare I2C Clear RX Done"] pub mod clr_rx_done; -#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_activity`] +#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_activity`] module"] pub type CLR_ACTIVITY = crate::Reg; #[doc = "DesignWare I2C Clear Activity"] pub mod clr_activity; -#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_stop_det`] +#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_stop_det`] module"] pub type CLR_STOP_DET = crate::Reg; #[doc = "DesignWare I2C Clear Stop DET"] pub mod clr_stop_det; -#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_start_det`] +#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_start_det`] module"] pub type CLR_START_DET = crate::Reg; #[doc = "DesignWare I2C Clear Start DET"] pub mod clr_start_det; -#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_gen_call`] +#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_gen_call`] module"] pub type CLR_GEN_CALL = crate::Reg; #[doc = "DesignWare I2C Clear General Call"] pub mod clr_gen_call; -#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable`] +#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] pub type ENABLE = crate::Reg; #[doc = "DesignWare I2C Enable"] pub mod enable; -#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`status`] +#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] pub type STATUS = crate::Reg; #[doc = "DesignWare I2C Status"] pub mod status; -#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txflr`] +#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txflr`] module"] pub type TXFLR = crate::Reg; #[doc = "DesignWare I2C TX Failure"] pub mod txflr; -#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxflr`] +#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxflr`] module"] pub type RXFLR = crate::Reg; #[doc = "DesignWare I2C RX Failure"] pub mod rxflr; -#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sda_hold`] +#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] pub type SDA_HOLD = crate::Reg; #[doc = "DesignWare I2C SDA Hold"] pub mod sda_hold; -#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_abrt_source`] +#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_abrt_source`] module"] pub type TX_ABRT_SOURCE = crate::Reg; #[doc = "DesignWare I2C TX Abort Source"] pub mod tx_abrt_source; -#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_status`] +#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_status`] module"] pub type ENABLE_STATUS = crate::Reg; #[doc = "DesignWare I2C Enable Status"] pub mod enable_status; -#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_restart_det`] +#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_restart_det`] module"] pub type CLR_RESTART_DET = crate::Reg; #[doc = "DesignWare I2C Clear Restart DET"] pub mod clr_restart_det; -#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_param_1`] +#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_param_1`] module"] pub type COMP_PARAM_1 = crate::Reg; #[doc = "DesignWare I2C Compatibility Parameter 1"] pub mod comp_param_1; -#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_version`] +#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_version`] module"] pub type COMP_VERSION = crate::Reg; #[doc = "DesignWare I2C Compatibility Version"] pub mod comp_version; -#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_type`] +#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_type`] module"] pub type COMP_TYPE = crate::Reg; #[doc = "DesignWare I2C Compatibility Type"] diff --git a/jh7110-vf2-12a-pac/src/i2c4/clr_activity.rs b/jh7110-vf2-12a-pac/src/i2c4/clr_activity.rs index d26bb80..1ee2297 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/clr_activity.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/clr_activity.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_activity` reader - clr_activity"] pub type CLR_ACTIVITY_R = crate::FieldReader; #[doc = "Field `clr_activity` writer - clr_activity"] -pub type CLR_ACTIVITY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_ACTIVITY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] #[must_use] - pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { - CLR_ACTIVITY_W::new(self) + pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { + CLR_ACTIVITY_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/clr_gen_call.rs b/jh7110-vf2-12a-pac/src/i2c4/clr_gen_call.rs index a9ea5af..4a7c5ba 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/clr_gen_call.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/clr_gen_call.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_gen_call` reader - clr_gen_call"] pub type CLR_GEN_CALL_R = crate::FieldReader; #[doc = "Field `clr_gen_call` writer - clr_gen_call"] -pub type CLR_GEN_CALL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_GEN_CALL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] #[must_use] - pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { - CLR_GEN_CALL_W::new(self) + pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { + CLR_GEN_CALL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/clr_intr.rs b/jh7110-vf2-12a-pac/src/i2c4/clr_intr.rs index a7daf57..cf57b09 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/clr_intr.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/clr_intr.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/clr_rd_req.rs b/jh7110-vf2-12a-pac/src/i2c4/clr_rd_req.rs index e275da1..4beae9d 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/clr_rd_req.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/clr_rd_req.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rd_req` reader - clr_rd_req"] pub type CLR_RD_REQ_R = crate::FieldReader; #[doc = "Field `clr_rd_req` writer - clr_rd_req"] -pub type CLR_RD_REQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RD_REQ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] #[must_use] - pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { - CLR_RD_REQ_W::new(self) + pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { + CLR_RD_REQ_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/clr_restart_det.rs b/jh7110-vf2-12a-pac/src/i2c4/clr_restart_det.rs index 5be7f5d..88d193c 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/clr_restart_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/clr_restart_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_restart_det` reader - clr_restart_det"] pub type CLR_RESTART_DET_R = crate::FieldReader; #[doc = "Field `clr_restart_det` writer - clr_restart_det"] -pub type CLR_RESTART_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RESTART_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] #[must_use] - pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { - CLR_RESTART_DET_W::new(self) + pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { + CLR_RESTART_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/clr_rx_done.rs b/jh7110-vf2-12a-pac/src/i2c4/clr_rx_done.rs index 02d83c5..7e14a3f 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/clr_rx_done.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/clr_rx_done.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_done` reader - clr_rx_done"] pub type CLR_RX_DONE_R = crate::FieldReader; #[doc = "Field `clr_rx_done` writer - clr_rx_done"] -pub type CLR_RX_DONE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_DONE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] #[must_use] - pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { - CLR_RX_DONE_W::new(self) + pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { + CLR_RX_DONE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/clr_rx_over.rs b/jh7110-vf2-12a-pac/src/i2c4/clr_rx_over.rs index 6d7ff4e..2302921 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/clr_rx_over.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/clr_rx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_over` reader - clr_rx_over"] pub type CLR_RX_OVER_R = crate::FieldReader; #[doc = "Field `clr_rx_over` writer - clr_rx_over"] -pub type CLR_RX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] #[must_use] - pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { - CLR_RX_OVER_W::new(self) + pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { + CLR_RX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/clr_rx_under.rs b/jh7110-vf2-12a-pac/src/i2c4/clr_rx_under.rs index 4a24f7c..35e15bd 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/clr_rx_under.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/clr_rx_under.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_under` reader - clr_rx_under"] pub type CLR_RX_UNDER_R = crate::FieldReader; #[doc = "Field `clr_rx_under` writer - clr_rx_under"] -pub type CLR_RX_UNDER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_UNDER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] #[must_use] - pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { - CLR_RX_UNDER_W::new(self) + pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { + CLR_RX_UNDER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/clr_start_det.rs b/jh7110-vf2-12a-pac/src/i2c4/clr_start_det.rs index cebc4bc..2314f65 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/clr_start_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/clr_start_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_start_det` reader - clr_start_det"] pub type CLR_START_DET_R = crate::FieldReader; #[doc = "Field `clr_start_det` writer - clr_start_det"] -pub type CLR_START_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_START_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] #[must_use] - pub fn clr_start_det(&mut self) -> CLR_START_DET_W { - CLR_START_DET_W::new(self) + pub fn clr_start_det(&mut self) -> CLR_START_DET_W { + CLR_START_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/clr_stop_det.rs b/jh7110-vf2-12a-pac/src/i2c4/clr_stop_det.rs index 44f39f3..49abcac 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/clr_stop_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/clr_stop_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_stop_det` reader - clr_stop_det"] pub type CLR_STOP_DET_R = crate::FieldReader; #[doc = "Field `clr_stop_det` writer - clr_stop_det"] -pub type CLR_STOP_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_STOP_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] #[must_use] - pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { - CLR_STOP_DET_W::new(self) + pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { + CLR_STOP_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/clr_tx_abrt.rs b/jh7110-vf2-12a-pac/src/i2c4/clr_tx_abrt.rs index 6ac441c..3bc0f6f 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/clr_tx_abrt.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/clr_tx_abrt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_abrt` reader - clr_tx_abrt"] pub type CLR_TX_ABRT_R = crate::FieldReader; #[doc = "Field `clr_tx_abrt` writer - clr_tx_abrt"] -pub type CLR_TX_ABRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_ABRT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] #[must_use] - pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { - CLR_TX_ABRT_W::new(self) + pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { + CLR_TX_ABRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/clr_tx_over.rs b/jh7110-vf2-12a-pac/src/i2c4/clr_tx_over.rs index 2b32b52..a5b6933 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/clr_tx_over.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/clr_tx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_over` reader - clr_tx_over"] pub type CLR_TX_OVER_R = crate::FieldReader; #[doc = "Field `clr_tx_over` writer - clr_tx_over"] -pub type CLR_TX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] #[must_use] - pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { - CLR_TX_OVER_W::new(self) + pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { + CLR_TX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/comp_param_1.rs b/jh7110-vf2-12a-pac/src/i2c4/comp_param_1.rs index 24a22e1..95c5002 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/comp_param_1.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/comp_param_1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/comp_type.rs b/jh7110-vf2-12a-pac/src/i2c4/comp_type.rs index ac916b5..1336c43 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/comp_type.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/comp_type.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/comp_version.rs b/jh7110-vf2-12a-pac/src/i2c4/comp_version.rs index 4be31fa..e8309c8 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/comp_version.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/comp_version.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/con.rs b/jh7110-vf2-12a-pac/src/i2c4/con.rs index 873c534..28aa865 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/con.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/con.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `master` reader - I2C Master Connection - 0: Slave, 1: Master"] pub type MASTER_R = crate::BitReader; #[doc = "Field `master` writer - I2C Master Connection - 0: Slave, 1: Master"] -pub type MASTER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `speed` reader - I2C Speed - 01: Standard, 10: Fast, 11: High"] pub type SPEED_R = crate::FieldReader; #[doc = "Field `speed` writer - I2C Speed - 01: Standard, 10: Fast, 11: High"] -pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `slave_10bitaddr` reader - I2C Slave 10-bit Address - 0: False, 1: True"] pub type SLAVE_10BITADDR_R = crate::BitReader; #[doc = "Field `slave_10bitaddr` writer - I2C Slave 10-bit Address - 0: False, 1: True"] -pub type SLAVE_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_10bitaddr` reader - I2C Master 10-bit Address - 0: False, 1: True"] pub type MASTER_10BITADDR_R = crate::BitReader; #[doc = "Field `master_10bitaddr` writer - I2C Master 10-bit Address - 0: False, 1: True"] -pub type MASTER_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_en` reader - I2C Restart Enable - 0: False, 1: True"] pub type RESTART_EN_R = crate::BitReader; #[doc = "Field `restart_en` writer - I2C Restart Enable - 0: False, 1: True"] -pub type RESTART_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_disable` reader - I2C Slave Disable - 0: False, 1: True"] pub type SLAVE_DISABLE_R = crate::BitReader; #[doc = "Field `slave_disable` writer - I2C Slave Disable - 0: False, 1: True"] -pub type SLAVE_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det_ifaddressed` reader - I2C Stop DET If Addressed - 0: False, 1: True"] pub type STOP_DET_IFADDRESSED_R = crate::BitReader; #[doc = "Field `stop_det_ifaddressed` writer - I2C Stop DET If Addressed - 0: False, 1: True"] -pub type STOP_DET_IFADDRESSED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty_ctrl` reader - I2C TX Empty Control - 0: False, 1: True"] pub type TX_EMPTY_CTRL_R = crate::BitReader; #[doc = "Field `tx_empty_ctrl` writer - I2C TX Empty Control - 0: False, 1: True"] -pub type TX_EMPTY_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_fifo_full_hld_ctrl` reader - I2C RX FIFO Full Hold Control - 0: False, 1: True"] pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; #[doc = "Field `rx_fifo_full_hld_ctrl` writer - I2C RX FIFO Full Hold Control - 0: False, 1: True"] -pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bus_clear_ctrl` reader - I2C Bus Clear Control - 0: False, 1: True"] pub type BUS_CLEAR_CTRL_R = crate::BitReader; #[doc = "Field `bus_clear_ctrl` writer - I2C Bus Clear Control - 0: False, 1: True"] -pub type BUS_CLEAR_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BUS_CLEAR_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] #[must_use] - pub fn master(&mut self) -> MASTER_W { - MASTER_W::new(self) + pub fn master(&mut self) -> MASTER_W { + MASTER_W::new(self, 0) } #[doc = "Bits 1:2 - I2C Speed - 01: Standard, 10: Fast, 11: High"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W { - SPEED_W::new(self) + pub fn speed(&mut self) -> SPEED_W { + SPEED_W::new(self, 1) } #[doc = "Bit 3 - I2C Slave 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { - SLAVE_10BITADDR_W::new(self) + pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { + SLAVE_10BITADDR_W::new(self, 3) } #[doc = "Bit 4 - I2C Master 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { - MASTER_10BITADDR_W::new(self) + pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { + MASTER_10BITADDR_W::new(self, 4) } #[doc = "Bit 5 - I2C Restart Enable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn restart_en(&mut self) -> RESTART_EN_W { - RESTART_EN_W::new(self) + pub fn restart_en(&mut self) -> RESTART_EN_W { + RESTART_EN_W::new(self, 5) } #[doc = "Bit 6 - I2C Slave Disable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { - SLAVE_DISABLE_W::new(self) + pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { + SLAVE_DISABLE_W::new(self, 6) } #[doc = "Bit 7 - I2C Stop DET If Addressed - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { - STOP_DET_IFADDRESSED_W::new(self) + pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { + STOP_DET_IFADDRESSED_W::new(self, 7) } #[doc = "Bit 8 - I2C TX Empty Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { - TX_EMPTY_CTRL_W::new(self) + pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { + TX_EMPTY_CTRL_W::new(self, 8) } #[doc = "Bit 9 - I2C RX FIFO Full Hold Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { - RX_FIFO_FULL_HLD_CTRL_W::new(self) + pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { + RX_FIFO_FULL_HLD_CTRL_W::new(self, 9) } #[doc = "Bit 11 - I2C Bus Clear Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { - BUS_CLEAR_CTRL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { + BUS_CLEAR_CTRL_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/data_cmd.rs b/jh7110-vf2-12a-pac/src/i2c4/data_cmd.rs index cf36408..2b320d4 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/data_cmd.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/data_cmd.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `dat` reader - Data Command Data Byte"] pub type DAT_R = crate::FieldReader; #[doc = "Field `dat` writer - Data Command Data Byte"] -pub type DAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `read` reader - Data Command READ Bit - 0: Write, 1: Read"] pub type READ_R = crate::BitReader; #[doc = "Field `read` writer - Data Command READ Bit - 0: Write, 1: Read"] -pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop` reader - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart` reader - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] pub type RESTART_R = crate::BitReader; #[doc = "Field `restart` writer - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] -pub type RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `first_data_byte` reader - Data Command First Data Byte - 0: False, 1: True"] pub type FIRST_DATA_BYTE_R = crate::BitReader; #[doc = "Field `first_data_byte` writer - Data Command First Data Byte - 0: False, 1: True"] -pub type FIRST_DATA_BYTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIRST_DATA_BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] #[must_use] - pub fn dat(&mut self) -> DAT_W { - DAT_W::new(self) + pub fn dat(&mut self) -> DAT_W { + DAT_W::new(self, 0) } #[doc = "Bit 8 - Data Command READ Bit - 0: Write, 1: Read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W { - READ_W::new(self) + pub fn read(&mut self) -> READ_W { + READ_W::new(self, 8) } #[doc = "Bit 9 - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 9) } #[doc = "Bit 10 - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] #[inline(always)] #[must_use] - pub fn restart(&mut self) -> RESTART_W { - RESTART_W::new(self) + pub fn restart(&mut self) -> RESTART_W { + RESTART_W::new(self, 10) } #[doc = "Bit 11 - Data Command First Data Byte - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { - FIRST_DATA_BYTE_W::new(self) + pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { + FIRST_DATA_BYTE_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/enable.rs b/jh7110-vf2-12a-pac/src/i2c4/enable.rs index c5ca9d7..3629f6b 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/enable.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/enable.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `abort` reader - abort"] pub type ABORT_R = crate::BitReader; #[doc = "Field `abort` writer - abort"] -pub type ABORT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 1 - abort"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 1 - abort"] #[inline(always)] #[must_use] - pub fn abort(&mut self) -> ABORT_W { - ABORT_W::new(self) + pub fn abort(&mut self) -> ABORT_W { + ABORT_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/enable_status.rs b/jh7110-vf2-12a-pac/src/i2c4/enable_status.rs index 2c102a6..8b9b7d3 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/enable_status.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/enable_status.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `activity` reader - activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tfe` reader - tfe"] pub type TFE_R = crate::BitReader; #[doc = "Field `tfe` writer - tfe"] -pub type TFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TFE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfne` reader - rfne"] pub type RFNE_R = crate::BitReader; #[doc = "Field `rfne` writer - rfne"] -pub type RFNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFNE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_activity` reader - master_activity"] pub type MASTER_ACTIVITY_R = crate::BitReader; #[doc = "Field `master_activity` writer - master_activity"] -pub type MASTER_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_activity` reader - slave_activity"] pub type SLAVE_ACTIVITY_R = crate::BitReader; #[doc = "Field `slave_activity` writer - slave_activity"] -pub type SLAVE_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - activity"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 0) } #[doc = "Bit 2 - tfe"] #[inline(always)] #[must_use] - pub fn tfe(&mut self) -> TFE_W { - TFE_W::new(self) + pub fn tfe(&mut self) -> TFE_W { + TFE_W::new(self, 2) } #[doc = "Bit 3 - rfne"] #[inline(always)] #[must_use] - pub fn rfne(&mut self) -> RFNE_W { - RFNE_W::new(self) + pub fn rfne(&mut self) -> RFNE_W { + RFNE_W::new(self, 3) } #[doc = "Bit 5 - master_activity"] #[inline(always)] #[must_use] - pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { - MASTER_ACTIVITY_W::new(self) + pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { + MASTER_ACTIVITY_W::new(self, 5) } #[doc = "Bit 6 - slave_activity"] #[inline(always)] #[must_use] - pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { - SLAVE_ACTIVITY_W::new(self) + pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { + SLAVE_ACTIVITY_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/fs_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c4/fs_scl_hcnt.rs index 9a9fd72..8a4f6d1 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/fs_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/fs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_hcnt` reader - fs_scl_hcnt"] pub type FS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_hcnt` writer - fs_scl_hcnt"] -pub type FS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { - FS_SCL_HCNT_W::new(self) + pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { + FS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/fs_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c4/fs_scl_lcnt.rs index 5e41cd1..4b4dd6b 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/fs_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/fs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_lcnt` reader - fs_scl_lcnt"] pub type FS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_lcnt` writer - fs_scl_lcnt"] -pub type FS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { - FS_SCL_LCNT_W::new(self) + pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { + FS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/hs_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c4/hs_scl_hcnt.rs index fba7f13..9b0a71c 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/hs_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/hs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_hcnt` reader - hs_scl_hcnt"] pub type HS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_hcnt` writer - hs_scl_hcnt"] -pub type HS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { - HS_SCL_HCNT_W::new(self) + pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { + HS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/hs_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c4/hs_scl_lcnt.rs index 9fca7a5..a715282 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/hs_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/hs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_lcnt` reader - hs_scl_lcnt"] pub type HS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_lcnt` writer - hs_scl_lcnt"] -pub type HS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { - HS_SCL_LCNT_W::new(self) + pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { + HS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/intr_mask.rs b/jh7110-vf2-12a-pac/src/i2c4/intr_mask.rs index 20a334f..769b629 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/intr_mask.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/intr_mask.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/intr_stat.rs b/jh7110-vf2-12a-pac/src/i2c4/intr_stat.rs index 2c2ba34..f376c26 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/intr_stat.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/raw_intr_stat.rs b/jh7110-vf2-12a-pac/src/i2c4/raw_intr_stat.rs index af97981..dd5e8e0 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/raw_intr_stat.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/raw_intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/rx_tl.rs b/jh7110-vf2-12a-pac/src/i2c4/rx_tl.rs index 1455a10..f3f39f4 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/rx_tl.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/rx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rx_tl` reader - rx_tl"] pub type RX_TL_R = crate::FieldReader; #[doc = "Field `rx_tl` writer - rx_tl"] -pub type RX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] #[must_use] - pub fn rx_tl(&mut self) -> RX_TL_W { - RX_TL_W::new(self) + pub fn rx_tl(&mut self) -> RX_TL_W { + RX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/rxflr.rs b/jh7110-vf2-12a-pac/src/i2c4/rxflr.rs index 910e254..4dccf5e 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/rxflr.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/rxflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rxflr` reader - rxflr"] pub type RXFLR_R = crate::FieldReader; #[doc = "Field `rxflr` writer - rxflr"] -pub type RXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] #[must_use] - pub fn rxflr(&mut self) -> RXFLR_W { - RXFLR_W::new(self) + pub fn rxflr(&mut self) -> RXFLR_W { + RXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/sar.rs b/jh7110-vf2-12a-pac/src/i2c4/sar.rs index d272e7a..1af6273 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/sar.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/sar.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Slave address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Slave address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Slave address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Slave address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; impl R { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Slave address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/sda_hold.rs b/jh7110-vf2-12a-pac/src/i2c4/sda_hold.rs index 82ceac5..d5d7512 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/sda_hold.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/sda_hold.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sda_hold` reader - sda_hold"] pub type SDA_HOLD_R = crate::FieldReader; #[doc = "Field `sda_hold` writer - sda_hold"] -pub type SDA_HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SDA_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] #[must_use] - pub fn sda_hold(&mut self) -> SDA_HOLD_W { - SDA_HOLD_W::new(self) + pub fn sda_hold(&mut self) -> SDA_HOLD_W { + SDA_HOLD_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/ss_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c4/ss_scl_hcnt.rs index 33736c7..77d7ea0 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/ss_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/ss_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_hcnt` reader - ss_scl_hcnt"] pub type SS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_hcnt` writer - ss_scl_hcnt"] -pub type SS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { - SS_SCL_HCNT_W::new(self) + pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { + SS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/ss_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c4/ss_scl_lcnt.rs index ce22b5d..8208747 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/ss_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/ss_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_lcnt` reader - ss_scl_lcnt"] pub type SS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_lcnt` writer - ss_scl_lcnt"] -pub type SS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { - SS_SCL_LCNT_W::new(self) + pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { + SS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/status.rs b/jh7110-vf2-12a-pac/src/i2c4/status.rs index 9489e49..1b7ab67 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/status.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/tar.rs b/jh7110-vf2-12a-pac/src/i2c4/tar.rs index 9fedc71..3044a8c 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/tar.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/tar.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Target address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Target address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Target address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Target address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; #[doc = "Field `mode` reader - Target addressing mode - 0: 7-bit, 1: 10-bit"] pub type MODE_R = crate::BitReader; #[doc = "Field `mode` writer - Target addressing mode - 0: 7-bit, 1: 10-bit"] -pub type MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Target address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } #[doc = "Bit 12 - Target addressing mode - 0: 7-bit, 1: 10-bit"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W { - MODE_W::new(self) + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 12) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/tx_abrt_source.rs b/jh7110-vf2-12a-pac/src/i2c4/tx_abrt_source.rs index 6f31813..c4fdf1a 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/tx_abrt_source.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/tx_abrt_source.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/tx_tl.rs b/jh7110-vf2-12a-pac/src/i2c4/tx_tl.rs index 84a1734..b0e6c64 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/tx_tl.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/tx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `tx_tl` reader - tx_tl"] pub type TX_TL_R = crate::FieldReader; #[doc = "Field `tx_tl` writer - tx_tl"] -pub type TX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] #[must_use] - pub fn tx_tl(&mut self) -> TX_TL_W { - TX_TL_W::new(self) + pub fn tx_tl(&mut self) -> TX_TL_W { + TX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c4/txflr.rs b/jh7110-vf2-12a-pac/src/i2c4/txflr.rs index b8e5fdd..5ca351d 100644 --- a/jh7110-vf2-12a-pac/src/i2c4/txflr.rs +++ b/jh7110-vf2-12a-pac/src/i2c4/txflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `txflr` reader - txflr"] pub type TXFLR_R = crate::FieldReader; #[doc = "Field `txflr` writer - txflr"] -pub type TXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - txflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - txflr"] #[inline(always)] #[must_use] - pub fn txflr(&mut self) -> TXFLR_W { - TXFLR_W::new(self) + pub fn txflr(&mut self) -> TXFLR_W { + TXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5.rs b/jh7110-vf2-12a-pac/src/i2c5.rs index d0fe76a..fdffe28 100644 --- a/jh7110-vf2-12a-pac/src/i2c5.rs +++ b/jh7110-vf2-12a-pac/src/i2c5.rs @@ -1,266 +1,416 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + con: CON, + tar: TAR, + sar: SAR, + _reserved3: [u8; 0x04], + data_cmd: DATA_CMD, + ss_scl_hcnt: SS_SCL_HCNT, + ss_scl_lcnt: SS_SCL_LCNT, + fs_scl_hcnt: FS_SCL_HCNT, + fs_scl_lcnt: FS_SCL_LCNT, + hs_scl_hcnt: HS_SCL_HCNT, + hs_scl_lcnt: HS_SCL_LCNT, + intr_stat: INTR_STAT, + intr_mask: INTR_MASK, + raw_intr_stat: RAW_INTR_STAT, + rx_tl: RX_TL, + tx_tl: TX_TL, + clr_intr: CLR_INTR, + clr_rx_under: CLR_RX_UNDER, + clr_rx_over: CLR_RX_OVER, + clr_tx_over: CLR_TX_OVER, + clr_rd_req: CLR_RD_REQ, + clr_tx_abrt: CLR_TX_ABRT, + clr_rx_done: CLR_RX_DONE, + clr_activity: CLR_ACTIVITY, + clr_stop_det: CLR_STOP_DET, + clr_start_det: CLR_START_DET, + clr_gen_call: CLR_GEN_CALL, + enable: ENABLE, + status: STATUS, + txflr: TXFLR, + rxflr: RXFLR, + sda_hold: SDA_HOLD, + tx_abrt_source: TX_ABRT_SOURCE, + _reserved32: [u8; 0x18], + enable_status: ENABLE_STATUS, + _reserved33: [u8; 0x08], + clr_restart_det: CLR_RESTART_DET, + _reserved34: [u8; 0x48], + comp_param_1: COMP_PARAM_1, + comp_version: COMP_VERSION, + comp_type: COMP_TYPE, +} +impl RegisterBlock { #[doc = "0x00 - DesignWare I2C CON"] - pub con: CON, + #[inline(always)] + pub const fn con(&self) -> &CON { + &self.con + } #[doc = "0x04 - DesignWare I2C TAR"] - pub tar: TAR, + #[inline(always)] + pub const fn tar(&self) -> &TAR { + &self.tar + } #[doc = "0x08 - DesignWare I2C SAR"] - pub sar: SAR, - _reserved3: [u8; 0x04], + #[inline(always)] + pub const fn sar(&self) -> &SAR { + &self.sar + } #[doc = "0x10 - DesignWare I2C Data Command"] - pub data_cmd: DATA_CMD, + #[inline(always)] + pub const fn data_cmd(&self) -> &DATA_CMD { + &self.data_cmd + } #[doc = "0x14 - DesignWare I2C SS SCL HCNT"] - pub ss_scl_hcnt: SS_SCL_HCNT, + #[inline(always)] + pub const fn ss_scl_hcnt(&self) -> &SS_SCL_HCNT { + &self.ss_scl_hcnt + } #[doc = "0x18 - DesignWare I2C SS SCL LCNT"] - pub ss_scl_lcnt: SS_SCL_LCNT, + #[inline(always)] + pub const fn ss_scl_lcnt(&self) -> &SS_SCL_LCNT { + &self.ss_scl_lcnt + } #[doc = "0x1c - DesignWare I2C FS SCL HCNT"] - pub fs_scl_hcnt: FS_SCL_HCNT, + #[inline(always)] + pub const fn fs_scl_hcnt(&self) -> &FS_SCL_HCNT { + &self.fs_scl_hcnt + } #[doc = "0x20 - DesignWare I2C FS SCL LCNT"] - pub fs_scl_lcnt: FS_SCL_LCNT, + #[inline(always)] + pub const fn fs_scl_lcnt(&self) -> &FS_SCL_LCNT { + &self.fs_scl_lcnt + } #[doc = "0x24 - DesignWare I2C HS SCL HCNT"] - pub hs_scl_hcnt: HS_SCL_HCNT, + #[inline(always)] + pub const fn hs_scl_hcnt(&self) -> &HS_SCL_HCNT { + &self.hs_scl_hcnt + } #[doc = "0x28 - DesignWare I2C HS SCL LCNT"] - pub hs_scl_lcnt: HS_SCL_LCNT, + #[inline(always)] + pub const fn hs_scl_lcnt(&self) -> &HS_SCL_LCNT { + &self.hs_scl_lcnt + } #[doc = "0x2c - DesignWare I2C Interrupt Status"] - pub intr_stat: INTR_STAT, + #[inline(always)] + pub const fn intr_stat(&self) -> &INTR_STAT { + &self.intr_stat + } #[doc = "0x30 - DesignWare I2C Interrupt Mask"] - pub intr_mask: INTR_MASK, + #[inline(always)] + pub const fn intr_mask(&self) -> &INTR_MASK { + &self.intr_mask + } #[doc = "0x34 - DesignWare I2C Raw Interrupt Status"] - pub raw_intr_stat: RAW_INTR_STAT, + #[inline(always)] + pub const fn raw_intr_stat(&self) -> &RAW_INTR_STAT { + &self.raw_intr_stat + } #[doc = "0x38 - DesignWare I2C RX TL"] - pub rx_tl: RX_TL, + #[inline(always)] + pub const fn rx_tl(&self) -> &RX_TL { + &self.rx_tl + } #[doc = "0x3c - DesignWare I2C TX TL"] - pub tx_tl: TX_TL, + #[inline(always)] + pub const fn tx_tl(&self) -> &TX_TL { + &self.tx_tl + } #[doc = "0x40 - DesignWare I2C Clear Interrrupt"] - pub clr_intr: CLR_INTR, + #[inline(always)] + pub const fn clr_intr(&self) -> &CLR_INTR { + &self.clr_intr + } #[doc = "0x44 - DesignWare I2C Clear RX Underrun"] - pub clr_rx_under: CLR_RX_UNDER, + #[inline(always)] + pub const fn clr_rx_under(&self) -> &CLR_RX_UNDER { + &self.clr_rx_under + } #[doc = "0x48 - DesignWare I2C Clear RX Overrun"] - pub clr_rx_over: CLR_RX_OVER, + #[inline(always)] + pub const fn clr_rx_over(&self) -> &CLR_RX_OVER { + &self.clr_rx_over + } #[doc = "0x4c - DesignWare I2C Clear TX Overrun"] - pub clr_tx_over: CLR_TX_OVER, + #[inline(always)] + pub const fn clr_tx_over(&self) -> &CLR_TX_OVER { + &self.clr_tx_over + } #[doc = "0x50 - DesignWare I2C Clear Read Request"] - pub clr_rd_req: CLR_RD_REQ, + #[inline(always)] + pub const fn clr_rd_req(&self) -> &CLR_RD_REQ { + &self.clr_rd_req + } #[doc = "0x54 - DesignWare I2C Clear TX Abort"] - pub clr_tx_abrt: CLR_TX_ABRT, + #[inline(always)] + pub const fn clr_tx_abrt(&self) -> &CLR_TX_ABRT { + &self.clr_tx_abrt + } #[doc = "0x58 - DesignWare I2C Clear RX Done"] - pub clr_rx_done: CLR_RX_DONE, + #[inline(always)] + pub const fn clr_rx_done(&self) -> &CLR_RX_DONE { + &self.clr_rx_done + } #[doc = "0x5c - DesignWare I2C Clear Activity"] - pub clr_activity: CLR_ACTIVITY, + #[inline(always)] + pub const fn clr_activity(&self) -> &CLR_ACTIVITY { + &self.clr_activity + } #[doc = "0x60 - DesignWare I2C Clear Stop DET"] - pub clr_stop_det: CLR_STOP_DET, + #[inline(always)] + pub const fn clr_stop_det(&self) -> &CLR_STOP_DET { + &self.clr_stop_det + } #[doc = "0x64 - DesignWare I2C Clear Start DET"] - pub clr_start_det: CLR_START_DET, + #[inline(always)] + pub const fn clr_start_det(&self) -> &CLR_START_DET { + &self.clr_start_det + } #[doc = "0x68 - DesignWare I2C Clear General Call"] - pub clr_gen_call: CLR_GEN_CALL, + #[inline(always)] + pub const fn clr_gen_call(&self) -> &CLR_GEN_CALL { + &self.clr_gen_call + } #[doc = "0x6c - DesignWare I2C Enable"] - pub enable: ENABLE, + #[inline(always)] + pub const fn enable(&self) -> &ENABLE { + &self.enable + } #[doc = "0x70 - DesignWare I2C Status"] - pub status: STATUS, + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } #[doc = "0x74 - DesignWare I2C TX Failure"] - pub txflr: TXFLR, + #[inline(always)] + pub const fn txflr(&self) -> &TXFLR { + &self.txflr + } #[doc = "0x78 - DesignWare I2C RX Failure"] - pub rxflr: RXFLR, + #[inline(always)] + pub const fn rxflr(&self) -> &RXFLR { + &self.rxflr + } #[doc = "0x7c - DesignWare I2C SDA Hold"] - pub sda_hold: SDA_HOLD, + #[inline(always)] + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold + } #[doc = "0x80 - DesignWare I2C TX Abort Source"] - pub tx_abrt_source: TX_ABRT_SOURCE, - _reserved32: [u8; 0x18], + #[inline(always)] + pub const fn tx_abrt_source(&self) -> &TX_ABRT_SOURCE { + &self.tx_abrt_source + } #[doc = "0x9c - DesignWare I2C Enable Status"] - pub enable_status: ENABLE_STATUS, - _reserved33: [u8; 0x08], + #[inline(always)] + pub const fn enable_status(&self) -> &ENABLE_STATUS { + &self.enable_status + } #[doc = "0xa8 - DesignWare I2C Clear Restart DET"] - pub clr_restart_det: CLR_RESTART_DET, - _reserved34: [u8; 0x48], + #[inline(always)] + pub const fn clr_restart_det(&self) -> &CLR_RESTART_DET { + &self.clr_restart_det + } #[doc = "0xf4 - DesignWare I2C Compatibility Parameter 1"] - pub comp_param_1: COMP_PARAM_1, + #[inline(always)] + pub const fn comp_param_1(&self) -> &COMP_PARAM_1 { + &self.comp_param_1 + } #[doc = "0xf8 - DesignWare I2C Compatibility Version"] - pub comp_version: COMP_VERSION, + #[inline(always)] + pub const fn comp_version(&self) -> &COMP_VERSION { + &self.comp_version + } #[doc = "0xfc - DesignWare I2C Compatibility Type"] - pub comp_type: COMP_TYPE, + #[inline(always)] + pub const fn comp_type(&self) -> &COMP_TYPE { + &self.comp_type + } } -#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`con`] +#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@con`] module"] pub type CON = crate::Reg; #[doc = "DesignWare I2C CON"] pub mod con; -#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tar`] +#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar`] module"] pub type TAR = crate::Reg; #[doc = "DesignWare I2C TAR"] pub mod tar; -#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sar`] +#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`] module"] pub type SAR = crate::Reg; #[doc = "DesignWare I2C SAR"] pub mod sar; -#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`data_cmd`] +#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_cmd`] module"] pub type DATA_CMD = crate::Reg; #[doc = "DesignWare I2C Data Command"] pub mod data_cmd; -#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_hcnt`] +#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_hcnt`] module"] pub type SS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL HCNT"] pub mod ss_scl_hcnt; -#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_lcnt`] +#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_lcnt`] module"] pub type SS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL LCNT"] pub mod ss_scl_lcnt; -#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_hcnt`] +#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_hcnt`] module"] pub type FS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL HCNT"] pub mod fs_scl_hcnt; -#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_lcnt`] +#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_lcnt`] module"] pub type FS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL LCNT"] pub mod fs_scl_lcnt; -#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_hcnt`] +#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_hcnt`] module"] pub type HS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL HCNT"] pub mod hs_scl_hcnt; -#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_lcnt`] +#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_lcnt`] module"] pub type HS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL LCNT"] pub mod hs_scl_lcnt; -#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_stat`] +#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"] pub type INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Interrupt Status"] pub mod intr_stat; -#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_mask`] +#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mask`] module"] pub type INTR_MASK = crate::Reg; #[doc = "DesignWare I2C Interrupt Mask"] pub mod intr_mask; -#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`raw_intr_stat`] +#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"] pub type RAW_INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Raw Interrupt Status"] pub mod raw_intr_stat; -#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rx_tl`] +#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tl`] module"] pub type RX_TL = crate::Reg; #[doc = "DesignWare I2C RX TL"] pub mod rx_tl; -#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_tl`] +#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_tl`] module"] pub type TX_TL = crate::Reg; #[doc = "DesignWare I2C TX TL"] pub mod tx_tl; -#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_intr`] +#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_intr`] module"] pub type CLR_INTR = crate::Reg; #[doc = "DesignWare I2C Clear Interrrupt"] pub mod clr_intr; -#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_under`] +#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_under`] module"] pub type CLR_RX_UNDER = crate::Reg; #[doc = "DesignWare I2C Clear RX Underrun"] pub mod clr_rx_under; -#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_over`] +#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_over`] module"] pub type CLR_RX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear RX Overrun"] pub mod clr_rx_over; -#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_over`] +#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_over`] module"] pub type CLR_TX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear TX Overrun"] pub mod clr_tx_over; -#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rd_req`] +#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rd_req`] module"] pub type CLR_RD_REQ = crate::Reg; #[doc = "DesignWare I2C Clear Read Request"] pub mod clr_rd_req; -#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_abrt`] +#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_abrt`] module"] pub type CLR_TX_ABRT = crate::Reg; #[doc = "DesignWare I2C Clear TX Abort"] pub mod clr_tx_abrt; -#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_done`] +#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_done`] module"] pub type CLR_RX_DONE = crate::Reg; #[doc = "DesignWare I2C Clear RX Done"] pub mod clr_rx_done; -#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_activity`] +#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_activity`] module"] pub type CLR_ACTIVITY = crate::Reg; #[doc = "DesignWare I2C Clear Activity"] pub mod clr_activity; -#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_stop_det`] +#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_stop_det`] module"] pub type CLR_STOP_DET = crate::Reg; #[doc = "DesignWare I2C Clear Stop DET"] pub mod clr_stop_det; -#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_start_det`] +#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_start_det`] module"] pub type CLR_START_DET = crate::Reg; #[doc = "DesignWare I2C Clear Start DET"] pub mod clr_start_det; -#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_gen_call`] +#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_gen_call`] module"] pub type CLR_GEN_CALL = crate::Reg; #[doc = "DesignWare I2C Clear General Call"] pub mod clr_gen_call; -#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable`] +#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] pub type ENABLE = crate::Reg; #[doc = "DesignWare I2C Enable"] pub mod enable; -#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`status`] +#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] pub type STATUS = crate::Reg; #[doc = "DesignWare I2C Status"] pub mod status; -#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txflr`] +#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txflr`] module"] pub type TXFLR = crate::Reg; #[doc = "DesignWare I2C TX Failure"] pub mod txflr; -#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxflr`] +#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxflr`] module"] pub type RXFLR = crate::Reg; #[doc = "DesignWare I2C RX Failure"] pub mod rxflr; -#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sda_hold`] +#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] pub type SDA_HOLD = crate::Reg; #[doc = "DesignWare I2C SDA Hold"] pub mod sda_hold; -#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_abrt_source`] +#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_abrt_source`] module"] pub type TX_ABRT_SOURCE = crate::Reg; #[doc = "DesignWare I2C TX Abort Source"] pub mod tx_abrt_source; -#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_status`] +#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_status`] module"] pub type ENABLE_STATUS = crate::Reg; #[doc = "DesignWare I2C Enable Status"] pub mod enable_status; -#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_restart_det`] +#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_restart_det`] module"] pub type CLR_RESTART_DET = crate::Reg; #[doc = "DesignWare I2C Clear Restart DET"] pub mod clr_restart_det; -#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_param_1`] +#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_param_1`] module"] pub type COMP_PARAM_1 = crate::Reg; #[doc = "DesignWare I2C Compatibility Parameter 1"] pub mod comp_param_1; -#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_version`] +#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_version`] module"] pub type COMP_VERSION = crate::Reg; #[doc = "DesignWare I2C Compatibility Version"] pub mod comp_version; -#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_type`] +#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_type`] module"] pub type COMP_TYPE = crate::Reg; #[doc = "DesignWare I2C Compatibility Type"] diff --git a/jh7110-vf2-12a-pac/src/i2c5/clr_activity.rs b/jh7110-vf2-12a-pac/src/i2c5/clr_activity.rs index d26bb80..1ee2297 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/clr_activity.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/clr_activity.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_activity` reader - clr_activity"] pub type CLR_ACTIVITY_R = crate::FieldReader; #[doc = "Field `clr_activity` writer - clr_activity"] -pub type CLR_ACTIVITY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_ACTIVITY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] #[must_use] - pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { - CLR_ACTIVITY_W::new(self) + pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { + CLR_ACTIVITY_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/clr_gen_call.rs b/jh7110-vf2-12a-pac/src/i2c5/clr_gen_call.rs index a9ea5af..4a7c5ba 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/clr_gen_call.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/clr_gen_call.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_gen_call` reader - clr_gen_call"] pub type CLR_GEN_CALL_R = crate::FieldReader; #[doc = "Field `clr_gen_call` writer - clr_gen_call"] -pub type CLR_GEN_CALL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_GEN_CALL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] #[must_use] - pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { - CLR_GEN_CALL_W::new(self) + pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { + CLR_GEN_CALL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/clr_intr.rs b/jh7110-vf2-12a-pac/src/i2c5/clr_intr.rs index a7daf57..cf57b09 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/clr_intr.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/clr_intr.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/clr_rd_req.rs b/jh7110-vf2-12a-pac/src/i2c5/clr_rd_req.rs index e275da1..4beae9d 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/clr_rd_req.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/clr_rd_req.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rd_req` reader - clr_rd_req"] pub type CLR_RD_REQ_R = crate::FieldReader; #[doc = "Field `clr_rd_req` writer - clr_rd_req"] -pub type CLR_RD_REQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RD_REQ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] #[must_use] - pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { - CLR_RD_REQ_W::new(self) + pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { + CLR_RD_REQ_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/clr_restart_det.rs b/jh7110-vf2-12a-pac/src/i2c5/clr_restart_det.rs index 5be7f5d..88d193c 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/clr_restart_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/clr_restart_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_restart_det` reader - clr_restart_det"] pub type CLR_RESTART_DET_R = crate::FieldReader; #[doc = "Field `clr_restart_det` writer - clr_restart_det"] -pub type CLR_RESTART_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RESTART_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] #[must_use] - pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { - CLR_RESTART_DET_W::new(self) + pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { + CLR_RESTART_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/clr_rx_done.rs b/jh7110-vf2-12a-pac/src/i2c5/clr_rx_done.rs index 02d83c5..7e14a3f 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/clr_rx_done.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/clr_rx_done.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_done` reader - clr_rx_done"] pub type CLR_RX_DONE_R = crate::FieldReader; #[doc = "Field `clr_rx_done` writer - clr_rx_done"] -pub type CLR_RX_DONE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_DONE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] #[must_use] - pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { - CLR_RX_DONE_W::new(self) + pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { + CLR_RX_DONE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/clr_rx_over.rs b/jh7110-vf2-12a-pac/src/i2c5/clr_rx_over.rs index 6d7ff4e..2302921 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/clr_rx_over.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/clr_rx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_over` reader - clr_rx_over"] pub type CLR_RX_OVER_R = crate::FieldReader; #[doc = "Field `clr_rx_over` writer - clr_rx_over"] -pub type CLR_RX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] #[must_use] - pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { - CLR_RX_OVER_W::new(self) + pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { + CLR_RX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/clr_rx_under.rs b/jh7110-vf2-12a-pac/src/i2c5/clr_rx_under.rs index 4a24f7c..35e15bd 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/clr_rx_under.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/clr_rx_under.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_under` reader - clr_rx_under"] pub type CLR_RX_UNDER_R = crate::FieldReader; #[doc = "Field `clr_rx_under` writer - clr_rx_under"] -pub type CLR_RX_UNDER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_UNDER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] #[must_use] - pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { - CLR_RX_UNDER_W::new(self) + pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { + CLR_RX_UNDER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/clr_start_det.rs b/jh7110-vf2-12a-pac/src/i2c5/clr_start_det.rs index cebc4bc..2314f65 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/clr_start_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/clr_start_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_start_det` reader - clr_start_det"] pub type CLR_START_DET_R = crate::FieldReader; #[doc = "Field `clr_start_det` writer - clr_start_det"] -pub type CLR_START_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_START_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] #[must_use] - pub fn clr_start_det(&mut self) -> CLR_START_DET_W { - CLR_START_DET_W::new(self) + pub fn clr_start_det(&mut self) -> CLR_START_DET_W { + CLR_START_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/clr_stop_det.rs b/jh7110-vf2-12a-pac/src/i2c5/clr_stop_det.rs index 44f39f3..49abcac 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/clr_stop_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/clr_stop_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_stop_det` reader - clr_stop_det"] pub type CLR_STOP_DET_R = crate::FieldReader; #[doc = "Field `clr_stop_det` writer - clr_stop_det"] -pub type CLR_STOP_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_STOP_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] #[must_use] - pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { - CLR_STOP_DET_W::new(self) + pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { + CLR_STOP_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/clr_tx_abrt.rs b/jh7110-vf2-12a-pac/src/i2c5/clr_tx_abrt.rs index 6ac441c..3bc0f6f 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/clr_tx_abrt.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/clr_tx_abrt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_abrt` reader - clr_tx_abrt"] pub type CLR_TX_ABRT_R = crate::FieldReader; #[doc = "Field `clr_tx_abrt` writer - clr_tx_abrt"] -pub type CLR_TX_ABRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_ABRT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] #[must_use] - pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { - CLR_TX_ABRT_W::new(self) + pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { + CLR_TX_ABRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/clr_tx_over.rs b/jh7110-vf2-12a-pac/src/i2c5/clr_tx_over.rs index 2b32b52..a5b6933 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/clr_tx_over.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/clr_tx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_over` reader - clr_tx_over"] pub type CLR_TX_OVER_R = crate::FieldReader; #[doc = "Field `clr_tx_over` writer - clr_tx_over"] -pub type CLR_TX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] #[must_use] - pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { - CLR_TX_OVER_W::new(self) + pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { + CLR_TX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/comp_param_1.rs b/jh7110-vf2-12a-pac/src/i2c5/comp_param_1.rs index 24a22e1..95c5002 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/comp_param_1.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/comp_param_1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/comp_type.rs b/jh7110-vf2-12a-pac/src/i2c5/comp_type.rs index ac916b5..1336c43 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/comp_type.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/comp_type.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/comp_version.rs b/jh7110-vf2-12a-pac/src/i2c5/comp_version.rs index 4be31fa..e8309c8 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/comp_version.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/comp_version.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/con.rs b/jh7110-vf2-12a-pac/src/i2c5/con.rs index 873c534..28aa865 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/con.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/con.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `master` reader - I2C Master Connection - 0: Slave, 1: Master"] pub type MASTER_R = crate::BitReader; #[doc = "Field `master` writer - I2C Master Connection - 0: Slave, 1: Master"] -pub type MASTER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `speed` reader - I2C Speed - 01: Standard, 10: Fast, 11: High"] pub type SPEED_R = crate::FieldReader; #[doc = "Field `speed` writer - I2C Speed - 01: Standard, 10: Fast, 11: High"] -pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `slave_10bitaddr` reader - I2C Slave 10-bit Address - 0: False, 1: True"] pub type SLAVE_10BITADDR_R = crate::BitReader; #[doc = "Field `slave_10bitaddr` writer - I2C Slave 10-bit Address - 0: False, 1: True"] -pub type SLAVE_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_10bitaddr` reader - I2C Master 10-bit Address - 0: False, 1: True"] pub type MASTER_10BITADDR_R = crate::BitReader; #[doc = "Field `master_10bitaddr` writer - I2C Master 10-bit Address - 0: False, 1: True"] -pub type MASTER_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_en` reader - I2C Restart Enable - 0: False, 1: True"] pub type RESTART_EN_R = crate::BitReader; #[doc = "Field `restart_en` writer - I2C Restart Enable - 0: False, 1: True"] -pub type RESTART_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_disable` reader - I2C Slave Disable - 0: False, 1: True"] pub type SLAVE_DISABLE_R = crate::BitReader; #[doc = "Field `slave_disable` writer - I2C Slave Disable - 0: False, 1: True"] -pub type SLAVE_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det_ifaddressed` reader - I2C Stop DET If Addressed - 0: False, 1: True"] pub type STOP_DET_IFADDRESSED_R = crate::BitReader; #[doc = "Field `stop_det_ifaddressed` writer - I2C Stop DET If Addressed - 0: False, 1: True"] -pub type STOP_DET_IFADDRESSED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty_ctrl` reader - I2C TX Empty Control - 0: False, 1: True"] pub type TX_EMPTY_CTRL_R = crate::BitReader; #[doc = "Field `tx_empty_ctrl` writer - I2C TX Empty Control - 0: False, 1: True"] -pub type TX_EMPTY_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_fifo_full_hld_ctrl` reader - I2C RX FIFO Full Hold Control - 0: False, 1: True"] pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; #[doc = "Field `rx_fifo_full_hld_ctrl` writer - I2C RX FIFO Full Hold Control - 0: False, 1: True"] -pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bus_clear_ctrl` reader - I2C Bus Clear Control - 0: False, 1: True"] pub type BUS_CLEAR_CTRL_R = crate::BitReader; #[doc = "Field `bus_clear_ctrl` writer - I2C Bus Clear Control - 0: False, 1: True"] -pub type BUS_CLEAR_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BUS_CLEAR_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] #[must_use] - pub fn master(&mut self) -> MASTER_W { - MASTER_W::new(self) + pub fn master(&mut self) -> MASTER_W { + MASTER_W::new(self, 0) } #[doc = "Bits 1:2 - I2C Speed - 01: Standard, 10: Fast, 11: High"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W { - SPEED_W::new(self) + pub fn speed(&mut self) -> SPEED_W { + SPEED_W::new(self, 1) } #[doc = "Bit 3 - I2C Slave 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { - SLAVE_10BITADDR_W::new(self) + pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { + SLAVE_10BITADDR_W::new(self, 3) } #[doc = "Bit 4 - I2C Master 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { - MASTER_10BITADDR_W::new(self) + pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { + MASTER_10BITADDR_W::new(self, 4) } #[doc = "Bit 5 - I2C Restart Enable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn restart_en(&mut self) -> RESTART_EN_W { - RESTART_EN_W::new(self) + pub fn restart_en(&mut self) -> RESTART_EN_W { + RESTART_EN_W::new(self, 5) } #[doc = "Bit 6 - I2C Slave Disable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { - SLAVE_DISABLE_W::new(self) + pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { + SLAVE_DISABLE_W::new(self, 6) } #[doc = "Bit 7 - I2C Stop DET If Addressed - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { - STOP_DET_IFADDRESSED_W::new(self) + pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { + STOP_DET_IFADDRESSED_W::new(self, 7) } #[doc = "Bit 8 - I2C TX Empty Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { - TX_EMPTY_CTRL_W::new(self) + pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { + TX_EMPTY_CTRL_W::new(self, 8) } #[doc = "Bit 9 - I2C RX FIFO Full Hold Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { - RX_FIFO_FULL_HLD_CTRL_W::new(self) + pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { + RX_FIFO_FULL_HLD_CTRL_W::new(self, 9) } #[doc = "Bit 11 - I2C Bus Clear Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { - BUS_CLEAR_CTRL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { + BUS_CLEAR_CTRL_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/data_cmd.rs b/jh7110-vf2-12a-pac/src/i2c5/data_cmd.rs index cf36408..2b320d4 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/data_cmd.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/data_cmd.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `dat` reader - Data Command Data Byte"] pub type DAT_R = crate::FieldReader; #[doc = "Field `dat` writer - Data Command Data Byte"] -pub type DAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `read` reader - Data Command READ Bit - 0: Write, 1: Read"] pub type READ_R = crate::BitReader; #[doc = "Field `read` writer - Data Command READ Bit - 0: Write, 1: Read"] -pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop` reader - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart` reader - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] pub type RESTART_R = crate::BitReader; #[doc = "Field `restart` writer - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] -pub type RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `first_data_byte` reader - Data Command First Data Byte - 0: False, 1: True"] pub type FIRST_DATA_BYTE_R = crate::BitReader; #[doc = "Field `first_data_byte` writer - Data Command First Data Byte - 0: False, 1: True"] -pub type FIRST_DATA_BYTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIRST_DATA_BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] #[must_use] - pub fn dat(&mut self) -> DAT_W { - DAT_W::new(self) + pub fn dat(&mut self) -> DAT_W { + DAT_W::new(self, 0) } #[doc = "Bit 8 - Data Command READ Bit - 0: Write, 1: Read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W { - READ_W::new(self) + pub fn read(&mut self) -> READ_W { + READ_W::new(self, 8) } #[doc = "Bit 9 - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 9) } #[doc = "Bit 10 - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] #[inline(always)] #[must_use] - pub fn restart(&mut self) -> RESTART_W { - RESTART_W::new(self) + pub fn restart(&mut self) -> RESTART_W { + RESTART_W::new(self, 10) } #[doc = "Bit 11 - Data Command First Data Byte - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { - FIRST_DATA_BYTE_W::new(self) + pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { + FIRST_DATA_BYTE_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/enable.rs b/jh7110-vf2-12a-pac/src/i2c5/enable.rs index c5ca9d7..3629f6b 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/enable.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/enable.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `abort` reader - abort"] pub type ABORT_R = crate::BitReader; #[doc = "Field `abort` writer - abort"] -pub type ABORT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 1 - abort"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 1 - abort"] #[inline(always)] #[must_use] - pub fn abort(&mut self) -> ABORT_W { - ABORT_W::new(self) + pub fn abort(&mut self) -> ABORT_W { + ABORT_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/enable_status.rs b/jh7110-vf2-12a-pac/src/i2c5/enable_status.rs index 2c102a6..8b9b7d3 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/enable_status.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/enable_status.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `activity` reader - activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tfe` reader - tfe"] pub type TFE_R = crate::BitReader; #[doc = "Field `tfe` writer - tfe"] -pub type TFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TFE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfne` reader - rfne"] pub type RFNE_R = crate::BitReader; #[doc = "Field `rfne` writer - rfne"] -pub type RFNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFNE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_activity` reader - master_activity"] pub type MASTER_ACTIVITY_R = crate::BitReader; #[doc = "Field `master_activity` writer - master_activity"] -pub type MASTER_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_activity` reader - slave_activity"] pub type SLAVE_ACTIVITY_R = crate::BitReader; #[doc = "Field `slave_activity` writer - slave_activity"] -pub type SLAVE_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - activity"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 0) } #[doc = "Bit 2 - tfe"] #[inline(always)] #[must_use] - pub fn tfe(&mut self) -> TFE_W { - TFE_W::new(self) + pub fn tfe(&mut self) -> TFE_W { + TFE_W::new(self, 2) } #[doc = "Bit 3 - rfne"] #[inline(always)] #[must_use] - pub fn rfne(&mut self) -> RFNE_W { - RFNE_W::new(self) + pub fn rfne(&mut self) -> RFNE_W { + RFNE_W::new(self, 3) } #[doc = "Bit 5 - master_activity"] #[inline(always)] #[must_use] - pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { - MASTER_ACTIVITY_W::new(self) + pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { + MASTER_ACTIVITY_W::new(self, 5) } #[doc = "Bit 6 - slave_activity"] #[inline(always)] #[must_use] - pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { - SLAVE_ACTIVITY_W::new(self) + pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { + SLAVE_ACTIVITY_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/fs_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c5/fs_scl_hcnt.rs index 9a9fd72..8a4f6d1 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/fs_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/fs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_hcnt` reader - fs_scl_hcnt"] pub type FS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_hcnt` writer - fs_scl_hcnt"] -pub type FS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { - FS_SCL_HCNT_W::new(self) + pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { + FS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/fs_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c5/fs_scl_lcnt.rs index 5e41cd1..4b4dd6b 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/fs_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/fs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_lcnt` reader - fs_scl_lcnt"] pub type FS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_lcnt` writer - fs_scl_lcnt"] -pub type FS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { - FS_SCL_LCNT_W::new(self) + pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { + FS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/hs_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c5/hs_scl_hcnt.rs index fba7f13..9b0a71c 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/hs_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/hs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_hcnt` reader - hs_scl_hcnt"] pub type HS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_hcnt` writer - hs_scl_hcnt"] -pub type HS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { - HS_SCL_HCNT_W::new(self) + pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { + HS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/hs_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c5/hs_scl_lcnt.rs index 9fca7a5..a715282 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/hs_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/hs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_lcnt` reader - hs_scl_lcnt"] pub type HS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_lcnt` writer - hs_scl_lcnt"] -pub type HS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { - HS_SCL_LCNT_W::new(self) + pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { + HS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/intr_mask.rs b/jh7110-vf2-12a-pac/src/i2c5/intr_mask.rs index 20a334f..769b629 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/intr_mask.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/intr_mask.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/intr_stat.rs b/jh7110-vf2-12a-pac/src/i2c5/intr_stat.rs index 2c2ba34..f376c26 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/intr_stat.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/raw_intr_stat.rs b/jh7110-vf2-12a-pac/src/i2c5/raw_intr_stat.rs index af97981..dd5e8e0 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/raw_intr_stat.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/raw_intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/rx_tl.rs b/jh7110-vf2-12a-pac/src/i2c5/rx_tl.rs index 1455a10..f3f39f4 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/rx_tl.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/rx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rx_tl` reader - rx_tl"] pub type RX_TL_R = crate::FieldReader; #[doc = "Field `rx_tl` writer - rx_tl"] -pub type RX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] #[must_use] - pub fn rx_tl(&mut self) -> RX_TL_W { - RX_TL_W::new(self) + pub fn rx_tl(&mut self) -> RX_TL_W { + RX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/rxflr.rs b/jh7110-vf2-12a-pac/src/i2c5/rxflr.rs index 910e254..4dccf5e 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/rxflr.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/rxflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rxflr` reader - rxflr"] pub type RXFLR_R = crate::FieldReader; #[doc = "Field `rxflr` writer - rxflr"] -pub type RXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] #[must_use] - pub fn rxflr(&mut self) -> RXFLR_W { - RXFLR_W::new(self) + pub fn rxflr(&mut self) -> RXFLR_W { + RXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/sar.rs b/jh7110-vf2-12a-pac/src/i2c5/sar.rs index d272e7a..1af6273 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/sar.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/sar.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Slave address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Slave address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Slave address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Slave address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; impl R { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Slave address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/sda_hold.rs b/jh7110-vf2-12a-pac/src/i2c5/sda_hold.rs index 82ceac5..d5d7512 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/sda_hold.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/sda_hold.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sda_hold` reader - sda_hold"] pub type SDA_HOLD_R = crate::FieldReader; #[doc = "Field `sda_hold` writer - sda_hold"] -pub type SDA_HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SDA_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] #[must_use] - pub fn sda_hold(&mut self) -> SDA_HOLD_W { - SDA_HOLD_W::new(self) + pub fn sda_hold(&mut self) -> SDA_HOLD_W { + SDA_HOLD_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/ss_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c5/ss_scl_hcnt.rs index 33736c7..77d7ea0 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/ss_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/ss_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_hcnt` reader - ss_scl_hcnt"] pub type SS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_hcnt` writer - ss_scl_hcnt"] -pub type SS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { - SS_SCL_HCNT_W::new(self) + pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { + SS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/ss_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c5/ss_scl_lcnt.rs index ce22b5d..8208747 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/ss_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/ss_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_lcnt` reader - ss_scl_lcnt"] pub type SS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_lcnt` writer - ss_scl_lcnt"] -pub type SS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { - SS_SCL_LCNT_W::new(self) + pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { + SS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/status.rs b/jh7110-vf2-12a-pac/src/i2c5/status.rs index 9489e49..1b7ab67 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/status.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/tar.rs b/jh7110-vf2-12a-pac/src/i2c5/tar.rs index 9fedc71..3044a8c 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/tar.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/tar.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Target address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Target address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Target address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Target address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; #[doc = "Field `mode` reader - Target addressing mode - 0: 7-bit, 1: 10-bit"] pub type MODE_R = crate::BitReader; #[doc = "Field `mode` writer - Target addressing mode - 0: 7-bit, 1: 10-bit"] -pub type MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Target address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } #[doc = "Bit 12 - Target addressing mode - 0: 7-bit, 1: 10-bit"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W { - MODE_W::new(self) + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 12) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/tx_abrt_source.rs b/jh7110-vf2-12a-pac/src/i2c5/tx_abrt_source.rs index 6f31813..c4fdf1a 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/tx_abrt_source.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/tx_abrt_source.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/tx_tl.rs b/jh7110-vf2-12a-pac/src/i2c5/tx_tl.rs index 84a1734..b0e6c64 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/tx_tl.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/tx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `tx_tl` reader - tx_tl"] pub type TX_TL_R = crate::FieldReader; #[doc = "Field `tx_tl` writer - tx_tl"] -pub type TX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] #[must_use] - pub fn tx_tl(&mut self) -> TX_TL_W { - TX_TL_W::new(self) + pub fn tx_tl(&mut self) -> TX_TL_W { + TX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c5/txflr.rs b/jh7110-vf2-12a-pac/src/i2c5/txflr.rs index b8e5fdd..5ca351d 100644 --- a/jh7110-vf2-12a-pac/src/i2c5/txflr.rs +++ b/jh7110-vf2-12a-pac/src/i2c5/txflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `txflr` reader - txflr"] pub type TXFLR_R = crate::FieldReader; #[doc = "Field `txflr` writer - txflr"] -pub type TXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - txflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - txflr"] #[inline(always)] #[must_use] - pub fn txflr(&mut self) -> TXFLR_W { - TXFLR_W::new(self) + pub fn txflr(&mut self) -> TXFLR_W { + TXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6.rs b/jh7110-vf2-12a-pac/src/i2c6.rs index d0fe76a..fdffe28 100644 --- a/jh7110-vf2-12a-pac/src/i2c6.rs +++ b/jh7110-vf2-12a-pac/src/i2c6.rs @@ -1,266 +1,416 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + con: CON, + tar: TAR, + sar: SAR, + _reserved3: [u8; 0x04], + data_cmd: DATA_CMD, + ss_scl_hcnt: SS_SCL_HCNT, + ss_scl_lcnt: SS_SCL_LCNT, + fs_scl_hcnt: FS_SCL_HCNT, + fs_scl_lcnt: FS_SCL_LCNT, + hs_scl_hcnt: HS_SCL_HCNT, + hs_scl_lcnt: HS_SCL_LCNT, + intr_stat: INTR_STAT, + intr_mask: INTR_MASK, + raw_intr_stat: RAW_INTR_STAT, + rx_tl: RX_TL, + tx_tl: TX_TL, + clr_intr: CLR_INTR, + clr_rx_under: CLR_RX_UNDER, + clr_rx_over: CLR_RX_OVER, + clr_tx_over: CLR_TX_OVER, + clr_rd_req: CLR_RD_REQ, + clr_tx_abrt: CLR_TX_ABRT, + clr_rx_done: CLR_RX_DONE, + clr_activity: CLR_ACTIVITY, + clr_stop_det: CLR_STOP_DET, + clr_start_det: CLR_START_DET, + clr_gen_call: CLR_GEN_CALL, + enable: ENABLE, + status: STATUS, + txflr: TXFLR, + rxflr: RXFLR, + sda_hold: SDA_HOLD, + tx_abrt_source: TX_ABRT_SOURCE, + _reserved32: [u8; 0x18], + enable_status: ENABLE_STATUS, + _reserved33: [u8; 0x08], + clr_restart_det: CLR_RESTART_DET, + _reserved34: [u8; 0x48], + comp_param_1: COMP_PARAM_1, + comp_version: COMP_VERSION, + comp_type: COMP_TYPE, +} +impl RegisterBlock { #[doc = "0x00 - DesignWare I2C CON"] - pub con: CON, + #[inline(always)] + pub const fn con(&self) -> &CON { + &self.con + } #[doc = "0x04 - DesignWare I2C TAR"] - pub tar: TAR, + #[inline(always)] + pub const fn tar(&self) -> &TAR { + &self.tar + } #[doc = "0x08 - DesignWare I2C SAR"] - pub sar: SAR, - _reserved3: [u8; 0x04], + #[inline(always)] + pub const fn sar(&self) -> &SAR { + &self.sar + } #[doc = "0x10 - DesignWare I2C Data Command"] - pub data_cmd: DATA_CMD, + #[inline(always)] + pub const fn data_cmd(&self) -> &DATA_CMD { + &self.data_cmd + } #[doc = "0x14 - DesignWare I2C SS SCL HCNT"] - pub ss_scl_hcnt: SS_SCL_HCNT, + #[inline(always)] + pub const fn ss_scl_hcnt(&self) -> &SS_SCL_HCNT { + &self.ss_scl_hcnt + } #[doc = "0x18 - DesignWare I2C SS SCL LCNT"] - pub ss_scl_lcnt: SS_SCL_LCNT, + #[inline(always)] + pub const fn ss_scl_lcnt(&self) -> &SS_SCL_LCNT { + &self.ss_scl_lcnt + } #[doc = "0x1c - DesignWare I2C FS SCL HCNT"] - pub fs_scl_hcnt: FS_SCL_HCNT, + #[inline(always)] + pub const fn fs_scl_hcnt(&self) -> &FS_SCL_HCNT { + &self.fs_scl_hcnt + } #[doc = "0x20 - DesignWare I2C FS SCL LCNT"] - pub fs_scl_lcnt: FS_SCL_LCNT, + #[inline(always)] + pub const fn fs_scl_lcnt(&self) -> &FS_SCL_LCNT { + &self.fs_scl_lcnt + } #[doc = "0x24 - DesignWare I2C HS SCL HCNT"] - pub hs_scl_hcnt: HS_SCL_HCNT, + #[inline(always)] + pub const fn hs_scl_hcnt(&self) -> &HS_SCL_HCNT { + &self.hs_scl_hcnt + } #[doc = "0x28 - DesignWare I2C HS SCL LCNT"] - pub hs_scl_lcnt: HS_SCL_LCNT, + #[inline(always)] + pub const fn hs_scl_lcnt(&self) -> &HS_SCL_LCNT { + &self.hs_scl_lcnt + } #[doc = "0x2c - DesignWare I2C Interrupt Status"] - pub intr_stat: INTR_STAT, + #[inline(always)] + pub const fn intr_stat(&self) -> &INTR_STAT { + &self.intr_stat + } #[doc = "0x30 - DesignWare I2C Interrupt Mask"] - pub intr_mask: INTR_MASK, + #[inline(always)] + pub const fn intr_mask(&self) -> &INTR_MASK { + &self.intr_mask + } #[doc = "0x34 - DesignWare I2C Raw Interrupt Status"] - pub raw_intr_stat: RAW_INTR_STAT, + #[inline(always)] + pub const fn raw_intr_stat(&self) -> &RAW_INTR_STAT { + &self.raw_intr_stat + } #[doc = "0x38 - DesignWare I2C RX TL"] - pub rx_tl: RX_TL, + #[inline(always)] + pub const fn rx_tl(&self) -> &RX_TL { + &self.rx_tl + } #[doc = "0x3c - DesignWare I2C TX TL"] - pub tx_tl: TX_TL, + #[inline(always)] + pub const fn tx_tl(&self) -> &TX_TL { + &self.tx_tl + } #[doc = "0x40 - DesignWare I2C Clear Interrrupt"] - pub clr_intr: CLR_INTR, + #[inline(always)] + pub const fn clr_intr(&self) -> &CLR_INTR { + &self.clr_intr + } #[doc = "0x44 - DesignWare I2C Clear RX Underrun"] - pub clr_rx_under: CLR_RX_UNDER, + #[inline(always)] + pub const fn clr_rx_under(&self) -> &CLR_RX_UNDER { + &self.clr_rx_under + } #[doc = "0x48 - DesignWare I2C Clear RX Overrun"] - pub clr_rx_over: CLR_RX_OVER, + #[inline(always)] + pub const fn clr_rx_over(&self) -> &CLR_RX_OVER { + &self.clr_rx_over + } #[doc = "0x4c - DesignWare I2C Clear TX Overrun"] - pub clr_tx_over: CLR_TX_OVER, + #[inline(always)] + pub const fn clr_tx_over(&self) -> &CLR_TX_OVER { + &self.clr_tx_over + } #[doc = "0x50 - DesignWare I2C Clear Read Request"] - pub clr_rd_req: CLR_RD_REQ, + #[inline(always)] + pub const fn clr_rd_req(&self) -> &CLR_RD_REQ { + &self.clr_rd_req + } #[doc = "0x54 - DesignWare I2C Clear TX Abort"] - pub clr_tx_abrt: CLR_TX_ABRT, + #[inline(always)] + pub const fn clr_tx_abrt(&self) -> &CLR_TX_ABRT { + &self.clr_tx_abrt + } #[doc = "0x58 - DesignWare I2C Clear RX Done"] - pub clr_rx_done: CLR_RX_DONE, + #[inline(always)] + pub const fn clr_rx_done(&self) -> &CLR_RX_DONE { + &self.clr_rx_done + } #[doc = "0x5c - DesignWare I2C Clear Activity"] - pub clr_activity: CLR_ACTIVITY, + #[inline(always)] + pub const fn clr_activity(&self) -> &CLR_ACTIVITY { + &self.clr_activity + } #[doc = "0x60 - DesignWare I2C Clear Stop DET"] - pub clr_stop_det: CLR_STOP_DET, + #[inline(always)] + pub const fn clr_stop_det(&self) -> &CLR_STOP_DET { + &self.clr_stop_det + } #[doc = "0x64 - DesignWare I2C Clear Start DET"] - pub clr_start_det: CLR_START_DET, + #[inline(always)] + pub const fn clr_start_det(&self) -> &CLR_START_DET { + &self.clr_start_det + } #[doc = "0x68 - DesignWare I2C Clear General Call"] - pub clr_gen_call: CLR_GEN_CALL, + #[inline(always)] + pub const fn clr_gen_call(&self) -> &CLR_GEN_CALL { + &self.clr_gen_call + } #[doc = "0x6c - DesignWare I2C Enable"] - pub enable: ENABLE, + #[inline(always)] + pub const fn enable(&self) -> &ENABLE { + &self.enable + } #[doc = "0x70 - DesignWare I2C Status"] - pub status: STATUS, + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } #[doc = "0x74 - DesignWare I2C TX Failure"] - pub txflr: TXFLR, + #[inline(always)] + pub const fn txflr(&self) -> &TXFLR { + &self.txflr + } #[doc = "0x78 - DesignWare I2C RX Failure"] - pub rxflr: RXFLR, + #[inline(always)] + pub const fn rxflr(&self) -> &RXFLR { + &self.rxflr + } #[doc = "0x7c - DesignWare I2C SDA Hold"] - pub sda_hold: SDA_HOLD, + #[inline(always)] + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold + } #[doc = "0x80 - DesignWare I2C TX Abort Source"] - pub tx_abrt_source: TX_ABRT_SOURCE, - _reserved32: [u8; 0x18], + #[inline(always)] + pub const fn tx_abrt_source(&self) -> &TX_ABRT_SOURCE { + &self.tx_abrt_source + } #[doc = "0x9c - DesignWare I2C Enable Status"] - pub enable_status: ENABLE_STATUS, - _reserved33: [u8; 0x08], + #[inline(always)] + pub const fn enable_status(&self) -> &ENABLE_STATUS { + &self.enable_status + } #[doc = "0xa8 - DesignWare I2C Clear Restart DET"] - pub clr_restart_det: CLR_RESTART_DET, - _reserved34: [u8; 0x48], + #[inline(always)] + pub const fn clr_restart_det(&self) -> &CLR_RESTART_DET { + &self.clr_restart_det + } #[doc = "0xf4 - DesignWare I2C Compatibility Parameter 1"] - pub comp_param_1: COMP_PARAM_1, + #[inline(always)] + pub const fn comp_param_1(&self) -> &COMP_PARAM_1 { + &self.comp_param_1 + } #[doc = "0xf8 - DesignWare I2C Compatibility Version"] - pub comp_version: COMP_VERSION, + #[inline(always)] + pub const fn comp_version(&self) -> &COMP_VERSION { + &self.comp_version + } #[doc = "0xfc - DesignWare I2C Compatibility Type"] - pub comp_type: COMP_TYPE, + #[inline(always)] + pub const fn comp_type(&self) -> &COMP_TYPE { + &self.comp_type + } } -#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`con`] +#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@con`] module"] pub type CON = crate::Reg; #[doc = "DesignWare I2C CON"] pub mod con; -#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tar`] +#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar`] module"] pub type TAR = crate::Reg; #[doc = "DesignWare I2C TAR"] pub mod tar; -#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sar`] +#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`] module"] pub type SAR = crate::Reg; #[doc = "DesignWare I2C SAR"] pub mod sar; -#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`data_cmd`] +#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_cmd`] module"] pub type DATA_CMD = crate::Reg; #[doc = "DesignWare I2C Data Command"] pub mod data_cmd; -#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_hcnt`] +#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_hcnt`] module"] pub type SS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL HCNT"] pub mod ss_scl_hcnt; -#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_lcnt`] +#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_lcnt`] module"] pub type SS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL LCNT"] pub mod ss_scl_lcnt; -#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_hcnt`] +#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_hcnt`] module"] pub type FS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL HCNT"] pub mod fs_scl_hcnt; -#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_lcnt`] +#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_lcnt`] module"] pub type FS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL LCNT"] pub mod fs_scl_lcnt; -#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_hcnt`] +#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_hcnt`] module"] pub type HS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL HCNT"] pub mod hs_scl_hcnt; -#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_lcnt`] +#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_lcnt`] module"] pub type HS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL LCNT"] pub mod hs_scl_lcnt; -#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_stat`] +#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"] pub type INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Interrupt Status"] pub mod intr_stat; -#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_mask`] +#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mask`] module"] pub type INTR_MASK = crate::Reg; #[doc = "DesignWare I2C Interrupt Mask"] pub mod intr_mask; -#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`raw_intr_stat`] +#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"] pub type RAW_INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Raw Interrupt Status"] pub mod raw_intr_stat; -#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rx_tl`] +#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tl`] module"] pub type RX_TL = crate::Reg; #[doc = "DesignWare I2C RX TL"] pub mod rx_tl; -#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_tl`] +#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_tl`] module"] pub type TX_TL = crate::Reg; #[doc = "DesignWare I2C TX TL"] pub mod tx_tl; -#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_intr`] +#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_intr`] module"] pub type CLR_INTR = crate::Reg; #[doc = "DesignWare I2C Clear Interrrupt"] pub mod clr_intr; -#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_under`] +#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_under`] module"] pub type CLR_RX_UNDER = crate::Reg; #[doc = "DesignWare I2C Clear RX Underrun"] pub mod clr_rx_under; -#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_over`] +#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_over`] module"] pub type CLR_RX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear RX Overrun"] pub mod clr_rx_over; -#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_over`] +#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_over`] module"] pub type CLR_TX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear TX Overrun"] pub mod clr_tx_over; -#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rd_req`] +#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rd_req`] module"] pub type CLR_RD_REQ = crate::Reg; #[doc = "DesignWare I2C Clear Read Request"] pub mod clr_rd_req; -#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_abrt`] +#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_abrt`] module"] pub type CLR_TX_ABRT = crate::Reg; #[doc = "DesignWare I2C Clear TX Abort"] pub mod clr_tx_abrt; -#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_done`] +#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_done`] module"] pub type CLR_RX_DONE = crate::Reg; #[doc = "DesignWare I2C Clear RX Done"] pub mod clr_rx_done; -#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_activity`] +#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_activity`] module"] pub type CLR_ACTIVITY = crate::Reg; #[doc = "DesignWare I2C Clear Activity"] pub mod clr_activity; -#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_stop_det`] +#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_stop_det`] module"] pub type CLR_STOP_DET = crate::Reg; #[doc = "DesignWare I2C Clear Stop DET"] pub mod clr_stop_det; -#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_start_det`] +#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_start_det`] module"] pub type CLR_START_DET = crate::Reg; #[doc = "DesignWare I2C Clear Start DET"] pub mod clr_start_det; -#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_gen_call`] +#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_gen_call`] module"] pub type CLR_GEN_CALL = crate::Reg; #[doc = "DesignWare I2C Clear General Call"] pub mod clr_gen_call; -#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable`] +#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] pub type ENABLE = crate::Reg; #[doc = "DesignWare I2C Enable"] pub mod enable; -#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`status`] +#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] pub type STATUS = crate::Reg; #[doc = "DesignWare I2C Status"] pub mod status; -#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txflr`] +#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txflr`] module"] pub type TXFLR = crate::Reg; #[doc = "DesignWare I2C TX Failure"] pub mod txflr; -#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxflr`] +#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxflr`] module"] pub type RXFLR = crate::Reg; #[doc = "DesignWare I2C RX Failure"] pub mod rxflr; -#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sda_hold`] +#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] pub type SDA_HOLD = crate::Reg; #[doc = "DesignWare I2C SDA Hold"] pub mod sda_hold; -#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_abrt_source`] +#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_abrt_source`] module"] pub type TX_ABRT_SOURCE = crate::Reg; #[doc = "DesignWare I2C TX Abort Source"] pub mod tx_abrt_source; -#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_status`] +#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_status`] module"] pub type ENABLE_STATUS = crate::Reg; #[doc = "DesignWare I2C Enable Status"] pub mod enable_status; -#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_restart_det`] +#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_restart_det`] module"] pub type CLR_RESTART_DET = crate::Reg; #[doc = "DesignWare I2C Clear Restart DET"] pub mod clr_restart_det; -#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_param_1`] +#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_param_1`] module"] pub type COMP_PARAM_1 = crate::Reg; #[doc = "DesignWare I2C Compatibility Parameter 1"] pub mod comp_param_1; -#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_version`] +#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_version`] module"] pub type COMP_VERSION = crate::Reg; #[doc = "DesignWare I2C Compatibility Version"] pub mod comp_version; -#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_type`] +#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_type`] module"] pub type COMP_TYPE = crate::Reg; #[doc = "DesignWare I2C Compatibility Type"] diff --git a/jh7110-vf2-12a-pac/src/i2c6/clr_activity.rs b/jh7110-vf2-12a-pac/src/i2c6/clr_activity.rs index d26bb80..1ee2297 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/clr_activity.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/clr_activity.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_activity` reader - clr_activity"] pub type CLR_ACTIVITY_R = crate::FieldReader; #[doc = "Field `clr_activity` writer - clr_activity"] -pub type CLR_ACTIVITY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_ACTIVITY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] #[must_use] - pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { - CLR_ACTIVITY_W::new(self) + pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { + CLR_ACTIVITY_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/clr_gen_call.rs b/jh7110-vf2-12a-pac/src/i2c6/clr_gen_call.rs index a9ea5af..4a7c5ba 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/clr_gen_call.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/clr_gen_call.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_gen_call` reader - clr_gen_call"] pub type CLR_GEN_CALL_R = crate::FieldReader; #[doc = "Field `clr_gen_call` writer - clr_gen_call"] -pub type CLR_GEN_CALL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_GEN_CALL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] #[must_use] - pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { - CLR_GEN_CALL_W::new(self) + pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { + CLR_GEN_CALL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/clr_intr.rs b/jh7110-vf2-12a-pac/src/i2c6/clr_intr.rs index a7daf57..cf57b09 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/clr_intr.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/clr_intr.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/clr_rd_req.rs b/jh7110-vf2-12a-pac/src/i2c6/clr_rd_req.rs index e275da1..4beae9d 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/clr_rd_req.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/clr_rd_req.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rd_req` reader - clr_rd_req"] pub type CLR_RD_REQ_R = crate::FieldReader; #[doc = "Field `clr_rd_req` writer - clr_rd_req"] -pub type CLR_RD_REQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RD_REQ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] #[must_use] - pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { - CLR_RD_REQ_W::new(self) + pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { + CLR_RD_REQ_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/clr_restart_det.rs b/jh7110-vf2-12a-pac/src/i2c6/clr_restart_det.rs index 5be7f5d..88d193c 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/clr_restart_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/clr_restart_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_restart_det` reader - clr_restart_det"] pub type CLR_RESTART_DET_R = crate::FieldReader; #[doc = "Field `clr_restart_det` writer - clr_restart_det"] -pub type CLR_RESTART_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RESTART_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] #[must_use] - pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { - CLR_RESTART_DET_W::new(self) + pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { + CLR_RESTART_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/clr_rx_done.rs b/jh7110-vf2-12a-pac/src/i2c6/clr_rx_done.rs index 02d83c5..7e14a3f 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/clr_rx_done.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/clr_rx_done.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_done` reader - clr_rx_done"] pub type CLR_RX_DONE_R = crate::FieldReader; #[doc = "Field `clr_rx_done` writer - clr_rx_done"] -pub type CLR_RX_DONE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_DONE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] #[must_use] - pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { - CLR_RX_DONE_W::new(self) + pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { + CLR_RX_DONE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/clr_rx_over.rs b/jh7110-vf2-12a-pac/src/i2c6/clr_rx_over.rs index 6d7ff4e..2302921 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/clr_rx_over.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/clr_rx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_over` reader - clr_rx_over"] pub type CLR_RX_OVER_R = crate::FieldReader; #[doc = "Field `clr_rx_over` writer - clr_rx_over"] -pub type CLR_RX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] #[must_use] - pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { - CLR_RX_OVER_W::new(self) + pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { + CLR_RX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/clr_rx_under.rs b/jh7110-vf2-12a-pac/src/i2c6/clr_rx_under.rs index 4a24f7c..35e15bd 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/clr_rx_under.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/clr_rx_under.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_under` reader - clr_rx_under"] pub type CLR_RX_UNDER_R = crate::FieldReader; #[doc = "Field `clr_rx_under` writer - clr_rx_under"] -pub type CLR_RX_UNDER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_UNDER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] #[must_use] - pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { - CLR_RX_UNDER_W::new(self) + pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { + CLR_RX_UNDER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/clr_start_det.rs b/jh7110-vf2-12a-pac/src/i2c6/clr_start_det.rs index cebc4bc..2314f65 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/clr_start_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/clr_start_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_start_det` reader - clr_start_det"] pub type CLR_START_DET_R = crate::FieldReader; #[doc = "Field `clr_start_det` writer - clr_start_det"] -pub type CLR_START_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_START_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] #[must_use] - pub fn clr_start_det(&mut self) -> CLR_START_DET_W { - CLR_START_DET_W::new(self) + pub fn clr_start_det(&mut self) -> CLR_START_DET_W { + CLR_START_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/clr_stop_det.rs b/jh7110-vf2-12a-pac/src/i2c6/clr_stop_det.rs index 44f39f3..49abcac 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/clr_stop_det.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/clr_stop_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_stop_det` reader - clr_stop_det"] pub type CLR_STOP_DET_R = crate::FieldReader; #[doc = "Field `clr_stop_det` writer - clr_stop_det"] -pub type CLR_STOP_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_STOP_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] #[must_use] - pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { - CLR_STOP_DET_W::new(self) + pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { + CLR_STOP_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/clr_tx_abrt.rs b/jh7110-vf2-12a-pac/src/i2c6/clr_tx_abrt.rs index 6ac441c..3bc0f6f 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/clr_tx_abrt.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/clr_tx_abrt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_abrt` reader - clr_tx_abrt"] pub type CLR_TX_ABRT_R = crate::FieldReader; #[doc = "Field `clr_tx_abrt` writer - clr_tx_abrt"] -pub type CLR_TX_ABRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_ABRT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] #[must_use] - pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { - CLR_TX_ABRT_W::new(self) + pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { + CLR_TX_ABRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/clr_tx_over.rs b/jh7110-vf2-12a-pac/src/i2c6/clr_tx_over.rs index 2b32b52..a5b6933 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/clr_tx_over.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/clr_tx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_over` reader - clr_tx_over"] pub type CLR_TX_OVER_R = crate::FieldReader; #[doc = "Field `clr_tx_over` writer - clr_tx_over"] -pub type CLR_TX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] #[must_use] - pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { - CLR_TX_OVER_W::new(self) + pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { + CLR_TX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/comp_param_1.rs b/jh7110-vf2-12a-pac/src/i2c6/comp_param_1.rs index 24a22e1..95c5002 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/comp_param_1.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/comp_param_1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/comp_type.rs b/jh7110-vf2-12a-pac/src/i2c6/comp_type.rs index ac916b5..1336c43 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/comp_type.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/comp_type.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/comp_version.rs b/jh7110-vf2-12a-pac/src/i2c6/comp_version.rs index 4be31fa..e8309c8 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/comp_version.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/comp_version.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/con.rs b/jh7110-vf2-12a-pac/src/i2c6/con.rs index 873c534..28aa865 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/con.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/con.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `master` reader - I2C Master Connection - 0: Slave, 1: Master"] pub type MASTER_R = crate::BitReader; #[doc = "Field `master` writer - I2C Master Connection - 0: Slave, 1: Master"] -pub type MASTER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `speed` reader - I2C Speed - 01: Standard, 10: Fast, 11: High"] pub type SPEED_R = crate::FieldReader; #[doc = "Field `speed` writer - I2C Speed - 01: Standard, 10: Fast, 11: High"] -pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `slave_10bitaddr` reader - I2C Slave 10-bit Address - 0: False, 1: True"] pub type SLAVE_10BITADDR_R = crate::BitReader; #[doc = "Field `slave_10bitaddr` writer - I2C Slave 10-bit Address - 0: False, 1: True"] -pub type SLAVE_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_10bitaddr` reader - I2C Master 10-bit Address - 0: False, 1: True"] pub type MASTER_10BITADDR_R = crate::BitReader; #[doc = "Field `master_10bitaddr` writer - I2C Master 10-bit Address - 0: False, 1: True"] -pub type MASTER_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_en` reader - I2C Restart Enable - 0: False, 1: True"] pub type RESTART_EN_R = crate::BitReader; #[doc = "Field `restart_en` writer - I2C Restart Enable - 0: False, 1: True"] -pub type RESTART_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_disable` reader - I2C Slave Disable - 0: False, 1: True"] pub type SLAVE_DISABLE_R = crate::BitReader; #[doc = "Field `slave_disable` writer - I2C Slave Disable - 0: False, 1: True"] -pub type SLAVE_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det_ifaddressed` reader - I2C Stop DET If Addressed - 0: False, 1: True"] pub type STOP_DET_IFADDRESSED_R = crate::BitReader; #[doc = "Field `stop_det_ifaddressed` writer - I2C Stop DET If Addressed - 0: False, 1: True"] -pub type STOP_DET_IFADDRESSED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty_ctrl` reader - I2C TX Empty Control - 0: False, 1: True"] pub type TX_EMPTY_CTRL_R = crate::BitReader; #[doc = "Field `tx_empty_ctrl` writer - I2C TX Empty Control - 0: False, 1: True"] -pub type TX_EMPTY_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_fifo_full_hld_ctrl` reader - I2C RX FIFO Full Hold Control - 0: False, 1: True"] pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; #[doc = "Field `rx_fifo_full_hld_ctrl` writer - I2C RX FIFO Full Hold Control - 0: False, 1: True"] -pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bus_clear_ctrl` reader - I2C Bus Clear Control - 0: False, 1: True"] pub type BUS_CLEAR_CTRL_R = crate::BitReader; #[doc = "Field `bus_clear_ctrl` writer - I2C Bus Clear Control - 0: False, 1: True"] -pub type BUS_CLEAR_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BUS_CLEAR_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] #[must_use] - pub fn master(&mut self) -> MASTER_W { - MASTER_W::new(self) + pub fn master(&mut self) -> MASTER_W { + MASTER_W::new(self, 0) } #[doc = "Bits 1:2 - I2C Speed - 01: Standard, 10: Fast, 11: High"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W { - SPEED_W::new(self) + pub fn speed(&mut self) -> SPEED_W { + SPEED_W::new(self, 1) } #[doc = "Bit 3 - I2C Slave 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { - SLAVE_10BITADDR_W::new(self) + pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { + SLAVE_10BITADDR_W::new(self, 3) } #[doc = "Bit 4 - I2C Master 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { - MASTER_10BITADDR_W::new(self) + pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { + MASTER_10BITADDR_W::new(self, 4) } #[doc = "Bit 5 - I2C Restart Enable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn restart_en(&mut self) -> RESTART_EN_W { - RESTART_EN_W::new(self) + pub fn restart_en(&mut self) -> RESTART_EN_W { + RESTART_EN_W::new(self, 5) } #[doc = "Bit 6 - I2C Slave Disable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { - SLAVE_DISABLE_W::new(self) + pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { + SLAVE_DISABLE_W::new(self, 6) } #[doc = "Bit 7 - I2C Stop DET If Addressed - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { - STOP_DET_IFADDRESSED_W::new(self) + pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { + STOP_DET_IFADDRESSED_W::new(self, 7) } #[doc = "Bit 8 - I2C TX Empty Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { - TX_EMPTY_CTRL_W::new(self) + pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { + TX_EMPTY_CTRL_W::new(self, 8) } #[doc = "Bit 9 - I2C RX FIFO Full Hold Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { - RX_FIFO_FULL_HLD_CTRL_W::new(self) + pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { + RX_FIFO_FULL_HLD_CTRL_W::new(self, 9) } #[doc = "Bit 11 - I2C Bus Clear Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { - BUS_CLEAR_CTRL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { + BUS_CLEAR_CTRL_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/data_cmd.rs b/jh7110-vf2-12a-pac/src/i2c6/data_cmd.rs index cf36408..2b320d4 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/data_cmd.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/data_cmd.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `dat` reader - Data Command Data Byte"] pub type DAT_R = crate::FieldReader; #[doc = "Field `dat` writer - Data Command Data Byte"] -pub type DAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `read` reader - Data Command READ Bit - 0: Write, 1: Read"] pub type READ_R = crate::BitReader; #[doc = "Field `read` writer - Data Command READ Bit - 0: Write, 1: Read"] -pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop` reader - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart` reader - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] pub type RESTART_R = crate::BitReader; #[doc = "Field `restart` writer - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] -pub type RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `first_data_byte` reader - Data Command First Data Byte - 0: False, 1: True"] pub type FIRST_DATA_BYTE_R = crate::BitReader; #[doc = "Field `first_data_byte` writer - Data Command First Data Byte - 0: False, 1: True"] -pub type FIRST_DATA_BYTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIRST_DATA_BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] #[must_use] - pub fn dat(&mut self) -> DAT_W { - DAT_W::new(self) + pub fn dat(&mut self) -> DAT_W { + DAT_W::new(self, 0) } #[doc = "Bit 8 - Data Command READ Bit - 0: Write, 1: Read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W { - READ_W::new(self) + pub fn read(&mut self) -> READ_W { + READ_W::new(self, 8) } #[doc = "Bit 9 - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 9) } #[doc = "Bit 10 - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] #[inline(always)] #[must_use] - pub fn restart(&mut self) -> RESTART_W { - RESTART_W::new(self) + pub fn restart(&mut self) -> RESTART_W { + RESTART_W::new(self, 10) } #[doc = "Bit 11 - Data Command First Data Byte - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { - FIRST_DATA_BYTE_W::new(self) + pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { + FIRST_DATA_BYTE_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/enable.rs b/jh7110-vf2-12a-pac/src/i2c6/enable.rs index c5ca9d7..3629f6b 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/enable.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/enable.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `abort` reader - abort"] pub type ABORT_R = crate::BitReader; #[doc = "Field `abort` writer - abort"] -pub type ABORT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 1 - abort"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 1 - abort"] #[inline(always)] #[must_use] - pub fn abort(&mut self) -> ABORT_W { - ABORT_W::new(self) + pub fn abort(&mut self) -> ABORT_W { + ABORT_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/enable_status.rs b/jh7110-vf2-12a-pac/src/i2c6/enable_status.rs index 2c102a6..8b9b7d3 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/enable_status.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/enable_status.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `activity` reader - activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tfe` reader - tfe"] pub type TFE_R = crate::BitReader; #[doc = "Field `tfe` writer - tfe"] -pub type TFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TFE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfne` reader - rfne"] pub type RFNE_R = crate::BitReader; #[doc = "Field `rfne` writer - rfne"] -pub type RFNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFNE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_activity` reader - master_activity"] pub type MASTER_ACTIVITY_R = crate::BitReader; #[doc = "Field `master_activity` writer - master_activity"] -pub type MASTER_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_activity` reader - slave_activity"] pub type SLAVE_ACTIVITY_R = crate::BitReader; #[doc = "Field `slave_activity` writer - slave_activity"] -pub type SLAVE_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - activity"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 0) } #[doc = "Bit 2 - tfe"] #[inline(always)] #[must_use] - pub fn tfe(&mut self) -> TFE_W { - TFE_W::new(self) + pub fn tfe(&mut self) -> TFE_W { + TFE_W::new(self, 2) } #[doc = "Bit 3 - rfne"] #[inline(always)] #[must_use] - pub fn rfne(&mut self) -> RFNE_W { - RFNE_W::new(self) + pub fn rfne(&mut self) -> RFNE_W { + RFNE_W::new(self, 3) } #[doc = "Bit 5 - master_activity"] #[inline(always)] #[must_use] - pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { - MASTER_ACTIVITY_W::new(self) + pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { + MASTER_ACTIVITY_W::new(self, 5) } #[doc = "Bit 6 - slave_activity"] #[inline(always)] #[must_use] - pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { - SLAVE_ACTIVITY_W::new(self) + pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { + SLAVE_ACTIVITY_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/fs_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c6/fs_scl_hcnt.rs index 9a9fd72..8a4f6d1 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/fs_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/fs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_hcnt` reader - fs_scl_hcnt"] pub type FS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_hcnt` writer - fs_scl_hcnt"] -pub type FS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { - FS_SCL_HCNT_W::new(self) + pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { + FS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/fs_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c6/fs_scl_lcnt.rs index 5e41cd1..4b4dd6b 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/fs_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/fs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_lcnt` reader - fs_scl_lcnt"] pub type FS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_lcnt` writer - fs_scl_lcnt"] -pub type FS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { - FS_SCL_LCNT_W::new(self) + pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { + FS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/hs_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c6/hs_scl_hcnt.rs index fba7f13..9b0a71c 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/hs_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/hs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_hcnt` reader - hs_scl_hcnt"] pub type HS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_hcnt` writer - hs_scl_hcnt"] -pub type HS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { - HS_SCL_HCNT_W::new(self) + pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { + HS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/hs_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c6/hs_scl_lcnt.rs index 9fca7a5..a715282 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/hs_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/hs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_lcnt` reader - hs_scl_lcnt"] pub type HS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_lcnt` writer - hs_scl_lcnt"] -pub type HS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { - HS_SCL_LCNT_W::new(self) + pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { + HS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/intr_mask.rs b/jh7110-vf2-12a-pac/src/i2c6/intr_mask.rs index 20a334f..769b629 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/intr_mask.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/intr_mask.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/intr_stat.rs b/jh7110-vf2-12a-pac/src/i2c6/intr_stat.rs index 2c2ba34..f376c26 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/intr_stat.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/raw_intr_stat.rs b/jh7110-vf2-12a-pac/src/i2c6/raw_intr_stat.rs index af97981..dd5e8e0 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/raw_intr_stat.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/raw_intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/rx_tl.rs b/jh7110-vf2-12a-pac/src/i2c6/rx_tl.rs index 1455a10..f3f39f4 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/rx_tl.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/rx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rx_tl` reader - rx_tl"] pub type RX_TL_R = crate::FieldReader; #[doc = "Field `rx_tl` writer - rx_tl"] -pub type RX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] #[must_use] - pub fn rx_tl(&mut self) -> RX_TL_W { - RX_TL_W::new(self) + pub fn rx_tl(&mut self) -> RX_TL_W { + RX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/rxflr.rs b/jh7110-vf2-12a-pac/src/i2c6/rxflr.rs index 910e254..4dccf5e 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/rxflr.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/rxflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rxflr` reader - rxflr"] pub type RXFLR_R = crate::FieldReader; #[doc = "Field `rxflr` writer - rxflr"] -pub type RXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] #[must_use] - pub fn rxflr(&mut self) -> RXFLR_W { - RXFLR_W::new(self) + pub fn rxflr(&mut self) -> RXFLR_W { + RXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/sar.rs b/jh7110-vf2-12a-pac/src/i2c6/sar.rs index d272e7a..1af6273 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/sar.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/sar.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Slave address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Slave address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Slave address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Slave address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; impl R { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Slave address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/sda_hold.rs b/jh7110-vf2-12a-pac/src/i2c6/sda_hold.rs index 82ceac5..d5d7512 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/sda_hold.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/sda_hold.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sda_hold` reader - sda_hold"] pub type SDA_HOLD_R = crate::FieldReader; #[doc = "Field `sda_hold` writer - sda_hold"] -pub type SDA_HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SDA_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] #[must_use] - pub fn sda_hold(&mut self) -> SDA_HOLD_W { - SDA_HOLD_W::new(self) + pub fn sda_hold(&mut self) -> SDA_HOLD_W { + SDA_HOLD_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/ss_scl_hcnt.rs b/jh7110-vf2-12a-pac/src/i2c6/ss_scl_hcnt.rs index 33736c7..77d7ea0 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/ss_scl_hcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/ss_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_hcnt` reader - ss_scl_hcnt"] pub type SS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_hcnt` writer - ss_scl_hcnt"] -pub type SS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { - SS_SCL_HCNT_W::new(self) + pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { + SS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/ss_scl_lcnt.rs b/jh7110-vf2-12a-pac/src/i2c6/ss_scl_lcnt.rs index ce22b5d..8208747 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/ss_scl_lcnt.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/ss_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_lcnt` reader - ss_scl_lcnt"] pub type SS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_lcnt` writer - ss_scl_lcnt"] -pub type SS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { - SS_SCL_LCNT_W::new(self) + pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { + SS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/status.rs b/jh7110-vf2-12a-pac/src/i2c6/status.rs index 9489e49..1b7ab67 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/status.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/tar.rs b/jh7110-vf2-12a-pac/src/i2c6/tar.rs index 9fedc71..3044a8c 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/tar.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/tar.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Target address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Target address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Target address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Target address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; #[doc = "Field `mode` reader - Target addressing mode - 0: 7-bit, 1: 10-bit"] pub type MODE_R = crate::BitReader; #[doc = "Field `mode` writer - Target addressing mode - 0: 7-bit, 1: 10-bit"] -pub type MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Target address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } #[doc = "Bit 12 - Target addressing mode - 0: 7-bit, 1: 10-bit"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W { - MODE_W::new(self) + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 12) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/tx_abrt_source.rs b/jh7110-vf2-12a-pac/src/i2c6/tx_abrt_source.rs index 6f31813..c4fdf1a 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/tx_abrt_source.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/tx_abrt_source.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/tx_tl.rs b/jh7110-vf2-12a-pac/src/i2c6/tx_tl.rs index 84a1734..b0e6c64 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/tx_tl.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/tx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `tx_tl` reader - tx_tl"] pub type TX_TL_R = crate::FieldReader; #[doc = "Field `tx_tl` writer - tx_tl"] -pub type TX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] #[must_use] - pub fn tx_tl(&mut self) -> TX_TL_W { - TX_TL_W::new(self) + pub fn tx_tl(&mut self) -> TX_TL_W { + TX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/i2c6/txflr.rs b/jh7110-vf2-12a-pac/src/i2c6/txflr.rs index b8e5fdd..5ca351d 100644 --- a/jh7110-vf2-12a-pac/src/i2c6/txflr.rs +++ b/jh7110-vf2-12a-pac/src/i2c6/txflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `txflr` reader - txflr"] pub type TXFLR_R = crate::FieldReader; #[doc = "Field `txflr` writer - txflr"] -pub type TXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - txflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - txflr"] #[inline(always)] #[must_use] - pub fn txflr(&mut self) -> TXFLR_W { - TXFLR_W::new(self) + pub fn txflr(&mut self) -> TXFLR_W { + TXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/lib.rs b/jh7110-vf2-12a-pac/src/lib.rs index a732104..53fa8c7 100644 --- a/jh7110-vf2-12a-pac/src/lib.rs +++ b/jh7110-vf2-12a-pac/src/lib.rs @@ -1,19 +1,5 @@ -#![doc = "Peripheral access API for STARFIVE VISIONFIVE 2 V1.2A microcontrollers (generated using svd2rust v0.30.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] -svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.30.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] -#![deny(dead_code)] -#![deny(improper_ctypes)] -#![deny(missing_docs)] -#![deny(no_mangle_generic_items)] -#![deny(non_shorthand_field_patterns)] -#![deny(overflowing_literals)] -#![deny(path_statements)] -#![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] -#![deny(unconditional_recursion)] -#![deny(unused_allocation)] -#![deny(unused_comparisons)] -#![deny(unused_parens)] -#![deny(while_true)] +#![doc = "Peripheral access API for STARFIVE VISIONFIVE 2 V1.2A microcontrollers (generated using svd2rust v0.31.2 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.31.2/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] #![allow(non_camel_case_types)] #![allow(non_snake_case)] #![no_std] @@ -26,6 +12,7 @@ pub mod generic; #[cfg(feature = "rt")] extern "C" {} #[doc(hidden)] +#[repr(C)] pub union Vector { pub _handler: unsafe extern "C" fn(), pub _reserved: usize, diff --git a/jh7110-vf2-12a-pac/src/plic.rs b/jh7110-vf2-12a-pac/src/plic.rs index f319cf6..ee9067d 100644 --- a/jh7110-vf2-12a-pac/src/plic.rs +++ b/jh7110-vf2-12a-pac/src/plic.rs @@ -2,1246 +2,1952 @@ #[repr(C)] pub struct RegisterBlock { _reserved0: [u8; 0x04], + priority_1: PRIORITY_1, + priority_2: PRIORITY_2, + priority_3: PRIORITY_3, + priority_4: PRIORITY_4, + priority_5: PRIORITY_5, + priority_6: PRIORITY_6, + priority_7: PRIORITY_7, + priority_8: PRIORITY_8, + priority_9: PRIORITY_9, + priority_10: PRIORITY_10, + priority_11: PRIORITY_11, + priority_12: PRIORITY_12, + priority_13: PRIORITY_13, + priority_14: PRIORITY_14, + priority_15: PRIORITY_15, + priority_16: PRIORITY_16, + priority_17: PRIORITY_17, + priority_18: PRIORITY_18, + priority_19: PRIORITY_19, + priority_20: PRIORITY_20, + priority_21: PRIORITY_21, + priority_22: PRIORITY_22, + priority_23: PRIORITY_23, + priority_24: PRIORITY_24, + priority_25: PRIORITY_25, + priority_26: PRIORITY_26, + priority_27: PRIORITY_27, + priority_28: PRIORITY_28, + priority_29: PRIORITY_29, + priority_30: PRIORITY_30, + priority_31: PRIORITY_31, + priority_32: PRIORITY_32, + priority_33: PRIORITY_33, + priority_34: PRIORITY_34, + priority_35: PRIORITY_35, + priority_36: PRIORITY_36, + priority_37: PRIORITY_37, + priority_38: PRIORITY_38, + priority_39: PRIORITY_39, + priority_40: PRIORITY_40, + priority_41: PRIORITY_41, + priority_42: PRIORITY_42, + priority_43: PRIORITY_43, + priority_44: PRIORITY_44, + priority_45: PRIORITY_45, + priority_46: PRIORITY_46, + priority_47: PRIORITY_47, + priority_48: PRIORITY_48, + priority_49: PRIORITY_49, + priority_50: PRIORITY_50, + priority_51: PRIORITY_51, + priority_52: PRIORITY_52, + priority_53: PRIORITY_53, + priority_54: PRIORITY_54, + priority_55: PRIORITY_55, + priority_56: PRIORITY_56, + priority_57: PRIORITY_57, + priority_58: PRIORITY_58, + priority_59: PRIORITY_59, + priority_60: PRIORITY_60, + priority_61: PRIORITY_61, + priority_62: PRIORITY_62, + priority_63: PRIORITY_63, + priority_64: PRIORITY_64, + priority_65: PRIORITY_65, + priority_66: PRIORITY_66, + priority_67: PRIORITY_67, + priority_68: PRIORITY_68, + priority_69: PRIORITY_69, + priority_70: PRIORITY_70, + priority_71: PRIORITY_71, + priority_72: PRIORITY_72, + priority_73: PRIORITY_73, + priority_74: PRIORITY_74, + priority_75: PRIORITY_75, + priority_76: PRIORITY_76, + priority_77: PRIORITY_77, + priority_78: PRIORITY_78, + priority_79: PRIORITY_79, + priority_80: PRIORITY_80, + priority_81: PRIORITY_81, + priority_82: PRIORITY_82, + priority_83: PRIORITY_83, + priority_84: PRIORITY_84, + priority_85: PRIORITY_85, + priority_86: PRIORITY_86, + priority_87: PRIORITY_87, + priority_88: PRIORITY_88, + priority_89: PRIORITY_89, + priority_90: PRIORITY_90, + priority_91: PRIORITY_91, + priority_92: PRIORITY_92, + priority_93: PRIORITY_93, + priority_94: PRIORITY_94, + priority_95: PRIORITY_95, + priority_96: PRIORITY_96, + priority_97: PRIORITY_97, + priority_98: PRIORITY_98, + priority_99: PRIORITY_99, + priority_100: PRIORITY_100, + priority_101: PRIORITY_101, + priority_102: PRIORITY_102, + priority_103: PRIORITY_103, + priority_104: PRIORITY_104, + priority_105: PRIORITY_105, + priority_106: PRIORITY_106, + priority_107: PRIORITY_107, + priority_108: PRIORITY_108, + priority_109: PRIORITY_109, + priority_110: PRIORITY_110, + priority_111: PRIORITY_111, + priority_112: PRIORITY_112, + priority_113: PRIORITY_113, + priority_114: PRIORITY_114, + priority_115: PRIORITY_115, + priority_116: PRIORITY_116, + priority_117: PRIORITY_117, + priority_118: PRIORITY_118, + priority_119: PRIORITY_119, + priority_120: PRIORITY_120, + priority_121: PRIORITY_121, + priority_122: PRIORITY_122, + priority_123: PRIORITY_123, + priority_124: PRIORITY_124, + priority_125: PRIORITY_125, + priority_126: PRIORITY_126, + priority_127: PRIORITY_127, + priority_128: PRIORITY_128, + priority_129: PRIORITY_129, + priority_130: PRIORITY_130, + priority_131: PRIORITY_131, + priority_132: PRIORITY_132, + priority_133: PRIORITY_133, + priority_134: PRIORITY_134, + priority_135: PRIORITY_135, + priority_136: PRIORITY_136, + _reserved136: [u8; 0x0ddc], + pending_0: PENDING_0, + pending_1: PENDING_1, + pending_2: PENDING_2, + pending_3: PENDING_3, + pending_4: PENDING_4, + _reserved141: [u8; 0x0fec], + enable_0_0: ENABLE_0_0, + enable_1_0: ENABLE_1_0, + enable_2_0: ENABLE_2_0, + enable_3_0: ENABLE_3_0, + enable_4_0: ENABLE_4_0, + _reserved146: [u8; 0x6c], + enable_0_1: ENABLE_0_1, + enable_1_1: ENABLE_1_1, + enable_2_1: ENABLE_2_1, + enable_3_1: ENABLE_3_1, + enable_4_1: ENABLE_4_1, + _reserved151: [u8; 0x6c], + enable_0_2: ENABLE_0_2, + enable_1_2: ENABLE_1_2, + enable_2_2: ENABLE_2_2, + enable_3_2: ENABLE_3_2, + enable_4_2: ENABLE_4_2, + _reserved156: [u8; 0x6c], + enable_0_3: ENABLE_0_3, + enable_1_3: ENABLE_1_3, + enable_2_3: ENABLE_2_3, + enable_3_3: ENABLE_3_3, + enable_4_3: ENABLE_4_3, + _reserved161: [u8; 0x6c], + enable_0_4: ENABLE_0_4, + enable_1_4: ENABLE_1_4, + enable_2_4: ENABLE_2_4, + enable_3_4: ENABLE_3_4, + enable_4_4: ENABLE_4_4, + _reserved166: [u8; 0x001f_ddec], + threshold_0: THRESHOLD_0, + claimplete_0: CLAIMPLETE_0, + _reserved168: [u8; 0x0ff8], + threshold_1: THRESHOLD_1, + claimplete_1: CLAIMPLETE_1, + _reserved170: [u8; 0x0ff8], + threshold_2: THRESHOLD_2, + claimplete_2: CLAIMPLETE_2, + _reserved172: [u8; 0x0ff8], + threshold_3: THRESHOLD_3, + claimplete_3: CLAIMPLETE_3, + _reserved174: [u8; 0x0ff8], + threshold_4: THRESHOLD_4, + claimplete_4: CLAIMPLETE_4, +} +impl RegisterBlock { #[doc = "0x04 - PRIORITY Register for interrupt id 1"] - pub priority_1: PRIORITY_1, + #[inline(always)] + pub const fn priority_1(&self) -> &PRIORITY_1 { + &self.priority_1 + } #[doc = "0x08 - PRIORITY Register for interrupt id 2"] - pub priority_2: PRIORITY_2, + #[inline(always)] + pub const fn priority_2(&self) -> &PRIORITY_2 { + &self.priority_2 + } #[doc = "0x0c - PRIORITY Register for interrupt id 3"] - pub priority_3: PRIORITY_3, + #[inline(always)] + pub const fn priority_3(&self) -> &PRIORITY_3 { + &self.priority_3 + } #[doc = "0x10 - PRIORITY Register for interrupt id 4"] - pub priority_4: PRIORITY_4, + #[inline(always)] + pub const fn priority_4(&self) -> &PRIORITY_4 { + &self.priority_4 + } #[doc = "0x14 - PRIORITY Register for interrupt id 5"] - pub priority_5: PRIORITY_5, + #[inline(always)] + pub const fn priority_5(&self) -> &PRIORITY_5 { + &self.priority_5 + } #[doc = "0x18 - PRIORITY Register for interrupt id 6"] - pub priority_6: PRIORITY_6, + #[inline(always)] + pub const fn priority_6(&self) -> &PRIORITY_6 { + &self.priority_6 + } #[doc = "0x1c - PRIORITY Register for interrupt id 7"] - pub priority_7: PRIORITY_7, + #[inline(always)] + pub const fn priority_7(&self) -> &PRIORITY_7 { + &self.priority_7 + } #[doc = "0x20 - PRIORITY Register for interrupt id 8"] - pub priority_8: PRIORITY_8, + #[inline(always)] + pub const fn priority_8(&self) -> &PRIORITY_8 { + &self.priority_8 + } #[doc = "0x24 - PRIORITY Register for interrupt id 9"] - pub priority_9: PRIORITY_9, + #[inline(always)] + pub const fn priority_9(&self) -> &PRIORITY_9 { + &self.priority_9 + } #[doc = "0x28 - PRIORITY Register for interrupt id 10"] - pub priority_10: PRIORITY_10, + #[inline(always)] + pub const fn priority_10(&self) -> &PRIORITY_10 { + &self.priority_10 + } #[doc = "0x2c - PRIORITY Register for interrupt id 11"] - pub priority_11: PRIORITY_11, + #[inline(always)] + pub const fn priority_11(&self) -> &PRIORITY_11 { + &self.priority_11 + } #[doc = "0x30 - PRIORITY Register for interrupt id 12"] - pub priority_12: PRIORITY_12, + #[inline(always)] + pub const fn priority_12(&self) -> &PRIORITY_12 { + &self.priority_12 + } #[doc = "0x34 - PRIORITY Register for interrupt id 13"] - pub priority_13: PRIORITY_13, + #[inline(always)] + pub const fn priority_13(&self) -> &PRIORITY_13 { + &self.priority_13 + } #[doc = "0x38 - PRIORITY Register for interrupt id 14"] - pub priority_14: PRIORITY_14, + #[inline(always)] + pub const fn priority_14(&self) -> &PRIORITY_14 { + &self.priority_14 + } #[doc = "0x3c - PRIORITY Register for interrupt id 15"] - pub priority_15: PRIORITY_15, + #[inline(always)] + pub const fn priority_15(&self) -> &PRIORITY_15 { + &self.priority_15 + } #[doc = "0x40 - PRIORITY Register for interrupt id 16"] - pub priority_16: PRIORITY_16, + #[inline(always)] + pub const fn priority_16(&self) -> &PRIORITY_16 { + &self.priority_16 + } #[doc = "0x44 - PRIORITY Register for interrupt id 17"] - pub priority_17: PRIORITY_17, + #[inline(always)] + pub const fn priority_17(&self) -> &PRIORITY_17 { + &self.priority_17 + } #[doc = "0x48 - PRIORITY Register for interrupt id 18"] - pub priority_18: PRIORITY_18, + #[inline(always)] + pub const fn priority_18(&self) -> &PRIORITY_18 { + &self.priority_18 + } #[doc = "0x4c - PRIORITY Register for interrupt id 19"] - pub priority_19: PRIORITY_19, + #[inline(always)] + pub const fn priority_19(&self) -> &PRIORITY_19 { + &self.priority_19 + } #[doc = "0x50 - PRIORITY Register for interrupt id 20"] - pub priority_20: PRIORITY_20, + #[inline(always)] + pub const fn priority_20(&self) -> &PRIORITY_20 { + &self.priority_20 + } #[doc = "0x54 - PRIORITY Register for interrupt id 21"] - pub priority_21: PRIORITY_21, + #[inline(always)] + pub const fn priority_21(&self) -> &PRIORITY_21 { + &self.priority_21 + } #[doc = "0x58 - PRIORITY Register for interrupt id 22"] - pub priority_22: PRIORITY_22, + #[inline(always)] + pub const fn priority_22(&self) -> &PRIORITY_22 { + &self.priority_22 + } #[doc = "0x5c - PRIORITY Register for interrupt id 23"] - pub priority_23: PRIORITY_23, + #[inline(always)] + pub const fn priority_23(&self) -> &PRIORITY_23 { + &self.priority_23 + } #[doc = "0x60 - PRIORITY Register for interrupt id 24"] - pub priority_24: PRIORITY_24, + #[inline(always)] + pub const fn priority_24(&self) -> &PRIORITY_24 { + &self.priority_24 + } #[doc = "0x64 - PRIORITY Register for interrupt id 25"] - pub priority_25: PRIORITY_25, + #[inline(always)] + pub const fn priority_25(&self) -> &PRIORITY_25 { + &self.priority_25 + } #[doc = "0x68 - PRIORITY Register for interrupt id 26"] - pub priority_26: PRIORITY_26, + #[inline(always)] + pub const fn priority_26(&self) -> &PRIORITY_26 { + &self.priority_26 + } #[doc = "0x6c - PRIORITY Register for interrupt id 27"] - pub priority_27: PRIORITY_27, + #[inline(always)] + pub const fn priority_27(&self) -> &PRIORITY_27 { + &self.priority_27 + } #[doc = "0x70 - PRIORITY Register for interrupt id 28"] - pub priority_28: PRIORITY_28, + #[inline(always)] + pub const fn priority_28(&self) -> &PRIORITY_28 { + &self.priority_28 + } #[doc = "0x74 - PRIORITY Register for interrupt id 29"] - pub priority_29: PRIORITY_29, + #[inline(always)] + pub const fn priority_29(&self) -> &PRIORITY_29 { + &self.priority_29 + } #[doc = "0x78 - PRIORITY Register for interrupt id 30"] - pub priority_30: PRIORITY_30, + #[inline(always)] + pub const fn priority_30(&self) -> &PRIORITY_30 { + &self.priority_30 + } #[doc = "0x7c - PRIORITY Register for interrupt id 31"] - pub priority_31: PRIORITY_31, + #[inline(always)] + pub const fn priority_31(&self) -> &PRIORITY_31 { + &self.priority_31 + } #[doc = "0x80 - PRIORITY Register for interrupt id 32"] - pub priority_32: PRIORITY_32, + #[inline(always)] + pub const fn priority_32(&self) -> &PRIORITY_32 { + &self.priority_32 + } #[doc = "0x84 - PRIORITY Register for interrupt id 33"] - pub priority_33: PRIORITY_33, + #[inline(always)] + pub const fn priority_33(&self) -> &PRIORITY_33 { + &self.priority_33 + } #[doc = "0x88 - PRIORITY Register for interrupt id 34"] - pub priority_34: PRIORITY_34, + #[inline(always)] + pub const fn priority_34(&self) -> &PRIORITY_34 { + &self.priority_34 + } #[doc = "0x8c - PRIORITY Register for interrupt id 35"] - pub priority_35: PRIORITY_35, + #[inline(always)] + pub const fn priority_35(&self) -> &PRIORITY_35 { + &self.priority_35 + } #[doc = "0x90 - PRIORITY Register for interrupt id 36"] - pub priority_36: PRIORITY_36, + #[inline(always)] + pub const fn priority_36(&self) -> &PRIORITY_36 { + &self.priority_36 + } #[doc = "0x94 - PRIORITY Register for interrupt id 37"] - pub priority_37: PRIORITY_37, + #[inline(always)] + pub const fn priority_37(&self) -> &PRIORITY_37 { + &self.priority_37 + } #[doc = "0x98 - PRIORITY Register for interrupt id 38"] - pub priority_38: PRIORITY_38, + #[inline(always)] + pub const fn priority_38(&self) -> &PRIORITY_38 { + &self.priority_38 + } #[doc = "0x9c - PRIORITY Register for interrupt id 39"] - pub priority_39: PRIORITY_39, + #[inline(always)] + pub const fn priority_39(&self) -> &PRIORITY_39 { + &self.priority_39 + } #[doc = "0xa0 - PRIORITY Register for interrupt id 40"] - pub priority_40: PRIORITY_40, + #[inline(always)] + pub const fn priority_40(&self) -> &PRIORITY_40 { + &self.priority_40 + } #[doc = "0xa4 - PRIORITY Register for interrupt id 41"] - pub priority_41: PRIORITY_41, + #[inline(always)] + pub const fn priority_41(&self) -> &PRIORITY_41 { + &self.priority_41 + } #[doc = "0xa8 - PRIORITY Register for interrupt id 42"] - pub priority_42: PRIORITY_42, + #[inline(always)] + pub const fn priority_42(&self) -> &PRIORITY_42 { + &self.priority_42 + } #[doc = "0xac - PRIORITY Register for interrupt id 43"] - pub priority_43: PRIORITY_43, + #[inline(always)] + pub const fn priority_43(&self) -> &PRIORITY_43 { + &self.priority_43 + } #[doc = "0xb0 - PRIORITY Register for interrupt id 44"] - pub priority_44: PRIORITY_44, + #[inline(always)] + pub const fn priority_44(&self) -> &PRIORITY_44 { + &self.priority_44 + } #[doc = "0xb4 - PRIORITY Register for interrupt id 45"] - pub priority_45: PRIORITY_45, + #[inline(always)] + pub const fn priority_45(&self) -> &PRIORITY_45 { + &self.priority_45 + } #[doc = "0xb8 - PRIORITY Register for interrupt id 46"] - pub priority_46: PRIORITY_46, + #[inline(always)] + pub const fn priority_46(&self) -> &PRIORITY_46 { + &self.priority_46 + } #[doc = "0xbc - PRIORITY Register for interrupt id 47"] - pub priority_47: PRIORITY_47, + #[inline(always)] + pub const fn priority_47(&self) -> &PRIORITY_47 { + &self.priority_47 + } #[doc = "0xc0 - PRIORITY Register for interrupt id 48"] - pub priority_48: PRIORITY_48, + #[inline(always)] + pub const fn priority_48(&self) -> &PRIORITY_48 { + &self.priority_48 + } #[doc = "0xc4 - PRIORITY Register for interrupt id 49"] - pub priority_49: PRIORITY_49, + #[inline(always)] + pub const fn priority_49(&self) -> &PRIORITY_49 { + &self.priority_49 + } #[doc = "0xc8 - PRIORITY Register for interrupt id 50"] - pub priority_50: PRIORITY_50, + #[inline(always)] + pub const fn priority_50(&self) -> &PRIORITY_50 { + &self.priority_50 + } #[doc = "0xcc - PRIORITY Register for interrupt id 51"] - pub priority_51: PRIORITY_51, + #[inline(always)] + pub const fn priority_51(&self) -> &PRIORITY_51 { + &self.priority_51 + } #[doc = "0xd0 - PRIORITY Register for interrupt id 52"] - pub priority_52: PRIORITY_52, + #[inline(always)] + pub const fn priority_52(&self) -> &PRIORITY_52 { + &self.priority_52 + } #[doc = "0xd4 - PRIORITY Register for interrupt id 53"] - pub priority_53: PRIORITY_53, + #[inline(always)] + pub const fn priority_53(&self) -> &PRIORITY_53 { + &self.priority_53 + } #[doc = "0xd8 - PRIORITY Register for interrupt id 54"] - pub priority_54: PRIORITY_54, + #[inline(always)] + pub const fn priority_54(&self) -> &PRIORITY_54 { + &self.priority_54 + } #[doc = "0xdc - PRIORITY Register for interrupt id 55"] - pub priority_55: PRIORITY_55, + #[inline(always)] + pub const fn priority_55(&self) -> &PRIORITY_55 { + &self.priority_55 + } #[doc = "0xe0 - PRIORITY Register for interrupt id 56"] - pub priority_56: PRIORITY_56, + #[inline(always)] + pub const fn priority_56(&self) -> &PRIORITY_56 { + &self.priority_56 + } #[doc = "0xe4 - PRIORITY Register for interrupt id 57"] - pub priority_57: PRIORITY_57, + #[inline(always)] + pub const fn priority_57(&self) -> &PRIORITY_57 { + &self.priority_57 + } #[doc = "0xe8 - PRIORITY Register for interrupt id 58"] - pub priority_58: PRIORITY_58, + #[inline(always)] + pub const fn priority_58(&self) -> &PRIORITY_58 { + &self.priority_58 + } #[doc = "0xec - PRIORITY Register for interrupt id 59"] - pub priority_59: PRIORITY_59, + #[inline(always)] + pub const fn priority_59(&self) -> &PRIORITY_59 { + &self.priority_59 + } #[doc = "0xf0 - PRIORITY Register for interrupt id 60"] - pub priority_60: PRIORITY_60, + #[inline(always)] + pub const fn priority_60(&self) -> &PRIORITY_60 { + &self.priority_60 + } #[doc = "0xf4 - PRIORITY Register for interrupt id 61"] - pub priority_61: PRIORITY_61, + #[inline(always)] + pub const fn priority_61(&self) -> &PRIORITY_61 { + &self.priority_61 + } #[doc = "0xf8 - PRIORITY Register for interrupt id 62"] - pub priority_62: PRIORITY_62, + #[inline(always)] + pub const fn priority_62(&self) -> &PRIORITY_62 { + &self.priority_62 + } #[doc = "0xfc - PRIORITY Register for interrupt id 63"] - pub priority_63: PRIORITY_63, + #[inline(always)] + pub const fn priority_63(&self) -> &PRIORITY_63 { + &self.priority_63 + } #[doc = "0x100 - PRIORITY Register for interrupt id 64"] - pub priority_64: PRIORITY_64, + #[inline(always)] + pub const fn priority_64(&self) -> &PRIORITY_64 { + &self.priority_64 + } #[doc = "0x104 - PRIORITY Register for interrupt id 65"] - pub priority_65: PRIORITY_65, + #[inline(always)] + pub const fn priority_65(&self) -> &PRIORITY_65 { + &self.priority_65 + } #[doc = "0x108 - PRIORITY Register for interrupt id 66"] - pub priority_66: PRIORITY_66, + #[inline(always)] + pub const fn priority_66(&self) -> &PRIORITY_66 { + &self.priority_66 + } #[doc = "0x10c - PRIORITY Register for interrupt id 67"] - pub priority_67: PRIORITY_67, + #[inline(always)] + pub const fn priority_67(&self) -> &PRIORITY_67 { + &self.priority_67 + } #[doc = "0x110 - PRIORITY Register for interrupt id 68"] - pub priority_68: PRIORITY_68, + #[inline(always)] + pub const fn priority_68(&self) -> &PRIORITY_68 { + &self.priority_68 + } #[doc = "0x114 - PRIORITY Register for interrupt id 69"] - pub priority_69: PRIORITY_69, + #[inline(always)] + pub const fn priority_69(&self) -> &PRIORITY_69 { + &self.priority_69 + } #[doc = "0x118 - PRIORITY Register for interrupt id 70"] - pub priority_70: PRIORITY_70, + #[inline(always)] + pub const fn priority_70(&self) -> &PRIORITY_70 { + &self.priority_70 + } #[doc = "0x11c - PRIORITY Register for interrupt id 71"] - pub priority_71: PRIORITY_71, + #[inline(always)] + pub const fn priority_71(&self) -> &PRIORITY_71 { + &self.priority_71 + } #[doc = "0x120 - PRIORITY Register for interrupt id 72"] - pub priority_72: PRIORITY_72, + #[inline(always)] + pub const fn priority_72(&self) -> &PRIORITY_72 { + &self.priority_72 + } #[doc = "0x124 - PRIORITY Register for interrupt id 73"] - pub priority_73: PRIORITY_73, + #[inline(always)] + pub const fn priority_73(&self) -> &PRIORITY_73 { + &self.priority_73 + } #[doc = "0x128 - PRIORITY Register for interrupt id 74"] - pub priority_74: PRIORITY_74, + #[inline(always)] + pub const fn priority_74(&self) -> &PRIORITY_74 { + &self.priority_74 + } #[doc = "0x12c - PRIORITY Register for interrupt id 75"] - pub priority_75: PRIORITY_75, + #[inline(always)] + pub const fn priority_75(&self) -> &PRIORITY_75 { + &self.priority_75 + } #[doc = "0x130 - PRIORITY Register for interrupt id 76"] - pub priority_76: PRIORITY_76, + #[inline(always)] + pub const fn priority_76(&self) -> &PRIORITY_76 { + &self.priority_76 + } #[doc = "0x134 - PRIORITY Register for interrupt id 77"] - pub priority_77: PRIORITY_77, + #[inline(always)] + pub const fn priority_77(&self) -> &PRIORITY_77 { + &self.priority_77 + } #[doc = "0x138 - PRIORITY Register for interrupt id 78"] - pub priority_78: PRIORITY_78, + #[inline(always)] + pub const fn priority_78(&self) -> &PRIORITY_78 { + &self.priority_78 + } #[doc = "0x13c - PRIORITY Register for interrupt id 79"] - pub priority_79: PRIORITY_79, + #[inline(always)] + pub const fn priority_79(&self) -> &PRIORITY_79 { + &self.priority_79 + } #[doc = "0x140 - PRIORITY Register for interrupt id 80"] - pub priority_80: PRIORITY_80, + #[inline(always)] + pub const fn priority_80(&self) -> &PRIORITY_80 { + &self.priority_80 + } #[doc = "0x144 - PRIORITY Register for interrupt id 81"] - pub priority_81: PRIORITY_81, + #[inline(always)] + pub const fn priority_81(&self) -> &PRIORITY_81 { + &self.priority_81 + } #[doc = "0x148 - PRIORITY Register for interrupt id 82"] - pub priority_82: PRIORITY_82, + #[inline(always)] + pub const fn priority_82(&self) -> &PRIORITY_82 { + &self.priority_82 + } #[doc = "0x14c - PRIORITY Register for interrupt id 83"] - pub priority_83: PRIORITY_83, + #[inline(always)] + pub const fn priority_83(&self) -> &PRIORITY_83 { + &self.priority_83 + } #[doc = "0x150 - PRIORITY Register for interrupt id 84"] - pub priority_84: PRIORITY_84, + #[inline(always)] + pub const fn priority_84(&self) -> &PRIORITY_84 { + &self.priority_84 + } #[doc = "0x154 - PRIORITY Register for interrupt id 85"] - pub priority_85: PRIORITY_85, + #[inline(always)] + pub const fn priority_85(&self) -> &PRIORITY_85 { + &self.priority_85 + } #[doc = "0x158 - PRIORITY Register for interrupt id 86"] - pub priority_86: PRIORITY_86, + #[inline(always)] + pub const fn priority_86(&self) -> &PRIORITY_86 { + &self.priority_86 + } #[doc = "0x15c - PRIORITY Register for interrupt id 87"] - pub priority_87: PRIORITY_87, + #[inline(always)] + pub const fn priority_87(&self) -> &PRIORITY_87 { + &self.priority_87 + } #[doc = "0x160 - PRIORITY Register for interrupt id 88"] - pub priority_88: PRIORITY_88, + #[inline(always)] + pub const fn priority_88(&self) -> &PRIORITY_88 { + &self.priority_88 + } #[doc = "0x164 - PRIORITY Register for interrupt id 89"] - pub priority_89: PRIORITY_89, + #[inline(always)] + pub const fn priority_89(&self) -> &PRIORITY_89 { + &self.priority_89 + } #[doc = "0x168 - PRIORITY Register for interrupt id 90"] - pub priority_90: PRIORITY_90, + #[inline(always)] + pub const fn priority_90(&self) -> &PRIORITY_90 { + &self.priority_90 + } #[doc = "0x16c - PRIORITY Register for interrupt id 91"] - pub priority_91: PRIORITY_91, + #[inline(always)] + pub const fn priority_91(&self) -> &PRIORITY_91 { + &self.priority_91 + } #[doc = "0x170 - PRIORITY Register for interrupt id 92"] - pub priority_92: PRIORITY_92, + #[inline(always)] + pub const fn priority_92(&self) -> &PRIORITY_92 { + &self.priority_92 + } #[doc = "0x174 - PRIORITY Register for interrupt id 93"] - pub priority_93: PRIORITY_93, + #[inline(always)] + pub const fn priority_93(&self) -> &PRIORITY_93 { + &self.priority_93 + } #[doc = "0x178 - PRIORITY Register for interrupt id 94"] - pub priority_94: PRIORITY_94, + #[inline(always)] + pub const fn priority_94(&self) -> &PRIORITY_94 { + &self.priority_94 + } #[doc = "0x17c - PRIORITY Register for interrupt id 95"] - pub priority_95: PRIORITY_95, + #[inline(always)] + pub const fn priority_95(&self) -> &PRIORITY_95 { + &self.priority_95 + } #[doc = "0x180 - PRIORITY Register for interrupt id 96"] - pub priority_96: PRIORITY_96, + #[inline(always)] + pub const fn priority_96(&self) -> &PRIORITY_96 { + &self.priority_96 + } #[doc = "0x184 - PRIORITY Register for interrupt id 97"] - pub priority_97: PRIORITY_97, + #[inline(always)] + pub const fn priority_97(&self) -> &PRIORITY_97 { + &self.priority_97 + } #[doc = "0x188 - PRIORITY Register for interrupt id 98"] - pub priority_98: PRIORITY_98, + #[inline(always)] + pub const fn priority_98(&self) -> &PRIORITY_98 { + &self.priority_98 + } #[doc = "0x18c - PRIORITY Register for interrupt id 99"] - pub priority_99: PRIORITY_99, + #[inline(always)] + pub const fn priority_99(&self) -> &PRIORITY_99 { + &self.priority_99 + } #[doc = "0x190 - PRIORITY Register for interrupt id 100"] - pub priority_100: PRIORITY_100, + #[inline(always)] + pub const fn priority_100(&self) -> &PRIORITY_100 { + &self.priority_100 + } #[doc = "0x194 - PRIORITY Register for interrupt id 101"] - pub priority_101: PRIORITY_101, + #[inline(always)] + pub const fn priority_101(&self) -> &PRIORITY_101 { + &self.priority_101 + } #[doc = "0x198 - PRIORITY Register for interrupt id 102"] - pub priority_102: PRIORITY_102, + #[inline(always)] + pub const fn priority_102(&self) -> &PRIORITY_102 { + &self.priority_102 + } #[doc = "0x19c - PRIORITY Register for interrupt id 103"] - pub priority_103: PRIORITY_103, + #[inline(always)] + pub const fn priority_103(&self) -> &PRIORITY_103 { + &self.priority_103 + } #[doc = "0x1a0 - PRIORITY Register for interrupt id 104"] - pub priority_104: PRIORITY_104, + #[inline(always)] + pub const fn priority_104(&self) -> &PRIORITY_104 { + &self.priority_104 + } #[doc = "0x1a4 - PRIORITY Register for interrupt id 105"] - pub priority_105: PRIORITY_105, + #[inline(always)] + pub const fn priority_105(&self) -> &PRIORITY_105 { + &self.priority_105 + } #[doc = "0x1a8 - PRIORITY Register for interrupt id 106"] - pub priority_106: PRIORITY_106, + #[inline(always)] + pub const fn priority_106(&self) -> &PRIORITY_106 { + &self.priority_106 + } #[doc = "0x1ac - PRIORITY Register for interrupt id 107"] - pub priority_107: PRIORITY_107, + #[inline(always)] + pub const fn priority_107(&self) -> &PRIORITY_107 { + &self.priority_107 + } #[doc = "0x1b0 - PRIORITY Register for interrupt id 108"] - pub priority_108: PRIORITY_108, + #[inline(always)] + pub const fn priority_108(&self) -> &PRIORITY_108 { + &self.priority_108 + } #[doc = "0x1b4 - PRIORITY Register for interrupt id 109"] - pub priority_109: PRIORITY_109, + #[inline(always)] + pub const fn priority_109(&self) -> &PRIORITY_109 { + &self.priority_109 + } #[doc = "0x1b8 - PRIORITY Register for interrupt id 110"] - pub priority_110: PRIORITY_110, + #[inline(always)] + pub const fn priority_110(&self) -> &PRIORITY_110 { + &self.priority_110 + } #[doc = "0x1bc - PRIORITY Register for interrupt id 111"] - pub priority_111: PRIORITY_111, + #[inline(always)] + pub const fn priority_111(&self) -> &PRIORITY_111 { + &self.priority_111 + } #[doc = "0x1c0 - PRIORITY Register for interrupt id 112"] - pub priority_112: PRIORITY_112, + #[inline(always)] + pub const fn priority_112(&self) -> &PRIORITY_112 { + &self.priority_112 + } #[doc = "0x1c4 - PRIORITY Register for interrupt id 113"] - pub priority_113: PRIORITY_113, + #[inline(always)] + pub const fn priority_113(&self) -> &PRIORITY_113 { + &self.priority_113 + } #[doc = "0x1c8 - PRIORITY Register for interrupt id 114"] - pub priority_114: PRIORITY_114, + #[inline(always)] + pub const fn priority_114(&self) -> &PRIORITY_114 { + &self.priority_114 + } #[doc = "0x1cc - PRIORITY Register for interrupt id 115"] - pub priority_115: PRIORITY_115, + #[inline(always)] + pub const fn priority_115(&self) -> &PRIORITY_115 { + &self.priority_115 + } #[doc = "0x1d0 - PRIORITY Register for interrupt id 116"] - pub priority_116: PRIORITY_116, + #[inline(always)] + pub const fn priority_116(&self) -> &PRIORITY_116 { + &self.priority_116 + } #[doc = "0x1d4 - PRIORITY Register for interrupt id 117"] - pub priority_117: PRIORITY_117, + #[inline(always)] + pub const fn priority_117(&self) -> &PRIORITY_117 { + &self.priority_117 + } #[doc = "0x1d8 - PRIORITY Register for interrupt id 118"] - pub priority_118: PRIORITY_118, + #[inline(always)] + pub const fn priority_118(&self) -> &PRIORITY_118 { + &self.priority_118 + } #[doc = "0x1dc - PRIORITY Register for interrupt id 119"] - pub priority_119: PRIORITY_119, + #[inline(always)] + pub const fn priority_119(&self) -> &PRIORITY_119 { + &self.priority_119 + } #[doc = "0x1e0 - PRIORITY Register for interrupt id 120"] - pub priority_120: PRIORITY_120, + #[inline(always)] + pub const fn priority_120(&self) -> &PRIORITY_120 { + &self.priority_120 + } #[doc = "0x1e4 - PRIORITY Register for interrupt id 121"] - pub priority_121: PRIORITY_121, + #[inline(always)] + pub const fn priority_121(&self) -> &PRIORITY_121 { + &self.priority_121 + } #[doc = "0x1e8 - PRIORITY Register for interrupt id 122"] - pub priority_122: PRIORITY_122, + #[inline(always)] + pub const fn priority_122(&self) -> &PRIORITY_122 { + &self.priority_122 + } #[doc = "0x1ec - PRIORITY Register for interrupt id 123"] - pub priority_123: PRIORITY_123, + #[inline(always)] + pub const fn priority_123(&self) -> &PRIORITY_123 { + &self.priority_123 + } #[doc = "0x1f0 - PRIORITY Register for interrupt id 124"] - pub priority_124: PRIORITY_124, + #[inline(always)] + pub const fn priority_124(&self) -> &PRIORITY_124 { + &self.priority_124 + } #[doc = "0x1f4 - PRIORITY Register for interrupt id 125"] - pub priority_125: PRIORITY_125, + #[inline(always)] + pub const fn priority_125(&self) -> &PRIORITY_125 { + &self.priority_125 + } #[doc = "0x1f8 - PRIORITY Register for interrupt id 126"] - pub priority_126: PRIORITY_126, + #[inline(always)] + pub const fn priority_126(&self) -> &PRIORITY_126 { + &self.priority_126 + } #[doc = "0x1fc - PRIORITY Register for interrupt id 127"] - pub priority_127: PRIORITY_127, + #[inline(always)] + pub const fn priority_127(&self) -> &PRIORITY_127 { + &self.priority_127 + } #[doc = "0x200 - PRIORITY Register for interrupt id 128"] - pub priority_128: PRIORITY_128, + #[inline(always)] + pub const fn priority_128(&self) -> &PRIORITY_128 { + &self.priority_128 + } #[doc = "0x204 - PRIORITY Register for interrupt id 129"] - pub priority_129: PRIORITY_129, + #[inline(always)] + pub const fn priority_129(&self) -> &PRIORITY_129 { + &self.priority_129 + } #[doc = "0x208 - PRIORITY Register for interrupt id 130"] - pub priority_130: PRIORITY_130, + #[inline(always)] + pub const fn priority_130(&self) -> &PRIORITY_130 { + &self.priority_130 + } #[doc = "0x20c - PRIORITY Register for interrupt id 131"] - pub priority_131: PRIORITY_131, + #[inline(always)] + pub const fn priority_131(&self) -> &PRIORITY_131 { + &self.priority_131 + } #[doc = "0x210 - PRIORITY Register for interrupt id 132"] - pub priority_132: PRIORITY_132, + #[inline(always)] + pub const fn priority_132(&self) -> &PRIORITY_132 { + &self.priority_132 + } #[doc = "0x214 - PRIORITY Register for interrupt id 133"] - pub priority_133: PRIORITY_133, + #[inline(always)] + pub const fn priority_133(&self) -> &PRIORITY_133 { + &self.priority_133 + } #[doc = "0x218 - PRIORITY Register for interrupt id 134"] - pub priority_134: PRIORITY_134, + #[inline(always)] + pub const fn priority_134(&self) -> &PRIORITY_134 { + &self.priority_134 + } #[doc = "0x21c - PRIORITY Register for interrupt id 135"] - pub priority_135: PRIORITY_135, + #[inline(always)] + pub const fn priority_135(&self) -> &PRIORITY_135 { + &self.priority_135 + } #[doc = "0x220 - PRIORITY Register for interrupt id 136"] - pub priority_136: PRIORITY_136, - _reserved136: [u8; 0x0ddc], + #[inline(always)] + pub const fn priority_136(&self) -> &PRIORITY_136 { + &self.priority_136 + } #[doc = "0x1000 - PENDING Register for interrupt ids 31 to 0"] - pub pending_0: PENDING_0, + #[inline(always)] + pub const fn pending_0(&self) -> &PENDING_0 { + &self.pending_0 + } #[doc = "0x1004 - PENDING Register for interrupt ids 63 to 32"] - pub pending_1: PENDING_1, + #[inline(always)] + pub const fn pending_1(&self) -> &PENDING_1 { + &self.pending_1 + } #[doc = "0x1008 - PENDING Register for interrupt ids 95 to 64"] - pub pending_2: PENDING_2, + #[inline(always)] + pub const fn pending_2(&self) -> &PENDING_2 { + &self.pending_2 + } #[doc = "0x100c - PENDING Register for interrupt ids 127 to 96"] - pub pending_3: PENDING_3, + #[inline(always)] + pub const fn pending_3(&self) -> &PENDING_3 { + &self.pending_3 + } #[doc = "0x1010 - PENDING Register for interrupt ids 136 to 128"] - pub pending_4: PENDING_4, - _reserved141: [u8; 0x0fec], + #[inline(always)] + pub const fn pending_4(&self) -> &PENDING_4 { + &self.pending_4 + } #[doc = "0x2000 - ENABLE Register for interrupt ids 31 to 0 for hart 0"] - pub enable_0_0: ENABLE_0_0, + #[inline(always)] + pub const fn enable_0_0(&self) -> &ENABLE_0_0 { + &self.enable_0_0 + } #[doc = "0x2004 - ENABLE Register for interrupt ids 63 to 32 for hart 0"] - pub enable_1_0: ENABLE_1_0, + #[inline(always)] + pub const fn enable_1_0(&self) -> &ENABLE_1_0 { + &self.enable_1_0 + } #[doc = "0x2008 - ENABLE Register for interrupt ids 95 to 64 for hart 0"] - pub enable_2_0: ENABLE_2_0, + #[inline(always)] + pub const fn enable_2_0(&self) -> &ENABLE_2_0 { + &self.enable_2_0 + } #[doc = "0x200c - ENABLE Register for interrupt ids 127 to 96 for hart 0"] - pub enable_3_0: ENABLE_3_0, + #[inline(always)] + pub const fn enable_3_0(&self) -> &ENABLE_3_0 { + &self.enable_3_0 + } #[doc = "0x2010 - ENABLE Register for interrupt ids 136 to 128 for hart 0"] - pub enable_4_0: ENABLE_4_0, - _reserved146: [u8; 0x6c], + #[inline(always)] + pub const fn enable_4_0(&self) -> &ENABLE_4_0 { + &self.enable_4_0 + } #[doc = "0x2080 - ENABLE Register for interrupt ids 31 to 0 for hart 1"] - pub enable_0_1: ENABLE_0_1, + #[inline(always)] + pub const fn enable_0_1(&self) -> &ENABLE_0_1 { + &self.enable_0_1 + } #[doc = "0x2084 - ENABLE Register for interrupt ids 63 to 32 for hart 1"] - pub enable_1_1: ENABLE_1_1, + #[inline(always)] + pub const fn enable_1_1(&self) -> &ENABLE_1_1 { + &self.enable_1_1 + } #[doc = "0x2088 - ENABLE Register for interrupt ids 95 to 64 for hart 1"] - pub enable_2_1: ENABLE_2_1, + #[inline(always)] + pub const fn enable_2_1(&self) -> &ENABLE_2_1 { + &self.enable_2_1 + } #[doc = "0x208c - ENABLE Register for interrupt ids 127 to 96 for hart 1"] - pub enable_3_1: ENABLE_3_1, + #[inline(always)] + pub const fn enable_3_1(&self) -> &ENABLE_3_1 { + &self.enable_3_1 + } #[doc = "0x2090 - ENABLE Register for interrupt ids 136 to 128 for hart 1"] - pub enable_4_1: ENABLE_4_1, - _reserved151: [u8; 0x6c], + #[inline(always)] + pub const fn enable_4_1(&self) -> &ENABLE_4_1 { + &self.enable_4_1 + } #[doc = "0x2100 - ENABLE Register for interrupt ids 31 to 0 for hart 2"] - pub enable_0_2: ENABLE_0_2, + #[inline(always)] + pub const fn enable_0_2(&self) -> &ENABLE_0_2 { + &self.enable_0_2 + } #[doc = "0x2104 - ENABLE Register for interrupt ids 63 to 32 for hart 2"] - pub enable_1_2: ENABLE_1_2, + #[inline(always)] + pub const fn enable_1_2(&self) -> &ENABLE_1_2 { + &self.enable_1_2 + } #[doc = "0x2108 - ENABLE Register for interrupt ids 95 to 64 for hart 2"] - pub enable_2_2: ENABLE_2_2, + #[inline(always)] + pub const fn enable_2_2(&self) -> &ENABLE_2_2 { + &self.enable_2_2 + } #[doc = "0x210c - ENABLE Register for interrupt ids 127 to 96 for hart 2"] - pub enable_3_2: ENABLE_3_2, + #[inline(always)] + pub const fn enable_3_2(&self) -> &ENABLE_3_2 { + &self.enable_3_2 + } #[doc = "0x2110 - ENABLE Register for interrupt ids 136 to 128 for hart 2"] - pub enable_4_2: ENABLE_4_2, - _reserved156: [u8; 0x6c], + #[inline(always)] + pub const fn enable_4_2(&self) -> &ENABLE_4_2 { + &self.enable_4_2 + } #[doc = "0x2180 - ENABLE Register for interrupt ids 31 to 0 for hart 3"] - pub enable_0_3: ENABLE_0_3, + #[inline(always)] + pub const fn enable_0_3(&self) -> &ENABLE_0_3 { + &self.enable_0_3 + } #[doc = "0x2184 - ENABLE Register for interrupt ids 63 to 32 for hart 3"] - pub enable_1_3: ENABLE_1_3, + #[inline(always)] + pub const fn enable_1_3(&self) -> &ENABLE_1_3 { + &self.enable_1_3 + } #[doc = "0x2188 - ENABLE Register for interrupt ids 95 to 64 for hart 3"] - pub enable_2_3: ENABLE_2_3, + #[inline(always)] + pub const fn enable_2_3(&self) -> &ENABLE_2_3 { + &self.enable_2_3 + } #[doc = "0x218c - ENABLE Register for interrupt ids 127 to 96 for hart 3"] - pub enable_3_3: ENABLE_3_3, + #[inline(always)] + pub const fn enable_3_3(&self) -> &ENABLE_3_3 { + &self.enable_3_3 + } #[doc = "0x2190 - ENABLE Register for interrupt ids 136 to 128 for hart 3"] - pub enable_4_3: ENABLE_4_3, - _reserved161: [u8; 0x6c], + #[inline(always)] + pub const fn enable_4_3(&self) -> &ENABLE_4_3 { + &self.enable_4_3 + } #[doc = "0x2200 - ENABLE Register for interrupt ids 31 to 0 for hart 4"] - pub enable_0_4: ENABLE_0_4, + #[inline(always)] + pub const fn enable_0_4(&self) -> &ENABLE_0_4 { + &self.enable_0_4 + } #[doc = "0x2204 - ENABLE Register for interrupt ids 63 to 32 for hart 4"] - pub enable_1_4: ENABLE_1_4, + #[inline(always)] + pub const fn enable_1_4(&self) -> &ENABLE_1_4 { + &self.enable_1_4 + } #[doc = "0x2208 - ENABLE Register for interrupt ids 95 to 64 for hart 4"] - pub enable_2_4: ENABLE_2_4, + #[inline(always)] + pub const fn enable_2_4(&self) -> &ENABLE_2_4 { + &self.enable_2_4 + } #[doc = "0x220c - ENABLE Register for interrupt ids 127 to 96 for hart 4"] - pub enable_3_4: ENABLE_3_4, + #[inline(always)] + pub const fn enable_3_4(&self) -> &ENABLE_3_4 { + &self.enable_3_4 + } #[doc = "0x2210 - ENABLE Register for interrupt ids 136 to 128 for hart 4"] - pub enable_4_4: ENABLE_4_4, - _reserved166: [u8; 0x001f_ddec], + #[inline(always)] + pub const fn enable_4_4(&self) -> &ENABLE_4_4 { + &self.enable_4_4 + } #[doc = "0x200000 - PRIORITY THRESHOLD Register for hart 0"] - pub threshold_0: THRESHOLD_0, + #[inline(always)] + pub const fn threshold_0(&self) -> &THRESHOLD_0 { + &self.threshold_0 + } #[doc = "0x200004 - CLAIM and COMPLETE Register for hart 0"] - pub claimplete_0: CLAIMPLETE_0, - _reserved168: [u8; 0x0ff8], + #[inline(always)] + pub const fn claimplete_0(&self) -> &CLAIMPLETE_0 { + &self.claimplete_0 + } #[doc = "0x201000 - PRIORITY THRESHOLD Register for hart 1"] - pub threshold_1: THRESHOLD_1, + #[inline(always)] + pub const fn threshold_1(&self) -> &THRESHOLD_1 { + &self.threshold_1 + } #[doc = "0x201004 - CLAIM and COMPLETE Register for hart 1"] - pub claimplete_1: CLAIMPLETE_1, - _reserved170: [u8; 0x0ff8], + #[inline(always)] + pub const fn claimplete_1(&self) -> &CLAIMPLETE_1 { + &self.claimplete_1 + } #[doc = "0x202000 - PRIORITY THRESHOLD Register for hart 2"] - pub threshold_2: THRESHOLD_2, + #[inline(always)] + pub const fn threshold_2(&self) -> &THRESHOLD_2 { + &self.threshold_2 + } #[doc = "0x202004 - CLAIM and COMPLETE Register for hart 2"] - pub claimplete_2: CLAIMPLETE_2, - _reserved172: [u8; 0x0ff8], + #[inline(always)] + pub const fn claimplete_2(&self) -> &CLAIMPLETE_2 { + &self.claimplete_2 + } #[doc = "0x203000 - PRIORITY THRESHOLD Register for hart 3"] - pub threshold_3: THRESHOLD_3, + #[inline(always)] + pub const fn threshold_3(&self) -> &THRESHOLD_3 { + &self.threshold_3 + } #[doc = "0x203004 - CLAIM and COMPLETE Register for hart 3"] - pub claimplete_3: CLAIMPLETE_3, - _reserved174: [u8; 0x0ff8], + #[inline(always)] + pub const fn claimplete_3(&self) -> &CLAIMPLETE_3 { + &self.claimplete_3 + } #[doc = "0x204000 - PRIORITY THRESHOLD Register for hart 4"] - pub threshold_4: THRESHOLD_4, + #[inline(always)] + pub const fn threshold_4(&self) -> &THRESHOLD_4 { + &self.threshold_4 + } #[doc = "0x204004 - CLAIM and COMPLETE Register for hart 4"] - pub claimplete_4: CLAIMPLETE_4, + #[inline(always)] + pub const fn claimplete_4(&self) -> &CLAIMPLETE_4 { + &self.claimplete_4 + } } -#[doc = "priority_1 (rw) register accessor: PRIORITY Register for interrupt id 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_1`] +#[doc = "priority_1 (rw) register accessor: PRIORITY Register for interrupt id 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_1`] module"] pub type PRIORITY_1 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 1"] pub mod priority_1; -#[doc = "priority_2 (rw) register accessor: PRIORITY Register for interrupt id 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_2`] +#[doc = "priority_2 (rw) register accessor: PRIORITY Register for interrupt id 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_2`] module"] pub type PRIORITY_2 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 2"] pub mod priority_2; -#[doc = "priority_3 (rw) register accessor: PRIORITY Register for interrupt id 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_3`] +#[doc = "priority_3 (rw) register accessor: PRIORITY Register for interrupt id 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_3`] module"] pub type PRIORITY_3 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 3"] pub mod priority_3; -#[doc = "priority_4 (rw) register accessor: PRIORITY Register for interrupt id 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_4`] +#[doc = "priority_4 (rw) register accessor: PRIORITY Register for interrupt id 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_4`] module"] pub type PRIORITY_4 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 4"] pub mod priority_4; -#[doc = "priority_5 (rw) register accessor: PRIORITY Register for interrupt id 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_5`] +#[doc = "priority_5 (rw) register accessor: PRIORITY Register for interrupt id 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_5`] module"] pub type PRIORITY_5 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 5"] pub mod priority_5; -#[doc = "priority_6 (rw) register accessor: PRIORITY Register for interrupt id 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_6::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_6`] +#[doc = "priority_6 (rw) register accessor: PRIORITY Register for interrupt id 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_6::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_6`] module"] pub type PRIORITY_6 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 6"] pub mod priority_6; -#[doc = "priority_7 (rw) register accessor: PRIORITY Register for interrupt id 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_7::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_7`] +#[doc = "priority_7 (rw) register accessor: PRIORITY Register for interrupt id 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_7::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_7`] module"] pub type PRIORITY_7 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 7"] pub mod priority_7; -#[doc = "priority_8 (rw) register accessor: PRIORITY Register for interrupt id 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_8`] +#[doc = "priority_8 (rw) register accessor: PRIORITY Register for interrupt id 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_8`] module"] pub type PRIORITY_8 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 8"] pub mod priority_8; -#[doc = "priority_9 (rw) register accessor: PRIORITY Register for interrupt id 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_9::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_9`] +#[doc = "priority_9 (rw) register accessor: PRIORITY Register for interrupt id 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_9::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_9`] module"] pub type PRIORITY_9 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 9"] pub mod priority_9; -#[doc = "priority_10 (rw) register accessor: PRIORITY Register for interrupt id 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_10::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_10`] +#[doc = "priority_10 (rw) register accessor: PRIORITY Register for interrupt id 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_10::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_10`] module"] pub type PRIORITY_10 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 10"] pub mod priority_10; -#[doc = "priority_11 (rw) register accessor: PRIORITY Register for interrupt id 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_11::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_11`] +#[doc = "priority_11 (rw) register accessor: PRIORITY Register for interrupt id 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_11::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_11`] module"] pub type PRIORITY_11 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 11"] pub mod priority_11; -#[doc = "priority_12 (rw) register accessor: PRIORITY Register for interrupt id 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_12::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_12`] +#[doc = "priority_12 (rw) register accessor: PRIORITY Register for interrupt id 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_12::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_12`] module"] pub type PRIORITY_12 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 12"] pub mod priority_12; -#[doc = "priority_13 (rw) register accessor: PRIORITY Register for interrupt id 13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_13::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_13`] +#[doc = "priority_13 (rw) register accessor: PRIORITY Register for interrupt id 13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_13::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_13`] module"] pub type PRIORITY_13 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 13"] pub mod priority_13; -#[doc = "priority_14 (rw) register accessor: PRIORITY Register for interrupt id 14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_14::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_14`] +#[doc = "priority_14 (rw) register accessor: PRIORITY Register for interrupt id 14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_14::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_14`] module"] pub type PRIORITY_14 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 14"] pub mod priority_14; -#[doc = "priority_15 (rw) register accessor: PRIORITY Register for interrupt id 15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_15::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_15`] +#[doc = "priority_15 (rw) register accessor: PRIORITY Register for interrupt id 15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_15::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_15`] module"] pub type PRIORITY_15 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 15"] pub mod priority_15; -#[doc = "priority_16 (rw) register accessor: PRIORITY Register for interrupt id 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_16::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_16`] +#[doc = "priority_16 (rw) register accessor: PRIORITY Register for interrupt id 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_16::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_16`] module"] pub type PRIORITY_16 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 16"] pub mod priority_16; -#[doc = "priority_17 (rw) register accessor: PRIORITY Register for interrupt id 17\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_17::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_17::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_17`] +#[doc = "priority_17 (rw) register accessor: PRIORITY Register for interrupt id 17\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_17::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_17::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_17`] module"] pub type PRIORITY_17 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 17"] pub mod priority_17; -#[doc = "priority_18 (rw) register accessor: PRIORITY Register for interrupt id 18\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_18::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_18::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_18`] +#[doc = "priority_18 (rw) register accessor: PRIORITY Register for interrupt id 18\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_18::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_18::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_18`] module"] pub type PRIORITY_18 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 18"] pub mod priority_18; -#[doc = "priority_19 (rw) register accessor: PRIORITY Register for interrupt id 19\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_19::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_19`] +#[doc = "priority_19 (rw) register accessor: PRIORITY Register for interrupt id 19\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_19::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_19`] module"] pub type PRIORITY_19 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 19"] pub mod priority_19; -#[doc = "priority_20 (rw) register accessor: PRIORITY Register for interrupt id 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_20::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_20`] +#[doc = "priority_20 (rw) register accessor: PRIORITY Register for interrupt id 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_20::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_20`] module"] pub type PRIORITY_20 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 20"] pub mod priority_20; -#[doc = "priority_21 (rw) register accessor: PRIORITY Register for interrupt id 21\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_21::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_21::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_21`] +#[doc = "priority_21 (rw) register accessor: PRIORITY Register for interrupt id 21\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_21::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_21::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_21`] module"] pub type PRIORITY_21 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 21"] pub mod priority_21; -#[doc = "priority_22 (rw) register accessor: PRIORITY Register for interrupt id 22\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_22::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_22::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_22`] +#[doc = "priority_22 (rw) register accessor: PRIORITY Register for interrupt id 22\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_22::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_22::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_22`] module"] pub type PRIORITY_22 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 22"] pub mod priority_22; -#[doc = "priority_23 (rw) register accessor: PRIORITY Register for interrupt id 23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_23::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_23`] +#[doc = "priority_23 (rw) register accessor: PRIORITY Register for interrupt id 23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_23::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_23`] module"] pub type PRIORITY_23 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 23"] pub mod priority_23; -#[doc = "priority_24 (rw) register accessor: PRIORITY Register for interrupt id 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_24::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_24`] +#[doc = "priority_24 (rw) register accessor: PRIORITY Register for interrupt id 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_24::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_24`] module"] pub type PRIORITY_24 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 24"] pub mod priority_24; -#[doc = "priority_25 (rw) register accessor: PRIORITY Register for interrupt id 25\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_25::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_25::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_25`] +#[doc = "priority_25 (rw) register accessor: PRIORITY Register for interrupt id 25\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_25::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_25::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_25`] module"] pub type PRIORITY_25 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 25"] pub mod priority_25; -#[doc = "priority_26 (rw) register accessor: PRIORITY Register for interrupt id 26\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_26::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_26::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_26`] +#[doc = "priority_26 (rw) register accessor: PRIORITY Register for interrupt id 26\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_26::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_26::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_26`] module"] pub type PRIORITY_26 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 26"] pub mod priority_26; -#[doc = "priority_27 (rw) register accessor: PRIORITY Register for interrupt id 27\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_27::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_27`] +#[doc = "priority_27 (rw) register accessor: PRIORITY Register for interrupt id 27\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_27::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_27`] module"] pub type PRIORITY_27 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 27"] pub mod priority_27; -#[doc = "priority_28 (rw) register accessor: PRIORITY Register for interrupt id 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_28::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_28`] +#[doc = "priority_28 (rw) register accessor: PRIORITY Register for interrupt id 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_28::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_28`] module"] pub type PRIORITY_28 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 28"] pub mod priority_28; -#[doc = "priority_29 (rw) register accessor: PRIORITY Register for interrupt id 29\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_29::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_29::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_29`] +#[doc = "priority_29 (rw) register accessor: PRIORITY Register for interrupt id 29\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_29::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_29::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_29`] module"] pub type PRIORITY_29 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 29"] pub mod priority_29; -#[doc = "priority_30 (rw) register accessor: PRIORITY Register for interrupt id 30\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_30::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_30::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_30`] +#[doc = "priority_30 (rw) register accessor: PRIORITY Register for interrupt id 30\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_30::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_30::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_30`] module"] pub type PRIORITY_30 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 30"] pub mod priority_30; -#[doc = "priority_31 (rw) register accessor: PRIORITY Register for interrupt id 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_31::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_31::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_31`] +#[doc = "priority_31 (rw) register accessor: PRIORITY Register for interrupt id 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_31::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_31::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_31`] module"] pub type PRIORITY_31 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 31"] pub mod priority_31; -#[doc = "priority_32 (rw) register accessor: PRIORITY Register for interrupt id 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_32::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_32`] +#[doc = "priority_32 (rw) register accessor: PRIORITY Register for interrupt id 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_32::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_32`] module"] pub type PRIORITY_32 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 32"] pub mod priority_32; -#[doc = "priority_33 (rw) register accessor: PRIORITY Register for interrupt id 33\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_33::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_33::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_33`] +#[doc = "priority_33 (rw) register accessor: PRIORITY Register for interrupt id 33\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_33::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_33::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_33`] module"] pub type PRIORITY_33 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 33"] pub mod priority_33; -#[doc = "priority_34 (rw) register accessor: PRIORITY Register for interrupt id 34\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_34::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_34::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_34`] +#[doc = "priority_34 (rw) register accessor: PRIORITY Register for interrupt id 34\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_34::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_34::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_34`] module"] pub type PRIORITY_34 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 34"] pub mod priority_34; -#[doc = "priority_35 (rw) register accessor: PRIORITY Register for interrupt id 35\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_35::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_35::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_35`] +#[doc = "priority_35 (rw) register accessor: PRIORITY Register for interrupt id 35\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_35::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_35::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_35`] module"] pub type PRIORITY_35 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 35"] pub mod priority_35; -#[doc = "priority_36 (rw) register accessor: PRIORITY Register for interrupt id 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_36::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_36`] +#[doc = "priority_36 (rw) register accessor: PRIORITY Register for interrupt id 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_36::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_36`] module"] pub type PRIORITY_36 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 36"] pub mod priority_36; -#[doc = "priority_37 (rw) register accessor: PRIORITY Register for interrupt id 37\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_37::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_37::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_37`] +#[doc = "priority_37 (rw) register accessor: PRIORITY Register for interrupt id 37\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_37::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_37::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_37`] module"] pub type PRIORITY_37 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 37"] pub mod priority_37; -#[doc = "priority_38 (rw) register accessor: PRIORITY Register for interrupt id 38\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_38::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_38::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_38`] +#[doc = "priority_38 (rw) register accessor: PRIORITY Register for interrupt id 38\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_38::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_38::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_38`] module"] pub type PRIORITY_38 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 38"] pub mod priority_38; -#[doc = "priority_39 (rw) register accessor: PRIORITY Register for interrupt id 39\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_39::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_39::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_39`] +#[doc = "priority_39 (rw) register accessor: PRIORITY Register for interrupt id 39\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_39::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_39::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_39`] module"] pub type PRIORITY_39 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 39"] pub mod priority_39; -#[doc = "priority_40 (rw) register accessor: PRIORITY Register for interrupt id 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_40::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_40`] +#[doc = "priority_40 (rw) register accessor: PRIORITY Register for interrupt id 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_40::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_40`] module"] pub type PRIORITY_40 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 40"] pub mod priority_40; -#[doc = "priority_41 (rw) register accessor: PRIORITY Register for interrupt id 41\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_41::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_41::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_41`] +#[doc = "priority_41 (rw) register accessor: PRIORITY Register for interrupt id 41\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_41::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_41::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_41`] module"] pub type PRIORITY_41 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 41"] pub mod priority_41; -#[doc = "priority_42 (rw) register accessor: PRIORITY Register for interrupt id 42\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_42::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_42::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_42`] +#[doc = "priority_42 (rw) register accessor: PRIORITY Register for interrupt id 42\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_42::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_42::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_42`] module"] pub type PRIORITY_42 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 42"] pub mod priority_42; -#[doc = "priority_43 (rw) register accessor: PRIORITY Register for interrupt id 43\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_43::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_43::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_43`] +#[doc = "priority_43 (rw) register accessor: PRIORITY Register for interrupt id 43\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_43::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_43::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_43`] module"] pub type PRIORITY_43 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 43"] pub mod priority_43; -#[doc = "priority_44 (rw) register accessor: PRIORITY Register for interrupt id 44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_44::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_44`] +#[doc = "priority_44 (rw) register accessor: PRIORITY Register for interrupt id 44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_44::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_44`] module"] pub type PRIORITY_44 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 44"] pub mod priority_44; -#[doc = "priority_45 (rw) register accessor: PRIORITY Register for interrupt id 45\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_45::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_45::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_45`] +#[doc = "priority_45 (rw) register accessor: PRIORITY Register for interrupt id 45\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_45::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_45::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_45`] module"] pub type PRIORITY_45 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 45"] pub mod priority_45; -#[doc = "priority_46 (rw) register accessor: PRIORITY Register for interrupt id 46\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_46::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_46::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_46`] +#[doc = "priority_46 (rw) register accessor: PRIORITY Register for interrupt id 46\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_46::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_46::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_46`] module"] pub type PRIORITY_46 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 46"] pub mod priority_46; -#[doc = "priority_47 (rw) register accessor: PRIORITY Register for interrupt id 47\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_47::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_47::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_47`] +#[doc = "priority_47 (rw) register accessor: PRIORITY Register for interrupt id 47\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_47::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_47::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_47`] module"] pub type PRIORITY_47 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 47"] pub mod priority_47; -#[doc = "priority_48 (rw) register accessor: PRIORITY Register for interrupt id 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_48`] +#[doc = "priority_48 (rw) register accessor: PRIORITY Register for interrupt id 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_48`] module"] pub type PRIORITY_48 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 48"] pub mod priority_48; -#[doc = "priority_49 (rw) register accessor: PRIORITY Register for interrupt id 49\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_49::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_49::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_49`] +#[doc = "priority_49 (rw) register accessor: PRIORITY Register for interrupt id 49\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_49::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_49::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_49`] module"] pub type PRIORITY_49 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 49"] pub mod priority_49; -#[doc = "priority_50 (rw) register accessor: PRIORITY Register for interrupt id 50\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_50::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_50::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_50`] +#[doc = "priority_50 (rw) register accessor: PRIORITY Register for interrupt id 50\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_50::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_50::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_50`] module"] pub type PRIORITY_50 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 50"] pub mod priority_50; -#[doc = "priority_51 (rw) register accessor: PRIORITY Register for interrupt id 51\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_51::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_51::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_51`] +#[doc = "priority_51 (rw) register accessor: PRIORITY Register for interrupt id 51\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_51::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_51::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_51`] module"] pub type PRIORITY_51 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 51"] pub mod priority_51; -#[doc = "priority_52 (rw) register accessor: PRIORITY Register for interrupt id 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_52`] +#[doc = "priority_52 (rw) register accessor: PRIORITY Register for interrupt id 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_52`] module"] pub type PRIORITY_52 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 52"] pub mod priority_52; -#[doc = "priority_53 (rw) register accessor: PRIORITY Register for interrupt id 53\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_53::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_53::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_53`] +#[doc = "priority_53 (rw) register accessor: PRIORITY Register for interrupt id 53\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_53::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_53::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_53`] module"] pub type PRIORITY_53 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 53"] pub mod priority_53; -#[doc = "priority_54 (rw) register accessor: PRIORITY Register for interrupt id 54\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_54::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_54::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_54`] +#[doc = "priority_54 (rw) register accessor: PRIORITY Register for interrupt id 54\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_54::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_54::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_54`] module"] pub type PRIORITY_54 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 54"] pub mod priority_54; -#[doc = "priority_55 (rw) register accessor: PRIORITY Register for interrupt id 55\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_55::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_55::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_55`] +#[doc = "priority_55 (rw) register accessor: PRIORITY Register for interrupt id 55\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_55::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_55::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_55`] module"] pub type PRIORITY_55 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 55"] pub mod priority_55; -#[doc = "priority_56 (rw) register accessor: PRIORITY Register for interrupt id 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_56`] +#[doc = "priority_56 (rw) register accessor: PRIORITY Register for interrupt id 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_56`] module"] pub type PRIORITY_56 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 56"] pub mod priority_56; -#[doc = "priority_57 (rw) register accessor: PRIORITY Register for interrupt id 57\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_57::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_57::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_57`] +#[doc = "priority_57 (rw) register accessor: PRIORITY Register for interrupt id 57\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_57::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_57::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_57`] module"] pub type PRIORITY_57 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 57"] pub mod priority_57; -#[doc = "priority_58 (rw) register accessor: PRIORITY Register for interrupt id 58\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_58::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_58::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_58`] +#[doc = "priority_58 (rw) register accessor: PRIORITY Register for interrupt id 58\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_58::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_58::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_58`] module"] pub type PRIORITY_58 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 58"] pub mod priority_58; -#[doc = "priority_59 (rw) register accessor: PRIORITY Register for interrupt id 59\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_59::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_59::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_59`] +#[doc = "priority_59 (rw) register accessor: PRIORITY Register for interrupt id 59\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_59::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_59::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_59`] module"] pub type PRIORITY_59 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 59"] pub mod priority_59; -#[doc = "priority_60 (rw) register accessor: PRIORITY Register for interrupt id 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_60`] +#[doc = "priority_60 (rw) register accessor: PRIORITY Register for interrupt id 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_60`] module"] pub type PRIORITY_60 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 60"] pub mod priority_60; -#[doc = "priority_61 (rw) register accessor: PRIORITY Register for interrupt id 61\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_61::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_61::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_61`] +#[doc = "priority_61 (rw) register accessor: PRIORITY Register for interrupt id 61\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_61::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_61::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_61`] module"] pub type PRIORITY_61 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 61"] pub mod priority_61; -#[doc = "priority_62 (rw) register accessor: PRIORITY Register for interrupt id 62\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_62::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_62::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_62`] +#[doc = "priority_62 (rw) register accessor: PRIORITY Register for interrupt id 62\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_62::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_62::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_62`] module"] pub type PRIORITY_62 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 62"] pub mod priority_62; -#[doc = "priority_63 (rw) register accessor: PRIORITY Register for interrupt id 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_63::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_63::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_63`] +#[doc = "priority_63 (rw) register accessor: PRIORITY Register for interrupt id 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_63::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_63::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_63`] module"] pub type PRIORITY_63 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 63"] pub mod priority_63; -#[doc = "priority_64 (rw) register accessor: PRIORITY Register for interrupt id 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_64`] +#[doc = "priority_64 (rw) register accessor: PRIORITY Register for interrupt id 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_64`] module"] pub type PRIORITY_64 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 64"] pub mod priority_64; -#[doc = "priority_65 (rw) register accessor: PRIORITY Register for interrupt id 65\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_65::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_65::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_65`] +#[doc = "priority_65 (rw) register accessor: PRIORITY Register for interrupt id 65\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_65::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_65::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_65`] module"] pub type PRIORITY_65 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 65"] pub mod priority_65; -#[doc = "priority_66 (rw) register accessor: PRIORITY Register for interrupt id 66\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_66::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_66::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_66`] +#[doc = "priority_66 (rw) register accessor: PRIORITY Register for interrupt id 66\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_66::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_66::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_66`] module"] pub type PRIORITY_66 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 66"] pub mod priority_66; -#[doc = "priority_67 (rw) register accessor: PRIORITY Register for interrupt id 67\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_67::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_67::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_67`] +#[doc = "priority_67 (rw) register accessor: PRIORITY Register for interrupt id 67\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_67::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_67::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_67`] module"] pub type PRIORITY_67 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 67"] pub mod priority_67; -#[doc = "priority_68 (rw) register accessor: PRIORITY Register for interrupt id 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_68`] +#[doc = "priority_68 (rw) register accessor: PRIORITY Register for interrupt id 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_68`] module"] pub type PRIORITY_68 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 68"] pub mod priority_68; -#[doc = "priority_69 (rw) register accessor: PRIORITY Register for interrupt id 69\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_69::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_69::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_69`] +#[doc = "priority_69 (rw) register accessor: PRIORITY Register for interrupt id 69\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_69::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_69::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_69`] module"] pub type PRIORITY_69 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 69"] pub mod priority_69; -#[doc = "priority_70 (rw) register accessor: PRIORITY Register for interrupt id 70\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_70::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_70::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_70`] +#[doc = "priority_70 (rw) register accessor: PRIORITY Register for interrupt id 70\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_70::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_70::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_70`] module"] pub type PRIORITY_70 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 70"] pub mod priority_70; -#[doc = "priority_71 (rw) register accessor: PRIORITY Register for interrupt id 71\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_71::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_71::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_71`] +#[doc = "priority_71 (rw) register accessor: PRIORITY Register for interrupt id 71\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_71::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_71::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_71`] module"] pub type PRIORITY_71 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 71"] pub mod priority_71; -#[doc = "priority_72 (rw) register accessor: PRIORITY Register for interrupt id 72\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_72::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_72::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_72`] +#[doc = "priority_72 (rw) register accessor: PRIORITY Register for interrupt id 72\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_72::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_72::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_72`] module"] pub type PRIORITY_72 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 72"] pub mod priority_72; -#[doc = "priority_73 (rw) register accessor: PRIORITY Register for interrupt id 73\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_73::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_73::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_73`] +#[doc = "priority_73 (rw) register accessor: PRIORITY Register for interrupt id 73\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_73::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_73::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_73`] module"] pub type PRIORITY_73 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 73"] pub mod priority_73; -#[doc = "priority_74 (rw) register accessor: PRIORITY Register for interrupt id 74\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_74::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_74::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_74`] +#[doc = "priority_74 (rw) register accessor: PRIORITY Register for interrupt id 74\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_74::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_74::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_74`] module"] pub type PRIORITY_74 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 74"] pub mod priority_74; -#[doc = "priority_75 (rw) register accessor: PRIORITY Register for interrupt id 75\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_75::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_75::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_75`] +#[doc = "priority_75 (rw) register accessor: PRIORITY Register for interrupt id 75\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_75::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_75::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_75`] module"] pub type PRIORITY_75 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 75"] pub mod priority_75; -#[doc = "priority_76 (rw) register accessor: PRIORITY Register for interrupt id 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_76`] +#[doc = "priority_76 (rw) register accessor: PRIORITY Register for interrupt id 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_76`] module"] pub type PRIORITY_76 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 76"] pub mod priority_76; -#[doc = "priority_77 (rw) register accessor: PRIORITY Register for interrupt id 77\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_77::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_77::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_77`] +#[doc = "priority_77 (rw) register accessor: PRIORITY Register for interrupt id 77\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_77::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_77::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_77`] module"] pub type PRIORITY_77 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 77"] pub mod priority_77; -#[doc = "priority_78 (rw) register accessor: PRIORITY Register for interrupt id 78\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_78::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_78::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_78`] +#[doc = "priority_78 (rw) register accessor: PRIORITY Register for interrupt id 78\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_78::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_78::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_78`] module"] pub type PRIORITY_78 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 78"] pub mod priority_78; -#[doc = "priority_79 (rw) register accessor: PRIORITY Register for interrupt id 79\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_79::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_79::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_79`] +#[doc = "priority_79 (rw) register accessor: PRIORITY Register for interrupt id 79\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_79::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_79::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_79`] module"] pub type PRIORITY_79 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 79"] pub mod priority_79; -#[doc = "priority_80 (rw) register accessor: PRIORITY Register for interrupt id 80\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_80::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_80::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_80`] +#[doc = "priority_80 (rw) register accessor: PRIORITY Register for interrupt id 80\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_80::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_80::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_80`] module"] pub type PRIORITY_80 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 80"] pub mod priority_80; -#[doc = "priority_81 (rw) register accessor: PRIORITY Register for interrupt id 81\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_81::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_81::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_81`] +#[doc = "priority_81 (rw) register accessor: PRIORITY Register for interrupt id 81\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_81::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_81::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_81`] module"] pub type PRIORITY_81 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 81"] pub mod priority_81; -#[doc = "priority_82 (rw) register accessor: PRIORITY Register for interrupt id 82\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_82::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_82::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_82`] +#[doc = "priority_82 (rw) register accessor: PRIORITY Register for interrupt id 82\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_82::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_82::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_82`] module"] pub type PRIORITY_82 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 82"] pub mod priority_82; -#[doc = "priority_83 (rw) register accessor: PRIORITY Register for interrupt id 83\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_83::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_83::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_83`] +#[doc = "priority_83 (rw) register accessor: PRIORITY Register for interrupt id 83\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_83::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_83::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_83`] module"] pub type PRIORITY_83 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 83"] pub mod priority_83; -#[doc = "priority_84 (rw) register accessor: PRIORITY Register for interrupt id 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_84`] +#[doc = "priority_84 (rw) register accessor: PRIORITY Register for interrupt id 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_84`] module"] pub type PRIORITY_84 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 84"] pub mod priority_84; -#[doc = "priority_85 (rw) register accessor: PRIORITY Register for interrupt id 85\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_85::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_85::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_85`] +#[doc = "priority_85 (rw) register accessor: PRIORITY Register for interrupt id 85\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_85::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_85::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_85`] module"] pub type PRIORITY_85 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 85"] pub mod priority_85; -#[doc = "priority_86 (rw) register accessor: PRIORITY Register for interrupt id 86\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_86::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_86::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_86`] +#[doc = "priority_86 (rw) register accessor: PRIORITY Register for interrupt id 86\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_86::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_86::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_86`] module"] pub type PRIORITY_86 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 86"] pub mod priority_86; -#[doc = "priority_87 (rw) register accessor: PRIORITY Register for interrupt id 87\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_87::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_87::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_87`] +#[doc = "priority_87 (rw) register accessor: PRIORITY Register for interrupt id 87\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_87::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_87::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_87`] module"] pub type PRIORITY_87 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 87"] pub mod priority_87; -#[doc = "priority_88 (rw) register accessor: PRIORITY Register for interrupt id 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_88`] +#[doc = "priority_88 (rw) register accessor: PRIORITY Register for interrupt id 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_88`] module"] pub type PRIORITY_88 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 88"] pub mod priority_88; -#[doc = "priority_89 (rw) register accessor: PRIORITY Register for interrupt id 89\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_89::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_89::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_89`] +#[doc = "priority_89 (rw) register accessor: PRIORITY Register for interrupt id 89\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_89::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_89::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_89`] module"] pub type PRIORITY_89 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 89"] pub mod priority_89; -#[doc = "priority_90 (rw) register accessor: PRIORITY Register for interrupt id 90\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_90::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_90::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_90`] +#[doc = "priority_90 (rw) register accessor: PRIORITY Register for interrupt id 90\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_90::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_90::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_90`] module"] pub type PRIORITY_90 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 90"] pub mod priority_90; -#[doc = "priority_91 (rw) register accessor: PRIORITY Register for interrupt id 91\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_91::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_91::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_91`] +#[doc = "priority_91 (rw) register accessor: PRIORITY Register for interrupt id 91\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_91::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_91::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_91`] module"] pub type PRIORITY_91 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 91"] pub mod priority_91; -#[doc = "priority_92 (rw) register accessor: PRIORITY Register for interrupt id 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_92`] +#[doc = "priority_92 (rw) register accessor: PRIORITY Register for interrupt id 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_92`] module"] pub type PRIORITY_92 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 92"] pub mod priority_92; -#[doc = "priority_93 (rw) register accessor: PRIORITY Register for interrupt id 93\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_93::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_93::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_93`] +#[doc = "priority_93 (rw) register accessor: PRIORITY Register for interrupt id 93\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_93::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_93::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_93`] module"] pub type PRIORITY_93 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 93"] pub mod priority_93; -#[doc = "priority_94 (rw) register accessor: PRIORITY Register for interrupt id 94\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_94::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_94::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_94`] +#[doc = "priority_94 (rw) register accessor: PRIORITY Register for interrupt id 94\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_94::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_94::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_94`] module"] pub type PRIORITY_94 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 94"] pub mod priority_94; -#[doc = "priority_95 (rw) register accessor: PRIORITY Register for interrupt id 95\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_95::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_95::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_95`] +#[doc = "priority_95 (rw) register accessor: PRIORITY Register for interrupt id 95\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_95::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_95::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_95`] module"] pub type PRIORITY_95 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 95"] pub mod priority_95; -#[doc = "priority_96 (rw) register accessor: PRIORITY Register for interrupt id 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_96`] +#[doc = "priority_96 (rw) register accessor: PRIORITY Register for interrupt id 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_96`] module"] pub type PRIORITY_96 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 96"] pub mod priority_96; -#[doc = "priority_97 (rw) register accessor: PRIORITY Register for interrupt id 97\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_97::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_97::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_97`] +#[doc = "priority_97 (rw) register accessor: PRIORITY Register for interrupt id 97\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_97::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_97::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_97`] module"] pub type PRIORITY_97 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 97"] pub mod priority_97; -#[doc = "priority_98 (rw) register accessor: PRIORITY Register for interrupt id 98\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_98::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_98::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_98`] +#[doc = "priority_98 (rw) register accessor: PRIORITY Register for interrupt id 98\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_98::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_98::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_98`] module"] pub type PRIORITY_98 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 98"] pub mod priority_98; -#[doc = "priority_99 (rw) register accessor: PRIORITY Register for interrupt id 99\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_99::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_99::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_99`] +#[doc = "priority_99 (rw) register accessor: PRIORITY Register for interrupt id 99\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_99::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_99::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_99`] module"] pub type PRIORITY_99 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 99"] pub mod priority_99; -#[doc = "priority_100 (rw) register accessor: PRIORITY Register for interrupt id 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_100`] +#[doc = "priority_100 (rw) register accessor: PRIORITY Register for interrupt id 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_100`] module"] pub type PRIORITY_100 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 100"] pub mod priority_100; -#[doc = "priority_101 (rw) register accessor: PRIORITY Register for interrupt id 101\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_101::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_101::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_101`] +#[doc = "priority_101 (rw) register accessor: PRIORITY Register for interrupt id 101\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_101::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_101::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_101`] module"] pub type PRIORITY_101 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 101"] pub mod priority_101; -#[doc = "priority_102 (rw) register accessor: PRIORITY Register for interrupt id 102\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_102::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_102::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_102`] +#[doc = "priority_102 (rw) register accessor: PRIORITY Register for interrupt id 102\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_102::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_102::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_102`] module"] pub type PRIORITY_102 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 102"] pub mod priority_102; -#[doc = "priority_103 (rw) register accessor: PRIORITY Register for interrupt id 103\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_103::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_103::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_103`] +#[doc = "priority_103 (rw) register accessor: PRIORITY Register for interrupt id 103\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_103::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_103::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_103`] module"] pub type PRIORITY_103 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 103"] pub mod priority_103; -#[doc = "priority_104 (rw) register accessor: PRIORITY Register for interrupt id 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_104`] +#[doc = "priority_104 (rw) register accessor: PRIORITY Register for interrupt id 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_104`] module"] pub type PRIORITY_104 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 104"] pub mod priority_104; -#[doc = "priority_105 (rw) register accessor: PRIORITY Register for interrupt id 105\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_105::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_105::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_105`] +#[doc = "priority_105 (rw) register accessor: PRIORITY Register for interrupt id 105\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_105::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_105::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_105`] module"] pub type PRIORITY_105 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 105"] pub mod priority_105; -#[doc = "priority_106 (rw) register accessor: PRIORITY Register for interrupt id 106\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_106::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_106::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_106`] +#[doc = "priority_106 (rw) register accessor: PRIORITY Register for interrupt id 106\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_106::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_106::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_106`] module"] pub type PRIORITY_106 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 106"] pub mod priority_106; -#[doc = "priority_107 (rw) register accessor: PRIORITY Register for interrupt id 107\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_107::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_107::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_107`] +#[doc = "priority_107 (rw) register accessor: PRIORITY Register for interrupt id 107\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_107::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_107::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_107`] module"] pub type PRIORITY_107 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 107"] pub mod priority_107; -#[doc = "priority_108 (rw) register accessor: PRIORITY Register for interrupt id 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_108`] +#[doc = "priority_108 (rw) register accessor: PRIORITY Register for interrupt id 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_108`] module"] pub type PRIORITY_108 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 108"] pub mod priority_108; -#[doc = "priority_109 (rw) register accessor: PRIORITY Register for interrupt id 109\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_109::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_109::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_109`] +#[doc = "priority_109 (rw) register accessor: PRIORITY Register for interrupt id 109\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_109::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_109::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_109`] module"] pub type PRIORITY_109 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 109"] pub mod priority_109; -#[doc = "priority_110 (rw) register accessor: PRIORITY Register for interrupt id 110\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_110::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_110::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_110`] +#[doc = "priority_110 (rw) register accessor: PRIORITY Register for interrupt id 110\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_110::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_110::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_110`] module"] pub type PRIORITY_110 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 110"] pub mod priority_110; -#[doc = "priority_111 (rw) register accessor: PRIORITY Register for interrupt id 111\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_111::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_111::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_111`] +#[doc = "priority_111 (rw) register accessor: PRIORITY Register for interrupt id 111\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_111::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_111::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_111`] module"] pub type PRIORITY_111 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 111"] pub mod priority_111; -#[doc = "priority_112 (rw) register accessor: PRIORITY Register for interrupt id 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_112`] +#[doc = "priority_112 (rw) register accessor: PRIORITY Register for interrupt id 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_112`] module"] pub type PRIORITY_112 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 112"] pub mod priority_112; -#[doc = "priority_113 (rw) register accessor: PRIORITY Register for interrupt id 113\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_113::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_113::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_113`] +#[doc = "priority_113 (rw) register accessor: PRIORITY Register for interrupt id 113\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_113::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_113::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_113`] module"] pub type PRIORITY_113 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 113"] pub mod priority_113; -#[doc = "priority_114 (rw) register accessor: PRIORITY Register for interrupt id 114\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_114::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_114::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_114`] +#[doc = "priority_114 (rw) register accessor: PRIORITY Register for interrupt id 114\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_114::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_114::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_114`] module"] pub type PRIORITY_114 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 114"] pub mod priority_114; -#[doc = "priority_115 (rw) register accessor: PRIORITY Register for interrupt id 115\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_115::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_115::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_115`] +#[doc = "priority_115 (rw) register accessor: PRIORITY Register for interrupt id 115\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_115::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_115::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_115`] module"] pub type PRIORITY_115 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 115"] pub mod priority_115; -#[doc = "priority_116 (rw) register accessor: PRIORITY Register for interrupt id 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_116`] +#[doc = "priority_116 (rw) register accessor: PRIORITY Register for interrupt id 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_116`] module"] pub type PRIORITY_116 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 116"] pub mod priority_116; -#[doc = "priority_117 (rw) register accessor: PRIORITY Register for interrupt id 117\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_117::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_117::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_117`] +#[doc = "priority_117 (rw) register accessor: PRIORITY Register for interrupt id 117\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_117::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_117::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_117`] module"] pub type PRIORITY_117 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 117"] pub mod priority_117; -#[doc = "priority_118 (rw) register accessor: PRIORITY Register for interrupt id 118\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_118::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_118::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_118`] +#[doc = "priority_118 (rw) register accessor: PRIORITY Register for interrupt id 118\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_118::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_118::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_118`] module"] pub type PRIORITY_118 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 118"] pub mod priority_118; -#[doc = "priority_119 (rw) register accessor: PRIORITY Register for interrupt id 119\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_119::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_119::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_119`] +#[doc = "priority_119 (rw) register accessor: PRIORITY Register for interrupt id 119\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_119::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_119::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_119`] module"] pub type PRIORITY_119 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 119"] pub mod priority_119; -#[doc = "priority_120 (rw) register accessor: PRIORITY Register for interrupt id 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_120`] +#[doc = "priority_120 (rw) register accessor: PRIORITY Register for interrupt id 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_120`] module"] pub type PRIORITY_120 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 120"] pub mod priority_120; -#[doc = "priority_121 (rw) register accessor: PRIORITY Register for interrupt id 121\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_121::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_121::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_121`] +#[doc = "priority_121 (rw) register accessor: PRIORITY Register for interrupt id 121\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_121::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_121::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_121`] module"] pub type PRIORITY_121 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 121"] pub mod priority_121; -#[doc = "priority_122 (rw) register accessor: PRIORITY Register for interrupt id 122\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_122::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_122::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_122`] +#[doc = "priority_122 (rw) register accessor: PRIORITY Register for interrupt id 122\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_122::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_122::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_122`] module"] pub type PRIORITY_122 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 122"] pub mod priority_122; -#[doc = "priority_123 (rw) register accessor: PRIORITY Register for interrupt id 123\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_123::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_123::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_123`] +#[doc = "priority_123 (rw) register accessor: PRIORITY Register for interrupt id 123\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_123::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_123::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_123`] module"] pub type PRIORITY_123 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 123"] pub mod priority_123; -#[doc = "priority_124 (rw) register accessor: PRIORITY Register for interrupt id 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_124`] +#[doc = "priority_124 (rw) register accessor: PRIORITY Register for interrupt id 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_124`] module"] pub type PRIORITY_124 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 124"] pub mod priority_124; -#[doc = "priority_125 (rw) register accessor: PRIORITY Register for interrupt id 125\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_125::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_125::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_125`] +#[doc = "priority_125 (rw) register accessor: PRIORITY Register for interrupt id 125\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_125::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_125::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_125`] module"] pub type PRIORITY_125 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 125"] pub mod priority_125; -#[doc = "priority_126 (rw) register accessor: PRIORITY Register for interrupt id 126\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_126::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_126::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_126`] +#[doc = "priority_126 (rw) register accessor: PRIORITY Register for interrupt id 126\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_126::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_126::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_126`] module"] pub type PRIORITY_126 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 126"] pub mod priority_126; -#[doc = "priority_127 (rw) register accessor: PRIORITY Register for interrupt id 127\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_127::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_127::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_127`] +#[doc = "priority_127 (rw) register accessor: PRIORITY Register for interrupt id 127\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_127::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_127::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_127`] module"] pub type PRIORITY_127 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 127"] pub mod priority_127; -#[doc = "priority_128 (rw) register accessor: PRIORITY Register for interrupt id 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_128`] +#[doc = "priority_128 (rw) register accessor: PRIORITY Register for interrupt id 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_128`] module"] pub type PRIORITY_128 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 128"] pub mod priority_128; -#[doc = "priority_129 (rw) register accessor: PRIORITY Register for interrupt id 129\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_129::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_129::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_129`] +#[doc = "priority_129 (rw) register accessor: PRIORITY Register for interrupt id 129\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_129::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_129::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_129`] module"] pub type PRIORITY_129 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 129"] pub mod priority_129; -#[doc = "priority_130 (rw) register accessor: PRIORITY Register for interrupt id 130\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_130::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_130::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_130`] +#[doc = "priority_130 (rw) register accessor: PRIORITY Register for interrupt id 130\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_130::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_130::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_130`] module"] pub type PRIORITY_130 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 130"] pub mod priority_130; -#[doc = "priority_131 (rw) register accessor: PRIORITY Register for interrupt id 131\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_131::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_131::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_131`] +#[doc = "priority_131 (rw) register accessor: PRIORITY Register for interrupt id 131\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_131::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_131::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_131`] module"] pub type PRIORITY_131 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 131"] pub mod priority_131; -#[doc = "priority_132 (rw) register accessor: PRIORITY Register for interrupt id 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_132::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_132::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_132`] +#[doc = "priority_132 (rw) register accessor: PRIORITY Register for interrupt id 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_132::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_132::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_132`] module"] pub type PRIORITY_132 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 132"] pub mod priority_132; -#[doc = "priority_133 (rw) register accessor: PRIORITY Register for interrupt id 133\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_133::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_133::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_133`] +#[doc = "priority_133 (rw) register accessor: PRIORITY Register for interrupt id 133\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_133::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_133::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_133`] module"] pub type PRIORITY_133 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 133"] pub mod priority_133; -#[doc = "priority_134 (rw) register accessor: PRIORITY Register for interrupt id 134\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_134::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_134::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_134`] +#[doc = "priority_134 (rw) register accessor: PRIORITY Register for interrupt id 134\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_134::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_134::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_134`] module"] pub type PRIORITY_134 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 134"] pub mod priority_134; -#[doc = "priority_135 (rw) register accessor: PRIORITY Register for interrupt id 135\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_135::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_135::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_135`] +#[doc = "priority_135 (rw) register accessor: PRIORITY Register for interrupt id 135\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_135::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_135::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_135`] module"] pub type PRIORITY_135 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 135"] pub mod priority_135; -#[doc = "priority_136 (rw) register accessor: PRIORITY Register for interrupt id 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_136`] +#[doc = "priority_136 (rw) register accessor: PRIORITY Register for interrupt id 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_136`] module"] pub type PRIORITY_136 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 136"] pub mod priority_136; -#[doc = "pending_0 (rw) register accessor: PENDING Register for interrupt ids 31 to 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pending_0`] +#[doc = "pending_0 (rw) register accessor: PENDING Register for interrupt ids 31 to 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_0`] module"] pub type PENDING_0 = crate::Reg; #[doc = "PENDING Register for interrupt ids 31 to 0"] pub mod pending_0; -#[doc = "pending_1 (rw) register accessor: PENDING Register for interrupt ids 63 to 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pending_1`] +#[doc = "pending_1 (rw) register accessor: PENDING Register for interrupt ids 63 to 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_1`] module"] pub type PENDING_1 = crate::Reg; #[doc = "PENDING Register for interrupt ids 63 to 32"] pub mod pending_1; -#[doc = "pending_2 (rw) register accessor: PENDING Register for interrupt ids 95 to 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pending_2`] +#[doc = "pending_2 (rw) register accessor: PENDING Register for interrupt ids 95 to 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_2`] module"] pub type PENDING_2 = crate::Reg; #[doc = "PENDING Register for interrupt ids 95 to 64"] pub mod pending_2; -#[doc = "pending_3 (rw) register accessor: PENDING Register for interrupt ids 127 to 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pending_3`] +#[doc = "pending_3 (rw) register accessor: PENDING Register for interrupt ids 127 to 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_3`] module"] pub type PENDING_3 = crate::Reg; #[doc = "PENDING Register for interrupt ids 127 to 96"] pub mod pending_3; -#[doc = "pending_4 (rw) register accessor: PENDING Register for interrupt ids 136 to 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pending_4`] +#[doc = "pending_4 (rw) register accessor: PENDING Register for interrupt ids 136 to 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_4`] module"] pub type PENDING_4 = crate::Reg; #[doc = "PENDING Register for interrupt ids 136 to 128"] pub mod pending_4; -#[doc = "enable_0_0 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_0_0`] +#[doc = "enable_0_0 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_0_0`] module"] pub type ENABLE_0_0 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 31 to 0 for hart 0"] pub mod enable_0_0; -#[doc = "enable_1_0 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_1_0`] +#[doc = "enable_1_0 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_1_0`] module"] pub type ENABLE_1_0 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 63 to 32 for hart 0"] pub mod enable_1_0; -#[doc = "enable_2_0 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_2_0`] +#[doc = "enable_2_0 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_2_0`] module"] pub type ENABLE_2_0 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 95 to 64 for hart 0"] pub mod enable_2_0; -#[doc = "enable_3_0 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_3_0`] +#[doc = "enable_3_0 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_3_0`] module"] pub type ENABLE_3_0 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 127 to 96 for hart 0"] pub mod enable_3_0; -#[doc = "enable_4_0 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_4_0`] +#[doc = "enable_4_0 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_4_0`] module"] pub type ENABLE_4_0 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 136 to 128 for hart 0"] pub mod enable_4_0; -#[doc = "enable_0_1 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_0_1`] +#[doc = "enable_0_1 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_0_1`] module"] pub type ENABLE_0_1 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 31 to 0 for hart 1"] pub mod enable_0_1; -#[doc = "enable_1_1 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_1_1`] +#[doc = "enable_1_1 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_1_1`] module"] pub type ENABLE_1_1 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 63 to 32 for hart 1"] pub mod enable_1_1; -#[doc = "enable_2_1 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_2_1`] +#[doc = "enable_2_1 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_2_1`] module"] pub type ENABLE_2_1 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 95 to 64 for hart 1"] pub mod enable_2_1; -#[doc = "enable_3_1 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_3_1`] +#[doc = "enable_3_1 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_3_1`] module"] pub type ENABLE_3_1 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 127 to 96 for hart 1"] pub mod enable_3_1; -#[doc = "enable_4_1 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_4_1`] +#[doc = "enable_4_1 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_4_1`] module"] pub type ENABLE_4_1 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 136 to 128 for hart 1"] pub mod enable_4_1; -#[doc = "enable_0_2 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_0_2`] +#[doc = "enable_0_2 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_0_2`] module"] pub type ENABLE_0_2 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 31 to 0 for hart 2"] pub mod enable_0_2; -#[doc = "enable_1_2 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_1_2`] +#[doc = "enable_1_2 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_1_2`] module"] pub type ENABLE_1_2 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 63 to 32 for hart 2"] pub mod enable_1_2; -#[doc = "enable_2_2 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_2_2`] +#[doc = "enable_2_2 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_2_2`] module"] pub type ENABLE_2_2 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 95 to 64 for hart 2"] pub mod enable_2_2; -#[doc = "enable_3_2 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_3_2`] +#[doc = "enable_3_2 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_3_2`] module"] pub type ENABLE_3_2 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 127 to 96 for hart 2"] pub mod enable_3_2; -#[doc = "enable_4_2 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_4_2`] +#[doc = "enable_4_2 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_4_2`] module"] pub type ENABLE_4_2 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 136 to 128 for hart 2"] pub mod enable_4_2; -#[doc = "enable_0_3 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_0_3`] +#[doc = "enable_0_3 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_0_3`] module"] pub type ENABLE_0_3 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 31 to 0 for hart 3"] pub mod enable_0_3; -#[doc = "enable_1_3 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_1_3`] +#[doc = "enable_1_3 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_1_3`] module"] pub type ENABLE_1_3 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 63 to 32 for hart 3"] pub mod enable_1_3; -#[doc = "enable_2_3 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_2_3`] +#[doc = "enable_2_3 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_2_3`] module"] pub type ENABLE_2_3 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 95 to 64 for hart 3"] pub mod enable_2_3; -#[doc = "enable_3_3 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_3_3`] +#[doc = "enable_3_3 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_3_3`] module"] pub type ENABLE_3_3 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 127 to 96 for hart 3"] pub mod enable_3_3; -#[doc = "enable_4_3 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_4_3`] +#[doc = "enable_4_3 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_4_3`] module"] pub type ENABLE_4_3 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 136 to 128 for hart 3"] pub mod enable_4_3; -#[doc = "enable_0_4 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_0_4`] +#[doc = "enable_0_4 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_0_4`] module"] pub type ENABLE_0_4 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 31 to 0 for hart 4"] pub mod enable_0_4; -#[doc = "enable_1_4 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_1_4`] +#[doc = "enable_1_4 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_1_4`] module"] pub type ENABLE_1_4 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 63 to 32 for hart 4"] pub mod enable_1_4; -#[doc = "enable_2_4 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_2_4`] +#[doc = "enable_2_4 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_2_4`] module"] pub type ENABLE_2_4 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 95 to 64 for hart 4"] pub mod enable_2_4; -#[doc = "enable_3_4 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_3_4`] +#[doc = "enable_3_4 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_3_4`] module"] pub type ENABLE_3_4 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 127 to 96 for hart 4"] pub mod enable_3_4; -#[doc = "enable_4_4 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_4_4`] +#[doc = "enable_4_4 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_4_4`] module"] pub type ENABLE_4_4 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 136 to 128 for hart 4"] pub mod enable_4_4; -#[doc = "threshold_0 (rw) register accessor: PRIORITY THRESHOLD Register for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`threshold_0`] +#[doc = "threshold_0 (rw) register accessor: PRIORITY THRESHOLD Register for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@threshold_0`] module"] pub type THRESHOLD_0 = crate::Reg; #[doc = "PRIORITY THRESHOLD Register for hart 0"] pub mod threshold_0; -#[doc = "claimplete_0 (rw) register accessor: CLAIM and COMPLETE Register for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`claimplete_0`] +#[doc = "claimplete_0 (rw) register accessor: CLAIM and COMPLETE Register for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@claimplete_0`] module"] pub type CLAIMPLETE_0 = crate::Reg; #[doc = "CLAIM and COMPLETE Register for hart 0"] pub mod claimplete_0; -#[doc = "threshold_1 (rw) register accessor: PRIORITY THRESHOLD Register for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`threshold_1`] +#[doc = "threshold_1 (rw) register accessor: PRIORITY THRESHOLD Register for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@threshold_1`] module"] pub type THRESHOLD_1 = crate::Reg; #[doc = "PRIORITY THRESHOLD Register for hart 1"] pub mod threshold_1; -#[doc = "claimplete_1 (rw) register accessor: CLAIM and COMPLETE Register for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`claimplete_1`] +#[doc = "claimplete_1 (rw) register accessor: CLAIM and COMPLETE Register for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@claimplete_1`] module"] pub type CLAIMPLETE_1 = crate::Reg; #[doc = "CLAIM and COMPLETE Register for hart 1"] pub mod claimplete_1; -#[doc = "threshold_2 (rw) register accessor: PRIORITY THRESHOLD Register for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`threshold_2`] +#[doc = "threshold_2 (rw) register accessor: PRIORITY THRESHOLD Register for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@threshold_2`] module"] pub type THRESHOLD_2 = crate::Reg; #[doc = "PRIORITY THRESHOLD Register for hart 2"] pub mod threshold_2; -#[doc = "claimplete_2 (rw) register accessor: CLAIM and COMPLETE Register for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`claimplete_2`] +#[doc = "claimplete_2 (rw) register accessor: CLAIM and COMPLETE Register for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@claimplete_2`] module"] pub type CLAIMPLETE_2 = crate::Reg; #[doc = "CLAIM and COMPLETE Register for hart 2"] pub mod claimplete_2; -#[doc = "threshold_3 (rw) register accessor: PRIORITY THRESHOLD Register for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`threshold_3`] +#[doc = "threshold_3 (rw) register accessor: PRIORITY THRESHOLD Register for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@threshold_3`] module"] pub type THRESHOLD_3 = crate::Reg; #[doc = "PRIORITY THRESHOLD Register for hart 3"] pub mod threshold_3; -#[doc = "claimplete_3 (rw) register accessor: CLAIM and COMPLETE Register for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`claimplete_3`] +#[doc = "claimplete_3 (rw) register accessor: CLAIM and COMPLETE Register for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@claimplete_3`] module"] pub type CLAIMPLETE_3 = crate::Reg; #[doc = "CLAIM and COMPLETE Register for hart 3"] pub mod claimplete_3; -#[doc = "threshold_4 (rw) register accessor: PRIORITY THRESHOLD Register for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`threshold_4`] +#[doc = "threshold_4 (rw) register accessor: PRIORITY THRESHOLD Register for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@threshold_4`] module"] pub type THRESHOLD_4 = crate::Reg; #[doc = "PRIORITY THRESHOLD Register for hart 4"] pub mod threshold_4; -#[doc = "claimplete_4 (rw) register accessor: CLAIM and COMPLETE Register for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`claimplete_4`] +#[doc = "claimplete_4 (rw) register accessor: CLAIM and COMPLETE Register for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@claimplete_4`] module"] pub type CLAIMPLETE_4 = crate::Reg; #[doc = "CLAIM and COMPLETE Register for hart 4"] diff --git a/jh7110-vf2-12a-pac/src/plic/claimplete_0.rs b/jh7110-vf2-12a-pac/src/plic/claimplete_0.rs index 8c7b2a1..309a345 100644 --- a/jh7110-vf2-12a-pac/src/plic/claimplete_0.rs +++ b/jh7110-vf2-12a-pac/src/plic/claimplete_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/claimplete_1.rs b/jh7110-vf2-12a-pac/src/plic/claimplete_1.rs index d25d107..71b03ed 100644 --- a/jh7110-vf2-12a-pac/src/plic/claimplete_1.rs +++ b/jh7110-vf2-12a-pac/src/plic/claimplete_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/claimplete_2.rs b/jh7110-vf2-12a-pac/src/plic/claimplete_2.rs index df5f3c6..b8c77a7 100644 --- a/jh7110-vf2-12a-pac/src/plic/claimplete_2.rs +++ b/jh7110-vf2-12a-pac/src/plic/claimplete_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/claimplete_3.rs b/jh7110-vf2-12a-pac/src/plic/claimplete_3.rs index 9980c87..77ba974 100644 --- a/jh7110-vf2-12a-pac/src/plic/claimplete_3.rs +++ b/jh7110-vf2-12a-pac/src/plic/claimplete_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/claimplete_4.rs b/jh7110-vf2-12a-pac/src/plic/claimplete_4.rs index 43b2a4a..5ee1c30 100644 --- a/jh7110-vf2-12a-pac/src/plic/claimplete_4.rs +++ b/jh7110-vf2-12a-pac/src/plic/claimplete_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_0_0.rs b/jh7110-vf2-12a-pac/src/plic/enable_0_0.rs index 9133aae..4a37545 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_0_0.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_0_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_0_1.rs b/jh7110-vf2-12a-pac/src/plic/enable_0_1.rs index 4f9e123..f8c0460 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_0_1.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_0_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_0_2.rs b/jh7110-vf2-12a-pac/src/plic/enable_0_2.rs index 5244d6d..bc1016b 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_0_2.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_0_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_0_3.rs b/jh7110-vf2-12a-pac/src/plic/enable_0_3.rs index 9368da5..6918758 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_0_3.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_0_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_0_4.rs b/jh7110-vf2-12a-pac/src/plic/enable_0_4.rs index 65619b0..d1825e0 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_0_4.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_0_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_1_0.rs b/jh7110-vf2-12a-pac/src/plic/enable_1_0.rs index 56ce5ec..d091de1 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_1_0.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_1_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_1_1.rs b/jh7110-vf2-12a-pac/src/plic/enable_1_1.rs index 5e51188..a03d978 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_1_1.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_1_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_1_2.rs b/jh7110-vf2-12a-pac/src/plic/enable_1_2.rs index 7a53a26..2c1899e 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_1_2.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_1_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_1_3.rs b/jh7110-vf2-12a-pac/src/plic/enable_1_3.rs index faedbfd..e962578 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_1_3.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_1_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_1_4.rs b/jh7110-vf2-12a-pac/src/plic/enable_1_4.rs index 70387de..57ad871 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_1_4.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_1_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_2_0.rs b/jh7110-vf2-12a-pac/src/plic/enable_2_0.rs index 6020e35..1691b10 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_2_0.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_2_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_2_1.rs b/jh7110-vf2-12a-pac/src/plic/enable_2_1.rs index 61e1ddf..c909155 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_2_1.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_2_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_2_2.rs b/jh7110-vf2-12a-pac/src/plic/enable_2_2.rs index 32c1275..9983cf7 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_2_2.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_2_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_2_3.rs b/jh7110-vf2-12a-pac/src/plic/enable_2_3.rs index 117eb71..6c59c83 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_2_3.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_2_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_2_4.rs b/jh7110-vf2-12a-pac/src/plic/enable_2_4.rs index 7e696c5..90b0170 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_2_4.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_2_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_3_0.rs b/jh7110-vf2-12a-pac/src/plic/enable_3_0.rs index 9c95f64..6788c15 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_3_0.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_3_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_3_1.rs b/jh7110-vf2-12a-pac/src/plic/enable_3_1.rs index 275fea8..441f1fe 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_3_1.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_3_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_3_2.rs b/jh7110-vf2-12a-pac/src/plic/enable_3_2.rs index eca95ad..7a3eff1 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_3_2.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_3_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_3_3.rs b/jh7110-vf2-12a-pac/src/plic/enable_3_3.rs index 1a0c02a..29f11f6 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_3_3.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_3_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_3_4.rs b/jh7110-vf2-12a-pac/src/plic/enable_3_4.rs index a787567..cf5a3b6 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_3_4.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_3_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_4_0.rs b/jh7110-vf2-12a-pac/src/plic/enable_4_0.rs index d53199e..f225813 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_4_0.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_4_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_4_1.rs b/jh7110-vf2-12a-pac/src/plic/enable_4_1.rs index d7e9c36..c75a645 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_4_1.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_4_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_4_2.rs b/jh7110-vf2-12a-pac/src/plic/enable_4_2.rs index c5826fb..616309f 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_4_2.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_4_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_4_3.rs b/jh7110-vf2-12a-pac/src/plic/enable_4_3.rs index 3d7f221..88e2dc2 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_4_3.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_4_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/enable_4_4.rs b/jh7110-vf2-12a-pac/src/plic/enable_4_4.rs index d7f4788..18bd59b 100644 --- a/jh7110-vf2-12a-pac/src/plic/enable_4_4.rs +++ b/jh7110-vf2-12a-pac/src/plic/enable_4_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/pending_0.rs b/jh7110-vf2-12a-pac/src/plic/pending_0.rs index d727a23..e716f6e 100644 --- a/jh7110-vf2-12a-pac/src/plic/pending_0.rs +++ b/jh7110-vf2-12a-pac/src/plic/pending_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/pending_1.rs b/jh7110-vf2-12a-pac/src/plic/pending_1.rs index 1ab928f..36eb516 100644 --- a/jh7110-vf2-12a-pac/src/plic/pending_1.rs +++ b/jh7110-vf2-12a-pac/src/plic/pending_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/pending_2.rs b/jh7110-vf2-12a-pac/src/plic/pending_2.rs index 16dc73b..c198eeb 100644 --- a/jh7110-vf2-12a-pac/src/plic/pending_2.rs +++ b/jh7110-vf2-12a-pac/src/plic/pending_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/pending_3.rs b/jh7110-vf2-12a-pac/src/plic/pending_3.rs index 01eca65..031b4d4 100644 --- a/jh7110-vf2-12a-pac/src/plic/pending_3.rs +++ b/jh7110-vf2-12a-pac/src/plic/pending_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/pending_4.rs b/jh7110-vf2-12a-pac/src/plic/pending_4.rs index 89e175d..8398e03 100644 --- a/jh7110-vf2-12a-pac/src/plic/pending_4.rs +++ b/jh7110-vf2-12a-pac/src/plic/pending_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_1.rs b/jh7110-vf2-12a-pac/src/plic/priority_1.rs index 89a2c4c..14af182 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_1.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_10.rs b/jh7110-vf2-12a-pac/src/plic/priority_10.rs index da4d61a..ae62e7f 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_10.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_10.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_100.rs b/jh7110-vf2-12a-pac/src/plic/priority_100.rs index 59cb32e..092d916 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_100.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_100.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_101.rs b/jh7110-vf2-12a-pac/src/plic/priority_101.rs index 6baf61e..5f3d5d8 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_101.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_101.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_102.rs b/jh7110-vf2-12a-pac/src/plic/priority_102.rs index c042534..87e17ba 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_102.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_102.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_103.rs b/jh7110-vf2-12a-pac/src/plic/priority_103.rs index 2c9f028..c03dede 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_103.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_103.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_104.rs b/jh7110-vf2-12a-pac/src/plic/priority_104.rs index 2230d10..deb4152 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_104.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_104.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_105.rs b/jh7110-vf2-12a-pac/src/plic/priority_105.rs index 26c4e2c..08f405c 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_105.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_105.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_106.rs b/jh7110-vf2-12a-pac/src/plic/priority_106.rs index 822f269..3a3be00 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_106.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_106.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_107.rs b/jh7110-vf2-12a-pac/src/plic/priority_107.rs index 6445925..89dbc01 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_107.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_107.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_108.rs b/jh7110-vf2-12a-pac/src/plic/priority_108.rs index 1686dc6..79c2d77 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_108.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_108.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_109.rs b/jh7110-vf2-12a-pac/src/plic/priority_109.rs index dc5e268..c8f90eb 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_109.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_109.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_11.rs b/jh7110-vf2-12a-pac/src/plic/priority_11.rs index 67ed54c..898a24a 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_11.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_11.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_110.rs b/jh7110-vf2-12a-pac/src/plic/priority_110.rs index f2aaaea..daf1b9a 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_110.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_110.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_111.rs b/jh7110-vf2-12a-pac/src/plic/priority_111.rs index 1388d35..1b19243 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_111.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_111.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_112.rs b/jh7110-vf2-12a-pac/src/plic/priority_112.rs index d290c0f..b5fa4ac 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_112.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_112.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_113.rs b/jh7110-vf2-12a-pac/src/plic/priority_113.rs index 10969f5..52df03e 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_113.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_113.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_114.rs b/jh7110-vf2-12a-pac/src/plic/priority_114.rs index eb98b42..7d4fa73 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_114.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_114.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_115.rs b/jh7110-vf2-12a-pac/src/plic/priority_115.rs index 2e7df6f..160973c 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_115.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_115.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_116.rs b/jh7110-vf2-12a-pac/src/plic/priority_116.rs index 45067de..6a44fb4 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_116.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_116.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_117.rs b/jh7110-vf2-12a-pac/src/plic/priority_117.rs index 0d80317..1fcd72e 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_117.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_117.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_118.rs b/jh7110-vf2-12a-pac/src/plic/priority_118.rs index f73de88..0a16f24 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_118.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_118.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_119.rs b/jh7110-vf2-12a-pac/src/plic/priority_119.rs index 4beda48..a27fd7d 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_119.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_119.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_12.rs b/jh7110-vf2-12a-pac/src/plic/priority_12.rs index 15817eb..14597b2 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_12.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_12.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_120.rs b/jh7110-vf2-12a-pac/src/plic/priority_120.rs index 21249b1..071cd28 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_120.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_120.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_121.rs b/jh7110-vf2-12a-pac/src/plic/priority_121.rs index d24778d..aabcf64 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_121.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_121.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_122.rs b/jh7110-vf2-12a-pac/src/plic/priority_122.rs index 463a95f..1f5aee5 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_122.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_122.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_123.rs b/jh7110-vf2-12a-pac/src/plic/priority_123.rs index 46f5339..4a9a3d1 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_123.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_123.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_124.rs b/jh7110-vf2-12a-pac/src/plic/priority_124.rs index 87d348d..6cf6ce0 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_124.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_124.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_125.rs b/jh7110-vf2-12a-pac/src/plic/priority_125.rs index 837d895..902c421 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_125.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_125.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_126.rs b/jh7110-vf2-12a-pac/src/plic/priority_126.rs index 902fc89..7c8c322 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_126.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_126.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_127.rs b/jh7110-vf2-12a-pac/src/plic/priority_127.rs index b0fe334..051179d 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_127.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_127.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_128.rs b/jh7110-vf2-12a-pac/src/plic/priority_128.rs index 6e888f7..4937dfe 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_128.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_128.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_129.rs b/jh7110-vf2-12a-pac/src/plic/priority_129.rs index 5602dad..3a22cda 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_129.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_129.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_13.rs b/jh7110-vf2-12a-pac/src/plic/priority_13.rs index f77071e..1e717fb 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_13.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_13.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_130.rs b/jh7110-vf2-12a-pac/src/plic/priority_130.rs index 72ec4cb..154fb8c 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_130.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_130.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_131.rs b/jh7110-vf2-12a-pac/src/plic/priority_131.rs index 02600ae..3ef39ed 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_131.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_131.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_132.rs b/jh7110-vf2-12a-pac/src/plic/priority_132.rs index cd0928b..e88db40 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_132.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_132.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_133.rs b/jh7110-vf2-12a-pac/src/plic/priority_133.rs index 615c9b9..1f2b499 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_133.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_133.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_134.rs b/jh7110-vf2-12a-pac/src/plic/priority_134.rs index 2514c00..af67dfd 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_134.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_134.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_135.rs b/jh7110-vf2-12a-pac/src/plic/priority_135.rs index a7a3a19..aceba08 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_135.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_135.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_136.rs b/jh7110-vf2-12a-pac/src/plic/priority_136.rs index be5df2a..f135836 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_136.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_136.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_14.rs b/jh7110-vf2-12a-pac/src/plic/priority_14.rs index e7f630a..f36f0e7 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_14.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_14.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_15.rs b/jh7110-vf2-12a-pac/src/plic/priority_15.rs index 6f39ea8..c560a75 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_15.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_15.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_16.rs b/jh7110-vf2-12a-pac/src/plic/priority_16.rs index 016251b..ccbb07f 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_16.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_16.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_17.rs b/jh7110-vf2-12a-pac/src/plic/priority_17.rs index 15c9e24..6d68631 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_17.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_17.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_18.rs b/jh7110-vf2-12a-pac/src/plic/priority_18.rs index d9e70c8..7b68752 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_18.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_18.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_19.rs b/jh7110-vf2-12a-pac/src/plic/priority_19.rs index e1cbce8..00ed894 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_19.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_19.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_2.rs b/jh7110-vf2-12a-pac/src/plic/priority_2.rs index 1561743..d0dfb0c 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_2.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_20.rs b/jh7110-vf2-12a-pac/src/plic/priority_20.rs index 4e14bf5..d5b049a 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_20.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_20.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_21.rs b/jh7110-vf2-12a-pac/src/plic/priority_21.rs index b4f712a..fbd03e0 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_21.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_21.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_22.rs b/jh7110-vf2-12a-pac/src/plic/priority_22.rs index adc7327..1a0ef02 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_22.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_22.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_23.rs b/jh7110-vf2-12a-pac/src/plic/priority_23.rs index dee61df..313f17f 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_23.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_23.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_24.rs b/jh7110-vf2-12a-pac/src/plic/priority_24.rs index 2b1d82b..413a617 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_24.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_24.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_25.rs b/jh7110-vf2-12a-pac/src/plic/priority_25.rs index a8f2863..b89a622 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_25.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_25.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_26.rs b/jh7110-vf2-12a-pac/src/plic/priority_26.rs index b67a6fd..98933ba 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_26.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_26.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_27.rs b/jh7110-vf2-12a-pac/src/plic/priority_27.rs index 4c20368..611e611 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_27.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_27.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_28.rs b/jh7110-vf2-12a-pac/src/plic/priority_28.rs index df68c98..e3be6ec 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_28.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_28.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_29.rs b/jh7110-vf2-12a-pac/src/plic/priority_29.rs index a524f03..941b4df 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_29.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_29.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_3.rs b/jh7110-vf2-12a-pac/src/plic/priority_3.rs index 682d6ca..9cf51b3 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_3.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_30.rs b/jh7110-vf2-12a-pac/src/plic/priority_30.rs index b3250f5..3a94aeb 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_30.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_30.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_31.rs b/jh7110-vf2-12a-pac/src/plic/priority_31.rs index c11c081..da4c621 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_31.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_31.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_32.rs b/jh7110-vf2-12a-pac/src/plic/priority_32.rs index 66db062..23c9cc6 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_32.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_32.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_33.rs b/jh7110-vf2-12a-pac/src/plic/priority_33.rs index c2d33cf..68f75fe 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_33.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_33.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_34.rs b/jh7110-vf2-12a-pac/src/plic/priority_34.rs index 7c6575c..16ec987 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_34.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_34.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_35.rs b/jh7110-vf2-12a-pac/src/plic/priority_35.rs index ebc3d7e..bb78a11 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_35.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_35.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_36.rs b/jh7110-vf2-12a-pac/src/plic/priority_36.rs index d45bc5c..934a266 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_36.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_36.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_37.rs b/jh7110-vf2-12a-pac/src/plic/priority_37.rs index 59ad4b9..684e44b 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_37.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_37.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_38.rs b/jh7110-vf2-12a-pac/src/plic/priority_38.rs index 40d64cc..d80810f 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_38.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_38.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_39.rs b/jh7110-vf2-12a-pac/src/plic/priority_39.rs index 3270b4f..4a6ecb7 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_39.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_39.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_4.rs b/jh7110-vf2-12a-pac/src/plic/priority_4.rs index ce93212..f251a12 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_4.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_40.rs b/jh7110-vf2-12a-pac/src/plic/priority_40.rs index 8eb085d..2792352 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_40.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_40.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_41.rs b/jh7110-vf2-12a-pac/src/plic/priority_41.rs index 7e150ae..7c66f0f 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_41.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_41.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_42.rs b/jh7110-vf2-12a-pac/src/plic/priority_42.rs index 7e69daa..a429467 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_42.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_42.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_43.rs b/jh7110-vf2-12a-pac/src/plic/priority_43.rs index 412e4f5..40be5d5 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_43.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_43.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_44.rs b/jh7110-vf2-12a-pac/src/plic/priority_44.rs index 9c412f5..ed41ba6 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_44.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_44.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_45.rs b/jh7110-vf2-12a-pac/src/plic/priority_45.rs index 7638a0a..4596730 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_45.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_45.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_46.rs b/jh7110-vf2-12a-pac/src/plic/priority_46.rs index 251dd67..66c6b21 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_46.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_46.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_47.rs b/jh7110-vf2-12a-pac/src/plic/priority_47.rs index f5f4cfa..7f969c0 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_47.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_47.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_48.rs b/jh7110-vf2-12a-pac/src/plic/priority_48.rs index b1ec29c..cc848bc 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_48.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_48.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_49.rs b/jh7110-vf2-12a-pac/src/plic/priority_49.rs index f37ecf9..962a102 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_49.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_49.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_5.rs b/jh7110-vf2-12a-pac/src/plic/priority_5.rs index ab2392d..066b5be 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_5.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_5.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_50.rs b/jh7110-vf2-12a-pac/src/plic/priority_50.rs index b58ca84..8202647 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_50.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_50.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_51.rs b/jh7110-vf2-12a-pac/src/plic/priority_51.rs index efe3297..e990197 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_51.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_51.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_52.rs b/jh7110-vf2-12a-pac/src/plic/priority_52.rs index 3a59d4d..6de4a93 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_52.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_52.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_53.rs b/jh7110-vf2-12a-pac/src/plic/priority_53.rs index 33065b1..ee1c587 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_53.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_53.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_54.rs b/jh7110-vf2-12a-pac/src/plic/priority_54.rs index b2140fc..ea867e3 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_54.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_54.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_55.rs b/jh7110-vf2-12a-pac/src/plic/priority_55.rs index 8958031..caf4382 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_55.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_55.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_56.rs b/jh7110-vf2-12a-pac/src/plic/priority_56.rs index 574abb0..09057d8 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_56.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_56.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_57.rs b/jh7110-vf2-12a-pac/src/plic/priority_57.rs index 2faa376..dd2d40d 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_57.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_57.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_58.rs b/jh7110-vf2-12a-pac/src/plic/priority_58.rs index a57dbb4..6858abf 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_58.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_58.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_59.rs b/jh7110-vf2-12a-pac/src/plic/priority_59.rs index 1528850..11a98bb 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_59.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_59.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_6.rs b/jh7110-vf2-12a-pac/src/plic/priority_6.rs index ab5418b..89ae6ae 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_6.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_6.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_60.rs b/jh7110-vf2-12a-pac/src/plic/priority_60.rs index d8e5b6d..1f72fc3 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_60.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_60.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_61.rs b/jh7110-vf2-12a-pac/src/plic/priority_61.rs index 9b538df..2050250 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_61.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_61.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_62.rs b/jh7110-vf2-12a-pac/src/plic/priority_62.rs index b104138..565e1be 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_62.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_62.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_63.rs b/jh7110-vf2-12a-pac/src/plic/priority_63.rs index ed1a48e..5a1854f 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_63.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_63.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_64.rs b/jh7110-vf2-12a-pac/src/plic/priority_64.rs index 327d342..a18646a 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_64.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_64.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_65.rs b/jh7110-vf2-12a-pac/src/plic/priority_65.rs index 3dbdc1f..c7ce4a8 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_65.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_65.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_66.rs b/jh7110-vf2-12a-pac/src/plic/priority_66.rs index 7a5cc54..a8b9b96 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_66.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_66.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_67.rs b/jh7110-vf2-12a-pac/src/plic/priority_67.rs index 1d91f1a..503c6fc 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_67.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_67.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_68.rs b/jh7110-vf2-12a-pac/src/plic/priority_68.rs index e538789..bcae2d2 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_68.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_68.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_69.rs b/jh7110-vf2-12a-pac/src/plic/priority_69.rs index 33c3036..c6727bd 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_69.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_69.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_7.rs b/jh7110-vf2-12a-pac/src/plic/priority_7.rs index 59313df..4f781bd 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_7.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_7.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_70.rs b/jh7110-vf2-12a-pac/src/plic/priority_70.rs index bbde1c5..57f263d 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_70.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_70.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_71.rs b/jh7110-vf2-12a-pac/src/plic/priority_71.rs index 510c12d..8b907db 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_71.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_71.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_72.rs b/jh7110-vf2-12a-pac/src/plic/priority_72.rs index d9e146b..df9d8b9 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_72.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_72.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_73.rs b/jh7110-vf2-12a-pac/src/plic/priority_73.rs index 99d2fdf..06b91f1 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_73.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_73.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_74.rs b/jh7110-vf2-12a-pac/src/plic/priority_74.rs index d1fa3dc..14fdec1 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_74.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_74.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_75.rs b/jh7110-vf2-12a-pac/src/plic/priority_75.rs index 7c618ad..3743a49 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_75.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_75.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_76.rs b/jh7110-vf2-12a-pac/src/plic/priority_76.rs index 0a6ee28..5ca57d9 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_76.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_76.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_77.rs b/jh7110-vf2-12a-pac/src/plic/priority_77.rs index 25e404a..c61835d 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_77.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_77.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_78.rs b/jh7110-vf2-12a-pac/src/plic/priority_78.rs index 8fca3e5..c9c7802 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_78.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_78.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_79.rs b/jh7110-vf2-12a-pac/src/plic/priority_79.rs index 2a3dc4f..e55c5bd 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_79.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_79.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_8.rs b/jh7110-vf2-12a-pac/src/plic/priority_8.rs index 5a0bc51..28aabc8 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_8.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_8.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_80.rs b/jh7110-vf2-12a-pac/src/plic/priority_80.rs index 052fb8f..2cfbe0c 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_80.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_80.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_81.rs b/jh7110-vf2-12a-pac/src/plic/priority_81.rs index 894c968..ddc872f 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_81.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_81.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_82.rs b/jh7110-vf2-12a-pac/src/plic/priority_82.rs index 6a6f7cb..554c940 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_82.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_82.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_83.rs b/jh7110-vf2-12a-pac/src/plic/priority_83.rs index 8d1851f..d1e9bbe 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_83.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_83.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_84.rs b/jh7110-vf2-12a-pac/src/plic/priority_84.rs index 09df181..cf97ab5 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_84.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_84.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_85.rs b/jh7110-vf2-12a-pac/src/plic/priority_85.rs index f3231d8..4ad3a05 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_85.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_85.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_86.rs b/jh7110-vf2-12a-pac/src/plic/priority_86.rs index ea7d42c..4dc1ae5 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_86.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_86.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_87.rs b/jh7110-vf2-12a-pac/src/plic/priority_87.rs index f8a4257..88a3b6b 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_87.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_87.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_88.rs b/jh7110-vf2-12a-pac/src/plic/priority_88.rs index 65e64e4..f97b14a 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_88.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_88.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_89.rs b/jh7110-vf2-12a-pac/src/plic/priority_89.rs index 7d49585..0ca387d 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_89.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_89.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_9.rs b/jh7110-vf2-12a-pac/src/plic/priority_9.rs index 24e030b..5704dfa 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_9.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_9.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_90.rs b/jh7110-vf2-12a-pac/src/plic/priority_90.rs index 5e86147..2697019 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_90.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_90.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_91.rs b/jh7110-vf2-12a-pac/src/plic/priority_91.rs index 69ace79..bf640c8 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_91.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_91.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_92.rs b/jh7110-vf2-12a-pac/src/plic/priority_92.rs index d00bb9a..6ea53de 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_92.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_92.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_93.rs b/jh7110-vf2-12a-pac/src/plic/priority_93.rs index 202b810..b6b5394 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_93.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_93.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_94.rs b/jh7110-vf2-12a-pac/src/plic/priority_94.rs index b6149e3..e5af85c 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_94.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_94.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_95.rs b/jh7110-vf2-12a-pac/src/plic/priority_95.rs index aa9eedf..94326ee 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_95.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_95.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_96.rs b/jh7110-vf2-12a-pac/src/plic/priority_96.rs index 68a103a..cdc85e0 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_96.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_96.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_97.rs b/jh7110-vf2-12a-pac/src/plic/priority_97.rs index 25e467e..7595282 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_97.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_97.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_98.rs b/jh7110-vf2-12a-pac/src/plic/priority_98.rs index 491167a..f9bff80 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_98.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_98.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/priority_99.rs b/jh7110-vf2-12a-pac/src/plic/priority_99.rs index 3db062c..66302fe 100644 --- a/jh7110-vf2-12a-pac/src/plic/priority_99.rs +++ b/jh7110-vf2-12a-pac/src/plic/priority_99.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/threshold_0.rs b/jh7110-vf2-12a-pac/src/plic/threshold_0.rs index 72e255d..67e7685 100644 --- a/jh7110-vf2-12a-pac/src/plic/threshold_0.rs +++ b/jh7110-vf2-12a-pac/src/plic/threshold_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/threshold_1.rs b/jh7110-vf2-12a-pac/src/plic/threshold_1.rs index b026258..4ee93ce 100644 --- a/jh7110-vf2-12a-pac/src/plic/threshold_1.rs +++ b/jh7110-vf2-12a-pac/src/plic/threshold_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/threshold_2.rs b/jh7110-vf2-12a-pac/src/plic/threshold_2.rs index 46a0d5e..cb915f7 100644 --- a/jh7110-vf2-12a-pac/src/plic/threshold_2.rs +++ b/jh7110-vf2-12a-pac/src/plic/threshold_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/threshold_3.rs b/jh7110-vf2-12a-pac/src/plic/threshold_3.rs index 04d7d53..96e5722 100644 --- a/jh7110-vf2-12a-pac/src/plic/threshold_3.rs +++ b/jh7110-vf2-12a-pac/src/plic/threshold_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/plic/threshold_4.rs b/jh7110-vf2-12a-pac/src/plic/threshold_4.rs index d85ce7b..933ec87 100644 --- a/jh7110-vf2-12a-pac/src/plic/threshold_4.rs +++ b/jh7110-vf2-12a-pac/src/plic/threshold_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu.rs b/jh7110-vf2-12a-pac/src/pmu.rs index 26e11b8..2a44091 100644 --- a/jh7110-vf2-12a-pac/src/pmu.rs +++ b/jh7110-vf2-12a-pac/src/pmu.rs @@ -2,157 +2,243 @@ #[repr(C)] pub struct RegisterBlock { _reserved0: [u8; 0x04], - #[doc = "0x04 - Hardware Event Turn-On Mask"] - pub hard_event_turn_on_mask: HARD_EVENT_TURN_ON_MASK, + hard_event_turn_on_mask: HARD_EVENT_TURN_ON_MASK, _reserved1: [u8; 0x04], + soft_turn_on_power_mode: SOFT_TURN_ON_POWER_MODE, + soft_turn_off_power_mode: SOFT_TURN_OFF_POWER_MODE, + timeout_seq_thd: TIMEOUT_SEQ_THD, + pdc0: PDC0, + pdc1: PDC1, + pdc2: PDC2, + _reserved7: [u8; 0x20], + sw_encourage: SW_ENCOURAGE, + tim: TIM, + pch_bypass: PCH_BYPASS, + pch_pstate: PCH_PSTATE, + pch_timeout: PCH_TIMEOUT, + lp_timeout: LP_TIMEOUT, + hard_turn_on_power_mode: HARD_TURN_ON_POWER_MODE, + _reserved14: [u8; 0x20], + current_power_mode: CURRENT_POWER_MODE, + current_seq_state: CURRENT_SEQ_STATE, + event_status: EVENT_STATUS, + int_status: INT_STATUS, + hw_event_crd: HW_EVENT_CRD, + encourage_type_crd: ENCOURAGE_TYPE_CRD, + pch_active: PCH_ACTIVE, +} +impl RegisterBlock { + #[doc = "0x04 - Hardware Event Turn-On Mask"] + #[inline(always)] + pub const fn hard_event_turn_on_mask(&self) -> &HARD_EVENT_TURN_ON_MASK { + &self.hard_event_turn_on_mask + } #[doc = "0x0c - Software Turn-On Power Mode"] - pub soft_turn_on_power_mode: SOFT_TURN_ON_POWER_MODE, + #[inline(always)] + pub const fn soft_turn_on_power_mode(&self) -> &SOFT_TURN_ON_POWER_MODE { + &self.soft_turn_on_power_mode + } #[doc = "0x10 - Software Turn-Off Power Mode"] - pub soft_turn_off_power_mode: SOFT_TURN_OFF_POWER_MODE, + #[inline(always)] + pub const fn soft_turn_off_power_mode(&self) -> &SOFT_TURN_OFF_POWER_MODE { + &self.soft_turn_off_power_mode + } #[doc = "0x14 - Threshold Sequence Timeout"] - pub timeout_seq_thd: TIMEOUT_SEQ_THD, + #[inline(always)] + pub const fn timeout_seq_thd(&self) -> &TIMEOUT_SEQ_THD { + &self.timeout_seq_thd + } #[doc = "0x18 - Powerdomain Cascade 0"] - pub pdc0: PDC0, + #[inline(always)] + pub const fn pdc0(&self) -> &PDC0 { + &self.pdc0 + } #[doc = "0x1c - Powerdomain Cascade 1"] - pub pdc1: PDC1, + #[inline(always)] + pub const fn pdc1(&self) -> &PDC1 { + &self.pdc1 + } #[doc = "0x20 - Powerdomain Cascade 2"] - pub pdc2: PDC2, - _reserved7: [u8; 0x20], + #[inline(always)] + pub const fn pdc2(&self) -> &PDC2 { + &self.pdc2 + } #[doc = "0x44 - Software Encouragement"] - pub sw_encourage: SW_ENCOURAGE, + #[inline(always)] + pub const fn sw_encourage(&self) -> &SW_ENCOURAGE { + &self.sw_encourage + } #[doc = "0x48 - TIMER Interrupt Mask"] - pub tim: TIM, + #[inline(always)] + pub const fn tim(&self) -> &TIM { + &self.tim + } #[doc = "0x4c - P-channel Bypass"] - pub pch_bypass: PCH_BYPASS, + #[inline(always)] + pub const fn pch_bypass(&self) -> &PCH_BYPASS { + &self.pch_bypass + } #[doc = "0x50 - P-channel PSTATE"] - pub pch_pstate: PCH_PSTATE, + #[inline(always)] + pub const fn pch_pstate(&self) -> &PCH_PSTATE { + &self.pch_pstate + } #[doc = "0x54 - P-channel Timeout Threshold"] - pub pch_timeout: PCH_TIMEOUT, + #[inline(always)] + pub const fn pch_timeout(&self) -> &PCH_TIMEOUT { + &self.pch_timeout + } #[doc = "0x58 - LP Cell Control Timeout Threshold"] - pub lp_timeout: LP_TIMEOUT, + #[inline(always)] + pub const fn lp_timeout(&self) -> &LP_TIMEOUT { + &self.lp_timeout + } #[doc = "0x5c - Hardware Turn-On Power Mode"] - pub hard_turn_on_power_mode: HARD_TURN_ON_POWER_MODE, - _reserved14: [u8; 0x20], + #[inline(always)] + pub const fn hard_turn_on_power_mode(&self) -> &HARD_TURN_ON_POWER_MODE { + &self.hard_turn_on_power_mode + } #[doc = "0x80 - Current Power Mode"] - pub current_power_mode: CURRENT_POWER_MODE, + #[inline(always)] + pub const fn current_power_mode(&self) -> &CURRENT_POWER_MODE { + &self.current_power_mode + } #[doc = "0x84 - Current Sequence State"] - pub current_seq_state: CURRENT_SEQ_STATE, + #[inline(always)] + pub const fn current_seq_state(&self) -> &CURRENT_SEQ_STATE { + &self.current_seq_state + } #[doc = "0x88 - PMU Event Status"] - pub event_status: EVENT_STATUS, + #[inline(always)] + pub const fn event_status(&self) -> &EVENT_STATUS { + &self.event_status + } #[doc = "0x8c - PMU Interrupt Status"] - pub int_status: INT_STATUS, + #[inline(always)] + pub const fn int_status(&self) -> &INT_STATUS { + &self.int_status + } #[doc = "0x90 - Hardware Event Record"] - pub hw_event_crd: HW_EVENT_CRD, + #[inline(always)] + pub const fn hw_event_crd(&self) -> &HW_EVENT_CRD { + &self.hw_event_crd + } #[doc = "0x94 - Hardware Event Type Record"] - pub encourage_type_crd: ENCOURAGE_TYPE_CRD, + #[inline(always)] + pub const fn encourage_type_crd(&self) -> &ENCOURAGE_TYPE_CRD { + &self.encourage_type_crd + } #[doc = "0x98 - P-channel PACTIVE Status"] - pub pch_active: PCH_ACTIVE, + #[inline(always)] + pub const fn pch_active(&self) -> &PCH_ACTIVE { + &self.pch_active + } } -#[doc = "hard_event_turn_on_mask (rw) register accessor: Hardware Event Turn-On Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hard_event_turn_on_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hard_event_turn_on_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hard_event_turn_on_mask`] +#[doc = "hard_event_turn_on_mask (rw) register accessor: Hardware Event Turn-On Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hard_event_turn_on_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hard_event_turn_on_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hard_event_turn_on_mask`] module"] pub type HARD_EVENT_TURN_ON_MASK = crate::Reg; #[doc = "Hardware Event Turn-On Mask"] pub mod hard_event_turn_on_mask; -#[doc = "soft_turn_on_power_mode (rw) register accessor: Software Turn-On Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_turn_on_power_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_turn_on_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_turn_on_power_mode`] +#[doc = "soft_turn_on_power_mode (rw) register accessor: Software Turn-On Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_turn_on_power_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_turn_on_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_turn_on_power_mode`] module"] pub type SOFT_TURN_ON_POWER_MODE = crate::Reg; #[doc = "Software Turn-On Power Mode"] pub mod soft_turn_on_power_mode; -#[doc = "soft_turn_off_power_mode (rw) register accessor: Software Turn-Off Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_turn_off_power_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_turn_off_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_turn_off_power_mode`] +#[doc = "soft_turn_off_power_mode (rw) register accessor: Software Turn-Off Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_turn_off_power_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_turn_off_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_turn_off_power_mode`] module"] pub type SOFT_TURN_OFF_POWER_MODE = crate::Reg; #[doc = "Software Turn-Off Power Mode"] pub mod soft_turn_off_power_mode; -#[doc = "timeout_seq_thd (rw) register accessor: Threshold Sequence Timeout\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_seq_thd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timeout_seq_thd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`timeout_seq_thd`] +#[doc = "timeout_seq_thd (rw) register accessor: Threshold Sequence Timeout\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_seq_thd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timeout_seq_thd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timeout_seq_thd`] module"] pub type TIMEOUT_SEQ_THD = crate::Reg; #[doc = "Threshold Sequence Timeout"] pub mod timeout_seq_thd; -#[doc = "pdc0 (rw) register accessor: Powerdomain Cascade 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pdc0`] +#[doc = "pdc0 (rw) register accessor: Powerdomain Cascade 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdc0`] module"] pub type PDC0 = crate::Reg; #[doc = "Powerdomain Cascade 0"] pub mod pdc0; -#[doc = "pdc1 (rw) register accessor: Powerdomain Cascade 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pdc1`] +#[doc = "pdc1 (rw) register accessor: Powerdomain Cascade 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdc1`] module"] pub type PDC1 = crate::Reg; #[doc = "Powerdomain Cascade 1"] pub mod pdc1; -#[doc = "pdc2 (rw) register accessor: Powerdomain Cascade 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pdc2`] +#[doc = "pdc2 (rw) register accessor: Powerdomain Cascade 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdc2`] module"] pub type PDC2 = crate::Reg; #[doc = "Powerdomain Cascade 2"] pub mod pdc2; -#[doc = "sw_encourage (rw) register accessor: Software Encouragement\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_encourage::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_encourage::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sw_encourage`] +#[doc = "sw_encourage (rw) register accessor: Software Encouragement\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_encourage::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_encourage::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sw_encourage`] module"] pub type SW_ENCOURAGE = crate::Reg; #[doc = "Software Encouragement"] pub mod sw_encourage; -#[doc = "tim (rw) register accessor: TIMER Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tim`] +#[doc = "tim (rw) register accessor: TIMER Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim`] module"] pub type TIM = crate::Reg; #[doc = "TIMER Interrupt Mask"] pub mod tim; -#[doc = "pch_bypass (rw) register accessor: P-channel Bypass\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_bypass::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pch_bypass`] +#[doc = "pch_bypass (rw) register accessor: P-channel Bypass\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_bypass::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pch_bypass`] module"] pub type PCH_BYPASS = crate::Reg; #[doc = "P-channel Bypass"] pub mod pch_bypass; -#[doc = "pch_pstate (rw) register accessor: P-channel PSTATE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_pstate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_pstate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pch_pstate`] +#[doc = "pch_pstate (rw) register accessor: P-channel PSTATE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_pstate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_pstate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pch_pstate`] module"] pub type PCH_PSTATE = crate::Reg; #[doc = "P-channel PSTATE"] pub mod pch_pstate; -#[doc = "pch_timeout (rw) register accessor: P-channel Timeout Threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pch_timeout`] +#[doc = "pch_timeout (rw) register accessor: P-channel Timeout Threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pch_timeout`] module"] pub type PCH_TIMEOUT = crate::Reg; #[doc = "P-channel Timeout Threshold"] pub mod pch_timeout; -#[doc = "lp_timeout (rw) register accessor: LP Cell Control Timeout Threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lp_timeout`] +#[doc = "lp_timeout (rw) register accessor: LP Cell Control Timeout Threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_timeout`] module"] pub type LP_TIMEOUT = crate::Reg; #[doc = "LP Cell Control Timeout Threshold"] pub mod lp_timeout; -#[doc = "hard_turn_on_power_mode (rw) register accessor: Hardware Turn-On Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hard_turn_on_power_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hard_turn_on_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hard_turn_on_power_mode`] +#[doc = "hard_turn_on_power_mode (rw) register accessor: Hardware Turn-On Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hard_turn_on_power_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hard_turn_on_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hard_turn_on_power_mode`] module"] pub type HARD_TURN_ON_POWER_MODE = crate::Reg; #[doc = "Hardware Turn-On Power Mode"] pub mod hard_turn_on_power_mode; -#[doc = "current_power_mode (rw) register accessor: Current Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`current_power_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`current_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`current_power_mode`] +#[doc = "current_power_mode (rw) register accessor: Current Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`current_power_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`current_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@current_power_mode`] module"] pub type CURRENT_POWER_MODE = crate::Reg; #[doc = "Current Power Mode"] pub mod current_power_mode; -#[doc = "current_seq_state (rw) register accessor: Current Sequence State\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`current_seq_state::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`current_seq_state::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`current_seq_state`] +#[doc = "current_seq_state (rw) register accessor: Current Sequence State\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`current_seq_state::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`current_seq_state::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@current_seq_state`] module"] pub type CURRENT_SEQ_STATE = crate::Reg; #[doc = "Current Sequence State"] pub mod current_seq_state; -#[doc = "event_status (rw) register accessor: PMU Event Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`event_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`event_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`event_status`] +#[doc = "event_status (rw) register accessor: PMU Event Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`event_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`event_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@event_status`] module"] pub type EVENT_STATUS = crate::Reg; #[doc = "PMU Event Status"] pub mod event_status; -#[doc = "int_status (rw) register accessor: PMU Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`int_status`] +#[doc = "int_status (rw) register accessor: PMU Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_status`] module"] pub type INT_STATUS = crate::Reg; #[doc = "PMU Interrupt Status"] pub mod int_status; -#[doc = "hw_event_crd (rw) register accessor: Hardware Event Record\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_event_crd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hw_event_crd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hw_event_crd`] +#[doc = "hw_event_crd (rw) register accessor: Hardware Event Record\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_event_crd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hw_event_crd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_event_crd`] module"] pub type HW_EVENT_CRD = crate::Reg; #[doc = "Hardware Event Record"] pub mod hw_event_crd; -#[doc = "encourage_type_crd (rw) register accessor: Hardware Event Type Record\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`encourage_type_crd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`encourage_type_crd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`encourage_type_crd`] +#[doc = "encourage_type_crd (rw) register accessor: Hardware Event Type Record\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`encourage_type_crd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`encourage_type_crd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@encourage_type_crd`] module"] pub type ENCOURAGE_TYPE_CRD = crate::Reg; #[doc = "Hardware Event Type Record"] pub mod encourage_type_crd; -#[doc = "pch_active (rw) register accessor: P-channel PACTIVE Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_active::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_active::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pch_active`] +#[doc = "pch_active (rw) register accessor: P-channel PACTIVE Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_active::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_active::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pch_active`] module"] pub type PCH_ACTIVE = crate::Reg; #[doc = "P-channel PACTIVE Status"] diff --git a/jh7110-vf2-12a-pac/src/pmu/current_power_mode.rs b/jh7110-vf2-12a-pac/src/pmu/current_power_mode.rs index 7d70502..fa5dad7 100644 --- a/jh7110-vf2-12a-pac/src/pmu/current_power_mode.rs +++ b/jh7110-vf2-12a-pac/src/pmu/current_power_mode.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `systop_power_mode` reader - SYSTOP turn-on power mode."] pub type SYSTOP_POWER_MODE_R = crate::BitReader; #[doc = "Field `systop_power_mode` writer - SYSTOP turn-on power mode."] -pub type SYSTOP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SYSTOP_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `cpu_power_mode` reader - CPU turn-on power mode."] pub type CPU_POWER_MODE_R = crate::BitReader; #[doc = "Field `cpu_power_mode` writer - CPU turn-on power mode."] -pub type CPU_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CPU_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gpua_power_mode` reader - GPUA turn-on power mode."] pub type GPUA_POWER_MODE_R = crate::BitReader; #[doc = "Field `gpua_power_mode` writer - GPUA turn-on power mode."] -pub type GPUA_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GPUA_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `vdec_power_mode` reader - VDEC turn-on power mode."] pub type VDEC_POWER_MODE_R = crate::BitReader; #[doc = "Field `vdec_power_mode` writer - VDEC turn-on power mode."] -pub type VDEC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VDEC_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `vout_power_mode` reader - VOUT turn-on power mode."] pub type VOUT_POWER_MODE_R = crate::BitReader; #[doc = "Field `vout_power_mode` writer - VOUT turn-on power mode."] -pub type VOUT_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VOUT_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `isp_power_mode` reader - ISP turn-on power mode."] pub type ISP_POWER_MODE_R = crate::BitReader; #[doc = "Field `isp_power_mode` writer - ISP turn-on power mode."] -pub type ISP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ISP_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `venc_power_mode` reader - VENC turn-on power mode."] pub type VENC_POWER_MODE_R = crate::BitReader; #[doc = "Field `venc_power_mode` writer - VENC turn-on power mode."] -pub type VENC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VENC_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - SYSTOP turn-on power mode."] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - SYSTOP turn-on power mode."] #[inline(always)] #[must_use] - pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { - SYSTOP_POWER_MODE_W::new(self) + pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { + SYSTOP_POWER_MODE_W::new(self, 0) } #[doc = "Bit 1 - CPU turn-on power mode."] #[inline(always)] #[must_use] - pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { - CPU_POWER_MODE_W::new(self) + pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { + CPU_POWER_MODE_W::new(self, 1) } #[doc = "Bit 2 - GPUA turn-on power mode."] #[inline(always)] #[must_use] - pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { - GPUA_POWER_MODE_W::new(self) + pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { + GPUA_POWER_MODE_W::new(self, 2) } #[doc = "Bit 3 - VDEC turn-on power mode."] #[inline(always)] #[must_use] - pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { - VDEC_POWER_MODE_W::new(self) + pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { + VDEC_POWER_MODE_W::new(self, 3) } #[doc = "Bit 4 - VOUT turn-on power mode."] #[inline(always)] #[must_use] - pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { - VOUT_POWER_MODE_W::new(self) + pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { + VOUT_POWER_MODE_W::new(self, 4) } #[doc = "Bit 5 - ISP turn-on power mode."] #[inline(always)] #[must_use] - pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { - ISP_POWER_MODE_W::new(self) + pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { + ISP_POWER_MODE_W::new(self, 5) } #[doc = "Bit 6 - VENC turn-on power mode."] #[inline(always)] #[must_use] - pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { - VENC_POWER_MODE_W::new(self) + pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { + VENC_POWER_MODE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/current_seq_state.rs b/jh7110-vf2-12a-pac/src/pmu/current_seq_state.rs index de5ac6c..4534c7b 100644 --- a/jh7110-vf2-12a-pac/src/pmu/current_seq_state.rs +++ b/jh7110-vf2-12a-pac/src/pmu/current_seq_state.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/encourage_type_crd.rs b/jh7110-vf2-12a-pac/src/pmu/encourage_type_crd.rs index 1aff2c2..d32a1c9 100644 --- a/jh7110-vf2-12a-pac/src/pmu/encourage_type_crd.rs +++ b/jh7110-vf2-12a-pac/src/pmu/encourage_type_crd.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/event_status.rs b/jh7110-vf2-12a-pac/src/pmu/event_status.rs index 8fdbd4c..c34a9b6 100644 --- a/jh7110-vf2-12a-pac/src/pmu/event_status.rs +++ b/jh7110-vf2-12a-pac/src/pmu/event_status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/hard_event_turn_on_mask.rs b/jh7110-vf2-12a-pac/src/pmu/hard_event_turn_on_mask.rs index 1ddfc49..21850d6 100644 --- a/jh7110-vf2-12a-pac/src/pmu/hard_event_turn_on_mask.rs +++ b/jh7110-vf2-12a-pac/src/pmu/hard_event_turn_on_mask.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `hard_event_0_on_mask` reader - RTC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] pub type HARD_EVENT_0_ON_MASK_R = crate::BitReader; #[doc = "Field `hard_event_0_on_mask` writer - RTC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] -pub type HARD_EVENT_0_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HARD_EVENT_0_ON_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `hard_event_1_on_mask` reader - GMAC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] pub type HARD_EVENT_1_ON_MASK_R = crate::BitReader; #[doc = "Field `hard_event_1_on_mask` writer - GMAC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] -pub type HARD_EVENT_1_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HARD_EVENT_1_ON_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `hard_event_2_on_mask` reader - RFU, 1: mask hardware event, 0: enable hardware event"] pub type HARD_EVENT_2_ON_MASK_R = crate::BitReader; #[doc = "Field `hard_event_2_on_mask` writer - RFU, 1: mask hardware event, 0: enable hardware event"] -pub type HARD_EVENT_2_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HARD_EVENT_2_ON_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `hard_event_3_on_mask` reader - RGPIO0 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] pub type HARD_EVENT_3_ON_MASK_R = crate::BitReader; #[doc = "Field `hard_event_3_on_mask` writer - RGPIO0 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] -pub type HARD_EVENT_3_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HARD_EVENT_3_ON_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `hard_event_4_on_mask` reader - RGPIO1 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] pub type HARD_EVENT_4_ON_MASK_R = crate::BitReader; #[doc = "Field `hard_event_4_on_mask` writer - RGPIO1 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] -pub type HARD_EVENT_4_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HARD_EVENT_4_ON_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `hard_event_5_on_mask` reader - RGPIO2 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] pub type HARD_EVENT_5_ON_MASK_R = crate::BitReader; #[doc = "Field `hard_event_5_on_mask` writer - RGPIO2 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] -pub type HARD_EVENT_5_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HARD_EVENT_5_ON_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `hard_event_6_on_mask` reader - RGPIO3 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] pub type HARD_EVENT_6_ON_MASK_R = crate::BitReader; #[doc = "Field `hard_event_6_on_mask` writer - RGPIO3 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] -pub type HARD_EVENT_6_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HARD_EVENT_6_ON_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `hard_event_7_on_mask` reader - GPU event, 1: mask hardware event, 0: enable hardware event"] pub type HARD_EVENT_7_ON_MASK_R = crate::BitReader; #[doc = "Field `hard_event_7_on_mask` writer - GPU event, 1: mask hardware event, 0: enable hardware event"] -pub type HARD_EVENT_7_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HARD_EVENT_7_ON_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RTC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] @@ -80,68 +80,56 @@ impl W { #[doc = "Bit 0 - RTC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] #[must_use] - pub fn hard_event_0_on_mask( - &mut self, - ) -> HARD_EVENT_0_ON_MASK_W { - HARD_EVENT_0_ON_MASK_W::new(self) + pub fn hard_event_0_on_mask(&mut self) -> HARD_EVENT_0_ON_MASK_W { + HARD_EVENT_0_ON_MASK_W::new(self, 0) } #[doc = "Bit 1 - GMAC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] #[must_use] - pub fn hard_event_1_on_mask( - &mut self, - ) -> HARD_EVENT_1_ON_MASK_W { - HARD_EVENT_1_ON_MASK_W::new(self) + pub fn hard_event_1_on_mask(&mut self) -> HARD_EVENT_1_ON_MASK_W { + HARD_EVENT_1_ON_MASK_W::new(self, 1) } #[doc = "Bit 2 - RFU, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] #[must_use] - pub fn hard_event_2_on_mask( - &mut self, - ) -> HARD_EVENT_2_ON_MASK_W { - HARD_EVENT_2_ON_MASK_W::new(self) + pub fn hard_event_2_on_mask(&mut self) -> HARD_EVENT_2_ON_MASK_W { + HARD_EVENT_2_ON_MASK_W::new(self, 2) } #[doc = "Bit 3 - RGPIO0 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] #[must_use] - pub fn hard_event_3_on_mask( - &mut self, - ) -> HARD_EVENT_3_ON_MASK_W { - HARD_EVENT_3_ON_MASK_W::new(self) + pub fn hard_event_3_on_mask(&mut self) -> HARD_EVENT_3_ON_MASK_W { + HARD_EVENT_3_ON_MASK_W::new(self, 3) } #[doc = "Bit 4 - RGPIO1 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] #[must_use] - pub fn hard_event_4_on_mask( - &mut self, - ) -> HARD_EVENT_4_ON_MASK_W { - HARD_EVENT_4_ON_MASK_W::new(self) + pub fn hard_event_4_on_mask(&mut self) -> HARD_EVENT_4_ON_MASK_W { + HARD_EVENT_4_ON_MASK_W::new(self, 4) } #[doc = "Bit 5 - RGPIO2 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] #[must_use] - pub fn hard_event_5_on_mask( - &mut self, - ) -> HARD_EVENT_5_ON_MASK_W { - HARD_EVENT_5_ON_MASK_W::new(self) + pub fn hard_event_5_on_mask(&mut self) -> HARD_EVENT_5_ON_MASK_W { + HARD_EVENT_5_ON_MASK_W::new(self, 5) } #[doc = "Bit 6 - RGPIO3 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] #[must_use] - pub fn hard_event_6_on_mask( - &mut self, - ) -> HARD_EVENT_6_ON_MASK_W { - HARD_EVENT_6_ON_MASK_W::new(self) + pub fn hard_event_6_on_mask(&mut self) -> HARD_EVENT_6_ON_MASK_W { + HARD_EVENT_6_ON_MASK_W::new(self, 6) } #[doc = "Bit 7 - GPU event, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] #[must_use] - pub fn hard_event_7_on_mask( - &mut self, - ) -> HARD_EVENT_7_ON_MASK_W { - HARD_EVENT_7_ON_MASK_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn hard_event_7_on_mask(&mut self) -> HARD_EVENT_7_ON_MASK_W { + HARD_EVENT_7_ON_MASK_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/hard_turn_on_power_mode.rs b/jh7110-vf2-12a-pac/src/pmu/hard_turn_on_power_mode.rs index e0b0efb..a13aa48 100644 --- a/jh7110-vf2-12a-pac/src/pmu/hard_turn_on_power_mode.rs +++ b/jh7110-vf2-12a-pac/src/pmu/hard_turn_on_power_mode.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `systop_power_mode` reader - SYSTOP turn-on power mode."] pub type SYSTOP_POWER_MODE_R = crate::BitReader; #[doc = "Field `systop_power_mode` writer - SYSTOP turn-on power mode."] -pub type SYSTOP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SYSTOP_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `cpu_power_mode` reader - CPU turn-on power mode."] pub type CPU_POWER_MODE_R = crate::BitReader; #[doc = "Field `cpu_power_mode` writer - CPU turn-on power mode."] -pub type CPU_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CPU_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gpua_power_mode` reader - GPUA turn-on power mode."] pub type GPUA_POWER_MODE_R = crate::BitReader; #[doc = "Field `gpua_power_mode` writer - GPUA turn-on power mode."] -pub type GPUA_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GPUA_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `vdec_power_mode` reader - VDEC turn-on power mode."] pub type VDEC_POWER_MODE_R = crate::BitReader; #[doc = "Field `vdec_power_mode` writer - VDEC turn-on power mode."] -pub type VDEC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VDEC_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `vout_power_mode` reader - VOUT turn-on power mode."] pub type VOUT_POWER_MODE_R = crate::BitReader; #[doc = "Field `vout_power_mode` writer - VOUT turn-on power mode."] -pub type VOUT_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VOUT_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `isp_power_mode` reader - ISP turn-on power mode."] pub type ISP_POWER_MODE_R = crate::BitReader; #[doc = "Field `isp_power_mode` writer - ISP turn-on power mode."] -pub type ISP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ISP_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `venc_power_mode` reader - VENC turn-on power mode."] pub type VENC_POWER_MODE_R = crate::BitReader; #[doc = "Field `venc_power_mode` writer - VENC turn-on power mode."] -pub type VENC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VENC_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - SYSTOP turn-on power mode."] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - SYSTOP turn-on power mode."] #[inline(always)] #[must_use] - pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { - SYSTOP_POWER_MODE_W::new(self) + pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { + SYSTOP_POWER_MODE_W::new(self, 0) } #[doc = "Bit 1 - CPU turn-on power mode."] #[inline(always)] #[must_use] - pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { - CPU_POWER_MODE_W::new(self) + pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { + CPU_POWER_MODE_W::new(self, 1) } #[doc = "Bit 2 - GPUA turn-on power mode."] #[inline(always)] #[must_use] - pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { - GPUA_POWER_MODE_W::new(self) + pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { + GPUA_POWER_MODE_W::new(self, 2) } #[doc = "Bit 3 - VDEC turn-on power mode."] #[inline(always)] #[must_use] - pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { - VDEC_POWER_MODE_W::new(self) + pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { + VDEC_POWER_MODE_W::new(self, 3) } #[doc = "Bit 4 - VOUT turn-on power mode."] #[inline(always)] #[must_use] - pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { - VOUT_POWER_MODE_W::new(self) + pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { + VOUT_POWER_MODE_W::new(self, 4) } #[doc = "Bit 5 - ISP turn-on power mode."] #[inline(always)] #[must_use] - pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { - ISP_POWER_MODE_W::new(self) + pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { + ISP_POWER_MODE_W::new(self, 5) } #[doc = "Bit 6 - VENC turn-on power mode."] #[inline(always)] #[must_use] - pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { - VENC_POWER_MODE_W::new(self) + pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { + VENC_POWER_MODE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/hw_event_crd.rs b/jh7110-vf2-12a-pac/src/pmu/hw_event_crd.rs index bdd1461..c2905d2 100644 --- a/jh7110-vf2-12a-pac/src/pmu/hw_event_crd.rs +++ b/jh7110-vf2-12a-pac/src/pmu/hw_event_crd.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/int_status.rs b/jh7110-vf2-12a-pac/src/pmu/int_status.rs index 841a9e8..4e918b9 100644 --- a/jh7110-vf2-12a-pac/src/pmu/int_status.rs +++ b/jh7110-vf2-12a-pac/src/pmu/int_status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/lp_timeout.rs b/jh7110-vf2-12a-pac/src/pmu/lp_timeout.rs index 8fdf4f0..57a8810 100644 --- a/jh7110-vf2-12a-pac/src/pmu/lp_timeout.rs +++ b/jh7110-vf2-12a-pac/src/pmu/lp_timeout.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lp_timeout` reader - LP Cell Control signal waiting carries acknowledge timeout."] pub type LP_TIMEOUT_R = crate::FieldReader; #[doc = "Field `lp_timeout` writer - LP Cell Control signal waiting carries acknowledge timeout."] -pub type LP_TIMEOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LP_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - LP Cell Control signal waiting carries acknowledge timeout."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - LP Cell Control signal waiting carries acknowledge timeout."] #[inline(always)] #[must_use] - pub fn lp_timeout(&mut self) -> LP_TIMEOUT_W { - LP_TIMEOUT_W::new(self) + pub fn lp_timeout(&mut self) -> LP_TIMEOUT_W { + LP_TIMEOUT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/pch_active.rs b/jh7110-vf2-12a-pac/src/pmu/pch_active.rs index c0d4dc2..1ca0ff9 100644 --- a/jh7110-vf2-12a-pac/src/pmu/pch_active.rs +++ b/jh7110-vf2-12a-pac/src/pmu/pch_active.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/pch_bypass.rs b/jh7110-vf2-12a-pac/src/pmu/pch_bypass.rs index e07a79f..7978dba 100644 --- a/jh7110-vf2-12a-pac/src/pmu/pch_bypass.rs +++ b/jh7110-vf2-12a-pac/src/pmu/pch_bypass.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `pch_bypass` reader - Bypass P-channel. 0: enable p-channel, 1: bypass p-channel"] pub type PCH_BYPASS_R = crate::BitReader; #[doc = "Field `pch_bypass` writer - Bypass P-channel. 0: enable p-channel, 1: bypass p-channel"] -pub type PCH_BYPASS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PCH_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Bypass P-channel. 0: enable p-channel, 1: bypass p-channel"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Bypass P-channel. 0: enable p-channel, 1: bypass p-channel"] #[inline(always)] #[must_use] - pub fn pch_bypass(&mut self) -> PCH_BYPASS_W { - PCH_BYPASS_W::new(self) + pub fn pch_bypass(&mut self) -> PCH_BYPASS_W { + PCH_BYPASS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/pch_pstate.rs b/jh7110-vf2-12a-pac/src/pmu/pch_pstate.rs index 2b2f0a9..e311176 100644 --- a/jh7110-vf2-12a-pac/src/pmu/pch_pstate.rs +++ b/jh7110-vf2-12a-pac/src/pmu/pch_pstate.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `pch_pstate` reader - P-channel state set"] pub type PCH_PSTATE_R = crate::FieldReader; #[doc = "Field `pch_pstate` writer - P-channel state set"] -pub type PCH_PSTATE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PCH_PSTATE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; impl R { #[doc = "Bits 0:4 - P-channel state set"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:4 - P-channel state set"] #[inline(always)] #[must_use] - pub fn pch_pstate(&mut self) -> PCH_PSTATE_W { - PCH_PSTATE_W::new(self) + pub fn pch_pstate(&mut self) -> PCH_PSTATE_W { + PCH_PSTATE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/pch_timeout.rs b/jh7110-vf2-12a-pac/src/pmu/pch_timeout.rs index 4ae8e16..54098c5 100644 --- a/jh7110-vf2-12a-pac/src/pmu/pch_timeout.rs +++ b/jh7110-vf2-12a-pac/src/pmu/pch_timeout.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `pch_timeout` reader - P-channel waiting device acknowledge timeout."] pub type PCH_TIMEOUT_R = crate::FieldReader; #[doc = "Field `pch_timeout` writer - P-channel waiting device acknowledge timeout."] -pub type PCH_TIMEOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type PCH_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - P-channel waiting device acknowledge timeout."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - P-channel waiting device acknowledge timeout."] #[inline(always)] #[must_use] - pub fn pch_timeout(&mut self) -> PCH_TIMEOUT_W { - PCH_TIMEOUT_W::new(self) + pub fn pch_timeout(&mut self) -> PCH_TIMEOUT_W { + PCH_TIMEOUT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/pdc0.rs b/jh7110-vf2-12a-pac/src/pmu/pdc0.rs index 49fa8c4..dfdf300 100644 --- a/jh7110-vf2-12a-pac/src/pmu/pdc0.rs +++ b/jh7110-vf2-12a-pac/src/pmu/pdc0.rs @@ -5,27 +5,27 @@ pub type W = crate::W; #[doc = "Field `pd0_off_cas` reader - Power domain 0 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD0_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd0_off_cas` writer - Power domain 0 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD0_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD0_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd0_on_cas` reader - Power domain 0 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD0_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd0_on_cas` writer - Power domain 0 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD0_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD0_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd1_off_cas` reader - Power domain 1 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD1_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd1_off_cas` writer - Power domain 1 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD1_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD1_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd1_on_cas` reader - Power domain 1 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD1_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd1_on_cas` writer - Power domain 1 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD1_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD1_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd2_off_cas` reader - Power domain 2 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD2_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd2_off_cas` writer - Power domain 2 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD2_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD2_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd2_on_cas` reader - Power domain 2 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD2_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd2_on_cas` writer - Power domain 2 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD2_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD2_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; impl R { #[doc = "Bits 0:4 - Power domain 0 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] @@ -62,40 +62,44 @@ impl W { #[doc = "Bits 0:4 - Power domain 0 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd0_off_cas(&mut self) -> PD0_OFF_CAS_W { - PD0_OFF_CAS_W::new(self) + pub fn pd0_off_cas(&mut self) -> PD0_OFF_CAS_W { + PD0_OFF_CAS_W::new(self, 0) } #[doc = "Bits 5:9 - Power domain 0 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd0_on_cas(&mut self) -> PD0_ON_CAS_W { - PD0_ON_CAS_W::new(self) + pub fn pd0_on_cas(&mut self) -> PD0_ON_CAS_W { + PD0_ON_CAS_W::new(self, 5) } #[doc = "Bits 10:14 - Power domain 1 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd1_off_cas(&mut self) -> PD1_OFF_CAS_W { - PD1_OFF_CAS_W::new(self) + pub fn pd1_off_cas(&mut self) -> PD1_OFF_CAS_W { + PD1_OFF_CAS_W::new(self, 10) } #[doc = "Bits 15:19 - Power domain 1 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd1_on_cas(&mut self) -> PD1_ON_CAS_W { - PD1_ON_CAS_W::new(self) + pub fn pd1_on_cas(&mut self) -> PD1_ON_CAS_W { + PD1_ON_CAS_W::new(self, 15) } #[doc = "Bits 20:24 - Power domain 2 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd2_off_cas(&mut self) -> PD2_OFF_CAS_W { - PD2_OFF_CAS_W::new(self) + pub fn pd2_off_cas(&mut self) -> PD2_OFF_CAS_W { + PD2_OFF_CAS_W::new(self, 20) } #[doc = "Bits 25:29 - Power domain 2 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd2_on_cas(&mut self) -> PD2_ON_CAS_W { - PD2_ON_CAS_W::new(self) + pub fn pd2_on_cas(&mut self) -> PD2_ON_CAS_W { + PD2_ON_CAS_W::new(self, 25) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/pdc1.rs b/jh7110-vf2-12a-pac/src/pmu/pdc1.rs index 5d0521e..ed69421 100644 --- a/jh7110-vf2-12a-pac/src/pmu/pdc1.rs +++ b/jh7110-vf2-12a-pac/src/pmu/pdc1.rs @@ -5,27 +5,27 @@ pub type W = crate::W; #[doc = "Field `pd3_off_cas` reader - Power domain 3 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD3_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd3_off_cas` writer - Power domain 3 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD3_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD3_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd3_on_cas` reader - Power domain 3 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD3_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd3_on_cas` writer - Power domain 3 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD3_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD3_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd4_off_cas` reader - Power domain 4 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD4_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd4_off_cas` writer - Power domain 4 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD4_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD4_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd4_on_cas` reader - Power domain 4 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD4_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd4_on_cas` writer - Power domain 4 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD4_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD4_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd5_off_cas` reader - Power domain 5 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD5_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd5_off_cas` writer - Power domain 5 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD5_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD5_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd5_on_cas` reader - Power domain 5 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD5_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd5_on_cas` writer - Power domain 5 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD5_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD5_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; impl R { #[doc = "Bits 0:4 - Power domain 3 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] @@ -62,40 +62,44 @@ impl W { #[doc = "Bits 0:4 - Power domain 3 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd3_off_cas(&mut self) -> PD3_OFF_CAS_W { - PD3_OFF_CAS_W::new(self) + pub fn pd3_off_cas(&mut self) -> PD3_OFF_CAS_W { + PD3_OFF_CAS_W::new(self, 0) } #[doc = "Bits 5:9 - Power domain 3 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd3_on_cas(&mut self) -> PD3_ON_CAS_W { - PD3_ON_CAS_W::new(self) + pub fn pd3_on_cas(&mut self) -> PD3_ON_CAS_W { + PD3_ON_CAS_W::new(self, 5) } #[doc = "Bits 10:14 - Power domain 4 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd4_off_cas(&mut self) -> PD4_OFF_CAS_W { - PD4_OFF_CAS_W::new(self) + pub fn pd4_off_cas(&mut self) -> PD4_OFF_CAS_W { + PD4_OFF_CAS_W::new(self, 10) } #[doc = "Bits 15:19 - Power domain 4 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd4_on_cas(&mut self) -> PD4_ON_CAS_W { - PD4_ON_CAS_W::new(self) + pub fn pd4_on_cas(&mut self) -> PD4_ON_CAS_W { + PD4_ON_CAS_W::new(self, 15) } #[doc = "Bits 20:24 - Power domain 5 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd5_off_cas(&mut self) -> PD5_OFF_CAS_W { - PD5_OFF_CAS_W::new(self) + pub fn pd5_off_cas(&mut self) -> PD5_OFF_CAS_W { + PD5_OFF_CAS_W::new(self, 20) } #[doc = "Bits 25:29 - Power domain 5 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd5_on_cas(&mut self) -> PD5_ON_CAS_W { - PD5_ON_CAS_W::new(self) + pub fn pd5_on_cas(&mut self) -> PD5_ON_CAS_W { + PD5_ON_CAS_W::new(self, 25) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/pdc2.rs b/jh7110-vf2-12a-pac/src/pmu/pdc2.rs index 7624c7d..956c250 100644 --- a/jh7110-vf2-12a-pac/src/pmu/pdc2.rs +++ b/jh7110-vf2-12a-pac/src/pmu/pdc2.rs @@ -5,27 +5,27 @@ pub type W = crate::W; #[doc = "Field `pd6_off_cas` reader - Power domain 6 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD6_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd6_off_cas` writer - Power domain 6 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD6_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD6_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd6_on_cas` reader - Power domain 6 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD6_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd6_on_cas` writer - Power domain 6 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD6_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD6_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd7_off_cas` reader - Power domain 7 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD7_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd7_off_cas` writer - Power domain 7 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD7_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD7_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd7_on_cas` reader - Power domain 7 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD7_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd7_on_cas` writer - Power domain 7 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD7_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD7_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd8_off_cas` reader - Power domain 8 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD8_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd8_off_cas` writer - Power domain 8 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD8_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD8_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd8_on_cas` reader - Power domain 8 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD8_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd8_on_cas` writer - Power domain 8 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD8_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD8_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; impl R { #[doc = "Bits 0:4 - Power domain 6 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] @@ -62,40 +62,44 @@ impl W { #[doc = "Bits 0:4 - Power domain 6 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd6_off_cas(&mut self) -> PD6_OFF_CAS_W { - PD6_OFF_CAS_W::new(self) + pub fn pd6_off_cas(&mut self) -> PD6_OFF_CAS_W { + PD6_OFF_CAS_W::new(self, 0) } #[doc = "Bits 5:9 - Power domain 6 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd6_on_cas(&mut self) -> PD6_ON_CAS_W { - PD6_ON_CAS_W::new(self) + pub fn pd6_on_cas(&mut self) -> PD6_ON_CAS_W { + PD6_ON_CAS_W::new(self, 5) } #[doc = "Bits 10:14 - Power domain 7 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd7_off_cas(&mut self) -> PD7_OFF_CAS_W { - PD7_OFF_CAS_W::new(self) + pub fn pd7_off_cas(&mut self) -> PD7_OFF_CAS_W { + PD7_OFF_CAS_W::new(self, 10) } #[doc = "Bits 15:19 - Power domain 7 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd7_on_cas(&mut self) -> PD7_ON_CAS_W { - PD7_ON_CAS_W::new(self) + pub fn pd7_on_cas(&mut self) -> PD7_ON_CAS_W { + PD7_ON_CAS_W::new(self, 15) } #[doc = "Bits 20:24 - Power domain 8 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd8_off_cas(&mut self) -> PD8_OFF_CAS_W { - PD8_OFF_CAS_W::new(self) + pub fn pd8_off_cas(&mut self) -> PD8_OFF_CAS_W { + PD8_OFF_CAS_W::new(self, 20) } #[doc = "Bits 25:29 - Power domain 8 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd8_on_cas(&mut self) -> PD8_ON_CAS_W { - PD8_ON_CAS_W::new(self) + pub fn pd8_on_cas(&mut self) -> PD8_ON_CAS_W { + PD8_ON_CAS_W::new(self, 25) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/soft_turn_off_power_mode.rs b/jh7110-vf2-12a-pac/src/pmu/soft_turn_off_power_mode.rs index 6c09db0..4954cfe 100644 --- a/jh7110-vf2-12a-pac/src/pmu/soft_turn_off_power_mode.rs +++ b/jh7110-vf2-12a-pac/src/pmu/soft_turn_off_power_mode.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `systop_power_mode` reader - SYSTOP turn-off power mode."] pub type SYSTOP_POWER_MODE_R = crate::BitReader; #[doc = "Field `systop_power_mode` writer - SYSTOP turn-off power mode."] -pub type SYSTOP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SYSTOP_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `cpu_power_mode` reader - CPU turn-off power mode."] pub type CPU_POWER_MODE_R = crate::BitReader; #[doc = "Field `cpu_power_mode` writer - CPU turn-off power mode."] -pub type CPU_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CPU_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gpua_power_mode` reader - GPUA turn-off power mode."] pub type GPUA_POWER_MODE_R = crate::BitReader; #[doc = "Field `gpua_power_mode` writer - GPUA turn-off power mode."] -pub type GPUA_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GPUA_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `vdec_power_mode` reader - VDEC turn-off power mode."] pub type VDEC_POWER_MODE_R = crate::BitReader; #[doc = "Field `vdec_power_mode` writer - VDEC turn-off power mode."] -pub type VDEC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VDEC_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `vout_power_mode` reader - VOUT turn-off power mode."] pub type VOUT_POWER_MODE_R = crate::BitReader; #[doc = "Field `vout_power_mode` writer - VOUT turn-off power mode."] -pub type VOUT_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VOUT_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `isp_power_mode` reader - ISP turn-off power mode."] pub type ISP_POWER_MODE_R = crate::BitReader; #[doc = "Field `isp_power_mode` writer - ISP turn-off power mode."] -pub type ISP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ISP_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `venc_power_mode` reader - VENC turn-off power mode."] pub type VENC_POWER_MODE_R = crate::BitReader; #[doc = "Field `venc_power_mode` writer - VENC turn-off power mode."] -pub type VENC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VENC_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - SYSTOP turn-off power mode."] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - SYSTOP turn-off power mode."] #[inline(always)] #[must_use] - pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { - SYSTOP_POWER_MODE_W::new(self) + pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { + SYSTOP_POWER_MODE_W::new(self, 0) } #[doc = "Bit 1 - CPU turn-off power mode."] #[inline(always)] #[must_use] - pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { - CPU_POWER_MODE_W::new(self) + pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { + CPU_POWER_MODE_W::new(self, 1) } #[doc = "Bit 2 - GPUA turn-off power mode."] #[inline(always)] #[must_use] - pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { - GPUA_POWER_MODE_W::new(self) + pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { + GPUA_POWER_MODE_W::new(self, 2) } #[doc = "Bit 3 - VDEC turn-off power mode."] #[inline(always)] #[must_use] - pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { - VDEC_POWER_MODE_W::new(self) + pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { + VDEC_POWER_MODE_W::new(self, 3) } #[doc = "Bit 4 - VOUT turn-off power mode."] #[inline(always)] #[must_use] - pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { - VOUT_POWER_MODE_W::new(self) + pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { + VOUT_POWER_MODE_W::new(self, 4) } #[doc = "Bit 5 - ISP turn-off power mode."] #[inline(always)] #[must_use] - pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { - ISP_POWER_MODE_W::new(self) + pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { + ISP_POWER_MODE_W::new(self, 5) } #[doc = "Bit 6 - VENC turn-off power mode."] #[inline(always)] #[must_use] - pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { - VENC_POWER_MODE_W::new(self) + pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { + VENC_POWER_MODE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/soft_turn_on_power_mode.rs b/jh7110-vf2-12a-pac/src/pmu/soft_turn_on_power_mode.rs index d587985..1a9ffe2 100644 --- a/jh7110-vf2-12a-pac/src/pmu/soft_turn_on_power_mode.rs +++ b/jh7110-vf2-12a-pac/src/pmu/soft_turn_on_power_mode.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `systop_power_mode` reader - SYSTOP turn-on power mode."] pub type SYSTOP_POWER_MODE_R = crate::BitReader; #[doc = "Field `systop_power_mode` writer - SYSTOP turn-on power mode."] -pub type SYSTOP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SYSTOP_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `cpu_power_mode` reader - CPU turn-on power mode."] pub type CPU_POWER_MODE_R = crate::BitReader; #[doc = "Field `cpu_power_mode` writer - CPU turn-on power mode."] -pub type CPU_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CPU_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gpua_power_mode` reader - GPUA turn-on power mode."] pub type GPUA_POWER_MODE_R = crate::BitReader; #[doc = "Field `gpua_power_mode` writer - GPUA turn-on power mode."] -pub type GPUA_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GPUA_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `vdec_power_mode` reader - VDEC turn-on power mode."] pub type VDEC_POWER_MODE_R = crate::BitReader; #[doc = "Field `vdec_power_mode` writer - VDEC turn-on power mode."] -pub type VDEC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VDEC_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `vout_power_mode` reader - VOUT turn-on power mode."] pub type VOUT_POWER_MODE_R = crate::BitReader; #[doc = "Field `vout_power_mode` writer - VOUT turn-on power mode."] -pub type VOUT_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VOUT_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `isp_power_mode` reader - ISP turn-on power mode."] pub type ISP_POWER_MODE_R = crate::BitReader; #[doc = "Field `isp_power_mode` writer - ISP turn-on power mode."] -pub type ISP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ISP_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `venc_power_mode` reader - VENC turn-on power mode."] pub type VENC_POWER_MODE_R = crate::BitReader; #[doc = "Field `venc_power_mode` writer - VENC turn-on power mode."] -pub type VENC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VENC_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - SYSTOP turn-on power mode."] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - SYSTOP turn-on power mode."] #[inline(always)] #[must_use] - pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { - SYSTOP_POWER_MODE_W::new(self) + pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { + SYSTOP_POWER_MODE_W::new(self, 0) } #[doc = "Bit 1 - CPU turn-on power mode."] #[inline(always)] #[must_use] - pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { - CPU_POWER_MODE_W::new(self) + pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { + CPU_POWER_MODE_W::new(self, 1) } #[doc = "Bit 2 - GPUA turn-on power mode."] #[inline(always)] #[must_use] - pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { - GPUA_POWER_MODE_W::new(self) + pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { + GPUA_POWER_MODE_W::new(self, 2) } #[doc = "Bit 3 - VDEC turn-on power mode."] #[inline(always)] #[must_use] - pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { - VDEC_POWER_MODE_W::new(self) + pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { + VDEC_POWER_MODE_W::new(self, 3) } #[doc = "Bit 4 - VOUT turn-on power mode."] #[inline(always)] #[must_use] - pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { - VOUT_POWER_MODE_W::new(self) + pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { + VOUT_POWER_MODE_W::new(self, 4) } #[doc = "Bit 5 - ISP turn-on power mode."] #[inline(always)] #[must_use] - pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { - ISP_POWER_MODE_W::new(self) + pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { + ISP_POWER_MODE_W::new(self, 5) } #[doc = "Bit 6 - VENC turn-on power mode."] #[inline(always)] #[must_use] - pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { - VENC_POWER_MODE_W::new(self) + pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { + VENC_POWER_MODE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/sw_encourage.rs b/jh7110-vf2-12a-pac/src/pmu/sw_encourage.rs index d8b550e..3fceb35 100644 --- a/jh7110-vf2-12a-pac/src/pmu/sw_encourage.rs +++ b/jh7110-vf2-12a-pac/src/pmu/sw_encourage.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sw_encourage` reader - Software Encouragement"] pub type SW_ENCOURAGE_R = crate::FieldReader; #[doc = "Field `sw_encourage` writer - Software Encouragement"] -pub type SW_ENCOURAGE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SW_ENCOURAGE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Software Encouragement"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - Software Encouragement"] #[inline(always)] #[must_use] - pub fn sw_encourage(&mut self) -> SW_ENCOURAGE_W { - SW_ENCOURAGE_W::new(self) + pub fn sw_encourage(&mut self) -> SW_ENCOURAGE_W { + SW_ENCOURAGE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/tim.rs b/jh7110-vf2-12a-pac/src/pmu/tim.rs index 521a85c..d7760a3 100644 --- a/jh7110-vf2-12a-pac/src/pmu/tim.rs +++ b/jh7110-vf2-12a-pac/src/pmu/tim.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `seq_done_mask` reader - Mask the sequence complete event. 0: mask, 1: unmask"] pub type SEQ_DONE_MASK_R = crate::BitReader; #[doc = "Field `seq_done_mask` writer - Mask the sequence complete event. 0: mask, 1: unmask"] -pub type SEQ_DONE_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SEQ_DONE_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `hw_req_mask` reader - Mask the hardware encouragement request. 0: mask, 1: unmask"] pub type HW_REQ_MASK_R = crate::BitReader; #[doc = "Field `hw_req_mask` writer - Mask the hardware encouragement request. 0: mask, 1: unmask"] -pub type HW_REQ_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HW_REQ_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sw_fail_mask` reader - Mask the software encouragement failure event. 0: mask, 1: unmask"] pub type SW_FAIL_MASK_R = crate::FieldReader; #[doc = "Field `sw_fail_mask` writer - Mask the software encouragement failure event. 0: mask, 1: unmask"] -pub type SW_FAIL_MASK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SW_FAIL_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `hw_fail_mask` reader - Mask the hardware encouragement failure event. 0: mask, 1: unmask"] pub type HW_FAIL_MASK_R = crate::FieldReader; #[doc = "Field `hw_fail_mask` writer - Mask the hardware encouragement failure event. 0: mask, 1: unmask"] -pub type HW_FAIL_MASK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type HW_FAIL_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pch_fail_mask` reader - Mask the P-channel encouragement failure event. 0: mask, 1: unmask"] pub type PCH_FAIL_MASK_R = crate::FieldReader; #[doc = "Field `pch_fail_mask` writer - Mask the P-channel encouragement failure event. 0: mask, 1: unmask"] -pub type PCH_FAIL_MASK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PCH_FAIL_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bit 0 - Mask the sequence complete event. 0: mask, 1: unmask"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - Mask the sequence complete event. 0: mask, 1: unmask"] #[inline(always)] #[must_use] - pub fn seq_done_mask(&mut self) -> SEQ_DONE_MASK_W { - SEQ_DONE_MASK_W::new(self) + pub fn seq_done_mask(&mut self) -> SEQ_DONE_MASK_W { + SEQ_DONE_MASK_W::new(self, 0) } #[doc = "Bit 1 - Mask the hardware encouragement request. 0: mask, 1: unmask"] #[inline(always)] #[must_use] - pub fn hw_req_mask(&mut self) -> HW_REQ_MASK_W { - HW_REQ_MASK_W::new(self) + pub fn hw_req_mask(&mut self) -> HW_REQ_MASK_W { + HW_REQ_MASK_W::new(self, 1) } #[doc = "Bits 2:3 - Mask the software encouragement failure event. 0: mask, 1: unmask"] #[inline(always)] #[must_use] - pub fn sw_fail_mask(&mut self) -> SW_FAIL_MASK_W { - SW_FAIL_MASK_W::new(self) + pub fn sw_fail_mask(&mut self) -> SW_FAIL_MASK_W { + SW_FAIL_MASK_W::new(self, 2) } #[doc = "Bits 4:5 - Mask the hardware encouragement failure event. 0: mask, 1: unmask"] #[inline(always)] #[must_use] - pub fn hw_fail_mask(&mut self) -> HW_FAIL_MASK_W { - HW_FAIL_MASK_W::new(self) + pub fn hw_fail_mask(&mut self) -> HW_FAIL_MASK_W { + HW_FAIL_MASK_W::new(self, 4) } #[doc = "Bits 6:8 - Mask the P-channel encouragement failure event. 0: mask, 1: unmask"] #[inline(always)] #[must_use] - pub fn pch_fail_mask(&mut self) -> PCH_FAIL_MASK_W { - PCH_FAIL_MASK_W::new(self) + pub fn pch_fail_mask(&mut self) -> PCH_FAIL_MASK_W { + PCH_FAIL_MASK_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pmu/timeout_seq_thd.rs b/jh7110-vf2-12a-pac/src/pmu/timeout_seq_thd.rs index 09a763c..0ec9877 100644 --- a/jh7110-vf2-12a-pac/src/pmu/timeout_seq_thd.rs +++ b/jh7110-vf2-12a-pac/src/pmu/timeout_seq_thd.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `timeout_seq_thd` reader - Threshold Sequence Timeout"] pub type TIMEOUT_SEQ_THD_R = crate::FieldReader; #[doc = "Field `timeout_seq_thd` writer - Threshold Sequence Timeout"] -pub type TIMEOUT_SEQ_THD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type TIMEOUT_SEQ_THD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Threshold Sequence Timeout"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:15 - Threshold Sequence Timeout"] #[inline(always)] #[must_use] - pub fn timeout_seq_thd(&mut self) -> TIMEOUT_SEQ_THD_W { - TIMEOUT_SEQ_THD_W::new(self) + pub fn timeout_seq_thd(&mut self) -> TIMEOUT_SEQ_THD_W { + TIMEOUT_SEQ_THD_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pwm.rs b/jh7110-vf2-12a-pac/src/pwm.rs index 8f4ac84..4ef2f7e 100644 --- a/jh7110-vf2-12a-pac/src/pwm.rs +++ b/jh7110-vf2-12a-pac/src/pwm.rs @@ -1,31 +1,49 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + cntr: CNTR, + hrc: HRC, + lrc: LRC, + ctrl: CTRL, +} +impl RegisterBlock { #[doc = "0x00 - PTC counter register"] - pub cntr: CNTR, + #[inline(always)] + pub const fn cntr(&self) -> &CNTR { + &self.cntr + } #[doc = "0x04 - PTC duty-cycle register"] - pub hrc: HRC, + #[inline(always)] + pub const fn hrc(&self) -> &HRC { + &self.hrc + } #[doc = "0x08 - PTC period register"] - pub lrc: LRC, + #[inline(always)] + pub const fn lrc(&self) -> &LRC { + &self.lrc + } #[doc = "0x0c - PTC control register"] - pub ctrl: CTRL, + #[inline(always)] + pub const fn ctrl(&self) -> &CTRL { + &self.ctrl + } } -#[doc = "cntr (rw) register accessor: PTC counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cntr`] +#[doc = "cntr (rw) register accessor: PTC counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntr`] module"] pub type CNTR = crate::Reg; #[doc = "PTC counter register"] pub mod cntr; -#[doc = "hrc (rw) register accessor: PTC duty-cycle register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hrc`] +#[doc = "hrc (rw) register accessor: PTC duty-cycle register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hrc`] module"] pub type HRC = crate::Reg; #[doc = "PTC duty-cycle register"] pub mod hrc; -#[doc = "lrc (rw) register accessor: PTC period register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lrc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lrc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lrc`] +#[doc = "lrc (rw) register accessor: PTC period register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lrc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lrc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lrc`] module"] pub type LRC = crate::Reg; #[doc = "PTC period register"] pub mod lrc; -#[doc = "ctrl (rw) register accessor: PTC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctrl`] +#[doc = "ctrl (rw) register accessor: PTC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] pub type CTRL = crate::Reg; #[doc = "PTC control register"] diff --git a/jh7110-vf2-12a-pac/src/pwm/cntr.rs b/jh7110-vf2-12a-pac/src/pwm/cntr.rs index 5a4551c..3db645d 100644 --- a/jh7110-vf2-12a-pac/src/pwm/cntr.rs +++ b/jh7110-vf2-12a-pac/src/pwm/cntr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `cntr` reader - PWM PTC counter"] pub type CNTR_R = crate::FieldReader; #[doc = "Field `cntr` writer - PWM PTC counter"] -pub type CNTR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CNTR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - PWM PTC counter"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - PWM PTC counter"] #[inline(always)] #[must_use] - pub fn cntr(&mut self) -> CNTR_W { - CNTR_W::new(self) + pub fn cntr(&mut self) -> CNTR_W { + CNTR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pwm/ctrl.rs b/jh7110-vf2-12a-pac/src/pwm/ctrl.rs index 6d49410..d31b70b 100644 --- a/jh7110-vf2-12a-pac/src/pwm/ctrl.rs +++ b/jh7110-vf2-12a-pac/src/pwm/ctrl.rs @@ -5,39 +5,39 @@ pub type W = crate::W; #[doc = "Field `en` reader - PWM PTC enable"] pub type EN_R = crate::BitReader; #[doc = "Field `en` writer - PWM PTC enable"] -pub type EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `eclk` reader - PWM PTC enable clock"] pub type ECLK_R = crate::BitReader; #[doc = "Field `eclk` writer - PWM PTC enable clock"] -pub type ECLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ECLK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `nec` reader - PWM PTC nec"] pub type NEC_R = crate::BitReader; #[doc = "Field `nec` writer - PWM PTC nec"] -pub type NEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type NEC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `oe` reader - PWM PTC oe"] pub type OE_R = crate::BitReader; #[doc = "Field `oe` writer - PWM PTC oe"] -pub type OE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `single` reader - PWM PTC single"] pub type SINGLE_R = crate::BitReader; #[doc = "Field `single` writer - PWM PTC single"] -pub type SINGLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SINGLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `inte` reader - PWM PTC interrupt enable"] pub type INTE_R = crate::BitReader; #[doc = "Field `inte` writer - PWM PTC interrupt enable"] -pub type INTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type INTE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `int` reader - PWM PTC interrupt"] pub type INT_R = crate::BitReader; #[doc = "Field `int` writer - PWM PTC interrupt"] -pub type INT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type INT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `cntrrst` reader - PWM PTC counter reset"] pub type CNTRRST_R = crate::BitReader; #[doc = "Field `cntrrst` writer - PWM PTC counter reset"] -pub type CNTRRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CNTRRST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `capte` reader - PWM PTC capte"] pub type CAPTE_R = crate::BitReader; #[doc = "Field `capte` writer - PWM PTC capte"] -pub type CAPTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CAPTE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - PWM PTC enable"] #[inline(always)] @@ -89,58 +89,62 @@ impl W { #[doc = "Bit 0 - PWM PTC enable"] #[inline(always)] #[must_use] - pub fn en(&mut self) -> EN_W { - EN_W::new(self) + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) } #[doc = "Bit 1 - PWM PTC enable clock"] #[inline(always)] #[must_use] - pub fn eclk(&mut self) -> ECLK_W { - ECLK_W::new(self) + pub fn eclk(&mut self) -> ECLK_W { + ECLK_W::new(self, 1) } #[doc = "Bit 2 - PWM PTC nec"] #[inline(always)] #[must_use] - pub fn nec(&mut self) -> NEC_W { - NEC_W::new(self) + pub fn nec(&mut self) -> NEC_W { + NEC_W::new(self, 2) } #[doc = "Bit 3 - PWM PTC oe"] #[inline(always)] #[must_use] - pub fn oe(&mut self) -> OE_W { - OE_W::new(self) + pub fn oe(&mut self) -> OE_W { + OE_W::new(self, 3) } #[doc = "Bit 4 - PWM PTC single"] #[inline(always)] #[must_use] - pub fn single(&mut self) -> SINGLE_W { - SINGLE_W::new(self) + pub fn single(&mut self) -> SINGLE_W { + SINGLE_W::new(self, 4) } #[doc = "Bit 5 - PWM PTC interrupt enable"] #[inline(always)] #[must_use] - pub fn inte(&mut self) -> INTE_W { - INTE_W::new(self) + pub fn inte(&mut self) -> INTE_W { + INTE_W::new(self, 5) } #[doc = "Bit 6 - PWM PTC interrupt"] #[inline(always)] #[must_use] - pub fn int(&mut self) -> INT_W { - INT_W::new(self) + pub fn int(&mut self) -> INT_W { + INT_W::new(self, 6) } #[doc = "Bit 7 - PWM PTC counter reset"] #[inline(always)] #[must_use] - pub fn cntrrst(&mut self) -> CNTRRST_W { - CNTRRST_W::new(self) + pub fn cntrrst(&mut self) -> CNTRRST_W { + CNTRRST_W::new(self, 7) } #[doc = "Bit 8 - PWM PTC capte"] #[inline(always)] #[must_use] - pub fn capte(&mut self) -> CAPTE_W { - CAPTE_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn capte(&mut self) -> CAPTE_W { + CAPTE_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pwm/hrc.rs b/jh7110-vf2-12a-pac/src/pwm/hrc.rs index 5930506..f044a89 100644 --- a/jh7110-vf2-12a-pac/src/pwm/hrc.rs +++ b/jh7110-vf2-12a-pac/src/pwm/hrc.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hrc` reader - PWM PTC duty-cycle value"] pub type HRC_R = crate::FieldReader; #[doc = "Field `hrc` writer - PWM PTC duty-cycle value"] -pub type HRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HRC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - PWM PTC duty-cycle value"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - PWM PTC duty-cycle value"] #[inline(always)] #[must_use] - pub fn hrc(&mut self) -> HRC_W { - HRC_W::new(self) + pub fn hrc(&mut self) -> HRC_W { + HRC_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/pwm/lrc.rs b/jh7110-vf2-12a-pac/src/pwm/lrc.rs index 11328ad..31fedc3 100644 --- a/jh7110-vf2-12a-pac/src/pwm/lrc.rs +++ b/jh7110-vf2-12a-pac/src/pwm/lrc.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lrc` reader - PWM PTC period value"] pub type LRC_R = crate::FieldReader; #[doc = "Field `lrc` writer - PWM PTC period value"] -pub type LRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type LRC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - PWM PTC period value"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - PWM PTC period value"] #[inline(always)] #[must_use] - pub fn lrc(&mut self) -> LRC_W { - LRC_W::new(self) + pub fn lrc(&mut self) -> LRC_W { + LRC_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi.rs b/jh7110-vf2-12a-pac/src/qspi.rs index 1ff3ba9..b17e09f 100644 --- a/jh7110-vf2-12a-pac/src/qspi.rs +++ b/jh7110-vf2-12a-pac/src/qspi.rs @@ -1,226 +1,352 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + config: CONFIG, + rd_instr: RD_INSTR, + wr_instr: WR_INSTR, + delay: DELAY, + read_capture: READ_CAPTURE, + size: SIZE, + sram_partition: SRAM_PARTITION, + indirect_trigger: INDIRECT_TRIGGER, + dma: DMA, + remap: REMAP, + mode_bit: MODE_BIT, + sdram_level: SDRAM_LEVEL, + _reserved12: [u8; 0x08], + wr_completion_ctrl: WR_COMPLETION_CTRL, + _reserved13: [u8; 0x04], + irq_status: IRQ_STATUS, + irq_mask: IRQ_MASK, + _reserved15: [u8; 0x18], + indirect_rd: INDIRECT_RD, + indirect_rd_watermark: INDIRECT_RD_WATERMARK, + indirect_rd_start_addr: INDIRECT_RD_START_ADDR, + indirect_rd_bytes: INDIRECT_RD_BYTES, + indirect_wr: INDIRECT_WR, + indirect_wr_watermark: INDIRECT_WR_WATERMARK, + indirect_wr_start_addr: INDIRECT_WR_START_ADDR, + indirect_wr_bytes: INDIRECT_WR_BYTES, + _reserved23: [u8; 0x10], + cmd_ctrl: CMD_CTRL, + cmd_address: CMD_ADDRESS, + _reserved25: [u8; 0x08], + cmd_read_at_lower: CMD_READ_AT_LOWER, + cmd_read_at_upper: CMD_READ_AT_UPPER, + cmd_write_at_lower: CMD_WRITE_AT_LOWER, + cmd_write_at_upper: CMD_WRITE_AT_UPPER, + polling_status: POLLING_STATUS, + _reserved30: [u8; 0x2c], + ext_lower: EXT_LOWER, +} +impl RegisterBlock { #[doc = "0x00 - Cadence QSPI Configuration"] - pub config: CONFIG, + #[inline(always)] + pub const fn config(&self) -> &CONFIG { + &self.config + } #[doc = "0x04 - Cadence QSPI Read Instruction"] - pub rd_instr: RD_INSTR, + #[inline(always)] + pub const fn rd_instr(&self) -> &RD_INSTR { + &self.rd_instr + } #[doc = "0x08 - Cadence QSPI Write Instruction"] - pub wr_instr: WR_INSTR, + #[inline(always)] + pub const fn wr_instr(&self) -> &WR_INSTR { + &self.wr_instr + } #[doc = "0x0c - Cadence QSPI Delay"] - pub delay: DELAY, + #[inline(always)] + pub const fn delay(&self) -> &DELAY { + &self.delay + } #[doc = "0x10 - Cadence QSPI Read Capture"] - pub read_capture: READ_CAPTURE, + #[inline(always)] + pub const fn read_capture(&self) -> &READ_CAPTURE { + &self.read_capture + } #[doc = "0x14 - Cadence QSPI Size Configuration"] - pub size: SIZE, + #[inline(always)] + pub const fn size(&self) -> &SIZE { + &self.size + } #[doc = "0x18 - Cadence QSPI SRAM Partition Size"] - pub sram_partition: SRAM_PARTITION, + #[inline(always)] + pub const fn sram_partition(&self) -> &SRAM_PARTITION { + &self.sram_partition + } #[doc = "0x1c - Cadence QSPI Indirect Trigger Address"] - pub indirect_trigger: INDIRECT_TRIGGER, + #[inline(always)] + pub const fn indirect_trigger(&self) -> &INDIRECT_TRIGGER { + &self.indirect_trigger + } #[doc = "0x20 - Cadence QSPI Direct Memory Access"] - pub dma: DMA, + #[inline(always)] + pub const fn dma(&self) -> &DMA { + &self.dma + } #[doc = "0x24 - Cadence QSPI Remap Address"] - pub remap: REMAP, + #[inline(always)] + pub const fn remap(&self) -> &REMAP { + &self.remap + } #[doc = "0x28 - Cadence QSPI Mode Bit(s)"] - pub mode_bit: MODE_BIT, + #[inline(always)] + pub const fn mode_bit(&self) -> &MODE_BIT { + &self.mode_bit + } #[doc = "0x2c - Cadence QSPI SDRAM Level"] - pub sdram_level: SDRAM_LEVEL, - _reserved12: [u8; 0x08], + #[inline(always)] + pub const fn sdram_level(&self) -> &SDRAM_LEVEL { + &self.sdram_level + } #[doc = "0x38 - Cadence QSPI Write Completion Control"] - pub wr_completion_ctrl: WR_COMPLETION_CTRL, - _reserved13: [u8; 0x04], + #[inline(always)] + pub const fn wr_completion_ctrl(&self) -> &WR_COMPLETION_CTRL { + &self.wr_completion_ctrl + } #[doc = "0x40 - Cadence QSPI IRQ Status"] - pub irq_status: IRQ_STATUS, + #[inline(always)] + pub const fn irq_status(&self) -> &IRQ_STATUS { + &self.irq_status + } #[doc = "0x44 - Cadence QSPI IRQ Mask"] - pub irq_mask: IRQ_MASK, - _reserved15: [u8; 0x18], + #[inline(always)] + pub const fn irq_mask(&self) -> &IRQ_MASK { + &self.irq_mask + } #[doc = "0x60 - Cadence QSPI Indirect Read"] - pub indirect_rd: INDIRECT_RD, + #[inline(always)] + pub const fn indirect_rd(&self) -> &INDIRECT_RD { + &self.indirect_rd + } #[doc = "0x64 - Cadence QSPI Indirect Read Watermark"] - pub indirect_rd_watermark: INDIRECT_RD_WATERMARK, + #[inline(always)] + pub const fn indirect_rd_watermark(&self) -> &INDIRECT_RD_WATERMARK { + &self.indirect_rd_watermark + } #[doc = "0x68 - Cadence QSPI Indirect Read Start Address"] - pub indirect_rd_start_addr: INDIRECT_RD_START_ADDR, + #[inline(always)] + pub const fn indirect_rd_start_addr(&self) -> &INDIRECT_RD_START_ADDR { + &self.indirect_rd_start_addr + } #[doc = "0x6c - Cadence QSPI Indirect Read Bytes"] - pub indirect_rd_bytes: INDIRECT_RD_BYTES, + #[inline(always)] + pub const fn indirect_rd_bytes(&self) -> &INDIRECT_RD_BYTES { + &self.indirect_rd_bytes + } #[doc = "0x70 - Cadence QSPI Indirect Write"] - pub indirect_wr: INDIRECT_WR, + #[inline(always)] + pub const fn indirect_wr(&self) -> &INDIRECT_WR { + &self.indirect_wr + } #[doc = "0x74 - Cadence QSPI Indirect Write Watermark"] - pub indirect_wr_watermark: INDIRECT_WR_WATERMARK, + #[inline(always)] + pub const fn indirect_wr_watermark(&self) -> &INDIRECT_WR_WATERMARK { + &self.indirect_wr_watermark + } #[doc = "0x78 - Cadence QSPI Indirect Write Start Address"] - pub indirect_wr_start_addr: INDIRECT_WR_START_ADDR, + #[inline(always)] + pub const fn indirect_wr_start_addr(&self) -> &INDIRECT_WR_START_ADDR { + &self.indirect_wr_start_addr + } #[doc = "0x7c - Cadence QSPI Indirect Write Bytes"] - pub indirect_wr_bytes: INDIRECT_WR_BYTES, - _reserved23: [u8; 0x10], + #[inline(always)] + pub const fn indirect_wr_bytes(&self) -> &INDIRECT_WR_BYTES { + &self.indirect_wr_bytes + } #[doc = "0x90 - Cadence QSPI Command Control"] - pub cmd_ctrl: CMD_CTRL, + #[inline(always)] + pub const fn cmd_ctrl(&self) -> &CMD_CTRL { + &self.cmd_ctrl + } #[doc = "0x94 - Cadence QSPI Command Address"] - pub cmd_address: CMD_ADDRESS, - _reserved25: [u8; 0x08], + #[inline(always)] + pub const fn cmd_address(&self) -> &CMD_ADDRESS { + &self.cmd_address + } #[doc = "0xa0 - Cadence QSPI Command Read at Lower"] - pub cmd_read_at_lower: CMD_READ_AT_LOWER, + #[inline(always)] + pub const fn cmd_read_at_lower(&self) -> &CMD_READ_AT_LOWER { + &self.cmd_read_at_lower + } #[doc = "0xa4 - Cadence QSPI Command Read at Upper"] - pub cmd_read_at_upper: CMD_READ_AT_UPPER, + #[inline(always)] + pub const fn cmd_read_at_upper(&self) -> &CMD_READ_AT_UPPER { + &self.cmd_read_at_upper + } #[doc = "0xa8 - Cadence QSPI Command Write at Lower"] - pub cmd_write_at_lower: CMD_WRITE_AT_LOWER, + #[inline(always)] + pub const fn cmd_write_at_lower(&self) -> &CMD_WRITE_AT_LOWER { + &self.cmd_write_at_lower + } #[doc = "0xac - Cadence QSPI Command Write at Upper"] - pub cmd_write_at_upper: CMD_WRITE_AT_UPPER, + #[inline(always)] + pub const fn cmd_write_at_upper(&self) -> &CMD_WRITE_AT_UPPER { + &self.cmd_write_at_upper + } #[doc = "0xb0 - Cadence QSPI Polling Status"] - pub polling_status: POLLING_STATUS, - _reserved30: [u8; 0x2c], + #[inline(always)] + pub const fn polling_status(&self) -> &POLLING_STATUS { + &self.polling_status + } #[doc = "0xe0 - Cadence QSPI Extension Lower"] - pub ext_lower: EXT_LOWER, + #[inline(always)] + pub const fn ext_lower(&self) -> &EXT_LOWER { + &self.ext_lower + } } -#[doc = "config (rw) register accessor: Cadence QSPI Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`config`] +#[doc = "config (rw) register accessor: Cadence QSPI Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] pub type CONFIG = crate::Reg; #[doc = "Cadence QSPI Configuration"] pub mod config; -#[doc = "rd_instr (rw) register accessor: Cadence QSPI Read Instruction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_instr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rd_instr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rd_instr`] +#[doc = "rd_instr (rw) register accessor: Cadence QSPI Read Instruction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_instr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rd_instr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_instr`] module"] pub type RD_INSTR = crate::Reg; #[doc = "Cadence QSPI Read Instruction"] pub mod rd_instr; -#[doc = "wr_instr (rw) register accessor: Cadence QSPI Write Instruction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_instr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_instr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wr_instr`] +#[doc = "wr_instr (rw) register accessor: Cadence QSPI Write Instruction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_instr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_instr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wr_instr`] module"] pub type WR_INSTR = crate::Reg; #[doc = "Cadence QSPI Write Instruction"] pub mod wr_instr; -#[doc = "delay (rw) register accessor: Cadence QSPI Delay\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`delay::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`delay::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`delay`] +#[doc = "delay (rw) register accessor: Cadence QSPI Delay\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`delay::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`delay::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@delay`] module"] pub type DELAY = crate::Reg; #[doc = "Cadence QSPI Delay"] pub mod delay; -#[doc = "read_capture (rw) register accessor: Cadence QSPI Read Capture\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`read_capture::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`read_capture::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`read_capture`] +#[doc = "read_capture (rw) register accessor: Cadence QSPI Read Capture\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`read_capture::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`read_capture::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@read_capture`] module"] pub type READ_CAPTURE = crate::Reg; #[doc = "Cadence QSPI Read Capture"] pub mod read_capture; -#[doc = "size (rw) register accessor: Cadence QSPI Size Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`size`] +#[doc = "size (rw) register accessor: Cadence QSPI Size Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@size`] module"] pub type SIZE = crate::Reg; #[doc = "Cadence QSPI Size Configuration"] pub mod size; -#[doc = "sram_partition (rw) register accessor: Cadence QSPI SRAM Partition Size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sram_partition::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sram_partition::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sram_partition`] +#[doc = "sram_partition (rw) register accessor: Cadence QSPI SRAM Partition Size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sram_partition::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sram_partition::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_partition`] module"] pub type SRAM_PARTITION = crate::Reg; #[doc = "Cadence QSPI SRAM Partition Size"] pub mod sram_partition; -#[doc = "indirect_trigger (rw) register accessor: Cadence QSPI Indirect Trigger Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_trigger::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_trigger::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_trigger`] +#[doc = "indirect_trigger (rw) register accessor: Cadence QSPI Indirect Trigger Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_trigger::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_trigger::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_trigger`] module"] pub type INDIRECT_TRIGGER = crate::Reg; #[doc = "Cadence QSPI Indirect Trigger Address"] pub mod indirect_trigger; -#[doc = "dma (rw) register accessor: Cadence QSPI Direct Memory Access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dma`] +#[doc = "dma (rw) register accessor: Cadence QSPI Direct Memory Access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma`] module"] pub type DMA = crate::Reg; #[doc = "Cadence QSPI Direct Memory Access"] pub mod dma; -#[doc = "remap (rw) register accessor: Cadence QSPI Remap Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`remap::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`remap::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`remap`] +#[doc = "remap (rw) register accessor: Cadence QSPI Remap Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`remap::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`remap::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@remap`] module"] pub type REMAP = crate::Reg; #[doc = "Cadence QSPI Remap Address"] pub mod remap; -#[doc = "mode_bit (rw) register accessor: Cadence QSPI Mode Bit(s)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode_bit::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode_bit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mode_bit`] +#[doc = "mode_bit (rw) register accessor: Cadence QSPI Mode Bit(s)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode_bit::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode_bit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode_bit`] module"] pub type MODE_BIT = crate::Reg; #[doc = "Cadence QSPI Mode Bit(s)"] pub mod mode_bit; -#[doc = "sdram_level (rw) register accessor: Cadence QSPI SDRAM Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdram_level::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdram_level::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sdram_level`] +#[doc = "sdram_level (rw) register accessor: Cadence QSPI SDRAM Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdram_level::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdram_level::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdram_level`] module"] pub type SDRAM_LEVEL = crate::Reg; #[doc = "Cadence QSPI SDRAM Level"] pub mod sdram_level; -#[doc = "wr_completion_ctrl (rw) register accessor: Cadence QSPI Write Completion Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_completion_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_completion_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wr_completion_ctrl`] +#[doc = "wr_completion_ctrl (rw) register accessor: Cadence QSPI Write Completion Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_completion_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_completion_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wr_completion_ctrl`] module"] pub type WR_COMPLETION_CTRL = crate::Reg; #[doc = "Cadence QSPI Write Completion Control"] pub mod wr_completion_ctrl; -#[doc = "irq_status (rw) register accessor: Cadence QSPI IRQ Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`irq_status`] +#[doc = "irq_status (rw) register accessor: Cadence QSPI IRQ Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_status`] module"] pub type IRQ_STATUS = crate::Reg; #[doc = "Cadence QSPI IRQ Status"] pub mod irq_status; -#[doc = "irq_mask (rw) register accessor: Cadence QSPI IRQ Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`irq_mask`] +#[doc = "irq_mask (rw) register accessor: Cadence QSPI IRQ Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_mask`] module"] pub type IRQ_MASK = crate::Reg; #[doc = "Cadence QSPI IRQ Mask"] pub mod irq_mask; -#[doc = "indirect_rd (rw) register accessor: Cadence QSPI Indirect Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_rd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_rd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_rd`] +#[doc = "indirect_rd (rw) register accessor: Cadence QSPI Indirect Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_rd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_rd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_rd`] module"] pub type INDIRECT_RD = crate::Reg; #[doc = "Cadence QSPI Indirect Read"] pub mod indirect_rd; -#[doc = "indirect_rd_watermark (rw) register accessor: Cadence QSPI Indirect Read Watermark\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_rd_watermark::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_rd_watermark::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_rd_watermark`] +#[doc = "indirect_rd_watermark (rw) register accessor: Cadence QSPI Indirect Read Watermark\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_rd_watermark::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_rd_watermark::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_rd_watermark`] module"] pub type INDIRECT_RD_WATERMARK = crate::Reg; #[doc = "Cadence QSPI Indirect Read Watermark"] pub mod indirect_rd_watermark; -#[doc = "indirect_rd_start_addr (rw) register accessor: Cadence QSPI Indirect Read Start Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_rd_start_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_rd_start_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_rd_start_addr`] +#[doc = "indirect_rd_start_addr (rw) register accessor: Cadence QSPI Indirect Read Start Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_rd_start_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_rd_start_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_rd_start_addr`] module"] pub type INDIRECT_RD_START_ADDR = crate::Reg; #[doc = "Cadence QSPI Indirect Read Start Address"] pub mod indirect_rd_start_addr; -#[doc = "indirect_rd_bytes (rw) register accessor: Cadence QSPI Indirect Read Bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_rd_bytes::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_rd_bytes::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_rd_bytes`] +#[doc = "indirect_rd_bytes (rw) register accessor: Cadence QSPI Indirect Read Bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_rd_bytes::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_rd_bytes::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_rd_bytes`] module"] pub type INDIRECT_RD_BYTES = crate::Reg; #[doc = "Cadence QSPI Indirect Read Bytes"] pub mod indirect_rd_bytes; -#[doc = "indirect_wr (rw) register accessor: Cadence QSPI Indirect Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_wr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_wr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_wr`] +#[doc = "indirect_wr (rw) register accessor: Cadence QSPI Indirect Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_wr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_wr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_wr`] module"] pub type INDIRECT_WR = crate::Reg; #[doc = "Cadence QSPI Indirect Write"] pub mod indirect_wr; -#[doc = "indirect_wr_watermark (rw) register accessor: Cadence QSPI Indirect Write Watermark\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_wr_watermark::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_wr_watermark::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_wr_watermark`] +#[doc = "indirect_wr_watermark (rw) register accessor: Cadence QSPI Indirect Write Watermark\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_wr_watermark::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_wr_watermark::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_wr_watermark`] module"] pub type INDIRECT_WR_WATERMARK = crate::Reg; #[doc = "Cadence QSPI Indirect Write Watermark"] pub mod indirect_wr_watermark; -#[doc = "indirect_wr_start_addr (rw) register accessor: Cadence QSPI Indirect Write Start Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_wr_start_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_wr_start_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_wr_start_addr`] +#[doc = "indirect_wr_start_addr (rw) register accessor: Cadence QSPI Indirect Write Start Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_wr_start_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_wr_start_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_wr_start_addr`] module"] pub type INDIRECT_WR_START_ADDR = crate::Reg; #[doc = "Cadence QSPI Indirect Write Start Address"] pub mod indirect_wr_start_addr; -#[doc = "indirect_wr_bytes (rw) register accessor: Cadence QSPI Indirect Write Bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_wr_bytes::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_wr_bytes::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_wr_bytes`] +#[doc = "indirect_wr_bytes (rw) register accessor: Cadence QSPI Indirect Write Bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_wr_bytes::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_wr_bytes::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_wr_bytes`] module"] pub type INDIRECT_WR_BYTES = crate::Reg; #[doc = "Cadence QSPI Indirect Write Bytes"] pub mod indirect_wr_bytes; -#[doc = "cmd_ctrl (rw) register accessor: Cadence QSPI Command Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmd_ctrl`] +#[doc = "cmd_ctrl (rw) register accessor: Cadence QSPI Command Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_ctrl`] module"] pub type CMD_CTRL = crate::Reg; #[doc = "Cadence QSPI Command Control"] pub mod cmd_ctrl; -#[doc = "cmd_address (rw) register accessor: Cadence QSPI Command Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_address::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmd_address`] +#[doc = "cmd_address (rw) register accessor: Cadence QSPI Command Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_address::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_address`] module"] pub type CMD_ADDRESS = crate::Reg; #[doc = "Cadence QSPI Command Address"] pub mod cmd_address; -#[doc = "cmd_read_at_lower (rw) register accessor: Cadence QSPI Command Read at Lower\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_read_at_lower::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_read_at_lower::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmd_read_at_lower`] +#[doc = "cmd_read_at_lower (rw) register accessor: Cadence QSPI Command Read at Lower\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_read_at_lower::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_read_at_lower::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_read_at_lower`] module"] pub type CMD_READ_AT_LOWER = crate::Reg; #[doc = "Cadence QSPI Command Read at Lower"] pub mod cmd_read_at_lower; -#[doc = "cmd_read_at_upper (rw) register accessor: Cadence QSPI Command Read at Upper\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_read_at_upper::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_read_at_upper::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmd_read_at_upper`] +#[doc = "cmd_read_at_upper (rw) register accessor: Cadence QSPI Command Read at Upper\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_read_at_upper::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_read_at_upper::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_read_at_upper`] module"] pub type CMD_READ_AT_UPPER = crate::Reg; #[doc = "Cadence QSPI Command Read at Upper"] pub mod cmd_read_at_upper; -#[doc = "cmd_write_at_lower (rw) register accessor: Cadence QSPI Command Write at Lower\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_write_at_lower::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_write_at_lower::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmd_write_at_lower`] +#[doc = "cmd_write_at_lower (rw) register accessor: Cadence QSPI Command Write at Lower\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_write_at_lower::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_write_at_lower::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_write_at_lower`] module"] pub type CMD_WRITE_AT_LOWER = crate::Reg; #[doc = "Cadence QSPI Command Write at Lower"] pub mod cmd_write_at_lower; -#[doc = "cmd_write_at_upper (rw) register accessor: Cadence QSPI Command Write at Upper\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_write_at_upper::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_write_at_upper::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmd_write_at_upper`] +#[doc = "cmd_write_at_upper (rw) register accessor: Cadence QSPI Command Write at Upper\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_write_at_upper::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_write_at_upper::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_write_at_upper`] module"] pub type CMD_WRITE_AT_UPPER = crate::Reg; #[doc = "Cadence QSPI Command Write at Upper"] pub mod cmd_write_at_upper; -#[doc = "polling_status (rw) register accessor: Cadence QSPI Polling Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`polling_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`polling_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`polling_status`] +#[doc = "polling_status (rw) register accessor: Cadence QSPI Polling Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`polling_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`polling_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@polling_status`] module"] pub type POLLING_STATUS = crate::Reg; #[doc = "Cadence QSPI Polling Status"] pub mod polling_status; -#[doc = "ext_lower (rw) register accessor: Cadence QSPI Extension Lower\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_lower::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_lower::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ext_lower`] +#[doc = "ext_lower (rw) register accessor: Cadence QSPI Extension Lower\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_lower::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_lower::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_lower`] module"] pub type EXT_LOWER = crate::Reg; #[doc = "Cadence QSPI Extension Lower"] diff --git a/jh7110-vf2-12a-pac/src/qspi/cmd_address.rs b/jh7110-vf2-12a-pac/src/qspi/cmd_address.rs index d508d41..5f821d2 100644 --- a/jh7110-vf2-12a-pac/src/qspi/cmd_address.rs +++ b/jh7110-vf2-12a-pac/src/qspi/cmd_address.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `address` reader - address"] pub type ADDRESS_R = crate::FieldReader; #[doc = "Field `address` writer - address"] -pub type ADDRESS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - address"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - address"] #[inline(always)] #[must_use] - pub fn address(&mut self) -> ADDRESS_W { - ADDRESS_W::new(self) + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/cmd_ctrl.rs b/jh7110-vf2-12a-pac/src/qspi/cmd_ctrl.rs index 8a263f0..69e1036 100644 --- a/jh7110-vf2-12a-pac/src/qspi/cmd_ctrl.rs +++ b/jh7110-vf2-12a-pac/src/qspi/cmd_ctrl.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `execute` reader - Execute-in-Place (XIP)"] pub type EXECUTE_R = crate::BitReader; #[doc = "Field `execute` writer - Execute-in-Place (XIP)"] -pub type EXECUTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EXECUTE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `in_progress` reader - Command in progress"] pub type IN_PROGRESS_R = crate::BitReader; #[doc = "Field `in_progress` writer - Command in progress"] -pub type IN_PROGRESS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IN_PROGRESS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dummy` reader - Dummy command"] pub type DUMMY_R = crate::FieldReader; #[doc = "Field `dummy` writer - Dummy command"] -pub type DUMMY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type DUMMY_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `wr_bytes` reader - Write bytes"] pub type WR_BYTES_R = crate::FieldReader; #[doc = "Field `wr_bytes` writer - Write bytes"] -pub type WR_BYTES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type WR_BYTES_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `wr_en` reader - Write enable"] pub type WR_EN_R = crate::BitReader; #[doc = "Field `wr_en` writer - Write enable"] -pub type WR_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type WR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `add_bytes` reader - Add command bytes"] pub type ADD_BYTES_R = crate::FieldReader; #[doc = "Field `add_bytes` writer - Add command bytes"] -pub type ADD_BYTES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type ADD_BYTES_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `addr_en` reader - Address enable"] pub type ADDR_EN_R = crate::BitReader; #[doc = "Field `addr_en` writer - Address enable"] -pub type ADDR_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ADDR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_bytes` reader - Read bytes"] pub type RD_BYTES_R = crate::FieldReader; #[doc = "Field `rd_bytes` writer - Read bytes"] -pub type RD_BYTES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type RD_BYTES_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `rd_en` reader - Read enable"] pub type RD_EN_R = crate::BitReader; #[doc = "Field `rd_en` writer - Read enable"] -pub type RD_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `opcode` reader - Command opcode"] pub type OPCODE_R = crate::FieldReader; #[doc = "Field `opcode` writer - Command opcode"] -pub type OPCODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type OPCODE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bit 0 - Execute-in-Place (XIP)"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bit 0 - Execute-in-Place (XIP)"] #[inline(always)] #[must_use] - pub fn execute(&mut self) -> EXECUTE_W { - EXECUTE_W::new(self) + pub fn execute(&mut self) -> EXECUTE_W { + EXECUTE_W::new(self, 0) } #[doc = "Bit 1 - Command in progress"] #[inline(always)] #[must_use] - pub fn in_progress(&mut self) -> IN_PROGRESS_W { - IN_PROGRESS_W::new(self) + pub fn in_progress(&mut self) -> IN_PROGRESS_W { + IN_PROGRESS_W::new(self, 1) } #[doc = "Bits 7:11 - Dummy command"] #[inline(always)] #[must_use] - pub fn dummy(&mut self) -> DUMMY_W { - DUMMY_W::new(self) + pub fn dummy(&mut self) -> DUMMY_W { + DUMMY_W::new(self, 7) } #[doc = "Bits 12:14 - Write bytes"] #[inline(always)] #[must_use] - pub fn wr_bytes(&mut self) -> WR_BYTES_W { - WR_BYTES_W::new(self) + pub fn wr_bytes(&mut self) -> WR_BYTES_W { + WR_BYTES_W::new(self, 12) } #[doc = "Bit 15 - Write enable"] #[inline(always)] #[must_use] - pub fn wr_en(&mut self) -> WR_EN_W { - WR_EN_W::new(self) + pub fn wr_en(&mut self) -> WR_EN_W { + WR_EN_W::new(self, 15) } #[doc = "Bits 16:17 - Add command bytes"] #[inline(always)] #[must_use] - pub fn add_bytes(&mut self) -> ADD_BYTES_W { - ADD_BYTES_W::new(self) + pub fn add_bytes(&mut self) -> ADD_BYTES_W { + ADD_BYTES_W::new(self, 16) } #[doc = "Bit 19 - Address enable"] #[inline(always)] #[must_use] - pub fn addr_en(&mut self) -> ADDR_EN_W { - ADDR_EN_W::new(self) + pub fn addr_en(&mut self) -> ADDR_EN_W { + ADDR_EN_W::new(self, 19) } #[doc = "Bits 20:22 - Read bytes"] #[inline(always)] #[must_use] - pub fn rd_bytes(&mut self) -> RD_BYTES_W { - RD_BYTES_W::new(self) + pub fn rd_bytes(&mut self) -> RD_BYTES_W { + RD_BYTES_W::new(self, 20) } #[doc = "Bit 23 - Read enable"] #[inline(always)] #[must_use] - pub fn rd_en(&mut self) -> RD_EN_W { - RD_EN_W::new(self) + pub fn rd_en(&mut self) -> RD_EN_W { + RD_EN_W::new(self, 23) } #[doc = "Bits 24:31 - Command opcode"] #[inline(always)] #[must_use] - pub fn opcode(&mut self) -> OPCODE_W { - OPCODE_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn opcode(&mut self) -> OPCODE_W { + OPCODE_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/cmd_read_at_lower.rs b/jh7110-vf2-12a-pac/src/qspi/cmd_read_at_lower.rs index fb1f108..1604970 100644 --- a/jh7110-vf2-12a-pac/src/qspi/cmd_read_at_lower.rs +++ b/jh7110-vf2-12a-pac/src/qspi/cmd_read_at_lower.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `read_at_lower` reader - read_at_lower"] pub type READ_AT_LOWER_R = crate::FieldReader; #[doc = "Field `read_at_lower` writer - read_at_lower"] -pub type READ_AT_LOWER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type READ_AT_LOWER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - read_at_lower"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - read_at_lower"] #[inline(always)] #[must_use] - pub fn read_at_lower(&mut self) -> READ_AT_LOWER_W { - READ_AT_LOWER_W::new(self) + pub fn read_at_lower(&mut self) -> READ_AT_LOWER_W { + READ_AT_LOWER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/cmd_read_at_upper.rs b/jh7110-vf2-12a-pac/src/qspi/cmd_read_at_upper.rs index f829ee5..6f7d5e6 100644 --- a/jh7110-vf2-12a-pac/src/qspi/cmd_read_at_upper.rs +++ b/jh7110-vf2-12a-pac/src/qspi/cmd_read_at_upper.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `read_at_upper` reader - read_at_upper"] pub type READ_AT_UPPER_R = crate::FieldReader; #[doc = "Field `read_at_upper` writer - read_at_upper"] -pub type READ_AT_UPPER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type READ_AT_UPPER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - read_at_upper"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - read_at_upper"] #[inline(always)] #[must_use] - pub fn read_at_upper(&mut self) -> READ_AT_UPPER_W { - READ_AT_UPPER_W::new(self) + pub fn read_at_upper(&mut self) -> READ_AT_UPPER_W { + READ_AT_UPPER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/cmd_write_at_lower.rs b/jh7110-vf2-12a-pac/src/qspi/cmd_write_at_lower.rs index 719d693..b98a00a 100644 --- a/jh7110-vf2-12a-pac/src/qspi/cmd_write_at_lower.rs +++ b/jh7110-vf2-12a-pac/src/qspi/cmd_write_at_lower.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `write_at_lower` reader - write_at_lower"] pub type WRITE_AT_LOWER_R = crate::FieldReader; #[doc = "Field `write_at_lower` writer - write_at_lower"] -pub type WRITE_AT_LOWER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type WRITE_AT_LOWER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - write_at_lower"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - write_at_lower"] #[inline(always)] #[must_use] - pub fn write_at_lower(&mut self) -> WRITE_AT_LOWER_W { - WRITE_AT_LOWER_W::new(self) + pub fn write_at_lower(&mut self) -> WRITE_AT_LOWER_W { + WRITE_AT_LOWER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/cmd_write_at_upper.rs b/jh7110-vf2-12a-pac/src/qspi/cmd_write_at_upper.rs index 7dc97fd..ebf247e 100644 --- a/jh7110-vf2-12a-pac/src/qspi/cmd_write_at_upper.rs +++ b/jh7110-vf2-12a-pac/src/qspi/cmd_write_at_upper.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `write_at_upper` reader - write_at_upper"] pub type WRITE_AT_UPPER_R = crate::FieldReader; #[doc = "Field `write_at_upper` writer - write_at_upper"] -pub type WRITE_AT_UPPER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type WRITE_AT_UPPER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - write_at_upper"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - write_at_upper"] #[inline(always)] #[must_use] - pub fn write_at_upper(&mut self) -> WRITE_AT_UPPER_W { - WRITE_AT_UPPER_W::new(self) + pub fn write_at_upper(&mut self) -> WRITE_AT_UPPER_W { + WRITE_AT_UPPER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/config.rs b/jh7110-vf2-12a-pac/src/qspi/config.rs index 8db366f..7d63937 100644 --- a/jh7110-vf2-12a-pac/src/qspi/config.rs +++ b/jh7110-vf2-12a-pac/src/qspi/config.rs @@ -5,39 +5,39 @@ pub type W = crate::W; #[doc = "Field `enable` reader - Enable the QSPI controller"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `enable` writer - Enable the QSPI controller"] -pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `enb_dir_acc_ctrl` reader - Enable direct access controller"] pub type ENB_DIR_ACC_CTRL_R = crate::BitReader; #[doc = "Field `enb_dir_acc_ctrl` writer - Enable direct access controller"] -pub type ENB_DIR_ACC_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ENB_DIR_ACC_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `decode` reader - Enable the QSPI decoder"] pub type DECODE_R = crate::BitReader; #[doc = "Field `decode` writer - Enable the QSPI decoder"] -pub type DECODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DECODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `chipselect` reader - Chip select - CS0: 0b1110, CS1: 0b1101, CS2: 0b1011, CS3: 0b0111"] pub type CHIPSELECT_R = crate::FieldReader; #[doc = "Field `chipselect` writer - Chip select - CS0: 0b1110, CS1: 0b1101, CS2: 0b1011, CS3: 0b0111"] -pub type CHIPSELECT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type CHIPSELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `dma` reader - Enable Direct Memory Access"] pub type DMA_R = crate::BitReader; #[doc = "Field `dma` writer - Enable Direct Memory Access"] -pub type DMA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `baud` reader - Set the QSPI BAUD rate divisor"] pub type BAUD_R = crate::FieldReader; #[doc = "Field `baud` writer - Set the QSPI BAUD rate divisor"] -pub type BAUD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type BAUD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `dtr_proto` reader - Enable DTR Protocol"] pub type DTR_PROTO_R = crate::BitReader; #[doc = "Field `dtr_proto` writer - Enable DTR Protocol"] -pub type DTR_PROTO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DTR_PROTO_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dual_opcode` reader - Enable Dual Opcode Mode"] pub type DUAL_OPCODE_R = crate::BitReader; #[doc = "Field `dual_opcode` writer - Enable Dual Opcode Mode"] -pub type DUAL_OPCODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DUAL_OPCODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `idle` reader - Set Idle"] pub type IDLE_R = crate::BitReader; #[doc = "Field `idle` writer - Set Idle"] -pub type IDLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IDLE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable the QSPI controller"] #[inline(always)] @@ -89,58 +89,62 @@ impl W { #[doc = "Bit 0 - Enable the QSPI controller"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W { - ENABLE_W::new(self) + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 0) } #[doc = "Bit 7 - Enable direct access controller"] #[inline(always)] #[must_use] - pub fn enb_dir_acc_ctrl(&mut self) -> ENB_DIR_ACC_CTRL_W { - ENB_DIR_ACC_CTRL_W::new(self) + pub fn enb_dir_acc_ctrl(&mut self) -> ENB_DIR_ACC_CTRL_W { + ENB_DIR_ACC_CTRL_W::new(self, 7) } #[doc = "Bit 9 - Enable the QSPI decoder"] #[inline(always)] #[must_use] - pub fn decode(&mut self) -> DECODE_W { - DECODE_W::new(self) + pub fn decode(&mut self) -> DECODE_W { + DECODE_W::new(self, 9) } #[doc = "Bits 10:13 - Chip select - CS0: 0b1110, CS1: 0b1101, CS2: 0b1011, CS3: 0b0111"] #[inline(always)] #[must_use] - pub fn chipselect(&mut self) -> CHIPSELECT_W { - CHIPSELECT_W::new(self) + pub fn chipselect(&mut self) -> CHIPSELECT_W { + CHIPSELECT_W::new(self, 10) } #[doc = "Bit 15 - Enable Direct Memory Access"] #[inline(always)] #[must_use] - pub fn dma(&mut self) -> DMA_W { - DMA_W::new(self) + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 15) } #[doc = "Bits 19:22 - Set the QSPI BAUD rate divisor"] #[inline(always)] #[must_use] - pub fn baud(&mut self) -> BAUD_W { - BAUD_W::new(self) + pub fn baud(&mut self) -> BAUD_W { + BAUD_W::new(self, 19) } #[doc = "Bit 24 - Enable DTR Protocol"] #[inline(always)] #[must_use] - pub fn dtr_proto(&mut self) -> DTR_PROTO_W { - DTR_PROTO_W::new(self) + pub fn dtr_proto(&mut self) -> DTR_PROTO_W { + DTR_PROTO_W::new(self, 24) } #[doc = "Bit 30 - Enable Dual Opcode Mode"] #[inline(always)] #[must_use] - pub fn dual_opcode(&mut self) -> DUAL_OPCODE_W { - DUAL_OPCODE_W::new(self) + pub fn dual_opcode(&mut self) -> DUAL_OPCODE_W { + DUAL_OPCODE_W::new(self, 30) } #[doc = "Bit 31 - Set Idle"] #[inline(always)] #[must_use] - pub fn idle(&mut self) -> IDLE_W { - IDLE_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn idle(&mut self) -> IDLE_W { + IDLE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/delay.rs b/jh7110-vf2-12a-pac/src/qspi/delay.rs index 3614dc4..41252ea 100644 --- a/jh7110-vf2-12a-pac/src/qspi/delay.rs +++ b/jh7110-vf2-12a-pac/src/qspi/delay.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `tslch` reader - TSLCH Delay Value"] pub type TSLCH_R = crate::FieldReader; #[doc = "Field `tslch` writer - TSLCH Delay Value"] -pub type TSLCH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type TSLCH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `tchsh` reader - TCHSH Delay Value"] pub type TCHSH_R = crate::FieldReader; #[doc = "Field `tchsh` writer - TCHSH Delay Value"] -pub type TCHSH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type TCHSH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `tsd2d` reader - TSD2D Delay Value"] pub type TSD2D_R = crate::FieldReader; #[doc = "Field `tsd2d` writer - TSD2D Delay Value"] -pub type TSD2D_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type TSD2D_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `tshsl` reader - TSHSL Delay Value"] pub type TSHSL_R = crate::FieldReader; #[doc = "Field `tshsl` writer - TSHSL Delay Value"] -pub type TSHSL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type TSHSL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - TSLCH Delay Value"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:7 - TSLCH Delay Value"] #[inline(always)] #[must_use] - pub fn tslch(&mut self) -> TSLCH_W { - TSLCH_W::new(self) + pub fn tslch(&mut self) -> TSLCH_W { + TSLCH_W::new(self, 0) } #[doc = "Bits 8:15 - TCHSH Delay Value"] #[inline(always)] #[must_use] - pub fn tchsh(&mut self) -> TCHSH_W { - TCHSH_W::new(self) + pub fn tchsh(&mut self) -> TCHSH_W { + TCHSH_W::new(self, 8) } #[doc = "Bits 16:23 - TSD2D Delay Value"] #[inline(always)] #[must_use] - pub fn tsd2d(&mut self) -> TSD2D_W { - TSD2D_W::new(self) + pub fn tsd2d(&mut self) -> TSD2D_W { + TSD2D_W::new(self, 16) } #[doc = "Bits 24:31 - TSHSL Delay Value"] #[inline(always)] #[must_use] - pub fn tshsl(&mut self) -> TSHSL_W { - TSHSL_W::new(self) + pub fn tshsl(&mut self) -> TSHSL_W { + TSHSL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/dma.rs b/jh7110-vf2-12a-pac/src/qspi/dma.rs index 69f69f7..d092c2c 100644 --- a/jh7110-vf2-12a-pac/src/qspi/dma.rs +++ b/jh7110-vf2-12a-pac/src/qspi/dma.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `single` reader - single"] pub type SINGLE_R = crate::FieldReader; #[doc = "Field `single` writer - single"] -pub type SINGLE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SINGLE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `burst` reader - burst"] pub type BURST_R = crate::FieldReader; #[doc = "Field `burst` writer - burst"] -pub type BURST_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type BURST_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - single"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:7 - single"] #[inline(always)] #[must_use] - pub fn single(&mut self) -> SINGLE_W { - SINGLE_W::new(self) + pub fn single(&mut self) -> SINGLE_W { + SINGLE_W::new(self, 0) } #[doc = "Bits 8:15 - burst"] #[inline(always)] #[must_use] - pub fn burst(&mut self) -> BURST_W { - BURST_W::new(self) + pub fn burst(&mut self) -> BURST_W { + BURST_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/ext_lower.rs b/jh7110-vf2-12a-pac/src/qspi/ext_lower.rs index 680588c..6e216e5 100644 --- a/jh7110-vf2-12a-pac/src/qspi/ext_lower.rs +++ b/jh7110-vf2-12a-pac/src/qspi/ext_lower.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `stig` reader - stig"] pub type STIG_R = crate::FieldReader; #[doc = "Field `stig` writer - stig"] -pub type STIG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type STIG_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; #[doc = "Field `write` reader - write"] pub type WRITE_R = crate::FieldReader; #[doc = "Field `write` writer - write"] -pub type WRITE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type WRITE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `read` reader - read"] pub type READ_R = crate::FieldReader; #[doc = "Field `read` writer - read"] -pub type READ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type READ_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:15 - stig"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:15 - stig"] #[inline(always)] #[must_use] - pub fn stig(&mut self) -> STIG_W { - STIG_W::new(self) + pub fn stig(&mut self) -> STIG_W { + STIG_W::new(self, 0) } #[doc = "Bits 16:23 - write"] #[inline(always)] #[must_use] - pub fn write(&mut self) -> WRITE_W { - WRITE_W::new(self) + pub fn write(&mut self) -> WRITE_W { + WRITE_W::new(self, 16) } #[doc = "Bits 24:31 - read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W { - READ_W::new(self) + pub fn read(&mut self) -> READ_W { + READ_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/indirect_rd.rs b/jh7110-vf2-12a-pac/src/qspi/indirect_rd.rs index 3b7556b..b35b5ac 100644 --- a/jh7110-vf2-12a-pac/src/qspi/indirect_rd.rs +++ b/jh7110-vf2-12a-pac/src/qspi/indirect_rd.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `start` reader - Start indirect read"] pub type START_R = crate::BitReader; #[doc = "Field `start` writer - Start indirect read"] -pub type START_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `cancel` reader - Cancel indirect read"] pub type CANCEL_R = crate::BitReader; #[doc = "Field `cancel` writer - Cancel indirect read"] -pub type CANCEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CANCEL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `done` reader - Indirect read done"] pub type DONE_R = crate::BitReader; #[doc = "Field `done` writer - Indirect read done"] -pub type DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DONE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Start indirect read"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bit 0 - Start indirect read"] #[inline(always)] #[must_use] - pub fn start(&mut self) -> START_W { - START_W::new(self) + pub fn start(&mut self) -> START_W { + START_W::new(self, 0) } #[doc = "Bit 1 - Cancel indirect read"] #[inline(always)] #[must_use] - pub fn cancel(&mut self) -> CANCEL_W { - CANCEL_W::new(self) + pub fn cancel(&mut self) -> CANCEL_W { + CANCEL_W::new(self, 1) } #[doc = "Bit 5 - Indirect read done"] #[inline(always)] #[must_use] - pub fn done(&mut self) -> DONE_W { - DONE_W::new(self) + pub fn done(&mut self) -> DONE_W { + DONE_W::new(self, 5) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/indirect_rd_bytes.rs b/jh7110-vf2-12a-pac/src/qspi/indirect_rd_bytes.rs index a8a6fef..edbb0a9 100644 --- a/jh7110-vf2-12a-pac/src/qspi/indirect_rd_bytes.rs +++ b/jh7110-vf2-12a-pac/src/qspi/indirect_rd_bytes.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `bytes` reader - bytes"] pub type BYTES_R = crate::FieldReader; #[doc = "Field `bytes` writer - bytes"] -pub type BYTES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type BYTES_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - bytes"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - bytes"] #[inline(always)] #[must_use] - pub fn bytes(&mut self) -> BYTES_W { - BYTES_W::new(self) + pub fn bytes(&mut self) -> BYTES_W { + BYTES_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/indirect_rd_start_addr.rs b/jh7110-vf2-12a-pac/src/qspi/indirect_rd_start_addr.rs index aafb690..d10e9ab 100644 --- a/jh7110-vf2-12a-pac/src/qspi/indirect_rd_start_addr.rs +++ b/jh7110-vf2-12a-pac/src/qspi/indirect_rd_start_addr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `address` reader - address"] pub type ADDRESS_R = crate::FieldReader; #[doc = "Field `address` writer - address"] -pub type ADDRESS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - address"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - address"] #[inline(always)] #[must_use] - pub fn address(&mut self) -> ADDRESS_W { - ADDRESS_W::new(self) + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/indirect_rd_watermark.rs b/jh7110-vf2-12a-pac/src/qspi/indirect_rd_watermark.rs index d8c6380..205a080 100644 --- a/jh7110-vf2-12a-pac/src/qspi/indirect_rd_watermark.rs +++ b/jh7110-vf2-12a-pac/src/qspi/indirect_rd_watermark.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `watermark` reader - watermark"] pub type WATERMARK_R = crate::FieldReader; #[doc = "Field `watermark` writer - watermark"] -pub type WATERMARK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type WATERMARK_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - watermark"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - watermark"] #[inline(always)] #[must_use] - pub fn watermark(&mut self) -> WATERMARK_W { - WATERMARK_W::new(self) + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/indirect_trigger.rs b/jh7110-vf2-12a-pac/src/qspi/indirect_trigger.rs index ba6a3fa..464fa57 100644 --- a/jh7110-vf2-12a-pac/src/qspi/indirect_trigger.rs +++ b/jh7110-vf2-12a-pac/src/qspi/indirect_trigger.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `address` reader - address"] pub type ADDRESS_R = crate::FieldReader; #[doc = "Field `address` writer - address"] -pub type ADDRESS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - address"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - address"] #[inline(always)] #[must_use] - pub fn address(&mut self) -> ADDRESS_W { - ADDRESS_W::new(self) + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/indirect_wr.rs b/jh7110-vf2-12a-pac/src/qspi/indirect_wr.rs index b54ed68..6d2d076 100644 --- a/jh7110-vf2-12a-pac/src/qspi/indirect_wr.rs +++ b/jh7110-vf2-12a-pac/src/qspi/indirect_wr.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `start` reader - Start indirect write"] pub type START_R = crate::BitReader; #[doc = "Field `start` writer - Start indirect write"] -pub type START_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `cancel` reader - Cancel indirect write"] pub type CANCEL_R = crate::BitReader; #[doc = "Field `cancel` writer - Cancel indirect write"] -pub type CANCEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CANCEL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `done` reader - Indirect write done"] pub type DONE_R = crate::BitReader; #[doc = "Field `done` writer - Indirect write done"] -pub type DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DONE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Start indirect write"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bit 0 - Start indirect write"] #[inline(always)] #[must_use] - pub fn start(&mut self) -> START_W { - START_W::new(self) + pub fn start(&mut self) -> START_W { + START_W::new(self, 0) } #[doc = "Bit 1 - Cancel indirect write"] #[inline(always)] #[must_use] - pub fn cancel(&mut self) -> CANCEL_W { - CANCEL_W::new(self) + pub fn cancel(&mut self) -> CANCEL_W { + CANCEL_W::new(self, 1) } #[doc = "Bit 5 - Indirect write done"] #[inline(always)] #[must_use] - pub fn done(&mut self) -> DONE_W { - DONE_W::new(self) + pub fn done(&mut self) -> DONE_W { + DONE_W::new(self, 5) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/indirect_wr_bytes.rs b/jh7110-vf2-12a-pac/src/qspi/indirect_wr_bytes.rs index 7fb2291..0732f0a 100644 --- a/jh7110-vf2-12a-pac/src/qspi/indirect_wr_bytes.rs +++ b/jh7110-vf2-12a-pac/src/qspi/indirect_wr_bytes.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `bytes` reader - bytes"] pub type BYTES_R = crate::FieldReader; #[doc = "Field `bytes` writer - bytes"] -pub type BYTES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type BYTES_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - bytes"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - bytes"] #[inline(always)] #[must_use] - pub fn bytes(&mut self) -> BYTES_W { - BYTES_W::new(self) + pub fn bytes(&mut self) -> BYTES_W { + BYTES_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/indirect_wr_start_addr.rs b/jh7110-vf2-12a-pac/src/qspi/indirect_wr_start_addr.rs index a907a11..0ed2591 100644 --- a/jh7110-vf2-12a-pac/src/qspi/indirect_wr_start_addr.rs +++ b/jh7110-vf2-12a-pac/src/qspi/indirect_wr_start_addr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `address` reader - address"] pub type ADDRESS_R = crate::FieldReader; #[doc = "Field `address` writer - address"] -pub type ADDRESS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - address"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - address"] #[inline(always)] #[must_use] - pub fn address(&mut self) -> ADDRESS_W { - ADDRESS_W::new(self) + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/indirect_wr_watermark.rs b/jh7110-vf2-12a-pac/src/qspi/indirect_wr_watermark.rs index 3a95c8d..8d2065c 100644 --- a/jh7110-vf2-12a-pac/src/qspi/indirect_wr_watermark.rs +++ b/jh7110-vf2-12a-pac/src/qspi/indirect_wr_watermark.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `watermark` reader - watermark"] pub type WATERMARK_R = crate::FieldReader; #[doc = "Field `watermark` writer - watermark"] -pub type WATERMARK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type WATERMARK_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - watermark"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - watermark"] #[inline(always)] #[must_use] - pub fn watermark(&mut self) -> WATERMARK_W { - WATERMARK_W::new(self) + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/irq_mask.rs b/jh7110-vf2-12a-pac/src/qspi/irq_mask.rs index 5905f86..0f87114 100644 --- a/jh7110-vf2-12a-pac/src/qspi/irq_mask.rs +++ b/jh7110-vf2-12a-pac/src/qspi/irq_mask.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `mode_err` reader - Mode error interrupt"] pub type MODE_ERR_R = crate::BitReader; #[doc = "Field `mode_err` writer - Mode error interrupt"] -pub type MODE_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `underflow` reader - Buffer underflow interrupt"] pub type UNDERFLOW_R = crate::BitReader; #[doc = "Field `underflow` writer - Buffer underflow interrupt"] -pub type UNDERFLOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type UNDERFLOW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ind_comp` reader - Indirect computation interrupt"] pub type IND_COMP_R = crate::BitReader; #[doc = "Field `ind_comp` writer - Indirect computation interrupt"] -pub type IND_COMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IND_COMP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ind_rd_reject` reader - Indirect read rejection interrupt"] pub type IND_RD_REJECT_R = crate::BitReader; #[doc = "Field `ind_rd_reject` writer - Indirect read rejection interrupt"] -pub type IND_RD_REJECT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IND_RD_REJECT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `wr_protected_err` reader - Write protected error interrupt"] pub type WR_PROTECTED_ERR_R = crate::BitReader; #[doc = "Field `wr_protected_err` writer - Write protected error interrupt"] -pub type WR_PROTECTED_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type WR_PROTECTED_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `illegal_ahb_err` reader - Illegal AHB clock error interrupt"] pub type ILLEGAL_AHB_ERR_R = crate::BitReader; #[doc = "Field `illegal_ahb_err` writer - Illegal AHB clock error interrupt"] -pub type ILLEGAL_AHB_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ILLEGAL_AHB_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `watermark` reader - Watermark interrupt"] pub type WATERMARK_R = crate::BitReader; #[doc = "Field `watermark` writer - Watermark interrupt"] -pub type WATERMARK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type WATERMARK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ind_sram_full` reader - Indirect SRAM full interrupt"] pub type IND_SRAM_FULL_R = crate::BitReader; #[doc = "Field `ind_sram_full` writer - Indirect SRAM full interrupt"] -pub type IND_SRAM_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IND_SRAM_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Mode error interrupt"] #[inline(always)] @@ -80,52 +80,56 @@ impl W { #[doc = "Bit 0 - Mode error interrupt"] #[inline(always)] #[must_use] - pub fn mode_err(&mut self) -> MODE_ERR_W { - MODE_ERR_W::new(self) + pub fn mode_err(&mut self) -> MODE_ERR_W { + MODE_ERR_W::new(self, 0) } #[doc = "Bit 1 - Buffer underflow interrupt"] #[inline(always)] #[must_use] - pub fn underflow(&mut self) -> UNDERFLOW_W { - UNDERFLOW_W::new(self) + pub fn underflow(&mut self) -> UNDERFLOW_W { + UNDERFLOW_W::new(self, 1) } #[doc = "Bit 2 - Indirect computation interrupt"] #[inline(always)] #[must_use] - pub fn ind_comp(&mut self) -> IND_COMP_W { - IND_COMP_W::new(self) + pub fn ind_comp(&mut self) -> IND_COMP_W { + IND_COMP_W::new(self, 2) } #[doc = "Bit 3 - Indirect read rejection interrupt"] #[inline(always)] #[must_use] - pub fn ind_rd_reject(&mut self) -> IND_RD_REJECT_W { - IND_RD_REJECT_W::new(self) + pub fn ind_rd_reject(&mut self) -> IND_RD_REJECT_W { + IND_RD_REJECT_W::new(self, 3) } #[doc = "Bit 4 - Write protected error interrupt"] #[inline(always)] #[must_use] - pub fn wr_protected_err(&mut self) -> WR_PROTECTED_ERR_W { - WR_PROTECTED_ERR_W::new(self) + pub fn wr_protected_err(&mut self) -> WR_PROTECTED_ERR_W { + WR_PROTECTED_ERR_W::new(self, 4) } #[doc = "Bit 5 - Illegal AHB clock error interrupt"] #[inline(always)] #[must_use] - pub fn illegal_ahb_err(&mut self) -> ILLEGAL_AHB_ERR_W { - ILLEGAL_AHB_ERR_W::new(self) + pub fn illegal_ahb_err(&mut self) -> ILLEGAL_AHB_ERR_W { + ILLEGAL_AHB_ERR_W::new(self, 5) } #[doc = "Bit 6 - Watermark interrupt"] #[inline(always)] #[must_use] - pub fn watermark(&mut self) -> WATERMARK_W { - WATERMARK_W::new(self) + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W::new(self, 6) } #[doc = "Bit 12 - Indirect SRAM full interrupt"] #[inline(always)] #[must_use] - pub fn ind_sram_full(&mut self) -> IND_SRAM_FULL_W { - IND_SRAM_FULL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn ind_sram_full(&mut self) -> IND_SRAM_FULL_W { + IND_SRAM_FULL_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/irq_status.rs b/jh7110-vf2-12a-pac/src/qspi/irq_status.rs index 2d399ef..4401e3f 100644 --- a/jh7110-vf2-12a-pac/src/qspi/irq_status.rs +++ b/jh7110-vf2-12a-pac/src/qspi/irq_status.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `mode_err` reader - Mode error interrupt"] pub type MODE_ERR_R = crate::BitReader; #[doc = "Field `mode_err` writer - Mode error interrupt"] -pub type MODE_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `underflow` reader - Buffer underflow interrupt"] pub type UNDERFLOW_R = crate::BitReader; #[doc = "Field `underflow` writer - Buffer underflow interrupt"] -pub type UNDERFLOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type UNDERFLOW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ind_comp` reader - Indirect computation interrupt"] pub type IND_COMP_R = crate::BitReader; #[doc = "Field `ind_comp` writer - Indirect computation interrupt"] -pub type IND_COMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IND_COMP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ind_rd_reject` reader - Indirect read rejection interrupt"] pub type IND_RD_REJECT_R = crate::BitReader; #[doc = "Field `ind_rd_reject` writer - Indirect read rejection interrupt"] -pub type IND_RD_REJECT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IND_RD_REJECT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `wr_protected_err` reader - Write protected error interrupt"] pub type WR_PROTECTED_ERR_R = crate::BitReader; #[doc = "Field `wr_protected_err` writer - Write protected error interrupt"] -pub type WR_PROTECTED_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type WR_PROTECTED_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `illegal_ahb_err` reader - Illegal AHB clock error interrupt"] pub type ILLEGAL_AHB_ERR_R = crate::BitReader; #[doc = "Field `illegal_ahb_err` writer - Illegal AHB clock error interrupt"] -pub type ILLEGAL_AHB_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ILLEGAL_AHB_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `watermark` reader - Watermark interrupt"] pub type WATERMARK_R = crate::BitReader; #[doc = "Field `watermark` writer - Watermark interrupt"] -pub type WATERMARK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type WATERMARK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ind_sram_full` reader - Indirect SRAM full interrupt"] pub type IND_SRAM_FULL_R = crate::BitReader; #[doc = "Field `ind_sram_full` writer - Indirect SRAM full interrupt"] -pub type IND_SRAM_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IND_SRAM_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Mode error interrupt"] #[inline(always)] @@ -80,52 +80,56 @@ impl W { #[doc = "Bit 0 - Mode error interrupt"] #[inline(always)] #[must_use] - pub fn mode_err(&mut self) -> MODE_ERR_W { - MODE_ERR_W::new(self) + pub fn mode_err(&mut self) -> MODE_ERR_W { + MODE_ERR_W::new(self, 0) } #[doc = "Bit 1 - Buffer underflow interrupt"] #[inline(always)] #[must_use] - pub fn underflow(&mut self) -> UNDERFLOW_W { - UNDERFLOW_W::new(self) + pub fn underflow(&mut self) -> UNDERFLOW_W { + UNDERFLOW_W::new(self, 1) } #[doc = "Bit 2 - Indirect computation interrupt"] #[inline(always)] #[must_use] - pub fn ind_comp(&mut self) -> IND_COMP_W { - IND_COMP_W::new(self) + pub fn ind_comp(&mut self) -> IND_COMP_W { + IND_COMP_W::new(self, 2) } #[doc = "Bit 3 - Indirect read rejection interrupt"] #[inline(always)] #[must_use] - pub fn ind_rd_reject(&mut self) -> IND_RD_REJECT_W { - IND_RD_REJECT_W::new(self) + pub fn ind_rd_reject(&mut self) -> IND_RD_REJECT_W { + IND_RD_REJECT_W::new(self, 3) } #[doc = "Bit 4 - Write protected error interrupt"] #[inline(always)] #[must_use] - pub fn wr_protected_err(&mut self) -> WR_PROTECTED_ERR_W { - WR_PROTECTED_ERR_W::new(self) + pub fn wr_protected_err(&mut self) -> WR_PROTECTED_ERR_W { + WR_PROTECTED_ERR_W::new(self, 4) } #[doc = "Bit 5 - Illegal AHB clock error interrupt"] #[inline(always)] #[must_use] - pub fn illegal_ahb_err(&mut self) -> ILLEGAL_AHB_ERR_W { - ILLEGAL_AHB_ERR_W::new(self) + pub fn illegal_ahb_err(&mut self) -> ILLEGAL_AHB_ERR_W { + ILLEGAL_AHB_ERR_W::new(self, 5) } #[doc = "Bit 6 - Watermark interrupt"] #[inline(always)] #[must_use] - pub fn watermark(&mut self) -> WATERMARK_W { - WATERMARK_W::new(self) + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W::new(self, 6) } #[doc = "Bit 12 - Indirect SRAM full interrupt"] #[inline(always)] #[must_use] - pub fn ind_sram_full(&mut self) -> IND_SRAM_FULL_W { - IND_SRAM_FULL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn ind_sram_full(&mut self) -> IND_SRAM_FULL_W { + IND_SRAM_FULL_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/mode_bit.rs b/jh7110-vf2-12a-pac/src/qspi/mode_bit.rs index fd794a8..8190db7 100644 --- a/jh7110-vf2-12a-pac/src/qspi/mode_bit.rs +++ b/jh7110-vf2-12a-pac/src/qspi/mode_bit.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `mode` reader - mode"] pub type MODE_R = crate::FieldReader; #[doc = "Field `mode` writer - mode"] -pub type MODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - mode"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - mode"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W { - MODE_W::new(self) + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/polling_status.rs b/jh7110-vf2-12a-pac/src/qspi/polling_status.rs index a1a1a6b..48c87b0 100644 --- a/jh7110-vf2-12a-pac/src/qspi/polling_status.rs +++ b/jh7110-vf2-12a-pac/src/qspi/polling_status.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `status` reader - status"] pub type STATUS_R = crate::FieldReader; #[doc = "Field `status` writer - status"] -pub type STATUS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type STATUS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; #[doc = "Field `dummy` reader - dummy"] pub type DUMMY_R = crate::FieldReader; #[doc = "Field `dummy` writer - dummy"] -pub type DUMMY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type DUMMY_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; impl R { #[doc = "Bits 0:15 - status"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:15 - status"] #[inline(always)] #[must_use] - pub fn status(&mut self) -> STATUS_W { - STATUS_W::new(self) + pub fn status(&mut self) -> STATUS_W { + STATUS_W::new(self, 0) } #[doc = "Bits 16:20 - dummy"] #[inline(always)] #[must_use] - pub fn dummy(&mut self) -> DUMMY_W { - DUMMY_W::new(self) + pub fn dummy(&mut self) -> DUMMY_W { + DUMMY_W::new(self, 16) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/rd_instr.rs b/jh7110-vf2-12a-pac/src/qspi/rd_instr.rs index 01773c7..a14d7d8 100644 --- a/jh7110-vf2-12a-pac/src/qspi/rd_instr.rs +++ b/jh7110-vf2-12a-pac/src/qspi/rd_instr.rs @@ -5,27 +5,27 @@ pub type W = crate::W; #[doc = "Field `opcode` reader - Instruction Opcode"] pub type OPCODE_R = crate::FieldReader; #[doc = "Field `opcode` writer - Instruction Opcode"] -pub type OPCODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type OPCODE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `type_instr` reader - Type of Instruction"] pub type TYPE_INSTR_R = crate::FieldReader; #[doc = "Field `type_instr` writer - Type of Instruction"] -pub type TYPE_INSTR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TYPE_INSTR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `type_addr` reader - Type of Address"] pub type TYPE_ADDR_R = crate::FieldReader; #[doc = "Field `type_addr` writer - Type of Address"] -pub type TYPE_ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TYPE_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `type_data` reader - type_data"] pub type TYPE_DATA_R = crate::FieldReader; #[doc = "Field `type_data` writer - type_data"] -pub type TYPE_DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TYPE_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `mode_en` reader - Mode"] pub type MODE_EN_R = crate::BitReader; #[doc = "Field `mode_en` writer - Mode"] -pub type MODE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dummy` reader - Send dummy signal to stall the device"] pub type DUMMY_R = crate::FieldReader; #[doc = "Field `dummy` writer - Send dummy signal to stall the device"] -pub type DUMMY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type DUMMY_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; impl R { #[doc = "Bits 0:7 - Instruction Opcode"] #[inline(always)] @@ -62,40 +62,44 @@ impl W { #[doc = "Bits 0:7 - Instruction Opcode"] #[inline(always)] #[must_use] - pub fn opcode(&mut self) -> OPCODE_W { - OPCODE_W::new(self) + pub fn opcode(&mut self) -> OPCODE_W { + OPCODE_W::new(self, 0) } #[doc = "Bits 8:9 - Type of Instruction"] #[inline(always)] #[must_use] - pub fn type_instr(&mut self) -> TYPE_INSTR_W { - TYPE_INSTR_W::new(self) + pub fn type_instr(&mut self) -> TYPE_INSTR_W { + TYPE_INSTR_W::new(self, 8) } #[doc = "Bits 12:13 - Type of Address"] #[inline(always)] #[must_use] - pub fn type_addr(&mut self) -> TYPE_ADDR_W { - TYPE_ADDR_W::new(self) + pub fn type_addr(&mut self) -> TYPE_ADDR_W { + TYPE_ADDR_W::new(self, 12) } #[doc = "Bits 16:17 - type_data"] #[inline(always)] #[must_use] - pub fn type_data(&mut self) -> TYPE_DATA_W { - TYPE_DATA_W::new(self) + pub fn type_data(&mut self) -> TYPE_DATA_W { + TYPE_DATA_W::new(self, 16) } #[doc = "Bit 20 - Mode"] #[inline(always)] #[must_use] - pub fn mode_en(&mut self) -> MODE_EN_W { - MODE_EN_W::new(self) + pub fn mode_en(&mut self) -> MODE_EN_W { + MODE_EN_W::new(self, 20) } #[doc = "Bits 24:28 - Send dummy signal to stall the device"] #[inline(always)] #[must_use] - pub fn dummy(&mut self) -> DUMMY_W { - DUMMY_W::new(self) + pub fn dummy(&mut self) -> DUMMY_W { + DUMMY_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/read_capture.rs b/jh7110-vf2-12a-pac/src/qspi/read_capture.rs index 95a546d..e9d9683 100644 --- a/jh7110-vf2-12a-pac/src/qspi/read_capture.rs +++ b/jh7110-vf2-12a-pac/src/qspi/read_capture.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `bypass` reader - Bypass the Read Capture"] pub type BYPASS_R = crate::BitReader; #[doc = "Field `bypass` writer - Bypass the Read Capture"] -pub type BYPASS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `delay` reader - Read Capture Delay Value"] pub type DELAY_R = crate::FieldReader; #[doc = "Field `delay` writer - Read Capture Delay Value"] -pub type DELAY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bit 0 - Bypass the Read Capture"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Bypass the Read Capture"] #[inline(always)] #[must_use] - pub fn bypass(&mut self) -> BYPASS_W { - BYPASS_W::new(self) + pub fn bypass(&mut self) -> BYPASS_W { + BYPASS_W::new(self, 0) } #[doc = "Bits 1:4 - Read Capture Delay Value"] #[inline(always)] #[must_use] - pub fn delay(&mut self) -> DELAY_W { - DELAY_W::new(self) + pub fn delay(&mut self) -> DELAY_W { + DELAY_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/remap.rs b/jh7110-vf2-12a-pac/src/qspi/remap.rs index 08817cf..61a35ba 100644 --- a/jh7110-vf2-12a-pac/src/qspi/remap.rs +++ b/jh7110-vf2-12a-pac/src/qspi/remap.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `address` reader - address"] pub type ADDRESS_R = crate::FieldReader; #[doc = "Field `address` writer - address"] -pub type ADDRESS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - address"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - address"] #[inline(always)] #[must_use] - pub fn address(&mut self) -> ADDRESS_W { - ADDRESS_W::new(self) + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/sdram_level.rs b/jh7110-vf2-12a-pac/src/qspi/sdram_level.rs index 9b85b9b..43f3d10 100644 --- a/jh7110-vf2-12a-pac/src/qspi/sdram_level.rs +++ b/jh7110-vf2-12a-pac/src/qspi/sdram_level.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/size.rs b/jh7110-vf2-12a-pac/src/qspi/size.rs index de6de89..bd4058d 100644 --- a/jh7110-vf2-12a-pac/src/qspi/size.rs +++ b/jh7110-vf2-12a-pac/src/qspi/size.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `address` reader - Address Size in Bytes"] pub type ADDRESS_R = crate::FieldReader; #[doc = "Field `address` writer - Address Size in Bytes"] -pub type ADDRESS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `page` reader - Page Size in Bytes"] pub type PAGE_R = crate::FieldReader; #[doc = "Field `page` writer - Page Size in Bytes"] -pub type PAGE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; +pub type PAGE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; #[doc = "Field `block` reader - Block Size in Bytes"] pub type BLOCK_R = crate::FieldReader; #[doc = "Field `block` writer - Block Size in Bytes"] -pub type BLOCK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type BLOCK_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:3 - Address Size in Bytes"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:3 - Address Size in Bytes"] #[inline(always)] #[must_use] - pub fn address(&mut self) -> ADDRESS_W { - ADDRESS_W::new(self) + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) } #[doc = "Bits 4:15 - Page Size in Bytes"] #[inline(always)] #[must_use] - pub fn page(&mut self) -> PAGE_W { - PAGE_W::new(self) + pub fn page(&mut self) -> PAGE_W { + PAGE_W::new(self, 4) } #[doc = "Bits 16:21 - Block Size in Bytes"] #[inline(always)] #[must_use] - pub fn block(&mut self) -> BLOCK_W { - BLOCK_W::new(self) + pub fn block(&mut self) -> BLOCK_W { + BLOCK_W::new(self, 16) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/sram_partition.rs b/jh7110-vf2-12a-pac/src/qspi/sram_partition.rs index c2a5fd0..daf2451 100644 --- a/jh7110-vf2-12a-pac/src/qspi/sram_partition.rs +++ b/jh7110-vf2-12a-pac/src/qspi/sram_partition.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `size` reader - Partition size in bytes"] pub type SIZE_R = crate::FieldReader; #[doc = "Field `size` writer - Partition size in bytes"] -pub type SIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - Partition size in bytes"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - Partition size in bytes"] #[inline(always)] #[must_use] - pub fn size(&mut self) -> SIZE_W { - SIZE_W::new(self) + pub fn size(&mut self) -> SIZE_W { + SIZE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/wr_completion_ctrl.rs b/jh7110-vf2-12a-pac/src/qspi/wr_completion_ctrl.rs index 8413a1e..dbefab4 100644 --- a/jh7110-vf2-12a-pac/src/qspi/wr_completion_ctrl.rs +++ b/jh7110-vf2-12a-pac/src/qspi/wr_completion_ctrl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `disable_auto_poll` reader - SPI NAND flashes require the address of the status register to be passed in the Read SR command. Also, some SPI NOR flashes like the Cypress Semper flash expect a 4-byte dummy address in the Read SR command in DTR mode. But this controller does not support address phase in the Read SR command when doing auto-HW polling. So, disable write completion polling on the controller's side. spi-nand and spi-nor will take care of polling the status register."] pub type DISABLE_AUTO_POLL_R = crate::BitReader; #[doc = "Field `disable_auto_poll` writer - SPI NAND flashes require the address of the status register to be passed in the Read SR command. Also, some SPI NOR flashes like the Cypress Semper flash expect a 4-byte dummy address in the Read SR command in DTR mode. But this controller does not support address phase in the Read SR command when doing auto-HW polling. So, disable write completion polling on the controller's side. spi-nand and spi-nor will take care of polling the status register."] -pub type DISABLE_AUTO_POLL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DISABLE_AUTO_POLL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 14 - SPI NAND flashes require the address of the status register to be passed in the Read SR command. Also, some SPI NOR flashes like the Cypress Semper flash expect a 4-byte dummy address in the Read SR command in DTR mode. But this controller does not support address phase in the Read SR command when doing auto-HW polling. So, disable write completion polling on the controller's side. spi-nand and spi-nor will take care of polling the status register."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 14 - SPI NAND flashes require the address of the status register to be passed in the Read SR command. Also, some SPI NOR flashes like the Cypress Semper flash expect a 4-byte dummy address in the Read SR command in DTR mode. But this controller does not support address phase in the Read SR command when doing auto-HW polling. So, disable write completion polling on the controller's side. spi-nand and spi-nor will take care of polling the status register."] #[inline(always)] #[must_use] - pub fn disable_auto_poll(&mut self) -> DISABLE_AUTO_POLL_W { - DISABLE_AUTO_POLL_W::new(self) + pub fn disable_auto_poll(&mut self) -> DISABLE_AUTO_POLL_W { + DISABLE_AUTO_POLL_W::new(self, 14) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/qspi/wr_instr.rs b/jh7110-vf2-12a-pac/src/qspi/wr_instr.rs index 8a9c951..2d0ba7a 100644 --- a/jh7110-vf2-12a-pac/src/qspi/wr_instr.rs +++ b/jh7110-vf2-12a-pac/src/qspi/wr_instr.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `opcode` reader - Instruction Opcode"] pub type OPCODE_R = crate::FieldReader; #[doc = "Field `opcode` writer - Instruction Opcode"] -pub type OPCODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type OPCODE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `type_addr` reader - Type of Address"] pub type TYPE_ADDR_R = crate::FieldReader; #[doc = "Field `type_addr` writer - Type of Address"] -pub type TYPE_ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TYPE_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `type_data` reader - type_data"] pub type TYPE_DATA_R = crate::FieldReader; #[doc = "Field `type_data` writer - type_data"] -pub type TYPE_DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TYPE_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:7 - Instruction Opcode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:7 - Instruction Opcode"] #[inline(always)] #[must_use] - pub fn opcode(&mut self) -> OPCODE_W { - OPCODE_W::new(self) + pub fn opcode(&mut self) -> OPCODE_W { + OPCODE_W::new(self, 0) } #[doc = "Bits 12:13 - Type of Address"] #[inline(always)] #[must_use] - pub fn type_addr(&mut self) -> TYPE_ADDR_W { - TYPE_ADDR_W::new(self) + pub fn type_addr(&mut self) -> TYPE_ADDR_W { + TYPE_ADDR_W::new(self, 12) } #[doc = "Bits 16:17 - type_data"] #[inline(always)] #[must_use] - pub fn type_data(&mut self) -> TYPE_DATA_W { - TYPE_DATA_W::new(self) + pub fn type_data(&mut self) -> TYPE_DATA_W { + TYPE_DATA_W::new(self, 16) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0.rs b/jh7110-vf2-12a-pac/src/spi0.rs index e1d7fdc..6e69208 100644 --- a/jh7110-vf2-12a-pac/src/spi0.rs +++ b/jh7110-vf2-12a-pac/src/spi0.rs @@ -1,146 +1,220 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] - pub ssp_cr0: SSP_CR0, + ssp_cr0: SSP_CR0, _reserved1: [u8; 0x02], - #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] - pub ssp_cr1: SSP_CR1, + ssp_cr1: SSP_CR1, _reserved2: [u8; 0x02], - #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] - pub ssp_dr: SSP_DR, + ssp_dr: SSP_DR, _reserved3: [u8; 0x02], - #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] - pub ssp_sr: SSP_SR, + ssp_sr: SSP_SR, _reserved4: [u8; 0x02], - #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] - pub ssp_cpsr: SSP_CPSR, + ssp_cpsr: SSP_CPSR, _reserved5: [u8; 0x02], - #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] - pub ssp_imsc: SSP_IMSC, + ssp_imsc: SSP_IMSC, _reserved6: [u8; 0x02], - #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] - pub ssp_ris: SSP_RIS, + ssp_ris: SSP_RIS, _reserved7: [u8; 0x02], - #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] - pub ssp_mis: SSP_MIS, + ssp_mis: SSP_MIS, _reserved8: [u8; 0x02], - #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] - pub ssp_icr: SSP_ICR, + ssp_icr: SSP_ICR, _reserved9: [u8; 0x02], - #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] - pub ssp_dmacr: SSP_DMACR, + ssp_dmacr: SSP_DMACR, _reserved10: [u8; 0x0fba], - #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id0: SSP_PERIPH_ID0, + ssp_periph_id0: SSP_PERIPH_ID0, _reserved11: [u8; 0x02], - #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id1: SSP_PERIPH_ID1, + ssp_periph_id1: SSP_PERIPH_ID1, _reserved12: [u8; 0x02], - #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id2: SSP_PERIPH_ID2, + ssp_periph_id2: SSP_PERIPH_ID2, _reserved13: [u8; 0x02], - #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id3: SSP_PERIPH_ID3, + ssp_periph_id3: SSP_PERIPH_ID3, _reserved14: [u8; 0x02], - #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id0: SSP_PCELL_ID0, + ssp_pcell_id0: SSP_PCELL_ID0, _reserved15: [u8; 0x02], - #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id1: SSP_PCELL_ID1, + ssp_pcell_id1: SSP_PCELL_ID1, _reserved16: [u8; 0x02], - #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id2: SSP_PCELL_ID2, + ssp_pcell_id2: SSP_PCELL_ID2, _reserved17: [u8; 0x02], + ssp_pcell_id3: SSP_PCELL_ID3, +} +impl RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr0(&self) -> &SSP_CR0 { + &self.ssp_cr0 + } + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr1(&self) -> &SSP_CR1 { + &self.ssp_cr1 + } + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + #[inline(always)] + pub const fn ssp_dr(&self) -> &SSP_DR { + &self.ssp_dr + } + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + #[inline(always)] + pub const fn ssp_sr(&self) -> &SSP_SR { + &self.ssp_sr + } + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + #[inline(always)] + pub const fn ssp_cpsr(&self) -> &SSP_CPSR { + &self.ssp_cpsr + } + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + #[inline(always)] + pub const fn ssp_imsc(&self) -> &SSP_IMSC { + &self.ssp_imsc + } + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + #[inline(always)] + pub const fn ssp_ris(&self) -> &SSP_RIS { + &self.ssp_ris + } + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + #[inline(always)] + pub const fn ssp_mis(&self) -> &SSP_MIS { + &self.ssp_mis + } + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + #[inline(always)] + pub const fn ssp_icr(&self) -> &SSP_ICR { + &self.ssp_icr + } + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + #[inline(always)] + pub const fn ssp_dmacr(&self) -> &SSP_DMACR { + &self.ssp_dmacr + } + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id0(&self) -> &SSP_PERIPH_ID0 { + &self.ssp_periph_id0 + } + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id1(&self) -> &SSP_PERIPH_ID1 { + &self.ssp_periph_id1 + } + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id2(&self) -> &SSP_PERIPH_ID2 { + &self.ssp_periph_id2 + } + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id3(&self) -> &SSP_PERIPH_ID3 { + &self.ssp_periph_id3 + } + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id0(&self) -> &SSP_PCELL_ID0 { + &self.ssp_pcell_id0 + } + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id1(&self) -> &SSP_PCELL_ID1 { + &self.ssp_pcell_id1 + } + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id2(&self) -> &SSP_PCELL_ID2 { + &self.ssp_pcell_id2 + } #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id3: SSP_PCELL_ID3, + #[inline(always)] + pub const fn ssp_pcell_id3(&self) -> &SSP_PCELL_ID3 { + &self.ssp_pcell_id3 + } } -#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr0`] module"] pub type SSP_CR0 = crate::Reg; #[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] pub mod ssp_cr0; -#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr1`] module"] pub type SSP_CR1 = crate::Reg; #[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] pub mod ssp_cr1; -#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dr`] module"] pub type SSP_DR = crate::Reg; #[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] pub mod ssp_dr; -#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_sr`] module"] pub type SSP_SR = crate::Reg; #[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] pub mod ssp_sr; -#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cpsr`] module"] pub type SSP_CPSR = crate::Reg; #[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] pub mod ssp_cpsr; -#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_imsc`] module"] pub type SSP_IMSC = crate::Reg; #[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] pub mod ssp_imsc; -#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_ris`] module"] pub type SSP_RIS = crate::Reg; #[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] pub mod ssp_ris; -#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_mis`] module"] pub type SSP_MIS = crate::Reg; #[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] pub mod ssp_mis; -#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_icr`] module"] pub type SSP_ICR = crate::Reg; #[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] pub mod ssp_icr; -#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dmacr`] module"] pub type SSP_DMACR = crate::Reg; #[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] pub mod ssp_dmacr; -#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id0`] module"] pub type SSP_PERIPH_ID0 = crate::Reg; #[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id0; -#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id1`] module"] pub type SSP_PERIPH_ID1 = crate::Reg; #[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id1; -#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id2`] module"] pub type SSP_PERIPH_ID2 = crate::Reg; #[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id2; -#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id3`] module"] pub type SSP_PERIPH_ID3 = crate::Reg; #[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id3; -#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id0`] module"] pub type SSP_PCELL_ID0 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id0; -#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id1`] module"] pub type SSP_PCELL_ID1 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id1; -#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id2`] module"] pub type SSP_PCELL_ID2 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id2; -#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id3`] module"] pub type SSP_PCELL_ID3 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_cpsr.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_cpsr.rs index 214d9da..2fa25a9 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_cpsr.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_cpsr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] pub type CPSDVSR_R = crate::FieldReader; #[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] -pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type CPSDVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] #[must_use] - pub fn cpsdvsr(&mut self) -> CPSDVSR_W { - CPSDVSR_W::new(self) + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_cr0.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_cr0.rs index 1f3740e..b3ee9c6 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_cr0.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_cr0.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `dss` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] pub type DSS_R = crate::FieldReader; #[doc = "Field `dss` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] -pub type DSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type DSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] pub type FRF_R = crate::FieldReader; #[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] -pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] pub type SPO_R = crate::BitReader; #[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] -pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPO_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] pub type SPH_R = crate::BitReader; #[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] -pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPH_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] @@ -56,35 +56,39 @@ impl W { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] #[must_use] - pub fn dss(&mut self) -> DSS_W { - DSS_W::new(self) + pub fn dss(&mut self) -> DSS_W { + DSS_W::new(self, 0) } #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] #[inline(always)] #[must_use] - pub fn frf(&mut self) -> FRF_W { - FRF_W::new(self) + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self, 4) } #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn spo(&mut self) -> SPO_W { - SPO_W::new(self) + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self, 6) } #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn sph(&mut self) -> SPH_W { - SPH_W::new(self) + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self, 6) } #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_cr1.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_cr1.rs index 69dbcbd..b115461 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_cr1.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_cr1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] pub type LBM_R = crate::BitReader; #[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] -pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LBM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] pub type SSE_R = crate::BitReader; #[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] -pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SSE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] pub type MS_R = crate::BitReader; #[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] -pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] pub type SOD_R = crate::BitReader; #[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] -pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SOD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] #[must_use] - pub fn lbm(&mut self) -> LBM_W { - LBM_W::new(self) + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self, 0) } #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] #[inline(always)] #[must_use] - pub fn sse(&mut self) -> SSE_W { - SSE_W::new(self) + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self, 1) } #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] #[inline(always)] #[must_use] - pub fn ms(&mut self) -> MS_W { - MS_W::new(self) + pub fn ms(&mut self) -> MS_W { + MS_W::new(self, 2) } #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] #[inline(always)] #[must_use] - pub fn sod(&mut self) -> SOD_W { - SOD_W::new(self) + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_dmacr.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_dmacr.rs index c20ae0f..d7fd182 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_dmacr.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_dmacr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub type RXDMAE_R = crate::BitReader; #[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] -pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub type TXDMAE_R = crate::BitReader; #[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] -pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W { - RXDMAE_W::new(self) + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self, 0) } #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W { - TXDMAE_W::new(self) + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_dr.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_dr.rs index 019ee7c..ad69481 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_dr.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_dr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub type DATA_R = crate::FieldReader; #[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] -pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W { - DATA_W::new(self) + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_icr.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_icr.rs index 9828eba..78a767d 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_icr.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_icr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] pub type RORIC_R = crate::BitReader; #[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] -pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] pub type RTIC_R = crate::BitReader; #[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] -pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIC_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] #[must_use] - pub fn roric(&mut self) -> RORIC_W { - RORIC_W::new(self) + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self, 0) } #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W { - RTIC_W::new(self) + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_imsc.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_imsc.rs index c628750..63738cd 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_imsc.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_imsc.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] pub type RORIM_R = crate::BitReader; #[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] -pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] pub type RTIM_R = crate::BitReader; #[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] -pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] pub type RXIM_R = crate::BitReader; #[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] -pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] pub type TXIM_R = crate::BitReader; #[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] -pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rorim(&mut self) -> RORIM_W { - RORIM_W::new(self) + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self, 0) } #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W { - RTIM_W::new(self) + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self, 1) } #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W { - RXIM_W::new(self) + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self, 2) } #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W { - TXIM_W::new(self) + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_mis.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_mis.rs index 358b1d4..1c50710 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_mis.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_mis.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id0.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id0.rs index 7210289..9b50e59 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id0.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id1.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id1.rs index 0953ee0..2e23cc7 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id1.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id2.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id2.rs index 5f0696d..1b5fb34 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id2.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id2.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id3.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id3.rs index c532f5c..6642d55 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id3.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_pcell_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_periph_id0.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_periph_id0.rs index 98a341a..c69007a 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_periph_id0.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_periph_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_periph_id1.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_periph_id1.rs index 0c53a92..71907fb 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_periph_id1.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_periph_id1.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_periph_id2.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_periph_id2.rs index 1b49543..2efc3ae 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_periph_id2.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_periph_id2.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_periph_id3.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_periph_id3.rs index 8f18a77..c2f7b1c 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_periph_id3.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_periph_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_ris.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_ris.rs index 46ca4be..27dee48 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_ris.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_ris.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi0/ssp_sr.rs b/jh7110-vf2-12a-pac/src/spi0/ssp_sr.rs index b25ffb6..bf388f5 100644 --- a/jh7110-vf2-12a-pac/src/spi0/ssp_sr.rs +++ b/jh7110-vf2-12a-pac/src/spi0/ssp_sr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1.rs b/jh7110-vf2-12a-pac/src/spi1.rs index e1d7fdc..6e69208 100644 --- a/jh7110-vf2-12a-pac/src/spi1.rs +++ b/jh7110-vf2-12a-pac/src/spi1.rs @@ -1,146 +1,220 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] - pub ssp_cr0: SSP_CR0, + ssp_cr0: SSP_CR0, _reserved1: [u8; 0x02], - #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] - pub ssp_cr1: SSP_CR1, + ssp_cr1: SSP_CR1, _reserved2: [u8; 0x02], - #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] - pub ssp_dr: SSP_DR, + ssp_dr: SSP_DR, _reserved3: [u8; 0x02], - #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] - pub ssp_sr: SSP_SR, + ssp_sr: SSP_SR, _reserved4: [u8; 0x02], - #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] - pub ssp_cpsr: SSP_CPSR, + ssp_cpsr: SSP_CPSR, _reserved5: [u8; 0x02], - #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] - pub ssp_imsc: SSP_IMSC, + ssp_imsc: SSP_IMSC, _reserved6: [u8; 0x02], - #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] - pub ssp_ris: SSP_RIS, + ssp_ris: SSP_RIS, _reserved7: [u8; 0x02], - #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] - pub ssp_mis: SSP_MIS, + ssp_mis: SSP_MIS, _reserved8: [u8; 0x02], - #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] - pub ssp_icr: SSP_ICR, + ssp_icr: SSP_ICR, _reserved9: [u8; 0x02], - #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] - pub ssp_dmacr: SSP_DMACR, + ssp_dmacr: SSP_DMACR, _reserved10: [u8; 0x0fba], - #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id0: SSP_PERIPH_ID0, + ssp_periph_id0: SSP_PERIPH_ID0, _reserved11: [u8; 0x02], - #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id1: SSP_PERIPH_ID1, + ssp_periph_id1: SSP_PERIPH_ID1, _reserved12: [u8; 0x02], - #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id2: SSP_PERIPH_ID2, + ssp_periph_id2: SSP_PERIPH_ID2, _reserved13: [u8; 0x02], - #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id3: SSP_PERIPH_ID3, + ssp_periph_id3: SSP_PERIPH_ID3, _reserved14: [u8; 0x02], - #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id0: SSP_PCELL_ID0, + ssp_pcell_id0: SSP_PCELL_ID0, _reserved15: [u8; 0x02], - #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id1: SSP_PCELL_ID1, + ssp_pcell_id1: SSP_PCELL_ID1, _reserved16: [u8; 0x02], - #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id2: SSP_PCELL_ID2, + ssp_pcell_id2: SSP_PCELL_ID2, _reserved17: [u8; 0x02], + ssp_pcell_id3: SSP_PCELL_ID3, +} +impl RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr0(&self) -> &SSP_CR0 { + &self.ssp_cr0 + } + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr1(&self) -> &SSP_CR1 { + &self.ssp_cr1 + } + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + #[inline(always)] + pub const fn ssp_dr(&self) -> &SSP_DR { + &self.ssp_dr + } + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + #[inline(always)] + pub const fn ssp_sr(&self) -> &SSP_SR { + &self.ssp_sr + } + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + #[inline(always)] + pub const fn ssp_cpsr(&self) -> &SSP_CPSR { + &self.ssp_cpsr + } + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + #[inline(always)] + pub const fn ssp_imsc(&self) -> &SSP_IMSC { + &self.ssp_imsc + } + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + #[inline(always)] + pub const fn ssp_ris(&self) -> &SSP_RIS { + &self.ssp_ris + } + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + #[inline(always)] + pub const fn ssp_mis(&self) -> &SSP_MIS { + &self.ssp_mis + } + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + #[inline(always)] + pub const fn ssp_icr(&self) -> &SSP_ICR { + &self.ssp_icr + } + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + #[inline(always)] + pub const fn ssp_dmacr(&self) -> &SSP_DMACR { + &self.ssp_dmacr + } + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id0(&self) -> &SSP_PERIPH_ID0 { + &self.ssp_periph_id0 + } + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id1(&self) -> &SSP_PERIPH_ID1 { + &self.ssp_periph_id1 + } + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id2(&self) -> &SSP_PERIPH_ID2 { + &self.ssp_periph_id2 + } + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id3(&self) -> &SSP_PERIPH_ID3 { + &self.ssp_periph_id3 + } + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id0(&self) -> &SSP_PCELL_ID0 { + &self.ssp_pcell_id0 + } + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id1(&self) -> &SSP_PCELL_ID1 { + &self.ssp_pcell_id1 + } + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id2(&self) -> &SSP_PCELL_ID2 { + &self.ssp_pcell_id2 + } #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id3: SSP_PCELL_ID3, + #[inline(always)] + pub const fn ssp_pcell_id3(&self) -> &SSP_PCELL_ID3 { + &self.ssp_pcell_id3 + } } -#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr0`] module"] pub type SSP_CR0 = crate::Reg; #[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] pub mod ssp_cr0; -#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr1`] module"] pub type SSP_CR1 = crate::Reg; #[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] pub mod ssp_cr1; -#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dr`] module"] pub type SSP_DR = crate::Reg; #[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] pub mod ssp_dr; -#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_sr`] module"] pub type SSP_SR = crate::Reg; #[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] pub mod ssp_sr; -#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cpsr`] module"] pub type SSP_CPSR = crate::Reg; #[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] pub mod ssp_cpsr; -#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_imsc`] module"] pub type SSP_IMSC = crate::Reg; #[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] pub mod ssp_imsc; -#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_ris`] module"] pub type SSP_RIS = crate::Reg; #[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] pub mod ssp_ris; -#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_mis`] module"] pub type SSP_MIS = crate::Reg; #[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] pub mod ssp_mis; -#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_icr`] module"] pub type SSP_ICR = crate::Reg; #[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] pub mod ssp_icr; -#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dmacr`] module"] pub type SSP_DMACR = crate::Reg; #[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] pub mod ssp_dmacr; -#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id0`] module"] pub type SSP_PERIPH_ID0 = crate::Reg; #[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id0; -#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id1`] module"] pub type SSP_PERIPH_ID1 = crate::Reg; #[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id1; -#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id2`] module"] pub type SSP_PERIPH_ID2 = crate::Reg; #[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id2; -#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id3`] module"] pub type SSP_PERIPH_ID3 = crate::Reg; #[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id3; -#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id0`] module"] pub type SSP_PCELL_ID0 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id0; -#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id1`] module"] pub type SSP_PCELL_ID1 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id1; -#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id2`] module"] pub type SSP_PCELL_ID2 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id2; -#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id3`] module"] pub type SSP_PCELL_ID3 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_cpsr.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_cpsr.rs index 214d9da..2fa25a9 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_cpsr.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_cpsr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] pub type CPSDVSR_R = crate::FieldReader; #[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] -pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type CPSDVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] #[must_use] - pub fn cpsdvsr(&mut self) -> CPSDVSR_W { - CPSDVSR_W::new(self) + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_cr0.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_cr0.rs index 1f3740e..b3ee9c6 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_cr0.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_cr0.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `dss` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] pub type DSS_R = crate::FieldReader; #[doc = "Field `dss` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] -pub type DSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type DSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] pub type FRF_R = crate::FieldReader; #[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] -pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] pub type SPO_R = crate::BitReader; #[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] -pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPO_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] pub type SPH_R = crate::BitReader; #[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] -pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPH_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] @@ -56,35 +56,39 @@ impl W { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] #[must_use] - pub fn dss(&mut self) -> DSS_W { - DSS_W::new(self) + pub fn dss(&mut self) -> DSS_W { + DSS_W::new(self, 0) } #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] #[inline(always)] #[must_use] - pub fn frf(&mut self) -> FRF_W { - FRF_W::new(self) + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self, 4) } #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn spo(&mut self) -> SPO_W { - SPO_W::new(self) + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self, 6) } #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn sph(&mut self) -> SPH_W { - SPH_W::new(self) + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self, 6) } #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_cr1.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_cr1.rs index 69dbcbd..b115461 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_cr1.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_cr1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] pub type LBM_R = crate::BitReader; #[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] -pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LBM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] pub type SSE_R = crate::BitReader; #[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] -pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SSE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] pub type MS_R = crate::BitReader; #[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] -pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] pub type SOD_R = crate::BitReader; #[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] -pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SOD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] #[must_use] - pub fn lbm(&mut self) -> LBM_W { - LBM_W::new(self) + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self, 0) } #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] #[inline(always)] #[must_use] - pub fn sse(&mut self) -> SSE_W { - SSE_W::new(self) + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self, 1) } #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] #[inline(always)] #[must_use] - pub fn ms(&mut self) -> MS_W { - MS_W::new(self) + pub fn ms(&mut self) -> MS_W { + MS_W::new(self, 2) } #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] #[inline(always)] #[must_use] - pub fn sod(&mut self) -> SOD_W { - SOD_W::new(self) + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_dmacr.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_dmacr.rs index c20ae0f..d7fd182 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_dmacr.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_dmacr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub type RXDMAE_R = crate::BitReader; #[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] -pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub type TXDMAE_R = crate::BitReader; #[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] -pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W { - RXDMAE_W::new(self) + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self, 0) } #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W { - TXDMAE_W::new(self) + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_dr.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_dr.rs index 019ee7c..ad69481 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_dr.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_dr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub type DATA_R = crate::FieldReader; #[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] -pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W { - DATA_W::new(self) + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_icr.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_icr.rs index 9828eba..78a767d 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_icr.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_icr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] pub type RORIC_R = crate::BitReader; #[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] -pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] pub type RTIC_R = crate::BitReader; #[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] -pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIC_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] #[must_use] - pub fn roric(&mut self) -> RORIC_W { - RORIC_W::new(self) + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self, 0) } #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W { - RTIC_W::new(self) + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_imsc.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_imsc.rs index c628750..63738cd 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_imsc.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_imsc.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] pub type RORIM_R = crate::BitReader; #[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] -pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] pub type RTIM_R = crate::BitReader; #[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] -pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] pub type RXIM_R = crate::BitReader; #[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] -pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] pub type TXIM_R = crate::BitReader; #[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] -pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rorim(&mut self) -> RORIM_W { - RORIM_W::new(self) + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self, 0) } #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W { - RTIM_W::new(self) + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self, 1) } #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W { - RXIM_W::new(self) + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self, 2) } #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W { - TXIM_W::new(self) + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_mis.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_mis.rs index 358b1d4..1c50710 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_mis.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_mis.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id0.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id0.rs index 7210289..9b50e59 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id0.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id1.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id1.rs index 0953ee0..2e23cc7 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id1.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id2.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id2.rs index 5f0696d..1b5fb34 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id2.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id2.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id3.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id3.rs index c532f5c..6642d55 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id3.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_pcell_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_periph_id0.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_periph_id0.rs index 98a341a..c69007a 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_periph_id0.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_periph_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_periph_id1.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_periph_id1.rs index 0c53a92..71907fb 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_periph_id1.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_periph_id1.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_periph_id2.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_periph_id2.rs index 1b49543..2efc3ae 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_periph_id2.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_periph_id2.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_periph_id3.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_periph_id3.rs index 8f18a77..c2f7b1c 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_periph_id3.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_periph_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_ris.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_ris.rs index 46ca4be..27dee48 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_ris.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_ris.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi1/ssp_sr.rs b/jh7110-vf2-12a-pac/src/spi1/ssp_sr.rs index b25ffb6..bf388f5 100644 --- a/jh7110-vf2-12a-pac/src/spi1/ssp_sr.rs +++ b/jh7110-vf2-12a-pac/src/spi1/ssp_sr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2.rs b/jh7110-vf2-12a-pac/src/spi2.rs index e1d7fdc..6e69208 100644 --- a/jh7110-vf2-12a-pac/src/spi2.rs +++ b/jh7110-vf2-12a-pac/src/spi2.rs @@ -1,146 +1,220 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] - pub ssp_cr0: SSP_CR0, + ssp_cr0: SSP_CR0, _reserved1: [u8; 0x02], - #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] - pub ssp_cr1: SSP_CR1, + ssp_cr1: SSP_CR1, _reserved2: [u8; 0x02], - #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] - pub ssp_dr: SSP_DR, + ssp_dr: SSP_DR, _reserved3: [u8; 0x02], - #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] - pub ssp_sr: SSP_SR, + ssp_sr: SSP_SR, _reserved4: [u8; 0x02], - #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] - pub ssp_cpsr: SSP_CPSR, + ssp_cpsr: SSP_CPSR, _reserved5: [u8; 0x02], - #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] - pub ssp_imsc: SSP_IMSC, + ssp_imsc: SSP_IMSC, _reserved6: [u8; 0x02], - #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] - pub ssp_ris: SSP_RIS, + ssp_ris: SSP_RIS, _reserved7: [u8; 0x02], - #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] - pub ssp_mis: SSP_MIS, + ssp_mis: SSP_MIS, _reserved8: [u8; 0x02], - #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] - pub ssp_icr: SSP_ICR, + ssp_icr: SSP_ICR, _reserved9: [u8; 0x02], - #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] - pub ssp_dmacr: SSP_DMACR, + ssp_dmacr: SSP_DMACR, _reserved10: [u8; 0x0fba], - #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id0: SSP_PERIPH_ID0, + ssp_periph_id0: SSP_PERIPH_ID0, _reserved11: [u8; 0x02], - #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id1: SSP_PERIPH_ID1, + ssp_periph_id1: SSP_PERIPH_ID1, _reserved12: [u8; 0x02], - #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id2: SSP_PERIPH_ID2, + ssp_periph_id2: SSP_PERIPH_ID2, _reserved13: [u8; 0x02], - #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id3: SSP_PERIPH_ID3, + ssp_periph_id3: SSP_PERIPH_ID3, _reserved14: [u8; 0x02], - #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id0: SSP_PCELL_ID0, + ssp_pcell_id0: SSP_PCELL_ID0, _reserved15: [u8; 0x02], - #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id1: SSP_PCELL_ID1, + ssp_pcell_id1: SSP_PCELL_ID1, _reserved16: [u8; 0x02], - #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id2: SSP_PCELL_ID2, + ssp_pcell_id2: SSP_PCELL_ID2, _reserved17: [u8; 0x02], + ssp_pcell_id3: SSP_PCELL_ID3, +} +impl RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr0(&self) -> &SSP_CR0 { + &self.ssp_cr0 + } + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr1(&self) -> &SSP_CR1 { + &self.ssp_cr1 + } + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + #[inline(always)] + pub const fn ssp_dr(&self) -> &SSP_DR { + &self.ssp_dr + } + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + #[inline(always)] + pub const fn ssp_sr(&self) -> &SSP_SR { + &self.ssp_sr + } + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + #[inline(always)] + pub const fn ssp_cpsr(&self) -> &SSP_CPSR { + &self.ssp_cpsr + } + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + #[inline(always)] + pub const fn ssp_imsc(&self) -> &SSP_IMSC { + &self.ssp_imsc + } + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + #[inline(always)] + pub const fn ssp_ris(&self) -> &SSP_RIS { + &self.ssp_ris + } + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + #[inline(always)] + pub const fn ssp_mis(&self) -> &SSP_MIS { + &self.ssp_mis + } + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + #[inline(always)] + pub const fn ssp_icr(&self) -> &SSP_ICR { + &self.ssp_icr + } + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + #[inline(always)] + pub const fn ssp_dmacr(&self) -> &SSP_DMACR { + &self.ssp_dmacr + } + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id0(&self) -> &SSP_PERIPH_ID0 { + &self.ssp_periph_id0 + } + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id1(&self) -> &SSP_PERIPH_ID1 { + &self.ssp_periph_id1 + } + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id2(&self) -> &SSP_PERIPH_ID2 { + &self.ssp_periph_id2 + } + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id3(&self) -> &SSP_PERIPH_ID3 { + &self.ssp_periph_id3 + } + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id0(&self) -> &SSP_PCELL_ID0 { + &self.ssp_pcell_id0 + } + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id1(&self) -> &SSP_PCELL_ID1 { + &self.ssp_pcell_id1 + } + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id2(&self) -> &SSP_PCELL_ID2 { + &self.ssp_pcell_id2 + } #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id3: SSP_PCELL_ID3, + #[inline(always)] + pub const fn ssp_pcell_id3(&self) -> &SSP_PCELL_ID3 { + &self.ssp_pcell_id3 + } } -#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr0`] module"] pub type SSP_CR0 = crate::Reg; #[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] pub mod ssp_cr0; -#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr1`] module"] pub type SSP_CR1 = crate::Reg; #[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] pub mod ssp_cr1; -#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dr`] module"] pub type SSP_DR = crate::Reg; #[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] pub mod ssp_dr; -#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_sr`] module"] pub type SSP_SR = crate::Reg; #[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] pub mod ssp_sr; -#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cpsr`] module"] pub type SSP_CPSR = crate::Reg; #[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] pub mod ssp_cpsr; -#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_imsc`] module"] pub type SSP_IMSC = crate::Reg; #[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] pub mod ssp_imsc; -#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_ris`] module"] pub type SSP_RIS = crate::Reg; #[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] pub mod ssp_ris; -#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_mis`] module"] pub type SSP_MIS = crate::Reg; #[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] pub mod ssp_mis; -#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_icr`] module"] pub type SSP_ICR = crate::Reg; #[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] pub mod ssp_icr; -#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dmacr`] module"] pub type SSP_DMACR = crate::Reg; #[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] pub mod ssp_dmacr; -#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id0`] module"] pub type SSP_PERIPH_ID0 = crate::Reg; #[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id0; -#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id1`] module"] pub type SSP_PERIPH_ID1 = crate::Reg; #[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id1; -#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id2`] module"] pub type SSP_PERIPH_ID2 = crate::Reg; #[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id2; -#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id3`] module"] pub type SSP_PERIPH_ID3 = crate::Reg; #[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id3; -#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id0`] module"] pub type SSP_PCELL_ID0 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id0; -#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id1`] module"] pub type SSP_PCELL_ID1 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id1; -#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id2`] module"] pub type SSP_PCELL_ID2 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id2; -#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id3`] module"] pub type SSP_PCELL_ID3 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_cpsr.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_cpsr.rs index 214d9da..2fa25a9 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_cpsr.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_cpsr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] pub type CPSDVSR_R = crate::FieldReader; #[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] -pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type CPSDVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] #[must_use] - pub fn cpsdvsr(&mut self) -> CPSDVSR_W { - CPSDVSR_W::new(self) + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_cr0.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_cr0.rs index 1f3740e..b3ee9c6 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_cr0.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_cr0.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `dss` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] pub type DSS_R = crate::FieldReader; #[doc = "Field `dss` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] -pub type DSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type DSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] pub type FRF_R = crate::FieldReader; #[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] -pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] pub type SPO_R = crate::BitReader; #[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] -pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPO_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] pub type SPH_R = crate::BitReader; #[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] -pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPH_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] @@ -56,35 +56,39 @@ impl W { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] #[must_use] - pub fn dss(&mut self) -> DSS_W { - DSS_W::new(self) + pub fn dss(&mut self) -> DSS_W { + DSS_W::new(self, 0) } #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] #[inline(always)] #[must_use] - pub fn frf(&mut self) -> FRF_W { - FRF_W::new(self) + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self, 4) } #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn spo(&mut self) -> SPO_W { - SPO_W::new(self) + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self, 6) } #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn sph(&mut self) -> SPH_W { - SPH_W::new(self) + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self, 6) } #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_cr1.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_cr1.rs index 69dbcbd..b115461 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_cr1.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_cr1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] pub type LBM_R = crate::BitReader; #[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] -pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LBM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] pub type SSE_R = crate::BitReader; #[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] -pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SSE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] pub type MS_R = crate::BitReader; #[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] -pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] pub type SOD_R = crate::BitReader; #[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] -pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SOD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] #[must_use] - pub fn lbm(&mut self) -> LBM_W { - LBM_W::new(self) + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self, 0) } #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] #[inline(always)] #[must_use] - pub fn sse(&mut self) -> SSE_W { - SSE_W::new(self) + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self, 1) } #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] #[inline(always)] #[must_use] - pub fn ms(&mut self) -> MS_W { - MS_W::new(self) + pub fn ms(&mut self) -> MS_W { + MS_W::new(self, 2) } #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] #[inline(always)] #[must_use] - pub fn sod(&mut self) -> SOD_W { - SOD_W::new(self) + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_dmacr.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_dmacr.rs index c20ae0f..d7fd182 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_dmacr.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_dmacr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub type RXDMAE_R = crate::BitReader; #[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] -pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub type TXDMAE_R = crate::BitReader; #[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] -pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W { - RXDMAE_W::new(self) + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self, 0) } #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W { - TXDMAE_W::new(self) + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_dr.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_dr.rs index 019ee7c..ad69481 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_dr.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_dr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub type DATA_R = crate::FieldReader; #[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] -pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W { - DATA_W::new(self) + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_icr.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_icr.rs index 9828eba..78a767d 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_icr.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_icr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] pub type RORIC_R = crate::BitReader; #[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] -pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] pub type RTIC_R = crate::BitReader; #[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] -pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIC_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] #[must_use] - pub fn roric(&mut self) -> RORIC_W { - RORIC_W::new(self) + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self, 0) } #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W { - RTIC_W::new(self) + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_imsc.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_imsc.rs index c628750..63738cd 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_imsc.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_imsc.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] pub type RORIM_R = crate::BitReader; #[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] -pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] pub type RTIM_R = crate::BitReader; #[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] -pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] pub type RXIM_R = crate::BitReader; #[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] -pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] pub type TXIM_R = crate::BitReader; #[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] -pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rorim(&mut self) -> RORIM_W { - RORIM_W::new(self) + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self, 0) } #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W { - RTIM_W::new(self) + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self, 1) } #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W { - RXIM_W::new(self) + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self, 2) } #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W { - TXIM_W::new(self) + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_mis.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_mis.rs index 358b1d4..1c50710 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_mis.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_mis.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id0.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id0.rs index 7210289..9b50e59 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id0.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id1.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id1.rs index 0953ee0..2e23cc7 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id1.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id2.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id2.rs index 5f0696d..1b5fb34 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id2.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id2.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id3.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id3.rs index c532f5c..6642d55 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id3.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_pcell_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_periph_id0.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_periph_id0.rs index 98a341a..c69007a 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_periph_id0.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_periph_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_periph_id1.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_periph_id1.rs index 0c53a92..71907fb 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_periph_id1.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_periph_id1.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_periph_id2.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_periph_id2.rs index 1b49543..2efc3ae 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_periph_id2.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_periph_id2.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_periph_id3.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_periph_id3.rs index 8f18a77..c2f7b1c 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_periph_id3.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_periph_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_ris.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_ris.rs index 46ca4be..27dee48 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_ris.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_ris.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi2/ssp_sr.rs b/jh7110-vf2-12a-pac/src/spi2/ssp_sr.rs index b25ffb6..bf388f5 100644 --- a/jh7110-vf2-12a-pac/src/spi2/ssp_sr.rs +++ b/jh7110-vf2-12a-pac/src/spi2/ssp_sr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3.rs b/jh7110-vf2-12a-pac/src/spi3.rs index e1d7fdc..6e69208 100644 --- a/jh7110-vf2-12a-pac/src/spi3.rs +++ b/jh7110-vf2-12a-pac/src/spi3.rs @@ -1,146 +1,220 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] - pub ssp_cr0: SSP_CR0, + ssp_cr0: SSP_CR0, _reserved1: [u8; 0x02], - #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] - pub ssp_cr1: SSP_CR1, + ssp_cr1: SSP_CR1, _reserved2: [u8; 0x02], - #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] - pub ssp_dr: SSP_DR, + ssp_dr: SSP_DR, _reserved3: [u8; 0x02], - #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] - pub ssp_sr: SSP_SR, + ssp_sr: SSP_SR, _reserved4: [u8; 0x02], - #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] - pub ssp_cpsr: SSP_CPSR, + ssp_cpsr: SSP_CPSR, _reserved5: [u8; 0x02], - #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] - pub ssp_imsc: SSP_IMSC, + ssp_imsc: SSP_IMSC, _reserved6: [u8; 0x02], - #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] - pub ssp_ris: SSP_RIS, + ssp_ris: SSP_RIS, _reserved7: [u8; 0x02], - #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] - pub ssp_mis: SSP_MIS, + ssp_mis: SSP_MIS, _reserved8: [u8; 0x02], - #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] - pub ssp_icr: SSP_ICR, + ssp_icr: SSP_ICR, _reserved9: [u8; 0x02], - #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] - pub ssp_dmacr: SSP_DMACR, + ssp_dmacr: SSP_DMACR, _reserved10: [u8; 0x0fba], - #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id0: SSP_PERIPH_ID0, + ssp_periph_id0: SSP_PERIPH_ID0, _reserved11: [u8; 0x02], - #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id1: SSP_PERIPH_ID1, + ssp_periph_id1: SSP_PERIPH_ID1, _reserved12: [u8; 0x02], - #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id2: SSP_PERIPH_ID2, + ssp_periph_id2: SSP_PERIPH_ID2, _reserved13: [u8; 0x02], - #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id3: SSP_PERIPH_ID3, + ssp_periph_id3: SSP_PERIPH_ID3, _reserved14: [u8; 0x02], - #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id0: SSP_PCELL_ID0, + ssp_pcell_id0: SSP_PCELL_ID0, _reserved15: [u8; 0x02], - #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id1: SSP_PCELL_ID1, + ssp_pcell_id1: SSP_PCELL_ID1, _reserved16: [u8; 0x02], - #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id2: SSP_PCELL_ID2, + ssp_pcell_id2: SSP_PCELL_ID2, _reserved17: [u8; 0x02], + ssp_pcell_id3: SSP_PCELL_ID3, +} +impl RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr0(&self) -> &SSP_CR0 { + &self.ssp_cr0 + } + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr1(&self) -> &SSP_CR1 { + &self.ssp_cr1 + } + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + #[inline(always)] + pub const fn ssp_dr(&self) -> &SSP_DR { + &self.ssp_dr + } + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + #[inline(always)] + pub const fn ssp_sr(&self) -> &SSP_SR { + &self.ssp_sr + } + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + #[inline(always)] + pub const fn ssp_cpsr(&self) -> &SSP_CPSR { + &self.ssp_cpsr + } + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + #[inline(always)] + pub const fn ssp_imsc(&self) -> &SSP_IMSC { + &self.ssp_imsc + } + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + #[inline(always)] + pub const fn ssp_ris(&self) -> &SSP_RIS { + &self.ssp_ris + } + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + #[inline(always)] + pub const fn ssp_mis(&self) -> &SSP_MIS { + &self.ssp_mis + } + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + #[inline(always)] + pub const fn ssp_icr(&self) -> &SSP_ICR { + &self.ssp_icr + } + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + #[inline(always)] + pub const fn ssp_dmacr(&self) -> &SSP_DMACR { + &self.ssp_dmacr + } + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id0(&self) -> &SSP_PERIPH_ID0 { + &self.ssp_periph_id0 + } + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id1(&self) -> &SSP_PERIPH_ID1 { + &self.ssp_periph_id1 + } + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id2(&self) -> &SSP_PERIPH_ID2 { + &self.ssp_periph_id2 + } + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id3(&self) -> &SSP_PERIPH_ID3 { + &self.ssp_periph_id3 + } + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id0(&self) -> &SSP_PCELL_ID0 { + &self.ssp_pcell_id0 + } + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id1(&self) -> &SSP_PCELL_ID1 { + &self.ssp_pcell_id1 + } + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id2(&self) -> &SSP_PCELL_ID2 { + &self.ssp_pcell_id2 + } #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id3: SSP_PCELL_ID3, + #[inline(always)] + pub const fn ssp_pcell_id3(&self) -> &SSP_PCELL_ID3 { + &self.ssp_pcell_id3 + } } -#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr0`] module"] pub type SSP_CR0 = crate::Reg; #[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] pub mod ssp_cr0; -#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr1`] module"] pub type SSP_CR1 = crate::Reg; #[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] pub mod ssp_cr1; -#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dr`] module"] pub type SSP_DR = crate::Reg; #[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] pub mod ssp_dr; -#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_sr`] module"] pub type SSP_SR = crate::Reg; #[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] pub mod ssp_sr; -#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cpsr`] module"] pub type SSP_CPSR = crate::Reg; #[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] pub mod ssp_cpsr; -#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_imsc`] module"] pub type SSP_IMSC = crate::Reg; #[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] pub mod ssp_imsc; -#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_ris`] module"] pub type SSP_RIS = crate::Reg; #[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] pub mod ssp_ris; -#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_mis`] module"] pub type SSP_MIS = crate::Reg; #[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] pub mod ssp_mis; -#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_icr`] module"] pub type SSP_ICR = crate::Reg; #[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] pub mod ssp_icr; -#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dmacr`] module"] pub type SSP_DMACR = crate::Reg; #[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] pub mod ssp_dmacr; -#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id0`] module"] pub type SSP_PERIPH_ID0 = crate::Reg; #[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id0; -#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id1`] module"] pub type SSP_PERIPH_ID1 = crate::Reg; #[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id1; -#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id2`] module"] pub type SSP_PERIPH_ID2 = crate::Reg; #[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id2; -#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id3`] module"] pub type SSP_PERIPH_ID3 = crate::Reg; #[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id3; -#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id0`] module"] pub type SSP_PCELL_ID0 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id0; -#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id1`] module"] pub type SSP_PCELL_ID1 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id1; -#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id2`] module"] pub type SSP_PCELL_ID2 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id2; -#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id3`] module"] pub type SSP_PCELL_ID3 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_cpsr.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_cpsr.rs index 214d9da..2fa25a9 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_cpsr.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_cpsr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] pub type CPSDVSR_R = crate::FieldReader; #[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] -pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type CPSDVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] #[must_use] - pub fn cpsdvsr(&mut self) -> CPSDVSR_W { - CPSDVSR_W::new(self) + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_cr0.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_cr0.rs index 1f3740e..b3ee9c6 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_cr0.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_cr0.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `dss` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] pub type DSS_R = crate::FieldReader; #[doc = "Field `dss` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] -pub type DSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type DSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] pub type FRF_R = crate::FieldReader; #[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] -pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] pub type SPO_R = crate::BitReader; #[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] -pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPO_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] pub type SPH_R = crate::BitReader; #[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] -pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPH_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] @@ -56,35 +56,39 @@ impl W { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] #[must_use] - pub fn dss(&mut self) -> DSS_W { - DSS_W::new(self) + pub fn dss(&mut self) -> DSS_W { + DSS_W::new(self, 0) } #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] #[inline(always)] #[must_use] - pub fn frf(&mut self) -> FRF_W { - FRF_W::new(self) + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self, 4) } #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn spo(&mut self) -> SPO_W { - SPO_W::new(self) + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self, 6) } #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn sph(&mut self) -> SPH_W { - SPH_W::new(self) + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self, 6) } #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_cr1.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_cr1.rs index 69dbcbd..b115461 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_cr1.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_cr1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] pub type LBM_R = crate::BitReader; #[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] -pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LBM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] pub type SSE_R = crate::BitReader; #[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] -pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SSE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] pub type MS_R = crate::BitReader; #[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] -pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] pub type SOD_R = crate::BitReader; #[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] -pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SOD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] #[must_use] - pub fn lbm(&mut self) -> LBM_W { - LBM_W::new(self) + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self, 0) } #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] #[inline(always)] #[must_use] - pub fn sse(&mut self) -> SSE_W { - SSE_W::new(self) + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self, 1) } #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] #[inline(always)] #[must_use] - pub fn ms(&mut self) -> MS_W { - MS_W::new(self) + pub fn ms(&mut self) -> MS_W { + MS_W::new(self, 2) } #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] #[inline(always)] #[must_use] - pub fn sod(&mut self) -> SOD_W { - SOD_W::new(self) + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_dmacr.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_dmacr.rs index c20ae0f..d7fd182 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_dmacr.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_dmacr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub type RXDMAE_R = crate::BitReader; #[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] -pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub type TXDMAE_R = crate::BitReader; #[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] -pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W { - RXDMAE_W::new(self) + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self, 0) } #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W { - TXDMAE_W::new(self) + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_dr.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_dr.rs index 019ee7c..ad69481 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_dr.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_dr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub type DATA_R = crate::FieldReader; #[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] -pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W { - DATA_W::new(self) + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_icr.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_icr.rs index 9828eba..78a767d 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_icr.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_icr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] pub type RORIC_R = crate::BitReader; #[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] -pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] pub type RTIC_R = crate::BitReader; #[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] -pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIC_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] #[must_use] - pub fn roric(&mut self) -> RORIC_W { - RORIC_W::new(self) + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self, 0) } #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W { - RTIC_W::new(self) + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_imsc.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_imsc.rs index c628750..63738cd 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_imsc.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_imsc.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] pub type RORIM_R = crate::BitReader; #[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] -pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] pub type RTIM_R = crate::BitReader; #[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] -pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] pub type RXIM_R = crate::BitReader; #[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] -pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] pub type TXIM_R = crate::BitReader; #[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] -pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rorim(&mut self) -> RORIM_W { - RORIM_W::new(self) + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self, 0) } #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W { - RTIM_W::new(self) + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self, 1) } #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W { - RXIM_W::new(self) + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self, 2) } #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W { - TXIM_W::new(self) + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_mis.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_mis.rs index 358b1d4..1c50710 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_mis.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_mis.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id0.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id0.rs index 7210289..9b50e59 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id0.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id1.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id1.rs index 0953ee0..2e23cc7 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id1.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id2.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id2.rs index 5f0696d..1b5fb34 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id2.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id2.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id3.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id3.rs index c532f5c..6642d55 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id3.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_pcell_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_periph_id0.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_periph_id0.rs index 98a341a..c69007a 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_periph_id0.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_periph_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_periph_id1.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_periph_id1.rs index 0c53a92..71907fb 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_periph_id1.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_periph_id1.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_periph_id2.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_periph_id2.rs index 1b49543..2efc3ae 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_periph_id2.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_periph_id2.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_periph_id3.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_periph_id3.rs index 8f18a77..c2f7b1c 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_periph_id3.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_periph_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_ris.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_ris.rs index 46ca4be..27dee48 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_ris.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_ris.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi3/ssp_sr.rs b/jh7110-vf2-12a-pac/src/spi3/ssp_sr.rs index b25ffb6..bf388f5 100644 --- a/jh7110-vf2-12a-pac/src/spi3/ssp_sr.rs +++ b/jh7110-vf2-12a-pac/src/spi3/ssp_sr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4.rs b/jh7110-vf2-12a-pac/src/spi4.rs index e1d7fdc..6e69208 100644 --- a/jh7110-vf2-12a-pac/src/spi4.rs +++ b/jh7110-vf2-12a-pac/src/spi4.rs @@ -1,146 +1,220 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] - pub ssp_cr0: SSP_CR0, + ssp_cr0: SSP_CR0, _reserved1: [u8; 0x02], - #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] - pub ssp_cr1: SSP_CR1, + ssp_cr1: SSP_CR1, _reserved2: [u8; 0x02], - #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] - pub ssp_dr: SSP_DR, + ssp_dr: SSP_DR, _reserved3: [u8; 0x02], - #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] - pub ssp_sr: SSP_SR, + ssp_sr: SSP_SR, _reserved4: [u8; 0x02], - #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] - pub ssp_cpsr: SSP_CPSR, + ssp_cpsr: SSP_CPSR, _reserved5: [u8; 0x02], - #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] - pub ssp_imsc: SSP_IMSC, + ssp_imsc: SSP_IMSC, _reserved6: [u8; 0x02], - #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] - pub ssp_ris: SSP_RIS, + ssp_ris: SSP_RIS, _reserved7: [u8; 0x02], - #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] - pub ssp_mis: SSP_MIS, + ssp_mis: SSP_MIS, _reserved8: [u8; 0x02], - #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] - pub ssp_icr: SSP_ICR, + ssp_icr: SSP_ICR, _reserved9: [u8; 0x02], - #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] - pub ssp_dmacr: SSP_DMACR, + ssp_dmacr: SSP_DMACR, _reserved10: [u8; 0x0fba], - #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id0: SSP_PERIPH_ID0, + ssp_periph_id0: SSP_PERIPH_ID0, _reserved11: [u8; 0x02], - #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id1: SSP_PERIPH_ID1, + ssp_periph_id1: SSP_PERIPH_ID1, _reserved12: [u8; 0x02], - #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id2: SSP_PERIPH_ID2, + ssp_periph_id2: SSP_PERIPH_ID2, _reserved13: [u8; 0x02], - #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id3: SSP_PERIPH_ID3, + ssp_periph_id3: SSP_PERIPH_ID3, _reserved14: [u8; 0x02], - #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id0: SSP_PCELL_ID0, + ssp_pcell_id0: SSP_PCELL_ID0, _reserved15: [u8; 0x02], - #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id1: SSP_PCELL_ID1, + ssp_pcell_id1: SSP_PCELL_ID1, _reserved16: [u8; 0x02], - #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id2: SSP_PCELL_ID2, + ssp_pcell_id2: SSP_PCELL_ID2, _reserved17: [u8; 0x02], + ssp_pcell_id3: SSP_PCELL_ID3, +} +impl RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr0(&self) -> &SSP_CR0 { + &self.ssp_cr0 + } + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr1(&self) -> &SSP_CR1 { + &self.ssp_cr1 + } + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + #[inline(always)] + pub const fn ssp_dr(&self) -> &SSP_DR { + &self.ssp_dr + } + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + #[inline(always)] + pub const fn ssp_sr(&self) -> &SSP_SR { + &self.ssp_sr + } + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + #[inline(always)] + pub const fn ssp_cpsr(&self) -> &SSP_CPSR { + &self.ssp_cpsr + } + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + #[inline(always)] + pub const fn ssp_imsc(&self) -> &SSP_IMSC { + &self.ssp_imsc + } + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + #[inline(always)] + pub const fn ssp_ris(&self) -> &SSP_RIS { + &self.ssp_ris + } + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + #[inline(always)] + pub const fn ssp_mis(&self) -> &SSP_MIS { + &self.ssp_mis + } + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + #[inline(always)] + pub const fn ssp_icr(&self) -> &SSP_ICR { + &self.ssp_icr + } + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + #[inline(always)] + pub const fn ssp_dmacr(&self) -> &SSP_DMACR { + &self.ssp_dmacr + } + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id0(&self) -> &SSP_PERIPH_ID0 { + &self.ssp_periph_id0 + } + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id1(&self) -> &SSP_PERIPH_ID1 { + &self.ssp_periph_id1 + } + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id2(&self) -> &SSP_PERIPH_ID2 { + &self.ssp_periph_id2 + } + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id3(&self) -> &SSP_PERIPH_ID3 { + &self.ssp_periph_id3 + } + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id0(&self) -> &SSP_PCELL_ID0 { + &self.ssp_pcell_id0 + } + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id1(&self) -> &SSP_PCELL_ID1 { + &self.ssp_pcell_id1 + } + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id2(&self) -> &SSP_PCELL_ID2 { + &self.ssp_pcell_id2 + } #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id3: SSP_PCELL_ID3, + #[inline(always)] + pub const fn ssp_pcell_id3(&self) -> &SSP_PCELL_ID3 { + &self.ssp_pcell_id3 + } } -#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr0`] module"] pub type SSP_CR0 = crate::Reg; #[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] pub mod ssp_cr0; -#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr1`] module"] pub type SSP_CR1 = crate::Reg; #[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] pub mod ssp_cr1; -#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dr`] module"] pub type SSP_DR = crate::Reg; #[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] pub mod ssp_dr; -#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_sr`] module"] pub type SSP_SR = crate::Reg; #[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] pub mod ssp_sr; -#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cpsr`] module"] pub type SSP_CPSR = crate::Reg; #[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] pub mod ssp_cpsr; -#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_imsc`] module"] pub type SSP_IMSC = crate::Reg; #[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] pub mod ssp_imsc; -#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_ris`] module"] pub type SSP_RIS = crate::Reg; #[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] pub mod ssp_ris; -#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_mis`] module"] pub type SSP_MIS = crate::Reg; #[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] pub mod ssp_mis; -#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_icr`] module"] pub type SSP_ICR = crate::Reg; #[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] pub mod ssp_icr; -#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dmacr`] module"] pub type SSP_DMACR = crate::Reg; #[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] pub mod ssp_dmacr; -#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id0`] module"] pub type SSP_PERIPH_ID0 = crate::Reg; #[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id0; -#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id1`] module"] pub type SSP_PERIPH_ID1 = crate::Reg; #[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id1; -#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id2`] module"] pub type SSP_PERIPH_ID2 = crate::Reg; #[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id2; -#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id3`] module"] pub type SSP_PERIPH_ID3 = crate::Reg; #[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id3; -#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id0`] module"] pub type SSP_PCELL_ID0 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id0; -#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id1`] module"] pub type SSP_PCELL_ID1 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id1; -#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id2`] module"] pub type SSP_PCELL_ID2 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id2; -#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id3`] module"] pub type SSP_PCELL_ID3 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_cpsr.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_cpsr.rs index 214d9da..2fa25a9 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_cpsr.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_cpsr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] pub type CPSDVSR_R = crate::FieldReader; #[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] -pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type CPSDVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] #[must_use] - pub fn cpsdvsr(&mut self) -> CPSDVSR_W { - CPSDVSR_W::new(self) + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_cr0.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_cr0.rs index 1f3740e..b3ee9c6 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_cr0.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_cr0.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `dss` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] pub type DSS_R = crate::FieldReader; #[doc = "Field `dss` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] -pub type DSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type DSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] pub type FRF_R = crate::FieldReader; #[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] -pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] pub type SPO_R = crate::BitReader; #[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] -pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPO_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] pub type SPH_R = crate::BitReader; #[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] -pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPH_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] @@ -56,35 +56,39 @@ impl W { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] #[must_use] - pub fn dss(&mut self) -> DSS_W { - DSS_W::new(self) + pub fn dss(&mut self) -> DSS_W { + DSS_W::new(self, 0) } #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] #[inline(always)] #[must_use] - pub fn frf(&mut self) -> FRF_W { - FRF_W::new(self) + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self, 4) } #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn spo(&mut self) -> SPO_W { - SPO_W::new(self) + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self, 6) } #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn sph(&mut self) -> SPH_W { - SPH_W::new(self) + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self, 6) } #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_cr1.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_cr1.rs index 69dbcbd..b115461 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_cr1.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_cr1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] pub type LBM_R = crate::BitReader; #[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] -pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LBM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] pub type SSE_R = crate::BitReader; #[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] -pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SSE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] pub type MS_R = crate::BitReader; #[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] -pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] pub type SOD_R = crate::BitReader; #[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] -pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SOD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] #[must_use] - pub fn lbm(&mut self) -> LBM_W { - LBM_W::new(self) + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self, 0) } #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] #[inline(always)] #[must_use] - pub fn sse(&mut self) -> SSE_W { - SSE_W::new(self) + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self, 1) } #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] #[inline(always)] #[must_use] - pub fn ms(&mut self) -> MS_W { - MS_W::new(self) + pub fn ms(&mut self) -> MS_W { + MS_W::new(self, 2) } #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] #[inline(always)] #[must_use] - pub fn sod(&mut self) -> SOD_W { - SOD_W::new(self) + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_dmacr.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_dmacr.rs index c20ae0f..d7fd182 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_dmacr.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_dmacr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub type RXDMAE_R = crate::BitReader; #[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] -pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub type TXDMAE_R = crate::BitReader; #[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] -pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W { - RXDMAE_W::new(self) + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self, 0) } #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W { - TXDMAE_W::new(self) + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_dr.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_dr.rs index 019ee7c..ad69481 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_dr.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_dr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub type DATA_R = crate::FieldReader; #[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] -pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W { - DATA_W::new(self) + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_icr.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_icr.rs index 9828eba..78a767d 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_icr.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_icr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] pub type RORIC_R = crate::BitReader; #[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] -pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] pub type RTIC_R = crate::BitReader; #[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] -pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIC_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] #[must_use] - pub fn roric(&mut self) -> RORIC_W { - RORIC_W::new(self) + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self, 0) } #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W { - RTIC_W::new(self) + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_imsc.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_imsc.rs index c628750..63738cd 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_imsc.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_imsc.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] pub type RORIM_R = crate::BitReader; #[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] -pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] pub type RTIM_R = crate::BitReader; #[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] -pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] pub type RXIM_R = crate::BitReader; #[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] -pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] pub type TXIM_R = crate::BitReader; #[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] -pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rorim(&mut self) -> RORIM_W { - RORIM_W::new(self) + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self, 0) } #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W { - RTIM_W::new(self) + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self, 1) } #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W { - RXIM_W::new(self) + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self, 2) } #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W { - TXIM_W::new(self) + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_mis.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_mis.rs index 358b1d4..1c50710 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_mis.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_mis.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id0.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id0.rs index 7210289..9b50e59 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id0.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id1.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id1.rs index 0953ee0..2e23cc7 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id1.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id2.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id2.rs index 5f0696d..1b5fb34 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id2.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id2.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id3.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id3.rs index c532f5c..6642d55 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id3.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_pcell_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_periph_id0.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_periph_id0.rs index 98a341a..c69007a 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_periph_id0.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_periph_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_periph_id1.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_periph_id1.rs index 0c53a92..71907fb 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_periph_id1.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_periph_id1.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_periph_id2.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_periph_id2.rs index 1b49543..2efc3ae 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_periph_id2.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_periph_id2.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_periph_id3.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_periph_id3.rs index 8f18a77..c2f7b1c 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_periph_id3.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_periph_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_ris.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_ris.rs index 46ca4be..27dee48 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_ris.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_ris.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi4/ssp_sr.rs b/jh7110-vf2-12a-pac/src/spi4/ssp_sr.rs index b25ffb6..bf388f5 100644 --- a/jh7110-vf2-12a-pac/src/spi4/ssp_sr.rs +++ b/jh7110-vf2-12a-pac/src/spi4/ssp_sr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5.rs b/jh7110-vf2-12a-pac/src/spi5.rs index e1d7fdc..6e69208 100644 --- a/jh7110-vf2-12a-pac/src/spi5.rs +++ b/jh7110-vf2-12a-pac/src/spi5.rs @@ -1,146 +1,220 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] - pub ssp_cr0: SSP_CR0, + ssp_cr0: SSP_CR0, _reserved1: [u8; 0x02], - #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] - pub ssp_cr1: SSP_CR1, + ssp_cr1: SSP_CR1, _reserved2: [u8; 0x02], - #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] - pub ssp_dr: SSP_DR, + ssp_dr: SSP_DR, _reserved3: [u8; 0x02], - #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] - pub ssp_sr: SSP_SR, + ssp_sr: SSP_SR, _reserved4: [u8; 0x02], - #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] - pub ssp_cpsr: SSP_CPSR, + ssp_cpsr: SSP_CPSR, _reserved5: [u8; 0x02], - #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] - pub ssp_imsc: SSP_IMSC, + ssp_imsc: SSP_IMSC, _reserved6: [u8; 0x02], - #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] - pub ssp_ris: SSP_RIS, + ssp_ris: SSP_RIS, _reserved7: [u8; 0x02], - #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] - pub ssp_mis: SSP_MIS, + ssp_mis: SSP_MIS, _reserved8: [u8; 0x02], - #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] - pub ssp_icr: SSP_ICR, + ssp_icr: SSP_ICR, _reserved9: [u8; 0x02], - #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] - pub ssp_dmacr: SSP_DMACR, + ssp_dmacr: SSP_DMACR, _reserved10: [u8; 0x0fba], - #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id0: SSP_PERIPH_ID0, + ssp_periph_id0: SSP_PERIPH_ID0, _reserved11: [u8; 0x02], - #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id1: SSP_PERIPH_ID1, + ssp_periph_id1: SSP_PERIPH_ID1, _reserved12: [u8; 0x02], - #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id2: SSP_PERIPH_ID2, + ssp_periph_id2: SSP_PERIPH_ID2, _reserved13: [u8; 0x02], - #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id3: SSP_PERIPH_ID3, + ssp_periph_id3: SSP_PERIPH_ID3, _reserved14: [u8; 0x02], - #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id0: SSP_PCELL_ID0, + ssp_pcell_id0: SSP_PCELL_ID0, _reserved15: [u8; 0x02], - #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id1: SSP_PCELL_ID1, + ssp_pcell_id1: SSP_PCELL_ID1, _reserved16: [u8; 0x02], - #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id2: SSP_PCELL_ID2, + ssp_pcell_id2: SSP_PCELL_ID2, _reserved17: [u8; 0x02], + ssp_pcell_id3: SSP_PCELL_ID3, +} +impl RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr0(&self) -> &SSP_CR0 { + &self.ssp_cr0 + } + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr1(&self) -> &SSP_CR1 { + &self.ssp_cr1 + } + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + #[inline(always)] + pub const fn ssp_dr(&self) -> &SSP_DR { + &self.ssp_dr + } + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + #[inline(always)] + pub const fn ssp_sr(&self) -> &SSP_SR { + &self.ssp_sr + } + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + #[inline(always)] + pub const fn ssp_cpsr(&self) -> &SSP_CPSR { + &self.ssp_cpsr + } + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + #[inline(always)] + pub const fn ssp_imsc(&self) -> &SSP_IMSC { + &self.ssp_imsc + } + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + #[inline(always)] + pub const fn ssp_ris(&self) -> &SSP_RIS { + &self.ssp_ris + } + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + #[inline(always)] + pub const fn ssp_mis(&self) -> &SSP_MIS { + &self.ssp_mis + } + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + #[inline(always)] + pub const fn ssp_icr(&self) -> &SSP_ICR { + &self.ssp_icr + } + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + #[inline(always)] + pub const fn ssp_dmacr(&self) -> &SSP_DMACR { + &self.ssp_dmacr + } + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id0(&self) -> &SSP_PERIPH_ID0 { + &self.ssp_periph_id0 + } + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id1(&self) -> &SSP_PERIPH_ID1 { + &self.ssp_periph_id1 + } + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id2(&self) -> &SSP_PERIPH_ID2 { + &self.ssp_periph_id2 + } + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id3(&self) -> &SSP_PERIPH_ID3 { + &self.ssp_periph_id3 + } + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id0(&self) -> &SSP_PCELL_ID0 { + &self.ssp_pcell_id0 + } + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id1(&self) -> &SSP_PCELL_ID1 { + &self.ssp_pcell_id1 + } + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id2(&self) -> &SSP_PCELL_ID2 { + &self.ssp_pcell_id2 + } #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id3: SSP_PCELL_ID3, + #[inline(always)] + pub const fn ssp_pcell_id3(&self) -> &SSP_PCELL_ID3 { + &self.ssp_pcell_id3 + } } -#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr0`] module"] pub type SSP_CR0 = crate::Reg; #[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] pub mod ssp_cr0; -#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr1`] module"] pub type SSP_CR1 = crate::Reg; #[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] pub mod ssp_cr1; -#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dr`] module"] pub type SSP_DR = crate::Reg; #[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] pub mod ssp_dr; -#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_sr`] module"] pub type SSP_SR = crate::Reg; #[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] pub mod ssp_sr; -#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cpsr`] module"] pub type SSP_CPSR = crate::Reg; #[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] pub mod ssp_cpsr; -#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_imsc`] module"] pub type SSP_IMSC = crate::Reg; #[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] pub mod ssp_imsc; -#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_ris`] module"] pub type SSP_RIS = crate::Reg; #[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] pub mod ssp_ris; -#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_mis`] module"] pub type SSP_MIS = crate::Reg; #[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] pub mod ssp_mis; -#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_icr`] module"] pub type SSP_ICR = crate::Reg; #[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] pub mod ssp_icr; -#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dmacr`] module"] pub type SSP_DMACR = crate::Reg; #[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] pub mod ssp_dmacr; -#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id0`] module"] pub type SSP_PERIPH_ID0 = crate::Reg; #[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id0; -#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id1`] module"] pub type SSP_PERIPH_ID1 = crate::Reg; #[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id1; -#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id2`] module"] pub type SSP_PERIPH_ID2 = crate::Reg; #[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id2; -#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id3`] module"] pub type SSP_PERIPH_ID3 = crate::Reg; #[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id3; -#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id0`] module"] pub type SSP_PCELL_ID0 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id0; -#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id1`] module"] pub type SSP_PCELL_ID1 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id1; -#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id2`] module"] pub type SSP_PCELL_ID2 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id2; -#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id3`] module"] pub type SSP_PCELL_ID3 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_cpsr.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_cpsr.rs index 214d9da..2fa25a9 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_cpsr.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_cpsr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] pub type CPSDVSR_R = crate::FieldReader; #[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] -pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type CPSDVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] #[must_use] - pub fn cpsdvsr(&mut self) -> CPSDVSR_W { - CPSDVSR_W::new(self) + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_cr0.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_cr0.rs index 1f3740e..b3ee9c6 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_cr0.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_cr0.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `dss` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] pub type DSS_R = crate::FieldReader; #[doc = "Field `dss` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] -pub type DSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type DSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] pub type FRF_R = crate::FieldReader; #[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] -pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] pub type SPO_R = crate::BitReader; #[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] -pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPO_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] pub type SPH_R = crate::BitReader; #[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] -pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPH_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] @@ -56,35 +56,39 @@ impl W { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] #[must_use] - pub fn dss(&mut self) -> DSS_W { - DSS_W::new(self) + pub fn dss(&mut self) -> DSS_W { + DSS_W::new(self, 0) } #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] #[inline(always)] #[must_use] - pub fn frf(&mut self) -> FRF_W { - FRF_W::new(self) + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self, 4) } #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn spo(&mut self) -> SPO_W { - SPO_W::new(self) + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self, 6) } #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn sph(&mut self) -> SPH_W { - SPH_W::new(self) + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self, 6) } #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_cr1.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_cr1.rs index 69dbcbd..b115461 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_cr1.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_cr1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] pub type LBM_R = crate::BitReader; #[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] -pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LBM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] pub type SSE_R = crate::BitReader; #[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] -pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SSE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] pub type MS_R = crate::BitReader; #[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] -pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] pub type SOD_R = crate::BitReader; #[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] -pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SOD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] #[must_use] - pub fn lbm(&mut self) -> LBM_W { - LBM_W::new(self) + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self, 0) } #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] #[inline(always)] #[must_use] - pub fn sse(&mut self) -> SSE_W { - SSE_W::new(self) + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self, 1) } #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] #[inline(always)] #[must_use] - pub fn ms(&mut self) -> MS_W { - MS_W::new(self) + pub fn ms(&mut self) -> MS_W { + MS_W::new(self, 2) } #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] #[inline(always)] #[must_use] - pub fn sod(&mut self) -> SOD_W { - SOD_W::new(self) + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_dmacr.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_dmacr.rs index c20ae0f..d7fd182 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_dmacr.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_dmacr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub type RXDMAE_R = crate::BitReader; #[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] -pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub type TXDMAE_R = crate::BitReader; #[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] -pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W { - RXDMAE_W::new(self) + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self, 0) } #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W { - TXDMAE_W::new(self) + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_dr.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_dr.rs index 019ee7c..ad69481 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_dr.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_dr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub type DATA_R = crate::FieldReader; #[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] -pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W { - DATA_W::new(self) + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_icr.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_icr.rs index 9828eba..78a767d 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_icr.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_icr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] pub type RORIC_R = crate::BitReader; #[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] -pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] pub type RTIC_R = crate::BitReader; #[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] -pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIC_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] #[must_use] - pub fn roric(&mut self) -> RORIC_W { - RORIC_W::new(self) + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self, 0) } #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W { - RTIC_W::new(self) + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_imsc.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_imsc.rs index c628750..63738cd 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_imsc.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_imsc.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] pub type RORIM_R = crate::BitReader; #[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] -pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] pub type RTIM_R = crate::BitReader; #[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] -pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] pub type RXIM_R = crate::BitReader; #[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] -pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] pub type TXIM_R = crate::BitReader; #[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] -pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rorim(&mut self) -> RORIM_W { - RORIM_W::new(self) + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self, 0) } #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W { - RTIM_W::new(self) + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self, 1) } #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W { - RXIM_W::new(self) + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self, 2) } #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W { - TXIM_W::new(self) + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_mis.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_mis.rs index 358b1d4..1c50710 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_mis.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_mis.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id0.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id0.rs index 7210289..9b50e59 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id0.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id1.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id1.rs index 0953ee0..2e23cc7 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id1.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id2.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id2.rs index 5f0696d..1b5fb34 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id2.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id2.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id3.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id3.rs index c532f5c..6642d55 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id3.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_pcell_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_periph_id0.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_periph_id0.rs index 98a341a..c69007a 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_periph_id0.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_periph_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_periph_id1.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_periph_id1.rs index 0c53a92..71907fb 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_periph_id1.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_periph_id1.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_periph_id2.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_periph_id2.rs index 1b49543..2efc3ae 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_periph_id2.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_periph_id2.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_periph_id3.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_periph_id3.rs index 8f18a77..c2f7b1c 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_periph_id3.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_periph_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_ris.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_ris.rs index 46ca4be..27dee48 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_ris.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_ris.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi5/ssp_sr.rs b/jh7110-vf2-12a-pac/src/spi5/ssp_sr.rs index b25ffb6..bf388f5 100644 --- a/jh7110-vf2-12a-pac/src/spi5/ssp_sr.rs +++ b/jh7110-vf2-12a-pac/src/spi5/ssp_sr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6.rs b/jh7110-vf2-12a-pac/src/spi6.rs index e1d7fdc..6e69208 100644 --- a/jh7110-vf2-12a-pac/src/spi6.rs +++ b/jh7110-vf2-12a-pac/src/spi6.rs @@ -1,146 +1,220 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] - pub ssp_cr0: SSP_CR0, + ssp_cr0: SSP_CR0, _reserved1: [u8; 0x02], - #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] - pub ssp_cr1: SSP_CR1, + ssp_cr1: SSP_CR1, _reserved2: [u8; 0x02], - #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] - pub ssp_dr: SSP_DR, + ssp_dr: SSP_DR, _reserved3: [u8; 0x02], - #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] - pub ssp_sr: SSP_SR, + ssp_sr: SSP_SR, _reserved4: [u8; 0x02], - #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] - pub ssp_cpsr: SSP_CPSR, + ssp_cpsr: SSP_CPSR, _reserved5: [u8; 0x02], - #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] - pub ssp_imsc: SSP_IMSC, + ssp_imsc: SSP_IMSC, _reserved6: [u8; 0x02], - #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] - pub ssp_ris: SSP_RIS, + ssp_ris: SSP_RIS, _reserved7: [u8; 0x02], - #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] - pub ssp_mis: SSP_MIS, + ssp_mis: SSP_MIS, _reserved8: [u8; 0x02], - #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] - pub ssp_icr: SSP_ICR, + ssp_icr: SSP_ICR, _reserved9: [u8; 0x02], - #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] - pub ssp_dmacr: SSP_DMACR, + ssp_dmacr: SSP_DMACR, _reserved10: [u8; 0x0fba], - #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id0: SSP_PERIPH_ID0, + ssp_periph_id0: SSP_PERIPH_ID0, _reserved11: [u8; 0x02], - #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id1: SSP_PERIPH_ID1, + ssp_periph_id1: SSP_PERIPH_ID1, _reserved12: [u8; 0x02], - #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id2: SSP_PERIPH_ID2, + ssp_periph_id2: SSP_PERIPH_ID2, _reserved13: [u8; 0x02], - #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id3: SSP_PERIPH_ID3, + ssp_periph_id3: SSP_PERIPH_ID3, _reserved14: [u8; 0x02], - #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id0: SSP_PCELL_ID0, + ssp_pcell_id0: SSP_PCELL_ID0, _reserved15: [u8; 0x02], - #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id1: SSP_PCELL_ID1, + ssp_pcell_id1: SSP_PCELL_ID1, _reserved16: [u8; 0x02], - #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id2: SSP_PCELL_ID2, + ssp_pcell_id2: SSP_PCELL_ID2, _reserved17: [u8; 0x02], + ssp_pcell_id3: SSP_PCELL_ID3, +} +impl RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr0(&self) -> &SSP_CR0 { + &self.ssp_cr0 + } + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr1(&self) -> &SSP_CR1 { + &self.ssp_cr1 + } + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + #[inline(always)] + pub const fn ssp_dr(&self) -> &SSP_DR { + &self.ssp_dr + } + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + #[inline(always)] + pub const fn ssp_sr(&self) -> &SSP_SR { + &self.ssp_sr + } + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + #[inline(always)] + pub const fn ssp_cpsr(&self) -> &SSP_CPSR { + &self.ssp_cpsr + } + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + #[inline(always)] + pub const fn ssp_imsc(&self) -> &SSP_IMSC { + &self.ssp_imsc + } + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + #[inline(always)] + pub const fn ssp_ris(&self) -> &SSP_RIS { + &self.ssp_ris + } + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + #[inline(always)] + pub const fn ssp_mis(&self) -> &SSP_MIS { + &self.ssp_mis + } + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + #[inline(always)] + pub const fn ssp_icr(&self) -> &SSP_ICR { + &self.ssp_icr + } + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + #[inline(always)] + pub const fn ssp_dmacr(&self) -> &SSP_DMACR { + &self.ssp_dmacr + } + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id0(&self) -> &SSP_PERIPH_ID0 { + &self.ssp_periph_id0 + } + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id1(&self) -> &SSP_PERIPH_ID1 { + &self.ssp_periph_id1 + } + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id2(&self) -> &SSP_PERIPH_ID2 { + &self.ssp_periph_id2 + } + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id3(&self) -> &SSP_PERIPH_ID3 { + &self.ssp_periph_id3 + } + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id0(&self) -> &SSP_PCELL_ID0 { + &self.ssp_pcell_id0 + } + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id1(&self) -> &SSP_PCELL_ID1 { + &self.ssp_pcell_id1 + } + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id2(&self) -> &SSP_PCELL_ID2 { + &self.ssp_pcell_id2 + } #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id3: SSP_PCELL_ID3, + #[inline(always)] + pub const fn ssp_pcell_id3(&self) -> &SSP_PCELL_ID3 { + &self.ssp_pcell_id3 + } } -#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr0`] module"] pub type SSP_CR0 = crate::Reg; #[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] pub mod ssp_cr0; -#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr1`] module"] pub type SSP_CR1 = crate::Reg; #[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] pub mod ssp_cr1; -#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dr`] module"] pub type SSP_DR = crate::Reg; #[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] pub mod ssp_dr; -#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_sr`] module"] pub type SSP_SR = crate::Reg; #[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] pub mod ssp_sr; -#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cpsr`] module"] pub type SSP_CPSR = crate::Reg; #[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] pub mod ssp_cpsr; -#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_imsc`] module"] pub type SSP_IMSC = crate::Reg; #[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] pub mod ssp_imsc; -#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_ris`] module"] pub type SSP_RIS = crate::Reg; #[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] pub mod ssp_ris; -#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_mis`] module"] pub type SSP_MIS = crate::Reg; #[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] pub mod ssp_mis; -#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_icr`] module"] pub type SSP_ICR = crate::Reg; #[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] pub mod ssp_icr; -#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dmacr`] module"] pub type SSP_DMACR = crate::Reg; #[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] pub mod ssp_dmacr; -#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id0`] module"] pub type SSP_PERIPH_ID0 = crate::Reg; #[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id0; -#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id1`] module"] pub type SSP_PERIPH_ID1 = crate::Reg; #[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id1; -#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id2`] module"] pub type SSP_PERIPH_ID2 = crate::Reg; #[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id2; -#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id3`] module"] pub type SSP_PERIPH_ID3 = crate::Reg; #[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id3; -#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id0`] module"] pub type SSP_PCELL_ID0 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id0; -#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id1`] module"] pub type SSP_PCELL_ID1 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id1; -#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id2`] module"] pub type SSP_PCELL_ID2 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id2; -#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id3`] module"] pub type SSP_PCELL_ID3 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_cpsr.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_cpsr.rs index 214d9da..2fa25a9 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_cpsr.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_cpsr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] pub type CPSDVSR_R = crate::FieldReader; #[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] -pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type CPSDVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] #[must_use] - pub fn cpsdvsr(&mut self) -> CPSDVSR_W { - CPSDVSR_W::new(self) + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_cr0.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_cr0.rs index 1f3740e..b3ee9c6 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_cr0.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_cr0.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `dss` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] pub type DSS_R = crate::FieldReader; #[doc = "Field `dss` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] -pub type DSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type DSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] pub type FRF_R = crate::FieldReader; #[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] -pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] pub type SPO_R = crate::BitReader; #[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] -pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPO_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] pub type SPH_R = crate::BitReader; #[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] -pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPH_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] @@ -56,35 +56,39 @@ impl W { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] #[must_use] - pub fn dss(&mut self) -> DSS_W { - DSS_W::new(self) + pub fn dss(&mut self) -> DSS_W { + DSS_W::new(self, 0) } #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] #[inline(always)] #[must_use] - pub fn frf(&mut self) -> FRF_W { - FRF_W::new(self) + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self, 4) } #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn spo(&mut self) -> SPO_W { - SPO_W::new(self) + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self, 6) } #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn sph(&mut self) -> SPH_W { - SPH_W::new(self) + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self, 6) } #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_cr1.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_cr1.rs index 69dbcbd..b115461 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_cr1.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_cr1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] pub type LBM_R = crate::BitReader; #[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] -pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LBM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] pub type SSE_R = crate::BitReader; #[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] -pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SSE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] pub type MS_R = crate::BitReader; #[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] -pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] pub type SOD_R = crate::BitReader; #[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] -pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SOD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] #[must_use] - pub fn lbm(&mut self) -> LBM_W { - LBM_W::new(self) + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self, 0) } #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] #[inline(always)] #[must_use] - pub fn sse(&mut self) -> SSE_W { - SSE_W::new(self) + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self, 1) } #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] #[inline(always)] #[must_use] - pub fn ms(&mut self) -> MS_W { - MS_W::new(self) + pub fn ms(&mut self) -> MS_W { + MS_W::new(self, 2) } #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] #[inline(always)] #[must_use] - pub fn sod(&mut self) -> SOD_W { - SOD_W::new(self) + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_dmacr.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_dmacr.rs index c20ae0f..d7fd182 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_dmacr.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_dmacr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub type RXDMAE_R = crate::BitReader; #[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] -pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub type TXDMAE_R = crate::BitReader; #[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] -pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W { - RXDMAE_W::new(self) + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self, 0) } #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W { - TXDMAE_W::new(self) + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_dr.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_dr.rs index 019ee7c..ad69481 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_dr.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_dr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub type DATA_R = crate::FieldReader; #[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] -pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W { - DATA_W::new(self) + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_icr.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_icr.rs index 9828eba..78a767d 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_icr.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_icr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] pub type RORIC_R = crate::BitReader; #[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] -pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] pub type RTIC_R = crate::BitReader; #[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] -pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIC_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] #[must_use] - pub fn roric(&mut self) -> RORIC_W { - RORIC_W::new(self) + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self, 0) } #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W { - RTIC_W::new(self) + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_imsc.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_imsc.rs index c628750..63738cd 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_imsc.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_imsc.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] pub type RORIM_R = crate::BitReader; #[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] -pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] pub type RTIM_R = crate::BitReader; #[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] -pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] pub type RXIM_R = crate::BitReader; #[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] -pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] pub type TXIM_R = crate::BitReader; #[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] -pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rorim(&mut self) -> RORIM_W { - RORIM_W::new(self) + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self, 0) } #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W { - RTIM_W::new(self) + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self, 1) } #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W { - RXIM_W::new(self) + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self, 2) } #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W { - TXIM_W::new(self) + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_mis.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_mis.rs index 358b1d4..1c50710 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_mis.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_mis.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id0.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id0.rs index 7210289..9b50e59 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id0.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id1.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id1.rs index 0953ee0..2e23cc7 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id1.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id2.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id2.rs index 5f0696d..1b5fb34 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id2.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id2.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id3.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id3.rs index c532f5c..6642d55 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id3.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_pcell_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_periph_id0.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_periph_id0.rs index 98a341a..c69007a 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_periph_id0.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_periph_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_periph_id1.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_periph_id1.rs index 0c53a92..71907fb 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_periph_id1.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_periph_id1.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_periph_id2.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_periph_id2.rs index 1b49543..2efc3ae 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_periph_id2.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_periph_id2.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_periph_id3.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_periph_id3.rs index 8f18a77..c2f7b1c 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_periph_id3.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_periph_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_ris.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_ris.rs index 46ca4be..27dee48 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_ris.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_ris.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/spi6/ssp_sr.rs b/jh7110-vf2-12a-pac/src/spi6/ssp_sr.rs index b25ffb6..bf388f5 100644 --- a/jh7110-vf2-12a-pac/src/spi6/ssp_sr.rs +++ b/jh7110-vf2-12a-pac/src/spi6/ssp_sr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon.rs b/jh7110-vf2-12a-pac/src/stg_syscon.rs index 6172b24..477eedb 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon.rs @@ -1,1864 +1,2798 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + stg_sysconsaif_syscfg0: STG_SYSCONSAIF_SYSCFG0, + stg_sysconsaif_syscfg4: STG_SYSCONSAIF_SYSCFG4, + stg_sysconsaif_syscfg8: STG_SYSCONSAIF_SYSCFG8, + stg_sysconsaif_syscfg12: STG_SYSCONSAIF_SYSCFG12, + stg_sysconsaif_syscfg16: STG_SYSCONSAIF_SYSCFG16, + stg_sysconsaif_syscfg20: STG_SYSCONSAIF_SYSCFG20, + stg_sysconsaif_syscfg24: STG_SYSCONSAIF_SYSCFG24, + stg_sysconsaif_syscfg28: STG_SYSCONSAIF_SYSCFG28, + stg_sysconsaif_syscfg32: STG_SYSCONSAIF_SYSCFG32, + stg_sysconsaif_syscfg36: STG_SYSCONSAIF_SYSCFG36, + stg_sysconsaif_syscfg40: STG_SYSCONSAIF_SYSCFG40, + stg_sysconsaif_syscfg44: STG_SYSCONSAIF_SYSCFG44, + stg_sysconsaif_syscfg48: STG_SYSCONSAIF_SYSCFG48, + stg_sysconsaif_syscfg52: STG_SYSCONSAIF_SYSCFG52, + stg_sysconsaif_syscfg56: STG_SYSCONSAIF_SYSCFG56, + stg_sysconsaif_syscfg60: STG_SYSCONSAIF_SYSCFG60, + stg_sysconsaif_syscfg64: STG_SYSCONSAIF_SYSCFG64, + stg_sysconsaif_syscfg68: STG_SYSCONSAIF_SYSCFG68, + stg_sysconsaif_syscfg72: STG_SYSCONSAIF_SYSCFG72, + stg_sysconsaif_syscfg76: STG_SYSCONSAIF_SYSCFG76, + stg_sysconsaif_syscfg80: STG_SYSCONSAIF_SYSCFG80, + stg_sysconsaif_syscfg84: STG_SYSCONSAIF_SYSCFG84, + stg_sysconsaif_syscfg88: STG_SYSCONSAIF_SYSCFG88, + stg_sysconsaif_syscfg92: STG_SYSCONSAIF_SYSCFG92, + stg_sysconsaif_syscfg96: STG_SYSCONSAIF_SYSCFG96, + stg_sysconsaif_syscfg100: STG_SYSCONSAIF_SYSCFG100, + stg_sysconsaif_syscfg104: STG_SYSCONSAIF_SYSCFG104, + stg_sysconsaif_syscfg108: STG_SYSCONSAIF_SYSCFG108, + stg_sysconsaif_syscfg112: STG_SYSCONSAIF_SYSCFG112, + stg_sysconsaif_syscfg116: STG_SYSCONSAIF_SYSCFG116, + stg_sysconsaif_syscfg120: STG_SYSCONSAIF_SYSCFG120, + stg_sysconsaif_syscfg124: STG_SYSCONSAIF_SYSCFG124, + stg_sysconsaif_syscfg128: STG_SYSCONSAIF_SYSCFG128, + stg_sysconsaif_syscfg132: STG_SYSCONSAIF_SYSCFG132, + stg_sysconsaif_syscfg136: STG_SYSCONSAIF_SYSCFG136, + stg_sysconsaif_syscfg140: STG_SYSCONSAIF_SYSCFG140, + stg_sysconsaif_syscfg144: STG_SYSCONSAIF_SYSCFG144, + stg_sysconsaif_syscfg148: STG_SYSCONSAIF_SYSCFG148, + stg_sysconsaif_syscfg152: STG_SYSCONSAIF_SYSCFG152, + stg_sysconsaif_syscfg156: STG_SYSCONSAIF_SYSCFG156, + stg_sysconsaif_syscfg160: STG_SYSCONSAIF_SYSCFG160, + stg_sysconsaif_syscfg164: STG_SYSCONSAIF_SYSCFG164, + stg_sysconsaif_syscfg168: STG_SYSCONSAIF_SYSCFG168, + stg_sysconsaif_syscfg172: STG_SYSCONSAIF_SYSCFG172, + stg_sysconsaif_syscfg176: STG_SYSCONSAIF_SYSCFG176, + stg_sysconsaif_syscfg180: STG_SYSCONSAIF_SYSCFG180, + stg_sysconsaif_syscfg184: STG_SYSCONSAIF_SYSCFG184, + stg_sysconsaif_syscfg188: STG_SYSCONSAIF_SYSCFG188, + stg_sysconsaif_syscfg192: STG_SYSCONSAIF_SYSCFG192, + stg_sysconsaif_syscfg196: STG_SYSCONSAIF_SYSCFG196, + stg_sysconsaif_syscfg200: STG_SYSCONSAIF_SYSCFG200, + stg_sysconsaif_syscfg204: STG_SYSCONSAIF_SYSCFG204, + stg_sysconsaif_syscfg208: STG_SYSCONSAIF_SYSCFG208, + stg_sysconsaif_syscfg212: STG_SYSCONSAIF_SYSCFG212, + stg_sysconsaif_syscfg216: STG_SYSCONSAIF_SYSCFG216, + stg_sysconsaif_syscfg220: STG_SYSCONSAIF_SYSCFG220, + stg_sysconsaif_syscfg224: STG_SYSCONSAIF_SYSCFG224, + stg_sysconsaif_syscfg228: STG_SYSCONSAIF_SYSCFG228, + stg_sysconsaif_syscfg232: STG_SYSCONSAIF_SYSCFG232, + stg_sysconsaif_syscfg236: STG_SYSCONSAIF_SYSCFG236, + stg_sysconsaif_syscfg240: STG_SYSCONSAIF_SYSCFG240, + stg_sysconsaif_syscfg244: STG_SYSCONSAIF_SYSCFG244, + stg_sysconsaif_syscfg248: STG_SYSCONSAIF_SYSCFG248, + stg_sysconsaif_syscfg252: STG_SYSCONSAIF_SYSCFG252, + stg_sysconsaif_syscfg256: STG_SYSCONSAIF_SYSCFG256, + stg_sysconsaif_syscfg260: STG_SYSCONSAIF_SYSCFG260, + stg_sysconsaif_syscfg264: STG_SYSCONSAIF_SYSCFG264, + stg_sysconsaif_syscfg268: STG_SYSCONSAIF_SYSCFG268, + stg_sysconsaif_syscfg272: STG_SYSCONSAIF_SYSCFG272, + stg_sysconsaif_syscfg276: STG_SYSCONSAIF_SYSCFG276, + stg_sysconsaif_syscfg280: STG_SYSCONSAIF_SYSCFG280, + stg_sysconsaif_syscfg284: STG_SYSCONSAIF_SYSCFG284, + stg_sysconsaif_syscfg288: STG_SYSCONSAIF_SYSCFG288, + stg_sysconsaif_syscfg292: STG_SYSCONSAIF_SYSCFG292, + stg_sysconsaif_syscfg296: STG_SYSCONSAIF_SYSCFG296, + stg_sysconsaif_syscfg300: STG_SYSCONSAIF_SYSCFG300, + stg_sysconsaif_syscfg304: STG_SYSCONSAIF_SYSCFG304, + stg_sysconsaif_syscfg308: STG_SYSCONSAIF_SYSCFG308, + stg_sysconsaif_syscfg312: STG_SYSCONSAIF_SYSCFG312, + stg_sysconsaif_syscfg316: STG_SYSCONSAIF_SYSCFG316, + stg_sysconsaif_syscfg320: STG_SYSCONSAIF_SYSCFG320, + stg_sysconsaif_syscfg324: STG_SYSCONSAIF_SYSCFG324, + stg_sysconsaif_syscfg328: STG_SYSCONSAIF_SYSCFG328, + stg_sysconsaif_syscfg332: STG_SYSCONSAIF_SYSCFG332, + stg_sysconsaif_syscfg336: STG_SYSCONSAIF_SYSCFG336, + stg_sysconsaif_syscfg340: STG_SYSCONSAIF_SYSCFG340, + stg_sysconsaif_syscfg344: STG_SYSCONSAIF_SYSCFG344, + stg_sysconsaif_syscfg348: STG_SYSCONSAIF_SYSCFG348, + stg_sysconsaif_syscfg352: STG_SYSCONSAIF_SYSCFG352, + stg_sysconsaif_syscfg356: STG_SYSCONSAIF_SYSCFG356, + stg_sysconsaif_syscfg360: STG_SYSCONSAIF_SYSCFG360, + stg_sysconsaif_syscfg364: STG_SYSCONSAIF_SYSCFG364, + stg_sysconsaif_syscfg368: STG_SYSCONSAIF_SYSCFG368, + stg_sysconsaif_syscfg372: STG_SYSCONSAIF_SYSCFG372, + stg_sysconsaif_syscfg376: STG_SYSCONSAIF_SYSCFG376, + stg_sysconsaif_syscfg380: STG_SYSCONSAIF_SYSCFG380, + stg_sysconsaif_syscfg384: STG_SYSCONSAIF_SYSCFG384, + stg_sysconsaif_syscfg388: STG_SYSCONSAIF_SYSCFG388, + stg_sysconsaif_syscfg392: STG_SYSCONSAIF_SYSCFG392, + stg_sysconsaif_syscfg396: STG_SYSCONSAIF_SYSCFG396, + stg_sysconsaif_syscfg400: STG_SYSCONSAIF_SYSCFG400, + stg_sysconsaif_syscfg404: STG_SYSCONSAIF_SYSCFG404, + stg_sysconsaif_syscfg408: STG_SYSCONSAIF_SYSCFG408, + stg_sysconsaif_syscfg412: STG_SYSCONSAIF_SYSCFG412, + stg_sysconsaif_syscfg416: STG_SYSCONSAIF_SYSCFG416, + stg_sysconsaif_syscfg420: STG_SYSCONSAIF_SYSCFG420, + stg_sysconsaif_syscfg424: STG_SYSCONSAIF_SYSCFG424, + stg_sysconsaif_syscfg428: STG_SYSCONSAIF_SYSCFG428, + stg_sysconsaif_syscfg432: STG_SYSCONSAIF_SYSCFG432, + stg_sysconsaif_syscfg436: STG_SYSCONSAIF_SYSCFG436, + stg_sysconsaif_syscfg440: STG_SYSCONSAIF_SYSCFG440, + stg_sysconsaif_syscfg444: STG_SYSCONSAIF_SYSCFG444, + stg_sysconsaif_syscfg448: STG_SYSCONSAIF_SYSCFG448, + stg_sysconsaif_syscfg452: STG_SYSCONSAIF_SYSCFG452, + stg_sysconsaif_syscfg456: STG_SYSCONSAIF_SYSCFG456, + stg_sysconsaif_syscfg460: STG_SYSCONSAIF_SYSCFG460, + stg_sysconsaif_syscfg464: STG_SYSCONSAIF_SYSCFG464, + stg_sysconsaif_syscfg468: STG_SYSCONSAIF_SYSCFG468, + stg_sysconsaif_syscfg472: STG_SYSCONSAIF_SYSCFG472, + stg_sysconsaif_syscfg476: STG_SYSCONSAIF_SYSCFG476, + stg_sysconsaif_syscfg480: STG_SYSCONSAIF_SYSCFG480, + stg_sysconsaif_syscfg484: STG_SYSCONSAIF_SYSCFG484, + stg_sysconsaif_syscfg488: STG_SYSCONSAIF_SYSCFG488, + stg_sysconsaif_syscfg492: STG_SYSCONSAIF_SYSCFG492, + _reserved124: [u8; 0x04], + stg_sysconsaif_syscfg500: STG_SYSCONSAIF_SYSCFG500, + stg_sysconsaif_syscfg504: STG_SYSCONSAIF_SYSCFG504, + stg_sysconsaif_syscfg508: STG_SYSCONSAIF_SYSCFG508, + stg_sysconsaif_syscfg512: STG_SYSCONSAIF_SYSCFG512, + stg_sysconsaif_syscfg516: STG_SYSCONSAIF_SYSCFG516, + stg_sysconsaif_syscfg520: STG_SYSCONSAIF_SYSCFG520, + stg_sysconsaif_syscfg524: STG_SYSCONSAIF_SYSCFG524, + stg_sysconsaif_syscfg528: STG_SYSCONSAIF_SYSCFG528, + stg_sysconsaif_syscfg532: STG_SYSCONSAIF_SYSCFG532, + stg_sysconsaif_syscfg536: STG_SYSCONSAIF_SYSCFG536, + stg_sysconsaif_syscfg540: STG_SYSCONSAIF_SYSCFG540, + stg_sysconsaif_syscfg544: STG_SYSCONSAIF_SYSCFG544, + stg_sysconsaif_syscfg548: STG_SYSCONSAIF_SYSCFG548, + stg_sysconsaif_syscfg552: STG_SYSCONSAIF_SYSCFG552, + stg_sysconsaif_syscfg556: STG_SYSCONSAIF_SYSCFG556, + stg_sysconsaif_syscfg560: STG_SYSCONSAIF_SYSCFG560, + stg_sysconsaif_syscfg564: STG_SYSCONSAIF_SYSCFG564, + stg_sysconsaif_syscfg568: STG_SYSCONSAIF_SYSCFG568, + stg_sysconsaif_syscfg572: STG_SYSCONSAIF_SYSCFG572, + stg_sysconsaif_syscfg576: STG_SYSCONSAIF_SYSCFG576, + stg_sysconsaif_syscfg580: STG_SYSCONSAIF_SYSCFG580, + stg_sysconsaif_syscfg584: STG_SYSCONSAIF_SYSCFG584, + stg_sysconsaif_syscfg588: STG_SYSCONSAIF_SYSCFG588, + stg_sysconsaif_syscfg592: STG_SYSCONSAIF_SYSCFG592, + stg_sysconsaif_syscfg596: STG_SYSCONSAIF_SYSCFG596, + stg_sysconsaif_syscfg600: STG_SYSCONSAIF_SYSCFG600, + stg_sysconsaif_syscfg604: STG_SYSCONSAIF_SYSCFG604, + stg_sysconsaif_syscfg608: STG_SYSCONSAIF_SYSCFG608, + stg_sysconsaif_syscfg612: STG_SYSCONSAIF_SYSCFG612, + stg_sysconsaif_syscfg616: STG_SYSCONSAIF_SYSCFG616, + stg_sysconsaif_syscfg620: STG_SYSCONSAIF_SYSCFG620, + stg_sysconsaif_syscfg624: STG_SYSCONSAIF_SYSCFG624, + stg_sysconsaif_syscfg628: STG_SYSCONSAIF_SYSCFG628, + stg_sysconsaif_syscfg632: STG_SYSCONSAIF_SYSCFG632, + stg_sysconsaif_syscfg636: STG_SYSCONSAIF_SYSCFG636, + stg_sysconsaif_syscfg640: STG_SYSCONSAIF_SYSCFG640, + stg_sysconsaif_syscfg644: STG_SYSCONSAIF_SYSCFG644, + stg_sysconsaif_syscfg648: STG_SYSCONSAIF_SYSCFG648, + stg_sysconsaif_syscfg652: STG_SYSCONSAIF_SYSCFG652, + stg_sysconsaif_syscfg656: STG_SYSCONSAIF_SYSCFG656, + stg_sysconsaif_syscfg660: STG_SYSCONSAIF_SYSCFG660, + stg_sysconsaif_syscfg664: STG_SYSCONSAIF_SYSCFG664, + stg_sysconsaif_syscfg668: STG_SYSCONSAIF_SYSCFG668, + stg_sysconsaif_syscfg672: STG_SYSCONSAIF_SYSCFG672, + stg_sysconsaif_syscfg676: STG_SYSCONSAIF_SYSCFG676, + stg_sysconsaif_syscfg680: STG_SYSCONSAIF_SYSCFG680, + stg_sysconsaif_syscfg684: STG_SYSCONSAIF_SYSCFG684, + stg_sysconsaif_syscfg688: STG_SYSCONSAIF_SYSCFG688, + stg_sysconsaif_syscfg692: STG_SYSCONSAIF_SYSCFG692, + stg_sysconsaif_syscfg696: STG_SYSCONSAIF_SYSCFG696, + stg_sysconsaif_syscfg700: STG_SYSCONSAIF_SYSCFG700, + stg_sysconsaif_syscfg704: STG_SYSCONSAIF_SYSCFG704, + stg_sysconsaif_syscfg708: STG_SYSCONSAIF_SYSCFG708, + stg_sysconsaif_syscfg712: STG_SYSCONSAIF_SYSCFG712, + stg_sysconsaif_syscfg716: STG_SYSCONSAIF_SYSCFG716, + stg_sysconsaif_syscfg720: STG_SYSCONSAIF_SYSCFG720, + stg_sysconsaif_syscfg724: STG_SYSCONSAIF_SYSCFG724, + stg_sysconsaif_syscfg728: STG_SYSCONSAIF_SYSCFG728, + stg_sysconsaif_syscfg732: STG_SYSCONSAIF_SYSCFG732, + stg_sysconsaif_syscfg736: STG_SYSCONSAIF_SYSCFG736, + stg_sysconsaif_syscfg740: STG_SYSCONSAIF_SYSCFG740, + stg_sysconsaif_syscfg744: STG_SYSCONSAIF_SYSCFG744, + stg_sysconsaif_syscfg748: STG_SYSCONSAIF_SYSCFG748, + stg_sysconsaif_syscfg752: STG_SYSCONSAIF_SYSCFG752, + stg_sysconsaif_syscfg756: STG_SYSCONSAIF_SYSCFG756, + stg_sysconsaif_syscfg760: STG_SYSCONSAIF_SYSCFG760, + stg_sysconsaif_syscfg764: STG_SYSCONSAIF_SYSCFG764, + stg_sysconsaif_syscfg768: STG_SYSCONSAIF_SYSCFG768, + stg_sysconsaif_syscfg772: STG_SYSCONSAIF_SYSCFG772, + stg_sysconsaif_syscfg776: STG_SYSCONSAIF_SYSCFG776, + stg_sysconsaif_syscfg780: STG_SYSCONSAIF_SYSCFG780, + stg_sysconsaif_syscfg784: STG_SYSCONSAIF_SYSCFG784, + stg_sysconsaif_syscfg788: STG_SYSCONSAIF_SYSCFG788, + stg_sysconsaif_syscfg792: STG_SYSCONSAIF_SYSCFG792, + stg_sysconsaif_syscfg796: STG_SYSCONSAIF_SYSCFG796, + stg_sysconsaif_syscfg800: STG_SYSCONSAIF_SYSCFG800, + stg_sysconsaif_syscfg804: STG_SYSCONSAIF_SYSCFG804, + stg_sysconsaif_syscfg808: STG_SYSCONSAIF_SYSCFG808, + stg_sysconsaif_syscfg812: STG_SYSCONSAIF_SYSCFG812, + stg_sysconsaif_syscfg816: STG_SYSCONSAIF_SYSCFG816, + stg_sysconsaif_syscfg820: STG_SYSCONSAIF_SYSCFG820, + stg_sysconsaif_syscfg824: STG_SYSCONSAIF_SYSCFG824, + stg_sysconsaif_syscfg828: STG_SYSCONSAIF_SYSCFG828, + stg_sysconsaif_syscfg832: STG_SYSCONSAIF_SYSCFG832, + stg_sysconsaif_syscfg836: STG_SYSCONSAIF_SYSCFG836, + stg_sysconsaif_syscfg840: STG_SYSCONSAIF_SYSCFG840, + stg_sysconsaif_syscfg844: STG_SYSCONSAIF_SYSCFG844, + stg_sysconsaif_syscfg848: STG_SYSCONSAIF_SYSCFG848, + stg_sysconsaif_syscfg852: STG_SYSCONSAIF_SYSCFG852, + stg_sysconsaif_syscfg856: STG_SYSCONSAIF_SYSCFG856, + stg_sysconsaif_syscfg860: STG_SYSCONSAIF_SYSCFG860, + stg_sysconsaif_syscfg864: STG_SYSCONSAIF_SYSCFG864, + stg_sysconsaif_syscfg868: STG_SYSCONSAIF_SYSCFG868, + stg_sysconsaif_syscfg872: STG_SYSCONSAIF_SYSCFG872, + stg_sysconsaif_syscfg876: STG_SYSCONSAIF_SYSCFG876, + stg_sysconsaif_syscfg880: STG_SYSCONSAIF_SYSCFG880, + stg_sysconsaif_syscfg884: STG_SYSCONSAIF_SYSCFG884, + stg_sysconsaif_syscfg888: STG_SYSCONSAIF_SYSCFG888, + stg_sysconsaif_syscfg892: STG_SYSCONSAIF_SYSCFG892, + stg_sysconsaif_syscfg896: STG_SYSCONSAIF_SYSCFG896, + stg_sysconsaif_syscfg900: STG_SYSCONSAIF_SYSCFG900, + stg_sysconsaif_syscfg904: STG_SYSCONSAIF_SYSCFG904, + stg_sysconsaif_syscfg908: STG_SYSCONSAIF_SYSCFG908, + stg_sysconsaif_syscfg912: STG_SYSCONSAIF_SYSCFG912, + stg_sysconsaif_syscfg916: STG_SYSCONSAIF_SYSCFG916, + stg_sysconsaif_syscfg920: STG_SYSCONSAIF_SYSCFG920, + stg_sysconsaif_syscfg924: STG_SYSCONSAIF_SYSCFG924, + stg_sysconsaif_syscfg928: STG_SYSCONSAIF_SYSCFG928, + stg_sysconsaif_syscfg932: STG_SYSCONSAIF_SYSCFG932, +} +impl RegisterBlock { #[doc = "0x00 - STG SYSCONSAIF SYSCFG 0"] - pub stg_sysconsaif_syscfg0: STG_SYSCONSAIF_SYSCFG0, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg0(&self) -> &STG_SYSCONSAIF_SYSCFG0 { + &self.stg_sysconsaif_syscfg0 + } #[doc = "0x04 - STG SYSCONSAIF SYSCFG 4"] - pub stg_sysconsaif_syscfg4: STG_SYSCONSAIF_SYSCFG4, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg4(&self) -> &STG_SYSCONSAIF_SYSCFG4 { + &self.stg_sysconsaif_syscfg4 + } #[doc = "0x08 - STG SYSCONSAIF SYSCFG 8"] - pub stg_sysconsaif_syscfg8: STG_SYSCONSAIF_SYSCFG8, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg8(&self) -> &STG_SYSCONSAIF_SYSCFG8 { + &self.stg_sysconsaif_syscfg8 + } #[doc = "0x0c - STG SYSCONSAIF SYSCFG 12"] - pub stg_sysconsaif_syscfg12: STG_SYSCONSAIF_SYSCFG12, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg12(&self) -> &STG_SYSCONSAIF_SYSCFG12 { + &self.stg_sysconsaif_syscfg12 + } #[doc = "0x10 - STG SYSCONSAIF SYSCFG 16"] - pub stg_sysconsaif_syscfg16: STG_SYSCONSAIF_SYSCFG16, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg16(&self) -> &STG_SYSCONSAIF_SYSCFG16 { + &self.stg_sysconsaif_syscfg16 + } #[doc = "0x14 - STG SYSCONSAIF SYSCFG 20"] - pub stg_sysconsaif_syscfg20: STG_SYSCONSAIF_SYSCFG20, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg20(&self) -> &STG_SYSCONSAIF_SYSCFG20 { + &self.stg_sysconsaif_syscfg20 + } #[doc = "0x18 - STG SYSCONSAIF SYSCFG 24"] - pub stg_sysconsaif_syscfg24: STG_SYSCONSAIF_SYSCFG24, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg24(&self) -> &STG_SYSCONSAIF_SYSCFG24 { + &self.stg_sysconsaif_syscfg24 + } #[doc = "0x1c - STG SYSCONSAIF SYSCFG 28"] - pub stg_sysconsaif_syscfg28: STG_SYSCONSAIF_SYSCFG28, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg28(&self) -> &STG_SYSCONSAIF_SYSCFG28 { + &self.stg_sysconsaif_syscfg28 + } #[doc = "0x20 - STG SYSCONSAIF SYSCFG 32"] - pub stg_sysconsaif_syscfg32: STG_SYSCONSAIF_SYSCFG32, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg32(&self) -> &STG_SYSCONSAIF_SYSCFG32 { + &self.stg_sysconsaif_syscfg32 + } #[doc = "0x24 - STG SYSCONSAIF SYSCFG 36"] - pub stg_sysconsaif_syscfg36: STG_SYSCONSAIF_SYSCFG36, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg36(&self) -> &STG_SYSCONSAIF_SYSCFG36 { + &self.stg_sysconsaif_syscfg36 + } #[doc = "0x28 - STG SYSCONSAIF SYSCFG 40"] - pub stg_sysconsaif_syscfg40: STG_SYSCONSAIF_SYSCFG40, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg40(&self) -> &STG_SYSCONSAIF_SYSCFG40 { + &self.stg_sysconsaif_syscfg40 + } #[doc = "0x2c - STG SYSCONSAIF SYSCFG 44"] - pub stg_sysconsaif_syscfg44: STG_SYSCONSAIF_SYSCFG44, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg44(&self) -> &STG_SYSCONSAIF_SYSCFG44 { + &self.stg_sysconsaif_syscfg44 + } #[doc = "0x30 - STG SYSCONSAIF SYSCFG 48"] - pub stg_sysconsaif_syscfg48: STG_SYSCONSAIF_SYSCFG48, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg48(&self) -> &STG_SYSCONSAIF_SYSCFG48 { + &self.stg_sysconsaif_syscfg48 + } #[doc = "0x34 - STG SYSCONSAIF SYSCFG 52"] - pub stg_sysconsaif_syscfg52: STG_SYSCONSAIF_SYSCFG52, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg52(&self) -> &STG_SYSCONSAIF_SYSCFG52 { + &self.stg_sysconsaif_syscfg52 + } #[doc = "0x38 - STG SYSCONSAIF SYSCFG 56"] - pub stg_sysconsaif_syscfg56: STG_SYSCONSAIF_SYSCFG56, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg56(&self) -> &STG_SYSCONSAIF_SYSCFG56 { + &self.stg_sysconsaif_syscfg56 + } #[doc = "0x3c - STG SYSCONSAIF SYSCFG 60"] - pub stg_sysconsaif_syscfg60: STG_SYSCONSAIF_SYSCFG60, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg60(&self) -> &STG_SYSCONSAIF_SYSCFG60 { + &self.stg_sysconsaif_syscfg60 + } #[doc = "0x40 - STG SYSCONSAIF SYSCFG 64"] - pub stg_sysconsaif_syscfg64: STG_SYSCONSAIF_SYSCFG64, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg64(&self) -> &STG_SYSCONSAIF_SYSCFG64 { + &self.stg_sysconsaif_syscfg64 + } #[doc = "0x44 - STG SYSCONSAIF SYSCFG 68"] - pub stg_sysconsaif_syscfg68: STG_SYSCONSAIF_SYSCFG68, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg68(&self) -> &STG_SYSCONSAIF_SYSCFG68 { + &self.stg_sysconsaif_syscfg68 + } #[doc = "0x48 - STG SYSCONSAIF SYSCFG 72"] - pub stg_sysconsaif_syscfg72: STG_SYSCONSAIF_SYSCFG72, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg72(&self) -> &STG_SYSCONSAIF_SYSCFG72 { + &self.stg_sysconsaif_syscfg72 + } #[doc = "0x4c - STG SYSCONSAIF SYSCFG 76"] - pub stg_sysconsaif_syscfg76: STG_SYSCONSAIF_SYSCFG76, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg76(&self) -> &STG_SYSCONSAIF_SYSCFG76 { + &self.stg_sysconsaif_syscfg76 + } #[doc = "0x50 - STG SYSCONSAIF SYSCFG 80"] - pub stg_sysconsaif_syscfg80: STG_SYSCONSAIF_SYSCFG80, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg80(&self) -> &STG_SYSCONSAIF_SYSCFG80 { + &self.stg_sysconsaif_syscfg80 + } #[doc = "0x54 - STG SYSCONSAIF SYSCFG 84"] - pub stg_sysconsaif_syscfg84: STG_SYSCONSAIF_SYSCFG84, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg84(&self) -> &STG_SYSCONSAIF_SYSCFG84 { + &self.stg_sysconsaif_syscfg84 + } #[doc = "0x58 - STG SYSCONSAIF SYSCFG 88"] - pub stg_sysconsaif_syscfg88: STG_SYSCONSAIF_SYSCFG88, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg88(&self) -> &STG_SYSCONSAIF_SYSCFG88 { + &self.stg_sysconsaif_syscfg88 + } #[doc = "0x5c - STG SYSCONSAIF SYSCFG 92"] - pub stg_sysconsaif_syscfg92: STG_SYSCONSAIF_SYSCFG92, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg92(&self) -> &STG_SYSCONSAIF_SYSCFG92 { + &self.stg_sysconsaif_syscfg92 + } #[doc = "0x60 - STG SYSCONSAIF SYSCFG 96"] - pub stg_sysconsaif_syscfg96: STG_SYSCONSAIF_SYSCFG96, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg96(&self) -> &STG_SYSCONSAIF_SYSCFG96 { + &self.stg_sysconsaif_syscfg96 + } #[doc = "0x64 - STG SYSCONSAIF SYSCFG 100"] - pub stg_sysconsaif_syscfg100: STG_SYSCONSAIF_SYSCFG100, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg100(&self) -> &STG_SYSCONSAIF_SYSCFG100 { + &self.stg_sysconsaif_syscfg100 + } #[doc = "0x68 - STG SYSCONSAIF SYSCFG 104"] - pub stg_sysconsaif_syscfg104: STG_SYSCONSAIF_SYSCFG104, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg104(&self) -> &STG_SYSCONSAIF_SYSCFG104 { + &self.stg_sysconsaif_syscfg104 + } #[doc = "0x6c - STG SYSCONSAIF SYSCFG 108"] - pub stg_sysconsaif_syscfg108: STG_SYSCONSAIF_SYSCFG108, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg108(&self) -> &STG_SYSCONSAIF_SYSCFG108 { + &self.stg_sysconsaif_syscfg108 + } #[doc = "0x70 - STG SYSCONSAIF SYSCFG 112"] - pub stg_sysconsaif_syscfg112: STG_SYSCONSAIF_SYSCFG112, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg112(&self) -> &STG_SYSCONSAIF_SYSCFG112 { + &self.stg_sysconsaif_syscfg112 + } #[doc = "0x74 - STG SYSCONSAIF SYSCFG 116"] - pub stg_sysconsaif_syscfg116: STG_SYSCONSAIF_SYSCFG116, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg116(&self) -> &STG_SYSCONSAIF_SYSCFG116 { + &self.stg_sysconsaif_syscfg116 + } #[doc = "0x78 - STG SYSCONSAIF SYSCFG 120"] - pub stg_sysconsaif_syscfg120: STG_SYSCONSAIF_SYSCFG120, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg120(&self) -> &STG_SYSCONSAIF_SYSCFG120 { + &self.stg_sysconsaif_syscfg120 + } #[doc = "0x7c - STG SYSCONSAIF SYSCFG 124"] - pub stg_sysconsaif_syscfg124: STG_SYSCONSAIF_SYSCFG124, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg124(&self) -> &STG_SYSCONSAIF_SYSCFG124 { + &self.stg_sysconsaif_syscfg124 + } #[doc = "0x80 - STG SYSCONSAIF SYSCFG 128"] - pub stg_sysconsaif_syscfg128: STG_SYSCONSAIF_SYSCFG128, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg128(&self) -> &STG_SYSCONSAIF_SYSCFG128 { + &self.stg_sysconsaif_syscfg128 + } #[doc = "0x84 - STG SYSCONSAIF SYSCFG 132"] - pub stg_sysconsaif_syscfg132: STG_SYSCONSAIF_SYSCFG132, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg132(&self) -> &STG_SYSCONSAIF_SYSCFG132 { + &self.stg_sysconsaif_syscfg132 + } #[doc = "0x88 - STG SYSCONSAIF SYSCFG 136"] - pub stg_sysconsaif_syscfg136: STG_SYSCONSAIF_SYSCFG136, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg136(&self) -> &STG_SYSCONSAIF_SYSCFG136 { + &self.stg_sysconsaif_syscfg136 + } #[doc = "0x8c - STG SYSCONSAIF SYSCFG 140"] - pub stg_sysconsaif_syscfg140: STG_SYSCONSAIF_SYSCFG140, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg140(&self) -> &STG_SYSCONSAIF_SYSCFG140 { + &self.stg_sysconsaif_syscfg140 + } #[doc = "0x90 - STG SYSCONSAIF SYSCFG 144"] - pub stg_sysconsaif_syscfg144: STG_SYSCONSAIF_SYSCFG144, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg144(&self) -> &STG_SYSCONSAIF_SYSCFG144 { + &self.stg_sysconsaif_syscfg144 + } #[doc = "0x94 - STG SYSCONSAIF SYSCFG 148"] - pub stg_sysconsaif_syscfg148: STG_SYSCONSAIF_SYSCFG148, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg148(&self) -> &STG_SYSCONSAIF_SYSCFG148 { + &self.stg_sysconsaif_syscfg148 + } #[doc = "0x98 - STG SYSCONSAIF SYSCFG 152"] - pub stg_sysconsaif_syscfg152: STG_SYSCONSAIF_SYSCFG152, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg152(&self) -> &STG_SYSCONSAIF_SYSCFG152 { + &self.stg_sysconsaif_syscfg152 + } #[doc = "0x9c - STG SYSCONSAIF SYSCFG 156"] - pub stg_sysconsaif_syscfg156: STG_SYSCONSAIF_SYSCFG156, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg156(&self) -> &STG_SYSCONSAIF_SYSCFG156 { + &self.stg_sysconsaif_syscfg156 + } #[doc = "0xa0 - STG SYSCONSAIF SYSCFG 160"] - pub stg_sysconsaif_syscfg160: STG_SYSCONSAIF_SYSCFG160, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg160(&self) -> &STG_SYSCONSAIF_SYSCFG160 { + &self.stg_sysconsaif_syscfg160 + } #[doc = "0xa4 - STG SYSCONSAIF SYSCFG 164"] - pub stg_sysconsaif_syscfg164: STG_SYSCONSAIF_SYSCFG164, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg164(&self) -> &STG_SYSCONSAIF_SYSCFG164 { + &self.stg_sysconsaif_syscfg164 + } #[doc = "0xa8 - STG SYSCONSAIF SYSCFG 168"] - pub stg_sysconsaif_syscfg168: STG_SYSCONSAIF_SYSCFG168, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg168(&self) -> &STG_SYSCONSAIF_SYSCFG168 { + &self.stg_sysconsaif_syscfg168 + } #[doc = "0xac - STG SYSCONSAIF SYSCFG 172"] - pub stg_sysconsaif_syscfg172: STG_SYSCONSAIF_SYSCFG172, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg172(&self) -> &STG_SYSCONSAIF_SYSCFG172 { + &self.stg_sysconsaif_syscfg172 + } #[doc = "0xb0 - STG SYSCONSAIF SYSCFG 176"] - pub stg_sysconsaif_syscfg176: STG_SYSCONSAIF_SYSCFG176, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg176(&self) -> &STG_SYSCONSAIF_SYSCFG176 { + &self.stg_sysconsaif_syscfg176 + } #[doc = "0xb4 - STG SYSCONSAIF SYSCFG 180"] - pub stg_sysconsaif_syscfg180: STG_SYSCONSAIF_SYSCFG180, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg180(&self) -> &STG_SYSCONSAIF_SYSCFG180 { + &self.stg_sysconsaif_syscfg180 + } #[doc = "0xb8 - STG SYSCONSAIF SYSCFG 184"] - pub stg_sysconsaif_syscfg184: STG_SYSCONSAIF_SYSCFG184, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg184(&self) -> &STG_SYSCONSAIF_SYSCFG184 { + &self.stg_sysconsaif_syscfg184 + } #[doc = "0xbc - STG SYSCONSAIF SYSCFG 188"] - pub stg_sysconsaif_syscfg188: STG_SYSCONSAIF_SYSCFG188, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg188(&self) -> &STG_SYSCONSAIF_SYSCFG188 { + &self.stg_sysconsaif_syscfg188 + } #[doc = "0xc0 - STG SYSCONSAIF SYSCFG 192"] - pub stg_sysconsaif_syscfg192: STG_SYSCONSAIF_SYSCFG192, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg192(&self) -> &STG_SYSCONSAIF_SYSCFG192 { + &self.stg_sysconsaif_syscfg192 + } #[doc = "0xc4 - STG SYSCONSAIF SYSCFG 196"] - pub stg_sysconsaif_syscfg196: STG_SYSCONSAIF_SYSCFG196, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg196(&self) -> &STG_SYSCONSAIF_SYSCFG196 { + &self.stg_sysconsaif_syscfg196 + } #[doc = "0xc8 - STG SYSCONSAIF SYSCFG 200"] - pub stg_sysconsaif_syscfg200: STG_SYSCONSAIF_SYSCFG200, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg200(&self) -> &STG_SYSCONSAIF_SYSCFG200 { + &self.stg_sysconsaif_syscfg200 + } #[doc = "0xcc - STG SYSCONSAIF SYSCFG 204"] - pub stg_sysconsaif_syscfg204: STG_SYSCONSAIF_SYSCFG204, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg204(&self) -> &STG_SYSCONSAIF_SYSCFG204 { + &self.stg_sysconsaif_syscfg204 + } #[doc = "0xd0 - STG SYSCONSAIF SYSCFG 208"] - pub stg_sysconsaif_syscfg208: STG_SYSCONSAIF_SYSCFG208, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg208(&self) -> &STG_SYSCONSAIF_SYSCFG208 { + &self.stg_sysconsaif_syscfg208 + } #[doc = "0xd4 - STG SYSCONSAIF SYSCFG 212"] - pub stg_sysconsaif_syscfg212: STG_SYSCONSAIF_SYSCFG212, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg212(&self) -> &STG_SYSCONSAIF_SYSCFG212 { + &self.stg_sysconsaif_syscfg212 + } #[doc = "0xd8 - STG SYSCONSAIF SYSCFG 216"] - pub stg_sysconsaif_syscfg216: STG_SYSCONSAIF_SYSCFG216, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg216(&self) -> &STG_SYSCONSAIF_SYSCFG216 { + &self.stg_sysconsaif_syscfg216 + } #[doc = "0xdc - STG SYSCONSAIF SYSCFG 220"] - pub stg_sysconsaif_syscfg220: STG_SYSCONSAIF_SYSCFG220, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg220(&self) -> &STG_SYSCONSAIF_SYSCFG220 { + &self.stg_sysconsaif_syscfg220 + } #[doc = "0xe0 - STG SYSCONSAIF SYSCFG 224"] - pub stg_sysconsaif_syscfg224: STG_SYSCONSAIF_SYSCFG224, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg224(&self) -> &STG_SYSCONSAIF_SYSCFG224 { + &self.stg_sysconsaif_syscfg224 + } #[doc = "0xe4 - STG SYSCONSAIF SYSCFG 228"] - pub stg_sysconsaif_syscfg228: STG_SYSCONSAIF_SYSCFG228, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg228(&self) -> &STG_SYSCONSAIF_SYSCFG228 { + &self.stg_sysconsaif_syscfg228 + } #[doc = "0xe8 - STG SYSCONSAIF SYSCFG 232"] - pub stg_sysconsaif_syscfg232: STG_SYSCONSAIF_SYSCFG232, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg232(&self) -> &STG_SYSCONSAIF_SYSCFG232 { + &self.stg_sysconsaif_syscfg232 + } #[doc = "0xec - STG SYSCONSAIF SYSCFG 236"] - pub stg_sysconsaif_syscfg236: STG_SYSCONSAIF_SYSCFG236, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg236(&self) -> &STG_SYSCONSAIF_SYSCFG236 { + &self.stg_sysconsaif_syscfg236 + } #[doc = "0xf0 - STG SYSCONSAIF SYSCFG 240"] - pub stg_sysconsaif_syscfg240: STG_SYSCONSAIF_SYSCFG240, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg240(&self) -> &STG_SYSCONSAIF_SYSCFG240 { + &self.stg_sysconsaif_syscfg240 + } #[doc = "0xf4 - STG SYSCONSAIF SYSCFG 244"] - pub stg_sysconsaif_syscfg244: STG_SYSCONSAIF_SYSCFG244, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg244(&self) -> &STG_SYSCONSAIF_SYSCFG244 { + &self.stg_sysconsaif_syscfg244 + } #[doc = "0xf8 - STG SYSCONSAIF SYSCFG 248"] - pub stg_sysconsaif_syscfg248: STG_SYSCONSAIF_SYSCFG248, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg248(&self) -> &STG_SYSCONSAIF_SYSCFG248 { + &self.stg_sysconsaif_syscfg248 + } #[doc = "0xfc - STG SYSCONSAIF SYSCFG 252"] - pub stg_sysconsaif_syscfg252: STG_SYSCONSAIF_SYSCFG252, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg252(&self) -> &STG_SYSCONSAIF_SYSCFG252 { + &self.stg_sysconsaif_syscfg252 + } #[doc = "0x100 - STG SYSCONSAIF SYSCFG 256"] - pub stg_sysconsaif_syscfg256: STG_SYSCONSAIF_SYSCFG256, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg256(&self) -> &STG_SYSCONSAIF_SYSCFG256 { + &self.stg_sysconsaif_syscfg256 + } #[doc = "0x104 - STG SYSCONSAIF SYSCFG 260"] - pub stg_sysconsaif_syscfg260: STG_SYSCONSAIF_SYSCFG260, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg260(&self) -> &STG_SYSCONSAIF_SYSCFG260 { + &self.stg_sysconsaif_syscfg260 + } #[doc = "0x108 - STG SYSCONSAIF SYSCFG 264"] - pub stg_sysconsaif_syscfg264: STG_SYSCONSAIF_SYSCFG264, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg264(&self) -> &STG_SYSCONSAIF_SYSCFG264 { + &self.stg_sysconsaif_syscfg264 + } #[doc = "0x10c - STG SYSCONSAIF SYSCFG 268"] - pub stg_sysconsaif_syscfg268: STG_SYSCONSAIF_SYSCFG268, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg268(&self) -> &STG_SYSCONSAIF_SYSCFG268 { + &self.stg_sysconsaif_syscfg268 + } #[doc = "0x110 - STG SYSCONSAIF SYSCFG 272"] - pub stg_sysconsaif_syscfg272: STG_SYSCONSAIF_SYSCFG272, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg272(&self) -> &STG_SYSCONSAIF_SYSCFG272 { + &self.stg_sysconsaif_syscfg272 + } #[doc = "0x114 - STG SYSCONSAIF SYSCFG 276"] - pub stg_sysconsaif_syscfg276: STG_SYSCONSAIF_SYSCFG276, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg276(&self) -> &STG_SYSCONSAIF_SYSCFG276 { + &self.stg_sysconsaif_syscfg276 + } #[doc = "0x118 - STG SYSCONSAIF SYSCFG 280"] - pub stg_sysconsaif_syscfg280: STG_SYSCONSAIF_SYSCFG280, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg280(&self) -> &STG_SYSCONSAIF_SYSCFG280 { + &self.stg_sysconsaif_syscfg280 + } #[doc = "0x11c - STG SYSCONSAIF SYSCFG 284"] - pub stg_sysconsaif_syscfg284: STG_SYSCONSAIF_SYSCFG284, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg284(&self) -> &STG_SYSCONSAIF_SYSCFG284 { + &self.stg_sysconsaif_syscfg284 + } #[doc = "0x120 - STG SYSCONSAIF SYSCFG 288"] - pub stg_sysconsaif_syscfg288: STG_SYSCONSAIF_SYSCFG288, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg288(&self) -> &STG_SYSCONSAIF_SYSCFG288 { + &self.stg_sysconsaif_syscfg288 + } #[doc = "0x124 - STG SYSCONSAIF SYSCFG 292"] - pub stg_sysconsaif_syscfg292: STG_SYSCONSAIF_SYSCFG292, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg292(&self) -> &STG_SYSCONSAIF_SYSCFG292 { + &self.stg_sysconsaif_syscfg292 + } #[doc = "0x128 - STG SYSCONSAIF SYSCFG 296"] - pub stg_sysconsaif_syscfg296: STG_SYSCONSAIF_SYSCFG296, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg296(&self) -> &STG_SYSCONSAIF_SYSCFG296 { + &self.stg_sysconsaif_syscfg296 + } #[doc = "0x12c - STG SYSCONSAIF SYSCFG 300"] - pub stg_sysconsaif_syscfg300: STG_SYSCONSAIF_SYSCFG300, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg300(&self) -> &STG_SYSCONSAIF_SYSCFG300 { + &self.stg_sysconsaif_syscfg300 + } #[doc = "0x130 - STG SYSCONSAIF SYSCFG 304"] - pub stg_sysconsaif_syscfg304: STG_SYSCONSAIF_SYSCFG304, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg304(&self) -> &STG_SYSCONSAIF_SYSCFG304 { + &self.stg_sysconsaif_syscfg304 + } #[doc = "0x134 - STG SYSCONSAIF SYSCFG 308"] - pub stg_sysconsaif_syscfg308: STG_SYSCONSAIF_SYSCFG308, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg308(&self) -> &STG_SYSCONSAIF_SYSCFG308 { + &self.stg_sysconsaif_syscfg308 + } #[doc = "0x138 - STG SYSCONSAIF SYSCFG 312"] - pub stg_sysconsaif_syscfg312: STG_SYSCONSAIF_SYSCFG312, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg312(&self) -> &STG_SYSCONSAIF_SYSCFG312 { + &self.stg_sysconsaif_syscfg312 + } #[doc = "0x13c - STG SYSCONSAIF SYSCFG 316"] - pub stg_sysconsaif_syscfg316: STG_SYSCONSAIF_SYSCFG316, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg316(&self) -> &STG_SYSCONSAIF_SYSCFG316 { + &self.stg_sysconsaif_syscfg316 + } #[doc = "0x140 - STG SYSCONSAIF SYSCFG 320"] - pub stg_sysconsaif_syscfg320: STG_SYSCONSAIF_SYSCFG320, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg320(&self) -> &STG_SYSCONSAIF_SYSCFG320 { + &self.stg_sysconsaif_syscfg320 + } #[doc = "0x144 - STG SYSCONSAIF SYSCFG 324"] - pub stg_sysconsaif_syscfg324: STG_SYSCONSAIF_SYSCFG324, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg324(&self) -> &STG_SYSCONSAIF_SYSCFG324 { + &self.stg_sysconsaif_syscfg324 + } #[doc = "0x148 - STG SYSCONSAIF SYSCFG 328"] - pub stg_sysconsaif_syscfg328: STG_SYSCONSAIF_SYSCFG328, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg328(&self) -> &STG_SYSCONSAIF_SYSCFG328 { + &self.stg_sysconsaif_syscfg328 + } #[doc = "0x14c - STG SYSCONSAIF SYSCFG 332"] - pub stg_sysconsaif_syscfg332: STG_SYSCONSAIF_SYSCFG332, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg332(&self) -> &STG_SYSCONSAIF_SYSCFG332 { + &self.stg_sysconsaif_syscfg332 + } #[doc = "0x150 - STG SYSCONSAIF SYSCFG 336"] - pub stg_sysconsaif_syscfg336: STG_SYSCONSAIF_SYSCFG336, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg336(&self) -> &STG_SYSCONSAIF_SYSCFG336 { + &self.stg_sysconsaif_syscfg336 + } #[doc = "0x154 - STG SYSCONSAIF SYSCFG 340"] - pub stg_sysconsaif_syscfg340: STG_SYSCONSAIF_SYSCFG340, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg340(&self) -> &STG_SYSCONSAIF_SYSCFG340 { + &self.stg_sysconsaif_syscfg340 + } #[doc = "0x158 - STG SYSCONSAIF SYSCFG 344"] - pub stg_sysconsaif_syscfg344: STG_SYSCONSAIF_SYSCFG344, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg344(&self) -> &STG_SYSCONSAIF_SYSCFG344 { + &self.stg_sysconsaif_syscfg344 + } #[doc = "0x15c - STG SYSCONSAIF SYSCFG 348"] - pub stg_sysconsaif_syscfg348: STG_SYSCONSAIF_SYSCFG348, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg348(&self) -> &STG_SYSCONSAIF_SYSCFG348 { + &self.stg_sysconsaif_syscfg348 + } #[doc = "0x160 - STG SYSCONSAIF SYSCFG 352"] - pub stg_sysconsaif_syscfg352: STG_SYSCONSAIF_SYSCFG352, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg352(&self) -> &STG_SYSCONSAIF_SYSCFG352 { + &self.stg_sysconsaif_syscfg352 + } #[doc = "0x164 - STG SYSCONSAIF SYSCFG 356"] - pub stg_sysconsaif_syscfg356: STG_SYSCONSAIF_SYSCFG356, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg356(&self) -> &STG_SYSCONSAIF_SYSCFG356 { + &self.stg_sysconsaif_syscfg356 + } #[doc = "0x168 - STG SYSCONSAIF SYSCFG 360"] - pub stg_sysconsaif_syscfg360: STG_SYSCONSAIF_SYSCFG360, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg360(&self) -> &STG_SYSCONSAIF_SYSCFG360 { + &self.stg_sysconsaif_syscfg360 + } #[doc = "0x16c - STG SYSCONSAIF SYSCFG 364"] - pub stg_sysconsaif_syscfg364: STG_SYSCONSAIF_SYSCFG364, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg364(&self) -> &STG_SYSCONSAIF_SYSCFG364 { + &self.stg_sysconsaif_syscfg364 + } #[doc = "0x170 - STG SYSCONSAIF SYSCFG 368"] - pub stg_sysconsaif_syscfg368: STG_SYSCONSAIF_SYSCFG368, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg368(&self) -> &STG_SYSCONSAIF_SYSCFG368 { + &self.stg_sysconsaif_syscfg368 + } #[doc = "0x174 - STG SYSCONSAIF SYSCFG 372"] - pub stg_sysconsaif_syscfg372: STG_SYSCONSAIF_SYSCFG372, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg372(&self) -> &STG_SYSCONSAIF_SYSCFG372 { + &self.stg_sysconsaif_syscfg372 + } #[doc = "0x178 - STG SYSCONSAIF SYSCFG 376"] - pub stg_sysconsaif_syscfg376: STG_SYSCONSAIF_SYSCFG376, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg376(&self) -> &STG_SYSCONSAIF_SYSCFG376 { + &self.stg_sysconsaif_syscfg376 + } #[doc = "0x17c - STG SYSCONSAIF SYSCFG 380"] - pub stg_sysconsaif_syscfg380: STG_SYSCONSAIF_SYSCFG380, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg380(&self) -> &STG_SYSCONSAIF_SYSCFG380 { + &self.stg_sysconsaif_syscfg380 + } #[doc = "0x180 - STG SYSCONSAIF SYSCFG 384"] - pub stg_sysconsaif_syscfg384: STG_SYSCONSAIF_SYSCFG384, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg384(&self) -> &STG_SYSCONSAIF_SYSCFG384 { + &self.stg_sysconsaif_syscfg384 + } #[doc = "0x184 - STG SYSCONSAIF SYSCFG 388"] - pub stg_sysconsaif_syscfg388: STG_SYSCONSAIF_SYSCFG388, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg388(&self) -> &STG_SYSCONSAIF_SYSCFG388 { + &self.stg_sysconsaif_syscfg388 + } #[doc = "0x188 - STG SYSCONSAIF SYSCFG 392"] - pub stg_sysconsaif_syscfg392: STG_SYSCONSAIF_SYSCFG392, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg392(&self) -> &STG_SYSCONSAIF_SYSCFG392 { + &self.stg_sysconsaif_syscfg392 + } #[doc = "0x18c - STG SYSCONSAIF SYSCFG 396"] - pub stg_sysconsaif_syscfg396: STG_SYSCONSAIF_SYSCFG396, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg396(&self) -> &STG_SYSCONSAIF_SYSCFG396 { + &self.stg_sysconsaif_syscfg396 + } #[doc = "0x190 - STG SYSCONSAIF SYSCFG 400"] - pub stg_sysconsaif_syscfg400: STG_SYSCONSAIF_SYSCFG400, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg400(&self) -> &STG_SYSCONSAIF_SYSCFG400 { + &self.stg_sysconsaif_syscfg400 + } #[doc = "0x194 - STG SYSCONSAIF SYSCFG 404"] - pub stg_sysconsaif_syscfg404: STG_SYSCONSAIF_SYSCFG404, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg404(&self) -> &STG_SYSCONSAIF_SYSCFG404 { + &self.stg_sysconsaif_syscfg404 + } #[doc = "0x198 - STG SYSCONSAIF SYSCFG 408"] - pub stg_sysconsaif_syscfg408: STG_SYSCONSAIF_SYSCFG408, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg408(&self) -> &STG_SYSCONSAIF_SYSCFG408 { + &self.stg_sysconsaif_syscfg408 + } #[doc = "0x19c - STG SYSCONSAIF SYSCFG 412"] - pub stg_sysconsaif_syscfg412: STG_SYSCONSAIF_SYSCFG412, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg412(&self) -> &STG_SYSCONSAIF_SYSCFG412 { + &self.stg_sysconsaif_syscfg412 + } #[doc = "0x1a0 - STG SYSCONSAIF SYSCFG 416"] - pub stg_sysconsaif_syscfg416: STG_SYSCONSAIF_SYSCFG416, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg416(&self) -> &STG_SYSCONSAIF_SYSCFG416 { + &self.stg_sysconsaif_syscfg416 + } #[doc = "0x1a4 - STG SYSCONSAIF SYSCFG 420"] - pub stg_sysconsaif_syscfg420: STG_SYSCONSAIF_SYSCFG420, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg420(&self) -> &STG_SYSCONSAIF_SYSCFG420 { + &self.stg_sysconsaif_syscfg420 + } #[doc = "0x1a8 - STG SYSCONSAIF SYSCFG 424"] - pub stg_sysconsaif_syscfg424: STG_SYSCONSAIF_SYSCFG424, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg424(&self) -> &STG_SYSCONSAIF_SYSCFG424 { + &self.stg_sysconsaif_syscfg424 + } #[doc = "0x1ac - STG SYSCONSAIF SYSCFG 428"] - pub stg_sysconsaif_syscfg428: STG_SYSCONSAIF_SYSCFG428, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg428(&self) -> &STG_SYSCONSAIF_SYSCFG428 { + &self.stg_sysconsaif_syscfg428 + } #[doc = "0x1b0 - STG SYSCONSAIF SYSCFG 432"] - pub stg_sysconsaif_syscfg432: STG_SYSCONSAIF_SYSCFG432, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg432(&self) -> &STG_SYSCONSAIF_SYSCFG432 { + &self.stg_sysconsaif_syscfg432 + } #[doc = "0x1b4 - STG SYSCONSAIF SYSCFG 436"] - pub stg_sysconsaif_syscfg436: STG_SYSCONSAIF_SYSCFG436, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg436(&self) -> &STG_SYSCONSAIF_SYSCFG436 { + &self.stg_sysconsaif_syscfg436 + } #[doc = "0x1b8 - STG SYSCONSAIF SYSCFG 440"] - pub stg_sysconsaif_syscfg440: STG_SYSCONSAIF_SYSCFG440, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg440(&self) -> &STG_SYSCONSAIF_SYSCFG440 { + &self.stg_sysconsaif_syscfg440 + } #[doc = "0x1bc - STG SYSCONSAIF SYSCFG 444"] - pub stg_sysconsaif_syscfg444: STG_SYSCONSAIF_SYSCFG444, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg444(&self) -> &STG_SYSCONSAIF_SYSCFG444 { + &self.stg_sysconsaif_syscfg444 + } #[doc = "0x1c0 - STG SYSCONSAIF SYSCFG 448"] - pub stg_sysconsaif_syscfg448: STG_SYSCONSAIF_SYSCFG448, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg448(&self) -> &STG_SYSCONSAIF_SYSCFG448 { + &self.stg_sysconsaif_syscfg448 + } #[doc = "0x1c4 - STG SYSCONSAIF SYSCFG 452"] - pub stg_sysconsaif_syscfg452: STG_SYSCONSAIF_SYSCFG452, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg452(&self) -> &STG_SYSCONSAIF_SYSCFG452 { + &self.stg_sysconsaif_syscfg452 + } #[doc = "0x1c8 - STG SYSCONSAIF SYSCFG 456"] - pub stg_sysconsaif_syscfg456: STG_SYSCONSAIF_SYSCFG456, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg456(&self) -> &STG_SYSCONSAIF_SYSCFG456 { + &self.stg_sysconsaif_syscfg456 + } #[doc = "0x1cc - STG SYSCONSAIF SYSCFG 460"] - pub stg_sysconsaif_syscfg460: STG_SYSCONSAIF_SYSCFG460, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg460(&self) -> &STG_SYSCONSAIF_SYSCFG460 { + &self.stg_sysconsaif_syscfg460 + } #[doc = "0x1d0 - STG SYSCONSAIF SYSCFG 464"] - pub stg_sysconsaif_syscfg464: STG_SYSCONSAIF_SYSCFG464, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg464(&self) -> &STG_SYSCONSAIF_SYSCFG464 { + &self.stg_sysconsaif_syscfg464 + } #[doc = "0x1d4 - STG SYSCONSAIF SYSCFG 468"] - pub stg_sysconsaif_syscfg468: STG_SYSCONSAIF_SYSCFG468, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg468(&self) -> &STG_SYSCONSAIF_SYSCFG468 { + &self.stg_sysconsaif_syscfg468 + } #[doc = "0x1d8 - STG SYSCONSAIF SYSCFG 472"] - pub stg_sysconsaif_syscfg472: STG_SYSCONSAIF_SYSCFG472, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg472(&self) -> &STG_SYSCONSAIF_SYSCFG472 { + &self.stg_sysconsaif_syscfg472 + } #[doc = "0x1dc - STG SYSCONSAIF SYSCFG 476"] - pub stg_sysconsaif_syscfg476: STG_SYSCONSAIF_SYSCFG476, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg476(&self) -> &STG_SYSCONSAIF_SYSCFG476 { + &self.stg_sysconsaif_syscfg476 + } #[doc = "0x1e0 - STG SYSCONSAIF SYSCFG 480"] - pub stg_sysconsaif_syscfg480: STG_SYSCONSAIF_SYSCFG480, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg480(&self) -> &STG_SYSCONSAIF_SYSCFG480 { + &self.stg_sysconsaif_syscfg480 + } #[doc = "0x1e4 - STG SYSCONSAIF SYSCFG 484"] - pub stg_sysconsaif_syscfg484: STG_SYSCONSAIF_SYSCFG484, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg484(&self) -> &STG_SYSCONSAIF_SYSCFG484 { + &self.stg_sysconsaif_syscfg484 + } #[doc = "0x1e8 - STG SYSCONSAIF SYSCFG 488"] - pub stg_sysconsaif_syscfg488: STG_SYSCONSAIF_SYSCFG488, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg488(&self) -> &STG_SYSCONSAIF_SYSCFG488 { + &self.stg_sysconsaif_syscfg488 + } #[doc = "0x1ec - STG SYSCONSAIF SYSCFG 492"] - pub stg_sysconsaif_syscfg492: STG_SYSCONSAIF_SYSCFG492, - _reserved124: [u8; 0x04], + #[inline(always)] + pub const fn stg_sysconsaif_syscfg492(&self) -> &STG_SYSCONSAIF_SYSCFG492 { + &self.stg_sysconsaif_syscfg492 + } #[doc = "0x1f4 - STG SYSCONSAIF SYSCFG 500"] - pub stg_sysconsaif_syscfg500: STG_SYSCONSAIF_SYSCFG500, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg500(&self) -> &STG_SYSCONSAIF_SYSCFG500 { + &self.stg_sysconsaif_syscfg500 + } #[doc = "0x1f8 - STG SYSCONSAIF SYSCFG 504"] - pub stg_sysconsaif_syscfg504: STG_SYSCONSAIF_SYSCFG504, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg504(&self) -> &STG_SYSCONSAIF_SYSCFG504 { + &self.stg_sysconsaif_syscfg504 + } #[doc = "0x1fc - STG SYSCONSAIF SYSCFG 508"] - pub stg_sysconsaif_syscfg508: STG_SYSCONSAIF_SYSCFG508, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg508(&self) -> &STG_SYSCONSAIF_SYSCFG508 { + &self.stg_sysconsaif_syscfg508 + } #[doc = "0x200 - STG SYSCONSAIF SYSCFG 512"] - pub stg_sysconsaif_syscfg512: STG_SYSCONSAIF_SYSCFG512, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg512(&self) -> &STG_SYSCONSAIF_SYSCFG512 { + &self.stg_sysconsaif_syscfg512 + } #[doc = "0x204 - STG SYSCONSAIF SYSCFG 516"] - pub stg_sysconsaif_syscfg516: STG_SYSCONSAIF_SYSCFG516, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg516(&self) -> &STG_SYSCONSAIF_SYSCFG516 { + &self.stg_sysconsaif_syscfg516 + } #[doc = "0x208 - STG SYSCONSAIF SYSCFG 520"] - pub stg_sysconsaif_syscfg520: STG_SYSCONSAIF_SYSCFG520, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg520(&self) -> &STG_SYSCONSAIF_SYSCFG520 { + &self.stg_sysconsaif_syscfg520 + } #[doc = "0x20c - STG SYSCONSAIF SYSCFG 524"] - pub stg_sysconsaif_syscfg524: STG_SYSCONSAIF_SYSCFG524, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg524(&self) -> &STG_SYSCONSAIF_SYSCFG524 { + &self.stg_sysconsaif_syscfg524 + } #[doc = "0x210 - STG SYSCONSAIF SYSCFG 528"] - pub stg_sysconsaif_syscfg528: STG_SYSCONSAIF_SYSCFG528, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg528(&self) -> &STG_SYSCONSAIF_SYSCFG528 { + &self.stg_sysconsaif_syscfg528 + } #[doc = "0x214 - STG SYSCONSAIF SYSCFG 532"] - pub stg_sysconsaif_syscfg532: STG_SYSCONSAIF_SYSCFG532, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg532(&self) -> &STG_SYSCONSAIF_SYSCFG532 { + &self.stg_sysconsaif_syscfg532 + } #[doc = "0x218 - STG SYSCONSAIF SYSCFG 536"] - pub stg_sysconsaif_syscfg536: STG_SYSCONSAIF_SYSCFG536, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg536(&self) -> &STG_SYSCONSAIF_SYSCFG536 { + &self.stg_sysconsaif_syscfg536 + } #[doc = "0x21c - STG SYSCONSAIF SYSCFG 540"] - pub stg_sysconsaif_syscfg540: STG_SYSCONSAIF_SYSCFG540, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg540(&self) -> &STG_SYSCONSAIF_SYSCFG540 { + &self.stg_sysconsaif_syscfg540 + } #[doc = "0x220 - STG SYSCONSAIF SYSCFG 544"] - pub stg_sysconsaif_syscfg544: STG_SYSCONSAIF_SYSCFG544, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg544(&self) -> &STG_SYSCONSAIF_SYSCFG544 { + &self.stg_sysconsaif_syscfg544 + } #[doc = "0x224 - STG SYSCONSAIF SYSCFG 548"] - pub stg_sysconsaif_syscfg548: STG_SYSCONSAIF_SYSCFG548, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg548(&self) -> &STG_SYSCONSAIF_SYSCFG548 { + &self.stg_sysconsaif_syscfg548 + } #[doc = "0x228 - STG SYSCONSAIF SYSCFG 552"] - pub stg_sysconsaif_syscfg552: STG_SYSCONSAIF_SYSCFG552, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg552(&self) -> &STG_SYSCONSAIF_SYSCFG552 { + &self.stg_sysconsaif_syscfg552 + } #[doc = "0x22c - STG SYSCONSAIF SYSCFG 556"] - pub stg_sysconsaif_syscfg556: STG_SYSCONSAIF_SYSCFG556, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg556(&self) -> &STG_SYSCONSAIF_SYSCFG556 { + &self.stg_sysconsaif_syscfg556 + } #[doc = "0x230 - STG SYSCONSAIF SYSCFG 560"] - pub stg_sysconsaif_syscfg560: STG_SYSCONSAIF_SYSCFG560, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg560(&self) -> &STG_SYSCONSAIF_SYSCFG560 { + &self.stg_sysconsaif_syscfg560 + } #[doc = "0x234 - STG SYSCONSAIF SYSCFG 564"] - pub stg_sysconsaif_syscfg564: STG_SYSCONSAIF_SYSCFG564, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg564(&self) -> &STG_SYSCONSAIF_SYSCFG564 { + &self.stg_sysconsaif_syscfg564 + } #[doc = "0x238 - STG SYSCONSAIF SYSCFG 568"] - pub stg_sysconsaif_syscfg568: STG_SYSCONSAIF_SYSCFG568, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg568(&self) -> &STG_SYSCONSAIF_SYSCFG568 { + &self.stg_sysconsaif_syscfg568 + } #[doc = "0x23c - STG SYSCONSAIF SYSCFG 572"] - pub stg_sysconsaif_syscfg572: STG_SYSCONSAIF_SYSCFG572, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg572(&self) -> &STG_SYSCONSAIF_SYSCFG572 { + &self.stg_sysconsaif_syscfg572 + } #[doc = "0x240 - STG SYSCONSAIF SYSCFG 576"] - pub stg_sysconsaif_syscfg576: STG_SYSCONSAIF_SYSCFG576, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg576(&self) -> &STG_SYSCONSAIF_SYSCFG576 { + &self.stg_sysconsaif_syscfg576 + } #[doc = "0x244 - STG SYSCONSAIF SYSCFG 580"] - pub stg_sysconsaif_syscfg580: STG_SYSCONSAIF_SYSCFG580, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg580(&self) -> &STG_SYSCONSAIF_SYSCFG580 { + &self.stg_sysconsaif_syscfg580 + } #[doc = "0x248 - STG SYSCONSAIF SYSCFG 584"] - pub stg_sysconsaif_syscfg584: STG_SYSCONSAIF_SYSCFG584, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg584(&self) -> &STG_SYSCONSAIF_SYSCFG584 { + &self.stg_sysconsaif_syscfg584 + } #[doc = "0x24c - STG SYSCONSAIF SYSCFG 588"] - pub stg_sysconsaif_syscfg588: STG_SYSCONSAIF_SYSCFG588, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg588(&self) -> &STG_SYSCONSAIF_SYSCFG588 { + &self.stg_sysconsaif_syscfg588 + } #[doc = "0x250 - STG SYSCONSAIF SYSCFG 592"] - pub stg_sysconsaif_syscfg592: STG_SYSCONSAIF_SYSCFG592, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg592(&self) -> &STG_SYSCONSAIF_SYSCFG592 { + &self.stg_sysconsaif_syscfg592 + } #[doc = "0x254 - STG SYSCONSAIF SYSCFG 596"] - pub stg_sysconsaif_syscfg596: STG_SYSCONSAIF_SYSCFG596, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg596(&self) -> &STG_SYSCONSAIF_SYSCFG596 { + &self.stg_sysconsaif_syscfg596 + } #[doc = "0x258 - STG SYSCONSAIF SYSCFG 600"] - pub stg_sysconsaif_syscfg600: STG_SYSCONSAIF_SYSCFG600, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg600(&self) -> &STG_SYSCONSAIF_SYSCFG600 { + &self.stg_sysconsaif_syscfg600 + } #[doc = "0x25c - STG SYSCONSAIF SYSCFG 604"] - pub stg_sysconsaif_syscfg604: STG_SYSCONSAIF_SYSCFG604, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg604(&self) -> &STG_SYSCONSAIF_SYSCFG604 { + &self.stg_sysconsaif_syscfg604 + } #[doc = "0x260 - STG SYSCONSAIF SYSCFG 608"] - pub stg_sysconsaif_syscfg608: STG_SYSCONSAIF_SYSCFG608, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg608(&self) -> &STG_SYSCONSAIF_SYSCFG608 { + &self.stg_sysconsaif_syscfg608 + } #[doc = "0x264 - STG SYSCONSAIF SYSCFG 612"] - pub stg_sysconsaif_syscfg612: STG_SYSCONSAIF_SYSCFG612, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg612(&self) -> &STG_SYSCONSAIF_SYSCFG612 { + &self.stg_sysconsaif_syscfg612 + } #[doc = "0x268 - STG SYSCONSAIF SYSCFG 616"] - pub stg_sysconsaif_syscfg616: STG_SYSCONSAIF_SYSCFG616, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg616(&self) -> &STG_SYSCONSAIF_SYSCFG616 { + &self.stg_sysconsaif_syscfg616 + } #[doc = "0x26c - STG SYSCONSAIF SYSCFG 620"] - pub stg_sysconsaif_syscfg620: STG_SYSCONSAIF_SYSCFG620, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg620(&self) -> &STG_SYSCONSAIF_SYSCFG620 { + &self.stg_sysconsaif_syscfg620 + } #[doc = "0x270 - STG SYSCONSAIF SYSCFG 624"] - pub stg_sysconsaif_syscfg624: STG_SYSCONSAIF_SYSCFG624, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg624(&self) -> &STG_SYSCONSAIF_SYSCFG624 { + &self.stg_sysconsaif_syscfg624 + } #[doc = "0x274 - STG SYSCONSAIF SYSCFG 628"] - pub stg_sysconsaif_syscfg628: STG_SYSCONSAIF_SYSCFG628, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg628(&self) -> &STG_SYSCONSAIF_SYSCFG628 { + &self.stg_sysconsaif_syscfg628 + } #[doc = "0x278 - STG SYSCONSAIF SYSCFG 632"] - pub stg_sysconsaif_syscfg632: STG_SYSCONSAIF_SYSCFG632, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg632(&self) -> &STG_SYSCONSAIF_SYSCFG632 { + &self.stg_sysconsaif_syscfg632 + } #[doc = "0x27c - STG SYSCONSAIF SYSCFG 636"] - pub stg_sysconsaif_syscfg636: STG_SYSCONSAIF_SYSCFG636, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg636(&self) -> &STG_SYSCONSAIF_SYSCFG636 { + &self.stg_sysconsaif_syscfg636 + } #[doc = "0x280 - STG SYSCONSAIF SYSCFG 640"] - pub stg_sysconsaif_syscfg640: STG_SYSCONSAIF_SYSCFG640, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg640(&self) -> &STG_SYSCONSAIF_SYSCFG640 { + &self.stg_sysconsaif_syscfg640 + } #[doc = "0x284 - STG SYSCONSAIF SYSCFG 644"] - pub stg_sysconsaif_syscfg644: STG_SYSCONSAIF_SYSCFG644, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg644(&self) -> &STG_SYSCONSAIF_SYSCFG644 { + &self.stg_sysconsaif_syscfg644 + } #[doc = "0x288 - STG SYSCONSAIF SYSCFG 648"] - pub stg_sysconsaif_syscfg648: STG_SYSCONSAIF_SYSCFG648, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg648(&self) -> &STG_SYSCONSAIF_SYSCFG648 { + &self.stg_sysconsaif_syscfg648 + } #[doc = "0x28c - STG SYSCONSAIF SYSCFG 652"] - pub stg_sysconsaif_syscfg652: STG_SYSCONSAIF_SYSCFG652, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg652(&self) -> &STG_SYSCONSAIF_SYSCFG652 { + &self.stg_sysconsaif_syscfg652 + } #[doc = "0x290 - STG SYSCONSAIF SYSCFG 656"] - pub stg_sysconsaif_syscfg656: STG_SYSCONSAIF_SYSCFG656, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg656(&self) -> &STG_SYSCONSAIF_SYSCFG656 { + &self.stg_sysconsaif_syscfg656 + } #[doc = "0x294 - STG SYSCONSAIF SYSCFG 660"] - pub stg_sysconsaif_syscfg660: STG_SYSCONSAIF_SYSCFG660, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg660(&self) -> &STG_SYSCONSAIF_SYSCFG660 { + &self.stg_sysconsaif_syscfg660 + } #[doc = "0x298 - STG SYSCONSAIF SYSCFG 664"] - pub stg_sysconsaif_syscfg664: STG_SYSCONSAIF_SYSCFG664, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg664(&self) -> &STG_SYSCONSAIF_SYSCFG664 { + &self.stg_sysconsaif_syscfg664 + } #[doc = "0x29c - STG SYSCONSAIF SYSCFG 668"] - pub stg_sysconsaif_syscfg668: STG_SYSCONSAIF_SYSCFG668, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg668(&self) -> &STG_SYSCONSAIF_SYSCFG668 { + &self.stg_sysconsaif_syscfg668 + } #[doc = "0x2a0 - STG SYSCONSAIF SYSCFG 672"] - pub stg_sysconsaif_syscfg672: STG_SYSCONSAIF_SYSCFG672, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg672(&self) -> &STG_SYSCONSAIF_SYSCFG672 { + &self.stg_sysconsaif_syscfg672 + } #[doc = "0x2a4 - STG SYSCONSAIF SYSCFG 676"] - pub stg_sysconsaif_syscfg676: STG_SYSCONSAIF_SYSCFG676, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg676(&self) -> &STG_SYSCONSAIF_SYSCFG676 { + &self.stg_sysconsaif_syscfg676 + } #[doc = "0x2a8 - STG SYSCONSAIF SYSCFG 680"] - pub stg_sysconsaif_syscfg680: STG_SYSCONSAIF_SYSCFG680, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg680(&self) -> &STG_SYSCONSAIF_SYSCFG680 { + &self.stg_sysconsaif_syscfg680 + } #[doc = "0x2ac - STG SYSCONSAIF SYSCFG 684"] - pub stg_sysconsaif_syscfg684: STG_SYSCONSAIF_SYSCFG684, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg684(&self) -> &STG_SYSCONSAIF_SYSCFG684 { + &self.stg_sysconsaif_syscfg684 + } #[doc = "0x2b0 - STG SYSCONSAIF SYSCFG 688"] - pub stg_sysconsaif_syscfg688: STG_SYSCONSAIF_SYSCFG688, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg688(&self) -> &STG_SYSCONSAIF_SYSCFG688 { + &self.stg_sysconsaif_syscfg688 + } #[doc = "0x2b4 - STG SYSCONSAIF SYSCFG 692"] - pub stg_sysconsaif_syscfg692: STG_SYSCONSAIF_SYSCFG692, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg692(&self) -> &STG_SYSCONSAIF_SYSCFG692 { + &self.stg_sysconsaif_syscfg692 + } #[doc = "0x2b8 - STG SYSCONSAIF SYSCFG 696"] - pub stg_sysconsaif_syscfg696: STG_SYSCONSAIF_SYSCFG696, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg696(&self) -> &STG_SYSCONSAIF_SYSCFG696 { + &self.stg_sysconsaif_syscfg696 + } #[doc = "0x2bc - STG SYSCONSAIF SYSCFG 700"] - pub stg_sysconsaif_syscfg700: STG_SYSCONSAIF_SYSCFG700, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg700(&self) -> &STG_SYSCONSAIF_SYSCFG700 { + &self.stg_sysconsaif_syscfg700 + } #[doc = "0x2c0 - STG SYSCONSAIF SYSCFG 704"] - pub stg_sysconsaif_syscfg704: STG_SYSCONSAIF_SYSCFG704, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg704(&self) -> &STG_SYSCONSAIF_SYSCFG704 { + &self.stg_sysconsaif_syscfg704 + } #[doc = "0x2c4 - STG SYSCONSAIF SYSCFG 708"] - pub stg_sysconsaif_syscfg708: STG_SYSCONSAIF_SYSCFG708, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg708(&self) -> &STG_SYSCONSAIF_SYSCFG708 { + &self.stg_sysconsaif_syscfg708 + } #[doc = "0x2c8 - STG SYSCONSAIF SYSCFG 712"] - pub stg_sysconsaif_syscfg712: STG_SYSCONSAIF_SYSCFG712, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg712(&self) -> &STG_SYSCONSAIF_SYSCFG712 { + &self.stg_sysconsaif_syscfg712 + } #[doc = "0x2cc - STG SYSCONSAIF SYSCFG 716"] - pub stg_sysconsaif_syscfg716: STG_SYSCONSAIF_SYSCFG716, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg716(&self) -> &STG_SYSCONSAIF_SYSCFG716 { + &self.stg_sysconsaif_syscfg716 + } #[doc = "0x2d0 - STG SYSCONSAIF SYSCFG 720"] - pub stg_sysconsaif_syscfg720: STG_SYSCONSAIF_SYSCFG720, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg720(&self) -> &STG_SYSCONSAIF_SYSCFG720 { + &self.stg_sysconsaif_syscfg720 + } #[doc = "0x2d4 - STG SYSCONSAIF SYSCFG 724"] - pub stg_sysconsaif_syscfg724: STG_SYSCONSAIF_SYSCFG724, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg724(&self) -> &STG_SYSCONSAIF_SYSCFG724 { + &self.stg_sysconsaif_syscfg724 + } #[doc = "0x2d8 - STG SYSCONSAIF SYSCFG 728"] - pub stg_sysconsaif_syscfg728: STG_SYSCONSAIF_SYSCFG728, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg728(&self) -> &STG_SYSCONSAIF_SYSCFG728 { + &self.stg_sysconsaif_syscfg728 + } #[doc = "0x2dc - STG SYSCONSAIF SYSCFG 732"] - pub stg_sysconsaif_syscfg732: STG_SYSCONSAIF_SYSCFG732, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg732(&self) -> &STG_SYSCONSAIF_SYSCFG732 { + &self.stg_sysconsaif_syscfg732 + } #[doc = "0x2e0 - STG SYSCONSAIF SYSCFG 736"] - pub stg_sysconsaif_syscfg736: STG_SYSCONSAIF_SYSCFG736, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg736(&self) -> &STG_SYSCONSAIF_SYSCFG736 { + &self.stg_sysconsaif_syscfg736 + } #[doc = "0x2e4 - STG SYSCONSAIF SYSCFG 740"] - pub stg_sysconsaif_syscfg740: STG_SYSCONSAIF_SYSCFG740, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg740(&self) -> &STG_SYSCONSAIF_SYSCFG740 { + &self.stg_sysconsaif_syscfg740 + } #[doc = "0x2e8 - STG SYSCONSAIF SYSCFG 744"] - pub stg_sysconsaif_syscfg744: STG_SYSCONSAIF_SYSCFG744, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg744(&self) -> &STG_SYSCONSAIF_SYSCFG744 { + &self.stg_sysconsaif_syscfg744 + } #[doc = "0x2ec - STG SYSCONSAIF SYSCFG 748"] - pub stg_sysconsaif_syscfg748: STG_SYSCONSAIF_SYSCFG748, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg748(&self) -> &STG_SYSCONSAIF_SYSCFG748 { + &self.stg_sysconsaif_syscfg748 + } #[doc = "0x2f0 - STG SYSCONSAIF SYSCFG 752"] - pub stg_sysconsaif_syscfg752: STG_SYSCONSAIF_SYSCFG752, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg752(&self) -> &STG_SYSCONSAIF_SYSCFG752 { + &self.stg_sysconsaif_syscfg752 + } #[doc = "0x2f4 - STG SYSCONSAIF SYSCFG 756"] - pub stg_sysconsaif_syscfg756: STG_SYSCONSAIF_SYSCFG756, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg756(&self) -> &STG_SYSCONSAIF_SYSCFG756 { + &self.stg_sysconsaif_syscfg756 + } #[doc = "0x2f8 - STG SYSCONSAIF SYSCFG 760"] - pub stg_sysconsaif_syscfg760: STG_SYSCONSAIF_SYSCFG760, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg760(&self) -> &STG_SYSCONSAIF_SYSCFG760 { + &self.stg_sysconsaif_syscfg760 + } #[doc = "0x2fc - STG SYSCONSAIF SYSCFG 764"] - pub stg_sysconsaif_syscfg764: STG_SYSCONSAIF_SYSCFG764, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg764(&self) -> &STG_SYSCONSAIF_SYSCFG764 { + &self.stg_sysconsaif_syscfg764 + } #[doc = "0x300 - STG SYSCONSAIF SYSCFG 768"] - pub stg_sysconsaif_syscfg768: STG_SYSCONSAIF_SYSCFG768, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg768(&self) -> &STG_SYSCONSAIF_SYSCFG768 { + &self.stg_sysconsaif_syscfg768 + } #[doc = "0x304 - STG SYSCONSAIF SYSCFG 772"] - pub stg_sysconsaif_syscfg772: STG_SYSCONSAIF_SYSCFG772, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg772(&self) -> &STG_SYSCONSAIF_SYSCFG772 { + &self.stg_sysconsaif_syscfg772 + } #[doc = "0x308 - STG SYSCONSAIF SYSCFG 776"] - pub stg_sysconsaif_syscfg776: STG_SYSCONSAIF_SYSCFG776, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg776(&self) -> &STG_SYSCONSAIF_SYSCFG776 { + &self.stg_sysconsaif_syscfg776 + } #[doc = "0x30c - STG SYSCONSAIF SYSCFG 780"] - pub stg_sysconsaif_syscfg780: STG_SYSCONSAIF_SYSCFG780, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg780(&self) -> &STG_SYSCONSAIF_SYSCFG780 { + &self.stg_sysconsaif_syscfg780 + } #[doc = "0x310 - STG SYSCONSAIF SYSCFG 784"] - pub stg_sysconsaif_syscfg784: STG_SYSCONSAIF_SYSCFG784, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg784(&self) -> &STG_SYSCONSAIF_SYSCFG784 { + &self.stg_sysconsaif_syscfg784 + } #[doc = "0x314 - STG SYSCONSAIF SYSCFG 788"] - pub stg_sysconsaif_syscfg788: STG_SYSCONSAIF_SYSCFG788, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg788(&self) -> &STG_SYSCONSAIF_SYSCFG788 { + &self.stg_sysconsaif_syscfg788 + } #[doc = "0x318 - STG SYSCONSAIF SYSCFG 792"] - pub stg_sysconsaif_syscfg792: STG_SYSCONSAIF_SYSCFG792, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg792(&self) -> &STG_SYSCONSAIF_SYSCFG792 { + &self.stg_sysconsaif_syscfg792 + } #[doc = "0x31c - STG SYSCONSAIF SYSCFG 796"] - pub stg_sysconsaif_syscfg796: STG_SYSCONSAIF_SYSCFG796, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg796(&self) -> &STG_SYSCONSAIF_SYSCFG796 { + &self.stg_sysconsaif_syscfg796 + } #[doc = "0x320 - STG SYSCONSAIF SYSCFG 800"] - pub stg_sysconsaif_syscfg800: STG_SYSCONSAIF_SYSCFG800, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg800(&self) -> &STG_SYSCONSAIF_SYSCFG800 { + &self.stg_sysconsaif_syscfg800 + } #[doc = "0x324 - STG SYSCONSAIF SYSCFG 804"] - pub stg_sysconsaif_syscfg804: STG_SYSCONSAIF_SYSCFG804, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg804(&self) -> &STG_SYSCONSAIF_SYSCFG804 { + &self.stg_sysconsaif_syscfg804 + } #[doc = "0x328 - STG SYSCONSAIF SYSCFG 808"] - pub stg_sysconsaif_syscfg808: STG_SYSCONSAIF_SYSCFG808, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg808(&self) -> &STG_SYSCONSAIF_SYSCFG808 { + &self.stg_sysconsaif_syscfg808 + } #[doc = "0x32c - STG SYSCONSAIF SYSCFG 812"] - pub stg_sysconsaif_syscfg812: STG_SYSCONSAIF_SYSCFG812, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg812(&self) -> &STG_SYSCONSAIF_SYSCFG812 { + &self.stg_sysconsaif_syscfg812 + } #[doc = "0x330 - STG SYSCONSAIF SYSCFG 816"] - pub stg_sysconsaif_syscfg816: STG_SYSCONSAIF_SYSCFG816, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg816(&self) -> &STG_SYSCONSAIF_SYSCFG816 { + &self.stg_sysconsaif_syscfg816 + } #[doc = "0x334 - STG SYSCONSAIF SYSCFG 820"] - pub stg_sysconsaif_syscfg820: STG_SYSCONSAIF_SYSCFG820, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg820(&self) -> &STG_SYSCONSAIF_SYSCFG820 { + &self.stg_sysconsaif_syscfg820 + } #[doc = "0x338 - STG SYSCONSAIF SYSCFG 824"] - pub stg_sysconsaif_syscfg824: STG_SYSCONSAIF_SYSCFG824, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg824(&self) -> &STG_SYSCONSAIF_SYSCFG824 { + &self.stg_sysconsaif_syscfg824 + } #[doc = "0x33c - STG SYSCONSAIF SYSCFG 828"] - pub stg_sysconsaif_syscfg828: STG_SYSCONSAIF_SYSCFG828, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg828(&self) -> &STG_SYSCONSAIF_SYSCFG828 { + &self.stg_sysconsaif_syscfg828 + } #[doc = "0x340 - STG SYSCONSAIF SYSCFG 832"] - pub stg_sysconsaif_syscfg832: STG_SYSCONSAIF_SYSCFG832, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg832(&self) -> &STG_SYSCONSAIF_SYSCFG832 { + &self.stg_sysconsaif_syscfg832 + } #[doc = "0x344 - STG SYSCONSAIF SYSCFG 836"] - pub stg_sysconsaif_syscfg836: STG_SYSCONSAIF_SYSCFG836, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg836(&self) -> &STG_SYSCONSAIF_SYSCFG836 { + &self.stg_sysconsaif_syscfg836 + } #[doc = "0x348 - STG SYSCONSAIF SYSCFG 840"] - pub stg_sysconsaif_syscfg840: STG_SYSCONSAIF_SYSCFG840, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg840(&self) -> &STG_SYSCONSAIF_SYSCFG840 { + &self.stg_sysconsaif_syscfg840 + } #[doc = "0x34c - STG SYSCONSAIF SYSCFG 844"] - pub stg_sysconsaif_syscfg844: STG_SYSCONSAIF_SYSCFG844, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg844(&self) -> &STG_SYSCONSAIF_SYSCFG844 { + &self.stg_sysconsaif_syscfg844 + } #[doc = "0x350 - STG SYSCONSAIF SYSCFG 848"] - pub stg_sysconsaif_syscfg848: STG_SYSCONSAIF_SYSCFG848, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg848(&self) -> &STG_SYSCONSAIF_SYSCFG848 { + &self.stg_sysconsaif_syscfg848 + } #[doc = "0x354 - STG SYSCONSAIF SYSCFG 852"] - pub stg_sysconsaif_syscfg852: STG_SYSCONSAIF_SYSCFG852, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg852(&self) -> &STG_SYSCONSAIF_SYSCFG852 { + &self.stg_sysconsaif_syscfg852 + } #[doc = "0x358 - STG SYSCONSAIF SYSCFG 856"] - pub stg_sysconsaif_syscfg856: STG_SYSCONSAIF_SYSCFG856, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg856(&self) -> &STG_SYSCONSAIF_SYSCFG856 { + &self.stg_sysconsaif_syscfg856 + } #[doc = "0x35c - STG SYSCONSAIF SYSCFG 860"] - pub stg_sysconsaif_syscfg860: STG_SYSCONSAIF_SYSCFG860, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg860(&self) -> &STG_SYSCONSAIF_SYSCFG860 { + &self.stg_sysconsaif_syscfg860 + } #[doc = "0x360 - STG SYSCONSAIF SYSCFG 864"] - pub stg_sysconsaif_syscfg864: STG_SYSCONSAIF_SYSCFG864, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg864(&self) -> &STG_SYSCONSAIF_SYSCFG864 { + &self.stg_sysconsaif_syscfg864 + } #[doc = "0x364 - STG SYSCONSAIF SYSCFG 868"] - pub stg_sysconsaif_syscfg868: STG_SYSCONSAIF_SYSCFG868, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg868(&self) -> &STG_SYSCONSAIF_SYSCFG868 { + &self.stg_sysconsaif_syscfg868 + } #[doc = "0x368 - STG SYSCONSAIF SYSCFG 872"] - pub stg_sysconsaif_syscfg872: STG_SYSCONSAIF_SYSCFG872, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg872(&self) -> &STG_SYSCONSAIF_SYSCFG872 { + &self.stg_sysconsaif_syscfg872 + } #[doc = "0x36c - STG SYSCONSAIF SYSCFG 876"] - pub stg_sysconsaif_syscfg876: STG_SYSCONSAIF_SYSCFG876, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg876(&self) -> &STG_SYSCONSAIF_SYSCFG876 { + &self.stg_sysconsaif_syscfg876 + } #[doc = "0x370 - STG SYSCONSAIF SYSCFG 880"] - pub stg_sysconsaif_syscfg880: STG_SYSCONSAIF_SYSCFG880, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg880(&self) -> &STG_SYSCONSAIF_SYSCFG880 { + &self.stg_sysconsaif_syscfg880 + } #[doc = "0x374 - STG SYSCONSAIF SYSCFG 884"] - pub stg_sysconsaif_syscfg884: STG_SYSCONSAIF_SYSCFG884, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg884(&self) -> &STG_SYSCONSAIF_SYSCFG884 { + &self.stg_sysconsaif_syscfg884 + } #[doc = "0x378 - STG SYSCONSAIF SYSCFG 888"] - pub stg_sysconsaif_syscfg888: STG_SYSCONSAIF_SYSCFG888, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg888(&self) -> &STG_SYSCONSAIF_SYSCFG888 { + &self.stg_sysconsaif_syscfg888 + } #[doc = "0x37c - STG SYSCONSAIF SYSCFG 892"] - pub stg_sysconsaif_syscfg892: STG_SYSCONSAIF_SYSCFG892, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg892(&self) -> &STG_SYSCONSAIF_SYSCFG892 { + &self.stg_sysconsaif_syscfg892 + } #[doc = "0x380 - STG SYSCONSAIF SYSCFG 896"] - pub stg_sysconsaif_syscfg896: STG_SYSCONSAIF_SYSCFG896, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg896(&self) -> &STG_SYSCONSAIF_SYSCFG896 { + &self.stg_sysconsaif_syscfg896 + } #[doc = "0x384 - STG SYSCONSAIF SYSCFG 900"] - pub stg_sysconsaif_syscfg900: STG_SYSCONSAIF_SYSCFG900, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg900(&self) -> &STG_SYSCONSAIF_SYSCFG900 { + &self.stg_sysconsaif_syscfg900 + } #[doc = "0x388 - STG SYSCONSAIF SYSCFG 904"] - pub stg_sysconsaif_syscfg904: STG_SYSCONSAIF_SYSCFG904, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg904(&self) -> &STG_SYSCONSAIF_SYSCFG904 { + &self.stg_sysconsaif_syscfg904 + } #[doc = "0x38c - STG SYSCONSAIF SYSCFG 908"] - pub stg_sysconsaif_syscfg908: STG_SYSCONSAIF_SYSCFG908, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg908(&self) -> &STG_SYSCONSAIF_SYSCFG908 { + &self.stg_sysconsaif_syscfg908 + } #[doc = "0x390 - STG SYSCONSAIF SYSCFG 912"] - pub stg_sysconsaif_syscfg912: STG_SYSCONSAIF_SYSCFG912, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg912(&self) -> &STG_SYSCONSAIF_SYSCFG912 { + &self.stg_sysconsaif_syscfg912 + } #[doc = "0x394 - STG SYSCONSAIF SYSCFG 916"] - pub stg_sysconsaif_syscfg916: STG_SYSCONSAIF_SYSCFG916, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg916(&self) -> &STG_SYSCONSAIF_SYSCFG916 { + &self.stg_sysconsaif_syscfg916 + } #[doc = "0x398 - STG SYSCONSAIF SYSCFG 920"] - pub stg_sysconsaif_syscfg920: STG_SYSCONSAIF_SYSCFG920, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg920(&self) -> &STG_SYSCONSAIF_SYSCFG920 { + &self.stg_sysconsaif_syscfg920 + } #[doc = "0x39c - STG SYSCONSAIF SYSCFG 924"] - pub stg_sysconsaif_syscfg924: STG_SYSCONSAIF_SYSCFG924, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg924(&self) -> &STG_SYSCONSAIF_SYSCFG924 { + &self.stg_sysconsaif_syscfg924 + } #[doc = "0x3a0 - STG SYSCONSAIF SYSCFG 928"] - pub stg_sysconsaif_syscfg928: STG_SYSCONSAIF_SYSCFG928, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg928(&self) -> &STG_SYSCONSAIF_SYSCFG928 { + &self.stg_sysconsaif_syscfg928 + } #[doc = "0x3a4 - STG SYSCONSAIF SYSCFG 932"] - pub stg_sysconsaif_syscfg932: STG_SYSCONSAIF_SYSCFG932, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg932(&self) -> &STG_SYSCONSAIF_SYSCFG932 { + &self.stg_sysconsaif_syscfg932 + } } -#[doc = "stg_sysconsaif_syscfg0 (rw) register accessor: STG SYSCONSAIF SYSCFG 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg0`] +#[doc = "stg_sysconsaif_syscfg0 (rw) register accessor: STG SYSCONSAIF SYSCFG 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg0`] module"] pub type STG_SYSCONSAIF_SYSCFG0 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 0"] pub mod stg_sysconsaif_syscfg0; -#[doc = "stg_sysconsaif_syscfg4 (rw) register accessor: STG SYSCONSAIF SYSCFG 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg4`] +#[doc = "stg_sysconsaif_syscfg4 (rw) register accessor: STG SYSCONSAIF SYSCFG 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg4`] module"] pub type STG_SYSCONSAIF_SYSCFG4 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 4"] pub mod stg_sysconsaif_syscfg4; -#[doc = "stg_sysconsaif_syscfg8 (rw) register accessor: STG SYSCONSAIF SYSCFG 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg8`] +#[doc = "stg_sysconsaif_syscfg8 (rw) register accessor: STG SYSCONSAIF SYSCFG 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg8`] module"] pub type STG_SYSCONSAIF_SYSCFG8 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 8"] pub mod stg_sysconsaif_syscfg8; -#[doc = "stg_sysconsaif_syscfg12 (rw) register accessor: STG SYSCONSAIF SYSCFG 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg12::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg12`] +#[doc = "stg_sysconsaif_syscfg12 (rw) register accessor: STG SYSCONSAIF SYSCFG 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg12::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg12`] module"] pub type STG_SYSCONSAIF_SYSCFG12 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 12"] pub mod stg_sysconsaif_syscfg12; -#[doc = "stg_sysconsaif_syscfg16 (rw) register accessor: STG SYSCONSAIF SYSCFG 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg16::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg16`] +#[doc = "stg_sysconsaif_syscfg16 (rw) register accessor: STG SYSCONSAIF SYSCFG 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg16::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg16`] module"] pub type STG_SYSCONSAIF_SYSCFG16 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 16"] pub mod stg_sysconsaif_syscfg16; -#[doc = "stg_sysconsaif_syscfg20 (rw) register accessor: STG SYSCONSAIF SYSCFG 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg20::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg20`] +#[doc = "stg_sysconsaif_syscfg20 (rw) register accessor: STG SYSCONSAIF SYSCFG 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg20::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg20`] module"] pub type STG_SYSCONSAIF_SYSCFG20 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 20"] pub mod stg_sysconsaif_syscfg20; -#[doc = "stg_sysconsaif_syscfg24 (rw) register accessor: STG SYSCONSAIF SYSCFG 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg24::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg24`] +#[doc = "stg_sysconsaif_syscfg24 (rw) register accessor: STG SYSCONSAIF SYSCFG 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg24::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg24`] module"] pub type STG_SYSCONSAIF_SYSCFG24 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 24"] pub mod stg_sysconsaif_syscfg24; -#[doc = "stg_sysconsaif_syscfg28 (rw) register accessor: STG SYSCONSAIF SYSCFG 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg28::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg28`] +#[doc = "stg_sysconsaif_syscfg28 (rw) register accessor: STG SYSCONSAIF SYSCFG 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg28::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg28`] module"] pub type STG_SYSCONSAIF_SYSCFG28 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 28"] pub mod stg_sysconsaif_syscfg28; -#[doc = "stg_sysconsaif_syscfg32 (rw) register accessor: STG SYSCONSAIF SYSCFG 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg32::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg32`] +#[doc = "stg_sysconsaif_syscfg32 (rw) register accessor: STG SYSCONSAIF SYSCFG 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg32::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg32`] module"] pub type STG_SYSCONSAIF_SYSCFG32 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 32"] pub mod stg_sysconsaif_syscfg32; -#[doc = "stg_sysconsaif_syscfg36 (rw) register accessor: STG SYSCONSAIF SYSCFG 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg36::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg36`] +#[doc = "stg_sysconsaif_syscfg36 (rw) register accessor: STG SYSCONSAIF SYSCFG 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg36::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg36`] module"] pub type STG_SYSCONSAIF_SYSCFG36 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 36"] pub mod stg_sysconsaif_syscfg36; -#[doc = "stg_sysconsaif_syscfg40 (rw) register accessor: STG SYSCONSAIF SYSCFG 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg40::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg40`] +#[doc = "stg_sysconsaif_syscfg40 (rw) register accessor: STG SYSCONSAIF SYSCFG 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg40::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg40`] module"] pub type STG_SYSCONSAIF_SYSCFG40 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 40"] pub mod stg_sysconsaif_syscfg40; -#[doc = "stg_sysconsaif_syscfg44 (rw) register accessor: STG SYSCONSAIF SYSCFG 44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg44::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg44`] +#[doc = "stg_sysconsaif_syscfg44 (rw) register accessor: STG SYSCONSAIF SYSCFG 44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg44::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg44`] module"] pub type STG_SYSCONSAIF_SYSCFG44 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 44"] pub mod stg_sysconsaif_syscfg44; -#[doc = "stg_sysconsaif_syscfg48 (rw) register accessor: STG SYSCONSAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg48`] +#[doc = "stg_sysconsaif_syscfg48 (rw) register accessor: STG SYSCONSAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg48`] module"] pub type STG_SYSCONSAIF_SYSCFG48 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 48"] pub mod stg_sysconsaif_syscfg48; -#[doc = "stg_sysconsaif_syscfg52 (rw) register accessor: STG SYSCONSAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg52`] +#[doc = "stg_sysconsaif_syscfg52 (rw) register accessor: STG SYSCONSAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg52`] module"] pub type STG_SYSCONSAIF_SYSCFG52 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 52"] pub mod stg_sysconsaif_syscfg52; -#[doc = "stg_sysconsaif_syscfg56 (rw) register accessor: STG SYSCONSAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg56`] +#[doc = "stg_sysconsaif_syscfg56 (rw) register accessor: STG SYSCONSAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg56`] module"] pub type STG_SYSCONSAIF_SYSCFG56 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 56"] pub mod stg_sysconsaif_syscfg56; -#[doc = "stg_sysconsaif_syscfg60 (rw) register accessor: STG SYSCONSAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg60`] +#[doc = "stg_sysconsaif_syscfg60 (rw) register accessor: STG SYSCONSAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg60`] module"] pub type STG_SYSCONSAIF_SYSCFG60 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 60"] pub mod stg_sysconsaif_syscfg60; -#[doc = "stg_sysconsaif_syscfg64 (rw) register accessor: STG SYSCONSAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg64`] +#[doc = "stg_sysconsaif_syscfg64 (rw) register accessor: STG SYSCONSAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg64`] module"] pub type STG_SYSCONSAIF_SYSCFG64 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 64"] pub mod stg_sysconsaif_syscfg64; -#[doc = "stg_sysconsaif_syscfg68 (rw) register accessor: STG SYSCONSAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg68`] +#[doc = "stg_sysconsaif_syscfg68 (rw) register accessor: STG SYSCONSAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg68`] module"] pub type STG_SYSCONSAIF_SYSCFG68 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 68"] pub mod stg_sysconsaif_syscfg68; -#[doc = "stg_sysconsaif_syscfg72 (rw) register accessor: STG SYSCONSAIF SYSCFG 72\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg72::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg72::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg72`] +#[doc = "stg_sysconsaif_syscfg72 (rw) register accessor: STG SYSCONSAIF SYSCFG 72\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg72::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg72::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg72`] module"] pub type STG_SYSCONSAIF_SYSCFG72 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 72"] pub mod stg_sysconsaif_syscfg72; -#[doc = "stg_sysconsaif_syscfg76 (rw) register accessor: STG SYSCONSAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg76`] +#[doc = "stg_sysconsaif_syscfg76 (rw) register accessor: STG SYSCONSAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg76`] module"] pub type STG_SYSCONSAIF_SYSCFG76 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 76"] pub mod stg_sysconsaif_syscfg76; -#[doc = "stg_sysconsaif_syscfg80 (rw) register accessor: STG SYSCONSAIF SYSCFG 80\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg80::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg80::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg80`] +#[doc = "stg_sysconsaif_syscfg80 (rw) register accessor: STG SYSCONSAIF SYSCFG 80\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg80::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg80::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg80`] module"] pub type STG_SYSCONSAIF_SYSCFG80 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 80"] pub mod stg_sysconsaif_syscfg80; -#[doc = "stg_sysconsaif_syscfg84 (rw) register accessor: STG SYSCONSAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg84`] +#[doc = "stg_sysconsaif_syscfg84 (rw) register accessor: STG SYSCONSAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg84`] module"] pub type STG_SYSCONSAIF_SYSCFG84 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 84"] pub mod stg_sysconsaif_syscfg84; -#[doc = "stg_sysconsaif_syscfg88 (rw) register accessor: STG SYSCONSAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg88`] +#[doc = "stg_sysconsaif_syscfg88 (rw) register accessor: STG SYSCONSAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg88`] module"] pub type STG_SYSCONSAIF_SYSCFG88 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 88"] pub mod stg_sysconsaif_syscfg88; -#[doc = "stg_sysconsaif_syscfg92 (rw) register accessor: STG SYSCONSAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg92`] +#[doc = "stg_sysconsaif_syscfg92 (rw) register accessor: STG SYSCONSAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg92`] module"] pub type STG_SYSCONSAIF_SYSCFG92 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 92"] pub mod stg_sysconsaif_syscfg92; -#[doc = "stg_sysconsaif_syscfg96 (rw) register accessor: STG SYSCONSAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg96`] +#[doc = "stg_sysconsaif_syscfg96 (rw) register accessor: STG SYSCONSAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg96`] module"] pub type STG_SYSCONSAIF_SYSCFG96 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 96"] pub mod stg_sysconsaif_syscfg96; -#[doc = "stg_sysconsaif_syscfg100 (rw) register accessor: STG SYSCONSAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg100`] +#[doc = "stg_sysconsaif_syscfg100 (rw) register accessor: STG SYSCONSAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg100`] module"] pub type STG_SYSCONSAIF_SYSCFG100 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 100"] pub mod stg_sysconsaif_syscfg100; -#[doc = "stg_sysconsaif_syscfg104 (rw) register accessor: STG SYSCONSAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg104`] +#[doc = "stg_sysconsaif_syscfg104 (rw) register accessor: STG SYSCONSAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg104`] module"] pub type STG_SYSCONSAIF_SYSCFG104 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 104"] pub mod stg_sysconsaif_syscfg104; -#[doc = "stg_sysconsaif_syscfg108 (rw) register accessor: STG SYSCONSAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg108`] +#[doc = "stg_sysconsaif_syscfg108 (rw) register accessor: STG SYSCONSAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg108`] module"] pub type STG_SYSCONSAIF_SYSCFG108 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 108"] pub mod stg_sysconsaif_syscfg108; -#[doc = "stg_sysconsaif_syscfg112 (rw) register accessor: STG SYSCONSAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg112`] +#[doc = "stg_sysconsaif_syscfg112 (rw) register accessor: STG SYSCONSAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg112`] module"] pub type STG_SYSCONSAIF_SYSCFG112 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 112"] pub mod stg_sysconsaif_syscfg112; -#[doc = "stg_sysconsaif_syscfg116 (rw) register accessor: STG SYSCONSAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg116`] +#[doc = "stg_sysconsaif_syscfg116 (rw) register accessor: STG SYSCONSAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg116`] module"] pub type STG_SYSCONSAIF_SYSCFG116 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 116"] pub mod stg_sysconsaif_syscfg116; -#[doc = "stg_sysconsaif_syscfg120 (rw) register accessor: STG SYSCONSAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg120`] +#[doc = "stg_sysconsaif_syscfg120 (rw) register accessor: STG SYSCONSAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg120`] module"] pub type STG_SYSCONSAIF_SYSCFG120 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 120"] pub mod stg_sysconsaif_syscfg120; -#[doc = "stg_sysconsaif_syscfg124 (rw) register accessor: STG SYSCONSAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg124`] +#[doc = "stg_sysconsaif_syscfg124 (rw) register accessor: STG SYSCONSAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg124`] module"] pub type STG_SYSCONSAIF_SYSCFG124 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 124"] pub mod stg_sysconsaif_syscfg124; -#[doc = "stg_sysconsaif_syscfg128 (rw) register accessor: STG SYSCONSAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg128`] +#[doc = "stg_sysconsaif_syscfg128 (rw) register accessor: STG SYSCONSAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg128`] module"] pub type STG_SYSCONSAIF_SYSCFG128 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 128"] pub mod stg_sysconsaif_syscfg128; -#[doc = "stg_sysconsaif_syscfg132 (rw) register accessor: STG SYSCONSAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg132::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg132::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg132`] +#[doc = "stg_sysconsaif_syscfg132 (rw) register accessor: STG SYSCONSAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg132::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg132::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg132`] module"] pub type STG_SYSCONSAIF_SYSCFG132 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 132"] pub mod stg_sysconsaif_syscfg132; -#[doc = "stg_sysconsaif_syscfg136 (rw) register accessor: STG SYSCONSAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg136`] +#[doc = "stg_sysconsaif_syscfg136 (rw) register accessor: STG SYSCONSAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg136`] module"] pub type STG_SYSCONSAIF_SYSCFG136 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 136"] pub mod stg_sysconsaif_syscfg136; -#[doc = "stg_sysconsaif_syscfg140 (rw) register accessor: STG SYSCONSAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg140::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg140::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg140`] +#[doc = "stg_sysconsaif_syscfg140 (rw) register accessor: STG SYSCONSAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg140::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg140::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg140`] module"] pub type STG_SYSCONSAIF_SYSCFG140 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 140"] pub mod stg_sysconsaif_syscfg140; -#[doc = "stg_sysconsaif_syscfg144 (rw) register accessor: STG SYSCONSAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg144::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg144::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg144`] +#[doc = "stg_sysconsaif_syscfg144 (rw) register accessor: STG SYSCONSAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg144::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg144::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg144`] module"] pub type STG_SYSCONSAIF_SYSCFG144 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 144"] pub mod stg_sysconsaif_syscfg144; -#[doc = "stg_sysconsaif_syscfg148 (rw) register accessor: STG SYSCONSAIF SYSCFG 148\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg148::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg148::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg148`] +#[doc = "stg_sysconsaif_syscfg148 (rw) register accessor: STG SYSCONSAIF SYSCFG 148\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg148::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg148::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg148`] module"] pub type STG_SYSCONSAIF_SYSCFG148 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 148"] pub mod stg_sysconsaif_syscfg148; -#[doc = "stg_sysconsaif_syscfg152 (rw) register accessor: STG SYSCONSAIF SYSCFG 152\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg152::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg152::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg152`] +#[doc = "stg_sysconsaif_syscfg152 (rw) register accessor: STG SYSCONSAIF SYSCFG 152\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg152::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg152::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg152`] module"] pub type STG_SYSCONSAIF_SYSCFG152 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 152"] pub mod stg_sysconsaif_syscfg152; -#[doc = "stg_sysconsaif_syscfg156 (rw) register accessor: STG SYSCONSAIF SYSCFG 156\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg156::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg156::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg156`] +#[doc = "stg_sysconsaif_syscfg156 (rw) register accessor: STG SYSCONSAIF SYSCFG 156\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg156::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg156::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg156`] module"] pub type STG_SYSCONSAIF_SYSCFG156 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 156"] pub mod stg_sysconsaif_syscfg156; -#[doc = "stg_sysconsaif_syscfg160 (rw) register accessor: STG SYSCONSAIF SYSCFG 160\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg160::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg160::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg160`] +#[doc = "stg_sysconsaif_syscfg160 (rw) register accessor: STG SYSCONSAIF SYSCFG 160\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg160::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg160::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg160`] module"] pub type STG_SYSCONSAIF_SYSCFG160 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 160"] pub mod stg_sysconsaif_syscfg160; -#[doc = "stg_sysconsaif_syscfg164 (rw) register accessor: STG SYSCONSAIF SYSCFG 164\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg164::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg164::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg164`] +#[doc = "stg_sysconsaif_syscfg164 (rw) register accessor: STG SYSCONSAIF SYSCFG 164\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg164::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg164::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg164`] module"] pub type STG_SYSCONSAIF_SYSCFG164 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 164"] pub mod stg_sysconsaif_syscfg164; -#[doc = "stg_sysconsaif_syscfg168 (rw) register accessor: STG SYSCONSAIF SYSCFG 168\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg168::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg168::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg168`] +#[doc = "stg_sysconsaif_syscfg168 (rw) register accessor: STG SYSCONSAIF SYSCFG 168\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg168::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg168::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg168`] module"] pub type STG_SYSCONSAIF_SYSCFG168 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 168"] pub mod stg_sysconsaif_syscfg168; -#[doc = "stg_sysconsaif_syscfg172 (rw) register accessor: STG SYSCONSAIF SYSCFG 172\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg172::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg172::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg172`] +#[doc = "stg_sysconsaif_syscfg172 (rw) register accessor: STG SYSCONSAIF SYSCFG 172\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg172::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg172::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg172`] module"] pub type STG_SYSCONSAIF_SYSCFG172 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 172"] pub mod stg_sysconsaif_syscfg172; -#[doc = "stg_sysconsaif_syscfg176 (rw) register accessor: STG SYSCONSAIF SYSCFG 176\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg176::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg176::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg176`] +#[doc = "stg_sysconsaif_syscfg176 (rw) register accessor: STG SYSCONSAIF SYSCFG 176\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg176::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg176::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg176`] module"] pub type STG_SYSCONSAIF_SYSCFG176 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 176"] pub mod stg_sysconsaif_syscfg176; -#[doc = "stg_sysconsaif_syscfg180 (rw) register accessor: STG SYSCONSAIF SYSCFG 180\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg180::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg180::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg180`] +#[doc = "stg_sysconsaif_syscfg180 (rw) register accessor: STG SYSCONSAIF SYSCFG 180\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg180::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg180::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg180`] module"] pub type STG_SYSCONSAIF_SYSCFG180 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 180"] pub mod stg_sysconsaif_syscfg180; -#[doc = "stg_sysconsaif_syscfg184 (rw) register accessor: STG SYSCONSAIF SYSCFG 184\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg184::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg184::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg184`] +#[doc = "stg_sysconsaif_syscfg184 (rw) register accessor: STG SYSCONSAIF SYSCFG 184\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg184::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg184::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg184`] module"] pub type STG_SYSCONSAIF_SYSCFG184 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 184"] pub mod stg_sysconsaif_syscfg184; -#[doc = "stg_sysconsaif_syscfg188 (rw) register accessor: STG SYSCONSAIF SYSCFG 188\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg188::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg188::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg188`] +#[doc = "stg_sysconsaif_syscfg188 (rw) register accessor: STG SYSCONSAIF SYSCFG 188\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg188::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg188::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg188`] module"] pub type STG_SYSCONSAIF_SYSCFG188 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 188"] pub mod stg_sysconsaif_syscfg188; -#[doc = "stg_sysconsaif_syscfg192 (rw) register accessor: STG SYSCONSAIF SYSCFG 192\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg192::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg192::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg192`] +#[doc = "stg_sysconsaif_syscfg192 (rw) register accessor: STG SYSCONSAIF SYSCFG 192\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg192::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg192::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg192`] module"] pub type STG_SYSCONSAIF_SYSCFG192 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 192"] pub mod stg_sysconsaif_syscfg192; -#[doc = "stg_sysconsaif_syscfg196 (rw) register accessor: STG SYSCONSAIF SYSCFG 196\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg196::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg196::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg196`] +#[doc = "stg_sysconsaif_syscfg196 (rw) register accessor: STG SYSCONSAIF SYSCFG 196\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg196::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg196::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg196`] module"] pub type STG_SYSCONSAIF_SYSCFG196 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 196"] pub mod stg_sysconsaif_syscfg196; -#[doc = "stg_sysconsaif_syscfg200 (rw) register accessor: STG SYSCONSAIF SYSCFG 200\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg200::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg200::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg200`] +#[doc = "stg_sysconsaif_syscfg200 (rw) register accessor: STG SYSCONSAIF SYSCFG 200\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg200::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg200::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg200`] module"] pub type STG_SYSCONSAIF_SYSCFG200 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 200"] pub mod stg_sysconsaif_syscfg200; -#[doc = "stg_sysconsaif_syscfg204 (rw) register accessor: STG SYSCONSAIF SYSCFG 204\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg204::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg204::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg204`] +#[doc = "stg_sysconsaif_syscfg204 (rw) register accessor: STG SYSCONSAIF SYSCFG 204\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg204::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg204::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg204`] module"] pub type STG_SYSCONSAIF_SYSCFG204 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 204"] pub mod stg_sysconsaif_syscfg204; -#[doc = "stg_sysconsaif_syscfg208 (rw) register accessor: STG SYSCONSAIF SYSCFG 208\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg208::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg208::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg208`] +#[doc = "stg_sysconsaif_syscfg208 (rw) register accessor: STG SYSCONSAIF SYSCFG 208\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg208::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg208::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg208`] module"] pub type STG_SYSCONSAIF_SYSCFG208 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 208"] pub mod stg_sysconsaif_syscfg208; -#[doc = "stg_sysconsaif_syscfg212 (rw) register accessor: STG SYSCONSAIF SYSCFG 212\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg212::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg212::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg212`] +#[doc = "stg_sysconsaif_syscfg212 (rw) register accessor: STG SYSCONSAIF SYSCFG 212\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg212::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg212::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg212`] module"] pub type STG_SYSCONSAIF_SYSCFG212 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 212"] pub mod stg_sysconsaif_syscfg212; -#[doc = "stg_sysconsaif_syscfg216 (rw) register accessor: STG SYSCONSAIF SYSCFG 216\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg216::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg216::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg216`] +#[doc = "stg_sysconsaif_syscfg216 (rw) register accessor: STG SYSCONSAIF SYSCFG 216\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg216::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg216::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg216`] module"] pub type STG_SYSCONSAIF_SYSCFG216 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 216"] pub mod stg_sysconsaif_syscfg216; -#[doc = "stg_sysconsaif_syscfg220 (rw) register accessor: STG SYSCONSAIF SYSCFG 220\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg220::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg220::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg220`] +#[doc = "stg_sysconsaif_syscfg220 (rw) register accessor: STG SYSCONSAIF SYSCFG 220\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg220::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg220::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg220`] module"] pub type STG_SYSCONSAIF_SYSCFG220 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 220"] pub mod stg_sysconsaif_syscfg220; -#[doc = "stg_sysconsaif_syscfg224 (rw) register accessor: STG SYSCONSAIF SYSCFG 224\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg224::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg224::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg224`] +#[doc = "stg_sysconsaif_syscfg224 (rw) register accessor: STG SYSCONSAIF SYSCFG 224\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg224::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg224::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg224`] module"] pub type STG_SYSCONSAIF_SYSCFG224 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 224"] pub mod stg_sysconsaif_syscfg224; -#[doc = "stg_sysconsaif_syscfg228 (rw) register accessor: STG SYSCONSAIF SYSCFG 228\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg228::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg228::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg228`] +#[doc = "stg_sysconsaif_syscfg228 (rw) register accessor: STG SYSCONSAIF SYSCFG 228\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg228::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg228::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg228`] module"] pub type STG_SYSCONSAIF_SYSCFG228 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 228"] pub mod stg_sysconsaif_syscfg228; -#[doc = "stg_sysconsaif_syscfg232 (rw) register accessor: STG SYSCONSAIF SYSCFG 232\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg232::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg232::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg232`] +#[doc = "stg_sysconsaif_syscfg232 (rw) register accessor: STG SYSCONSAIF SYSCFG 232\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg232::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg232::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg232`] module"] pub type STG_SYSCONSAIF_SYSCFG232 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 232"] pub mod stg_sysconsaif_syscfg232; -#[doc = "stg_sysconsaif_syscfg236 (rw) register accessor: STG SYSCONSAIF SYSCFG 236\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg236::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg236::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg236`] +#[doc = "stg_sysconsaif_syscfg236 (rw) register accessor: STG SYSCONSAIF SYSCFG 236\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg236::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg236::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg236`] module"] pub type STG_SYSCONSAIF_SYSCFG236 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 236"] pub mod stg_sysconsaif_syscfg236; -#[doc = "stg_sysconsaif_syscfg240 (rw) register accessor: STG SYSCONSAIF SYSCFG 240\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg240::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg240::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg240`] +#[doc = "stg_sysconsaif_syscfg240 (rw) register accessor: STG SYSCONSAIF SYSCFG 240\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg240::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg240::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg240`] module"] pub type STG_SYSCONSAIF_SYSCFG240 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 240"] pub mod stg_sysconsaif_syscfg240; -#[doc = "stg_sysconsaif_syscfg244 (rw) register accessor: STG SYSCONSAIF SYSCFG 244\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg244::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg244::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg244`] +#[doc = "stg_sysconsaif_syscfg244 (rw) register accessor: STG SYSCONSAIF SYSCFG 244\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg244::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg244::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg244`] module"] pub type STG_SYSCONSAIF_SYSCFG244 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 244"] pub mod stg_sysconsaif_syscfg244; -#[doc = "stg_sysconsaif_syscfg248 (rw) register accessor: STG SYSCONSAIF SYSCFG 248\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg248::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg248::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg248`] +#[doc = "stg_sysconsaif_syscfg248 (rw) register accessor: STG SYSCONSAIF SYSCFG 248\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg248::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg248::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg248`] module"] pub type STG_SYSCONSAIF_SYSCFG248 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 248"] pub mod stg_sysconsaif_syscfg248; -#[doc = "stg_sysconsaif_syscfg252 (rw) register accessor: STG SYSCONSAIF SYSCFG 252\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg252::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg252::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg252`] +#[doc = "stg_sysconsaif_syscfg252 (rw) register accessor: STG SYSCONSAIF SYSCFG 252\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg252::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg252::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg252`] module"] pub type STG_SYSCONSAIF_SYSCFG252 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 252"] pub mod stg_sysconsaif_syscfg252; -#[doc = "stg_sysconsaif_syscfg256 (rw) register accessor: STG SYSCONSAIF SYSCFG 256\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg256::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg256::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg256`] +#[doc = "stg_sysconsaif_syscfg256 (rw) register accessor: STG SYSCONSAIF SYSCFG 256\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg256::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg256::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg256`] module"] pub type STG_SYSCONSAIF_SYSCFG256 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 256"] pub mod stg_sysconsaif_syscfg256; -#[doc = "stg_sysconsaif_syscfg260 (rw) register accessor: STG SYSCONSAIF SYSCFG 260\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg260::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg260::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg260`] +#[doc = "stg_sysconsaif_syscfg260 (rw) register accessor: STG SYSCONSAIF SYSCFG 260\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg260::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg260::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg260`] module"] pub type STG_SYSCONSAIF_SYSCFG260 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 260"] pub mod stg_sysconsaif_syscfg260; -#[doc = "stg_sysconsaif_syscfg264 (rw) register accessor: STG SYSCONSAIF SYSCFG 264\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg264::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg264::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg264`] +#[doc = "stg_sysconsaif_syscfg264 (rw) register accessor: STG SYSCONSAIF SYSCFG 264\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg264::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg264::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg264`] module"] pub type STG_SYSCONSAIF_SYSCFG264 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 264"] pub mod stg_sysconsaif_syscfg264; -#[doc = "stg_sysconsaif_syscfg268 (rw) register accessor: STG SYSCONSAIF SYSCFG 268\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg268::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg268::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg268`] +#[doc = "stg_sysconsaif_syscfg268 (rw) register accessor: STG SYSCONSAIF SYSCFG 268\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg268::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg268::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg268`] module"] pub type STG_SYSCONSAIF_SYSCFG268 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 268"] pub mod stg_sysconsaif_syscfg268; -#[doc = "stg_sysconsaif_syscfg272 (rw) register accessor: STG SYSCONSAIF SYSCFG 272\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg272::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg272::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg272`] +#[doc = "stg_sysconsaif_syscfg272 (rw) register accessor: STG SYSCONSAIF SYSCFG 272\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg272::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg272::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg272`] module"] pub type STG_SYSCONSAIF_SYSCFG272 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 272"] pub mod stg_sysconsaif_syscfg272; -#[doc = "stg_sysconsaif_syscfg276 (rw) register accessor: STG SYSCONSAIF SYSCFG 276\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg276::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg276::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg276`] +#[doc = "stg_sysconsaif_syscfg276 (rw) register accessor: STG SYSCONSAIF SYSCFG 276\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg276::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg276::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg276`] module"] pub type STG_SYSCONSAIF_SYSCFG276 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 276"] pub mod stg_sysconsaif_syscfg276; -#[doc = "stg_sysconsaif_syscfg280 (rw) register accessor: STG SYSCONSAIF SYSCFG 280\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg280::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg280::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg280`] +#[doc = "stg_sysconsaif_syscfg280 (rw) register accessor: STG SYSCONSAIF SYSCFG 280\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg280::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg280::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg280`] module"] pub type STG_SYSCONSAIF_SYSCFG280 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 280"] pub mod stg_sysconsaif_syscfg280; -#[doc = "stg_sysconsaif_syscfg284 (rw) register accessor: STG SYSCONSAIF SYSCFG 284\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg284::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg284::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg284`] +#[doc = "stg_sysconsaif_syscfg284 (rw) register accessor: STG SYSCONSAIF SYSCFG 284\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg284::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg284::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg284`] module"] pub type STG_SYSCONSAIF_SYSCFG284 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 284"] pub mod stg_sysconsaif_syscfg284; -#[doc = "stg_sysconsaif_syscfg288 (rw) register accessor: STG SYSCONSAIF SYSCFG 288\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg288::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg288::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg288`] +#[doc = "stg_sysconsaif_syscfg288 (rw) register accessor: STG SYSCONSAIF SYSCFG 288\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg288::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg288::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg288`] module"] pub type STG_SYSCONSAIF_SYSCFG288 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 288"] pub mod stg_sysconsaif_syscfg288; -#[doc = "stg_sysconsaif_syscfg292 (rw) register accessor: STG SYSCONSAIF SYSCFG 292\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg292::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg292::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg292`] +#[doc = "stg_sysconsaif_syscfg292 (rw) register accessor: STG SYSCONSAIF SYSCFG 292\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg292::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg292::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg292`] module"] pub type STG_SYSCONSAIF_SYSCFG292 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 292"] pub mod stg_sysconsaif_syscfg292; -#[doc = "stg_sysconsaif_syscfg296 (rw) register accessor: STG SYSCONSAIF SYSCFG 296\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg296::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg296::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg296`] +#[doc = "stg_sysconsaif_syscfg296 (rw) register accessor: STG SYSCONSAIF SYSCFG 296\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg296::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg296::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg296`] module"] pub type STG_SYSCONSAIF_SYSCFG296 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 296"] pub mod stg_sysconsaif_syscfg296; -#[doc = "stg_sysconsaif_syscfg300 (rw) register accessor: STG SYSCONSAIF SYSCFG 300\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg300::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg300::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg300`] +#[doc = "stg_sysconsaif_syscfg300 (rw) register accessor: STG SYSCONSAIF SYSCFG 300\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg300::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg300::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg300`] module"] pub type STG_SYSCONSAIF_SYSCFG300 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 300"] pub mod stg_sysconsaif_syscfg300; -#[doc = "stg_sysconsaif_syscfg304 (rw) register accessor: STG SYSCONSAIF SYSCFG 304\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg304::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg304::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg304`] +#[doc = "stg_sysconsaif_syscfg304 (rw) register accessor: STG SYSCONSAIF SYSCFG 304\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg304::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg304::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg304`] module"] pub type STG_SYSCONSAIF_SYSCFG304 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 304"] pub mod stg_sysconsaif_syscfg304; -#[doc = "stg_sysconsaif_syscfg308 (rw) register accessor: STG SYSCONSAIF SYSCFG 308\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg308::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg308::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg308`] +#[doc = "stg_sysconsaif_syscfg308 (rw) register accessor: STG SYSCONSAIF SYSCFG 308\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg308::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg308::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg308`] module"] pub type STG_SYSCONSAIF_SYSCFG308 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 308"] pub mod stg_sysconsaif_syscfg308; -#[doc = "stg_sysconsaif_syscfg312 (rw) register accessor: STG SYSCONSAIF SYSCFG 312\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg312::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg312::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg312`] +#[doc = "stg_sysconsaif_syscfg312 (rw) register accessor: STG SYSCONSAIF SYSCFG 312\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg312::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg312::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg312`] module"] pub type STG_SYSCONSAIF_SYSCFG312 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 312"] pub mod stg_sysconsaif_syscfg312; -#[doc = "stg_sysconsaif_syscfg316 (rw) register accessor: STG SYSCONSAIF SYSCFG 316\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg316::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg316::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg316`] +#[doc = "stg_sysconsaif_syscfg316 (rw) register accessor: STG SYSCONSAIF SYSCFG 316\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg316::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg316::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg316`] module"] pub type STG_SYSCONSAIF_SYSCFG316 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 316"] pub mod stg_sysconsaif_syscfg316; -#[doc = "stg_sysconsaif_syscfg320 (rw) register accessor: STG SYSCONSAIF SYSCFG 320\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg320::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg320::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg320`] +#[doc = "stg_sysconsaif_syscfg320 (rw) register accessor: STG SYSCONSAIF SYSCFG 320\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg320::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg320::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg320`] module"] pub type STG_SYSCONSAIF_SYSCFG320 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 320"] pub mod stg_sysconsaif_syscfg320; -#[doc = "stg_sysconsaif_syscfg324 (rw) register accessor: STG SYSCONSAIF SYSCFG 324\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg324::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg324::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg324`] +#[doc = "stg_sysconsaif_syscfg324 (rw) register accessor: STG SYSCONSAIF SYSCFG 324\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg324::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg324::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg324`] module"] pub type STG_SYSCONSAIF_SYSCFG324 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 324"] pub mod stg_sysconsaif_syscfg324; -#[doc = "stg_sysconsaif_syscfg328 (rw) register accessor: STG SYSCONSAIF SYSCFG 328\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg328::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg328::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg328`] +#[doc = "stg_sysconsaif_syscfg328 (rw) register accessor: STG SYSCONSAIF SYSCFG 328\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg328::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg328::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg328`] module"] pub type STG_SYSCONSAIF_SYSCFG328 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 328"] pub mod stg_sysconsaif_syscfg328; -#[doc = "stg_sysconsaif_syscfg332 (rw) register accessor: STG SYSCONSAIF SYSCFG 332\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg332::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg332::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg332`] +#[doc = "stg_sysconsaif_syscfg332 (rw) register accessor: STG SYSCONSAIF SYSCFG 332\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg332::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg332::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg332`] module"] pub type STG_SYSCONSAIF_SYSCFG332 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 332"] pub mod stg_sysconsaif_syscfg332; -#[doc = "stg_sysconsaif_syscfg336 (rw) register accessor: STG SYSCONSAIF SYSCFG 336\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg336::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg336::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg336`] +#[doc = "stg_sysconsaif_syscfg336 (rw) register accessor: STG SYSCONSAIF SYSCFG 336\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg336::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg336::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg336`] module"] pub type STG_SYSCONSAIF_SYSCFG336 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 336"] pub mod stg_sysconsaif_syscfg336; -#[doc = "stg_sysconsaif_syscfg340 (rw) register accessor: STG SYSCONSAIF SYSCFG 340\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg340::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg340::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg340`] +#[doc = "stg_sysconsaif_syscfg340 (rw) register accessor: STG SYSCONSAIF SYSCFG 340\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg340::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg340::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg340`] module"] pub type STG_SYSCONSAIF_SYSCFG340 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 340"] pub mod stg_sysconsaif_syscfg340; -#[doc = "stg_sysconsaif_syscfg344 (rw) register accessor: STG SYSCONSAIF SYSCFG 344\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg344::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg344::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg344`] +#[doc = "stg_sysconsaif_syscfg344 (rw) register accessor: STG SYSCONSAIF SYSCFG 344\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg344::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg344::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg344`] module"] pub type STG_SYSCONSAIF_SYSCFG344 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 344"] pub mod stg_sysconsaif_syscfg344; -#[doc = "stg_sysconsaif_syscfg348 (rw) register accessor: STG SYSCONSAIF SYSCFG 348\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg348::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg348::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg348`] +#[doc = "stg_sysconsaif_syscfg348 (rw) register accessor: STG SYSCONSAIF SYSCFG 348\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg348::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg348::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg348`] module"] pub type STG_SYSCONSAIF_SYSCFG348 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 348"] pub mod stg_sysconsaif_syscfg348; -#[doc = "stg_sysconsaif_syscfg352 (rw) register accessor: STG SYSCONSAIF SYSCFG 352\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg352::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg352::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg352`] +#[doc = "stg_sysconsaif_syscfg352 (rw) register accessor: STG SYSCONSAIF SYSCFG 352\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg352::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg352::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg352`] module"] pub type STG_SYSCONSAIF_SYSCFG352 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 352"] pub mod stg_sysconsaif_syscfg352; -#[doc = "stg_sysconsaif_syscfg356 (rw) register accessor: STG SYSCONSAIF SYSCFG 356\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg356::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg356::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg356`] +#[doc = "stg_sysconsaif_syscfg356 (rw) register accessor: STG SYSCONSAIF SYSCFG 356\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg356::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg356::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg356`] module"] pub type STG_SYSCONSAIF_SYSCFG356 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 356"] pub mod stg_sysconsaif_syscfg356; -#[doc = "stg_sysconsaif_syscfg360 (rw) register accessor: STG SYSCONSAIF SYSCFG 360\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg360::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg360::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg360`] +#[doc = "stg_sysconsaif_syscfg360 (rw) register accessor: STG SYSCONSAIF SYSCFG 360\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg360::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg360::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg360`] module"] pub type STG_SYSCONSAIF_SYSCFG360 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 360"] pub mod stg_sysconsaif_syscfg360; -#[doc = "stg_sysconsaif_syscfg364 (rw) register accessor: STG SYSCONSAIF SYSCFG 364\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg364::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg364::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg364`] +#[doc = "stg_sysconsaif_syscfg364 (rw) register accessor: STG SYSCONSAIF SYSCFG 364\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg364::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg364::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg364`] module"] pub type STG_SYSCONSAIF_SYSCFG364 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 364"] pub mod stg_sysconsaif_syscfg364; -#[doc = "stg_sysconsaif_syscfg368 (rw) register accessor: STG SYSCONSAIF SYSCFG 368\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg368::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg368::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg368`] +#[doc = "stg_sysconsaif_syscfg368 (rw) register accessor: STG SYSCONSAIF SYSCFG 368\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg368::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg368::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg368`] module"] pub type STG_SYSCONSAIF_SYSCFG368 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 368"] pub mod stg_sysconsaif_syscfg368; -#[doc = "stg_sysconsaif_syscfg372 (rw) register accessor: STG SYSCONSAIF SYSCFG 372\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg372::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg372::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg372`] +#[doc = "stg_sysconsaif_syscfg372 (rw) register accessor: STG SYSCONSAIF SYSCFG 372\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg372::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg372::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg372`] module"] pub type STG_SYSCONSAIF_SYSCFG372 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 372"] pub mod stg_sysconsaif_syscfg372; -#[doc = "stg_sysconsaif_syscfg376 (rw) register accessor: STG SYSCONSAIF SYSCFG 376\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg376::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg376::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg376`] +#[doc = "stg_sysconsaif_syscfg376 (rw) register accessor: STG SYSCONSAIF SYSCFG 376\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg376::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg376::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg376`] module"] pub type STG_SYSCONSAIF_SYSCFG376 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 376"] pub mod stg_sysconsaif_syscfg376; -#[doc = "stg_sysconsaif_syscfg380 (rw) register accessor: STG SYSCONSAIF SYSCFG 380\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg380::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg380::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg380`] +#[doc = "stg_sysconsaif_syscfg380 (rw) register accessor: STG SYSCONSAIF SYSCFG 380\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg380::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg380::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg380`] module"] pub type STG_SYSCONSAIF_SYSCFG380 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 380"] pub mod stg_sysconsaif_syscfg380; -#[doc = "stg_sysconsaif_syscfg384 (rw) register accessor: STG SYSCONSAIF SYSCFG 384\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg384::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg384::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg384`] +#[doc = "stg_sysconsaif_syscfg384 (rw) register accessor: STG SYSCONSAIF SYSCFG 384\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg384::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg384::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg384`] module"] pub type STG_SYSCONSAIF_SYSCFG384 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 384"] pub mod stg_sysconsaif_syscfg384; -#[doc = "stg_sysconsaif_syscfg388 (rw) register accessor: STG SYSCONSAIF SYSCFG 388\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg388::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg388::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg388`] +#[doc = "stg_sysconsaif_syscfg388 (rw) register accessor: STG SYSCONSAIF SYSCFG 388\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg388::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg388::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg388`] module"] pub type STG_SYSCONSAIF_SYSCFG388 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 388"] pub mod stg_sysconsaif_syscfg388; -#[doc = "stg_sysconsaif_syscfg392 (rw) register accessor: STG SYSCONSAIF SYSCFG 392\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg392::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg392::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg392`] +#[doc = "stg_sysconsaif_syscfg392 (rw) register accessor: STG SYSCONSAIF SYSCFG 392\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg392::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg392::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg392`] module"] pub type STG_SYSCONSAIF_SYSCFG392 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 392"] pub mod stg_sysconsaif_syscfg392; -#[doc = "stg_sysconsaif_syscfg396 (rw) register accessor: STG SYSCONSAIF SYSCFG 396\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg396::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg396::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg396`] +#[doc = "stg_sysconsaif_syscfg396 (rw) register accessor: STG SYSCONSAIF SYSCFG 396\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg396::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg396::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg396`] module"] pub type STG_SYSCONSAIF_SYSCFG396 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 396"] pub mod stg_sysconsaif_syscfg396; -#[doc = "stg_sysconsaif_syscfg400 (rw) register accessor: STG SYSCONSAIF SYSCFG 400\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg400::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg400::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg400`] +#[doc = "stg_sysconsaif_syscfg400 (rw) register accessor: STG SYSCONSAIF SYSCFG 400\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg400::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg400::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg400`] module"] pub type STG_SYSCONSAIF_SYSCFG400 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 400"] pub mod stg_sysconsaif_syscfg400; -#[doc = "stg_sysconsaif_syscfg404 (rw) register accessor: STG SYSCONSAIF SYSCFG 404\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg404::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg404::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg404`] +#[doc = "stg_sysconsaif_syscfg404 (rw) register accessor: STG SYSCONSAIF SYSCFG 404\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg404::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg404::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg404`] module"] pub type STG_SYSCONSAIF_SYSCFG404 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 404"] pub mod stg_sysconsaif_syscfg404; -#[doc = "stg_sysconsaif_syscfg408 (rw) register accessor: STG SYSCONSAIF SYSCFG 408\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg408::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg408::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg408`] +#[doc = "stg_sysconsaif_syscfg408 (rw) register accessor: STG SYSCONSAIF SYSCFG 408\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg408::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg408::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg408`] module"] pub type STG_SYSCONSAIF_SYSCFG408 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 408"] pub mod stg_sysconsaif_syscfg408; -#[doc = "stg_sysconsaif_syscfg412 (rw) register accessor: STG SYSCONSAIF SYSCFG 412\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg412::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg412::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg412`] +#[doc = "stg_sysconsaif_syscfg412 (rw) register accessor: STG SYSCONSAIF SYSCFG 412\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg412::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg412::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg412`] module"] pub type STG_SYSCONSAIF_SYSCFG412 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 412"] pub mod stg_sysconsaif_syscfg412; -#[doc = "stg_sysconsaif_syscfg416 (rw) register accessor: STG SYSCONSAIF SYSCFG 416\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg416::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg416::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg416`] +#[doc = "stg_sysconsaif_syscfg416 (rw) register accessor: STG SYSCONSAIF SYSCFG 416\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg416::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg416::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg416`] module"] pub type STG_SYSCONSAIF_SYSCFG416 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 416"] pub mod stg_sysconsaif_syscfg416; -#[doc = "stg_sysconsaif_syscfg420 (rw) register accessor: STG SYSCONSAIF SYSCFG 420\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg420::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg420::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg420`] +#[doc = "stg_sysconsaif_syscfg420 (rw) register accessor: STG SYSCONSAIF SYSCFG 420\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg420::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg420::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg420`] module"] pub type STG_SYSCONSAIF_SYSCFG420 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 420"] pub mod stg_sysconsaif_syscfg420; -#[doc = "stg_sysconsaif_syscfg424 (rw) register accessor: STG SYSCONSAIF SYSCFG 424\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg424::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg424::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg424`] +#[doc = "stg_sysconsaif_syscfg424 (rw) register accessor: STG SYSCONSAIF SYSCFG 424\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg424::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg424::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg424`] module"] pub type STG_SYSCONSAIF_SYSCFG424 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 424"] pub mod stg_sysconsaif_syscfg424; -#[doc = "stg_sysconsaif_syscfg428 (rw) register accessor: STG SYSCONSAIF SYSCFG 428\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg428::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg428::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg428`] +#[doc = "stg_sysconsaif_syscfg428 (rw) register accessor: STG SYSCONSAIF SYSCFG 428\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg428::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg428::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg428`] module"] pub type STG_SYSCONSAIF_SYSCFG428 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 428"] pub mod stg_sysconsaif_syscfg428; -#[doc = "stg_sysconsaif_syscfg432 (rw) register accessor: STG SYSCONSAIF SYSCFG 432\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg432::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg432::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg432`] +#[doc = "stg_sysconsaif_syscfg432 (rw) register accessor: STG SYSCONSAIF SYSCFG 432\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg432::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg432::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg432`] module"] pub type STG_SYSCONSAIF_SYSCFG432 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 432"] pub mod stg_sysconsaif_syscfg432; -#[doc = "stg_sysconsaif_syscfg436 (rw) register accessor: STG SYSCONSAIF SYSCFG 436\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg436::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg436::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg436`] +#[doc = "stg_sysconsaif_syscfg436 (rw) register accessor: STG SYSCONSAIF SYSCFG 436\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg436::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg436::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg436`] module"] pub type STG_SYSCONSAIF_SYSCFG436 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 436"] pub mod stg_sysconsaif_syscfg436; -#[doc = "stg_sysconsaif_syscfg440 (rw) register accessor: STG SYSCONSAIF SYSCFG 440\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg440::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg440::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg440`] +#[doc = "stg_sysconsaif_syscfg440 (rw) register accessor: STG SYSCONSAIF SYSCFG 440\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg440::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg440::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg440`] module"] pub type STG_SYSCONSAIF_SYSCFG440 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 440"] pub mod stg_sysconsaif_syscfg440; -#[doc = "stg_sysconsaif_syscfg444 (rw) register accessor: STG SYSCONSAIF SYSCFG 444\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg444::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg444::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg444`] +#[doc = "stg_sysconsaif_syscfg444 (rw) register accessor: STG SYSCONSAIF SYSCFG 444\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg444::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg444::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg444`] module"] pub type STG_SYSCONSAIF_SYSCFG444 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 444"] pub mod stg_sysconsaif_syscfg444; -#[doc = "stg_sysconsaif_syscfg448 (rw) register accessor: STG SYSCONSAIF SYSCFG 448\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg448::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg448::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg448`] +#[doc = "stg_sysconsaif_syscfg448 (rw) register accessor: STG SYSCONSAIF SYSCFG 448\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg448::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg448::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg448`] module"] pub type STG_SYSCONSAIF_SYSCFG448 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 448"] pub mod stg_sysconsaif_syscfg448; -#[doc = "stg_sysconsaif_syscfg452 (rw) register accessor: STG SYSCONSAIF SYSCFG 452\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg452::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg452::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg452`] +#[doc = "stg_sysconsaif_syscfg452 (rw) register accessor: STG SYSCONSAIF SYSCFG 452\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg452::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg452::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg452`] module"] pub type STG_SYSCONSAIF_SYSCFG452 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 452"] pub mod stg_sysconsaif_syscfg452; -#[doc = "stg_sysconsaif_syscfg456 (rw) register accessor: STG SYSCONSAIF SYSCFG 456\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg456::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg456::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg456`] +#[doc = "stg_sysconsaif_syscfg456 (rw) register accessor: STG SYSCONSAIF SYSCFG 456\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg456::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg456::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg456`] module"] pub type STG_SYSCONSAIF_SYSCFG456 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 456"] pub mod stg_sysconsaif_syscfg456; -#[doc = "stg_sysconsaif_syscfg460 (rw) register accessor: STG SYSCONSAIF SYSCFG 460\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg460::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg460::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg460`] +#[doc = "stg_sysconsaif_syscfg460 (rw) register accessor: STG SYSCONSAIF SYSCFG 460\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg460::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg460::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg460`] module"] pub type STG_SYSCONSAIF_SYSCFG460 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 460"] pub mod stg_sysconsaif_syscfg460; -#[doc = "stg_sysconsaif_syscfg464 (rw) register accessor: STG SYSCONSAIF SYSCFG 464\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg464::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg464::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg464`] +#[doc = "stg_sysconsaif_syscfg464 (rw) register accessor: STG SYSCONSAIF SYSCFG 464\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg464::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg464::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg464`] module"] pub type STG_SYSCONSAIF_SYSCFG464 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 464"] pub mod stg_sysconsaif_syscfg464; -#[doc = "stg_sysconsaif_syscfg468 (rw) register accessor: STG SYSCONSAIF SYSCFG 468\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg468::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg468::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg468`] +#[doc = "stg_sysconsaif_syscfg468 (rw) register accessor: STG SYSCONSAIF SYSCFG 468\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg468::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg468::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg468`] module"] pub type STG_SYSCONSAIF_SYSCFG468 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 468"] pub mod stg_sysconsaif_syscfg468; -#[doc = "stg_sysconsaif_syscfg472 (rw) register accessor: STG SYSCONSAIF SYSCFG 472\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg472::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg472::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg472`] +#[doc = "stg_sysconsaif_syscfg472 (rw) register accessor: STG SYSCONSAIF SYSCFG 472\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg472::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg472::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg472`] module"] pub type STG_SYSCONSAIF_SYSCFG472 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 472"] pub mod stg_sysconsaif_syscfg472; -#[doc = "stg_sysconsaif_syscfg476 (rw) register accessor: STG SYSCONSAIF SYSCFG 476\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg476::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg476::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg476`] +#[doc = "stg_sysconsaif_syscfg476 (rw) register accessor: STG SYSCONSAIF SYSCFG 476\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg476::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg476::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg476`] module"] pub type STG_SYSCONSAIF_SYSCFG476 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 476"] pub mod stg_sysconsaif_syscfg476; -#[doc = "stg_sysconsaif_syscfg480 (rw) register accessor: STG SYSCONSAIF SYSCFG 480\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg480::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg480::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg480`] +#[doc = "stg_sysconsaif_syscfg480 (rw) register accessor: STG SYSCONSAIF SYSCFG 480\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg480::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg480::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg480`] module"] pub type STG_SYSCONSAIF_SYSCFG480 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 480"] pub mod stg_sysconsaif_syscfg480; -#[doc = "stg_sysconsaif_syscfg484 (rw) register accessor: STG SYSCONSAIF SYSCFG 484\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg484::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg484::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg484`] +#[doc = "stg_sysconsaif_syscfg484 (rw) register accessor: STG SYSCONSAIF SYSCFG 484\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg484::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg484::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg484`] module"] pub type STG_SYSCONSAIF_SYSCFG484 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 484"] pub mod stg_sysconsaif_syscfg484; -#[doc = "stg_sysconsaif_syscfg488 (rw) register accessor: STG SYSCONSAIF SYSCFG 488\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg488::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg488::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg488`] +#[doc = "stg_sysconsaif_syscfg488 (rw) register accessor: STG SYSCONSAIF SYSCFG 488\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg488::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg488::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg488`] module"] pub type STG_SYSCONSAIF_SYSCFG488 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 488"] pub mod stg_sysconsaif_syscfg488; -#[doc = "stg_sysconsaif_syscfg492 (rw) register accessor: STG SYSCONSAIF SYSCFG 492\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg492::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg492::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg492`] +#[doc = "stg_sysconsaif_syscfg492 (rw) register accessor: STG SYSCONSAIF SYSCFG 492\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg492::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg492::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg492`] module"] pub type STG_SYSCONSAIF_SYSCFG492 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 492"] pub mod stg_sysconsaif_syscfg492; -#[doc = "stg_sysconsaif_syscfg500 (rw) register accessor: STG SYSCONSAIF SYSCFG 500\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg500::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg500::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg500`] +#[doc = "stg_sysconsaif_syscfg500 (rw) register accessor: STG SYSCONSAIF SYSCFG 500\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg500::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg500::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg500`] module"] pub type STG_SYSCONSAIF_SYSCFG500 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 500"] pub mod stg_sysconsaif_syscfg500; -#[doc = "stg_sysconsaif_syscfg504 (rw) register accessor: STG SYSCONSAIF SYSCFG 504\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg504::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg504::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg504`] +#[doc = "stg_sysconsaif_syscfg504 (rw) register accessor: STG SYSCONSAIF SYSCFG 504\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg504::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg504::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg504`] module"] pub type STG_SYSCONSAIF_SYSCFG504 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 504"] pub mod stg_sysconsaif_syscfg504; -#[doc = "stg_sysconsaif_syscfg508 (rw) register accessor: STG SYSCONSAIF SYSCFG 508\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg508::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg508::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg508`] +#[doc = "stg_sysconsaif_syscfg508 (rw) register accessor: STG SYSCONSAIF SYSCFG 508\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg508::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg508::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg508`] module"] pub type STG_SYSCONSAIF_SYSCFG508 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 508"] pub mod stg_sysconsaif_syscfg508; -#[doc = "stg_sysconsaif_syscfg512 (rw) register accessor: STG SYSCONSAIF SYSCFG 512\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg512::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg512::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg512`] +#[doc = "stg_sysconsaif_syscfg512 (rw) register accessor: STG SYSCONSAIF SYSCFG 512\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg512::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg512::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg512`] module"] pub type STG_SYSCONSAIF_SYSCFG512 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 512"] pub mod stg_sysconsaif_syscfg512; -#[doc = "stg_sysconsaif_syscfg516 (rw) register accessor: STG SYSCONSAIF SYSCFG 516\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg516::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg516::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg516`] +#[doc = "stg_sysconsaif_syscfg516 (rw) register accessor: STG SYSCONSAIF SYSCFG 516\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg516::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg516::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg516`] module"] pub type STG_SYSCONSAIF_SYSCFG516 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 516"] pub mod stg_sysconsaif_syscfg516; -#[doc = "stg_sysconsaif_syscfg520 (rw) register accessor: STG SYSCONSAIF SYSCFG 520\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg520::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg520::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg520`] +#[doc = "stg_sysconsaif_syscfg520 (rw) register accessor: STG SYSCONSAIF SYSCFG 520\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg520::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg520::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg520`] module"] pub type STG_SYSCONSAIF_SYSCFG520 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 520"] pub mod stg_sysconsaif_syscfg520; -#[doc = "stg_sysconsaif_syscfg524 (rw) register accessor: STG SYSCONSAIF SYSCFG 524\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg524::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg524::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg524`] +#[doc = "stg_sysconsaif_syscfg524 (rw) register accessor: STG SYSCONSAIF SYSCFG 524\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg524::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg524::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg524`] module"] pub type STG_SYSCONSAIF_SYSCFG524 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 524"] pub mod stg_sysconsaif_syscfg524; -#[doc = "stg_sysconsaif_syscfg528 (rw) register accessor: STG SYSCONSAIF SYSCFG 528\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg528::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg528::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg528`] +#[doc = "stg_sysconsaif_syscfg528 (rw) register accessor: STG SYSCONSAIF SYSCFG 528\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg528::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg528::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg528`] module"] pub type STG_SYSCONSAIF_SYSCFG528 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 528"] pub mod stg_sysconsaif_syscfg528; -#[doc = "stg_sysconsaif_syscfg532 (rw) register accessor: STG SYSCONSAIF SYSCFG 532\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg532::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg532::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg532`] +#[doc = "stg_sysconsaif_syscfg532 (rw) register accessor: STG SYSCONSAIF SYSCFG 532\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg532::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg532::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg532`] module"] pub type STG_SYSCONSAIF_SYSCFG532 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 532"] pub mod stg_sysconsaif_syscfg532; -#[doc = "stg_sysconsaif_syscfg536 (rw) register accessor: STG SYSCONSAIF SYSCFG 536\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg536::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg536::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg536`] +#[doc = "stg_sysconsaif_syscfg536 (rw) register accessor: STG SYSCONSAIF SYSCFG 536\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg536::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg536::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg536`] module"] pub type STG_SYSCONSAIF_SYSCFG536 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 536"] pub mod stg_sysconsaif_syscfg536; -#[doc = "stg_sysconsaif_syscfg540 (rw) register accessor: STG SYSCONSAIF SYSCFG 540\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg540::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg540::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg540`] +#[doc = "stg_sysconsaif_syscfg540 (rw) register accessor: STG SYSCONSAIF SYSCFG 540\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg540::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg540::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg540`] module"] pub type STG_SYSCONSAIF_SYSCFG540 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 540"] pub mod stg_sysconsaif_syscfg540; -#[doc = "stg_sysconsaif_syscfg544 (rw) register accessor: STG SYSCONSAIF SYSCFG 544\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg544::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg544::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg544`] +#[doc = "stg_sysconsaif_syscfg544 (rw) register accessor: STG SYSCONSAIF SYSCFG 544\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg544::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg544::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg544`] module"] pub type STG_SYSCONSAIF_SYSCFG544 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 544"] pub mod stg_sysconsaif_syscfg544; -#[doc = "stg_sysconsaif_syscfg548 (rw) register accessor: STG SYSCONSAIF SYSCFG 548\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg548::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg548::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg548`] +#[doc = "stg_sysconsaif_syscfg548 (rw) register accessor: STG SYSCONSAIF SYSCFG 548\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg548::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg548::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg548`] module"] pub type STG_SYSCONSAIF_SYSCFG548 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 548"] pub mod stg_sysconsaif_syscfg548; -#[doc = "stg_sysconsaif_syscfg552 (rw) register accessor: STG SYSCONSAIF SYSCFG 552\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg552::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg552::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg552`] +#[doc = "stg_sysconsaif_syscfg552 (rw) register accessor: STG SYSCONSAIF SYSCFG 552\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg552::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg552::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg552`] module"] pub type STG_SYSCONSAIF_SYSCFG552 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 552"] pub mod stg_sysconsaif_syscfg552; -#[doc = "stg_sysconsaif_syscfg556 (rw) register accessor: STG SYSCONSAIF SYSCFG 556\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg556::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg556::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg556`] +#[doc = "stg_sysconsaif_syscfg556 (rw) register accessor: STG SYSCONSAIF SYSCFG 556\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg556::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg556::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg556`] module"] pub type STG_SYSCONSAIF_SYSCFG556 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 556"] pub mod stg_sysconsaif_syscfg556; -#[doc = "stg_sysconsaif_syscfg560 (rw) register accessor: STG SYSCONSAIF SYSCFG 560\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg560::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg560::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg560`] +#[doc = "stg_sysconsaif_syscfg560 (rw) register accessor: STG SYSCONSAIF SYSCFG 560\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg560::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg560::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg560`] module"] pub type STG_SYSCONSAIF_SYSCFG560 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 560"] pub mod stg_sysconsaif_syscfg560; -#[doc = "stg_sysconsaif_syscfg564 (rw) register accessor: STG SYSCONSAIF SYSCFG 564\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg564::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg564::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg564`] +#[doc = "stg_sysconsaif_syscfg564 (rw) register accessor: STG SYSCONSAIF SYSCFG 564\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg564::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg564::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg564`] module"] pub type STG_SYSCONSAIF_SYSCFG564 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 564"] pub mod stg_sysconsaif_syscfg564; -#[doc = "stg_sysconsaif_syscfg568 (rw) register accessor: STG SYSCONSAIF SYSCFG 568\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg568::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg568::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg568`] +#[doc = "stg_sysconsaif_syscfg568 (rw) register accessor: STG SYSCONSAIF SYSCFG 568\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg568::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg568::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg568`] module"] pub type STG_SYSCONSAIF_SYSCFG568 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 568"] pub mod stg_sysconsaif_syscfg568; -#[doc = "stg_sysconsaif_syscfg572 (rw) register accessor: STG SYSCONSAIF SYSCFG 572\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg572::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg572::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg572`] +#[doc = "stg_sysconsaif_syscfg572 (rw) register accessor: STG SYSCONSAIF SYSCFG 572\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg572::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg572::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg572`] module"] pub type STG_SYSCONSAIF_SYSCFG572 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 572"] pub mod stg_sysconsaif_syscfg572; -#[doc = "stg_sysconsaif_syscfg576 (rw) register accessor: STG SYSCONSAIF SYSCFG 576\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg576::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg576::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg576`] +#[doc = "stg_sysconsaif_syscfg576 (rw) register accessor: STG SYSCONSAIF SYSCFG 576\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg576::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg576::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg576`] module"] pub type STG_SYSCONSAIF_SYSCFG576 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 576"] pub mod stg_sysconsaif_syscfg576; -#[doc = "stg_sysconsaif_syscfg580 (rw) register accessor: STG SYSCONSAIF SYSCFG 580\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg580::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg580::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg580`] +#[doc = "stg_sysconsaif_syscfg580 (rw) register accessor: STG SYSCONSAIF SYSCFG 580\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg580::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg580::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg580`] module"] pub type STG_SYSCONSAIF_SYSCFG580 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 580"] pub mod stg_sysconsaif_syscfg580; -#[doc = "stg_sysconsaif_syscfg584 (rw) register accessor: STG SYSCONSAIF SYSCFG 584\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg584::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg584::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg584`] +#[doc = "stg_sysconsaif_syscfg584 (rw) register accessor: STG SYSCONSAIF SYSCFG 584\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg584::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg584::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg584`] module"] pub type STG_SYSCONSAIF_SYSCFG584 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 584"] pub mod stg_sysconsaif_syscfg584; -#[doc = "stg_sysconsaif_syscfg588 (rw) register accessor: STG SYSCONSAIF SYSCFG 588\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg588::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg588::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg588`] +#[doc = "stg_sysconsaif_syscfg588 (rw) register accessor: STG SYSCONSAIF SYSCFG 588\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg588::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg588::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg588`] module"] pub type STG_SYSCONSAIF_SYSCFG588 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 588"] pub mod stg_sysconsaif_syscfg588; -#[doc = "stg_sysconsaif_syscfg592 (rw) register accessor: STG SYSCONSAIF SYSCFG 592\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg592::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg592::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg592`] +#[doc = "stg_sysconsaif_syscfg592 (rw) register accessor: STG SYSCONSAIF SYSCFG 592\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg592::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg592::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg592`] module"] pub type STG_SYSCONSAIF_SYSCFG592 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 592"] pub mod stg_sysconsaif_syscfg592; -#[doc = "stg_sysconsaif_syscfg596 (rw) register accessor: STG SYSCONSAIF SYSCFG 596\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg596::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg596::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg596`] +#[doc = "stg_sysconsaif_syscfg596 (rw) register accessor: STG SYSCONSAIF SYSCFG 596\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg596::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg596::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg596`] module"] pub type STG_SYSCONSAIF_SYSCFG596 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 596"] pub mod stg_sysconsaif_syscfg596; -#[doc = "stg_sysconsaif_syscfg600 (rw) register accessor: STG SYSCONSAIF SYSCFG 600\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg600::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg600::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg600`] +#[doc = "stg_sysconsaif_syscfg600 (rw) register accessor: STG SYSCONSAIF SYSCFG 600\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg600::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg600::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg600`] module"] pub type STG_SYSCONSAIF_SYSCFG600 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 600"] pub mod stg_sysconsaif_syscfg600; -#[doc = "stg_sysconsaif_syscfg604 (rw) register accessor: STG SYSCONSAIF SYSCFG 604\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg604::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg604::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg604`] +#[doc = "stg_sysconsaif_syscfg604 (rw) register accessor: STG SYSCONSAIF SYSCFG 604\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg604::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg604::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg604`] module"] pub type STG_SYSCONSAIF_SYSCFG604 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 604"] pub mod stg_sysconsaif_syscfg604; -#[doc = "stg_sysconsaif_syscfg608 (rw) register accessor: STG SYSCONSAIF SYSCFG 608\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg608::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg608::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg608`] +#[doc = "stg_sysconsaif_syscfg608 (rw) register accessor: STG SYSCONSAIF SYSCFG 608\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg608::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg608::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg608`] module"] pub type STG_SYSCONSAIF_SYSCFG608 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 608"] pub mod stg_sysconsaif_syscfg608; -#[doc = "stg_sysconsaif_syscfg612 (rw) register accessor: STG SYSCONSAIF SYSCFG 612\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg612::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg612::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg612`] +#[doc = "stg_sysconsaif_syscfg612 (rw) register accessor: STG SYSCONSAIF SYSCFG 612\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg612::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg612::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg612`] module"] pub type STG_SYSCONSAIF_SYSCFG612 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 612"] pub mod stg_sysconsaif_syscfg612; -#[doc = "stg_sysconsaif_syscfg616 (rw) register accessor: STG SYSCONSAIF SYSCFG 616\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg616::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg616::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg616`] +#[doc = "stg_sysconsaif_syscfg616 (rw) register accessor: STG SYSCONSAIF SYSCFG 616\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg616::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg616::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg616`] module"] pub type STG_SYSCONSAIF_SYSCFG616 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 616"] pub mod stg_sysconsaif_syscfg616; -#[doc = "stg_sysconsaif_syscfg620 (rw) register accessor: STG SYSCONSAIF SYSCFG 620\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg620::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg620::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg620`] +#[doc = "stg_sysconsaif_syscfg620 (rw) register accessor: STG SYSCONSAIF SYSCFG 620\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg620::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg620::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg620`] module"] pub type STG_SYSCONSAIF_SYSCFG620 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 620"] pub mod stg_sysconsaif_syscfg620; -#[doc = "stg_sysconsaif_syscfg624 (rw) register accessor: STG SYSCONSAIF SYSCFG 624\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg624::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg624::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg624`] +#[doc = "stg_sysconsaif_syscfg624 (rw) register accessor: STG SYSCONSAIF SYSCFG 624\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg624::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg624::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg624`] module"] pub type STG_SYSCONSAIF_SYSCFG624 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 624"] pub mod stg_sysconsaif_syscfg624; -#[doc = "stg_sysconsaif_syscfg628 (rw) register accessor: STG SYSCONSAIF SYSCFG 628\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg628::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg628::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg628`] +#[doc = "stg_sysconsaif_syscfg628 (rw) register accessor: STG SYSCONSAIF SYSCFG 628\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg628::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg628::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg628`] module"] pub type STG_SYSCONSAIF_SYSCFG628 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 628"] pub mod stg_sysconsaif_syscfg628; -#[doc = "stg_sysconsaif_syscfg632 (rw) register accessor: STG SYSCONSAIF SYSCFG 632\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg632::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg632::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg632`] +#[doc = "stg_sysconsaif_syscfg632 (rw) register accessor: STG SYSCONSAIF SYSCFG 632\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg632::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg632::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg632`] module"] pub type STG_SYSCONSAIF_SYSCFG632 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 632"] pub mod stg_sysconsaif_syscfg632; -#[doc = "stg_sysconsaif_syscfg636 (rw) register accessor: STG SYSCONSAIF SYSCFG 636\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg636::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg636::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg636`] +#[doc = "stg_sysconsaif_syscfg636 (rw) register accessor: STG SYSCONSAIF SYSCFG 636\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg636::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg636::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg636`] module"] pub type STG_SYSCONSAIF_SYSCFG636 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 636"] pub mod stg_sysconsaif_syscfg636; -#[doc = "stg_sysconsaif_syscfg640 (rw) register accessor: STG SYSCONSAIF SYSCFG 640\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg640::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg640::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg640`] +#[doc = "stg_sysconsaif_syscfg640 (rw) register accessor: STG SYSCONSAIF SYSCFG 640\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg640::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg640::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg640`] module"] pub type STG_SYSCONSAIF_SYSCFG640 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 640"] pub mod stg_sysconsaif_syscfg640; -#[doc = "stg_sysconsaif_syscfg644 (rw) register accessor: STG SYSCONSAIF SYSCFG 644\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg644::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg644::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg644`] +#[doc = "stg_sysconsaif_syscfg644 (rw) register accessor: STG SYSCONSAIF SYSCFG 644\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg644::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg644::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg644`] module"] pub type STG_SYSCONSAIF_SYSCFG644 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 644"] pub mod stg_sysconsaif_syscfg644; -#[doc = "stg_sysconsaif_syscfg648 (rw) register accessor: STG SYSCONSAIF SYSCFG 648\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg648::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg648::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg648`] +#[doc = "stg_sysconsaif_syscfg648 (rw) register accessor: STG SYSCONSAIF SYSCFG 648\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg648::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg648::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg648`] module"] pub type STG_SYSCONSAIF_SYSCFG648 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 648"] pub mod stg_sysconsaif_syscfg648; -#[doc = "stg_sysconsaif_syscfg652 (rw) register accessor: STG SYSCONSAIF SYSCFG 652\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg652::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg652::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg652`] +#[doc = "stg_sysconsaif_syscfg652 (rw) register accessor: STG SYSCONSAIF SYSCFG 652\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg652::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg652::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg652`] module"] pub type STG_SYSCONSAIF_SYSCFG652 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 652"] pub mod stg_sysconsaif_syscfg652; -#[doc = "stg_sysconsaif_syscfg656 (rw) register accessor: STG SYSCONSAIF SYSCFG 656\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg656::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg656::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg656`] +#[doc = "stg_sysconsaif_syscfg656 (rw) register accessor: STG SYSCONSAIF SYSCFG 656\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg656::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg656::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg656`] module"] pub type STG_SYSCONSAIF_SYSCFG656 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 656"] pub mod stg_sysconsaif_syscfg656; -#[doc = "stg_sysconsaif_syscfg660 (rw) register accessor: STG SYSCONSAIF SYSCFG 660\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg660::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg660::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg660`] +#[doc = "stg_sysconsaif_syscfg660 (rw) register accessor: STG SYSCONSAIF SYSCFG 660\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg660::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg660::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg660`] module"] pub type STG_SYSCONSAIF_SYSCFG660 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 660"] pub mod stg_sysconsaif_syscfg660; -#[doc = "stg_sysconsaif_syscfg664 (rw) register accessor: STG SYSCONSAIF SYSCFG 664\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg664::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg664::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg664`] +#[doc = "stg_sysconsaif_syscfg664 (rw) register accessor: STG SYSCONSAIF SYSCFG 664\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg664::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg664::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg664`] module"] pub type STG_SYSCONSAIF_SYSCFG664 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 664"] pub mod stg_sysconsaif_syscfg664; -#[doc = "stg_sysconsaif_syscfg668 (rw) register accessor: STG SYSCONSAIF SYSCFG 668\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg668::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg668::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg668`] +#[doc = "stg_sysconsaif_syscfg668 (rw) register accessor: STG SYSCONSAIF SYSCFG 668\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg668::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg668::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg668`] module"] pub type STG_SYSCONSAIF_SYSCFG668 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 668"] pub mod stg_sysconsaif_syscfg668; -#[doc = "stg_sysconsaif_syscfg672 (rw) register accessor: STG SYSCONSAIF SYSCFG 672\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg672::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg672::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg672`] +#[doc = "stg_sysconsaif_syscfg672 (rw) register accessor: STG SYSCONSAIF SYSCFG 672\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg672::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg672::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg672`] module"] pub type STG_SYSCONSAIF_SYSCFG672 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 672"] pub mod stg_sysconsaif_syscfg672; -#[doc = "stg_sysconsaif_syscfg676 (rw) register accessor: STG SYSCONSAIF SYSCFG 676\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg676::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg676::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg676`] +#[doc = "stg_sysconsaif_syscfg676 (rw) register accessor: STG SYSCONSAIF SYSCFG 676\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg676::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg676::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg676`] module"] pub type STG_SYSCONSAIF_SYSCFG676 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 676"] pub mod stg_sysconsaif_syscfg676; -#[doc = "stg_sysconsaif_syscfg680 (rw) register accessor: STG SYSCONSAIF SYSCFG 680\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg680::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg680::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg680`] +#[doc = "stg_sysconsaif_syscfg680 (rw) register accessor: STG SYSCONSAIF SYSCFG 680\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg680::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg680::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg680`] module"] pub type STG_SYSCONSAIF_SYSCFG680 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 680"] pub mod stg_sysconsaif_syscfg680; -#[doc = "stg_sysconsaif_syscfg684 (rw) register accessor: STG SYSCONSAIF SYSCFG 684\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg684::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg684::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg684`] +#[doc = "stg_sysconsaif_syscfg684 (rw) register accessor: STG SYSCONSAIF SYSCFG 684\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg684::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg684::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg684`] module"] pub type STG_SYSCONSAIF_SYSCFG684 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 684"] pub mod stg_sysconsaif_syscfg684; -#[doc = "stg_sysconsaif_syscfg688 (rw) register accessor: STG SYSCONSAIF SYSCFG 688\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg688::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg688::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg688`] +#[doc = "stg_sysconsaif_syscfg688 (rw) register accessor: STG SYSCONSAIF SYSCFG 688\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg688::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg688::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg688`] module"] pub type STG_SYSCONSAIF_SYSCFG688 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 688"] pub mod stg_sysconsaif_syscfg688; -#[doc = "stg_sysconsaif_syscfg692 (rw) register accessor: STG SYSCONSAIF SYSCFG 692\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg692::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg692::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg692`] +#[doc = "stg_sysconsaif_syscfg692 (rw) register accessor: STG SYSCONSAIF SYSCFG 692\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg692::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg692::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg692`] module"] pub type STG_SYSCONSAIF_SYSCFG692 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 692"] pub mod stg_sysconsaif_syscfg692; -#[doc = "stg_sysconsaif_syscfg696 (rw) register accessor: STG SYSCONSAIF SYSCFG 696\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg696::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg696::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg696`] +#[doc = "stg_sysconsaif_syscfg696 (rw) register accessor: STG SYSCONSAIF SYSCFG 696\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg696::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg696::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg696`] module"] pub type STG_SYSCONSAIF_SYSCFG696 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 696"] pub mod stg_sysconsaif_syscfg696; -#[doc = "stg_sysconsaif_syscfg700 (rw) register accessor: STG SYSCONSAIF SYSCFG 700\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg700::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg700::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg700`] +#[doc = "stg_sysconsaif_syscfg700 (rw) register accessor: STG SYSCONSAIF SYSCFG 700\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg700::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg700::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg700`] module"] pub type STG_SYSCONSAIF_SYSCFG700 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 700"] pub mod stg_sysconsaif_syscfg700; -#[doc = "stg_sysconsaif_syscfg704 (rw) register accessor: STG SYSCONSAIF SYSCFG 704\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg704::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg704::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg704`] +#[doc = "stg_sysconsaif_syscfg704 (rw) register accessor: STG SYSCONSAIF SYSCFG 704\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg704::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg704::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg704`] module"] pub type STG_SYSCONSAIF_SYSCFG704 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 704"] pub mod stg_sysconsaif_syscfg704; -#[doc = "stg_sysconsaif_syscfg708 (rw) register accessor: STG SYSCONSAIF SYSCFG 708\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg708::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg708::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg708`] +#[doc = "stg_sysconsaif_syscfg708 (rw) register accessor: STG SYSCONSAIF SYSCFG 708\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg708::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg708::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg708`] module"] pub type STG_SYSCONSAIF_SYSCFG708 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 708"] pub mod stg_sysconsaif_syscfg708; -#[doc = "stg_sysconsaif_syscfg712 (rw) register accessor: STG SYSCONSAIF SYSCFG 712\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg712::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg712::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg712`] +#[doc = "stg_sysconsaif_syscfg712 (rw) register accessor: STG SYSCONSAIF SYSCFG 712\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg712::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg712::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg712`] module"] pub type STG_SYSCONSAIF_SYSCFG712 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 712"] pub mod stg_sysconsaif_syscfg712; -#[doc = "stg_sysconsaif_syscfg716 (rw) register accessor: STG SYSCONSAIF SYSCFG 716\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg716::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg716::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg716`] +#[doc = "stg_sysconsaif_syscfg716 (rw) register accessor: STG SYSCONSAIF SYSCFG 716\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg716::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg716::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg716`] module"] pub type STG_SYSCONSAIF_SYSCFG716 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 716"] pub mod stg_sysconsaif_syscfg716; -#[doc = "stg_sysconsaif_syscfg720 (rw) register accessor: STG SYSCONSAIF SYSCFG 720\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg720::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg720::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg720`] +#[doc = "stg_sysconsaif_syscfg720 (rw) register accessor: STG SYSCONSAIF SYSCFG 720\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg720::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg720::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg720`] module"] pub type STG_SYSCONSAIF_SYSCFG720 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 720"] pub mod stg_sysconsaif_syscfg720; -#[doc = "stg_sysconsaif_syscfg724 (rw) register accessor: STG SYSCONSAIF SYSCFG 724\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg724::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg724::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg724`] +#[doc = "stg_sysconsaif_syscfg724 (rw) register accessor: STG SYSCONSAIF SYSCFG 724\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg724::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg724::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg724`] module"] pub type STG_SYSCONSAIF_SYSCFG724 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 724"] pub mod stg_sysconsaif_syscfg724; -#[doc = "stg_sysconsaif_syscfg728 (rw) register accessor: STG SYSCONSAIF SYSCFG 728\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg728::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg728::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg728`] +#[doc = "stg_sysconsaif_syscfg728 (rw) register accessor: STG SYSCONSAIF SYSCFG 728\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg728::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg728::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg728`] module"] pub type STG_SYSCONSAIF_SYSCFG728 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 728"] pub mod stg_sysconsaif_syscfg728; -#[doc = "stg_sysconsaif_syscfg732 (rw) register accessor: STG SYSCONSAIF SYSCFG 732\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg732::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg732::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg732`] +#[doc = "stg_sysconsaif_syscfg732 (rw) register accessor: STG SYSCONSAIF SYSCFG 732\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg732::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg732::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg732`] module"] pub type STG_SYSCONSAIF_SYSCFG732 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 732"] pub mod stg_sysconsaif_syscfg732; -#[doc = "stg_sysconsaif_syscfg736 (rw) register accessor: STG SYSCONSAIF SYSCFG 736\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg736::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg736::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg736`] +#[doc = "stg_sysconsaif_syscfg736 (rw) register accessor: STG SYSCONSAIF SYSCFG 736\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg736::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg736::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg736`] module"] pub type STG_SYSCONSAIF_SYSCFG736 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 736"] pub mod stg_sysconsaif_syscfg736; -#[doc = "stg_sysconsaif_syscfg740 (rw) register accessor: STG SYSCONSAIF SYSCFG 740\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg740::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg740::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg740`] +#[doc = "stg_sysconsaif_syscfg740 (rw) register accessor: STG SYSCONSAIF SYSCFG 740\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg740::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg740::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg740`] module"] pub type STG_SYSCONSAIF_SYSCFG740 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 740"] pub mod stg_sysconsaif_syscfg740; -#[doc = "stg_sysconsaif_syscfg744 (rw) register accessor: STG SYSCONSAIF SYSCFG 744\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg744::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg744::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg744`] +#[doc = "stg_sysconsaif_syscfg744 (rw) register accessor: STG SYSCONSAIF SYSCFG 744\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg744::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg744::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg744`] module"] pub type STG_SYSCONSAIF_SYSCFG744 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 744"] pub mod stg_sysconsaif_syscfg744; -#[doc = "stg_sysconsaif_syscfg748 (rw) register accessor: STG SYSCONSAIF SYSCFG 748\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg748::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg748::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg748`] +#[doc = "stg_sysconsaif_syscfg748 (rw) register accessor: STG SYSCONSAIF SYSCFG 748\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg748::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg748::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg748`] module"] pub type STG_SYSCONSAIF_SYSCFG748 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 748"] pub mod stg_sysconsaif_syscfg748; -#[doc = "stg_sysconsaif_syscfg752 (rw) register accessor: STG SYSCONSAIF SYSCFG 752\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg752::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg752::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg752`] +#[doc = "stg_sysconsaif_syscfg752 (rw) register accessor: STG SYSCONSAIF SYSCFG 752\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg752::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg752::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg752`] module"] pub type STG_SYSCONSAIF_SYSCFG752 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 752"] pub mod stg_sysconsaif_syscfg752; -#[doc = "stg_sysconsaif_syscfg756 (rw) register accessor: STG SYSCONSAIF SYSCFG 756\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg756::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg756::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg756`] +#[doc = "stg_sysconsaif_syscfg756 (rw) register accessor: STG SYSCONSAIF SYSCFG 756\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg756::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg756::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg756`] module"] pub type STG_SYSCONSAIF_SYSCFG756 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 756"] pub mod stg_sysconsaif_syscfg756; -#[doc = "stg_sysconsaif_syscfg760 (rw) register accessor: STG SYSCONSAIF SYSCFG 760\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg760::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg760::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg760`] +#[doc = "stg_sysconsaif_syscfg760 (rw) register accessor: STG SYSCONSAIF SYSCFG 760\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg760::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg760::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg760`] module"] pub type STG_SYSCONSAIF_SYSCFG760 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 760"] pub mod stg_sysconsaif_syscfg760; -#[doc = "stg_sysconsaif_syscfg764 (rw) register accessor: STG SYSCONSAIF SYSCFG 764\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg764::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg764::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg764`] +#[doc = "stg_sysconsaif_syscfg764 (rw) register accessor: STG SYSCONSAIF SYSCFG 764\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg764::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg764::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg764`] module"] pub type STG_SYSCONSAIF_SYSCFG764 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 764"] pub mod stg_sysconsaif_syscfg764; -#[doc = "stg_sysconsaif_syscfg768 (rw) register accessor: STG SYSCONSAIF SYSCFG 768\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg768::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg768::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg768`] +#[doc = "stg_sysconsaif_syscfg768 (rw) register accessor: STG SYSCONSAIF SYSCFG 768\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg768::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg768::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg768`] module"] pub type STG_SYSCONSAIF_SYSCFG768 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 768"] pub mod stg_sysconsaif_syscfg768; -#[doc = "stg_sysconsaif_syscfg772 (rw) register accessor: STG SYSCONSAIF SYSCFG 772\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg772::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg772::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg772`] +#[doc = "stg_sysconsaif_syscfg772 (rw) register accessor: STG SYSCONSAIF SYSCFG 772\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg772::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg772::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg772`] module"] pub type STG_SYSCONSAIF_SYSCFG772 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 772"] pub mod stg_sysconsaif_syscfg772; -#[doc = "stg_sysconsaif_syscfg776 (rw) register accessor: STG SYSCONSAIF SYSCFG 776\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg776::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg776::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg776`] +#[doc = "stg_sysconsaif_syscfg776 (rw) register accessor: STG SYSCONSAIF SYSCFG 776\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg776::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg776::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg776`] module"] pub type STG_SYSCONSAIF_SYSCFG776 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 776"] pub mod stg_sysconsaif_syscfg776; -#[doc = "stg_sysconsaif_syscfg780 (rw) register accessor: STG SYSCONSAIF SYSCFG 780\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg780::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg780::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg780`] +#[doc = "stg_sysconsaif_syscfg780 (rw) register accessor: STG SYSCONSAIF SYSCFG 780\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg780::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg780::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg780`] module"] pub type STG_SYSCONSAIF_SYSCFG780 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 780"] pub mod stg_sysconsaif_syscfg780; -#[doc = "stg_sysconsaif_syscfg784 (rw) register accessor: STG SYSCONSAIF SYSCFG 784\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg784::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg784::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg784`] +#[doc = "stg_sysconsaif_syscfg784 (rw) register accessor: STG SYSCONSAIF SYSCFG 784\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg784::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg784::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg784`] module"] pub type STG_SYSCONSAIF_SYSCFG784 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 784"] pub mod stg_sysconsaif_syscfg784; -#[doc = "stg_sysconsaif_syscfg788 (rw) register accessor: STG SYSCONSAIF SYSCFG 788\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg788::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg788::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg788`] +#[doc = "stg_sysconsaif_syscfg788 (rw) register accessor: STG SYSCONSAIF SYSCFG 788\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg788::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg788::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg788`] module"] pub type STG_SYSCONSAIF_SYSCFG788 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 788"] pub mod stg_sysconsaif_syscfg788; -#[doc = "stg_sysconsaif_syscfg792 (rw) register accessor: STG SYSCONSAIF SYSCFG 792\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg792::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg792::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg792`] +#[doc = "stg_sysconsaif_syscfg792 (rw) register accessor: STG SYSCONSAIF SYSCFG 792\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg792::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg792::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg792`] module"] pub type STG_SYSCONSAIF_SYSCFG792 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 792"] pub mod stg_sysconsaif_syscfg792; -#[doc = "stg_sysconsaif_syscfg796 (rw) register accessor: STG SYSCONSAIF SYSCFG 796\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg796::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg796::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg796`] +#[doc = "stg_sysconsaif_syscfg796 (rw) register accessor: STG SYSCONSAIF SYSCFG 796\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg796::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg796::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg796`] module"] pub type STG_SYSCONSAIF_SYSCFG796 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 796"] pub mod stg_sysconsaif_syscfg796; -#[doc = "stg_sysconsaif_syscfg800 (rw) register accessor: STG SYSCONSAIF SYSCFG 800\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg800::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg800::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg800`] +#[doc = "stg_sysconsaif_syscfg800 (rw) register accessor: STG SYSCONSAIF SYSCFG 800\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg800::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg800::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg800`] module"] pub type STG_SYSCONSAIF_SYSCFG800 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 800"] pub mod stg_sysconsaif_syscfg800; -#[doc = "stg_sysconsaif_syscfg804 (rw) register accessor: STG SYSCONSAIF SYSCFG 804\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg804::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg804::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg804`] +#[doc = "stg_sysconsaif_syscfg804 (rw) register accessor: STG SYSCONSAIF SYSCFG 804\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg804::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg804::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg804`] module"] pub type STG_SYSCONSAIF_SYSCFG804 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 804"] pub mod stg_sysconsaif_syscfg804; -#[doc = "stg_sysconsaif_syscfg808 (rw) register accessor: STG SYSCONSAIF SYSCFG 808\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg808::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg808::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg808`] +#[doc = "stg_sysconsaif_syscfg808 (rw) register accessor: STG SYSCONSAIF SYSCFG 808\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg808::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg808::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg808`] module"] pub type STG_SYSCONSAIF_SYSCFG808 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 808"] pub mod stg_sysconsaif_syscfg808; -#[doc = "stg_sysconsaif_syscfg812 (rw) register accessor: STG SYSCONSAIF SYSCFG 812\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg812::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg812::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg812`] +#[doc = "stg_sysconsaif_syscfg812 (rw) register accessor: STG SYSCONSAIF SYSCFG 812\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg812::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg812::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg812`] module"] pub type STG_SYSCONSAIF_SYSCFG812 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 812"] pub mod stg_sysconsaif_syscfg812; -#[doc = "stg_sysconsaif_syscfg816 (rw) register accessor: STG SYSCONSAIF SYSCFG 816\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg816::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg816::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg816`] +#[doc = "stg_sysconsaif_syscfg816 (rw) register accessor: STG SYSCONSAIF SYSCFG 816\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg816::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg816::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg816`] module"] pub type STG_SYSCONSAIF_SYSCFG816 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 816"] pub mod stg_sysconsaif_syscfg816; -#[doc = "stg_sysconsaif_syscfg820 (rw) register accessor: STG SYSCONSAIF SYSCFG 820\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg820::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg820::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg820`] +#[doc = "stg_sysconsaif_syscfg820 (rw) register accessor: STG SYSCONSAIF SYSCFG 820\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg820::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg820::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg820`] module"] pub type STG_SYSCONSAIF_SYSCFG820 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 820"] pub mod stg_sysconsaif_syscfg820; -#[doc = "stg_sysconsaif_syscfg824 (rw) register accessor: STG SYSCONSAIF SYSCFG 824\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg824::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg824::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg824`] +#[doc = "stg_sysconsaif_syscfg824 (rw) register accessor: STG SYSCONSAIF SYSCFG 824\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg824::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg824::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg824`] module"] pub type STG_SYSCONSAIF_SYSCFG824 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 824"] pub mod stg_sysconsaif_syscfg824; -#[doc = "stg_sysconsaif_syscfg828 (rw) register accessor: STG SYSCONSAIF SYSCFG 828\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg828::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg828::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg828`] +#[doc = "stg_sysconsaif_syscfg828 (rw) register accessor: STG SYSCONSAIF SYSCFG 828\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg828::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg828::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg828`] module"] pub type STG_SYSCONSAIF_SYSCFG828 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 828"] pub mod stg_sysconsaif_syscfg828; -#[doc = "stg_sysconsaif_syscfg832 (rw) register accessor: STG SYSCONSAIF SYSCFG 832\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg832::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg832::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg832`] +#[doc = "stg_sysconsaif_syscfg832 (rw) register accessor: STG SYSCONSAIF SYSCFG 832\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg832::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg832::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg832`] module"] pub type STG_SYSCONSAIF_SYSCFG832 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 832"] pub mod stg_sysconsaif_syscfg832; -#[doc = "stg_sysconsaif_syscfg836 (rw) register accessor: STG SYSCONSAIF SYSCFG 836\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg836::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg836::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg836`] +#[doc = "stg_sysconsaif_syscfg836 (rw) register accessor: STG SYSCONSAIF SYSCFG 836\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg836::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg836::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg836`] module"] pub type STG_SYSCONSAIF_SYSCFG836 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 836"] pub mod stg_sysconsaif_syscfg836; -#[doc = "stg_sysconsaif_syscfg840 (rw) register accessor: STG SYSCONSAIF SYSCFG 840\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg840::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg840::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg840`] +#[doc = "stg_sysconsaif_syscfg840 (rw) register accessor: STG SYSCONSAIF SYSCFG 840\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg840::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg840::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg840`] module"] pub type STG_SYSCONSAIF_SYSCFG840 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 840"] pub mod stg_sysconsaif_syscfg840; -#[doc = "stg_sysconsaif_syscfg844 (rw) register accessor: STG SYSCONSAIF SYSCFG 844\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg844::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg844::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg844`] +#[doc = "stg_sysconsaif_syscfg844 (rw) register accessor: STG SYSCONSAIF SYSCFG 844\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg844::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg844::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg844`] module"] pub type STG_SYSCONSAIF_SYSCFG844 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 844"] pub mod stg_sysconsaif_syscfg844; -#[doc = "stg_sysconsaif_syscfg848 (rw) register accessor: STG SYSCONSAIF SYSCFG 848\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg848::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg848::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg848`] +#[doc = "stg_sysconsaif_syscfg848 (rw) register accessor: STG SYSCONSAIF SYSCFG 848\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg848::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg848::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg848`] module"] pub type STG_SYSCONSAIF_SYSCFG848 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 848"] pub mod stg_sysconsaif_syscfg848; -#[doc = "stg_sysconsaif_syscfg852 (rw) register accessor: STG SYSCONSAIF SYSCFG 852\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg852::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg852::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg852`] +#[doc = "stg_sysconsaif_syscfg852 (rw) register accessor: STG SYSCONSAIF SYSCFG 852\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg852::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg852::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg852`] module"] pub type STG_SYSCONSAIF_SYSCFG852 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 852"] pub mod stg_sysconsaif_syscfg852; -#[doc = "stg_sysconsaif_syscfg856 (rw) register accessor: STG SYSCONSAIF SYSCFG 856\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg856::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg856::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg856`] +#[doc = "stg_sysconsaif_syscfg856 (rw) register accessor: STG SYSCONSAIF SYSCFG 856\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg856::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg856::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg856`] module"] pub type STG_SYSCONSAIF_SYSCFG856 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 856"] pub mod stg_sysconsaif_syscfg856; -#[doc = "stg_sysconsaif_syscfg860 (rw) register accessor: STG SYSCONSAIF SYSCFG 860\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg860::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg860::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg860`] +#[doc = "stg_sysconsaif_syscfg860 (rw) register accessor: STG SYSCONSAIF SYSCFG 860\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg860::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg860::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg860`] module"] pub type STG_SYSCONSAIF_SYSCFG860 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 860"] pub mod stg_sysconsaif_syscfg860; -#[doc = "stg_sysconsaif_syscfg864 (rw) register accessor: STG SYSCONSAIF SYSCFG 864\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg864::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg864::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg864`] +#[doc = "stg_sysconsaif_syscfg864 (rw) register accessor: STG SYSCONSAIF SYSCFG 864\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg864::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg864::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg864`] module"] pub type STG_SYSCONSAIF_SYSCFG864 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 864"] pub mod stg_sysconsaif_syscfg864; -#[doc = "stg_sysconsaif_syscfg868 (rw) register accessor: STG SYSCONSAIF SYSCFG 868\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg868::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg868::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg868`] +#[doc = "stg_sysconsaif_syscfg868 (rw) register accessor: STG SYSCONSAIF SYSCFG 868\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg868::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg868::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg868`] module"] pub type STG_SYSCONSAIF_SYSCFG868 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 868"] pub mod stg_sysconsaif_syscfg868; -#[doc = "stg_sysconsaif_syscfg872 (rw) register accessor: STG SYSCONSAIF SYSCFG 872\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg872::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg872::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg872`] +#[doc = "stg_sysconsaif_syscfg872 (rw) register accessor: STG SYSCONSAIF SYSCFG 872\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg872::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg872::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg872`] module"] pub type STG_SYSCONSAIF_SYSCFG872 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 872"] pub mod stg_sysconsaif_syscfg872; -#[doc = "stg_sysconsaif_syscfg876 (rw) register accessor: STG SYSCONSAIF SYSCFG 876\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg876::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg876::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg876`] +#[doc = "stg_sysconsaif_syscfg876 (rw) register accessor: STG SYSCONSAIF SYSCFG 876\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg876::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg876::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg876`] module"] pub type STG_SYSCONSAIF_SYSCFG876 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 876"] pub mod stg_sysconsaif_syscfg876; -#[doc = "stg_sysconsaif_syscfg880 (rw) register accessor: STG SYSCONSAIF SYSCFG 880\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg880::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg880::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg880`] +#[doc = "stg_sysconsaif_syscfg880 (rw) register accessor: STG SYSCONSAIF SYSCFG 880\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg880::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg880::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg880`] module"] pub type STG_SYSCONSAIF_SYSCFG880 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 880"] pub mod stg_sysconsaif_syscfg880; -#[doc = "stg_sysconsaif_syscfg884 (rw) register accessor: STG SYSCONSAIF SYSCFG 884\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg884::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg884::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg884`] +#[doc = "stg_sysconsaif_syscfg884 (rw) register accessor: STG SYSCONSAIF SYSCFG 884\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg884::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg884::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg884`] module"] pub type STG_SYSCONSAIF_SYSCFG884 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 884"] pub mod stg_sysconsaif_syscfg884; -#[doc = "stg_sysconsaif_syscfg888 (rw) register accessor: STG SYSCONSAIF SYSCFG 888\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg888::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg888::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg888`] +#[doc = "stg_sysconsaif_syscfg888 (rw) register accessor: STG SYSCONSAIF SYSCFG 888\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg888::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg888::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg888`] module"] pub type STG_SYSCONSAIF_SYSCFG888 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 888"] pub mod stg_sysconsaif_syscfg888; -#[doc = "stg_sysconsaif_syscfg892 (rw) register accessor: STG SYSCONSAIF SYSCFG 892\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg892::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg892::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg892`] +#[doc = "stg_sysconsaif_syscfg892 (rw) register accessor: STG SYSCONSAIF SYSCFG 892\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg892::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg892::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg892`] module"] pub type STG_SYSCONSAIF_SYSCFG892 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 892"] pub mod stg_sysconsaif_syscfg892; -#[doc = "stg_sysconsaif_syscfg896 (rw) register accessor: STG SYSCONSAIF SYSCFG 896\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg896::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg896::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg896`] +#[doc = "stg_sysconsaif_syscfg896 (rw) register accessor: STG SYSCONSAIF SYSCFG 896\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg896::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg896::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg896`] module"] pub type STG_SYSCONSAIF_SYSCFG896 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 896"] pub mod stg_sysconsaif_syscfg896; -#[doc = "stg_sysconsaif_syscfg900 (rw) register accessor: STG SYSCONSAIF SYSCFG 900\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg900::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg900::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg900`] +#[doc = "stg_sysconsaif_syscfg900 (rw) register accessor: STG SYSCONSAIF SYSCFG 900\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg900::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg900::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg900`] module"] pub type STG_SYSCONSAIF_SYSCFG900 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 900"] pub mod stg_sysconsaif_syscfg900; -#[doc = "stg_sysconsaif_syscfg904 (rw) register accessor: STG SYSCONSAIF SYSCFG 904\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg904::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg904::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg904`] +#[doc = "stg_sysconsaif_syscfg904 (rw) register accessor: STG SYSCONSAIF SYSCFG 904\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg904::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg904::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg904`] module"] pub type STG_SYSCONSAIF_SYSCFG904 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 904"] pub mod stg_sysconsaif_syscfg904; -#[doc = "stg_sysconsaif_syscfg908 (rw) register accessor: STG SYSCONSAIF SYSCFG 908\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg908::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg908::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg908`] +#[doc = "stg_sysconsaif_syscfg908 (rw) register accessor: STG SYSCONSAIF SYSCFG 908\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg908::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg908::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg908`] module"] pub type STG_SYSCONSAIF_SYSCFG908 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 908"] pub mod stg_sysconsaif_syscfg908; -#[doc = "stg_sysconsaif_syscfg912 (rw) register accessor: STG SYSCONSAIF SYSCFG 912\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg912::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg912::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg912`] +#[doc = "stg_sysconsaif_syscfg912 (rw) register accessor: STG SYSCONSAIF SYSCFG 912\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg912::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg912::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg912`] module"] pub type STG_SYSCONSAIF_SYSCFG912 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 912"] pub mod stg_sysconsaif_syscfg912; -#[doc = "stg_sysconsaif_syscfg916 (rw) register accessor: STG SYSCONSAIF SYSCFG 916\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg916::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg916::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg916`] +#[doc = "stg_sysconsaif_syscfg916 (rw) register accessor: STG SYSCONSAIF SYSCFG 916\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg916::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg916::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg916`] module"] pub type STG_SYSCONSAIF_SYSCFG916 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 916"] pub mod stg_sysconsaif_syscfg916; -#[doc = "stg_sysconsaif_syscfg920 (rw) register accessor: STG SYSCONSAIF SYSCFG 920\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg920::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg920::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg920`] +#[doc = "stg_sysconsaif_syscfg920 (rw) register accessor: STG SYSCONSAIF SYSCFG 920\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg920::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg920::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg920`] module"] pub type STG_SYSCONSAIF_SYSCFG920 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 920"] pub mod stg_sysconsaif_syscfg920; -#[doc = "stg_sysconsaif_syscfg924 (rw) register accessor: STG SYSCONSAIF SYSCFG 924\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg924::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg924::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg924`] +#[doc = "stg_sysconsaif_syscfg924 (rw) register accessor: STG SYSCONSAIF SYSCFG 924\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg924::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg924::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg924`] module"] pub type STG_SYSCONSAIF_SYSCFG924 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 924"] pub mod stg_sysconsaif_syscfg924; -#[doc = "stg_sysconsaif_syscfg928 (rw) register accessor: STG SYSCONSAIF SYSCFG 928\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg928::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg928::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg928`] +#[doc = "stg_sysconsaif_syscfg928 (rw) register accessor: STG SYSCONSAIF SYSCFG 928\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg928::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg928::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg928`] module"] pub type STG_SYSCONSAIF_SYSCFG928 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 928"] pub mod stg_sysconsaif_syscfg928; -#[doc = "stg_sysconsaif_syscfg932 (rw) register accessor: STG SYSCONSAIF SYSCFG 932\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg932::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg932::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg932`] +#[doc = "stg_sysconsaif_syscfg932 (rw) register accessor: STG SYSCONSAIF SYSCFG 932\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg932::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg932::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg932`] module"] pub type STG_SYSCONSAIF_SYSCFG932 = crate::Reg; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg0.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg0.rs index 38458b8..d85514a 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg0.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg0.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `scfg_hprot_sd0` reader - scfg_hprot_sd0"] pub type SCFG_HPROT_SD0_R = crate::FieldReader; #[doc = "Field `scfg_hprot_sd0` writer - scfg_hprot_sd0"] -pub type SCFG_HPROT_SD0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_HPROT_SD0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_hprot_sd1` reader - scfg_hprot_sd1"] pub type SCFG_HPROT_SD1_R = crate::FieldReader; #[doc = "Field `scfg_hprot_sd1` writer - scfg_hprot_sd1"] -pub type SCFG_HPROT_SD1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_HPROT_SD1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `u0_cdn_usb_adp_en` reader - u0_cdn_usb_adp_en"] pub type U0_CDN_USB_ADP_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_adp_probe_ana` reader - u0_cdn_usb_adp_probe_ana"] pub type U0_CDN_USB_ADP_PROBE_ANA_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_adp_probe_ana` writer - u0_cdn_usb_adp_probe_ana"] -pub type U0_CDN_USB_ADP_PROBE_ANA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_ADP_PROBE_ANA_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_adp_probe_en` reader - u0_cdn_usb_adp_probe_en"] pub type U0_CDN_USB_ADP_PROBE_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_adp_sense_ana` reader - u0_cdn_usb_adp_sense_ana"] pub type U0_CDN_USB_ADP_SENSE_ANA_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_adp_sense_ana` writer - u0_cdn_usb_adp_sense_ana"] -pub type U0_CDN_USB_ADP_SENSE_ANA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_ADP_SENSE_ANA_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_adp_sense_en` reader - u0_cdn_usb_adp_sense_en"] pub type U0_CDN_USB_ADP_SENSE_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_adp_sink_current_en` reader - u0_cdn_usb_adp_sink_current_en"] @@ -33,37 +33,37 @@ pub type U0_CDN_USB_BC_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_chrg_vbus` reader - u0_cdn_usb_chrg_vbus"] pub type U0_CDN_USB_CHRG_VBUS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_chrg_vbus` writer - u0_cdn_usb_chrg_vbus"] -pub type U0_CDN_USB_CHRG_VBUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_CHRG_VBUS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_dcd_comp_sts` reader - u0_cdn_usb_dcd_comp_sts"] pub type U0_CDN_USB_DCD_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_dcd_comp_sts` writer - u0_cdn_usb_dcd_comp_sts"] -pub type U0_CDN_USB_DCD_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_DCD_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_dischrg_vbus` reader - u0_cdn_usb_dischrg_vbus"] pub type U0_CDN_USB_DISCHRG_VBUS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_dischrg_vbus` writer - u0_cdn_usb_dischrg_vbus"] -pub type U0_CDN_USB_DISCHRG_VBUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_DISCHRG_VBUS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_dm_vdat_ref_comp_en` reader - u0_cdn_usb_dm_vdat_ref_comp_en"] pub type U0_CDN_USB_DM_VDAT_REF_COMP_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_dm_vdat_ref_comp_sts` reader - u0_cdn_usb_dm_vdat_ref_comp_sts"] pub type U0_CDN_USB_DM_VDAT_REF_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_dm_vdat_ref_comp_sts` writer - u0_cdn_usb_dm_vdat_ref_comp_sts"] -pub type U0_CDN_USB_DM_VDAT_REF_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_DM_VDAT_REF_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_dm_vlgc_comp_en` reader - u0_cdn_usb_dm_vlgc_comp_en"] pub type U0_CDN_USB_DM_VLGC_COMP_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_dm_vlgc_comp_sts` reader - u0_cdn_usb_dm_vlgc_comp_sts"] pub type U0_CDN_USB_DM_VLGC_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_dm_vlgc_comp_sts` writer - u0_cdn_usb_dm_vlgc_comp_sts"] -pub type U0_CDN_USB_DM_VLGC_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_DM_VLGC_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_dp_vdat_ref_comp_en` reader - u0_cdn_usb_dp_vdat_ref_comp_en"] pub type U0_CDN_USB_DP_VDAT_REF_COMP_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_dp_vdat_ref_comp_sts` reader - u0_cdn_usb_dp_vdat_ref_comp_sts"] pub type U0_CDN_USB_DP_VDAT_REF_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_dp_vdat_ref_comp_sts` writer - u0_cdn_usb_dp_vdat_ref_comp_sts"] -pub type U0_CDN_USB_DP_VDAT_REF_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_DP_VDAT_REF_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_host_system_err` reader - u0_cdn_usb_host_system_err"] pub type U0_CDN_USB_HOST_SYSTEM_ERR_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_host_system_err` writer - u0_cdn_usb_host_system_err"] -pub type U0_CDN_USB_HOST_SYSTEM_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_HOST_SYSTEM_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_hsystem_err_ext` reader - u0_cdn_usb_hsystem_err_ext"] pub type U0_CDN_USB_HSYSTEM_ERR_EXT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_idm_sink_en` reader - u0_cdn_usb_idm_sink_en"] @@ -198,88 +198,90 @@ impl W { #[doc = "Bits 0:3 - scfg_hprot_sd0"] #[inline(always)] #[must_use] - pub fn scfg_hprot_sd0(&mut self) -> SCFG_HPROT_SD0_W { - SCFG_HPROT_SD0_W::new(self) + pub fn scfg_hprot_sd0(&mut self) -> SCFG_HPROT_SD0_W { + SCFG_HPROT_SD0_W::new(self, 0) } #[doc = "Bits 4:7 - scfg_hprot_sd1"] #[inline(always)] #[must_use] - pub fn scfg_hprot_sd1(&mut self) -> SCFG_HPROT_SD1_W { - SCFG_HPROT_SD1_W::new(self) + pub fn scfg_hprot_sd1(&mut self) -> SCFG_HPROT_SD1_W { + SCFG_HPROT_SD1_W::new(self, 4) } #[doc = "Bit 9 - u0_cdn_usb_adp_probe_ana"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_adp_probe_ana( &mut self, - ) -> U0_CDN_USB_ADP_PROBE_ANA_W { - U0_CDN_USB_ADP_PROBE_ANA_W::new(self) + ) -> U0_CDN_USB_ADP_PROBE_ANA_W { + U0_CDN_USB_ADP_PROBE_ANA_W::new(self, 9) } #[doc = "Bit 11 - u0_cdn_usb_adp_sense_ana"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_adp_sense_ana( &mut self, - ) -> U0_CDN_USB_ADP_SENSE_ANA_W { - U0_CDN_USB_ADP_SENSE_ANA_W::new(self) + ) -> U0_CDN_USB_ADP_SENSE_ANA_W { + U0_CDN_USB_ADP_SENSE_ANA_W::new(self, 11) } #[doc = "Bit 16 - u0_cdn_usb_chrg_vbus"] #[inline(always)] #[must_use] - pub fn u0_cdn_usb_chrg_vbus( - &mut self, - ) -> U0_CDN_USB_CHRG_VBUS_W { - U0_CDN_USB_CHRG_VBUS_W::new(self) + pub fn u0_cdn_usb_chrg_vbus(&mut self) -> U0_CDN_USB_CHRG_VBUS_W { + U0_CDN_USB_CHRG_VBUS_W::new(self, 16) } #[doc = "Bit 17 - u0_cdn_usb_dcd_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_dcd_comp_sts( &mut self, - ) -> U0_CDN_USB_DCD_COMP_STS_W { - U0_CDN_USB_DCD_COMP_STS_W::new(self) + ) -> U0_CDN_USB_DCD_COMP_STS_W { + U0_CDN_USB_DCD_COMP_STS_W::new(self, 17) } #[doc = "Bit 18 - u0_cdn_usb_dischrg_vbus"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_dischrg_vbus( &mut self, - ) -> U0_CDN_USB_DISCHRG_VBUS_W { - U0_CDN_USB_DISCHRG_VBUS_W::new(self) + ) -> U0_CDN_USB_DISCHRG_VBUS_W { + U0_CDN_USB_DISCHRG_VBUS_W::new(self, 18) } #[doc = "Bit 20 - u0_cdn_usb_dm_vdat_ref_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_dm_vdat_ref_comp_sts( &mut self, - ) -> U0_CDN_USB_DM_VDAT_REF_COMP_STS_W { - U0_CDN_USB_DM_VDAT_REF_COMP_STS_W::new(self) + ) -> U0_CDN_USB_DM_VDAT_REF_COMP_STS_W { + U0_CDN_USB_DM_VDAT_REF_COMP_STS_W::new(self, 20) } #[doc = "Bit 22 - u0_cdn_usb_dm_vlgc_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_dm_vlgc_comp_sts( &mut self, - ) -> U0_CDN_USB_DM_VLGC_COMP_STS_W { - U0_CDN_USB_DM_VLGC_COMP_STS_W::new(self) + ) -> U0_CDN_USB_DM_VLGC_COMP_STS_W { + U0_CDN_USB_DM_VLGC_COMP_STS_W::new(self, 22) } #[doc = "Bit 24 - u0_cdn_usb_dp_vdat_ref_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_dp_vdat_ref_comp_sts( &mut self, - ) -> U0_CDN_USB_DP_VDAT_REF_COMP_STS_W { - U0_CDN_USB_DP_VDAT_REF_COMP_STS_W::new(self) + ) -> U0_CDN_USB_DP_VDAT_REF_COMP_STS_W { + U0_CDN_USB_DP_VDAT_REF_COMP_STS_W::new(self, 24) } #[doc = "Bit 25 - u0_cdn_usb_host_system_err"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_host_system_err( &mut self, - ) -> U0_CDN_USB_HOST_SYSTEM_ERR_W { - U0_CDN_USB_HOST_SYSTEM_ERR_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_CDN_USB_HOST_SYSTEM_ERR_W { + U0_CDN_USB_HOST_SYSTEM_ERR_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg100.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg100.rs index 80dd684..45bc433 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg100.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg100.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg104.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg104.rs index 1adda62..4f179ca 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg104.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg104.rs @@ -28,7 +28,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg108.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg108.rs index 492434f..f583a5d 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg108.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg108.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg112.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg112.rs index 6c6e60a..00c20e4 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg112.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg112.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg116.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg116.rs index 0f63978..0256435 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg116.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg116.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg12.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg12.rs index 8ecb8dc..bd51844 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg12.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg12.rs @@ -7,44 +7,43 @@ pub type U0_CDN_USB_UTMI_RXVALIDH_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_sessvld` reader - u0_cdn_usb_utmi_sessvld"] pub type U0_CDN_USB_UTMI_SESSVLD_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_sessvld` writer - u0_cdn_usb_utmi_sessvld"] -pub type U0_CDN_USB_UTMI_SESSVLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_SESSVLD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_termselect_sit` reader - u0_cdn_usb_utmi_termselect_sit"] pub type U0_CDN_USB_UTMI_TERMSELECT_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_termselect_sit` writer - u0_cdn_usb_utmi_termselect_sit"] -pub type U0_CDN_USB_UTMI_TERMSELECT_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_TERMSELECT_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_tx_dat_sit` reader - u0_cdn_usb_utmi_tx_dat_sit"] pub type U0_CDN_USB_UTMI_TX_DAT_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_tx_dat_sit` writer - u0_cdn_usb_utmi_tx_dat_sit"] -pub type U0_CDN_USB_UTMI_TX_DAT_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_TX_DAT_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_tx_enable_n_sit` reader - u0_cdn_usb_utmi_tx_enable_n_sit"] pub type U0_CDN_USB_UTMI_TX_ENABLE_N_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_tx_enable_n_sit` writer - u0_cdn_usb_utmi_tx_enable_n_sit"] -pub type U0_CDN_USB_UTMI_TX_ENABLE_N_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_TX_ENABLE_N_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_tx_se0_sit` reader - u0_cdn_usb_utmi_tx_se0_sit"] pub type U0_CDN_USB_UTMI_TX_SE0_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_tx_se0_sit` writer - u0_cdn_usb_utmi_tx_se0_sit"] -pub type U0_CDN_USB_UTMI_TX_SE0_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_TX_SE0_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_txbitstuffenable_sit` reader - u0_cdn_usb_utmi_txbitstuffenable_sit"] pub type U0_CDN_USB_UTMI_TXBITSTUFFENABLE_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_txbitstuffenable_sit` writer - u0_cdn_usb_utmi_txbitstuffenable_sit"] -pub type U0_CDN_USB_UTMI_TXBITSTUFFENABLE_SIT_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_TXBITSTUFFENABLE_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_txready_sit` reader - u0_cdn_usb_utmi_txready_sit"] pub type U0_CDN_USB_UTMI_TXREADY_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_txvalid_sit` reader - u0_cdn_usb_utmi_txvalid_sit"] pub type U0_CDN_USB_UTMI_TXVALID_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_txvalid_sit` writer - u0_cdn_usb_utmi_txvalid_sit"] -pub type U0_CDN_USB_UTMI_TXVALID_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_TXVALID_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_txvalidh_sit` reader - u0_cdn_usb_utmi_txvalidh_sit"] pub type U0_CDN_USB_UTMI_TXVALIDH_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_txvalidh_sit` writer - u0_cdn_usb_utmi_txvalidh_sit"] -pub type U0_CDN_USB_UTMI_TXVALIDH_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_TXVALIDH_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_vbusvalid_sit` reader - u0_cdn_usb_utmi_vbusvalid_sit"] pub type U0_CDN_USB_UTMI_VBUSVALID_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_xcvrselect_sit` reader - u0_cdn_usb_utmi_xcvrselect_sit"] pub type U0_CDN_USB_UTMI_XCVRSELECT_SIT_R = crate::FieldReader; #[doc = "Field `u0_cdn_usb_utmi_xcvrselect_sit` writer - u0_cdn_usb_utmi_xcvrselect_sit"] -pub type U0_CDN_USB_UTMI_XCVRSELECT_SIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDN_USB_UTMI_XCVRSELECT_SIT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdn_usb_utmi_vdm_src_en` reader - u0_cdn_usb_utmi_vdm_src_en"] pub type U0_CDN_USB_UTMI_VDM_SRC_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_vdp_src_en` reader - u0_cdn_usb_utmi_vdp_src_en"] @@ -52,13 +51,13 @@ pub type U0_CDN_USB_UTMI_VDP_SRC_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_wakeup` reader - u0_cdn_usb_wakeup"] pub type U0_CDN_USB_WAKEUP_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_wakeup` writer - u0_cdn_usb_wakeup"] -pub type U0_CDN_USB_WAKEUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_WAKEUP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_xhc_d0_ack` reader - u0_cdn_usb_xhc_d0_ack"] pub type U0_CDN_USB_XHC_D0_ACK_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhc_d0_req` reader - u0_cdn_usb_xhc_d0_req"] pub type U0_CDN_USB_XHC_D0_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhc_d0_req` writer - u0_cdn_usb_xhc_d0_req"] -pub type U0_CDN_USB_XHC_D0_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_XHC_D0_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - u0_cdn_usb_utmi_rxvalidh_sit"] #[inline(always)] @@ -152,88 +151,92 @@ impl W { #[must_use] pub fn u0_cdn_usb_utmi_sessvld( &mut self, - ) -> U0_CDN_USB_UTMI_SESSVLD_W { - U0_CDN_USB_UTMI_SESSVLD_W::new(self) + ) -> U0_CDN_USB_UTMI_SESSVLD_W { + U0_CDN_USB_UTMI_SESSVLD_W::new(self, 1) } #[doc = "Bit 2 - u0_cdn_usb_utmi_termselect_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_termselect_sit( &mut self, - ) -> U0_CDN_USB_UTMI_TERMSELECT_SIT_W { - U0_CDN_USB_UTMI_TERMSELECT_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_TERMSELECT_SIT_W { + U0_CDN_USB_UTMI_TERMSELECT_SIT_W::new(self, 2) } #[doc = "Bit 3 - u0_cdn_usb_utmi_tx_dat_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_tx_dat_sit( &mut self, - ) -> U0_CDN_USB_UTMI_TX_DAT_SIT_W { - U0_CDN_USB_UTMI_TX_DAT_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_TX_DAT_SIT_W { + U0_CDN_USB_UTMI_TX_DAT_SIT_W::new(self, 3) } #[doc = "Bit 4 - u0_cdn_usb_utmi_tx_enable_n_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_tx_enable_n_sit( &mut self, - ) -> U0_CDN_USB_UTMI_TX_ENABLE_N_SIT_W { - U0_CDN_USB_UTMI_TX_ENABLE_N_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_TX_ENABLE_N_SIT_W { + U0_CDN_USB_UTMI_TX_ENABLE_N_SIT_W::new(self, 4) } #[doc = "Bit 5 - u0_cdn_usb_utmi_tx_se0_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_tx_se0_sit( &mut self, - ) -> U0_CDN_USB_UTMI_TX_SE0_SIT_W { - U0_CDN_USB_UTMI_TX_SE0_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_TX_SE0_SIT_W { + U0_CDN_USB_UTMI_TX_SE0_SIT_W::new(self, 5) } #[doc = "Bit 6 - u0_cdn_usb_utmi_txbitstuffenable_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_txbitstuffenable_sit( &mut self, - ) -> U0_CDN_USB_UTMI_TXBITSTUFFENABLE_SIT_W { - U0_CDN_USB_UTMI_TXBITSTUFFENABLE_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_TXBITSTUFFENABLE_SIT_W { + U0_CDN_USB_UTMI_TXBITSTUFFENABLE_SIT_W::new(self, 6) } #[doc = "Bit 8 - u0_cdn_usb_utmi_txvalid_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_txvalid_sit( &mut self, - ) -> U0_CDN_USB_UTMI_TXVALID_SIT_W { - U0_CDN_USB_UTMI_TXVALID_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_TXVALID_SIT_W { + U0_CDN_USB_UTMI_TXVALID_SIT_W::new(self, 8) } #[doc = "Bit 9 - u0_cdn_usb_utmi_txvalidh_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_txvalidh_sit( &mut self, - ) -> U0_CDN_USB_UTMI_TXVALIDH_SIT_W { - U0_CDN_USB_UTMI_TXVALIDH_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_TXVALIDH_SIT_W { + U0_CDN_USB_UTMI_TXVALIDH_SIT_W::new(self, 9) } #[doc = "Bits 11:12 - u0_cdn_usb_utmi_xcvrselect_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_xcvrselect_sit( &mut self, - ) -> U0_CDN_USB_UTMI_XCVRSELECT_SIT_W { - U0_CDN_USB_UTMI_XCVRSELECT_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_XCVRSELECT_SIT_W { + U0_CDN_USB_UTMI_XCVRSELECT_SIT_W::new(self, 11) } #[doc = "Bit 15 - u0_cdn_usb_wakeup"] #[inline(always)] #[must_use] - pub fn u0_cdn_usb_wakeup(&mut self) -> U0_CDN_USB_WAKEUP_W { - U0_CDN_USB_WAKEUP_W::new(self) + pub fn u0_cdn_usb_wakeup(&mut self) -> U0_CDN_USB_WAKEUP_W { + U0_CDN_USB_WAKEUP_W::new(self, 15) } #[doc = "Bit 17 - u0_cdn_usb_xhc_d0_req"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_xhc_d0_req( &mut self, - ) -> U0_CDN_USB_XHC_D0_REQ_W { - U0_CDN_USB_XHC_D0_REQ_W::new(self) + ) -> U0_CDN_USB_XHC_D0_REQ_W { + U0_CDN_USB_XHC_D0_REQ_W::new(self, 17) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg120.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg120.rs index 86c1c12..caa5895 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg120.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg120.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg124.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg124.rs index ac94c10..574a1b2 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg124.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg124.rs @@ -7,7 +7,7 @@ pub type U0_PLDA_PCIE_AXI4_MST0_AWUSER_42_32_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_mst0_rderr` reader - u0_plda_pcie_axi4_mst0_rderr"] pub type U0_PLDA_PCIE_AXI4_MST0_RDERR_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_mst0_rderr` writer - u0_plda_pcie_axi4_mst0_rderr"] -pub type U0_PLDA_PCIE_AXI4_MST0_RDERR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type U0_PLDA_PCIE_AXI4_MST0_RDERR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:10 - u0_plda_pcie_axi4_mst0_awuser_42_32"] #[inline(always)] @@ -26,10 +26,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_mst0_rderr( &mut self, - ) -> U0_PLDA_PCIE_AXI4_MST0_RDERR_W { - U0_PLDA_PCIE_AXI4_MST0_RDERR_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_MST0_RDERR_W { + U0_PLDA_PCIE_AXI4_MST0_RDERR_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg128.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg128.rs index 7f6e88e..805761e 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg128.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg128.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_mst0_ruser` reader - u0_plda_pcie_axi4_mst0_ruser"] pub type U0_PLDA_PCIE_AXI4_MST0_RUSER_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_mst0_ruser` writer - u0_plda_pcie_axi4_mst0_ruser"] -pub type U0_PLDA_PCIE_AXI4_MST0_RUSER_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_MST0_RUSER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_mst0_ruser"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_mst0_ruser( &mut self, - ) -> U0_PLDA_PCIE_AXI4_MST0_RUSER_W { - U0_PLDA_PCIE_AXI4_MST0_RUSER_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_MST0_RUSER_W { + U0_PLDA_PCIE_AXI4_MST0_RUSER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg132.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg132.rs index 1073759..9e2b614 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg132.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg132.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg136.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg136.rs index 9c0fe6d..285abf3 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg136.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg136.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_31_0` reader - u0_plda_pcie_axi4_slv0_aratomop_31_0"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_31_0` writer - u0_plda_pcie_axi4_slv0_aratomop_31_0"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aratomop_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_31_0( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg140.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg140.rs index 8d1537e..26fd0a6 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg140.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg140.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_63_32` reader - u0_plda_pcie_axi4_slv0_aratomop_63_32"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_63_32` writer - u0_plda_pcie_axi4_slv0_aratomop_63_32"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aratomop_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_63_32( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg144.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg144.rs index ebfe682..d4ecc58 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg144.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg144.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_95_64` reader - u0_plda_pcie_axi4_slv0_aratomop_95_64"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_95_64` writer - u0_plda_pcie_axi4_slv0_aratomop_95_64"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aratomop_95_64"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_95_64( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg148.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg148.rs index ea53397..58ea16a 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg148.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg148.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_127_96` reader - u0_plda_pcie_axi4_slv0_aratomop_127_96"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_127_96` writer - u0_plda_pcie_axi4_slv0_aratomop_127_96"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aratomop_127_96"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_127_96( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg152.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg152.rs index dc75b37..e7368cd 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg152.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg152.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_159_128` reader - u0_plda_pcie_axi4_slv0_aratomop_159_128"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_159_128` writer - u0_plda_pcie_axi4_slv0_aratomop_159_128"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aratomop_159_128"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_159_128( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg156.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg156.rs index 44cd4f4..7deb5ac 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg156.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg156.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_191_160` reader - u0_plda_pcie_axi4_slv0_aratomop_191_160"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_191_160` writer - u0_plda_pcie_axi4_slv0_aratomop_191_160"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aratomop_191_160"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_191_160( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg16.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg16.rs index 37cc577..62aa5a5 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg16.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg16.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg160.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg160.rs index 63f2ff0..0c3d846 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg160.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg160.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_223_192` reader - u0_plda_pcie_axi4_slv0_aratomop_223_192"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_223_192` writer - u0_plda_pcie_axi4_slv0_aratomop_223_192"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aratomop_223_192"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_223_192( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg164.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg164.rs index a929878..26a4df4 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg164.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg164.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_255_224` reader - u0_plda_pcie_axi4_slv0_aratomop_255_224"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_255_224` writer - u0_plda_pcie_axi4_slv0_aratomop_255_224"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aratomop_255_224"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_255_224( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg168.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg168.rs index 4805eed..cf6b171 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg168.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg168.rs @@ -5,18 +5,15 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_257_256` reader - u0_plda_pcie_axi4_slv0_aratomop_257_256"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_257_256_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_257_256` writer - u0_plda_pcie_axi4_slv0_aratomop_257_256"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_257_256_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_257_256_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_plda_pcie_axi4_slv0_arfunc` reader - u0_plda_pcie_axi4_slv0_arfunc"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARFUNC_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_arfunc` writer - u0_plda_pcie_axi4_slv0_arfunc"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARFUNC_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 15, O, u16>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARFUNC_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; #[doc = "Field `u0_plda_pcie_axi4_slv0_arregion` reader - u0_plda_pcie_axi4_slv0_arregion"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARREGION_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_arregion` writer - u0_plda_pcie_axi4_slv0_arregion"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARREGION_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 4, O>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARREGION_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:1 - u0_plda_pcie_axi4_slv0_aratomop_257_256"] #[inline(always)] @@ -42,26 +39,30 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_257_256( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_257_256_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_257_256_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_257_256_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_257_256_W::new(self, 0) } #[doc = "Bits 2:16 - u0_plda_pcie_axi4_slv0_arfunc"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_axi4_slv0_arfunc( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARFUNC_W { - U0_PLDA_PCIE_AXI4_SLV0_ARFUNC_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARFUNC_W { + U0_PLDA_PCIE_AXI4_SLV0_ARFUNC_W::new(self, 2) } #[doc = "Bits 17:20 - u0_plda_pcie_axi4_slv0_arregion"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_axi4_slv0_arregion( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARREGION_W { - U0_PLDA_PCIE_AXI4_SLV0_ARREGION_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARREGION_W { + U0_PLDA_PCIE_AXI4_SLV0_ARREGION_W::new(self, 17) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg172.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg172.rs index d4fca62..fe8a65a 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg172.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg172.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aruser_31_0` reader - u0_plda_pcie_axi4_slv0_aruser_31_0"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aruser_31_0` writer - u0_plda_pcie_axi4_slv0_aruser_31_0"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aruser_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aruser_31_0( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W { - U0_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W { + U0_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg176.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg176.rs index a4e74f2..3e00342 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg176.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg176.rs @@ -5,18 +5,15 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aruser_40_32` reader - u0_plda_pcie_axi4_slv0_aruser_40_32"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aruser_40_32` writer - u0_plda_pcie_axi4_slv0_aruser_40_32"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 9, O, u16>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; #[doc = "Field `u0_plda_pcie_axi4_slv0_awfunc` reader - u0_plda_pcie_axi4_slv0_awfunc"] pub type U0_PLDA_PCIE_AXI4_SLV0_AWFUNC_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_awfunc` writer - u0_plda_pcie_axi4_slv0_awfunc"] -pub type U0_PLDA_PCIE_AXI4_SLV0_AWFUNC_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 15, O, u16>; +pub type U0_PLDA_PCIE_AXI4_SLV0_AWFUNC_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; #[doc = "Field `u0_plda_pcie_axi4_slv0_awregion` reader - u0_plda_pcie_axi4_slv0_awregion"] pub type U0_PLDA_PCIE_AXI4_SLV0_AWREGION_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_awregion` writer - u0_plda_pcie_axi4_slv0_awregion"] -pub type U0_PLDA_PCIE_AXI4_SLV0_AWREGION_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 4, O>; +pub type U0_PLDA_PCIE_AXI4_SLV0_AWREGION_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:8 - u0_plda_pcie_axi4_slv0_aruser_40_32"] #[inline(always)] @@ -40,26 +37,30 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aruser_40_32( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W { - U0_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W { + U0_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W::new(self, 0) } #[doc = "Bits 9:23 - u0_plda_pcie_axi4_slv0_awfunc"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_axi4_slv0_awfunc( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_AWFUNC_W { - U0_PLDA_PCIE_AXI4_SLV0_AWFUNC_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_AWFUNC_W { + U0_PLDA_PCIE_AXI4_SLV0_AWFUNC_W::new(self, 9) } #[doc = "Bits 24:27 - u0_plda_pcie_axi4_slv0_awregion"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_axi4_slv0_awregion( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_AWREGION_W { - U0_PLDA_PCIE_AXI4_SLV0_AWREGION_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_AWREGION_W { + U0_PLDA_PCIE_AXI4_SLV0_AWREGION_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg180.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg180.rs index f840e71..dd6d1f4 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg180.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg180.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_awuser_31_0` reader - u0_plda_pcie_axi4_slv0_awuser_31_0"] pub type U0_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_awuser_31_0` writer - u0_plda_pcie_axi4_slv0_awuser_31_0"] -pub type U0_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_awuser_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_awuser_31_0( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W { - U0_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W { + U0_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg184.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg184.rs index 97e85af..003d48c 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg184.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg184.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_awuser_40_32` reader - u0_plda_pcie_axi4_slv0_awuser_40_32"] pub type U0_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_awuser_40_32` writer - u0_plda_pcie_axi4_slv0_awuser_40_32"] -pub type U0_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 9, O, u16>; +pub type U0_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; #[doc = "Field `u0_plda_pcie_axi4_slv0_rderr` reader - u0_plda_pcie_axi4_slv0_rderr"] pub type U0_PLDA_PCIE_AXI4_SLV0_RDERR_R = crate::FieldReader; impl R { @@ -27,10 +26,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_awuser_40_32( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W { - U0_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W { + U0_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg188.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg188.rs index 34d0d9e..3d0bc55 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg188.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg188.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg192.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg192.rs index 2f8132e..b7bd395 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg192.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg192.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_wderr` reader - u0_plda_pcie_axi4_slv0_wderr"] pub type U0_PLDA_PCIE_AXI4_SLV0_WDERR_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_wderr` writer - u0_plda_pcie_axi4_slv0_wderr"] -pub type U0_PLDA_PCIE_AXI4_SLV0_WDERR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type U0_PLDA_PCIE_AXI4_SLV0_WDERR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `u0_plda_pcie_axi4_slvl_arfunc` reader - u0_plda_pcie_axi4_slvl_arfunc"] pub type U0_PLDA_PCIE_AXI4_SLVL_ARFUNC_R = crate::FieldReader; impl R { @@ -26,10 +26,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_wderr( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_WDERR_W { - U0_PLDA_PCIE_AXI4_SLV0_WDERR_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_WDERR_W { + U0_PLDA_PCIE_AXI4_SLV0_WDERR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg196.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg196.rs index d37d50b..281bc93 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg196.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg196.rs @@ -5,26 +5,25 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slvl_awfunc` reader - u0_plda_pcie_axi4_slvl_awfunc"] pub type U0_PLDA_PCIE_AXI4_SLVL_AWFUNC_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slvl_awfunc` writer - u0_plda_pcie_axi4_slvl_awfunc"] -pub type U0_PLDA_PCIE_AXI4_SLVL_AWFUNC_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 15, O, u16>; +pub type U0_PLDA_PCIE_AXI4_SLVL_AWFUNC_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; #[doc = "Field `u0_plda_pcie_bus_width_o` reader - u0_plda_pcie_bus_width_o"] pub type U0_PLDA_PCIE_BUS_WIDTH_O_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_bypass_codec` reader - u0_plda_pcie_bypass_codec"] pub type U0_PLDA_PCIE_BYPASS_CODEC_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_bypass_codec` writer - u0_plda_pcie_bypass_codec"] -pub type U0_PLDA_PCIE_BYPASS_CODEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_BYPASS_CODEC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_ckref_src` reader - u0_plda_pcie_ckref_src"] pub type U0_PLDA_PCIE_CKREF_SRC_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_ckref_src` writer - u0_plda_pcie_ckref_src"] -pub type U0_PLDA_PCIE_CKREF_SRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLDA_PCIE_CKREF_SRC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_plda_pcie_clk_sel` reader - u0_plda_pcie_clk_sel"] pub type U0_PLDA_PCIE_CLK_SEL_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_clk_sel` writer - u0_plda_pcie_clk_sel"] -pub type U0_PLDA_PCIE_CLK_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLDA_PCIE_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_plda_pcie_clkreq` reader - u0_plda_pcie_clkreq"] pub type U0_PLDA_PCIE_CLKREQ_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_clkreq` writer - u0_plda_pcie_clkreq"] -pub type U0_PLDA_PCIE_CLKREQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_CLKREQ_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:14 - u0_plda_pcie_axi4_slvl_awfunc"] #[inline(always)] @@ -63,42 +62,44 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slvl_awfunc( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLVL_AWFUNC_W { - U0_PLDA_PCIE_AXI4_SLVL_AWFUNC_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLVL_AWFUNC_W { + U0_PLDA_PCIE_AXI4_SLVL_AWFUNC_W::new(self, 0) } #[doc = "Bit 17 - u0_plda_pcie_bypass_codec"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_bypass_codec( &mut self, - ) -> U0_PLDA_PCIE_BYPASS_CODEC_W { - U0_PLDA_PCIE_BYPASS_CODEC_W::new(self) + ) -> U0_PLDA_PCIE_BYPASS_CODEC_W { + U0_PLDA_PCIE_BYPASS_CODEC_W::new(self, 17) } #[doc = "Bits 18:19 - u0_plda_pcie_ckref_src"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_ckref_src( &mut self, - ) -> U0_PLDA_PCIE_CKREF_SRC_W { - U0_PLDA_PCIE_CKREF_SRC_W::new(self) + ) -> U0_PLDA_PCIE_CKREF_SRC_W { + U0_PLDA_PCIE_CKREF_SRC_W::new(self, 18) } #[doc = "Bits 20:21 - u0_plda_pcie_clk_sel"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_clk_sel( &mut self, - ) -> U0_PLDA_PCIE_CLK_SEL_W { - U0_PLDA_PCIE_CLK_SEL_W::new(self) + ) -> U0_PLDA_PCIE_CLK_SEL_W { + U0_PLDA_PCIE_CLK_SEL_W::new(self, 20) } #[doc = "Bit 22 - u0_plda_pcie_clkreq"] #[inline(always)] #[must_use] - pub fn u0_plda_pcie_clkreq( - &mut self, - ) -> U0_PLDA_PCIE_CLKREQ_W { - U0_PLDA_PCIE_CLKREQ_W::new(self) + pub fn u0_plda_pcie_clkreq(&mut self) -> U0_PLDA_PCIE_CLKREQ_W { + U0_PLDA_PCIE_CLKREQ_W::new(self, 22) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg20.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg20.rs index 0873486..5d98f12 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg20.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg20.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg200.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg200.rs index c1d847e..598ac36 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg200.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg200.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_31_0` reader - u0_plda_pcie_k_phyparam_31_0"] pub type U0_PLDA_PCIE_K_PHYPARAM_31_0_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_31_0` writer - u0_plda_pcie_k_phyparam_31_0"] -pub type U0_PLDA_PCIE_K_PHYPARAM_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_31_0( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_31_0_W { - U0_PLDA_PCIE_K_PHYPARAM_31_0_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_31_0_W { + U0_PLDA_PCIE_K_PHYPARAM_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg204.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg204.rs index 5bbcdfb..d2b37e7 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg204.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg204.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_63_32` reader - u0_plda_pcie_k_phyparam_63_32"] pub type U0_PLDA_PCIE_K_PHYPARAM_63_32_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_63_32` writer - u0_plda_pcie_k_phyparam_63_32"] -pub type U0_PLDA_PCIE_K_PHYPARAM_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_63_32( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_63_32_W { - U0_PLDA_PCIE_K_PHYPARAM_63_32_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_63_32_W { + U0_PLDA_PCIE_K_PHYPARAM_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg208.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg208.rs index 531f21d..2466778 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg208.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg208.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_95_64` reader - u0_plda_pcie_k_phyparam_95_64"] pub type U0_PLDA_PCIE_K_PHYPARAM_95_64_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_95_64` writer - u0_plda_pcie_k_phyparam_95_64"] -pub type U0_PLDA_PCIE_K_PHYPARAM_95_64_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_95_64_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_95_64"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_95_64( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_95_64_W { - U0_PLDA_PCIE_K_PHYPARAM_95_64_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_95_64_W { + U0_PLDA_PCIE_K_PHYPARAM_95_64_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg212.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg212.rs index 491907b..3e8f2e8 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg212.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg212.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_127_96` reader - u0_plda_pcie_k_phyparam_127_96"] pub type U0_PLDA_PCIE_K_PHYPARAM_127_96_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_127_96` writer - u0_plda_pcie_k_phyparam_127_96"] -pub type U0_PLDA_PCIE_K_PHYPARAM_127_96_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_127_96_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_127_96"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_127_96( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_127_96_W { - U0_PLDA_PCIE_K_PHYPARAM_127_96_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_127_96_W { + U0_PLDA_PCIE_K_PHYPARAM_127_96_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg216.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg216.rs index a68a7f3..118ea10 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg216.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg216.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_159_128` reader - u0_plda_pcie_k_phyparam_159_128"] pub type U0_PLDA_PCIE_K_PHYPARAM_159_128_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_159_128` writer - u0_plda_pcie_k_phyparam_159_128"] -pub type U0_PLDA_PCIE_K_PHYPARAM_159_128_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_159_128_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_159_128"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_159_128( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_159_128_W { - U0_PLDA_PCIE_K_PHYPARAM_159_128_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_159_128_W { + U0_PLDA_PCIE_K_PHYPARAM_159_128_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg220.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg220.rs index cda6df2..38e3cd3 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg220.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg220.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_191_160` reader - u0_plda_pcie_k_phyparam_191_160"] pub type U0_PLDA_PCIE_K_PHYPARAM_191_160_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_191_160` writer - u0_plda_pcie_k_phyparam_191_160"] -pub type U0_PLDA_PCIE_K_PHYPARAM_191_160_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_191_160_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_191_160"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_191_160( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_191_160_W { - U0_PLDA_PCIE_K_PHYPARAM_191_160_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_191_160_W { + U0_PLDA_PCIE_K_PHYPARAM_191_160_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg224.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg224.rs index a907bba..791783f 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg224.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg224.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_223_192` reader - u0_plda_pcie_k_phyparam_223_192"] pub type U0_PLDA_PCIE_K_PHYPARAM_223_192_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_223_192` writer - u0_plda_pcie_k_phyparam_223_192"] -pub type U0_PLDA_PCIE_K_PHYPARAM_223_192_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_223_192_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_223_192"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_223_192( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_223_192_W { - U0_PLDA_PCIE_K_PHYPARAM_223_192_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_223_192_W { + U0_PLDA_PCIE_K_PHYPARAM_223_192_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg228.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg228.rs index d00df8e..f108222 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg228.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg228.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_255_224` reader - u0_plda_pcie_k_phyparam_255_224"] pub type U0_PLDA_PCIE_K_PHYPARAM_255_224_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_255_224` writer - u0_plda_pcie_k_phyparam_255_224"] -pub type U0_PLDA_PCIE_K_PHYPARAM_255_224_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_255_224_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_255_224"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_255_224( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_255_224_W { - U0_PLDA_PCIE_K_PHYPARAM_255_224_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_255_224_W { + U0_PLDA_PCIE_K_PHYPARAM_255_224_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg232.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg232.rs index b885c46..19b95e2 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg232.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg232.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_287_256` reader - u0_plda_pcie_k_phyparam_287_256"] pub type U0_PLDA_PCIE_K_PHYPARAM_287_256_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_287_256` writer - u0_plda_pcie_k_phyparam_287_256"] -pub type U0_PLDA_PCIE_K_PHYPARAM_287_256_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_287_256_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_287_256"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_287_256( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_287_256_W { - U0_PLDA_PCIE_K_PHYPARAM_287_256_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_287_256_W { + U0_PLDA_PCIE_K_PHYPARAM_287_256_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg236.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg236.rs index 358059f..770d70a 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg236.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg236.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_319_288` reader - u0_plda_pcie_k_phyparam_319_288"] pub type U0_PLDA_PCIE_K_PHYPARAM_319_288_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_319_288` writer - u0_plda_pcie_k_phyparam_319_288"] -pub type U0_PLDA_PCIE_K_PHYPARAM_319_288_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_319_288_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_319_288"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_319_288( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_319_288_W { - U0_PLDA_PCIE_K_PHYPARAM_319_288_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_319_288_W { + U0_PLDA_PCIE_K_PHYPARAM_319_288_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg24.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg24.rs index c49afbe..6ecfa1c 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg24.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg24.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_cdn_usb_xhci_debug_sel` reader - u0_cdn_usb_xhci_debug_sel"] pub type U0_CDN_USB_XHCI_DEBUG_SEL_R = crate::FieldReader; #[doc = "Field `u0_cdn_usb_xhci_debug_sel` writer - u0_cdn_usb_xhci_debug_sel"] -pub type U0_CDN_USB_XHCI_DEBUG_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_CDN_USB_XHCI_DEBUG_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_cdn_usb_xhci_main_power_off_ack` reader - u0_cdn_usb_xhci_main_power_off_ack"] pub type U0_CDN_USB_XHCI_MAIN_POWER_OFF_ACK_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_main_power_off_req` reader - u0_cdn_usb_xhci_main_power_off_req"] @@ -13,13 +13,13 @@ pub type U0_CDN_USB_XHCI_MAIN_POWER_OFF_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_main_power_on_ready` reader - u0_cdn_usb_xhci_main_power_on_ready"] pub type U0_CDN_USB_XHCI_MAIN_POWER_ON_READY_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_main_power_on_ready` writer - u0_cdn_usb_xhci_main_power_on_ready"] -pub type U0_CDN_USB_XHCI_MAIN_POWER_ON_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_XHCI_MAIN_POWER_ON_READY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_xhci_main_power_on_req` reader - u0_cdn_usb_xhci_main_power_on_req"] pub type U0_CDN_USB_XHCI_MAIN_POWER_ON_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_main_power_on_valid` reader - u0_cdn_usb_xhci_main_power_on_valid"] pub type U0_CDN_USB_XHCI_MAIN_POWER_ON_VALID_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_main_power_on_valid` writer - u0_cdn_usb_xhci_main_power_on_valid"] -pub type U0_CDN_USB_XHCI_MAIN_POWER_ON_VALID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_XHCI_MAIN_POWER_ON_VALID_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_xhci_power_off_ack` reader - u0_cdn_usb_xhci_power_off_ack"] pub type U0_CDN_USB_XHCI_POWER_OFF_ACK_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_power_off_ready` reader - u0_cdn_usb_xhci_power_off_ready"] @@ -27,7 +27,7 @@ pub type U0_CDN_USB_XHCI_POWER_OFF_READY_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_power_off_req` reader - u0_cdn_usb_xhci_power_off_req"] pub type U0_CDN_USB_XHCI_POWER_OFF_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_power_off_req` writer - u0_cdn_usb_xhci_power_off_req"] -pub type U0_CDN_USB_XHCI_POWER_OFF_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_XHCI_POWER_OFF_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_xhci_power_on_ready` reader - u0_cdn_usb_xhci_power_on_ready"] pub type U0_CDN_USB_XHCI_POWER_ON_READY_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_power_on_req` reader - u0_cdn_usb_xhci_power_on_req"] @@ -35,7 +35,7 @@ pub type U0_CDN_USB_XHCI_POWER_ON_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_power_on_valid` reader - u0_cdn_usb_xhci_power_on_valid"] pub type U0_CDN_USB_XHCI_POWER_ON_VALID_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_power_on_valid` writer - u0_cdn_usb_xhci_power_on_valid"] -pub type U0_CDN_USB_XHCI_POWER_ON_VALID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_XHCI_POWER_ON_VALID_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_e2_sft7110_cease_from_tile_0` reader - u0_e2_sft7110_cease_from_tile_0"] pub type U0_E2_SFT7110_CEASE_FROM_TILE_0_R = crate::BitReader; #[doc = "Field `u0_e2_sft7110_debug_from_tile_0` reader - u0_e2_sft7110_debug_from_tile_0"] @@ -125,42 +125,46 @@ impl W { #[must_use] pub fn u0_cdn_usb_xhci_debug_sel( &mut self, - ) -> U0_CDN_USB_XHCI_DEBUG_SEL_W { - U0_CDN_USB_XHCI_DEBUG_SEL_W::new(self) + ) -> U0_CDN_USB_XHCI_DEBUG_SEL_W { + U0_CDN_USB_XHCI_DEBUG_SEL_W::new(self, 0) } #[doc = "Bit 7 - u0_cdn_usb_xhci_main_power_on_ready"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_xhci_main_power_on_ready( &mut self, - ) -> U0_CDN_USB_XHCI_MAIN_POWER_ON_READY_W { - U0_CDN_USB_XHCI_MAIN_POWER_ON_READY_W::new(self) + ) -> U0_CDN_USB_XHCI_MAIN_POWER_ON_READY_W { + U0_CDN_USB_XHCI_MAIN_POWER_ON_READY_W::new(self, 7) } #[doc = "Bit 9 - u0_cdn_usb_xhci_main_power_on_valid"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_xhci_main_power_on_valid( &mut self, - ) -> U0_CDN_USB_XHCI_MAIN_POWER_ON_VALID_W { - U0_CDN_USB_XHCI_MAIN_POWER_ON_VALID_W::new(self) + ) -> U0_CDN_USB_XHCI_MAIN_POWER_ON_VALID_W { + U0_CDN_USB_XHCI_MAIN_POWER_ON_VALID_W::new(self, 9) } #[doc = "Bit 12 - u0_cdn_usb_xhci_power_off_req"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_xhci_power_off_req( &mut self, - ) -> U0_CDN_USB_XHCI_POWER_OFF_REQ_W { - U0_CDN_USB_XHCI_POWER_OFF_REQ_W::new(self) + ) -> U0_CDN_USB_XHCI_POWER_OFF_REQ_W { + U0_CDN_USB_XHCI_POWER_OFF_REQ_W::new(self, 12) } #[doc = "Bit 15 - u0_cdn_usb_xhci_power_on_valid"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_xhci_power_on_valid( &mut self, - ) -> U0_CDN_USB_XHCI_POWER_ON_VALID_W { - U0_CDN_USB_XHCI_POWER_ON_VALID_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_CDN_USB_XHCI_POWER_ON_VALID_W { + U0_CDN_USB_XHCI_POWER_ON_VALID_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg240.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg240.rs index 993cc37..7cdce70 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg240.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg240.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_351_320` reader - u0_plda_pcie_k_phyparam_351_320"] pub type U0_PLDA_PCIE_K_PHYPARAM_351_320_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_351_320` writer - u0_plda_pcie_k_phyparam_351_320"] -pub type U0_PLDA_PCIE_K_PHYPARAM_351_320_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_351_320_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_351_320"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_351_320( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_351_320_W { - U0_PLDA_PCIE_K_PHYPARAM_351_320_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_351_320_W { + U0_PLDA_PCIE_K_PHYPARAM_351_320_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg244.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg244.rs index 8c7599a..80a76d8 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg244.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg244.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_383_352` reader - u0_plda_pcie_k_phyparam_383_352"] pub type U0_PLDA_PCIE_K_PHYPARAM_383_352_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_383_352` writer - u0_plda_pcie_k_phyparam_383_352"] -pub type U0_PLDA_PCIE_K_PHYPARAM_383_352_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_383_352_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_383_352"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_383_352( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_383_352_W { - U0_PLDA_PCIE_K_PHYPARAM_383_352_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_383_352_W { + U0_PLDA_PCIE_K_PHYPARAM_383_352_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg248.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg248.rs index 70d62ce..efaec9f 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg248.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg248.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_415_384` reader - u0_plda_pcie_k_phyparam_415_384"] pub type U0_PLDA_PCIE_K_PHYPARAM_415_384_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_415_384` writer - u0_plda_pcie_k_phyparam_415_384"] -pub type U0_PLDA_PCIE_K_PHYPARAM_415_384_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_415_384_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_415_384"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_415_384( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_415_384_W { - U0_PLDA_PCIE_K_PHYPARAM_415_384_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_415_384_W { + U0_PLDA_PCIE_K_PHYPARAM_415_384_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg252.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg252.rs index 0cd1a0f..d87d0a8 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg252.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg252.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_447_416` reader - u0_plda_pcie_k_phyparam_447_416"] pub type U0_PLDA_PCIE_K_PHYPARAM_447_416_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_447_416` writer - u0_plda_pcie_k_phyparam_447_416"] -pub type U0_PLDA_PCIE_K_PHYPARAM_447_416_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_447_416_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_447_416"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_447_416( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_447_416_W { - U0_PLDA_PCIE_K_PHYPARAM_447_416_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_447_416_W { + U0_PLDA_PCIE_K_PHYPARAM_447_416_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg256.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg256.rs index b5f63c9..1e2030f 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg256.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg256.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_479_448` reader - u0_plda_pcie_k_phyparam_479_448"] pub type U0_PLDA_PCIE_K_PHYPARAM_479_448_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_479_448` writer - u0_plda_pcie_k_phyparam_479_448"] -pub type U0_PLDA_PCIE_K_PHYPARAM_479_448_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_479_448_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_479_448"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_479_448( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_479_448_W { - U0_PLDA_PCIE_K_PHYPARAM_479_448_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_479_448_W { + U0_PLDA_PCIE_K_PHYPARAM_479_448_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg260.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg260.rs index 5ba063c..534d29d 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg260.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg260.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_511_480` reader - u0_plda_pcie_k_phyparam_511_480"] pub type U0_PLDA_PCIE_K_PHYPARAM_511_480_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_511_480` writer - u0_plda_pcie_k_phyparam_511_480"] -pub type U0_PLDA_PCIE_K_PHYPARAM_511_480_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_511_480_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_511_480"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_511_480( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_511_480_W { - U0_PLDA_PCIE_K_PHYPARAM_511_480_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_511_480_W { + U0_PLDA_PCIE_K_PHYPARAM_511_480_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg264.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg264.rs index cd6f826..5d4c4bc 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg264.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg264.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_543_512` reader - u0_plda_pcie_k_phyparam_543_512"] pub type U0_PLDA_PCIE_K_PHYPARAM_543_512_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_543_512` writer - u0_plda_pcie_k_phyparam_543_512"] -pub type U0_PLDA_PCIE_K_PHYPARAM_543_512_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_543_512_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_543_512"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_543_512( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_543_512_W { - U0_PLDA_PCIE_K_PHYPARAM_543_512_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_543_512_W { + U0_PLDA_PCIE_K_PHYPARAM_543_512_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg268.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg268.rs index 4e9b839..a34dc7b 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg268.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg268.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_575_544` reader - u0_plda_pcie_k_phyparam_575_544"] pub type U0_PLDA_PCIE_K_PHYPARAM_575_544_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_575_544` writer - u0_plda_pcie_k_phyparam_575_544"] -pub type U0_PLDA_PCIE_K_PHYPARAM_575_544_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_575_544_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_575_544"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_575_544( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_575_544_W { - U0_PLDA_PCIE_K_PHYPARAM_575_544_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_575_544_W { + U0_PLDA_PCIE_K_PHYPARAM_575_544_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg272.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg272.rs index c3c56ae..cdab83a 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg272.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg272.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_607_576` reader - u0_plda_pcie_k_phyparam_607_576"] pub type U0_PLDA_PCIE_K_PHYPARAM_607_576_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_607_576` writer - u0_plda_pcie_k_phyparam_607_576"] -pub type U0_PLDA_PCIE_K_PHYPARAM_607_576_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_607_576_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_607_576"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_607_576( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_607_576_W { - U0_PLDA_PCIE_K_PHYPARAM_607_576_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_607_576_W { + U0_PLDA_PCIE_K_PHYPARAM_607_576_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg276.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg276.rs index d1993a0..1ec64a9 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg276.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg276.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_639_608` reader - u0_plda_pcie_k_phyparam_639_608"] pub type U0_PLDA_PCIE_K_PHYPARAM_639_608_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_639_608` writer - u0_plda_pcie_k_phyparam_639_608"] -pub type U0_PLDA_PCIE_K_PHYPARAM_639_608_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_639_608_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_639_608"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_639_608( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_639_608_W { - U0_PLDA_PCIE_K_PHYPARAM_639_608_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_639_608_W { + U0_PLDA_PCIE_K_PHYPARAM_639_608_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg28.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg28.rs index f03ff50..2d392e1 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg28.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg28.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_e2_sft7110_nmi_0_rnmi_exception_vector` reader - u0_e2_sft7110_nmi_0_rnmi_exception_vector"] pub type U0_E2_SFT7110_NMI_0_RNMI_EXCEPTION_VECTOR_R = crate::FieldReader; #[doc = "Field `u0_e2_sft7110_nmi_0_rnmi_exception_vector` writer - u0_e2_sft7110_nmi_0_rnmi_exception_vector"] -pub type U0_E2_SFT7110_NMI_0_RNMI_EXCEPTION_VECTOR_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_E2_SFT7110_NMI_0_RNMI_EXCEPTION_VECTOR_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_e2_sft7110_nmi_0_rnmi_exception_vector"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_e2_sft7110_nmi_0_rnmi_exception_vector( &mut self, - ) -> U0_E2_SFT7110_NMI_0_RNMI_EXCEPTION_VECTOR_W { - U0_E2_SFT7110_NMI_0_RNMI_EXCEPTION_VECTOR_W::new(self) + ) -> U0_E2_SFT7110_NMI_0_RNMI_EXCEPTION_VECTOR_W { + U0_E2_SFT7110_NMI_0_RNMI_EXCEPTION_VECTOR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg280.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg280.rs index e11240d..f0d3af8 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg280.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg280.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_671_640` reader - u0_plda_pcie_k_phyparam_671_640"] pub type U0_PLDA_PCIE_K_PHYPARAM_671_640_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_671_640` writer - u0_plda_pcie_k_phyparam_671_640"] -pub type U0_PLDA_PCIE_K_PHYPARAM_671_640_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_671_640_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_671_640"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_671_640( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_671_640_W { - U0_PLDA_PCIE_K_PHYPARAM_671_640_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_671_640_W { + U0_PLDA_PCIE_K_PHYPARAM_671_640_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg284.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg284.rs index 605b20d..efaf516 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg284.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg284.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_703_672` reader - u0_plda_pcie_k_phyparam_703_672"] pub type U0_PLDA_PCIE_K_PHYPARAM_703_672_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_703_672` writer - u0_plda_pcie_k_phyparam_703_672"] -pub type U0_PLDA_PCIE_K_PHYPARAM_703_672_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_703_672_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_703_672"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_703_672( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_703_672_W { - U0_PLDA_PCIE_K_PHYPARAM_703_672_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_703_672_W { + U0_PLDA_PCIE_K_PHYPARAM_703_672_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg288.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg288.rs index 08c3c6c..a589513 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg288.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg288.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_735_704` reader - u0_plda_pcie_k_phyparam_735_704"] pub type U0_PLDA_PCIE_K_PHYPARAM_735_704_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_735_704` writer - u0_plda_pcie_k_phyparam_735_704"] -pub type U0_PLDA_PCIE_K_PHYPARAM_735_704_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_735_704_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_735_704"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_735_704( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_735_704_W { - U0_PLDA_PCIE_K_PHYPARAM_735_704_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_735_704_W { + U0_PLDA_PCIE_K_PHYPARAM_735_704_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg292.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg292.rs index 9120a9d..039ebee 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg292.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg292.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_767_736` reader - u0_plda_pcie_k_phyparam_767_736"] pub type U0_PLDA_PCIE_K_PHYPARAM_767_736_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_767_736` writer - u0_plda_pcie_k_phyparam_767_736"] -pub type U0_PLDA_PCIE_K_PHYPARAM_767_736_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_767_736_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_767_736"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_767_736( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_767_736_W { - U0_PLDA_PCIE_K_PHYPARAM_767_736_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_767_736_W { + U0_PLDA_PCIE_K_PHYPARAM_767_736_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg296.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg296.rs index 43a2c2d..cd11754 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg296.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg296.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_799_768` reader - u0_plda_pcie_k_phyparam_799_768"] pub type U0_PLDA_PCIE_K_PHYPARAM_799_768_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_799_768` writer - u0_plda_pcie_k_phyparam_799_768"] -pub type U0_PLDA_PCIE_K_PHYPARAM_799_768_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_799_768_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_799_768"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_799_768( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_799_768_W { - U0_PLDA_PCIE_K_PHYPARAM_799_768_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_799_768_W { + U0_PLDA_PCIE_K_PHYPARAM_799_768_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg300.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg300.rs index 595421a..a028736 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg300.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg300.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_831_800` reader - u0_plda_pcie_k_phyparam_831_800"] pub type U0_PLDA_PCIE_K_PHYPARAM_831_800_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_831_800` writer - u0_plda_pcie_k_phyparam_831_800"] -pub type U0_PLDA_PCIE_K_PHYPARAM_831_800_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_831_800_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_831_800"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_831_800( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_831_800_W { - U0_PLDA_PCIE_K_PHYPARAM_831_800_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_831_800_W { + U0_PLDA_PCIE_K_PHYPARAM_831_800_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg304.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg304.rs index 595d2be..0d116b1 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg304.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg304.rs @@ -5,18 +5,17 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_839_832` reader - u0_plda_pcie_k_phyparam_839_832"] pub type U0_PLDA_PCIE_K_PHYPARAM_839_832_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_839_832` writer - u0_plda_pcie_k_phyparam_839_832"] -pub type U0_PLDA_PCIE_K_PHYPARAM_839_832_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 8, O>; +pub type U0_PLDA_PCIE_K_PHYPARAM_839_832_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `u0_plda_pcie_k_rp_nep` reader - u0_plda_pcie_k_rp_nep"] pub type U0_PLDA_PCIE_K_RP_NEP_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_k_rp_nep` writer - u0_plda_pcie_k_rp_nep"] -pub type U0_PLDA_PCIE_K_RP_NEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_K_RP_NEP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_l1sub_entack` reader - u0_plda_pcie_l1sub_entack"] pub type U0_PLDA_PCIE_L1SUB_ENTACK_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_l1sub_entreq` reader - u0_plda_pcie_l1sub_entreq"] pub type U0_PLDA_PCIE_L1SUB_ENTREQ_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_l1sub_entreq` writer - u0_plda_pcie_l1sub_entreq"] -pub type U0_PLDA_PCIE_L1SUB_ENTREQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_L1SUB_ENTREQ_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - u0_plda_pcie_k_phyparam_839_832"] #[inline(always)] @@ -45,26 +44,30 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_839_832( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_839_832_W { - U0_PLDA_PCIE_K_PHYPARAM_839_832_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_839_832_W { + U0_PLDA_PCIE_K_PHYPARAM_839_832_W::new(self, 0) } #[doc = "Bit 8 - u0_plda_pcie_k_rp_nep"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_k_rp_nep( &mut self, - ) -> U0_PLDA_PCIE_K_RP_NEP_W { - U0_PLDA_PCIE_K_RP_NEP_W::new(self) + ) -> U0_PLDA_PCIE_K_RP_NEP_W { + U0_PLDA_PCIE_K_RP_NEP_W::new(self, 8) } #[doc = "Bit 10 - u0_plda_pcie_l1sub_entreq"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_l1sub_entreq( &mut self, - ) -> U0_PLDA_PCIE_L1SUB_ENTREQ_W { - U0_PLDA_PCIE_L1SUB_ENTREQ_W::new(self) + ) -> U0_PLDA_PCIE_L1SUB_ENTREQ_W { + U0_PLDA_PCIE_L1SUB_ENTREQ_W::new(self, 10) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg308.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg308.rs index 5526eab..2e356df 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg308.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg308.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_local_interrupt_in` reader - u0_plda_pcie_local_interrupt_in"] pub type U0_PLDA_PCIE_LOCAL_INTERRUPT_IN_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_local_interrupt_in` writer - u0_plda_pcie_local_interrupt_in"] -pub type U0_PLDA_PCIE_LOCAL_INTERRUPT_IN_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_LOCAL_INTERRUPT_IN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_local_interrupt_in"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_local_interrupt_in( &mut self, - ) -> U0_PLDA_PCIE_LOCAL_INTERRUPT_IN_W { - U0_PLDA_PCIE_LOCAL_INTERRUPT_IN_W::new(self) + ) -> U0_PLDA_PCIE_LOCAL_INTERRUPT_IN_W { + U0_PLDA_PCIE_LOCAL_INTERRUPT_IN_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg312.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg312.rs index c592a42..8983459 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg312.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg312.rs @@ -5,28 +5,27 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_mperstn` reader - u0_plda_pcie_mperstn"] pub type U0_PLDA_PCIE_MPERSTN_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_mperstn` writer - u0_plda_pcie_mperstn"] -pub type U0_PLDA_PCIE_MPERSTN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_MPERSTN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_pcie_ebuf_mode` reader - u0_plda_pcie_pcie_ebuf_mode"] pub type U0_PLDA_PCIE_PCIE_EBUF_MODE_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_pcie_ebuf_mode` writer - u0_plda_pcie_pcie_ebuf_mode"] -pub type U0_PLDA_PCIE_PCIE_EBUF_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_PCIE_EBUF_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_pcie_phy_test_cfg` reader - u0_plda_pcie_pcie_phy_test_cfg"] pub type U0_PLDA_PCIE_PCIE_PHY_TEST_CFG_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_pcie_phy_test_cfg` writer - u0_plda_pcie_pcie_phy_test_cfg"] -pub type U0_PLDA_PCIE_PCIE_PHY_TEST_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 23, O, u32>; +pub type U0_PLDA_PCIE_PCIE_PHY_TEST_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>; #[doc = "Field `u0_plda_pcie_pcie_rx_eq_training` reader - u0_plda_pcie_pcie_rx_eq_training"] pub type U0_PLDA_PCIE_PCIE_RX_EQ_TRAINING_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_pcie_rx_eq_training` writer - u0_plda_pcie_pcie_rx_eq_training"] -pub type U0_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_pcie_rxterm_en` reader - u0_plda_pcie_pcie_rxterm_en"] pub type U0_PLDA_PCIE_PCIE_RXTERM_EN_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_pcie_rxterm_en` writer - u0_plda_pcie_pcie_rxterm_en"] -pub type U0_PLDA_PCIE_PCIE_RXTERM_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_PCIE_RXTERM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_pcie_tx_onezeros` reader - u0_plda_pcie_pcie_tx_onezeros"] pub type U0_PLDA_PCIE_PCIE_TX_ONEZEROS_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_pcie_tx_onezeros` writer - u0_plda_pcie_pcie_tx_onezeros"] -pub type U0_PLDA_PCIE_PCIE_TX_ONEZEROS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_PCIE_TX_ONEZEROS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - u0_plda_pcie_mperstn"] #[inline(always)] @@ -65,50 +64,54 @@ impl W { #[must_use] pub fn u0_plda_pcie_mperstn( &mut self, - ) -> U0_PLDA_PCIE_MPERSTN_W { - U0_PLDA_PCIE_MPERSTN_W::new(self) + ) -> U0_PLDA_PCIE_MPERSTN_W { + U0_PLDA_PCIE_MPERSTN_W::new(self, 0) } #[doc = "Bit 1 - u0_plda_pcie_pcie_ebuf_mode"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_pcie_ebuf_mode( &mut self, - ) -> U0_PLDA_PCIE_PCIE_EBUF_MODE_W { - U0_PLDA_PCIE_PCIE_EBUF_MODE_W::new(self) + ) -> U0_PLDA_PCIE_PCIE_EBUF_MODE_W { + U0_PLDA_PCIE_PCIE_EBUF_MODE_W::new(self, 1) } #[doc = "Bits 2:24 - u0_plda_pcie_pcie_phy_test_cfg"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_pcie_phy_test_cfg( &mut self, - ) -> U0_PLDA_PCIE_PCIE_PHY_TEST_CFG_W { - U0_PLDA_PCIE_PCIE_PHY_TEST_CFG_W::new(self) + ) -> U0_PLDA_PCIE_PCIE_PHY_TEST_CFG_W { + U0_PLDA_PCIE_PCIE_PHY_TEST_CFG_W::new(self, 2) } #[doc = "Bit 25 - u0_plda_pcie_pcie_rx_eq_training"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_pcie_rx_eq_training( &mut self, - ) -> U0_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W { - U0_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W::new(self) + ) -> U0_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W { + U0_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W::new(self, 25) } #[doc = "Bit 26 - u0_plda_pcie_pcie_rxterm_en"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_pcie_rxterm_en( &mut self, - ) -> U0_PLDA_PCIE_PCIE_RXTERM_EN_W { - U0_PLDA_PCIE_PCIE_RXTERM_EN_W::new(self) + ) -> U0_PLDA_PCIE_PCIE_RXTERM_EN_W { + U0_PLDA_PCIE_PCIE_RXTERM_EN_W::new(self, 26) } #[doc = "Bit 27 - u0_plda_pcie_pcie_tx_onezeros"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_pcie_tx_onezeros( &mut self, - ) -> U0_PLDA_PCIE_PCIE_TX_ONEZEROS_W { - U0_PLDA_PCIE_PCIE_TX_ONEZEROS_W::new(self) + ) -> U0_PLDA_PCIE_PCIE_TX_ONEZEROS_W { + U0_PLDA_PCIE_PCIE_TX_ONEZEROS_W::new(self, 27) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg316.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg316.rs index 3f2e652..2554ee2 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg316.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg316.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_pf0_offset` reader - u0_plda_pcie_pf0_offset"] pub type U0_PLDA_PCIE_PF0_OFFSET_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_pf0_offset` writer - u0_plda_pcie_pf0_offset"] -pub type U0_PLDA_PCIE_PF0_OFFSET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; +pub type U0_PLDA_PCIE_PF0_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; impl R { #[doc = "Bits 0:19 - u0_plda_pcie_pf0_offset"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_pf0_offset( &mut self, - ) -> U0_PLDA_PCIE_PF0_OFFSET_W { - U0_PLDA_PCIE_PF0_OFFSET_W::new(self) + ) -> U0_PLDA_PCIE_PF0_OFFSET_W { + U0_PLDA_PCIE_PF0_OFFSET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg32.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg32.rs index b78cbcf..ca43a2e 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg32.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg32.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_e2_sft7110_nmi_0_rnmi_interrupt_vector` reader - u0_e2_sft7110_nmi_0_rnmi_interrupt_vector"] pub type U0_E2_SFT7110_NMI_0_RNMI_INTERRUPT_VECTOR_R = crate::FieldReader; #[doc = "Field `u0_e2_sft7110_nmi_0_rnmi_interrupt_vector` writer - u0_e2_sft7110_nmi_0_rnmi_interrupt_vector"] -pub type U0_E2_SFT7110_NMI_0_RNMI_INTERRUPT_VECTOR_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_E2_SFT7110_NMI_0_RNMI_INTERRUPT_VECTOR_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_e2_sft7110_nmi_0_rnmi_interrupt_vector"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_e2_sft7110_nmi_0_rnmi_interrupt_vector( &mut self, - ) -> U0_E2_SFT7110_NMI_0_RNMI_INTERRUPT_VECTOR_W { - U0_E2_SFT7110_NMI_0_RNMI_INTERRUPT_VECTOR_W::new(self) + ) -> U0_E2_SFT7110_NMI_0_RNMI_INTERRUPT_VECTOR_W { + U0_E2_SFT7110_NMI_0_RNMI_INTERRUPT_VECTOR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg320.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg320.rs index 1a1370d..918e7c8 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg320.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg320.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_pf1_offset` reader - u0_plda_pcie_pf1_offset"] pub type U0_PLDA_PCIE_PF1_OFFSET_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_pf1_offset` writer - u0_plda_pcie_pf1_offset"] -pub type U0_PLDA_PCIE_PF1_OFFSET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; +pub type U0_PLDA_PCIE_PF1_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; impl R { #[doc = "Bits 0:19 - u0_plda_pcie_pf1_offset"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_pf1_offset( &mut self, - ) -> U0_PLDA_PCIE_PF1_OFFSET_W { - U0_PLDA_PCIE_PF1_OFFSET_W::new(self) + ) -> U0_PLDA_PCIE_PF1_OFFSET_W { + U0_PLDA_PCIE_PF1_OFFSET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg324.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg324.rs index 57b9bf4..83abed6 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg324.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg324.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_pf2_offset` reader - u0_plda_pcie_pf2_offset"] pub type U0_PLDA_PCIE_PF2_OFFSET_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_pf2_offset` writer - u0_plda_pcie_pf2_offset"] -pub type U0_PLDA_PCIE_PF2_OFFSET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; +pub type U0_PLDA_PCIE_PF2_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; impl R { #[doc = "Bits 0:19 - u0_plda_pcie_pf2_offset"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_pf2_offset( &mut self, - ) -> U0_PLDA_PCIE_PF2_OFFSET_W { - U0_PLDA_PCIE_PF2_OFFSET_W::new(self) + ) -> U0_PLDA_PCIE_PF2_OFFSET_W { + U0_PLDA_PCIE_PF2_OFFSET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg328.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg328.rs index 2b56b64..cada965 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg328.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg328.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_pf3_offset` reader - u0_plda_pcie_pf3_offset"] pub type U0_PLDA_PCIE_PF3_OFFSET_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_pf3_offset` writer - u0_plda_pcie_pf3_offset"] -pub type U0_PLDA_PCIE_PF3_OFFSET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; +pub type U0_PLDA_PCIE_PF3_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; #[doc = "Field `u0_plda_pcie_phy_mode` reader - u0_plda_pcie_phy_mode"] pub type U0_PLDA_PCIE_PHY_MODE_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_phy_mode` writer - u0_plda_pcie_phy_mode"] -pub type U0_PLDA_PCIE_PHY_MODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLDA_PCIE_PHY_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_plda_pcie_pl_clkrem_allow` reader - u0_plda_pcie_pl_clkrem_allow"] pub type U0_PLDA_PCIE_PL_CLKREM_ALLOW_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_pl_clkrem_allow` writer - u0_plda_pcie_pl_clkrem_allow"] -pub type U0_PLDA_PCIE_PL_CLKREM_ALLOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_PL_CLKREM_ALLOW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_pl_clkreq_oen` reader - u0_plda_pcie_pl_clkreq_oen"] pub type U0_PLDA_PCIE_PL_CLKREQ_OEN_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_pl_equ_phase` reader - u0_plda_pcie_pl_equ_phase"] @@ -58,26 +58,30 @@ impl W { #[must_use] pub fn u0_plda_pcie_pf3_offset( &mut self, - ) -> U0_PLDA_PCIE_PF3_OFFSET_W { - U0_PLDA_PCIE_PF3_OFFSET_W::new(self) + ) -> U0_PLDA_PCIE_PF3_OFFSET_W { + U0_PLDA_PCIE_PF3_OFFSET_W::new(self, 0) } #[doc = "Bits 20:21 - u0_plda_pcie_phy_mode"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_phy_mode( &mut self, - ) -> U0_PLDA_PCIE_PHY_MODE_W { - U0_PLDA_PCIE_PHY_MODE_W::new(self) + ) -> U0_PLDA_PCIE_PHY_MODE_W { + U0_PLDA_PCIE_PHY_MODE_W::new(self, 20) } #[doc = "Bit 22 - u0_plda_pcie_pl_clkrem_allow"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_pl_clkrem_allow( &mut self, - ) -> U0_PLDA_PCIE_PL_CLKREM_ALLOW_W { - U0_PLDA_PCIE_PL_CLKREM_ALLOW_W::new(self) + ) -> U0_PLDA_PCIE_PL_CLKREM_ALLOW_W { + U0_PLDA_PCIE_PL_CLKREM_ALLOW_W::new(self, 22) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg332.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg332.rs index 91c5625..711bf58 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg332.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg332.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg336.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg336.rs index 36a70a2..e3bfc4e 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg336.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg336.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg340.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg340.rs index a6bff6a..46a79e1 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg340.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg340.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg344.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg344.rs index 8541bb7..be9e5a0 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg344.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg344.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg348.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg348.rs index 7030ca6..7c00d97 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg348.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg348.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg352.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg352.rs index 123e71d..0ec9da5 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg352.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg352.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_pl_wake_in` reader - u0_plda_pcie_pl_wake_in"] pub type U0_PLDA_PCIE_PL_WAKE_IN_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_pl_wake_in` writer - u0_plda_pcie_pl_wake_in"] -pub type U0_PLDA_PCIE_PL_WAKE_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_PL_WAKE_IN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_pl_wake_oen` reader - u0_plda_pcie_pl_wake_oen"] pub type U0_PLDA_PCIE_PL_WAKE_OEN_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_rx_standby_0` reader - u0_plda_pcie_rx_standby_0"] @@ -33,10 +33,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_pl_wake_in( &mut self, - ) -> U0_PLDA_PCIE_PL_WAKE_IN_W { - U0_PLDA_PCIE_PL_WAKE_IN_W::new(self) + ) -> U0_PLDA_PCIE_PL_WAKE_IN_W { + U0_PLDA_PCIE_PL_WAKE_IN_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg356.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg356.rs index 78e62ba..66e8f21 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg356.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg356.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_test_in_31_0` reader - u0_plda_pcie_test_in_31_0"] pub type U0_PLDA_PCIE_TEST_IN_31_0_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_test_in_31_0` writer - u0_plda_pcie_test_in_31_0"] -pub type U0_PLDA_PCIE_TEST_IN_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_TEST_IN_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_test_in_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_test_in_31_0( &mut self, - ) -> U0_PLDA_PCIE_TEST_IN_31_0_W { - U0_PLDA_PCIE_TEST_IN_31_0_W::new(self) + ) -> U0_PLDA_PCIE_TEST_IN_31_0_W { + U0_PLDA_PCIE_TEST_IN_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg36.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg36.rs index 79e2657..b468b57 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg36.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg36.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_e2_sft7110_reset_vector_0` reader - u0_e2_sft7110_reset_vector_0"] pub type U0_E2_SFT7110_RESET_VECTOR_0_R = crate::FieldReader; #[doc = "Field `u0_e2_sft7110_reset_vector_0` writer - u0_e2_sft7110_reset_vector_0"] -pub type U0_E2_SFT7110_RESET_VECTOR_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_E2_SFT7110_RESET_VECTOR_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_e2_sft7110_reset_vector_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_e2_sft7110_reset_vector_0( &mut self, - ) -> U0_E2_SFT7110_RESET_VECTOR_0_W { - U0_E2_SFT7110_RESET_VECTOR_0_W::new(self) + ) -> U0_E2_SFT7110_RESET_VECTOR_0_W { + U0_E2_SFT7110_RESET_VECTOR_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg360.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg360.rs index 6d5c176..489a26d 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg360.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg360.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_test_in_63_32` reader - u0_plda_pcie_test_in_63_32"] pub type U0_PLDA_PCIE_TEST_IN_63_32_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_test_in_63_32` writer - u0_plda_pcie_test_in_63_32"] -pub type U0_PLDA_PCIE_TEST_IN_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_TEST_IN_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_test_in_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_test_in_63_32( &mut self, - ) -> U0_PLDA_PCIE_TEST_IN_63_32_W { - U0_PLDA_PCIE_TEST_IN_63_32_W::new(self) + ) -> U0_PLDA_PCIE_TEST_IN_63_32_W { + U0_PLDA_PCIE_TEST_IN_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg364.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg364.rs index 12486e8..0b3817b 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg364.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg364.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg368.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg368.rs index a4bd073..25c6a1a 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg368.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg368.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg372.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg372.rs index dfa2533..3305bbc 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg372.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg372.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg376.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg376.rs index c78a775..a2c4edc 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg376.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg376.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg380.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg380.rs index 6e739d6..3c51564 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg380.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg380.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg384.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg384.rs index 251e0f6..16f5d9a 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg384.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg384.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg388.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg388.rs index c547c66..14abb5c 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg388.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg388.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg392.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg392.rs index edea5d4..3367405 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg392.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg392.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg396.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg396.rs index 8b92e32..93fc2a9 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg396.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg396.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg4.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg4.rs index d5a8ee4..0f8272f 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg4.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg4.rs @@ -9,57 +9,57 @@ pub type U0_CDN_USB_LTM_HOST_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_ltm_host_req_halt` reader - LTM interface to software"] pub type U0_CDN_USB_LTM_HOST_REQ_HALT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_ltm_host_req_halt` writer - LTM interface to software"] -pub type U0_CDN_USB_LTM_HOST_REQ_HALT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_LTM_HOST_REQ_HALT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_mdctrl_clk_sel` reader - u0_cdn_usb_mdctrl_clk_sel"] pub type U0_CDN_USB_MDCTRL_CLK_SEL_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_mdctrl_clk_sel` writer - u0_cdn_usb_mdctrl_clk_sel"] -pub type U0_CDN_USB_MDCTRL_CLK_SEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_MDCTRL_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_mdctrl_clk_status` reader - u0_cdn_usb_mdctrl_clk_status"] pub type U0_CDN_USB_MDCTRL_CLK_STATUS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_mode_strap` reader - Can onlly be changed when pwrup_rst_n is low"] pub type U0_CDN_USB_MODE_STRAP_R = crate::FieldReader; #[doc = "Field `u0_cdn_usb_mode_strap` writer - Can onlly be changed when pwrup_rst_n is low"] -pub type U0_CDN_USB_MODE_STRAP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U0_CDN_USB_MODE_STRAP_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_cdn_usb_otg_suspendm` reader - u0_cdn_usb_otg_suspendm"] pub type U0_CDN_USB_OTG_SUSPENDM_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_otg_suspendm` writer - u0_cdn_usb_otg_suspendm"] -pub type U0_CDN_USB_OTG_SUSPENDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_OTG_SUSPENDM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_otg_suspendm_byps` reader - u0_cdn_usb_otg_suspendm_byps"] pub type U0_CDN_USB_OTG_SUSPENDM_BYPS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_otg_suspendm_byps` writer - u0_cdn_usb_otg_suspendm_byps"] -pub type U0_CDN_USB_OTG_SUSPENDM_BYPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_OTG_SUSPENDM_BYPS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_phy_bvalid` reader - u0_cdn_usb_phy_bvalid"] pub type U0_CDN_USB_PHY_BVALID_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_pll_en` reader - u0_cdn_usb_pll_en"] pub type U0_CDN_USB_PLL_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_pll_en` writer - u0_cdn_usb_pll_en"] -pub type U0_CDN_USB_PLL_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_PLL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_refclk_mode` reader - u0_cdn_usb_refclk_mode"] pub type U0_CDN_USB_REFCLK_MODE_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_refclk_mode` writer - u0_cdn_usb_refclk_mode"] -pub type U0_CDN_USB_REFCLK_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_REFCLK_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_rid_a_comp_sts` reader - u0_cdn_usb_rid_a_comp_sts"] pub type U0_CDN_USB_RID_A_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_rid_a_comp_sts` writer - u0_cdn_usb_rid_a_comp_sts"] -pub type U0_CDN_USB_RID_A_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_RID_A_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_rid_b_comp_sts` reader - u0_cdn_usb_rid_b_comp_sts"] pub type U0_CDN_USB_RID_B_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_rid_b_comp_sts` writer - u0_cdn_usb_rid_b_comp_sts"] -pub type U0_CDN_USB_RID_B_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_RID_B_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_rid_c_comp_sts` reader - u0_cdn_usb_rid_c_comp_sts"] pub type U0_CDN_USB_RID_C_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_rid_c_comp_sts` writer - u0_cdn_usb_rid_c_comp_sts"] -pub type U0_CDN_USB_RID_C_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_RID_C_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_rid_float_comp_en` reader - u0_cdn_usb_rid_float_comp_en"] pub type U0_CDN_USB_RID_FLOAT_COMP_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_rid_float_comp_sts` reader - u0_cdn_usb_rid_float_comp_sts"] pub type U0_CDN_USB_RID_FLOAT_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_rid_float_comp_sts` writer - u0_cdn_usb_rid_float_comp_sts"] -pub type U0_CDN_USB_RID_FLOAT_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_RID_FLOAT_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_rid_gnd_comp_sts` reader - u0_cdn_usb_rid_gnd_comp_sts"] pub type U0_CDN_USB_RID_GND_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_rid_gnd_comp_sts` writer - u0_cdn_usb_rid_gnd_comp_sts"] -pub type U0_CDN_USB_RID_GND_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_RID_GND_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_rid_nonfloat_comp_en` reader - u0_cdn_usb_rid_nonfloat_comp_en"] pub type U0_CDN_USB_RID_NONFLOAT_COMP_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_rx_dm` reader - u0_cdn_usb_rx_dm"] @@ -167,96 +167,100 @@ impl W { #[must_use] pub fn u0_cdn_usb_ltm_host_req_halt( &mut self, - ) -> U0_CDN_USB_LTM_HOST_REQ_HALT_W { - U0_CDN_USB_LTM_HOST_REQ_HALT_W::new(self) + ) -> U0_CDN_USB_LTM_HOST_REQ_HALT_W { + U0_CDN_USB_LTM_HOST_REQ_HALT_W::new(self, 13) } #[doc = "Bit 14 - u0_cdn_usb_mdctrl_clk_sel"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_mdctrl_clk_sel( &mut self, - ) -> U0_CDN_USB_MDCTRL_CLK_SEL_W { - U0_CDN_USB_MDCTRL_CLK_SEL_W::new(self) + ) -> U0_CDN_USB_MDCTRL_CLK_SEL_W { + U0_CDN_USB_MDCTRL_CLK_SEL_W::new(self, 14) } #[doc = "Bits 16:18 - Can onlly be changed when pwrup_rst_n is low"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_mode_strap( &mut self, - ) -> U0_CDN_USB_MODE_STRAP_W { - U0_CDN_USB_MODE_STRAP_W::new(self) + ) -> U0_CDN_USB_MODE_STRAP_W { + U0_CDN_USB_MODE_STRAP_W::new(self, 16) } #[doc = "Bit 19 - u0_cdn_usb_otg_suspendm"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_otg_suspendm( &mut self, - ) -> U0_CDN_USB_OTG_SUSPENDM_W { - U0_CDN_USB_OTG_SUSPENDM_W::new(self) + ) -> U0_CDN_USB_OTG_SUSPENDM_W { + U0_CDN_USB_OTG_SUSPENDM_W::new(self, 19) } #[doc = "Bit 20 - u0_cdn_usb_otg_suspendm_byps"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_otg_suspendm_byps( &mut self, - ) -> U0_CDN_USB_OTG_SUSPENDM_BYPS_W { - U0_CDN_USB_OTG_SUSPENDM_BYPS_W::new(self) + ) -> U0_CDN_USB_OTG_SUSPENDM_BYPS_W { + U0_CDN_USB_OTG_SUSPENDM_BYPS_W::new(self, 20) } #[doc = "Bit 22 - u0_cdn_usb_pll_en"] #[inline(always)] #[must_use] - pub fn u0_cdn_usb_pll_en(&mut self) -> U0_CDN_USB_PLL_EN_W { - U0_CDN_USB_PLL_EN_W::new(self) + pub fn u0_cdn_usb_pll_en(&mut self) -> U0_CDN_USB_PLL_EN_W { + U0_CDN_USB_PLL_EN_W::new(self, 22) } #[doc = "Bit 23 - u0_cdn_usb_refclk_mode"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_refclk_mode( &mut self, - ) -> U0_CDN_USB_REFCLK_MODE_W { - U0_CDN_USB_REFCLK_MODE_W::new(self) + ) -> U0_CDN_USB_REFCLK_MODE_W { + U0_CDN_USB_REFCLK_MODE_W::new(self, 23) } #[doc = "Bit 24 - u0_cdn_usb_rid_a_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_rid_a_comp_sts( &mut self, - ) -> U0_CDN_USB_RID_A_COMP_STS_W { - U0_CDN_USB_RID_A_COMP_STS_W::new(self) + ) -> U0_CDN_USB_RID_A_COMP_STS_W { + U0_CDN_USB_RID_A_COMP_STS_W::new(self, 24) } #[doc = "Bit 25 - u0_cdn_usb_rid_b_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_rid_b_comp_sts( &mut self, - ) -> U0_CDN_USB_RID_B_COMP_STS_W { - U0_CDN_USB_RID_B_COMP_STS_W::new(self) + ) -> U0_CDN_USB_RID_B_COMP_STS_W { + U0_CDN_USB_RID_B_COMP_STS_W::new(self, 25) } #[doc = "Bit 26 - u0_cdn_usb_rid_c_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_rid_c_comp_sts( &mut self, - ) -> U0_CDN_USB_RID_C_COMP_STS_W { - U0_CDN_USB_RID_C_COMP_STS_W::new(self) + ) -> U0_CDN_USB_RID_C_COMP_STS_W { + U0_CDN_USB_RID_C_COMP_STS_W::new(self, 26) } #[doc = "Bit 28 - u0_cdn_usb_rid_float_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_rid_float_comp_sts( &mut self, - ) -> U0_CDN_USB_RID_FLOAT_COMP_STS_W { - U0_CDN_USB_RID_FLOAT_COMP_STS_W::new(self) + ) -> U0_CDN_USB_RID_FLOAT_COMP_STS_W { + U0_CDN_USB_RID_FLOAT_COMP_STS_W::new(self, 28) } #[doc = "Bit 29 - u0_cdn_usb_rid_gnd_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_rid_gnd_comp_sts( &mut self, - ) -> U0_CDN_USB_RID_GND_COMP_STS_W { - U0_CDN_USB_RID_GND_COMP_STS_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_CDN_USB_RID_GND_COMP_STS_W { + U0_CDN_USB_RID_GND_COMP_STS_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg40.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg40.rs index d19ee7a..5ed0182 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg40.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg40.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg400.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg400.rs index fea4c03..8ac81dc 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg400.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg400.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg404.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg404.rs index be1b755..fc7e19d 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg404.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg404.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg408.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg408.rs index 996784a..89b57d6 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg408.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg408.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg412.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg412.rs index 4979d21..e9d14f9 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg412.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg412.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg416.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg416.rs index eeeb1ce..6a877df 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg416.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg416.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg420.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg420.rs index eb2a132..e778111 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg420.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg420.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg424.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg424.rs index cfe423e..c039be5 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg424.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg424.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg428.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg428.rs index 73a74d1..5e04dc5 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg428.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg428.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg432.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg432.rs index 6116c00..5b74195 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg432.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg432.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg436.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg436.rs index f881fd9..8aa222b 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg436.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg436.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg44.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg44.rs index d10499c..673cb30 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg44.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg44.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_hifi4_altresetvec` reader - Reset Vector Address"] pub type U0_HIFI4_ALTRESETVEC_R = crate::FieldReader; #[doc = "Field `u0_hifi4_altresetvec` writer - Reset Vector Address"] -pub type U0_HIFI4_ALTRESETVEC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_HIFI4_ALTRESETVEC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - Reset Vector Address"] #[inline(always)] @@ -17,12 +17,14 @@ impl W { #[doc = "Bits 0:31 - Reset Vector Address"] #[inline(always)] #[must_use] - pub fn u0_hifi4_altresetvec( - &mut self, - ) -> U0_HIFI4_ALTRESETVEC_W { - U0_HIFI4_ALTRESETVEC_W::new(self) + pub fn u0_hifi4_altresetvec(&mut self) -> U0_HIFI4_ALTRESETVEC_W { + U0_HIFI4_ALTRESETVEC_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg440.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg440.rs index 006978d..978a42e 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg440.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg440.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg444.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg444.rs index 9f77601..b46ba5f 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg444.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg444.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg448.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg448.rs index 64d4cb1..11be6dc 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg448.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg448.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg452.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg452.rs index 06874f4..f06dbfe 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg452.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg452.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg456.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg456.rs index 7ddb0e9..c1fae0b 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg456.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg456.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg460.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg460.rs index c85a88c..2c41c2c 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg460.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg460.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg464.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg464.rs index 95ccb26..16b0ae3 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg464.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg464.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg468.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg468.rs index 6becc4e..9fcae7e 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg468.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg468.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg472.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg472.rs index 6e50753..9b6b493 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg472.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg472.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg476.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg476.rs index c680d12..99803e3 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg476.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg476.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg48.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg48.rs index 5b28a96..4b91c36 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg48.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg48.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_hifi4_breakin` reader - Debug signal"] pub type U0_HIFI4_BREAKIN_R = crate::BitReader; #[doc = "Field `u0_hifi4_breakin` writer - Debug signal"] -pub type U0_HIFI4_BREAKIN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_BREAKIN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_breakinack` reader - Debug signal"] pub type U0_HIFI4_BREAKINACK_R = crate::BitReader; #[doc = "Field `u0_hifi4_breakout` reader - Debug signal"] @@ -13,7 +13,7 @@ pub type U0_HIFI4_BREAKOUT_R = crate::BitReader; #[doc = "Field `u0_hifi4_breakoutack` reader - Debug signal"] pub type U0_HIFI4_BREAKOUTACK_R = crate::BitReader; #[doc = "Field `u0_hifi4_breakoutack` writer - Debug signal"] -pub type U0_HIFI4_BREAKOUTACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_BREAKOUTACK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_debugmode` reader - Debug signal"] pub type U0_HIFI4_DEBUGMODE_R = crate::BitReader; #[doc = "Field `u0_hifi4_doubleexceptionerror` reader - Fault Handling Signals"] @@ -25,7 +25,7 @@ pub type U0_HIFI4_IRAM1LOADSTORE_R = crate::BitReader; #[doc = "Field `u0_hifi4_ocdhaltonreset` reader - Debug signal"] pub type U0_HIFI4_OCDHALTONRESET_R = crate::BitReader; #[doc = "Field `u0_hifi4_ocdhaltonreset` writer - Debug signal"] -pub type U0_HIFI4_OCDHALTONRESET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_OCDHALTONRESET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_pfatalerror` reader - Fault Handling Signals"] pub type U0_HIFI4_PFATALERROR_R = crate::BitReader; impl R { @@ -84,26 +84,28 @@ impl W { #[doc = "Bit 0 - Debug signal"] #[inline(always)] #[must_use] - pub fn u0_hifi4_breakin(&mut self) -> U0_HIFI4_BREAKIN_W { - U0_HIFI4_BREAKIN_W::new(self) + pub fn u0_hifi4_breakin(&mut self) -> U0_HIFI4_BREAKIN_W { + U0_HIFI4_BREAKIN_W::new(self, 0) } #[doc = "Bit 3 - Debug signal"] #[inline(always)] #[must_use] - pub fn u0_hifi4_breakoutack( - &mut self, - ) -> U0_HIFI4_BREAKOUTACK_W { - U0_HIFI4_BREAKOUTACK_W::new(self) + pub fn u0_hifi4_breakoutack(&mut self) -> U0_HIFI4_BREAKOUTACK_W { + U0_HIFI4_BREAKOUTACK_W::new(self, 3) } #[doc = "Bit 8 - Debug signal"] #[inline(always)] #[must_use] pub fn u0_hifi4_ocdhaltonreset( &mut self, - ) -> U0_HIFI4_OCDHALTONRESET_W { - U0_HIFI4_OCDHALTONRESET_W::new(self) + ) -> U0_HIFI4_OCDHALTONRESET_W { + U0_HIFI4_OCDHALTONRESET_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg480.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg480.rs index ce9e85e..974e094 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg480.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg480.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg484.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg484.rs index 80780a3..16d685c 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg484.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg484.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg488.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg488.rs index 39f28b0..fde5249 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg488.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg488.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg492.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg492.rs index 886a46c..aa6f149 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg492.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg492.rs @@ -5,12 +5,11 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_test_sel` reader - u0_plda_pcie_test_sel"] pub type U0_PLDA_PCIE_TEST_SEL_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_test_sel` writer - u0_plda_pcie_test_sel"] -pub type U0_PLDA_PCIE_TEST_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type U0_PLDA_PCIE_TEST_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `u0_plda_pcie_tl_clock_freq` reader - u0_plda_pcie_tl_clock_freq"] pub type U0_PLDA_PCIE_TL_CLOCK_FREQ_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_tl_clock_freq` writer - u0_plda_pcie_tl_clock_freq"] -pub type U0_PLDA_PCIE_TL_CLOCK_FREQ_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 22, O, u32>; +pub type U0_PLDA_PCIE_TL_CLOCK_FREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; impl R { #[doc = "Bits 0:3 - u0_plda_pcie_test_sel"] #[inline(always)] @@ -29,18 +28,22 @@ impl W { #[must_use] pub fn u0_plda_pcie_test_sel( &mut self, - ) -> U0_PLDA_PCIE_TEST_SEL_W { - U0_PLDA_PCIE_TEST_SEL_W::new(self) + ) -> U0_PLDA_PCIE_TEST_SEL_W { + U0_PLDA_PCIE_TEST_SEL_W::new(self, 0) } #[doc = "Bits 4:25 - u0_plda_pcie_tl_clock_freq"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_tl_clock_freq( &mut self, - ) -> U0_PLDA_PCIE_TL_CLOCK_FREQ_W { - U0_PLDA_PCIE_TL_CLOCK_FREQ_W::new(self) + ) -> U0_PLDA_PCIE_TL_CLOCK_FREQ_W { + U0_PLDA_PCIE_TL_CLOCK_FREQ_W::new(self, 4) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg500.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg500.rs index 85d492a..d55fe25 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg500.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg500.rs @@ -5,63 +5,63 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_tx_pattern` reader - u0_plda_pcie_tx_pattern"] pub type U0_PLDA_PCIE_TX_PATTERN_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_tx_pattern` writer - u0_plda_pcie_tx_pattern"] -pub type U0_PLDA_PCIE_TX_PATTERN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLDA_PCIE_TX_PATTERN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_plda_pcie_usb3_bus_width` reader - u0_plda_pcie_usb3_bus_width"] pub type U0_PLDA_PCIE_USB3_BUS_WIDTH_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_usb3_bus_width` writer - u0_plda_pcie_usb3_bus_width"] -pub type U0_PLDA_PCIE_USB3_BUS_WIDTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLDA_PCIE_USB3_BUS_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_plda_pcie_usb3_phy_enable` reader - u0_plda_pcie_usb3_phy_enable"] pub type U0_PLDA_PCIE_USB3_PHY_ENABLE_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_usb3_phy_enable` writer - u0_plda_pcie_usb3_phy_enable"] -pub type U0_PLDA_PCIE_USB3_PHY_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_USB3_PHY_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_usb3_rate` reader - u0_plda_pcie_usb3_rate"] pub type U0_PLDA_PCIE_USB3_RATE_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_usb3_rate` writer - u0_plda_pcie_usb3_rate"] -pub type U0_PLDA_PCIE_USB3_RATE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLDA_PCIE_USB3_RATE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_plda_pcie_usb3_rx_standby` reader - u0_plda_pcie_usb3_rx_standby"] pub type U0_PLDA_PCIE_USB3_RX_STANDBY_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_usb3_rx_standby` writer - u0_plda_pcie_usb3_rx_standby"] -pub type U0_PLDA_PCIE_USB3_RX_STANDBY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_USB3_RX_STANDBY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_xwdecerr` reader - u0_plda_pcie_xwdecerr"] pub type U0_PLDA_PCIE_XWDECERR_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_xwerrclr` reader - u0_plda_pcie_xwerrclr"] pub type U0_PLDA_PCIE_XWERRCLR_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_xwerrclr` writer - u0_plda_pcie_xwerrclr"] -pub type U0_PLDA_PCIE_XWERRCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_XWERRCLR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_xwslverr` reader - u0_plda_pcie_xwslverr"] pub type U0_PLDA_PCIE_XWSLVERR_R = crate::BitReader; #[doc = "Field `u0_sec_top_sramcfg_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] pub type U0_SEC_TOP_SRAMCFG_SLP_R = crate::BitReader; #[doc = "Field `u0_sec_top_sramcfg_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] -pub type U0_SEC_TOP_SRAMCFG_SLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_SEC_TOP_SRAMCFG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sec_top_sramcfg_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] pub type U0_SEC_TOP_SRAMCFG_SRAM_CONFIG_SD_R = crate::BitReader; #[doc = "Field `u0_sec_top_sramcfg_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] -pub type U0_SEC_TOP_SRAMCFG_SRAM_CONFIG_SD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_SEC_TOP_SRAMCFG_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sec_top_sramcfg_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_SEC_TOP_SRAMCFG_RTSEL_R = crate::FieldReader; #[doc = "Field `u0_sec_top_sramcfg_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_SEC_TOP_SRAMCFG_RTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_SEC_TOP_SRAMCFG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_sec_top_sramcfg_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_SEC_TOP_SRAMCFG_PTSEL_R = crate::FieldReader; #[doc = "Field `u0_sec_top_sramcfg_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_SEC_TOP_SRAMCFG_PTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_SEC_TOP_SRAMCFG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_sec_top_sramcfg_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] pub type U0_SEC_TOP_SRAMCFG_TRB_R = crate::FieldReader; #[doc = "Field `u0_sec_top_sramcfg_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] -pub type U0_SEC_TOP_SRAMCFG_TRB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_SEC_TOP_SRAMCFG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_sec_top_sramcfg_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_SEC_TOP_SRAMCFG_WTSEL_R = crate::FieldReader; #[doc = "Field `u0_sec_top_sramcfg_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_SEC_TOP_SRAMCFG_WTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_SEC_TOP_SRAMCFG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_sec_top_sramcfg_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] pub type U0_SEC_TOP_SRAMCFG_VS_R = crate::BitReader; #[doc = "Field `u0_sec_top_sramcfg_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] -pub type U0_SEC_TOP_SRAMCFG_VS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_SEC_TOP_SRAMCFG_VS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sec_top_sramcfg_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] pub type U0_SEC_TOP_SRAMCFG_VG_R = crate::BitReader; #[doc = "Field `u0_sec_top_sramcfg_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] -pub type U0_SEC_TOP_SRAMCFG_VG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_SEC_TOP_SRAMCFG_VG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_align_detect` reader - u0_plda_pcie_align_detect"] pub type U0_PLDA_PCIE_ALIGN_DETECT_R = crate::BitReader; impl R { @@ -157,114 +157,118 @@ impl W { #[must_use] pub fn u0_plda_pcie_tx_pattern( &mut self, - ) -> U0_PLDA_PCIE_TX_PATTERN_W { - U0_PLDA_PCIE_TX_PATTERN_W::new(self) + ) -> U0_PLDA_PCIE_TX_PATTERN_W { + U0_PLDA_PCIE_TX_PATTERN_W::new(self, 0) } #[doc = "Bits 2:3 - u0_plda_pcie_usb3_bus_width"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_usb3_bus_width( &mut self, - ) -> U0_PLDA_PCIE_USB3_BUS_WIDTH_W { - U0_PLDA_PCIE_USB3_BUS_WIDTH_W::new(self) + ) -> U0_PLDA_PCIE_USB3_BUS_WIDTH_W { + U0_PLDA_PCIE_USB3_BUS_WIDTH_W::new(self, 2) } #[doc = "Bit 4 - u0_plda_pcie_usb3_phy_enable"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_usb3_phy_enable( &mut self, - ) -> U0_PLDA_PCIE_USB3_PHY_ENABLE_W { - U0_PLDA_PCIE_USB3_PHY_ENABLE_W::new(self) + ) -> U0_PLDA_PCIE_USB3_PHY_ENABLE_W { + U0_PLDA_PCIE_USB3_PHY_ENABLE_W::new(self, 4) } #[doc = "Bits 5:6 - u0_plda_pcie_usb3_rate"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_usb3_rate( &mut self, - ) -> U0_PLDA_PCIE_USB3_RATE_W { - U0_PLDA_PCIE_USB3_RATE_W::new(self) + ) -> U0_PLDA_PCIE_USB3_RATE_W { + U0_PLDA_PCIE_USB3_RATE_W::new(self, 5) } #[doc = "Bit 7 - u0_plda_pcie_usb3_rx_standby"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_usb3_rx_standby( &mut self, - ) -> U0_PLDA_PCIE_USB3_RX_STANDBY_W { - U0_PLDA_PCIE_USB3_RX_STANDBY_W::new(self) + ) -> U0_PLDA_PCIE_USB3_RX_STANDBY_W { + U0_PLDA_PCIE_USB3_RX_STANDBY_W::new(self, 7) } #[doc = "Bit 9 - u0_plda_pcie_xwerrclr"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_xwerrclr( &mut self, - ) -> U0_PLDA_PCIE_XWERRCLR_W { - U0_PLDA_PCIE_XWERRCLR_W::new(self) + ) -> U0_PLDA_PCIE_XWERRCLR_W { + U0_PLDA_PCIE_XWERRCLR_W::new(self, 9) } #[doc = "Bit 11 - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_sec_top_sramcfg_slp( &mut self, - ) -> U0_SEC_TOP_SRAMCFG_SLP_W { - U0_SEC_TOP_SRAMCFG_SLP_W::new(self) + ) -> U0_SEC_TOP_SRAMCFG_SLP_W { + U0_SEC_TOP_SRAMCFG_SLP_W::new(self, 11) } #[doc = "Bit 12 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_sec_top_sramcfg_sram_config_sd( &mut self, - ) -> U0_SEC_TOP_SRAMCFG_SRAM_CONFIG_SD_W { - U0_SEC_TOP_SRAMCFG_SRAM_CONFIG_SD_W::new(self) + ) -> U0_SEC_TOP_SRAMCFG_SRAM_CONFIG_SD_W { + U0_SEC_TOP_SRAMCFG_SRAM_CONFIG_SD_W::new(self, 12) } #[doc = "Bits 13:14 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_sec_top_sramcfg_rtsel( &mut self, - ) -> U0_SEC_TOP_SRAMCFG_RTSEL_W { - U0_SEC_TOP_SRAMCFG_RTSEL_W::new(self) + ) -> U0_SEC_TOP_SRAMCFG_RTSEL_W { + U0_SEC_TOP_SRAMCFG_RTSEL_W::new(self, 13) } #[doc = "Bits 15:16 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_sec_top_sramcfg_ptsel( &mut self, - ) -> U0_SEC_TOP_SRAMCFG_PTSEL_W { - U0_SEC_TOP_SRAMCFG_PTSEL_W::new(self) + ) -> U0_SEC_TOP_SRAMCFG_PTSEL_W { + U0_SEC_TOP_SRAMCFG_PTSEL_W::new(self, 15) } #[doc = "Bits 17:18 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_sec_top_sramcfg_trb( &mut self, - ) -> U0_SEC_TOP_SRAMCFG_TRB_W { - U0_SEC_TOP_SRAMCFG_TRB_W::new(self) + ) -> U0_SEC_TOP_SRAMCFG_TRB_W { + U0_SEC_TOP_SRAMCFG_TRB_W::new(self, 17) } #[doc = "Bits 19:20 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_sec_top_sramcfg_wtsel( &mut self, - ) -> U0_SEC_TOP_SRAMCFG_WTSEL_W { - U0_SEC_TOP_SRAMCFG_WTSEL_W::new(self) + ) -> U0_SEC_TOP_SRAMCFG_WTSEL_W { + U0_SEC_TOP_SRAMCFG_WTSEL_W::new(self, 19) } #[doc = "Bit 21 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_sec_top_sramcfg_vs( &mut self, - ) -> U0_SEC_TOP_SRAMCFG_VS_W { - U0_SEC_TOP_SRAMCFG_VS_W::new(self) + ) -> U0_SEC_TOP_SRAMCFG_VS_W { + U0_SEC_TOP_SRAMCFG_VS_W::new(self, 21) } #[doc = "Bit 22 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_sec_top_sramcfg_vg( &mut self, - ) -> U0_SEC_TOP_SRAMCFG_VG_W { - U0_SEC_TOP_SRAMCFG_VG_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_SEC_TOP_SRAMCFG_VG_W { + U0_SEC_TOP_SRAMCFG_VG_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg504.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg504.rs index f324066..260e8e7 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg504.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg504.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg508.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg508.rs index 630ebea..4790af3 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg508.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg508.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg512.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg512.rs index 7819245..ee3d556 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg512.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg512.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg516.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg516.rs index d520e8a..61b702a 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg516.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg516.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg52.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg52.rs index 91c2777..988049b 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg52.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg52.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg520.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg520.rs index 78cfc8b..94c6643 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg520.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg520.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg524.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg524.rs index 0e69a54..863f4b0 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg524.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg524.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg528.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg528.rs index 86aab47..0e5f4c8 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg528.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg528.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg532.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg532.rs index 0c7f5a9..37cb7e2 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg532.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg532.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg536.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg536.rs index 5a86fce..ac0616d 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg536.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg536.rs @@ -28,7 +28,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg540.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg540.rs index f98ec21..f3c6c11 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg540.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg540.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg544.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg544.rs index 01dc464..6b3aa74 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg544.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg544.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg548.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg548.rs index fa7a210..641c91a 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg548.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg548.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg552.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg552.rs index 995c7af..b2df9f1 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg552.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg552.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg556.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg556.rs index 445e741..7249981 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg556.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg556.rs @@ -7,7 +7,7 @@ pub type U1_PLDA_PCIE_AXI4_MST0_AWUSER_42_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_mst0_rderr` reader - u1_plda_pcie_axi4_mst0_rderr"] pub type U1_PLDA_PCIE_AXI4_MST0_RDERR_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_mst0_rderr` writer - u1_plda_pcie_axi4_mst0_rderr"] -pub type U1_PLDA_PCIE_AXI4_MST0_RDERR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type U1_PLDA_PCIE_AXI4_MST0_RDERR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:10 - u1_plda_pcie_axi4_mst0_awuser_42_32"] #[inline(always)] @@ -26,10 +26,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_mst0_rderr( &mut self, - ) -> U1_PLDA_PCIE_AXI4_MST0_RDERR_W { - U1_PLDA_PCIE_AXI4_MST0_RDERR_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_MST0_RDERR_W { + U1_PLDA_PCIE_AXI4_MST0_RDERR_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg56.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg56.rs index 85f9fdb..16bb481 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg56.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg56.rs @@ -7,13 +7,13 @@ pub type U0_HIFI4_PFAULTINFOVALID_R = crate::BitReader; #[doc = "Field `u0_hifi4_prid` reader - Module ID"] pub type U0_HIFI4_PRID_R = crate::FieldReader; #[doc = "Field `u0_hifi4_prid` writer - Module ID"] -pub type U0_HIFI4_PRID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type U0_HIFI4_PRID_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; #[doc = "Field `u0_hifi4_pwaitmode` reader - Wait Mode"] pub type U0_HIFI4_PWAITMODE_R = crate::BitReader; #[doc = "Field `u0_hifi4_runstall` reader - Run Stall"] pub type U0_HIFI4_RUNSTALL_R = crate::BitReader; #[doc = "Field `u0_hifi4_runstall` writer - Run Stall"] -pub type U0_HIFI4_RUNSTALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_RUNSTALL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Fault Handling Signals"] #[inline(always)] @@ -40,16 +40,20 @@ impl W { #[doc = "Bits 1:16 - Module ID"] #[inline(always)] #[must_use] - pub fn u0_hifi4_prid(&mut self) -> U0_HIFI4_PRID_W { - U0_HIFI4_PRID_W::new(self) + pub fn u0_hifi4_prid(&mut self) -> U0_HIFI4_PRID_W { + U0_HIFI4_PRID_W::new(self, 1) } #[doc = "Bit 18 - Run Stall"] #[inline(always)] #[must_use] - pub fn u0_hifi4_runstall(&mut self) -> U0_HIFI4_RUNSTALL_W { - U0_HIFI4_RUNSTALL_W::new(self) + pub fn u0_hifi4_runstall(&mut self) -> U0_HIFI4_RUNSTALL_W { + U0_HIFI4_RUNSTALL_W::new(self, 18) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg560.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg560.rs index eefe4c9..a4f627a 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg560.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg560.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_mst0_ruser` reader - u1_plda_pcie_axi4_mst0_ruser"] pub type U1_PLDA_PCIE_AXI4_MST0_RUSER_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_mst0_ruser` writer - u1_plda_pcie_axi4_mst0_ruser"] -pub type U1_PLDA_PCIE_AXI4_MST0_RUSER_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_MST0_RUSER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_mst0_ruser"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_mst0_ruser( &mut self, - ) -> U1_PLDA_PCIE_AXI4_MST0_RUSER_W { - U1_PLDA_PCIE_AXI4_MST0_RUSER_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_MST0_RUSER_W { + U1_PLDA_PCIE_AXI4_MST0_RUSER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg564.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg564.rs index 236f4f1..dadb069 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg564.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg564.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg568.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg568.rs index 456eed2..260a5df 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg568.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg568.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_31_0` reader - u1_plda_pcie_axi4_slv0_aratomop_31_0"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_31_0` writer - u1_plda_pcie_axi4_slv0_aratomop_31_0"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aratomop_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aratomop_31_0( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W { - U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W { + U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg572.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg572.rs index 2f76870..5f71a70 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg572.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg572.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_63_32` reader - u1_plda_pcie_axi4_slv0_aratomop_63_32"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_63_32` writer - u1_plda_pcie_axi4_slv0_aratomop_63_32"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aratomop_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aratomop_63_32( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W { - U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W { + U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg576.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg576.rs index c9a3ae3..22dd9d8 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg576.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg576.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_95_64` reader - u1_plda_pcie_axi4_slv0_aratomop_95_64"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_95_64` writer - u1_plda_pcie_axi4_slv0_aratomop_95_64"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aratomop_95_64"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aratomop_95_64( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W { - U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W { + U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg580.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg580.rs index 2fa0778..4dcce3c 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg580.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg580.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_127_96` reader - u1_plda_pcie_axi4_slv0_aratomop_127_96"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_127_96` writer - u1_plda_pcie_axi4_slv0_aratomop_127_96"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aratomop_127_96"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aratomop_127_96( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W { - U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W { + U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg584.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg584.rs index c67e8b4..bc16b4a 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg584.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg584.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_159_128` reader - u1_plda_pcie_axi4_slv0_aratomop_159_128"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_159_128` writer - u1_plda_pcie_axi4_slv0_aratomop_159_128"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aratomop_159_128"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aratomop_159_128( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W { - U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W { + U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg588.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg588.rs index 66ecf25..40a8580 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg588.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg588.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_191_160` reader - u1_plda_pcie_axi4_slv0_aratomop_191_160"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_191_160` writer - u1_plda_pcie_axi4_slv0_aratomop_191_160"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aratomop_191_160"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aratomop_191_160( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W { - U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W { + U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg592.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg592.rs index 64eb476..d17e158 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg592.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg592.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_223_192` reader - u1_plda_pcie_axi4_slv0_aratomop_223_192"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_223_192` writer - u1_plda_pcie_axi4_slv0_aratomop_223_192"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aratomop_223_192"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aratomop_223_192( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W { - U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W { + U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg596.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg596.rs index e7d14c6..c16ab9f 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg596.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg596.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_255_224` reader - u1_plda_pcie_axi4_slv0_aratomop_255_224"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_255_224` writer - u1_plda_pcie_axi4_slv0_aratomop_255_224"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aratomop_255_224"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aratomop_255_224( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W { - U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W { + U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg60.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg60.rs index 15a792a..5908a6e 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg60.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg60.rs @@ -5,13 +5,11 @@ pub type W = crate::W; #[doc = "Field `u0_hifi4_scfg_dsp_mst_offset_master` reader - Indicates that master port remap address"] pub type U0_HIFI4_SCFG_DSP_MST_OFFSET_MASTER_R = crate::FieldReader; #[doc = "Field `u0_hifi4_scfg_dsp_mst_offset_master` writer - Indicates that master port remap address"] -pub type U0_HIFI4_SCFG_DSP_MST_OFFSET_MASTER_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 12, O, u16>; +pub type U0_HIFI4_SCFG_DSP_MST_OFFSET_MASTER_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; #[doc = "Field `u0_hifi4_scfg_dsp_mst_offset_dma` reader - Indicates the DMA port remap address"] pub type U0_HIFI4_SCFG_DSP_MST_OFFSET_DMA_R = crate::FieldReader; #[doc = "Field `u0_hifi4_scfg_dsp_mst_offset_dma` writer - Indicates the DMA port remap address"] -pub type U0_HIFI4_SCFG_DSP_MST_OFFSET_DMA_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 12, O, u16>; +pub type U0_HIFI4_SCFG_DSP_MST_OFFSET_DMA_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; impl R { #[doc = "Bits 0:11 - Indicates that master port remap address"] #[inline(always)] @@ -30,18 +28,22 @@ impl W { #[must_use] pub fn u0_hifi4_scfg_dsp_mst_offset_master( &mut self, - ) -> U0_HIFI4_SCFG_DSP_MST_OFFSET_MASTER_W { - U0_HIFI4_SCFG_DSP_MST_OFFSET_MASTER_W::new(self) + ) -> U0_HIFI4_SCFG_DSP_MST_OFFSET_MASTER_W { + U0_HIFI4_SCFG_DSP_MST_OFFSET_MASTER_W::new(self, 0) } #[doc = "Bits 16:27 - Indicates the DMA port remap address"] #[inline(always)] #[must_use] pub fn u0_hifi4_scfg_dsp_mst_offset_dma( &mut self, - ) -> U0_HIFI4_SCFG_DSP_MST_OFFSET_DMA_W { - U0_HIFI4_SCFG_DSP_MST_OFFSET_DMA_W::new(self) + ) -> U0_HIFI4_SCFG_DSP_MST_OFFSET_DMA_W { + U0_HIFI4_SCFG_DSP_MST_OFFSET_DMA_W::new(self, 16) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg600.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg600.rs index b9b6a5d..8f9e468 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg600.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg600.rs @@ -5,18 +5,15 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_mst0_aratomop_257_256` reader - u1_plda_pcie_axi4_mst0_aratomop_257_256"] pub type U1_PLDA_PCIE_AXI4_MST0_ARATOMOP_257_256_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_mst0_aratomop_257_256` writer - u1_plda_pcie_axi4_mst0_aratomop_257_256"] -pub type U1_PLDA_PCIE_AXI4_MST0_ARATOMOP_257_256_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U1_PLDA_PCIE_AXI4_MST0_ARATOMOP_257_256_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_plda_pcie_axi4_slv0_arfunc` reader - u1_plda_pcie_axi4_slv0_arfunc"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARFUNC_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_arfunc` writer - u1_plda_pcie_axi4_slv0_arfunc"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARFUNC_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 15, O, u16>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARFUNC_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; #[doc = "Field `u1_plda_pcie_axi4_slv0_arregion` reader - u1_plda_pcie_axi4_slv0_arregion"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARREGION_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_arregion` writer - u1_plda_pcie_axi4_slv0_arregion"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARREGION_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 4, O>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARREGION_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:1 - u1_plda_pcie_axi4_mst0_aratomop_257_256"] #[inline(always)] @@ -42,26 +39,30 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_mst0_aratomop_257_256( &mut self, - ) -> U1_PLDA_PCIE_AXI4_MST0_ARATOMOP_257_256_W { - U1_PLDA_PCIE_AXI4_MST0_ARATOMOP_257_256_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_MST0_ARATOMOP_257_256_W { + U1_PLDA_PCIE_AXI4_MST0_ARATOMOP_257_256_W::new(self, 0) } #[doc = "Bits 2:16 - u1_plda_pcie_axi4_slv0_arfunc"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_axi4_slv0_arfunc( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARFUNC_W { - U1_PLDA_PCIE_AXI4_SLV0_ARFUNC_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARFUNC_W { + U1_PLDA_PCIE_AXI4_SLV0_ARFUNC_W::new(self, 2) } #[doc = "Bits 17:20 - u1_plda_pcie_axi4_slv0_arregion"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_axi4_slv0_arregion( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARREGION_W { - U1_PLDA_PCIE_AXI4_SLV0_ARREGION_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARREGION_W { + U1_PLDA_PCIE_AXI4_SLV0_ARREGION_W::new(self, 17) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg604.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg604.rs index 955085c..7cf769c 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg604.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg604.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aruser_31_0` reader - u1_plda_pcie_axi4_slv0_aruser_31_0"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aruser_31_0` writer - u1_plda_pcie_axi4_slv0_aruser_31_0"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aruser_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aruser_31_0( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W { - U1_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W { + U1_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg608.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg608.rs index 2def256..732cdb9 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg608.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg608.rs @@ -5,18 +5,15 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aruser_40_32` reader - u1_plda_pcie_axi4_slv0_aruser_40_32"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aruser_40_32` writer - u1_plda_pcie_axi4_slv0_aruser_40_32"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 9, O, u16>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; #[doc = "Field `u1_plda_pcie_axi4_slv0_awfunc` reader - u1_plda_pcie_axi4_slv0_awfunc"] pub type U1_PLDA_PCIE_AXI4_SLV0_AWFUNC_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_awfunc` writer - u1_plda_pcie_axi4_slv0_awfunc"] -pub type U1_PLDA_PCIE_AXI4_SLV0_AWFUNC_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 15, O, u16>; +pub type U1_PLDA_PCIE_AXI4_SLV0_AWFUNC_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; #[doc = "Field `u1_plda_pcie_axi4_slv0_awregion` reader - u1_plda_pcie_axi4_slv0_awregion"] pub type U1_PLDA_PCIE_AXI4_SLV0_AWREGION_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_awregion` writer - u1_plda_pcie_axi4_slv0_awregion"] -pub type U1_PLDA_PCIE_AXI4_SLV0_AWREGION_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 4, O>; +pub type U1_PLDA_PCIE_AXI4_SLV0_AWREGION_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:8 - u1_plda_pcie_axi4_slv0_aruser_40_32"] #[inline(always)] @@ -40,26 +37,30 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aruser_40_32( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W { - U1_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W { + U1_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W::new(self, 0) } #[doc = "Bits 9:23 - u1_plda_pcie_axi4_slv0_awfunc"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_axi4_slv0_awfunc( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_AWFUNC_W { - U1_PLDA_PCIE_AXI4_SLV0_AWFUNC_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_AWFUNC_W { + U1_PLDA_PCIE_AXI4_SLV0_AWFUNC_W::new(self, 9) } #[doc = "Bits 24:27 - u1_plda_pcie_axi4_slv0_awregion"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_axi4_slv0_awregion( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_AWREGION_W { - U1_PLDA_PCIE_AXI4_SLV0_AWREGION_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_AWREGION_W { + U1_PLDA_PCIE_AXI4_SLV0_AWREGION_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg612.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg612.rs index fbdc25e..88dbf6f 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg612.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg612.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_awuser_31_0` reader - u1_plda_pcie_axi4_slv0_awuser_31_0"] pub type U1_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_awuser_31_0` writer - u1_plda_pcie_axi4_slv0_awuser_31_0"] -pub type U1_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_awuser_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_awuser_31_0( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W { - U1_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W { + U1_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg616.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg616.rs index 734c21d..b0410ad 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg616.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg616.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_awuser_40_32` reader - u1_plda_pcie_axi4_slv0_awuser_40_32"] pub type U1_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_awuser_40_32` writer - u1_plda_pcie_axi4_slv0_awuser_40_32"] -pub type U1_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 9, O, u16>; +pub type U1_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; #[doc = "Field `u1_plda_pcie_axi4_slv0_rderr` reader - u1_plda_pcie_axi4_slv0_rderr"] pub type U1_PLDA_PCIE_AXI4_SLV0_RDERR_R = crate::FieldReader; impl R { @@ -27,10 +26,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_awuser_40_32( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W { - U1_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W { + U1_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg620.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg620.rs index 0e4b321..3d6a433 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg620.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg620.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg624.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg624.rs index a6e9054..5c35c14 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg624.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg624.rs @@ -5,12 +5,11 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_wderr` reader - u1_plda_pcie_axi4_slv0_wderr"] pub type U1_PLDA_PCIE_AXI4_SLV0_WDERR_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_wderr` writer - u1_plda_pcie_axi4_slv0_wderr"] -pub type U1_PLDA_PCIE_AXI4_SLV0_WDERR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type U1_PLDA_PCIE_AXI4_SLV0_WDERR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `u1_plda_pcie_axi4_slvl_arfunc` reader - u1_plda_pcie_axi4_slvl_arfunc"] pub type U1_PLDA_PCIE_AXI4_SLVL_ARFUNC_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slvl_arfunc` writer - u1_plda_pcie_axi4_slvl_arfunc"] -pub type U1_PLDA_PCIE_AXI4_SLVL_ARFUNC_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 15, O, u16>; +pub type U1_PLDA_PCIE_AXI4_SLVL_ARFUNC_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; impl R { #[doc = "Bits 0:7 - u1_plda_pcie_axi4_slv0_wderr"] #[inline(always)] @@ -29,18 +28,22 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_wderr( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_WDERR_W { - U1_PLDA_PCIE_AXI4_SLV0_WDERR_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_WDERR_W { + U1_PLDA_PCIE_AXI4_SLV0_WDERR_W::new(self, 0) } #[doc = "Bits 8:22 - u1_plda_pcie_axi4_slvl_arfunc"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_axi4_slvl_arfunc( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLVL_ARFUNC_W { - U1_PLDA_PCIE_AXI4_SLVL_ARFUNC_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLVL_ARFUNC_W { + U1_PLDA_PCIE_AXI4_SLVL_ARFUNC_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg628.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg628.rs index a660c88..e60fff2 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg628.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg628.rs @@ -5,26 +5,25 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slvl_awfunc` reader - u1_plda_pcie_axi4_slvl_awfunc"] pub type U1_PLDA_PCIE_AXI4_SLVL_AWFUNC_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slvl_awfunc` writer - u1_plda_pcie_axi4_slvl_awfunc"] -pub type U1_PLDA_PCIE_AXI4_SLVL_AWFUNC_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 15, O, u16>; +pub type U1_PLDA_PCIE_AXI4_SLVL_AWFUNC_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; #[doc = "Field `u1_plda_pcie_bus_width_o` reader - u1_plda_pcie_bus_width_o"] pub type U1_PLDA_PCIE_BUS_WIDTH_O_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_bypass_codec` reader - u1_plda_pcie_bypass_codec"] pub type U1_PLDA_PCIE_BYPASS_CODEC_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_bypass_codec` writer - u1_plda_pcie_bypass_codec"] -pub type U1_PLDA_PCIE_BYPASS_CODEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_BYPASS_CODEC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_ckref_src` reader - u1_plda_pcie_ckref_src"] pub type U1_PLDA_PCIE_CKREF_SRC_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_ckref_src` writer - u1_plda_pcie_ckref_src"] -pub type U1_PLDA_PCIE_CKREF_SRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U1_PLDA_PCIE_CKREF_SRC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_plda_pcie_clk_sel` reader - u1_plda_pcie_clk_sel"] pub type U1_PLDA_PCIE_CLK_SEL_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_clk_sel` writer - u1_plda_pcie_clk_sel"] -pub type U1_PLDA_PCIE_CLK_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U1_PLDA_PCIE_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_plda_pcie_clkreq` reader - u1_plda_pcie_clkreq"] pub type U1_PLDA_PCIE_CLKREQ_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_clkreq` writer - u1_plda_pcie_clkreq"] -pub type U1_PLDA_PCIE_CLKREQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_CLKREQ_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:14 - u1_plda_pcie_axi4_slvl_awfunc"] #[inline(always)] @@ -63,42 +62,44 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slvl_awfunc( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLVL_AWFUNC_W { - U1_PLDA_PCIE_AXI4_SLVL_AWFUNC_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLVL_AWFUNC_W { + U1_PLDA_PCIE_AXI4_SLVL_AWFUNC_W::new(self, 0) } #[doc = "Bit 17 - u1_plda_pcie_bypass_codec"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_bypass_codec( &mut self, - ) -> U1_PLDA_PCIE_BYPASS_CODEC_W { - U1_PLDA_PCIE_BYPASS_CODEC_W::new(self) + ) -> U1_PLDA_PCIE_BYPASS_CODEC_W { + U1_PLDA_PCIE_BYPASS_CODEC_W::new(self, 17) } #[doc = "Bits 18:19 - u1_plda_pcie_ckref_src"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_ckref_src( &mut self, - ) -> U1_PLDA_PCIE_CKREF_SRC_W { - U1_PLDA_PCIE_CKREF_SRC_W::new(self) + ) -> U1_PLDA_PCIE_CKREF_SRC_W { + U1_PLDA_PCIE_CKREF_SRC_W::new(self, 18) } #[doc = "Bits 20:21 - u1_plda_pcie_clk_sel"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_clk_sel( &mut self, - ) -> U1_PLDA_PCIE_CLK_SEL_W { - U1_PLDA_PCIE_CLK_SEL_W::new(self) + ) -> U1_PLDA_PCIE_CLK_SEL_W { + U1_PLDA_PCIE_CLK_SEL_W::new(self, 20) } #[doc = "Bit 22 - u1_plda_pcie_clkreq"] #[inline(always)] #[must_use] - pub fn u1_plda_pcie_clkreq( - &mut self, - ) -> U1_PLDA_PCIE_CLKREQ_W { - U1_PLDA_PCIE_CLKREQ_W::new(self) + pub fn u1_plda_pcie_clkreq(&mut self) -> U1_PLDA_PCIE_CLKREQ_W { + U1_PLDA_PCIE_CLKREQ_W::new(self, 22) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg632.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg632.rs index 7386447..469c29a 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg632.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg632.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_31_0` reader - u1_plda_pcie_k_phyparam_31_0"] pub type U1_PLDA_PCIE_K_PHYPARAM_31_0_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_31_0` writer - u1_plda_pcie_k_phyparam_31_0"] -pub type U1_PLDA_PCIE_K_PHYPARAM_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_31_0( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_31_0_W { - U1_PLDA_PCIE_K_PHYPARAM_31_0_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_31_0_W { + U1_PLDA_PCIE_K_PHYPARAM_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg636.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg636.rs index 6c3fbd3..39cdb50 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg636.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg636.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_63_32` reader - u1_plda_pcie_k_phyparam_63_32"] pub type U1_PLDA_PCIE_K_PHYPARAM_63_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_63_32` writer - u1_plda_pcie_k_phyparam_63_32"] -pub type U1_PLDA_PCIE_K_PHYPARAM_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_63_32( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_63_32_W { - U1_PLDA_PCIE_K_PHYPARAM_63_32_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_63_32_W { + U1_PLDA_PCIE_K_PHYPARAM_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg64.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg64.rs index ff0dd4d..8329950 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg64.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg64.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_hifi4_scfg_dsp_slv_offset` reader - The value indicates the slave port remap address"] pub type U0_HIFI4_SCFG_DSP_SLV_OFFSET_R = crate::FieldReader; #[doc = "Field `u0_hifi4_scfg_dsp_slv_offset` writer - The value indicates the slave port remap address"] -pub type U0_HIFI4_SCFG_DSP_SLV_OFFSET_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_HIFI4_SCFG_DSP_SLV_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - The value indicates the slave port remap address"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_hifi4_scfg_dsp_slv_offset( &mut self, - ) -> U0_HIFI4_SCFG_DSP_SLV_OFFSET_W { - U0_HIFI4_SCFG_DSP_SLV_OFFSET_W::new(self) + ) -> U0_HIFI4_SCFG_DSP_SLV_OFFSET_W { + U0_HIFI4_SCFG_DSP_SLV_OFFSET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg640.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg640.rs index 55e5c11..f333d10 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg640.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg640.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_95_64` reader - u1_plda_pcie_k_phyparam_95_64"] pub type U1_PLDA_PCIE_K_PHYPARAM_95_64_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_95_64` writer - u1_plda_pcie_k_phyparam_95_64"] -pub type U1_PLDA_PCIE_K_PHYPARAM_95_64_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_95_64_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_95_64"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_95_64( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_95_64_W { - U1_PLDA_PCIE_K_PHYPARAM_95_64_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_95_64_W { + U1_PLDA_PCIE_K_PHYPARAM_95_64_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg644.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg644.rs index 6c9eb06..b716f8a 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg644.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg644.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_127_96` reader - u1_plda_pcie_k_phyparam_127_96"] pub type U1_PLDA_PCIE_K_PHYPARAM_127_96_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_127_96` writer - u1_plda_pcie_k_phyparam_127_96"] -pub type U1_PLDA_PCIE_K_PHYPARAM_127_96_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_127_96_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_127_96"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_127_96( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_127_96_W { - U1_PLDA_PCIE_K_PHYPARAM_127_96_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_127_96_W { + U1_PLDA_PCIE_K_PHYPARAM_127_96_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg648.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg648.rs index 39452ce..8ea0bb4 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg648.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg648.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_159_128` reader - u1_plda_pcie_k_phyparam_159_128"] pub type U1_PLDA_PCIE_K_PHYPARAM_159_128_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_159_128` writer - u1_plda_pcie_k_phyparam_159_128"] -pub type U1_PLDA_PCIE_K_PHYPARAM_159_128_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_159_128_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_159_128"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_159_128( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_159_128_W { - U1_PLDA_PCIE_K_PHYPARAM_159_128_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_159_128_W { + U1_PLDA_PCIE_K_PHYPARAM_159_128_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg652.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg652.rs index 8275e9e..cbdae14 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg652.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg652.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_191_160` reader - u1_plda_pcie_k_phyparam_191_160"] pub type U1_PLDA_PCIE_K_PHYPARAM_191_160_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_191_160` writer - u1_plda_pcie_k_phyparam_191_160"] -pub type U1_PLDA_PCIE_K_PHYPARAM_191_160_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_191_160_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_191_160"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_191_160( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_191_160_W { - U1_PLDA_PCIE_K_PHYPARAM_191_160_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_191_160_W { + U1_PLDA_PCIE_K_PHYPARAM_191_160_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg656.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg656.rs index 6c97434..7559a4f 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg656.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg656.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_223_192` reader - u1_plda_pcie_k_phyparam_223_192"] pub type U1_PLDA_PCIE_K_PHYPARAM_223_192_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_223_192` writer - u1_plda_pcie_k_phyparam_223_192"] -pub type U1_PLDA_PCIE_K_PHYPARAM_223_192_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_223_192_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_223_192"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_223_192( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_223_192_W { - U1_PLDA_PCIE_K_PHYPARAM_223_192_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_223_192_W { + U1_PLDA_PCIE_K_PHYPARAM_223_192_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg660.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg660.rs index ccc8f56..6d595e5 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg660.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg660.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_255_224` reader - u1_plda_pcie_k_phyparam_255_224"] pub type U1_PLDA_PCIE_K_PHYPARAM_255_224_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_255_224` writer - u1_plda_pcie_k_phyparam_255_224"] -pub type U1_PLDA_PCIE_K_PHYPARAM_255_224_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_255_224_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_255_224"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_255_224( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_255_224_W { - U1_PLDA_PCIE_K_PHYPARAM_255_224_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_255_224_W { + U1_PLDA_PCIE_K_PHYPARAM_255_224_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg664.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg664.rs index ad2e18d..e87eac6 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg664.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg664.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_287_256` reader - u1_plda_pcie_k_phyparam_287_256"] pub type U1_PLDA_PCIE_K_PHYPARAM_287_256_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_287_256` writer - u1_plda_pcie_k_phyparam_287_256"] -pub type U1_PLDA_PCIE_K_PHYPARAM_287_256_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_287_256_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_287_256"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_287_256( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_287_256_W { - U1_PLDA_PCIE_K_PHYPARAM_287_256_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_287_256_W { + U1_PLDA_PCIE_K_PHYPARAM_287_256_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg668.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg668.rs index e077094..bad773b 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg668.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg668.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_319_288` reader - u1_plda_pcie_k_phyparam_319_288"] pub type U1_PLDA_PCIE_K_PHYPARAM_319_288_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_319_288` writer - u1_plda_pcie_k_phyparam_319_288"] -pub type U1_PLDA_PCIE_K_PHYPARAM_319_288_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_319_288_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_319_288"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_319_288( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_319_288_W { - U1_PLDA_PCIE_K_PHYPARAM_319_288_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_319_288_W { + U1_PLDA_PCIE_K_PHYPARAM_319_288_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg672.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg672.rs index f9366d2..c844238 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg672.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg672.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_351_320` reader - u1_plda_pcie_k_phyparam_351_320"] pub type U1_PLDA_PCIE_K_PHYPARAM_351_320_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_351_320` writer - u1_plda_pcie_k_phyparam_351_320"] -pub type U1_PLDA_PCIE_K_PHYPARAM_351_320_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_351_320_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_351_320"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_351_320( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_351_320_W { - U1_PLDA_PCIE_K_PHYPARAM_351_320_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_351_320_W { + U1_PLDA_PCIE_K_PHYPARAM_351_320_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg676.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg676.rs index e0a8c78..9b4d7ac 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg676.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg676.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_383_352` reader - u1_plda_pcie_k_phyparam_383_352"] pub type U1_PLDA_PCIE_K_PHYPARAM_383_352_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_383_352` writer - u1_plda_pcie_k_phyparam_383_352"] -pub type U1_PLDA_PCIE_K_PHYPARAM_383_352_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_383_352_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_383_352"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_383_352( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_383_352_W { - U1_PLDA_PCIE_K_PHYPARAM_383_352_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_383_352_W { + U1_PLDA_PCIE_K_PHYPARAM_383_352_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg68.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg68.rs index 5cfb7f6..29b2617 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg68.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg68.rs @@ -5,47 +5,43 @@ pub type W = crate::W; #[doc = "Field `u0_hifi4_scfg_sram_config_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] pub type U0_HIFI4_SCFG_SRAM_CONFIG_SLP_R = crate::BitReader; #[doc = "Field `u0_hifi4_scfg_sram_config_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] -pub type U0_HIFI4_SCFG_SRAM_CONFIG_SLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_SCFG_SRAM_CONFIG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_scfg_sram_config_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] pub type U0_HIFI4_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_R = crate::BitReader; #[doc = "Field `u0_hifi4_scfg_sram_config_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] -pub type U0_HIFI4_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_scfg_sram_config_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_HIFI4_SCFG_SRAM_CONFIG_RTSEL_R = crate::FieldReader; #[doc = "Field `u0_hifi4_scfg_sram_config_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_HIFI4_SCFG_SRAM_CONFIG_RTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_HIFI4_SCFG_SRAM_CONFIG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_hifi4_scfg_sram_config_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_HIFI4_SCFG_SRAM_CONFIG_PTSEL_R = crate::FieldReader; #[doc = "Field `u0_hifi4_scfg_sram_config_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_HIFI4_SCFG_SRAM_CONFIG_PTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_HIFI4_SCFG_SRAM_CONFIG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_hifi4_scfg_sram_config_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] pub type U0_HIFI4_SCFG_SRAM_CONFIG_TRB_R = crate::FieldReader; #[doc = "Field `u0_hifi4_scfg_sram_config_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] -pub type U0_HIFI4_SCFG_SRAM_CONFIG_TRB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_HIFI4_SCFG_SRAM_CONFIG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_hifi4_scfg_sram_config_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_HIFI4_SCFG_SRAM_CONFIG_WTSEL_R = crate::FieldReader; #[doc = "Field `u0_hifi4_scfg_sram_config_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_HIFI4_SCFG_SRAM_CONFIG_WTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_HIFI4_SCFG_SRAM_CONFIG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_hifi4_scfg_sram_config_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] pub type U0_HIFI4_SCFG_SRAM_CONFIG_VS_R = crate::BitReader; #[doc = "Field `u0_hifi4_scfg_sram_config_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] -pub type U0_HIFI4_SCFG_SRAM_CONFIG_VS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_SCFG_SRAM_CONFIG_VS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_scfg_sram_config_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] pub type U0_HIFI4_SCFG_SRAM_CONFIG_VG_R = crate::BitReader; #[doc = "Field `u0_hifi4_scfg_sram_config_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] -pub type U0_HIFI4_SCFG_SRAM_CONFIG_VG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_SCFG_SRAM_CONFIG_VG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_statvectorsel` reader - When the value is 1, it indicates that the AltResetVec is valid"] pub type U0_HIFI4_STATVECTORSEL_R = crate::BitReader; #[doc = "Field `u0_hifi4_statvectorsel` writer - When the value is 1, it indicates that the AltResetVec is valid"] -pub type U0_HIFI4_STATVECTORSEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_STATVECTORSEL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_trigin_idma` reader - DMA port trigger"] pub type U0_HIFI4_TRIGIN_IDMA_R = crate::BitReader; #[doc = "Field `u0_hifi4_trigin_idma` writer - DMA port trigger"] -pub type U0_HIFI4_TRIGIN_IDMA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_TRIGIN_IDMA_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_trigout_idma` reader - DMA port trigger"] pub type U0_HIFI4_TRIGOUT_IDMA_R = crate::BitReader; #[doc = "Field `u0_hifi4_xocdmode` reader - Debug signal"] @@ -127,82 +123,84 @@ impl W { #[must_use] pub fn u0_hifi4_scfg_sram_config_slp( &mut self, - ) -> U0_HIFI4_SCFG_SRAM_CONFIG_SLP_W { - U0_HIFI4_SCFG_SRAM_CONFIG_SLP_W::new(self) + ) -> U0_HIFI4_SCFG_SRAM_CONFIG_SLP_W { + U0_HIFI4_SCFG_SRAM_CONFIG_SLP_W::new(self, 0) } #[doc = "Bit 1 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_hifi4_scfg_sram_config_sram_config_sd( &mut self, - ) -> U0_HIFI4_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W { - U0_HIFI4_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self) + ) -> U0_HIFI4_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W { + U0_HIFI4_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self, 1) } #[doc = "Bits 2:3 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_hifi4_scfg_sram_config_rtsel( &mut self, - ) -> U0_HIFI4_SCFG_SRAM_CONFIG_RTSEL_W { - U0_HIFI4_SCFG_SRAM_CONFIG_RTSEL_W::new(self) + ) -> U0_HIFI4_SCFG_SRAM_CONFIG_RTSEL_W { + U0_HIFI4_SCFG_SRAM_CONFIG_RTSEL_W::new(self, 2) } #[doc = "Bits 4:5 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_hifi4_scfg_sram_config_ptsel( &mut self, - ) -> U0_HIFI4_SCFG_SRAM_CONFIG_PTSEL_W { - U0_HIFI4_SCFG_SRAM_CONFIG_PTSEL_W::new(self) + ) -> U0_HIFI4_SCFG_SRAM_CONFIG_PTSEL_W { + U0_HIFI4_SCFG_SRAM_CONFIG_PTSEL_W::new(self, 4) } #[doc = "Bits 6:7 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_hifi4_scfg_sram_config_trb( &mut self, - ) -> U0_HIFI4_SCFG_SRAM_CONFIG_TRB_W { - U0_HIFI4_SCFG_SRAM_CONFIG_TRB_W::new(self) + ) -> U0_HIFI4_SCFG_SRAM_CONFIG_TRB_W { + U0_HIFI4_SCFG_SRAM_CONFIG_TRB_W::new(self, 6) } #[doc = "Bits 8:9 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_hifi4_scfg_sram_config_wtsel( &mut self, - ) -> U0_HIFI4_SCFG_SRAM_CONFIG_WTSEL_W { - U0_HIFI4_SCFG_SRAM_CONFIG_WTSEL_W::new(self) + ) -> U0_HIFI4_SCFG_SRAM_CONFIG_WTSEL_W { + U0_HIFI4_SCFG_SRAM_CONFIG_WTSEL_W::new(self, 8) } #[doc = "Bit 10 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_hifi4_scfg_sram_config_vs( &mut self, - ) -> U0_HIFI4_SCFG_SRAM_CONFIG_VS_W { - U0_HIFI4_SCFG_SRAM_CONFIG_VS_W::new(self) + ) -> U0_HIFI4_SCFG_SRAM_CONFIG_VS_W { + U0_HIFI4_SCFG_SRAM_CONFIG_VS_W::new(self, 10) } #[doc = "Bit 11 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_hifi4_scfg_sram_config_vg( &mut self, - ) -> U0_HIFI4_SCFG_SRAM_CONFIG_VG_W { - U0_HIFI4_SCFG_SRAM_CONFIG_VG_W::new(self) + ) -> U0_HIFI4_SCFG_SRAM_CONFIG_VG_W { + U0_HIFI4_SCFG_SRAM_CONFIG_VG_W::new(self, 11) } #[doc = "Bit 12 - When the value is 1, it indicates that the AltResetVec is valid"] #[inline(always)] #[must_use] pub fn u0_hifi4_statvectorsel( &mut self, - ) -> U0_HIFI4_STATVECTORSEL_W { - U0_HIFI4_STATVECTORSEL_W::new(self) + ) -> U0_HIFI4_STATVECTORSEL_W { + U0_HIFI4_STATVECTORSEL_W::new(self, 12) } #[doc = "Bit 13 - DMA port trigger"] #[inline(always)] #[must_use] - pub fn u0_hifi4_trigin_idma( - &mut self, - ) -> U0_HIFI4_TRIGIN_IDMA_W { - U0_HIFI4_TRIGIN_IDMA_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn u0_hifi4_trigin_idma(&mut self) -> U0_HIFI4_TRIGIN_IDMA_W { + U0_HIFI4_TRIGIN_IDMA_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg680.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg680.rs index 777ecfb..6511134 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg680.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg680.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_415_384` reader - u1_plda_pcie_k_phyparam_415_384"] pub type U1_PLDA_PCIE_K_PHYPARAM_415_384_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_415_384` writer - u1_plda_pcie_k_phyparam_415_384"] -pub type U1_PLDA_PCIE_K_PHYPARAM_415_384_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_415_384_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_415_384"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_415_384( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_415_384_W { - U1_PLDA_PCIE_K_PHYPARAM_415_384_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_415_384_W { + U1_PLDA_PCIE_K_PHYPARAM_415_384_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg684.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg684.rs index c2373e8..3730b51 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg684.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg684.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_447_416` reader - u1_plda_pcie_k_phyparam_447_416"] pub type U1_PLDA_PCIE_K_PHYPARAM_447_416_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_447_416` writer - u1_plda_pcie_k_phyparam_447_416"] -pub type U1_PLDA_PCIE_K_PHYPARAM_447_416_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_447_416_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_447_416"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_447_416( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_447_416_W { - U1_PLDA_PCIE_K_PHYPARAM_447_416_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_447_416_W { + U1_PLDA_PCIE_K_PHYPARAM_447_416_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg688.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg688.rs index c2441b3..42d0273 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg688.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg688.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_479_448` reader - u1_plda_pcie_k_phyparam_479_448"] pub type U1_PLDA_PCIE_K_PHYPARAM_479_448_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_479_448` writer - u1_plda_pcie_k_phyparam_479_448"] -pub type U1_PLDA_PCIE_K_PHYPARAM_479_448_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_479_448_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_479_448"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_479_448( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_479_448_W { - U1_PLDA_PCIE_K_PHYPARAM_479_448_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_479_448_W { + U1_PLDA_PCIE_K_PHYPARAM_479_448_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg692.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg692.rs index 0961da4..78bdbd1 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg692.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg692.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_511_480` reader - u1_plda_pcie_k_phyparam_511_480"] pub type U1_PLDA_PCIE_K_PHYPARAM_511_480_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_511_480` writer - u1_plda_pcie_k_phyparam_511_480"] -pub type U1_PLDA_PCIE_K_PHYPARAM_511_480_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_511_480_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_511_480"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_511_480( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_511_480_W { - U1_PLDA_PCIE_K_PHYPARAM_511_480_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_511_480_W { + U1_PLDA_PCIE_K_PHYPARAM_511_480_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg696.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg696.rs index 131098f..b092a7d 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg696.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg696.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_543_512` reader - u1_plda_pcie_k_phyparam_543_512"] pub type U1_PLDA_PCIE_K_PHYPARAM_543_512_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_543_512` writer - u1_plda_pcie_k_phyparam_543_512"] -pub type U1_PLDA_PCIE_K_PHYPARAM_543_512_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_543_512_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_543_512"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_543_512( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_543_512_W { - U1_PLDA_PCIE_K_PHYPARAM_543_512_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_543_512_W { + U1_PLDA_PCIE_K_PHYPARAM_543_512_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg700.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg700.rs index 5a64c84..1a3f809 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg700.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg700.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_575_544` reader - u1_plda_pcie_k_phyparam_575_544"] pub type U1_PLDA_PCIE_K_PHYPARAM_575_544_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_575_544` writer - u1_plda_pcie_k_phyparam_575_544"] -pub type U1_PLDA_PCIE_K_PHYPARAM_575_544_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_575_544_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_575_544"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_575_544( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_575_544_W { - U1_PLDA_PCIE_K_PHYPARAM_575_544_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_575_544_W { + U1_PLDA_PCIE_K_PHYPARAM_575_544_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg704.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg704.rs index 74c01cf..b1d0ac8 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg704.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg704.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_607_576` reader - u1_plda_pcie_k_phyparam_607_576"] pub type U1_PLDA_PCIE_K_PHYPARAM_607_576_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_607_576` writer - u1_plda_pcie_k_phyparam_607_576"] -pub type U1_PLDA_PCIE_K_PHYPARAM_607_576_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_607_576_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_607_576"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_607_576( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_607_576_W { - U1_PLDA_PCIE_K_PHYPARAM_607_576_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_607_576_W { + U1_PLDA_PCIE_K_PHYPARAM_607_576_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg708.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg708.rs index 1d38d31..774d93e 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg708.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg708.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_639_608` reader - u1_plda_pcie_k_phyparam_639_608"] pub type U1_PLDA_PCIE_K_PHYPARAM_639_608_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_639_608` writer - u1_plda_pcie_k_phyparam_639_608"] -pub type U1_PLDA_PCIE_K_PHYPARAM_639_608_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_639_608_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_639_608"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_639_608( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_639_608_W { - U1_PLDA_PCIE_K_PHYPARAM_639_608_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_639_608_W { + U1_PLDA_PCIE_K_PHYPARAM_639_608_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg712.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg712.rs index 1e583dd..9e83df8 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg712.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg712.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_671_640` reader - u1_plda_pcie_k_phyparam_671_640"] pub type U1_PLDA_PCIE_K_PHYPARAM_671_640_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_671_640` writer - u1_plda_pcie_k_phyparam_671_640"] -pub type U1_PLDA_PCIE_K_PHYPARAM_671_640_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_671_640_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_671_640"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_671_640( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_671_640_W { - U1_PLDA_PCIE_K_PHYPARAM_671_640_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_671_640_W { + U1_PLDA_PCIE_K_PHYPARAM_671_640_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg716.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg716.rs index 030c5a8..a7ba456 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg716.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg716.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_703_672` reader - u1_plda_pcie_k_phyparam_703_672"] pub type U1_PLDA_PCIE_K_PHYPARAM_703_672_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_703_672` writer - u1_plda_pcie_k_phyparam_703_672"] -pub type U1_PLDA_PCIE_K_PHYPARAM_703_672_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_703_672_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_703_672"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_703_672( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_703_672_W { - U1_PLDA_PCIE_K_PHYPARAM_703_672_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_703_672_W { + U1_PLDA_PCIE_K_PHYPARAM_703_672_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg72.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg72.rs index bae7518..fc60c54 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg72.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg72.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg720.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg720.rs index aae170d..b03d03c 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg720.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg720.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_735_704` reader - u1_plda_pcie_k_phyparam_735_704"] pub type U1_PLDA_PCIE_K_PHYPARAM_735_704_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_735_704` writer - u1_plda_pcie_k_phyparam_735_704"] -pub type U1_PLDA_PCIE_K_PHYPARAM_735_704_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_735_704_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_735_704"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_735_704( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_735_704_W { - U1_PLDA_PCIE_K_PHYPARAM_735_704_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_735_704_W { + U1_PLDA_PCIE_K_PHYPARAM_735_704_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg724.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg724.rs index 9659d58..596c1ba 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg724.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg724.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_767_736` reader - u1_plda_pcie_k_phyparam_767_736"] pub type U1_PLDA_PCIE_K_PHYPARAM_767_736_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_767_736` writer - u1_plda_pcie_k_phyparam_767_736"] -pub type U1_PLDA_PCIE_K_PHYPARAM_767_736_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_767_736_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_767_736"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_767_736( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_767_736_W { - U1_PLDA_PCIE_K_PHYPARAM_767_736_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_767_736_W { + U1_PLDA_PCIE_K_PHYPARAM_767_736_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg728.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg728.rs index 0c676a9..2328a2e 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg728.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg728.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_799_768` reader - u1_plda_pcie_k_phyparam_799_768"] pub type U1_PLDA_PCIE_K_PHYPARAM_799_768_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_799_768` writer - u1_plda_pcie_k_phyparam_799_768"] -pub type U1_PLDA_PCIE_K_PHYPARAM_799_768_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_799_768_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_799_768"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_799_768( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_799_768_W { - U1_PLDA_PCIE_K_PHYPARAM_799_768_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_799_768_W { + U1_PLDA_PCIE_K_PHYPARAM_799_768_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg732.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg732.rs index 447ba10..c930a10 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg732.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg732.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_831_800` reader - u1_plda_pcie_k_phyparam_831_800"] pub type U1_PLDA_PCIE_K_PHYPARAM_831_800_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_831_800` writer - u1_plda_pcie_k_phyparam_831_800"] -pub type U1_PLDA_PCIE_K_PHYPARAM_831_800_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_831_800_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_831_800"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_831_800( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_831_800_W { - U1_PLDA_PCIE_K_PHYPARAM_831_800_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_831_800_W { + U1_PLDA_PCIE_K_PHYPARAM_831_800_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg736.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg736.rs index a5b0cf6..8722485 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg736.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg736.rs @@ -5,18 +5,17 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_839_832` reader - u1_plda_pcie_k_phyparam_839_832"] pub type U1_PLDA_PCIE_K_PHYPARAM_839_832_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_839_832` writer - u1_plda_pcie_k_phyparam_839_832"] -pub type U1_PLDA_PCIE_K_PHYPARAM_839_832_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 8, O>; +pub type U1_PLDA_PCIE_K_PHYPARAM_839_832_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `u1_plda_pcie_k_rp_nep` reader - u1_plda_pcie_k_rp_nep"] pub type U1_PLDA_PCIE_K_RP_NEP_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_k_rp_nep` writer - u1_plda_pcie_k_rp_nep"] -pub type U1_PLDA_PCIE_K_RP_NEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_K_RP_NEP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_l1sub_entack` reader - u1_plda_pcie_l1sub_entack"] pub type U1_PLDA_PCIE_L1SUB_ENTACK_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_l1sub_entreq` reader - u1_plda_pcie_l1sub_entreq"] pub type U1_PLDA_PCIE_L1SUB_ENTREQ_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_l1sub_entreq` writer - u1_plda_pcie_l1sub_entreq"] -pub type U1_PLDA_PCIE_L1SUB_ENTREQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_L1SUB_ENTREQ_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - u1_plda_pcie_k_phyparam_839_832"] #[inline(always)] @@ -45,26 +44,30 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_839_832( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_839_832_W { - U1_PLDA_PCIE_K_PHYPARAM_839_832_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_839_832_W { + U1_PLDA_PCIE_K_PHYPARAM_839_832_W::new(self, 0) } #[doc = "Bit 8 - u1_plda_pcie_k_rp_nep"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_k_rp_nep( &mut self, - ) -> U1_PLDA_PCIE_K_RP_NEP_W { - U1_PLDA_PCIE_K_RP_NEP_W::new(self) + ) -> U1_PLDA_PCIE_K_RP_NEP_W { + U1_PLDA_PCIE_K_RP_NEP_W::new(self, 8) } #[doc = "Bit 10 - u1_plda_pcie_l1sub_entreq"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_l1sub_entreq( &mut self, - ) -> U1_PLDA_PCIE_L1SUB_ENTREQ_W { - U1_PLDA_PCIE_L1SUB_ENTREQ_W::new(self) + ) -> U1_PLDA_PCIE_L1SUB_ENTREQ_W { + U1_PLDA_PCIE_L1SUB_ENTREQ_W::new(self, 10) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg740.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg740.rs index c23e470..8dfb9f4 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg740.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg740.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_local_interrupt_in` reader - u1_plda_pcie_local_interrupt_in"] pub type U1_PLDA_PCIE_LOCAL_INTERRUPT_IN_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_local_interrupt_in` writer - u1_plda_pcie_local_interrupt_in"] -pub type U1_PLDA_PCIE_LOCAL_INTERRUPT_IN_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_LOCAL_INTERRUPT_IN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_local_interrupt_in"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_local_interrupt_in( &mut self, - ) -> U1_PLDA_PCIE_LOCAL_INTERRUPT_IN_W { - U1_PLDA_PCIE_LOCAL_INTERRUPT_IN_W::new(self) + ) -> U1_PLDA_PCIE_LOCAL_INTERRUPT_IN_W { + U1_PLDA_PCIE_LOCAL_INTERRUPT_IN_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg744.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg744.rs index 37dc7fe..fe77514 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg744.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg744.rs @@ -5,28 +5,27 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_mperstn` reader - u1_plda_pcie_mperstn"] pub type U1_PLDA_PCIE_MPERSTN_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_mperstn` writer - u1_plda_pcie_mperstn"] -pub type U1_PLDA_PCIE_MPERSTN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_MPERSTN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_pcie_ebuf_mode` reader - u1_plda_pcie_pcie_ebuf_mode"] pub type U1_PLDA_PCIE_PCIE_EBUF_MODE_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_pcie_ebuf_mode` writer - u1_plda_pcie_pcie_ebuf_mode"] -pub type U1_PLDA_PCIE_PCIE_EBUF_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_PCIE_EBUF_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_pcie_phy_test_cfg` reader - u1_plda_pcie_pcie_phy_test_cfg"] pub type U1_PLDA_PCIE_PCIE_PHY_TEST_CFG_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pcie_phy_test_cfg` writer - u1_plda_pcie_pcie_phy_test_cfg"] -pub type U1_PLDA_PCIE_PCIE_PHY_TEST_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 23, O, u32>; +pub type U1_PLDA_PCIE_PCIE_PHY_TEST_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>; #[doc = "Field `u1_plda_pcie_pcie_rx_eq_training` reader - u1_plda_pcie_pcie_rx_eq_training"] pub type U1_PLDA_PCIE_PCIE_RX_EQ_TRAINING_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_pcie_rx_eq_training` writer - u1_plda_pcie_pcie_rx_eq_training"] -pub type U1_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_pcie_rxterm_en` reader - u1_plda_pcie_pcie_rxterm_en"] pub type U1_PLDA_PCIE_PCIE_RXTERM_EN_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_pcie_rxterm_en` writer - u1_plda_pcie_pcie_rxterm_en"] -pub type U1_PLDA_PCIE_PCIE_RXTERM_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_PCIE_RXTERM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_pcie_tx_oneszeros` reader - u1_plda_pcie_pcie_tx_oneszeros"] pub type U1_PLDA_PCIE_PCIE_TX_ONESZEROS_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_pcie_tx_oneszeros` writer - u1_plda_pcie_pcie_tx_oneszeros"] -pub type U1_PLDA_PCIE_PCIE_TX_ONESZEROS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_PCIE_TX_ONESZEROS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - u1_plda_pcie_mperstn"] #[inline(always)] @@ -65,50 +64,54 @@ impl W { #[must_use] pub fn u1_plda_pcie_mperstn( &mut self, - ) -> U1_PLDA_PCIE_MPERSTN_W { - U1_PLDA_PCIE_MPERSTN_W::new(self) + ) -> U1_PLDA_PCIE_MPERSTN_W { + U1_PLDA_PCIE_MPERSTN_W::new(self, 0) } #[doc = "Bit 1 - u1_plda_pcie_pcie_ebuf_mode"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_pcie_ebuf_mode( &mut self, - ) -> U1_PLDA_PCIE_PCIE_EBUF_MODE_W { - U1_PLDA_PCIE_PCIE_EBUF_MODE_W::new(self) + ) -> U1_PLDA_PCIE_PCIE_EBUF_MODE_W { + U1_PLDA_PCIE_PCIE_EBUF_MODE_W::new(self, 1) } #[doc = "Bits 2:24 - u1_plda_pcie_pcie_phy_test_cfg"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_pcie_phy_test_cfg( &mut self, - ) -> U1_PLDA_PCIE_PCIE_PHY_TEST_CFG_W { - U1_PLDA_PCIE_PCIE_PHY_TEST_CFG_W::new(self) + ) -> U1_PLDA_PCIE_PCIE_PHY_TEST_CFG_W { + U1_PLDA_PCIE_PCIE_PHY_TEST_CFG_W::new(self, 2) } #[doc = "Bit 25 - u1_plda_pcie_pcie_rx_eq_training"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_pcie_rx_eq_training( &mut self, - ) -> U1_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W { - U1_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W::new(self) + ) -> U1_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W { + U1_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W::new(self, 25) } #[doc = "Bit 26 - u1_plda_pcie_pcie_rxterm_en"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_pcie_rxterm_en( &mut self, - ) -> U1_PLDA_PCIE_PCIE_RXTERM_EN_W { - U1_PLDA_PCIE_PCIE_RXTERM_EN_W::new(self) + ) -> U1_PLDA_PCIE_PCIE_RXTERM_EN_W { + U1_PLDA_PCIE_PCIE_RXTERM_EN_W::new(self, 26) } #[doc = "Bit 27 - u1_plda_pcie_pcie_tx_oneszeros"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_pcie_tx_oneszeros( &mut self, - ) -> U1_PLDA_PCIE_PCIE_TX_ONESZEROS_W { - U1_PLDA_PCIE_PCIE_TX_ONESZEROS_W::new(self) + ) -> U1_PLDA_PCIE_PCIE_TX_ONESZEROS_W { + U1_PLDA_PCIE_PCIE_TX_ONESZEROS_W::new(self, 27) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg748.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg748.rs index 934c7e8..5219008 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg748.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg748.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pf0_offset` reader - u1_plda_pcie_pf0_offset"] pub type U1_PLDA_PCIE_PF0_OFFSET_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pf0_offset` writer - u1_plda_pcie_pf0_offset"] -pub type U1_PLDA_PCIE_PF0_OFFSET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; +pub type U1_PLDA_PCIE_PF0_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; impl R { #[doc = "Bits 0:19 - u1_plda_pcie_pf0_offset"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_pf0_offset( &mut self, - ) -> U1_PLDA_PCIE_PF0_OFFSET_W { - U1_PLDA_PCIE_PF0_OFFSET_W::new(self) + ) -> U1_PLDA_PCIE_PF0_OFFSET_W { + U1_PLDA_PCIE_PF0_OFFSET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg752.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg752.rs index dcf3eff..2aaea4c 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg752.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg752.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pf1_offset` reader - u1_plda_pcie_pf1_offset"] pub type U1_PLDA_PCIE_PF1_OFFSET_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pf1_offset` writer - u1_plda_pcie_pf1_offset"] -pub type U1_PLDA_PCIE_PF1_OFFSET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; +pub type U1_PLDA_PCIE_PF1_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; impl R { #[doc = "Bits 0:19 - u1_plda_pcie_pf1_offset"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_pf1_offset( &mut self, - ) -> U1_PLDA_PCIE_PF1_OFFSET_W { - U1_PLDA_PCIE_PF1_OFFSET_W::new(self) + ) -> U1_PLDA_PCIE_PF1_OFFSET_W { + U1_PLDA_PCIE_PF1_OFFSET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg756.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg756.rs index c723c87..0368fef 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg756.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg756.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pf2_offset` reader - u1_plda_pcie_pf2_offset"] pub type U1_PLDA_PCIE_PF2_OFFSET_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pf2_offset` writer - u1_plda_pcie_pf2_offset"] -pub type U1_PLDA_PCIE_PF2_OFFSET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; +pub type U1_PLDA_PCIE_PF2_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; impl R { #[doc = "Bits 0:19 - u1_plda_pcie_pf2_offset"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_pf2_offset( &mut self, - ) -> U1_PLDA_PCIE_PF2_OFFSET_W { - U1_PLDA_PCIE_PF2_OFFSET_W::new(self) + ) -> U1_PLDA_PCIE_PF2_OFFSET_W { + U1_PLDA_PCIE_PF2_OFFSET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg76.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg76.rs index 51aad11..6eb35c2 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg76.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg76.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg760.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg760.rs index d85e5b0..544aa4b 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg760.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg760.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pf3_offset` reader - u1_plda_pcie_pf3_offset"] pub type U1_PLDA_PCIE_PF3_OFFSET_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pf3_offset` writer - u1_plda_pcie_pf3_offset"] -pub type U1_PLDA_PCIE_PF3_OFFSET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; +pub type U1_PLDA_PCIE_PF3_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; #[doc = "Field `u1_plda_pcie_phy_mode` reader - u1_plda_pcie_phy_mode"] pub type U1_PLDA_PCIE_PHY_MODE_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_phy_mode` writer - u1_plda_pcie_phy_mode"] -pub type U1_PLDA_PCIE_PHY_MODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U1_PLDA_PCIE_PHY_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_plda_pcie_pl_clkrem_allow` reader - u1_plda_pcie_pl_clkrem_allow"] pub type U1_PLDA_PCIE_PL_CLKREM_ALLOW_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_pl_clkrem_allow` writer - u1_plda_pcie_pl_clkrem_allow"] -pub type U1_PLDA_PCIE_PL_CLKREM_ALLOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_PL_CLKREM_ALLOW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_pl_clkreq_oen` reader - u1_plda_pcie_pl_clkreq_oen"] pub type U1_PLDA_PCIE_PL_CLKREQ_OEN_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_pl_equ_phase` reader - u1_plda_pcie_pl_equ_phase"] @@ -58,26 +58,30 @@ impl W { #[must_use] pub fn u1_plda_pcie_pf3_offset( &mut self, - ) -> U1_PLDA_PCIE_PF3_OFFSET_W { - U1_PLDA_PCIE_PF3_OFFSET_W::new(self) + ) -> U1_PLDA_PCIE_PF3_OFFSET_W { + U1_PLDA_PCIE_PF3_OFFSET_W::new(self, 0) } #[doc = "Bits 20:21 - u1_plda_pcie_phy_mode"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_phy_mode( &mut self, - ) -> U1_PLDA_PCIE_PHY_MODE_W { - U1_PLDA_PCIE_PHY_MODE_W::new(self) + ) -> U1_PLDA_PCIE_PHY_MODE_W { + U1_PLDA_PCIE_PHY_MODE_W::new(self, 20) } #[doc = "Bit 22 - u1_plda_pcie_pl_clkrem_allow"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_pl_clkrem_allow( &mut self, - ) -> U1_PLDA_PCIE_PL_CLKREM_ALLOW_W { - U1_PLDA_PCIE_PL_CLKREM_ALLOW_W::new(self) + ) -> U1_PLDA_PCIE_PL_CLKREM_ALLOW_W { + U1_PLDA_PCIE_PL_CLKREM_ALLOW_W::new(self, 22) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg764.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg764.rs index ac9e3f7..86b5eb5 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg764.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg764.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg768.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg768.rs index 04830e2..ff4f581 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg768.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg768.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pl_sideband_in_31_0` reader - u1_plda_pcie_pl_sideband_in_31_0"] pub type U1_PLDA_PCIE_PL_SIDEBAND_IN_31_0_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pl_sideband_in_31_0` writer - u1_plda_pcie_pl_sideband_in_31_0"] -pub type U1_PLDA_PCIE_PL_SIDEBAND_IN_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_PL_SIDEBAND_IN_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_pl_sideband_in_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_pl_sideband_in_31_0( &mut self, - ) -> U1_PLDA_PCIE_PL_SIDEBAND_IN_31_0_W { - U1_PLDA_PCIE_PL_SIDEBAND_IN_31_0_W::new(self) + ) -> U1_PLDA_PCIE_PL_SIDEBAND_IN_31_0_W { + U1_PLDA_PCIE_PL_SIDEBAND_IN_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg772.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg772.rs index 882a27a..3552f55 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg772.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg772.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pl_sideband_in_63_32` reader - u1_plda_pcie_pl_sideband_in_63_32"] pub type U1_PLDA_PCIE_PL_SIDEBAND_IN_63_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pl_sideband_in_63_32` writer - u1_plda_pcie_pl_sideband_in_63_32"] -pub type U1_PLDA_PCIE_PL_SIDEBAND_IN_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_PL_SIDEBAND_IN_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_pl_sideband_in_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_pl_sideband_in_63_32( &mut self, - ) -> U1_PLDA_PCIE_PL_SIDEBAND_IN_63_32_W { - U1_PLDA_PCIE_PL_SIDEBAND_IN_63_32_W::new(self) + ) -> U1_PLDA_PCIE_PL_SIDEBAND_IN_63_32_W { + U1_PLDA_PCIE_PL_SIDEBAND_IN_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg776.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg776.rs index f543076..8da58f1 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg776.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg776.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pl_sideband_out_31_0` reader - u1_plda_pcie_pl_sideband_out_31_0"] pub type U1_PLDA_PCIE_PL_SIDEBAND_OUT_31_0_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pl_sideband_out_31_0` writer - u1_plda_pcie_pl_sideband_out_31_0"] -pub type U1_PLDA_PCIE_PL_SIDEBAND_OUT_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_PL_SIDEBAND_OUT_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_pl_sideband_out_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_pl_sideband_out_31_0( &mut self, - ) -> U1_PLDA_PCIE_PL_SIDEBAND_OUT_31_0_W { - U1_PLDA_PCIE_PL_SIDEBAND_OUT_31_0_W::new(self) + ) -> U1_PLDA_PCIE_PL_SIDEBAND_OUT_31_0_W { + U1_PLDA_PCIE_PL_SIDEBAND_OUT_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg780.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg780.rs index c517118..c667cd4 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg780.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg780.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pl_sideband_out_63_32` reader - u1_plda_pcie_pl_sideband_out_63_32"] pub type U1_PLDA_PCIE_PL_SIDEBAND_OUT_63_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pl_sideband_out_63_32` writer - u1_plda_pcie_pl_sideband_out_63_32"] -pub type U1_PLDA_PCIE_PL_SIDEBAND_OUT_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_PL_SIDEBAND_OUT_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_pl_sideband_out_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_pl_sideband_out_63_32( &mut self, - ) -> U1_PLDA_PCIE_PL_SIDEBAND_OUT_63_32_W { - U1_PLDA_PCIE_PL_SIDEBAND_OUT_63_32_W::new(self) + ) -> U1_PLDA_PCIE_PL_SIDEBAND_OUT_63_32_W { + U1_PLDA_PCIE_PL_SIDEBAND_OUT_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg784.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg784.rs index 881e651..7e6a043 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg784.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg784.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pl_wake_in` reader - u1_plda_pcie_pl_wake_in"] pub type U1_PLDA_PCIE_PL_WAKE_IN_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_pl_wake_in` writer - u1_plda_pcie_pl_wake_in"] -pub type U1_PLDA_PCIE_PL_WAKE_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_PL_WAKE_IN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_pl_wake_oen` reader - u1_plda_pcie_pl_wake_oen"] pub type U1_PLDA_PCIE_PL_WAKE_OEN_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_rx_standby_o` reader - u1_plda_pcie_rx_standby_o"] @@ -33,10 +33,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_pl_wake_in( &mut self, - ) -> U1_PLDA_PCIE_PL_WAKE_IN_W { - U1_PLDA_PCIE_PL_WAKE_IN_W::new(self) + ) -> U1_PLDA_PCIE_PL_WAKE_IN_W { + U1_PLDA_PCIE_PL_WAKE_IN_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg788.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg788.rs index acb4c51..08151e7 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg788.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg788.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_in_31_0` reader - u1_plda_pcie_test_in_31_0"] pub type U1_PLDA_PCIE_TEST_IN_31_0_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_in_31_0` writer - u1_plda_pcie_test_in_31_0"] -pub type U1_PLDA_PCIE_TEST_IN_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_IN_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_in_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_in_31_0( &mut self, - ) -> U1_PLDA_PCIE_TEST_IN_31_0_W { - U1_PLDA_PCIE_TEST_IN_31_0_W::new(self) + ) -> U1_PLDA_PCIE_TEST_IN_31_0_W { + U1_PLDA_PCIE_TEST_IN_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg792.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg792.rs index 7ffb829..3c5c847 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg792.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg792.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_in_63_32` reader - u1_plda_pcie_test_in_63_32"] pub type U1_PLDA_PCIE_TEST_IN_63_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_in_63_32` writer - u1_plda_pcie_test_in_63_32"] -pub type U1_PLDA_PCIE_TEST_IN_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_IN_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_in_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_in_63_32( &mut self, - ) -> U1_PLDA_PCIE_TEST_IN_63_32_W { - U1_PLDA_PCIE_TEST_IN_63_32_W::new(self) + ) -> U1_PLDA_PCIE_TEST_IN_63_32_W { + U1_PLDA_PCIE_TEST_IN_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg796.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg796.rs index a713f23..4e2d314 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg796.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg796.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_31_0` reader - u1_plda_pcie_test_out_bridge_31_0"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_31_0_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_31_0` writer - u1_plda_pcie_test_out_bridge_31_0"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_31_0( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_31_0_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_31_0_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_31_0_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg8.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg8.rs index 5eca371..3aff8cd 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg8.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg8.rs @@ -9,7 +9,7 @@ pub type U0_CDN_USB_RX_RCV_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_self_test` reader - For software bist_test"] pub type U0_CDN_USB_SELF_TEST_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_self_test` writer - For software bist_test"] -pub type U0_CDN_USB_SELF_TEST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_SELF_TEST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_sessend` reader - u0_cdn_usb_sessend"] pub type U0_CDN_USB_SESSEND_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_sessvalid` reader - u0_cdn_usb_sessvalid"] @@ -25,8 +25,7 @@ pub type U0_CDN_USB_USBDEV_MAIN_POWER_OFF_READY_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_main_power_off_req` reader - u0_cdn_usb_usbdev_main_power_off_req"] pub type U0_CDN_USB_USBDEV_MAIN_POWER_OFF_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_main_power_off_req` writer - u0_cdn_usb_usbdev_main_power_off_req"] -pub type U0_CDN_USB_USBDEV_MAIN_POWER_OFF_REQ_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_USBDEV_MAIN_POWER_OFF_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_usbdev_main_power_on_ready` reader - u0_cdn_usb_usbdev_main_power_on_ready"] pub type U0_CDN_USB_USBDEV_MAIN_POWER_ON_READY_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_main_power_on_req` reader - u0_cdn_usb_usbdev_main_power_on_req"] @@ -34,8 +33,7 @@ pub type U0_CDN_USB_USBDEV_MAIN_POWER_ON_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_main_power_on_valid` reader - u0_cdn_usb_usbdev_main_power_on_valid"] pub type U0_CDN_USB_USBDEV_MAIN_POWER_ON_VALID_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_main_power_on_valid` writer - u0_cdn_usb_usbdev_main_power_on_valid"] -pub type U0_CDN_USB_USBDEV_MAIN_POWER_ON_VALID_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_USBDEV_MAIN_POWER_ON_VALID_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_usbdev_power_off_ack` reader - u0_cdn_usb_usbdev_power_off_ack"] pub type U0_CDN_USB_USBDEV_POWER_OFF_ACK_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_power_off_ready` reader - u0_cdn_usb_usbdev_power_off_ready"] @@ -43,7 +41,7 @@ pub type U0_CDN_USB_USBDEV_POWER_OFF_READY_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_power_off_req` reader - u0_cdn_usb_usbdev_power_off_req"] pub type U0_CDN_USB_USBDEV_POWER_OFF_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_power_off_req` writer - u0_cdn_usb_usbdev_power_off_req"] -pub type U0_CDN_USB_USBDEV_POWER_OFF_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_USBDEV_POWER_OFF_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_usbdev_power_on_ready` reader - u0_cdn_usb_usbdev_power_on_ready"] pub type U0_CDN_USB_USBDEV_POWER_ON_READY_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_power_on_req` reader - u0_cdn_usb_usbdev_power_on_req"] @@ -51,19 +49,19 @@ pub type U0_CDN_USB_USBDEV_POWER_ON_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_power_on_valid` reader - u0_cdn_usb_usbdev_power_on_valid"] pub type U0_CDN_USB_USBDEV_POWER_ON_VALID_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_power_on_valid` writer - u0_cdn_usb_usbdev_power_on_valid"] -pub type U0_CDN_USB_USBDEV_POWER_ON_VALID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_USBDEV_POWER_ON_VALID_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_dmpulldown_sit` reader - u0_cdn_usb_utmi_dmpulldown_sit"] pub type U0_CDN_USB_UTMI_DMPULLDOWN_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_dmpulldown_sit` writer - u0_cdn_usb_utmi_dmpulldown_sit"] -pub type U0_CDN_USB_UTMI_DMPULLDOWN_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_DMPULLDOWN_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_dppulldown_sit` reader - u0_cdn_usb_utmi_dppulldown_sit"] pub type U0_CDN_USB_UTMI_DPPULLDOWN_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_dppulldown_sit` writer - u0_cdn_usb_utmi_dppulldown_sit"] -pub type U0_CDN_USB_UTMI_DPPULLDOWN_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_DPPULLDOWN_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_fslsserialmode_sit` reader - u0_cdn_usb_utmi_fslsserialmode_sit"] pub type U0_CDN_USB_UTMI_FSLSSERIALMODE_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_fslsserialmode_sit` writer - u0_cdn_usb_utmi_fslsserialmode_sit"] -pub type U0_CDN_USB_UTMI_FSLSSERIALMODE_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_FSLSSERIALMODE_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_hostdisconnect_sit` reader - u0_cdn_usb_utmi_hostdisconnect_sit"] pub type U0_CDN_USB_UTMI_HOSTDISCONNECT_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_iddig_sit` reader - u0_cdn_usb_utmi_iddig_sit"] @@ -71,13 +69,13 @@ pub type U0_CDN_USB_UTMI_IDDIG_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_idpullup_sit` reader - u0_cdn_usb_utmi_idpullup_sit"] pub type U0_CDN_USB_UTMI_IDPULLUP_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_idpullup_sit` writer - u0_cdn_usb_utmi_idpullup_sit"] -pub type U0_CDN_USB_UTMI_IDPULLUP_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_IDPULLUP_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_linestate_sit` reader - u0_cdn_usb_utmi_linestate_sit"] pub type U0_CDN_USB_UTMI_LINESTATE_SIT_R = crate::FieldReader; #[doc = "Field `u0_cdn_usb_utmi_opmode_sit` reader - u0_cdn_usb_utmi_opmode_sit"] pub type U0_CDN_USB_UTMI_OPMODE_SIT_R = crate::FieldReader; #[doc = "Field `u0_cdn_usb_utmi_opmode_sit` writer - u0_cdn_usb_utmi_opmode_sit"] -pub type U0_CDN_USB_UTMI_OPMODE_SIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDN_USB_UTMI_OPMODE_SIT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdn_usb_utmi_rxactive_sit` reader - u0_cdn_usb_utmi_rxactive_sit"] pub type U0_CDN_USB_UTMI_RXACTIVE_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_rxerror_sit` reader - u0_cdn_usb_utmi_rxerror_sit"] @@ -242,84 +240,86 @@ impl W { #[doc = "Bit 2 - For software bist_test"] #[inline(always)] #[must_use] - pub fn u0_cdn_usb_self_test( - &mut self, - ) -> U0_CDN_USB_SELF_TEST_W { - U0_CDN_USB_SELF_TEST_W::new(self) + pub fn u0_cdn_usb_self_test(&mut self) -> U0_CDN_USB_SELF_TEST_W { + U0_CDN_USB_SELF_TEST_W::new(self, 2) } #[doc = "Bit 9 - u0_cdn_usb_usbdev_main_power_off_req"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_usbdev_main_power_off_req( &mut self, - ) -> U0_CDN_USB_USBDEV_MAIN_POWER_OFF_REQ_W { - U0_CDN_USB_USBDEV_MAIN_POWER_OFF_REQ_W::new(self) + ) -> U0_CDN_USB_USBDEV_MAIN_POWER_OFF_REQ_W { + U0_CDN_USB_USBDEV_MAIN_POWER_OFF_REQ_W::new(self, 9) } #[doc = "Bit 12 - u0_cdn_usb_usbdev_main_power_on_valid"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_usbdev_main_power_on_valid( &mut self, - ) -> U0_CDN_USB_USBDEV_MAIN_POWER_ON_VALID_W { - U0_CDN_USB_USBDEV_MAIN_POWER_ON_VALID_W::new(self) + ) -> U0_CDN_USB_USBDEV_MAIN_POWER_ON_VALID_W { + U0_CDN_USB_USBDEV_MAIN_POWER_ON_VALID_W::new(self, 12) } #[doc = "Bit 15 - u0_cdn_usb_usbdev_power_off_req"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_usbdev_power_off_req( &mut self, - ) -> U0_CDN_USB_USBDEV_POWER_OFF_REQ_W { - U0_CDN_USB_USBDEV_POWER_OFF_REQ_W::new(self) + ) -> U0_CDN_USB_USBDEV_POWER_OFF_REQ_W { + U0_CDN_USB_USBDEV_POWER_OFF_REQ_W::new(self, 15) } #[doc = "Bit 18 - u0_cdn_usb_usbdev_power_on_valid"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_usbdev_power_on_valid( &mut self, - ) -> U0_CDN_USB_USBDEV_POWER_ON_VALID_W { - U0_CDN_USB_USBDEV_POWER_ON_VALID_W::new(self) + ) -> U0_CDN_USB_USBDEV_POWER_ON_VALID_W { + U0_CDN_USB_USBDEV_POWER_ON_VALID_W::new(self, 18) } #[doc = "Bit 19 - u0_cdn_usb_utmi_dmpulldown_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_dmpulldown_sit( &mut self, - ) -> U0_CDN_USB_UTMI_DMPULLDOWN_SIT_W { - U0_CDN_USB_UTMI_DMPULLDOWN_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_DMPULLDOWN_SIT_W { + U0_CDN_USB_UTMI_DMPULLDOWN_SIT_W::new(self, 19) } #[doc = "Bit 20 - u0_cdn_usb_utmi_dppulldown_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_dppulldown_sit( &mut self, - ) -> U0_CDN_USB_UTMI_DPPULLDOWN_SIT_W { - U0_CDN_USB_UTMI_DPPULLDOWN_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_DPPULLDOWN_SIT_W { + U0_CDN_USB_UTMI_DPPULLDOWN_SIT_W::new(self, 20) } #[doc = "Bit 21 - u0_cdn_usb_utmi_fslsserialmode_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_fslsserialmode_sit( &mut self, - ) -> U0_CDN_USB_UTMI_FSLSSERIALMODE_SIT_W { - U0_CDN_USB_UTMI_FSLSSERIALMODE_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_FSLSSERIALMODE_SIT_W { + U0_CDN_USB_UTMI_FSLSSERIALMODE_SIT_W::new(self, 21) } #[doc = "Bit 24 - u0_cdn_usb_utmi_idpullup_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_idpullup_sit( &mut self, - ) -> U0_CDN_USB_UTMI_IDPULLUP_SIT_W { - U0_CDN_USB_UTMI_IDPULLUP_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_IDPULLUP_SIT_W { + U0_CDN_USB_UTMI_IDPULLUP_SIT_W::new(self, 24) } #[doc = "Bits 27:28 - u0_cdn_usb_utmi_opmode_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_opmode_sit( &mut self, - ) -> U0_CDN_USB_UTMI_OPMODE_SIT_W { - U0_CDN_USB_UTMI_OPMODE_SIT_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_CDN_USB_UTMI_OPMODE_SIT_W { + U0_CDN_USB_UTMI_OPMODE_SIT_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg80.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg80.rs index 6cfbbe4..830be3f 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg80.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg80.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg800.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg800.rs index 563a0ff..13c21d2 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg800.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg800.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_63_32` reader - u1_plda_pcie_test_out_bridge_63_32"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_63_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_63_32` writer - u1_plda_pcie_test_out_bridge_63_32"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_63_32( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_63_32_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_63_32_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_63_32_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg804.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg804.rs index 728e5a1..6a91287 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg804.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg804.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_95_64` reader - u1_plda_pcie_test_out_bridge_95_64"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_95_64_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_95_64` writer - u1_plda_pcie_test_out_bridge_95_64"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_95_64_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_95_64_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_95_64"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_95_64( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_95_64_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_95_64_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_95_64_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_95_64_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg808.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg808.rs index 5a64cbc..999071b 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg808.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg808.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_127_96` reader - u1_plda_pcie_test_out_bridge_127_96"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_127_96_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_127_96` writer - u1_plda_pcie_test_out_bridge_127_96"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_127_96_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_127_96_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_127_96"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_127_96( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_127_96_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_127_96_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_127_96_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_127_96_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg812.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg812.rs index 16b4fbc..d046c29 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg812.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg812.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_159_128` reader - u1_plda_pcie_test_out_bridge_159_128"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_159_128_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_159_128` writer - u1_plda_pcie_test_out_bridge_159_128"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_159_128_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_159_128_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_159_128"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_159_128( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_159_128_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_159_128_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_159_128_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_159_128_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg816.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg816.rs index 7d7894a..5bbb50e 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg816.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg816.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_191_160` reader - u1_plda_pcie_test_out_bridge_191_160"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_191_160_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_191_160` writer - u1_plda_pcie_test_out_bridge_191_160"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_191_160_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_191_160_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_191_160"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_191_160( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_191_160_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_191_160_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_191_160_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_191_160_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg820.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg820.rs index 9a9f6a8..c11e306 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg820.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg820.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_223_192` reader - u1_plda_pcie_test_out_bridge_223_192"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_223_192_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_223_192` writer - u1_plda_pcie_test_out_bridge_223_192"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_223_192_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_223_192_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_223_192"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_223_192( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_223_192_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_223_192_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_223_192_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_223_192_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg824.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg824.rs index 6f10dd4..ba51067 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg824.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg824.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_255_224` reader - u1_plda_pcie_test_out_bridge_255_224"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_255_224_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_255_224` writer - u1_plda_pcie_test_out_bridge_255_224"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_255_224_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_255_224_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_255_224"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_255_224( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_255_224_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_255_224_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_255_224_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_255_224_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg828.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg828.rs index 9110f51..622aa1c 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg828.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg828.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_287_256` reader - u1_plda_pcie_test_out_bridge_287_256"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_287_256_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_287_256` writer - u1_plda_pcie_test_out_bridge_287_256"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_287_256_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_287_256_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_287_256"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_287_256( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_287_256_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_287_256_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_287_256_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_287_256_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg832.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg832.rs index e15a256..f7c65d6 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg832.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg832.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_319_288` reader - u1_plda_pcie_test_out_bridge_319_288"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_319_288_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_319_288` writer - u1_plda_pcie_test_out_bridge_319_288"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_319_288_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_319_288_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_319_288"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_319_288( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_319_288_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_319_288_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_319_288_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_319_288_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg836.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg836.rs index 99401ff..fb792da 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg836.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg836.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_351_320` reader - u1_plda_pcie_test_out_bridge_351_320"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_351_320_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_351_320` writer - u1_plda_pcie_test_out_bridge_351_320"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_351_320_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_351_320_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_351_320"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_351_320( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_351_320_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_351_320_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_351_320_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_351_320_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg84.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg84.rs index 52520dc..8658803 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg84.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg84.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg840.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg840.rs index c2a4eb8..842a3bf 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg840.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg840.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_383_352` reader - u1_plda_pcie_test_out_bridge_383_352"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_383_352_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_383_352` writer - u1_plda_pcie_test_out_bridge_383_352"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_383_352_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_383_352_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_383_352"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_383_352( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_383_352_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_383_352_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_383_352_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_383_352_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg844.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg844.rs index ad2290b..4ec4202 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg844.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg844.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_415_384` reader - u1_plda_pcie_test_out_bridge_415_384"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_415_384_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_415_384` writer - u1_plda_pcie_test_out_bridge_415_384"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_415_384_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_415_384_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_415_384"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_415_384( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_415_384_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_415_384_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_415_384_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_415_384_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg848.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg848.rs index 599a9b0..fa8f59a 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg848.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg848.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_447_416` reader - u1_plda_pcie_test_out_bridge_447_416"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_447_416_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_447_416` writer - u1_plda_pcie_test_out_bridge_447_416"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_447_416_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_447_416_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_447_416"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_447_416( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_447_416_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_447_416_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_447_416_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_447_416_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg852.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg852.rs index 7fa112f..323ccd1 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg852.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg852.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_479_448` reader - u1_plda_pcie_test_out_bridge_479_448"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_479_448_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_479_448` writer - u1_plda_pcie_test_out_bridge_479_448"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_479_448_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_479_448_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_479_448"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_479_448( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_479_448_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_479_448_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_479_448_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_479_448_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg856.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg856.rs index 79732b0..bb9f9c8 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg856.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg856.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_511_480` reader - u1_plda_pcie_test_out_bridge_511_480"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_511_480_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_511_480` writer - u1_plda_pcie_test_out_bridge_511_480"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_511_480_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_511_480_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_511_480"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_511_480( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_511_480_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_511_480_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_511_480_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_511_480_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg860.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg860.rs index c380594..683947b 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg860.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg860.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg864.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg864.rs index 757638f..8a2f015 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg864.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg864.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg868.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg868.rs index a8d630d..fb6aeb0 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg868.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg868.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg872.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg872.rs index 2329ebe..bd4f69d 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg872.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg872.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg876.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg876.rs index 66c0517..ceb690c 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg876.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg876.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg88.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg88.rs index 0a65c73..46873db 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg88.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg88.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg880.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg880.rs index 63bbb42..c1f6a05 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg880.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg880.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg884.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg884.rs index b4297a5..93d4bed 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg884.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg884.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg888.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg888.rs index 4b879f4..bb30140 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg888.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg888.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg892.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg892.rs index 19f1f61..4b35fbb 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg892.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg892.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg896.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg896.rs index 47a7e79..4029ccf 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg896.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg896.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg900.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg900.rs index 6ebdb5b..31fb9ef 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg900.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg900.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg904.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg904.rs index 981fe96..578f91f 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg904.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg904.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg908.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg908.rs index 443d43c..32b5e7f 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg908.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg908.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg912.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg912.rs index d12bb2b..2727f3a 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg912.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg912.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg916.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg916.rs index 325b174..37ac21c 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg916.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg916.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg92.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg92.rs index 2872a53..b4b2cea 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg92.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg92.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg920.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg920.rs index e58f2b8..7309fd3 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg920.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg920.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg924.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg924.rs index 3980f06..d09dbb2 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg924.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg924.rs @@ -5,12 +5,11 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_sel` reader - u1_plda_pcie_test_sel"] pub type U1_PLDA_PCIE_TEST_SEL_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_sel` writer - u1_plda_pcie_test_sel"] -pub type U1_PLDA_PCIE_TEST_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type U1_PLDA_PCIE_TEST_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `u1_plda_pcie_tl_clock_freq` reader - u1_plda_pcie_tl_clock_freq"] pub type U1_PLDA_PCIE_TL_CLOCK_FREQ_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_tl_clock_freq` writer - u1_plda_pcie_tl_clock_freq"] -pub type U1_PLDA_PCIE_TL_CLOCK_FREQ_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 22, O, u32>; +pub type U1_PLDA_PCIE_TL_CLOCK_FREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; impl R { #[doc = "Bits 0:3 - u1_plda_pcie_test_sel"] #[inline(always)] @@ -29,18 +28,22 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_sel( &mut self, - ) -> U1_PLDA_PCIE_TEST_SEL_W { - U1_PLDA_PCIE_TEST_SEL_W::new(self) + ) -> U1_PLDA_PCIE_TEST_SEL_W { + U1_PLDA_PCIE_TEST_SEL_W::new(self, 0) } #[doc = "Bits 4:25 - u1_plda_pcie_tl_clock_freq"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_tl_clock_freq( &mut self, - ) -> U1_PLDA_PCIE_TL_CLOCK_FREQ_W { - U1_PLDA_PCIE_TL_CLOCK_FREQ_W::new(self) + ) -> U1_PLDA_PCIE_TL_CLOCK_FREQ_W { + U1_PLDA_PCIE_TL_CLOCK_FREQ_W::new(self, 4) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg928.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg928.rs index 60d4b3d..aeec659 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg928.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg928.rs @@ -7,8 +7,7 @@ pub type U1_PLDA_PCIE_TL_CTRL_HOTPLUG_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_tl_report_hotplug` reader - u1_plda_pcie_tl_report_hotplug"] pub type U1_PLDA_PCIE_TL_REPORT_HOTPLUG_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_tl_report_hotplug` writer - u1_plda_pcie_tl_report_hotplug"] -pub type U1_PLDA_PCIE_TL_REPORT_HOTPLUG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 16, O, u16>; +pub type U1_PLDA_PCIE_TL_REPORT_HOTPLUG_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - u1_plda_pcie_tl_ctrl_hotplug"] #[inline(always)] @@ -27,10 +26,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_tl_report_hotplug( &mut self, - ) -> U1_PLDA_PCIE_TL_REPORT_HOTPLUG_W { - U1_PLDA_PCIE_TL_REPORT_HOTPLUG_W::new(self) + ) -> U1_PLDA_PCIE_TL_REPORT_HOTPLUG_W { + U1_PLDA_PCIE_TL_REPORT_HOTPLUG_W::new(self, 16) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg932.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg932.rs index 852dcd8..277ae10 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg932.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg932.rs @@ -5,29 +5,29 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_tx_pattern` reader - u1_plda_pcie_tx_pattern"] pub type U1_PLDA_PCIE_TX_PATTERN_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_tx_pattern` writer - u1_plda_pcie_tx_pattern"] -pub type U1_PLDA_PCIE_TX_PATTERN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U1_PLDA_PCIE_TX_PATTERN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_plda_pcie_usb3_bus_width` reader - u1_plda_pcie_usb3_bus_width"] pub type U1_PLDA_PCIE_USB3_BUS_WIDTH_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_usb3_bus_width` writer - u1_plda_pcie_usb3_bus_width"] -pub type U1_PLDA_PCIE_USB3_BUS_WIDTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U1_PLDA_PCIE_USB3_BUS_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_plda_pcie_usb3_phy_enable` reader - u1_plda_pcie_usb3_phy_enable"] pub type U1_PLDA_PCIE_USB3_PHY_ENABLE_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_usb3_phy_enable` writer - u1_plda_pcie_usb3_phy_enable"] -pub type U1_PLDA_PCIE_USB3_PHY_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_USB3_PHY_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_usb3_rate` reader - u1_plda_pcie_usb3_rate"] pub type U1_PLDA_PCIE_USB3_RATE_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_usb3_rate` writer - u1_plda_pcie_usb3_rate"] -pub type U1_PLDA_PCIE_USB3_RATE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U1_PLDA_PCIE_USB3_RATE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_plda_pcie_usb3_rx_standby` reader - u1_plda_pcie_usb3_rx_standby"] pub type U1_PLDA_PCIE_USB3_RX_STANDBY_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_usb3_rx_standby` writer - u1_plda_pcie_usb3_rx_standby"] -pub type U1_PLDA_PCIE_USB3_RX_STANDBY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_USB3_RX_STANDBY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_xwdecerr` reader - u1_plda_pcie_xwdecerr"] pub type U1_PLDA_PCIE_XWDECERR_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_xwerrclr` reader - u1_plda_pcie_xwerrclr"] pub type U1_PLDA_PCIE_XWERRCLR_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_xwerrclr` writer - u1_plda_pcie_xwerrclr"] -pub type U1_PLDA_PCIE_XWERRCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_XWERRCLR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_xwslverr` reader - u1_plda_pcie_xwslverr"] pub type U1_PLDA_PCIE_XWSLVERR_R = crate::BitReader; impl R { @@ -78,50 +78,54 @@ impl W { #[must_use] pub fn u1_plda_pcie_tx_pattern( &mut self, - ) -> U1_PLDA_PCIE_TX_PATTERN_W { - U1_PLDA_PCIE_TX_PATTERN_W::new(self) + ) -> U1_PLDA_PCIE_TX_PATTERN_W { + U1_PLDA_PCIE_TX_PATTERN_W::new(self, 0) } #[doc = "Bits 2:3 - u1_plda_pcie_usb3_bus_width"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_usb3_bus_width( &mut self, - ) -> U1_PLDA_PCIE_USB3_BUS_WIDTH_W { - U1_PLDA_PCIE_USB3_BUS_WIDTH_W::new(self) + ) -> U1_PLDA_PCIE_USB3_BUS_WIDTH_W { + U1_PLDA_PCIE_USB3_BUS_WIDTH_W::new(self, 2) } #[doc = "Bit 4 - u1_plda_pcie_usb3_phy_enable"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_usb3_phy_enable( &mut self, - ) -> U1_PLDA_PCIE_USB3_PHY_ENABLE_W { - U1_PLDA_PCIE_USB3_PHY_ENABLE_W::new(self) + ) -> U1_PLDA_PCIE_USB3_PHY_ENABLE_W { + U1_PLDA_PCIE_USB3_PHY_ENABLE_W::new(self, 4) } #[doc = "Bits 5:6 - u1_plda_pcie_usb3_rate"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_usb3_rate( &mut self, - ) -> U1_PLDA_PCIE_USB3_RATE_W { - U1_PLDA_PCIE_USB3_RATE_W::new(self) + ) -> U1_PLDA_PCIE_USB3_RATE_W { + U1_PLDA_PCIE_USB3_RATE_W::new(self, 5) } #[doc = "Bit 7 - u1_plda_pcie_usb3_rx_standby"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_usb3_rx_standby( &mut self, - ) -> U1_PLDA_PCIE_USB3_RX_STANDBY_W { - U1_PLDA_PCIE_USB3_RX_STANDBY_W::new(self) + ) -> U1_PLDA_PCIE_USB3_RX_STANDBY_W { + U1_PLDA_PCIE_USB3_RX_STANDBY_W::new(self, 7) } #[doc = "Bit 9 - u1_plda_pcie_xwerrclr"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_xwerrclr( &mut self, - ) -> U1_PLDA_PCIE_XWERRCLR_W { - U1_PLDA_PCIE_XWERRCLR_W::new(self) + ) -> U1_PLDA_PCIE_XWERRCLR_W { + U1_PLDA_PCIE_XWERRCLR_W::new(self, 9) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg96.rs b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg96.rs index 705affa..aec28ef 100644 --- a/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg96.rs +++ b/jh7110-vf2-12a-pac/src/stg_syscon/stg_sysconsaif_syscfg96.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg.rs b/jh7110-vf2-12a-pac/src/stgcrg.rs index f689ce7..52b9cf6 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg.rs @@ -1,228 +1,354 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + clk_hifi4_core: CLK_HIFI4_CORE, + clk_usb_apb: CLK_USB_APB, + clk_usb_utmi_apb: CLK_USB_UTMI_APB, + clk_usb_axi: CLK_USB_AXI, + clk_usb_ipm: CLK_USB_IPM, + clk_usb_stb: CLK_USB_STB, + clk_usb_app125: CLK_USB_APP125, + clk_usb_refclk: CLK_USB_REFCLK, + clk_u0_pcie_axi_mst0: CLK_U0_PCIE_AXI_MST0, + clk_u0_pcie_apb: CLK_U0_PCIE_APB, + clk_u0_pcie_tl: CLK_U0_PCIE_TL, + clk_u1_pcie_axi_mst0: CLK_U1_PCIE_AXI_MST0, + clk_u1_pcie_apb: CLK_U1_PCIE_APB, + clk_u1_pcie_tl: CLK_U1_PCIE_TL, + clk_pcie01_slv_dec_main: CLK_PCIE01_SLV_DEC_MAIN, + clk_sec_hclk: CLK_SEC_HCLK, + clk_sec_misc_ahb: CLK_SEC_MISC_AHB, + clk_stg_mtrx_group0_main: CLK_STG_MTRX_GROUP0_MAIN, + clk_stg_mtrx_group0_bus: CLK_STG_MTRX_GROUP0_BUS, + clk_stg_mtrx_group0_stg: CLK_STG_MTRX_GROUP0_STG, + clk_stg_mtrx_group1_main: CLK_STG_MTRX_GROUP1_MAIN, + clk_stg_mtrx_group1_bus: CLK_STG_MTRX_GROUP1_BUS, + clk_stg_mtrx_group1_stg: CLK_STG_MTRX_GROUP1_STG, + clk_stg_mtrx_group1_hifi: CLK_STG_MTRX_GROUP1_HIFI, + clk_e2_rtc: CLK_E2_RTC, + clk_e2_core: CLK_E2_CORE, + clk_e2_dbg: CLK_E2_DBG, + clk_dma_axi: CLK_DMA_AXI, + clk_dma_ahb: CLK_DMA_AHB, + soft_rst_addr_sel: SOFT_RST_ADDR_SEL, + stgcrg_rst_stat: STGCRG_RST_STAT, +} +impl RegisterBlock { #[doc = "0x00 - Clock HIFI4 Core"] - pub clk_hifi4_core: CLK_HIFI4_CORE, + #[inline(always)] + pub const fn clk_hifi4_core(&self) -> &CLK_HIFI4_CORE { + &self.clk_hifi4_core + } #[doc = "0x04 - Clock USB APB"] - pub clk_usb_apb: CLK_USB_APB, + #[inline(always)] + pub const fn clk_usb_apb(&self) -> &CLK_USB_APB { + &self.clk_usb_apb + } #[doc = "0x08 - Clock USB UTMI APB"] - pub clk_usb_utmi_apb: CLK_USB_UTMI_APB, + #[inline(always)] + pub const fn clk_usb_utmi_apb(&self) -> &CLK_USB_UTMI_APB { + &self.clk_usb_utmi_apb + } #[doc = "0x0c - Clock USB AXI"] - pub clk_usb_axi: CLK_USB_AXI, + #[inline(always)] + pub const fn clk_usb_axi(&self) -> &CLK_USB_AXI { + &self.clk_usb_axi + } #[doc = "0x10 - Clock USB AXI"] - pub clk_usb_ipm: CLK_USB_IPM, + #[inline(always)] + pub const fn clk_usb_ipm(&self) -> &CLK_USB_IPM { + &self.clk_usb_ipm + } #[doc = "0x14 - Clock USB STB"] - pub clk_usb_stb: CLK_USB_STB, + #[inline(always)] + pub const fn clk_usb_stb(&self) -> &CLK_USB_STB { + &self.clk_usb_stb + } #[doc = "0x18 - Clock USB APP 125"] - pub clk_usb_app125: CLK_USB_APP125, + #[inline(always)] + pub const fn clk_usb_app125(&self) -> &CLK_USB_APP125 { + &self.clk_usb_app125 + } #[doc = "0x1c - Clock USB Reference Clock"] - pub clk_usb_refclk: CLK_USB_REFCLK, + #[inline(always)] + pub const fn clk_usb_refclk(&self) -> &CLK_USB_REFCLK { + &self.clk_usb_refclk + } #[doc = "0x20 - U0 Clock PCIe AXI MST 0"] - pub clk_u0_pcie_axi_mst0: CLK_U0_PCIE_AXI_MST0, + #[inline(always)] + pub const fn clk_u0_pcie_axi_mst0(&self) -> &CLK_U0_PCIE_AXI_MST0 { + &self.clk_u0_pcie_axi_mst0 + } #[doc = "0x24 - U0 Clock PCIe APB"] - pub clk_u0_pcie_apb: CLK_U0_PCIE_APB, + #[inline(always)] + pub const fn clk_u0_pcie_apb(&self) -> &CLK_U0_PCIE_APB { + &self.clk_u0_pcie_apb + } #[doc = "0x28 - U0 Clock PCIe TL"] - pub clk_u0_pcie_tl: CLK_U0_PCIE_TL, + #[inline(always)] + pub const fn clk_u0_pcie_tl(&self) -> &CLK_U0_PCIE_TL { + &self.clk_u0_pcie_tl + } #[doc = "0x2c - U1 Clock PCIe AXI MST 0"] - pub clk_u1_pcie_axi_mst0: CLK_U1_PCIE_AXI_MST0, + #[inline(always)] + pub const fn clk_u1_pcie_axi_mst0(&self) -> &CLK_U1_PCIE_AXI_MST0 { + &self.clk_u1_pcie_axi_mst0 + } #[doc = "0x30 - U1 Clock PCIe APB"] - pub clk_u1_pcie_apb: CLK_U1_PCIE_APB, + #[inline(always)] + pub const fn clk_u1_pcie_apb(&self) -> &CLK_U1_PCIE_APB { + &self.clk_u1_pcie_apb + } #[doc = "0x34 - U1 Clock PCIe TL"] - pub clk_u1_pcie_tl: CLK_U1_PCIE_TL, + #[inline(always)] + pub const fn clk_u1_pcie_tl(&self) -> &CLK_U1_PCIE_TL { + &self.clk_u1_pcie_tl + } #[doc = "0x38 - Clock PCIe 01 SLV DEC Main"] - pub clk_pcie01_slv_dec_main: CLK_PCIE01_SLV_DEC_MAIN, + #[inline(always)] + pub const fn clk_pcie01_slv_dec_main(&self) -> &CLK_PCIE01_SLV_DEC_MAIN { + &self.clk_pcie01_slv_dec_main + } #[doc = "0x3c - Clock Security HCLK"] - pub clk_sec_hclk: CLK_SEC_HCLK, + #[inline(always)] + pub const fn clk_sec_hclk(&self) -> &CLK_SEC_HCLK { + &self.clk_sec_hclk + } #[doc = "0x40 - Clock Security Miscellaneous AHB"] - pub clk_sec_misc_ahb: CLK_SEC_MISC_AHB, + #[inline(always)] + pub const fn clk_sec_misc_ahb(&self) -> &CLK_SEC_MISC_AHB { + &self.clk_sec_misc_ahb + } #[doc = "0x44 - Clock STG MTRX Group 0 Main"] - pub clk_stg_mtrx_group0_main: CLK_STG_MTRX_GROUP0_MAIN, + #[inline(always)] + pub const fn clk_stg_mtrx_group0_main(&self) -> &CLK_STG_MTRX_GROUP0_MAIN { + &self.clk_stg_mtrx_group0_main + } #[doc = "0x48 - Clock STG MTRX Group 0 Bus"] - pub clk_stg_mtrx_group0_bus: CLK_STG_MTRX_GROUP0_BUS, + #[inline(always)] + pub const fn clk_stg_mtrx_group0_bus(&self) -> &CLK_STG_MTRX_GROUP0_BUS { + &self.clk_stg_mtrx_group0_bus + } #[doc = "0x4c - Clock STG MTRX Group 0 STG"] - pub clk_stg_mtrx_group0_stg: CLK_STG_MTRX_GROUP0_STG, + #[inline(always)] + pub const fn clk_stg_mtrx_group0_stg(&self) -> &CLK_STG_MTRX_GROUP0_STG { + &self.clk_stg_mtrx_group0_stg + } #[doc = "0x50 - Clock STG MTRX Group 1 Main"] - pub clk_stg_mtrx_group1_main: CLK_STG_MTRX_GROUP1_MAIN, + #[inline(always)] + pub const fn clk_stg_mtrx_group1_main(&self) -> &CLK_STG_MTRX_GROUP1_MAIN { + &self.clk_stg_mtrx_group1_main + } #[doc = "0x54 - Clock STG MTRX Group 1 Bus"] - pub clk_stg_mtrx_group1_bus: CLK_STG_MTRX_GROUP1_BUS, + #[inline(always)] + pub const fn clk_stg_mtrx_group1_bus(&self) -> &CLK_STG_MTRX_GROUP1_BUS { + &self.clk_stg_mtrx_group1_bus + } #[doc = "0x58 - Clock STG MTRX Group 1 STG"] - pub clk_stg_mtrx_group1_stg: CLK_STG_MTRX_GROUP1_STG, + #[inline(always)] + pub const fn clk_stg_mtrx_group1_stg(&self) -> &CLK_STG_MTRX_GROUP1_STG { + &self.clk_stg_mtrx_group1_stg + } #[doc = "0x5c - Clock STG MTRX Group 1 HIFI"] - pub clk_stg_mtrx_group1_hifi: CLK_STG_MTRX_GROUP1_HIFI, + #[inline(always)] + pub const fn clk_stg_mtrx_group1_hifi(&self) -> &CLK_STG_MTRX_GROUP1_HIFI { + &self.clk_stg_mtrx_group1_hifi + } #[doc = "0x60 - Clock E2 RTC"] - pub clk_e2_rtc: CLK_E2_RTC, + #[inline(always)] + pub const fn clk_e2_rtc(&self) -> &CLK_E2_RTC { + &self.clk_e2_rtc + } #[doc = "0x64 - Clock E2 Core"] - pub clk_e2_core: CLK_E2_CORE, + #[inline(always)] + pub const fn clk_e2_core(&self) -> &CLK_E2_CORE { + &self.clk_e2_core + } #[doc = "0x68 - Clock E2 DBG"] - pub clk_e2_dbg: CLK_E2_DBG, + #[inline(always)] + pub const fn clk_e2_dbg(&self) -> &CLK_E2_DBG { + &self.clk_e2_dbg + } #[doc = "0x6c - Clock DMA AXI"] - pub clk_dma_axi: CLK_DMA_AXI, + #[inline(always)] + pub const fn clk_dma_axi(&self) -> &CLK_DMA_AXI { + &self.clk_dma_axi + } #[doc = "0x70 - Clock DMA AHB"] - pub clk_dma_ahb: CLK_DMA_AHB, + #[inline(always)] + pub const fn clk_dma_ahb(&self) -> &CLK_DMA_AHB { + &self.clk_dma_ahb + } #[doc = "0x74 - Software RESET Address Selector"] - pub soft_rst_addr_sel: SOFT_RST_ADDR_SEL, + #[inline(always)] + pub const fn soft_rst_addr_sel(&self) -> &SOFT_RST_ADDR_SEL { + &self.soft_rst_addr_sel + } #[doc = "0x78 - STGCRG RESET Status"] - pub stgcrg_rst_stat: STGCRG_RST_STAT, + #[inline(always)] + pub const fn stgcrg_rst_stat(&self) -> &STGCRG_RST_STAT { + &self.stgcrg_rst_stat + } } -#[doc = "clk_hifi4_core (rw) register accessor: Clock HIFI4 Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_hifi4_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_hifi4_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_hifi4_core`] +#[doc = "clk_hifi4_core (rw) register accessor: Clock HIFI4 Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_hifi4_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_hifi4_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_hifi4_core`] module"] pub type CLK_HIFI4_CORE = crate::Reg; #[doc = "Clock HIFI4 Core"] pub mod clk_hifi4_core; -#[doc = "clk_usb_apb (rw) register accessor: Clock USB APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_usb_apb`] +#[doc = "clk_usb_apb (rw) register accessor: Clock USB APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_usb_apb`] module"] pub type CLK_USB_APB = crate::Reg; #[doc = "Clock USB APB"] pub mod clk_usb_apb; -#[doc = "clk_usb_utmi_apb (rw) register accessor: Clock USB UTMI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_utmi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_utmi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_usb_utmi_apb`] +#[doc = "clk_usb_utmi_apb (rw) register accessor: Clock USB UTMI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_utmi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_utmi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_usb_utmi_apb`] module"] pub type CLK_USB_UTMI_APB = crate::Reg; #[doc = "Clock USB UTMI APB"] pub mod clk_usb_utmi_apb; -#[doc = "clk_usb_axi (rw) register accessor: Clock USB AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_usb_axi`] +#[doc = "clk_usb_axi (rw) register accessor: Clock USB AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_usb_axi`] module"] pub type CLK_USB_AXI = crate::Reg; #[doc = "Clock USB AXI"] pub mod clk_usb_axi; -#[doc = "clk_usb_ipm (rw) register accessor: Clock USB AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_ipm::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_ipm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_usb_ipm`] +#[doc = "clk_usb_ipm (rw) register accessor: Clock USB AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_ipm::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_ipm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_usb_ipm`] module"] pub type CLK_USB_IPM = crate::Reg; #[doc = "Clock USB AXI"] pub mod clk_usb_ipm; -#[doc = "clk_usb_stb (rw) register accessor: Clock USB STB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_stb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_stb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_usb_stb`] +#[doc = "clk_usb_stb (rw) register accessor: Clock USB STB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_stb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_stb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_usb_stb`] module"] pub type CLK_USB_STB = crate::Reg; #[doc = "Clock USB STB"] pub mod clk_usb_stb; -#[doc = "clk_usb_app125 (rw) register accessor: Clock USB APP 125\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_app125::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_app125::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_usb_app125`] +#[doc = "clk_usb_app125 (rw) register accessor: Clock USB APP 125\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_app125::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_app125::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_usb_app125`] module"] pub type CLK_USB_APP125 = crate::Reg; #[doc = "Clock USB APP 125"] pub mod clk_usb_app125; -#[doc = "clk_usb_refclk (rw) register accessor: Clock USB Reference Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_refclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_refclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_usb_refclk`] +#[doc = "clk_usb_refclk (rw) register accessor: Clock USB Reference Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_refclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_refclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_usb_refclk`] module"] pub type CLK_USB_REFCLK = crate::Reg; #[doc = "Clock USB Reference Clock"] pub mod clk_usb_refclk; -#[doc = "clk_u0_pcie_axi_mst0 (rw) register accessor: U0 Clock PCIe AXI MST 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_pcie_axi_mst0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_pcie_axi_mst0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_pcie_axi_mst0`] +#[doc = "clk_u0_pcie_axi_mst0 (rw) register accessor: U0 Clock PCIe AXI MST 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_pcie_axi_mst0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_pcie_axi_mst0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_pcie_axi_mst0`] module"] pub type CLK_U0_PCIE_AXI_MST0 = crate::Reg; #[doc = "U0 Clock PCIe AXI MST 0"] pub mod clk_u0_pcie_axi_mst0; -#[doc = "clk_u0_pcie_apb (rw) register accessor: U0 Clock PCIe APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_pcie_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_pcie_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_pcie_apb`] +#[doc = "clk_u0_pcie_apb (rw) register accessor: U0 Clock PCIe APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_pcie_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_pcie_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_pcie_apb`] module"] pub type CLK_U0_PCIE_APB = crate::Reg; #[doc = "U0 Clock PCIe APB"] pub mod clk_u0_pcie_apb; -#[doc = "clk_u0_pcie_tl (rw) register accessor: U0 Clock PCIe TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_pcie_tl::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_pcie_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_pcie_tl`] +#[doc = "clk_u0_pcie_tl (rw) register accessor: U0 Clock PCIe TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_pcie_tl::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_pcie_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_pcie_tl`] module"] pub type CLK_U0_PCIE_TL = crate::Reg; #[doc = "U0 Clock PCIe TL"] pub mod clk_u0_pcie_tl; -#[doc = "clk_u1_pcie_axi_mst0 (rw) register accessor: U1 Clock PCIe AXI MST 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_pcie_axi_mst0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_pcie_axi_mst0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_pcie_axi_mst0`] +#[doc = "clk_u1_pcie_axi_mst0 (rw) register accessor: U1 Clock PCIe AXI MST 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_pcie_axi_mst0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_pcie_axi_mst0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_pcie_axi_mst0`] module"] pub type CLK_U1_PCIE_AXI_MST0 = crate::Reg; #[doc = "U1 Clock PCIe AXI MST 0"] pub mod clk_u1_pcie_axi_mst0; -#[doc = "clk_u1_pcie_apb (rw) register accessor: U1 Clock PCIe APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_pcie_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_pcie_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_pcie_apb`] +#[doc = "clk_u1_pcie_apb (rw) register accessor: U1 Clock PCIe APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_pcie_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_pcie_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_pcie_apb`] module"] pub type CLK_U1_PCIE_APB = crate::Reg; #[doc = "U1 Clock PCIe APB"] pub mod clk_u1_pcie_apb; -#[doc = "clk_u1_pcie_tl (rw) register accessor: U1 Clock PCIe TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_pcie_tl::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_pcie_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_pcie_tl`] +#[doc = "clk_u1_pcie_tl (rw) register accessor: U1 Clock PCIe TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_pcie_tl::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_pcie_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_pcie_tl`] module"] pub type CLK_U1_PCIE_TL = crate::Reg; #[doc = "U1 Clock PCIe TL"] pub mod clk_u1_pcie_tl; -#[doc = "clk_pcie01_slv_dec_main (rw) register accessor: Clock PCIe 01 SLV DEC Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pcie01_slv_dec_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pcie01_slv_dec_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pcie01_slv_dec_main`] +#[doc = "clk_pcie01_slv_dec_main (rw) register accessor: Clock PCIe 01 SLV DEC Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pcie01_slv_dec_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pcie01_slv_dec_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pcie01_slv_dec_main`] module"] pub type CLK_PCIE01_SLV_DEC_MAIN = crate::Reg; #[doc = "Clock PCIe 01 SLV DEC Main"] pub mod clk_pcie01_slv_dec_main; -#[doc = "clk_sec_hclk (rw) register accessor: Clock Security HCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_sec_hclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sec_hclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_sec_hclk`] +#[doc = "clk_sec_hclk (rw) register accessor: Clock Security HCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_sec_hclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sec_hclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_sec_hclk`] module"] pub type CLK_SEC_HCLK = crate::Reg; #[doc = "Clock Security HCLK"] pub mod clk_sec_hclk; -#[doc = "clk_sec_misc_ahb (rw) register accessor: Clock Security Miscellaneous AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_sec_misc_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sec_misc_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_sec_misc_ahb`] +#[doc = "clk_sec_misc_ahb (rw) register accessor: Clock Security Miscellaneous AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_sec_misc_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sec_misc_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_sec_misc_ahb`] module"] pub type CLK_SEC_MISC_AHB = crate::Reg; #[doc = "Clock Security Miscellaneous AHB"] pub mod clk_sec_misc_ahb; -#[doc = "clk_stg_mtrx_group0_main (rw) register accessor: Clock STG MTRX Group 0 Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group0_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group0_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_stg_mtrx_group0_main`] +#[doc = "clk_stg_mtrx_group0_main (rw) register accessor: Clock STG MTRX Group 0 Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group0_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group0_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_stg_mtrx_group0_main`] module"] pub type CLK_STG_MTRX_GROUP0_MAIN = crate::Reg; #[doc = "Clock STG MTRX Group 0 Main"] pub mod clk_stg_mtrx_group0_main; -#[doc = "clk_stg_mtrx_group0_bus (rw) register accessor: Clock STG MTRX Group 0 Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group0_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group0_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_stg_mtrx_group0_bus`] +#[doc = "clk_stg_mtrx_group0_bus (rw) register accessor: Clock STG MTRX Group 0 Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group0_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group0_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_stg_mtrx_group0_bus`] module"] pub type CLK_STG_MTRX_GROUP0_BUS = crate::Reg; #[doc = "Clock STG MTRX Group 0 Bus"] pub mod clk_stg_mtrx_group0_bus; -#[doc = "clk_stg_mtrx_group0_stg (rw) register accessor: Clock STG MTRX Group 0 STG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group0_stg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group0_stg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_stg_mtrx_group0_stg`] +#[doc = "clk_stg_mtrx_group0_stg (rw) register accessor: Clock STG MTRX Group 0 STG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group0_stg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group0_stg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_stg_mtrx_group0_stg`] module"] pub type CLK_STG_MTRX_GROUP0_STG = crate::Reg; #[doc = "Clock STG MTRX Group 0 STG"] pub mod clk_stg_mtrx_group0_stg; -#[doc = "clk_stg_mtrx_group1_main (rw) register accessor: Clock STG MTRX Group 1 Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group1_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group1_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_stg_mtrx_group1_main`] +#[doc = "clk_stg_mtrx_group1_main (rw) register accessor: Clock STG MTRX Group 1 Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group1_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group1_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_stg_mtrx_group1_main`] module"] pub type CLK_STG_MTRX_GROUP1_MAIN = crate::Reg; #[doc = "Clock STG MTRX Group 1 Main"] pub mod clk_stg_mtrx_group1_main; -#[doc = "clk_stg_mtrx_group1_bus (rw) register accessor: Clock STG MTRX Group 1 Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group1_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group1_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_stg_mtrx_group1_bus`] +#[doc = "clk_stg_mtrx_group1_bus (rw) register accessor: Clock STG MTRX Group 1 Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group1_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group1_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_stg_mtrx_group1_bus`] module"] pub type CLK_STG_MTRX_GROUP1_BUS = crate::Reg; #[doc = "Clock STG MTRX Group 1 Bus"] pub mod clk_stg_mtrx_group1_bus; -#[doc = "clk_stg_mtrx_group1_stg (rw) register accessor: Clock STG MTRX Group 1 STG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group1_stg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group1_stg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_stg_mtrx_group1_stg`] +#[doc = "clk_stg_mtrx_group1_stg (rw) register accessor: Clock STG MTRX Group 1 STG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group1_stg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group1_stg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_stg_mtrx_group1_stg`] module"] pub type CLK_STG_MTRX_GROUP1_STG = crate::Reg; #[doc = "Clock STG MTRX Group 1 STG"] pub mod clk_stg_mtrx_group1_stg; -#[doc = "clk_stg_mtrx_group1_hifi (rw) register accessor: Clock STG MTRX Group 1 HIFI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group1_hifi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group1_hifi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_stg_mtrx_group1_hifi`] +#[doc = "clk_stg_mtrx_group1_hifi (rw) register accessor: Clock STG MTRX Group 1 HIFI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group1_hifi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group1_hifi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_stg_mtrx_group1_hifi`] module"] pub type CLK_STG_MTRX_GROUP1_HIFI = crate::Reg; #[doc = "Clock STG MTRX Group 1 HIFI"] pub mod clk_stg_mtrx_group1_hifi; -#[doc = "clk_e2_rtc (rw) register accessor: Clock E2 RTC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_e2_rtc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_e2_rtc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_e2_rtc`] +#[doc = "clk_e2_rtc (rw) register accessor: Clock E2 RTC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_e2_rtc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_e2_rtc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_e2_rtc`] module"] pub type CLK_E2_RTC = crate::Reg; #[doc = "Clock E2 RTC"] pub mod clk_e2_rtc; -#[doc = "clk_e2_core (rw) register accessor: Clock E2 Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_e2_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_e2_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_e2_core`] +#[doc = "clk_e2_core (rw) register accessor: Clock E2 Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_e2_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_e2_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_e2_core`] module"] pub type CLK_E2_CORE = crate::Reg; #[doc = "Clock E2 Core"] pub mod clk_e2_core; -#[doc = "clk_e2_dbg (rw) register accessor: Clock E2 DBG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_e2_dbg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_e2_dbg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_e2_dbg`] +#[doc = "clk_e2_dbg (rw) register accessor: Clock E2 DBG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_e2_dbg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_e2_dbg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_e2_dbg`] module"] pub type CLK_E2_DBG = crate::Reg; #[doc = "Clock E2 DBG"] pub mod clk_e2_dbg; -#[doc = "clk_dma_axi (rw) register accessor: Clock DMA AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_dma_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_dma_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_dma_axi`] +#[doc = "clk_dma_axi (rw) register accessor: Clock DMA AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_dma_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_dma_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_dma_axi`] module"] pub type CLK_DMA_AXI = crate::Reg; #[doc = "Clock DMA AXI"] pub mod clk_dma_axi; -#[doc = "clk_dma_ahb (rw) register accessor: Clock DMA AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_dma_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_dma_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_dma_ahb`] +#[doc = "clk_dma_ahb (rw) register accessor: Clock DMA AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_dma_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_dma_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_dma_ahb`] module"] pub type CLK_DMA_AHB = crate::Reg; #[doc = "Clock DMA AHB"] pub mod clk_dma_ahb; -#[doc = "soft_rst_addr_sel (rw) register accessor: Software RESET Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_rst_addr_sel`] +#[doc = "soft_rst_addr_sel (rw) register accessor: Software RESET Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_rst_addr_sel`] module"] pub type SOFT_RST_ADDR_SEL = crate::Reg; #[doc = "Software RESET Address Selector"] pub mod soft_rst_addr_sel; -#[doc = "stgcrg_rst_stat (rw) register accessor: STGCRG RESET Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stgcrg_rst_stat::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stgcrg_rst_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stgcrg_rst_stat`] +#[doc = "stgcrg_rst_stat (rw) register accessor: STGCRG RESET Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stgcrg_rst_stat::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stgcrg_rst_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stgcrg_rst_stat`] module"] pub type STGCRG_RST_STAT = crate::Reg; #[doc = "STGCRG RESET Status"] diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_dma_ahb.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_dma_ahb.rs index 3b6fbfc..5fa8ca5 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_dma_ahb.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_dma_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_dma_axi.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_dma_axi.rs index 5894036..3f0cac3 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_dma_axi.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_dma_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_e2_core.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_e2_core.rs index 327bb44..8e7f48a 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_e2_core.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_e2_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_e2_dbg.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_e2_dbg.rs index c82c736..d776b89 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_e2_dbg.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_e2_dbg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_e2_rtc.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_e2_rtc.rs index f22780e..ac6cb39 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_e2_rtc.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_e2_rtc.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_hifi4_core.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_hifi4_core.rs index 714463f..ddcfd09 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_hifi4_core.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_hifi4_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_pcie01_slv_dec_main.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_pcie01_slv_dec_main.rs index 9546e89..f37f28b 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_pcie01_slv_dec_main.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_pcie01_slv_dec_main.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_sec_hclk.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_sec_hclk.rs index 2659357..f33ff15 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_sec_hclk.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_sec_hclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_sec_misc_ahb.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_sec_misc_ahb.rs index c178517..34c498a 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_sec_misc_ahb.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_sec_misc_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group0_bus.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group0_bus.rs index 8781f81..a13ef5a 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group0_bus.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group0_bus.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group0_main.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group0_main.rs index eabd069..174fc50 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group0_main.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group0_main.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group0_stg.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group0_stg.rs index cb6584b..9717b67 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group0_stg.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group0_stg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group1_bus.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group1_bus.rs index a330c2d..27b97b0 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group1_bus.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group1_bus.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group1_hifi.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group1_hifi.rs index b8c7a2c..0f70e97 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group1_hifi.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group1_hifi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group1_main.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group1_main.rs index 6ec8ada..9322888 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group1_main.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group1_main.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group1_stg.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group1_stg.rs index 0b22c38..1a14908 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group1_stg.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_stg_mtrx_group1_stg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_u0_pcie_apb.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_u0_pcie_apb.rs index dea7684..b10c31d 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_u0_pcie_apb.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_u0_pcie_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_u0_pcie_axi_mst0.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_u0_pcie_axi_mst0.rs index ca2abf5..4064560 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_u0_pcie_axi_mst0.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_u0_pcie_axi_mst0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_u0_pcie_tl.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_u0_pcie_tl.rs index 0ef62c0..51ef398 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_u0_pcie_tl.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_u0_pcie_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_u1_pcie_apb.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_u1_pcie_apb.rs index c860b6b..50cf831 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_u1_pcie_apb.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_u1_pcie_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_u1_pcie_axi_mst0.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_u1_pcie_axi_mst0.rs index 9408a60..b0b0f08 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_u1_pcie_axi_mst0.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_u1_pcie_axi_mst0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_u1_pcie_tl.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_u1_pcie_tl.rs index 43ded3a..c2eddb9 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_u1_pcie_tl.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_u1_pcie_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_apb.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_apb.rs index 7ce629a..0efd0a4 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_apb.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_app125.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_app125.rs index 3e3af58..c100e0f 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_app125.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_app125.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_axi.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_axi.rs index 2882c29..bdd6de4 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_axi.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_ipm.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_ipm.rs index 66c4fd1..5cae745 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_ipm.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_ipm.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_refclk.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_refclk.rs index b49c4fb..1ac3115 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_refclk.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_refclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_stb.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_stb.rs index ed474f9..4470877 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_stb.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_stb.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_utmi_apb.rs b/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_utmi_apb.rs index 45a42e3..e1ad342 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_utmi_apb.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/clk_usb_utmi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/soft_rst_addr_sel.rs b/jh7110-vf2-12a-pac/src/stgcrg/soft_rst_addr_sel.rs index 829170e..734359d 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/soft_rst_addr_sel.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/soft_rst_addr_sel.rs @@ -5,95 +5,95 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_stg_syscon_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_STG_SYSCON_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_stg_syscon_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_STG_SYSCON_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_STG_SYSCON_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_hifi4_rst_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_HIFI4_RST_CORE_R = crate::BitReader; #[doc = "Field `rst_u0_hifi4_rst_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_HIFI4_RST_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_HIFI4_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_hifi4_rst_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_HIFI4_RST_AXI_R = crate::BitReader; #[doc = "Field `rst_u0_hifi4_rst_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_HIFI4_RST_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_HIFI4_RST_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_sec_top_hreesetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SEC_TOP_HREESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_sec_top_hreesetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SEC_TOP_HREESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SEC_TOP_HREESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_e2_sft7110_rst_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_E2_SFT7110_RST_CORE_R = crate::BitReader; #[doc = "Field `rst_u0_e2_sft7110_rst_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_E2_SFT7110_RST_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_E2_SFT7110_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dma1p_8ch_56hs_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_dma1p_8ch_56hs_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dma1p_8ch_56hs_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_dma1p_8ch_56hs_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdn_usb_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDN_USB_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_cdn_usb_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDN_USB_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDN_USB_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdn_usb_rstn_usb_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDN_USB_RSTN_USB_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdn_usb_rstn_usb_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDN_USB_RSTN_USB_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDN_USB_RSTN_USB_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdn_usb_rstn_utmi_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDN_USB_RSTN_UTMI_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdn_usb_rstn_utmi_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDN_USB_RSTN_UTMI_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDN_USB_RSTN_UTMI_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdn_usb_rstn_pwrup` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDN_USB_RSTN_PWRUP_R = crate::BitReader; #[doc = "Field `rstn_u0_cdn_usb_rstn_pwrup` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDN_USB_RSTN_PWRUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDN_USB_RSTN_PWRUP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_mst0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_mst0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_slv0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_slv0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_slv` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_slv` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pci_rstn_brg` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCI_RSTN_BRG_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pci_rstn_brg` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCI_RSTN_BRG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCI_RSTN_BRG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_pcie` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_PCIE_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_pcie` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_PCIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_PCIE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_mst0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_mst0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_slv0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_slv0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_slv` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_slv` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_brg` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_BRG_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_brg` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_BRG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_BRG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_pcie` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_PCIE_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_pcie` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_PCIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_PCIE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -217,182 +217,186 @@ impl W { #[must_use] pub fn rstn_u0_stg_syscon_presetn( &mut self, - ) -> RSTN_U0_STG_SYSCON_PRESETN_W { - RSTN_U0_STG_SYSCON_PRESETN_W::new(self) + ) -> RSTN_U0_STG_SYSCON_PRESETN_W { + RSTN_U0_STG_SYSCON_PRESETN_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rst_u0_hifi4_rst_core(&mut self) -> RST_U0_HIFI4_RST_CORE_W { - RST_U0_HIFI4_RST_CORE_W::new(self) + pub fn rst_u0_hifi4_rst_core(&mut self) -> RST_U0_HIFI4_RST_CORE_W { + RST_U0_HIFI4_RST_CORE_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rst_u0_hifi4_rst_axi(&mut self) -> RST_U0_HIFI4_RST_AXI_W { - RST_U0_HIFI4_RST_AXI_W::new(self) + pub fn rst_u0_hifi4_rst_axi(&mut self) -> RST_U0_HIFI4_RST_AXI_W { + RST_U0_HIFI4_RST_AXI_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_sec_top_hreesetn( &mut self, - ) -> RSTN_U0_SEC_TOP_HREESETN_W { - RSTN_U0_SEC_TOP_HREESETN_W::new(self) + ) -> RSTN_U0_SEC_TOP_HREESETN_W { + RSTN_U0_SEC_TOP_HREESETN_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_e2_sft7110_rst_core( &mut self, - ) -> RST_U0_E2_SFT7110_RST_CORE_W { - RST_U0_E2_SFT7110_RST_CORE_W::new(self) + ) -> RST_U0_E2_SFT7110_RST_CORE_W { + RST_U0_E2_SFT7110_RST_CORE_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dma1p_8ch_56hs_rstn_axi( &mut self, - ) -> RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W { - RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W::new(self) + ) -> RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W { + RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dma1p_8ch_56hs_rstn_ahb( &mut self, - ) -> RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W { - RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W::new(self) + ) -> RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W { + RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdn_usb_rstn_axi( &mut self, - ) -> RSTN_U0_CDN_USB_RSTN_AXI_W { - RSTN_U0_CDN_USB_RSTN_AXI_W::new(self) + ) -> RSTN_U0_CDN_USB_RSTN_AXI_W { + RSTN_U0_CDN_USB_RSTN_AXI_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdn_usb_rstn_usb_apb( &mut self, - ) -> RSTN_U0_CDN_USB_RSTN_USB_APB_W { - RSTN_U0_CDN_USB_RSTN_USB_APB_W::new(self) + ) -> RSTN_U0_CDN_USB_RSTN_USB_APB_W { + RSTN_U0_CDN_USB_RSTN_USB_APB_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdn_usb_rstn_utmi_apb( &mut self, - ) -> RSTN_U0_CDN_USB_RSTN_UTMI_APB_W { - RSTN_U0_CDN_USB_RSTN_UTMI_APB_W::new(self) + ) -> RSTN_U0_CDN_USB_RSTN_UTMI_APB_W { + RSTN_U0_CDN_USB_RSTN_UTMI_APB_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdn_usb_rstn_pwrup( &mut self, - ) -> RSTN_U0_CDN_USB_RSTN_PWRUP_W { - RSTN_U0_CDN_USB_RSTN_PWRUP_W::new(self) + ) -> RSTN_U0_CDN_USB_RSTN_PWRUP_W { + RSTN_U0_CDN_USB_RSTN_PWRUP_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_axi_mst0( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W { - RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W { + RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_axi_slv0( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W { - RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W { + RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_axi_slv( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W { - RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W { + RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pci_rstn_brg( &mut self, - ) -> RSTN_U0_PLDA_PCI_RSTN_BRG_W { - RSTN_U0_PLDA_PCI_RSTN_BRG_W::new(self) + ) -> RSTN_U0_PLDA_PCI_RSTN_BRG_W { + RSTN_U0_PLDA_PCI_RSTN_BRG_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_pcie( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_PCIE_W { - RSTN_U0_PLDA_PCIE_RSTN_PCIE_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_PCIE_W { + RSTN_U0_PLDA_PCIE_RSTN_PCIE_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_apb( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_APB_W { - RSTN_U0_PLDA_PCIE_RSTN_APB_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_APB_W { + RSTN_U0_PLDA_PCIE_RSTN_APB_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_axi_mst0( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W { - RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W { + RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_axi_slv0( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W { - RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W { + RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_axi_slv( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W { - RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W { + RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_brg( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_BRG_W { - RSTN_U1_PLDA_PCIE_RSTN_BRG_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_BRG_W { + RSTN_U1_PLDA_PCIE_RSTN_BRG_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_pcie( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_PCIE_W { - RSTN_U1_PLDA_PCIE_RSTN_PCIE_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_PCIE_W { + RSTN_U1_PLDA_PCIE_RSTN_PCIE_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_apb( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_APB_W { - RSTN_U1_PLDA_PCIE_RSTN_APB_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> RSTN_U1_PLDA_PCIE_RSTN_APB_W { + RSTN_U1_PLDA_PCIE_RSTN_APB_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/stgcrg/stgcrg_rst_stat.rs b/jh7110-vf2-12a-pac/src/stgcrg/stgcrg_rst_stat.rs index 1ae80fa..6eff18f 100644 --- a/jh7110-vf2-12a-pac/src/stgcrg/stgcrg_rst_stat.rs +++ b/jh7110-vf2-12a-pac/src/stgcrg/stgcrg_rst_stat.rs @@ -5,95 +5,95 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_stg_syscon_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_STG_SYSCON_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_stg_syscon_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_STG_SYSCON_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_STG_SYSCON_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_hifi4_rst_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_HIFI4_RST_CORE_R = crate::BitReader; #[doc = "Field `rst_u0_hifi4_rst_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_HIFI4_RST_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_HIFI4_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_hifi4_rst_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_HIFI4_RST_AXI_R = crate::BitReader; #[doc = "Field `rst_u0_hifi4_rst_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_HIFI4_RST_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_HIFI4_RST_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_sec_top_hreesetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SEC_TOP_HREESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_sec_top_hreesetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SEC_TOP_HREESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SEC_TOP_HREESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_e2_sft7110_rst_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_E2_SFT7110_RST_CORE_R = crate::BitReader; #[doc = "Field `rst_u0_e2_sft7110_rst_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_E2_SFT7110_RST_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_E2_SFT7110_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dma1p_8ch_56hs_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_dma1p_8ch_56hs_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dma1p_8ch_56hs_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_dma1p_8ch_56hs_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdn_usb_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDN_USB_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_cdn_usb_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDN_USB_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDN_USB_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdn_usb_rstn_usb_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDN_USB_RSTN_USB_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdn_usb_rstn_usb_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDN_USB_RSTN_USB_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDN_USB_RSTN_USB_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdn_usb_rstn_utmi_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDN_USB_RSTN_UTMI_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdn_usb_rstn_utmi_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDN_USB_RSTN_UTMI_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDN_USB_RSTN_UTMI_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdn_usb_rstn_pwrup` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDN_USB_RSTN_PWRUP_R = crate::BitReader; #[doc = "Field `rstn_u0_cdn_usb_rstn_pwrup` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDN_USB_RSTN_PWRUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDN_USB_RSTN_PWRUP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_mst0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_mst0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_slv0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_slv0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_slv` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_slv` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pci_rstn_brg` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCI_RSTN_BRG_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pci_rstn_brg` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCI_RSTN_BRG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCI_RSTN_BRG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_pcie` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_PCIE_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_pcie` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_PCIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_PCIE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_mst0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_mst0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_slv0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_slv0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_slv` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_slv` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_brg` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_BRG_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_brg` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_BRG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_BRG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_pcie` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_PCIE_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_pcie` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_PCIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_PCIE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -217,182 +217,182 @@ impl W { #[must_use] pub fn rstn_u0_stg_syscon_presetn( &mut self, - ) -> RSTN_U0_STG_SYSCON_PRESETN_W { - RSTN_U0_STG_SYSCON_PRESETN_W::new(self) + ) -> RSTN_U0_STG_SYSCON_PRESETN_W { + RSTN_U0_STG_SYSCON_PRESETN_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rst_u0_hifi4_rst_core(&mut self) -> RST_U0_HIFI4_RST_CORE_W { - RST_U0_HIFI4_RST_CORE_W::new(self) + pub fn rst_u0_hifi4_rst_core(&mut self) -> RST_U0_HIFI4_RST_CORE_W { + RST_U0_HIFI4_RST_CORE_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rst_u0_hifi4_rst_axi(&mut self) -> RST_U0_HIFI4_RST_AXI_W { - RST_U0_HIFI4_RST_AXI_W::new(self) + pub fn rst_u0_hifi4_rst_axi(&mut self) -> RST_U0_HIFI4_RST_AXI_W { + RST_U0_HIFI4_RST_AXI_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_sec_top_hreesetn( - &mut self, - ) -> RSTN_U0_SEC_TOP_HREESETN_W { - RSTN_U0_SEC_TOP_HREESETN_W::new(self) + pub fn rstn_u0_sec_top_hreesetn(&mut self) -> RSTN_U0_SEC_TOP_HREESETN_W { + RSTN_U0_SEC_TOP_HREESETN_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_e2_sft7110_rst_core( &mut self, - ) -> RST_U0_E2_SFT7110_RST_CORE_W { - RST_U0_E2_SFT7110_RST_CORE_W::new(self) + ) -> RST_U0_E2_SFT7110_RST_CORE_W { + RST_U0_E2_SFT7110_RST_CORE_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dma1p_8ch_56hs_rstn_axi( &mut self, - ) -> RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W { - RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W::new(self) + ) -> RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W { + RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dma1p_8ch_56hs_rstn_ahb( &mut self, - ) -> RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W { - RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W::new(self) + ) -> RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W { + RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_cdn_usb_rstn_axi( - &mut self, - ) -> RSTN_U0_CDN_USB_RSTN_AXI_W { - RSTN_U0_CDN_USB_RSTN_AXI_W::new(self) + pub fn rstn_u0_cdn_usb_rstn_axi(&mut self) -> RSTN_U0_CDN_USB_RSTN_AXI_W { + RSTN_U0_CDN_USB_RSTN_AXI_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdn_usb_rstn_usb_apb( &mut self, - ) -> RSTN_U0_CDN_USB_RSTN_USB_APB_W { - RSTN_U0_CDN_USB_RSTN_USB_APB_W::new(self) + ) -> RSTN_U0_CDN_USB_RSTN_USB_APB_W { + RSTN_U0_CDN_USB_RSTN_USB_APB_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdn_usb_rstn_utmi_apb( &mut self, - ) -> RSTN_U0_CDN_USB_RSTN_UTMI_APB_W { - RSTN_U0_CDN_USB_RSTN_UTMI_APB_W::new(self) + ) -> RSTN_U0_CDN_USB_RSTN_UTMI_APB_W { + RSTN_U0_CDN_USB_RSTN_UTMI_APB_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdn_usb_rstn_pwrup( &mut self, - ) -> RSTN_U0_CDN_USB_RSTN_PWRUP_W { - RSTN_U0_CDN_USB_RSTN_PWRUP_W::new(self) + ) -> RSTN_U0_CDN_USB_RSTN_PWRUP_W { + RSTN_U0_CDN_USB_RSTN_PWRUP_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_axi_mst0( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W { - RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W { + RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_axi_slv0( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W { - RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W { + RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_axi_slv( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W { - RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W { + RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pci_rstn_brg( &mut self, - ) -> RSTN_U0_PLDA_PCI_RSTN_BRG_W { - RSTN_U0_PLDA_PCI_RSTN_BRG_W::new(self) + ) -> RSTN_U0_PLDA_PCI_RSTN_BRG_W { + RSTN_U0_PLDA_PCI_RSTN_BRG_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_pcie( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_PCIE_W { - RSTN_U0_PLDA_PCIE_RSTN_PCIE_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_PCIE_W { + RSTN_U0_PLDA_PCIE_RSTN_PCIE_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_apb( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_APB_W { - RSTN_U0_PLDA_PCIE_RSTN_APB_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_APB_W { + RSTN_U0_PLDA_PCIE_RSTN_APB_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_axi_mst0( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W { - RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W { + RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_axi_slv0( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W { - RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W { + RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_axi_slv( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W { - RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W { + RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_brg( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_BRG_W { - RSTN_U1_PLDA_PCIE_RSTN_BRG_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_BRG_W { + RSTN_U1_PLDA_PCIE_RSTN_BRG_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_pcie( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_PCIE_W { - RSTN_U1_PLDA_PCIE_RSTN_PCIE_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_PCIE_W { + RSTN_U1_PLDA_PCIE_RSTN_PCIE_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_apb( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_APB_W { - RSTN_U1_PLDA_PCIE_RSTN_APB_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> RSTN_U1_PLDA_PCIE_RSTN_APB_W { + RSTN_U1_PLDA_PCIE_RSTN_APB_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl.rs index 8dfa43c..d38021b 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl.rs @@ -1,1422 +1,1890 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SYS IOMUX CFG SAIF SYSCFG FMUX 0 DOEN"] - pub gpo_doen0: GPO_DOEN0, - #[doc = "0x04 - SYS IOMUX CFG SAIF SYSCFG FMUX 1 DOEN"] - pub gpo_doen1: GPO_DOEN1, - #[doc = "0x08 - SYS IOMUX CFG SAIF SYSCFG FMUX 2 DOEN"] - pub gpo_doen2: GPO_DOEN2, - #[doc = "0x0c - SYS IOMUX CFG SAIF SYSCFG FMUX 3 DOEN"] - pub gpo_doen3: GPO_DOEN3, - #[doc = "0x10 - SYS IOMUX CFG SAIF SYSCFG FMUX 4 DOEN"] - pub gpo_doen4: GPO_DOEN4, - #[doc = "0x14 - SYS IOMUX CFG SAIF SYSCFG FMUX 5 DOEN"] - pub gpo_doen5: GPO_DOEN5, - #[doc = "0x18 - SYS IOMUX CFG SAIF SYSCFG FMUX 6 DOEN"] - pub gpo_doen6: GPO_DOEN6, - #[doc = "0x1c - SYS IOMUX CFG SAIF SYSCFG FMUX 7 DOEN"] - pub gpo_doen7: GPO_DOEN7, - #[doc = "0x20 - SYS IOMUX CFG SAIF SYSCFG FMUX 8 DOEN"] - pub gpo_doen8: GPO_DOEN8, - #[doc = "0x24 - SYS IOMUX CFG SAIF SYSCFG FMUX 9 DOEN"] - pub gpo_doen9: GPO_DOEN9, - #[doc = "0x28 - SYS IOMUX CFG SAIF SYSCFG FMUX 10 DOEN"] - pub gpo_doen10: GPO_DOEN10, - #[doc = "0x2c - SYS IOMUX CFG SAIF SYSCFG FMUX 11 DOEN"] - pub gpo_doen11: GPO_DOEN11, - #[doc = "0x30 - SYS IOMUX CFG SAIF SYSCFG FMUX 12 DOEN"] - pub gpo_doen12: GPO_DOEN12, - #[doc = "0x34 - SYS IOMUX CFG SAIF SYSCFG FMUX 13 DOEN"] - pub gpo_doen13: GPO_DOEN13, + gpo_doen0: GPO_DOEN0, + gpo_doen1: GPO_DOEN1, + gpo_doen2: GPO_DOEN2, + gpo_doen3: GPO_DOEN3, + gpo_doen4: GPO_DOEN4, + gpo_doen5: GPO_DOEN5, + gpo_doen6: GPO_DOEN6, + gpo_doen7: GPO_DOEN7, + gpo_doen8: GPO_DOEN8, + gpo_doen9: GPO_DOEN9, + gpo_doen10: GPO_DOEN10, + gpo_doen11: GPO_DOEN11, + gpo_doen12: GPO_DOEN12, + gpo_doen13: GPO_DOEN13, _reserved_14_gpi0: [u8; 0x4c], - #[doc = "0x84 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 4 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi4: GPI4, - #[doc = "0x88 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 8 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi8: GPI8, - #[doc = "0x8c - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 12 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi12: GPI12, - #[doc = "0x90 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 16 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi16: GPI16, - #[doc = "0x94 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 20 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi20: GPI20, - #[doc = "0x98 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 24 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi24: GPI24, - #[doc = "0x9c - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 28 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi28: GPI28, - #[doc = "0xa0 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 32 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi32: GPI32, - #[doc = "0xa4 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 36 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi36: GPI36, - #[doc = "0xa8 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 40 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi40: GPI40, - #[doc = "0xac - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 44 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi44: GPI44, - #[doc = "0xb0 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 48 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi48: GPI48, - #[doc = "0xb4 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 52 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi52: GPI52, - #[doc = "0xb8 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 56 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi56: GPI56, - #[doc = "0xbc - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 60 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi60: GPI60, - #[doc = "0xc0 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 64 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi64: GPI64, - #[doc = "0xc4 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 68 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi68: GPI68, - #[doc = "0xc8 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 72 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi72: GPI72, - #[doc = "0xcc - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 76 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi76: GPI76, - #[doc = "0xd0 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 80 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi80: GPI80, - #[doc = "0xd4 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 84 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi84: GPI84, - #[doc = "0xd8 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 88 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi88: GPI88, - #[doc = "0xdc - Enable GPIO IRQ function"] - pub ioirq0: IOIRQ0, + gpi4: GPI4, + gpi8: GPI8, + gpi12: GPI12, + gpi16: GPI16, + gpi20: GPI20, + gpi24: GPI24, + gpi28: GPI28, + gpi32: GPI32, + gpi36: GPI36, + gpi40: GPI40, + gpi44: GPI44, + gpi48: GPI48, + gpi52: GPI52, + gpi56: GPI56, + gpi60: GPI60, + gpi64: GPI64, + gpi68: GPI68, + gpi72: GPI72, + gpi76: GPI76, + gpi80: GPI80, + gpi84: GPI84, + gpi88: GPI88, + ioirq0: IOIRQ0, _reserved38: [u8; 0x40], - #[doc = "0x120 - SYS IOMUX CFG SAIF SYSCFG PADCFG 288: GPIO0"] - pub padcfg_gpio0: PADCFG_GPIO0, - #[doc = "0x124 - SYS IOMUX CFG SAIF SYSCFG PADCFG 292: GPIO1"] - pub padcfg_gpio1: PADCFG_GPIO1, - #[doc = "0x128 - SYS IOMUX CFG SAIF SYSCFG PADCFG 296: GPIO2"] - pub padcfg_gpio2: PADCFG_GPIO2, - #[doc = "0x12c - SYS IOMUX CFG SAIF SYSCFG PADCFG 300: GPIO3"] - pub padcfg_gpio3: PADCFG_GPIO3, - #[doc = "0x130 - SYS IOMUX CFG SAIF SYSCFG PADCFG 304: GPIO4"] - pub padcfg_gpio4: PADCFG_GPIO4, - #[doc = "0x134 - SYS IOMUX CFG SAIF SYSCFG PADCFG 308: GPIO5"] - pub padcfg_gpio5: PADCFG_GPIO5, - #[doc = "0x138 - SYS IOMUX CFG SAIF SYSCFG PADCFG 312: GPIO6"] - pub padcfg_gpio6: PADCFG_GPIO6, - #[doc = "0x13c - SYS IOMUX CFG SAIF SYSCFG PADCFG 316: GPIO7"] - pub padcfg_gpio7: PADCFG_GPIO7, - #[doc = "0x140 - SYS IOMUX CFG SAIF SYSCFG PADCFG 320: GPIO8"] - pub padcfg_gpio8: PADCFG_GPIO8, - #[doc = "0x144 - SYS IOMUX CFG SAIF SYSCFG PADCFG 324: GPIO9"] - pub padcfg_gpio9: PADCFG_GPIO9, - #[doc = "0x148 - SYS IOMUX CFG SAIF SYSCFG PADCFG 328: GPIO10"] - pub padcfg_gpio10: PADCFG_GPIO10, - #[doc = "0x14c - SYS IOMUX CFG SAIF SYSCFG PADCFG 332: GPIO11"] - pub padcfg_gpio11: PADCFG_GPIO11, - #[doc = "0x150 - SYS IOMUX CFG SAIF SYSCFG PADCFG 336: GPIO12"] - pub padcfg_gpio12: PADCFG_GPIO12, - #[doc = "0x154 - SYS IOMUX CFG SAIF SYSCFG PADCFG 340: GPIO13"] - pub padcfg_gpio13: PADCFG_GPIO13, - #[doc = "0x158 - SYS IOMUX CFG SAIF SYSCFG PADCFG 344: GPIO14"] - pub padcfg_gpio14: PADCFG_GPIO14, - #[doc = "0x15c - SYS IOMUX CFG SAIF SYSCFG PADCFG 348: GPIO15"] - pub padcfg_gpio15: PADCFG_GPIO15, - #[doc = "0x160 - SYS IOMUX CFG SAIF SYSCFG PADCFG 352: GPIO16"] - pub padcfg_gpio16: PADCFG_GPIO16, - #[doc = "0x164 - SYS IOMUX CFG SAIF SYSCFG PADCFG 356: GPIO17"] - pub padcfg_gpio17: PADCFG_GPIO17, - #[doc = "0x168 - SYS IOMUX CFG SAIF SYSCFG PADCFG 360: GPIO18"] - pub padcfg_gpio18: PADCFG_GPIO18, - #[doc = "0x16c - SYS IOMUX CFG SAIF SYSCFG PADCFG 364: GPIO19"] - pub padcfg_gpio19: PADCFG_GPIO19, - #[doc = "0x170 - SYS IOMUX CFG SAIF SYSCFG PADCFG 368: GPIO20"] - pub padcfg_gpio20: PADCFG_GPIO20, - #[doc = "0x174 - SYS IOMUX CFG SAIF SYSCFG PADCFG 372: GPIO21"] - pub padcfg_gpio21: PADCFG_GPIO21, - #[doc = "0x178 - SYS IOMUX CFG SAIF SYSCFG PADCFG 376: GPIO22"] - pub padcfg_gpio22: PADCFG_GPIO22, - #[doc = "0x17c - SYS IOMUX CFG SAIF SYSCFG PADCFG 380: GPIO23"] - pub padcfg_gpio23: PADCFG_GPIO23, - #[doc = "0x180 - SYS IOMUX CFG SAIF SYSCFG PADCFG 384: GPIO24"] - pub padcfg_gpio24: PADCFG_GPIO24, - #[doc = "0x184 - SYS IOMUX CFG SAIF SYSCFG PADCFG 388: GPIO25"] - pub padcfg_gpio25: PADCFG_GPIO25, - #[doc = "0x188 - SYS IOMUX CFG SAIF SYSCFG PADCFG 392: GPIO26"] - pub padcfg_gpio26: PADCFG_GPIO26, - #[doc = "0x18c - SYS IOMUX CFG SAIF SYSCFG PADCFG 396: GPIO27"] - pub padcfg_gpio27: PADCFG_GPIO27, - #[doc = "0x190 - SYS IOMUX CFG SAIF SYSCFG PADCFG 400: GPIO28"] - pub padcfg_gpio28: PADCFG_GPIO28, - #[doc = "0x194 - SYS IOMUX CFG SAIF SYSCFG PADCFG 404: GPIO29"] - pub padcfg_gpio29: PADCFG_GPIO29, - #[doc = "0x198 - SYS IOMUX CFG SAIF SYSCFG PADCFG 408: GPIO30"] - pub padcfg_gpio30: PADCFG_GPIO30, - #[doc = "0x19c - SYS IOMUX CFG SAIF SYSCFG PADCFG 412: GPIO31"] - pub padcfg_gpio31: PADCFG_GPIO31, - #[doc = "0x1a0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 416: GPIO32"] - pub padcfg_gpio32: PADCFG_GPIO32, - #[doc = "0x1a4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 420: GPIO33"] - pub padcfg_gpio33: PADCFG_GPIO33, - #[doc = "0x1a8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 424: GPIO34"] - pub padcfg_gpio34: PADCFG_GPIO34, - #[doc = "0x1ac - SYS IOMUX CFG SAIF SYSCFG PADCFG 428: GPIO35"] - pub padcfg_gpio35: PADCFG_GPIO35, - #[doc = "0x1b0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 432: GPIO36"] - pub padcfg_gpio36: PADCFG_GPIO36, - #[doc = "0x1b4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 436: GPIO37"] - pub padcfg_gpio37: PADCFG_GPIO37, - #[doc = "0x1b8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 440: GPIO38"] - pub padcfg_gpio38: PADCFG_GPIO38, - #[doc = "0x1bc - SYS IOMUX CFG SAIF SYSCFG PADCFG 444: GPIO39"] - pub padcfg_gpio39: PADCFG_GPIO39, - #[doc = "0x1c0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 448: GPIO40"] - pub padcfg_gpio40: PADCFG_GPIO40, - #[doc = "0x1c4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 452: GPIO41"] - pub padcfg_gpio41: PADCFG_GPIO41, - #[doc = "0x1c8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 456: GPIO42"] - pub padcfg_gpio42: PADCFG_GPIO42, - #[doc = "0x1cc - SYS IOMUX CFG SAIF SYSCFG PADCFG 460: GPIO43"] - pub padcfg_gpio43: PADCFG_GPIO43, - #[doc = "0x1d0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 464: GPIO44"] - pub padcfg_gpio44: PADCFG_GPIO44, - #[doc = "0x1d4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 468: GPIO45"] - pub padcfg_gpio45: PADCFG_GPIO45, - #[doc = "0x1d8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 472: GPIO46"] - pub padcfg_gpio46: PADCFG_GPIO46, - #[doc = "0x1dc - SYS IOMUX CFG SAIF SYSCFG PADCFG 476: GPIO47"] - pub padcfg_gpio47: PADCFG_GPIO47, - #[doc = "0x1e0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 480: GPIO48"] - pub padcfg_gpio48: PADCFG_GPIO48, - #[doc = "0x1e4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 484: GPIO49"] - pub padcfg_gpio49: PADCFG_GPIO49, - #[doc = "0x1e8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 488: GPIO50"] - pub padcfg_gpio50: PADCFG_GPIO50, - #[doc = "0x1ec - SYS IOMUX CFG SAIF SYSCFG PADCFG 492: GPIO51"] - pub padcfg_gpio51: PADCFG_GPIO51, - #[doc = "0x1f0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 496: GPIO52"] - pub padcfg_gpio52: PADCFG_GPIO52, - #[doc = "0x1f4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 500: GPIO53"] - pub padcfg_gpio53: PADCFG_GPIO53, - #[doc = "0x1f8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 504: GPIO54"] - pub padcfg_gpio54: PADCFG_GPIO54, - #[doc = "0x1fc - SYS IOMUX CFG SAIF SYSCFG PADCFG 508: GPIO55"] - pub padcfg_gpio55: PADCFG_GPIO55, - #[doc = "0x200 - SYS IOMUX CFG SAIF SYSCFG PADCFG 512: GPIO56"] - pub padcfg_gpio56: PADCFG_GPIO56, - #[doc = "0x204 - SYS IOMUX CFG SAIF SYSCFG PADCFG 516: GPIO57"] - pub padcfg_gpio57: PADCFG_GPIO57, - #[doc = "0x208 - SYS IOMUX CFG SAIF SYSCFG PADCFG 520: GPIO58"] - pub padcfg_gpio58: PADCFG_GPIO58, - #[doc = "0x20c - SYS IOMUX CFG SAIF SYSCFG PADCFG 524: GPIO59"] - pub padcfg_gpio59: PADCFG_GPIO59, - #[doc = "0x210 - SYS IOMUX CFG SAIF SYSCFG PADCFG 528: GPIO60"] - pub padcfg_gpio60: PADCFG_GPIO60, - #[doc = "0x214 - SYS IOMUX CFG SAIF SYSCFG PADCFG 532: GPIO61"] - pub padcfg_gpio61: PADCFG_GPIO61, - #[doc = "0x218 - SYS IOMUX CFG SAIF SYSCFG PADCFG 536: GPIO62"] - pub padcfg_gpio62: PADCFG_GPIO62, - #[doc = "0x21c - SYS IOMUX CFG SAIF SYSCFG PADCFG 540: GPIO63"] - pub padcfg_gpio63: PADCFG_GPIO63, - #[doc = "0x220 - SYS IOMUX CFG SAIF SYSCFG PADCFG 544: SD0_CLK"] - pub padcfg_sd0_clk: PADCFG_SD0_CLK, - #[doc = "0x224 - SYS IOMUX CFG SAIF SYSCFG PADCFG 548: SD0_CMD"] - pub padcfg_sd0_cmd: PADCFG_SD0_CMD, - #[doc = "0x228 - SYS IOMUX CFG SAIF SYSCFG PADCFG 552: SD0_DATA0"] - pub padcfg_sd0_data0: PADCFG_SD0_DATA0, + padcfg_gpio0: PADCFG_GPIO0, + padcfg_gpio1: PADCFG_GPIO1, + padcfg_gpio2: PADCFG_GPIO2, + padcfg_gpio3: PADCFG_GPIO3, + padcfg_gpio4: PADCFG_GPIO4, + padcfg_gpio5: PADCFG_GPIO5, + padcfg_gpio6: PADCFG_GPIO6, + padcfg_gpio7: PADCFG_GPIO7, + padcfg_gpio8: PADCFG_GPIO8, + padcfg_gpio9: PADCFG_GPIO9, + padcfg_gpio10: PADCFG_GPIO10, + padcfg_gpio11: PADCFG_GPIO11, + padcfg_gpio12: PADCFG_GPIO12, + padcfg_gpio13: PADCFG_GPIO13, + padcfg_gpio14: PADCFG_GPIO14, + padcfg_gpio15: PADCFG_GPIO15, + padcfg_gpio16: PADCFG_GPIO16, + padcfg_gpio17: PADCFG_GPIO17, + padcfg_gpio18: PADCFG_GPIO18, + padcfg_gpio19: PADCFG_GPIO19, + padcfg_gpio20: PADCFG_GPIO20, + padcfg_gpio21: PADCFG_GPIO21, + padcfg_gpio22: PADCFG_GPIO22, + padcfg_gpio23: PADCFG_GPIO23, + padcfg_gpio24: PADCFG_GPIO24, + padcfg_gpio25: PADCFG_GPIO25, + padcfg_gpio26: PADCFG_GPIO26, + padcfg_gpio27: PADCFG_GPIO27, + padcfg_gpio28: PADCFG_GPIO28, + padcfg_gpio29: PADCFG_GPIO29, + padcfg_gpio30: PADCFG_GPIO30, + padcfg_gpio31: PADCFG_GPIO31, + padcfg_gpio32: PADCFG_GPIO32, + padcfg_gpio33: PADCFG_GPIO33, + padcfg_gpio34: PADCFG_GPIO34, + padcfg_gpio35: PADCFG_GPIO35, + padcfg_gpio36: PADCFG_GPIO36, + padcfg_gpio37: PADCFG_GPIO37, + padcfg_gpio38: PADCFG_GPIO38, + padcfg_gpio39: PADCFG_GPIO39, + padcfg_gpio40: PADCFG_GPIO40, + padcfg_gpio41: PADCFG_GPIO41, + padcfg_gpio42: PADCFG_GPIO42, + padcfg_gpio43: PADCFG_GPIO43, + padcfg_gpio44: PADCFG_GPIO44, + padcfg_gpio45: PADCFG_GPIO45, + padcfg_gpio46: PADCFG_GPIO46, + padcfg_gpio47: PADCFG_GPIO47, + padcfg_gpio48: PADCFG_GPIO48, + padcfg_gpio49: PADCFG_GPIO49, + padcfg_gpio50: PADCFG_GPIO50, + padcfg_gpio51: PADCFG_GPIO51, + padcfg_gpio52: PADCFG_GPIO52, + padcfg_gpio53: PADCFG_GPIO53, + padcfg_gpio54: PADCFG_GPIO54, + padcfg_gpio55: PADCFG_GPIO55, + padcfg_gpio56: PADCFG_GPIO56, + padcfg_gpio57: PADCFG_GPIO57, + padcfg_gpio58: PADCFG_GPIO58, + padcfg_gpio59: PADCFG_GPIO59, + padcfg_gpio60: PADCFG_GPIO60, + padcfg_gpio61: PADCFG_GPIO61, + padcfg_gpio62: PADCFG_GPIO62, + padcfg_gpio63: PADCFG_GPIO63, + padcfg_sd0_clk: PADCFG_SD0_CLK, + padcfg_sd0_cmd: PADCFG_SD0_CMD, + padcfg_sd0_data0: PADCFG_SD0_DATA0, _reserved105: [u8; 0x0c], - #[doc = "0x238 - SYS IOMUX CFG SAIF SYSCFG PADCFG 568: SD0_DATA1"] - pub padcfg_sd0_data1: PADCFG_SD0_DATA1, + padcfg_sd0_data1: PADCFG_SD0_DATA1, _reserved106: [u8; 0x0c], _reserved_106_padcfg_sd0: [u8; 0x04], _reserved107: [u8; 0x0c], - #[doc = "0x258 - SYS IOMUX CFG SAIF SYSCFG PADCFG 600: SD0_DATA3"] - pub padcfg_sd0_data3: PADCFG_SD0_DATA3, + padcfg_sd0_data3: PADCFG_SD0_DATA3, _reserved108: [u8; 0x0c], - #[doc = "0x268 - SYS IOMUX CFG SAIF SYSCFG PADCFG 616: SD0_DATA4"] - pub padcfg_sd0_data4: PADCFG_SD0_DATA4, + padcfg_sd0_data4: PADCFG_SD0_DATA4, _reserved109: [u8; 0x0c], - #[doc = "0x278 - SYS IOMUX CFG SAIF SYSCFG PADCFG 632: SD0_DATA5"] - pub padcfg_sd0_data5: PADCFG_SD0_DATA5, + padcfg_sd0_data5: PADCFG_SD0_DATA5, _reserved110: [u8; 0x08], - #[doc = "0x284 - SYS IOMUX CFG SAIF SYSCFG PADCFG 644: QSPI_SCLK"] - pub padcfg_qspi_sclk: PADCFG_QSPI_SCLK, + padcfg_qspi_sclk: PADCFG_QSPI_SCLK, _reserved_111_padcfg: [u8; 0x04], - #[doc = "0x28c - SYS IOMUX CFG SAIF SYSCFG PADCFG 652: QSPI_DATA0"] - pub padcfg_qspi_data0: PADCFG_QSPI_DATA0, + padcfg_qspi_data0: PADCFG_QSPI_DATA0, _reserved113: [u8; 0x08], - #[doc = "0x298 - SYS IOMUX CFG SAIF SYSCFG PADCFG 664: SD0_DATA7"] - pub padcfg_sd0_data7: PADCFG_SD0_DATA7, + padcfg_sd0_data7: PADCFG_SD0_DATA7, _reserved_114_func_sel0: [u8; 0x04], - #[doc = "0x2a0 - SYS IOMUX CFG SAIF SYSCFG 1"] - pub func_sel1: FUNC_SEL1, - #[doc = "0x2a4 - SYS IOMUX CFG SAIF SYSCFG 2"] - pub func_sel2: FUNC_SEL2, - #[doc = "0x2a8 - SYS IOMUX CFG SAIF SYSCFG 3"] - pub func_sel3: FUNC_SEL3, + func_sel1: FUNC_SEL1, + func_sel2: FUNC_SEL2, + func_sel3: FUNC_SEL3, _reserved_118_func_sel4: [u8; 0x04], - #[doc = "0x2b0 - SYS IOMUX CFG SAIF SYSCFG 5"] - pub func_sel5: FUNC_SEL5, - #[doc = "0x2b4 - SYS IOMUX CFG SAIF SYSCFG 6"] - pub func_sel6: FUNC_SEL6, + func_sel5: FUNC_SEL5, + func_sel6: FUNC_SEL6, _reserved121: [u8; 0x04], - #[doc = "0x2bc - SYS IOMUX CFG SAIF SYSCFG PADCFG 700: QSPI_DATA3"] - pub padcfg_qspi_data3: PADCFG_QSPI_DATA3, + padcfg_qspi_data3: PADCFG_QSPI_DATA3, } impl RegisterBlock { + #[doc = "0x00 - SYS IOMUX CFG SAIF SYSCFG FMUX 0 DOEN"] + #[inline(always)] + pub const fn gpo_doen0(&self) -> &GPO_DOEN0 { + &self.gpo_doen0 + } + #[doc = "0x04 - SYS IOMUX CFG SAIF SYSCFG FMUX 1 DOEN"] + #[inline(always)] + pub const fn gpo_doen1(&self) -> &GPO_DOEN1 { + &self.gpo_doen1 + } + #[doc = "0x08 - SYS IOMUX CFG SAIF SYSCFG FMUX 2 DOEN"] + #[inline(always)] + pub const fn gpo_doen2(&self) -> &GPO_DOEN2 { + &self.gpo_doen2 + } + #[doc = "0x0c - SYS IOMUX CFG SAIF SYSCFG FMUX 3 DOEN"] + #[inline(always)] + pub const fn gpo_doen3(&self) -> &GPO_DOEN3 { + &self.gpo_doen3 + } + #[doc = "0x10 - SYS IOMUX CFG SAIF SYSCFG FMUX 4 DOEN"] + #[inline(always)] + pub const fn gpo_doen4(&self) -> &GPO_DOEN4 { + &self.gpo_doen4 + } + #[doc = "0x14 - SYS IOMUX CFG SAIF SYSCFG FMUX 5 DOEN"] + #[inline(always)] + pub const fn gpo_doen5(&self) -> &GPO_DOEN5 { + &self.gpo_doen5 + } + #[doc = "0x18 - SYS IOMUX CFG SAIF SYSCFG FMUX 6 DOEN"] + #[inline(always)] + pub const fn gpo_doen6(&self) -> &GPO_DOEN6 { + &self.gpo_doen6 + } + #[doc = "0x1c - SYS IOMUX CFG SAIF SYSCFG FMUX 7 DOEN"] + #[inline(always)] + pub const fn gpo_doen7(&self) -> &GPO_DOEN7 { + &self.gpo_doen7 + } + #[doc = "0x20 - SYS IOMUX CFG SAIF SYSCFG FMUX 8 DOEN"] + #[inline(always)] + pub const fn gpo_doen8(&self) -> &GPO_DOEN8 { + &self.gpo_doen8 + } + #[doc = "0x24 - SYS IOMUX CFG SAIF SYSCFG FMUX 9 DOEN"] + #[inline(always)] + pub const fn gpo_doen9(&self) -> &GPO_DOEN9 { + &self.gpo_doen9 + } + #[doc = "0x28 - SYS IOMUX CFG SAIF SYSCFG FMUX 10 DOEN"] + #[inline(always)] + pub const fn gpo_doen10(&self) -> &GPO_DOEN10 { + &self.gpo_doen10 + } + #[doc = "0x2c - SYS IOMUX CFG SAIF SYSCFG FMUX 11 DOEN"] + #[inline(always)] + pub const fn gpo_doen11(&self) -> &GPO_DOEN11 { + &self.gpo_doen11 + } + #[doc = "0x30 - SYS IOMUX CFG SAIF SYSCFG FMUX 12 DOEN"] + #[inline(always)] + pub const fn gpo_doen12(&self) -> &GPO_DOEN12 { + &self.gpo_doen12 + } + #[doc = "0x34 - SYS IOMUX CFG SAIF SYSCFG FMUX 13 DOEN"] + #[inline(always)] + pub const fn gpo_doen13(&self) -> &GPO_DOEN13 { + &self.gpo_doen13 + } #[doc = "0x38 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 56: GPIO Interrupt Edge Trigger Selector"] #[inline(always)] pub const fn ioirq1(&self) -> &IOIRQ1 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x38 - SYS IOMUX CFG SAIF SYSCFG FMUX 14 DOEN"] #[inline(always)] pub const fn gpo_doen14(&self) -> &GPO_DOEN14 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x39 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 57: GPIO Interrupt Edge Trigger Selector"] #[inline(always)] pub const fn ioirq2(&self) -> &IOIRQ2 { - unsafe { &*(self as *const Self).cast::().add(57usize).cast() } + unsafe { &*(self as *const Self).cast::().add(57).cast() } } #[doc = "0x3a - SYS IOMUX CFGSAIF SYSCFG IOIRQ 58: GPIO Interrupt Clear"] #[inline(always)] pub const fn ioirq3(&self) -> &IOIRQ3 { - unsafe { &*(self as *const Self).cast::().add(58usize).cast() } + unsafe { &*(self as *const Self).cast::().add(58).cast() } } #[doc = "0x3b - SYS IOMUX CFGSAIF SYSCFG IOIRQ 59: GPIO Interrupt Clear"] #[inline(always)] pub const fn ioirq4(&self) -> &IOIRQ4 { - unsafe { &*(self as *const Self).cast::().add(59usize).cast() } + unsafe { &*(self as *const Self).cast::().add(59).cast() } } #[doc = "0x3c - SYS IOMUX CFGSAIF SYSCFG IOIRQ 60: GPIO Interrupt Both Edge Trigger Selector"] #[inline(always)] pub const fn ioirq5(&self) -> &IOIRQ5 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x3c - SYS IOMUX CFG SAIF SYSCFG FMUX 15 DOEN"] #[inline(always)] pub const fn gpo_doen15(&self) -> &GPO_DOEN15 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x3d - SYS IOMUX CFGSAIF SYSCFG IOIRQ 61: GPIO Interrupt Both Edge Trigger Selector"] #[inline(always)] pub const fn ioirq6(&self) -> &IOIRQ6 { - unsafe { &*(self as *const Self).cast::().add(61usize).cast() } + unsafe { &*(self as *const Self).cast::().add(61).cast() } } #[doc = "0x3e - SYS IOMUX CFGSAIF SYSCFG IOIRQ 62: GPIO Interrupt Edge Value"] #[inline(always)] pub const fn ioirq7(&self) -> &IOIRQ7 { - unsafe { &*(self as *const Self).cast::().add(62usize).cast() } + unsafe { &*(self as *const Self).cast::().add(62).cast() } } #[doc = "0x3f - SYS IOMUX CFGSAIF SYSCFG IOIRQ 63: GPIO Interrupt Edge Value"] #[inline(always)] pub const fn ioirq8(&self) -> &IOIRQ8 { - unsafe { &*(self as *const Self).cast::().add(63usize).cast() } + unsafe { &*(self as *const Self).cast::().add(63).cast() } } #[doc = "0x40 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 64: GPIO Interrupt Edge Mask Selector"] #[inline(always)] pub const fn ioirq9(&self) -> &IOIRQ9 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x40 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 0-3 DOUT"] #[inline(always)] pub const fn gpo_dout0_3(&self) -> &GPO_DOUT0_3 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x41 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 65: GPIO Interrupt Edge Mask Selector"] #[inline(always)] pub const fn ioirq10(&self) -> &IOIRQ10 { - unsafe { &*(self as *const Self).cast::().add(65usize).cast() } + unsafe { &*(self as *const Self).cast::().add(65).cast() } } #[doc = "0x42 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 66: GPIO Register Interrupt Status"] #[inline(always)] pub const fn ioirq11(&self) -> &IOIRQ11 { - unsafe { &*(self as *const Self).cast::().add(66usize).cast() } + unsafe { &*(self as *const Self).cast::().add(66).cast() } } #[doc = "0x43 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 67: GPIO Register Interrupt Status"] #[inline(always)] pub const fn ioirq12(&self) -> &IOIRQ12 { - unsafe { &*(self as *const Self).cast::().add(67usize).cast() } + unsafe { &*(self as *const Self).cast::().add(67).cast() } } #[doc = "0x44 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 68: GPIO Masked Interrupt Status"] #[inline(always)] pub const fn ioirq13(&self) -> &IOIRQ13 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x44 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 4-7 DOUT"] #[inline(always)] pub const fn gpo_dout4_7(&self) -> &GPO_DOUT4_7 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x45 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 69: GPIO Masked Interrupt Status"] #[inline(always)] pub const fn ioirq14(&self) -> &IOIRQ14 { - unsafe { &*(self as *const Self).cast::().add(69usize).cast() } + unsafe { &*(self as *const Self).cast::().add(69).cast() } } #[doc = "0x46 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 70: GPIO Synchronization Status"] #[inline(always)] pub const fn ioirq15(&self) -> &IOIRQ15 { - unsafe { &*(self as *const Self).cast::().add(70usize).cast() } + unsafe { &*(self as *const Self).cast::().add(70).cast() } } #[doc = "0x47 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 71: GPIO Synchronization Status"] #[inline(always)] pub const fn ioirq16(&self) -> &IOIRQ16 { - unsafe { &*(self as *const Self).cast::().add(71usize).cast() } + unsafe { &*(self as *const Self).cast::().add(71).cast() } } #[doc = "0x48 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 8-11 DOUT"] #[inline(always)] pub const fn gpo_dout8_11(&self) -> &GPO_DOUT8_11 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x4b - GPIO GMAC1 MDC Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_mdc_syscon(&self) -> &PADCFG_GMAC1_MDC_SYSCON { - unsafe { &*(self as *const Self).cast::().add(75usize).cast() } + unsafe { &*(self as *const Self).cast::().add(75).cast() } } #[doc = "0x4c - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 12-15 DOUT"] #[inline(always)] pub const fn gpo_dout12_15(&self) -> &GPO_DOUT12_15 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x4f - GPIO GMAC1 MDIO Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_mdio_syscon(&self) -> &PADCFG_GMAC1_MDIO_SYSCON { - unsafe { &*(self as *const Self).cast::().add(79usize).cast() } + unsafe { &*(self as *const Self).cast::().add(79).cast() } } #[doc = "0x50 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 16-19 DOUT"] #[inline(always)] pub const fn gpo_dout16_19(&self) -> &GPO_DOUT16_19 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x53 - GPIO GMAC1 RXD0 Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_rxd0_syscon(&self) -> &PADCFG_GMAC1_RXD0_SYSCON { - unsafe { &*(self as *const Self).cast::().add(83usize).cast() } + unsafe { &*(self as *const Self).cast::().add(83).cast() } } #[doc = "0x54 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 20-23 DOUT"] #[inline(always)] pub const fn gpo_dout20_23(&self) -> &GPO_DOUT20_23 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x57 - GPIO GMAC1 RXD1 Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_rxd1_syscon(&self) -> &PADCFG_GMAC1_RXD1_SYSCON { - unsafe { &*(self as *const Self).cast::().add(87usize).cast() } + unsafe { &*(self as *const Self).cast::().add(87).cast() } } #[doc = "0x58 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 24-27 DOUT"] #[inline(always)] pub const fn gpo_dout24_27(&self) -> &GPO_DOUT24_27 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x5b - GPIO GMAC1 RXD2 Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_rxd2_syscon(&self) -> &PADCFG_GMAC1_RXD2_SYSCON { - unsafe { &*(self as *const Self).cast::().add(91usize).cast() } + unsafe { &*(self as *const Self).cast::().add(91).cast() } } #[doc = "0x5c - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 28-31 DOUT"] #[inline(always)] pub const fn gpo_dout28_31(&self) -> &GPO_DOUT28_31 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x5f - GPIO GMAC1 RXD3 Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_rxd3_syscon(&self) -> &PADCFG_GMAC1_RXD3_SYSCON { - unsafe { &*(self as *const Self).cast::().add(95usize).cast() } + unsafe { &*(self as *const Self).cast::().add(95).cast() } } #[doc = "0x60 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 32-35 DOUT"] #[inline(always)] pub const fn gpo_dout32_35(&self) -> &GPO_DOUT32_35 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x63 - GPIO GMAC1 RXDV Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_rxdv_syscon(&self) -> &PADCFG_GMAC1_RXDV_SYSCON { - unsafe { &*(self as *const Self).cast::().add(99usize).cast() } + unsafe { &*(self as *const Self).cast::().add(99).cast() } } #[doc = "0x64 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 36-39 DOUT"] #[inline(always)] pub const fn gpo_dout36_39(&self) -> &GPO_DOUT36_39 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x67 - GPIO GMAC1 RXC Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_rxc_syscon(&self) -> &PADCFG_GMAC1_RXC_SYSCON { - unsafe { &*(self as *const Self).cast::().add(103usize).cast() } + unsafe { &*(self as *const Self).cast::().add(103).cast() } } #[doc = "0x68 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 40-43 DOUT"] #[inline(always)] pub const fn gpo_dout40_43(&self) -> &GPO_DOUT40_43 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x6b - GPIO GMAC1 TXD0 Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_txd0_syscon(&self) -> &PADCFG_GMAC1_TXD0_SYSCON { - unsafe { &*(self as *const Self).cast::().add(107usize).cast() } + unsafe { &*(self as *const Self).cast::().add(107).cast() } } #[doc = "0x6c - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 44-47 DOUT"] #[inline(always)] pub const fn gpo_dout44_47(&self) -> &GPO_DOUT44_47 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } } #[doc = "0x6f - GPIO GMAC1 TXD1 Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_txd1_syscon(&self) -> &PADCFG_GMAC1_TXD1_SYSCON { - unsafe { &*(self as *const Self).cast::().add(111usize).cast() } + unsafe { &*(self as *const Self).cast::().add(111).cast() } } #[doc = "0x70 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 48-51 DOUT"] #[inline(always)] pub const fn gpo_dout48_51(&self) -> &GPO_DOUT48_51 { - unsafe { &*(self as *const Self).cast::().add(112usize).cast() } + unsafe { &*(self as *const Self).cast::().add(112).cast() } } #[doc = "0x73 - GPIO GMAC1 TXD2 Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_txd2_syscon(&self) -> &PADCFG_GMAC1_TXD2_SYSCON { - unsafe { &*(self as *const Self).cast::().add(115usize).cast() } + unsafe { &*(self as *const Self).cast::().add(115).cast() } } #[doc = "0x74 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 52-55 DOUT"] #[inline(always)] pub const fn gpo_dout52_55(&self) -> &GPO_DOUT52_55 { - unsafe { &*(self as *const Self).cast::().add(116usize).cast() } + unsafe { &*(self as *const Self).cast::().add(116).cast() } } #[doc = "0x77 - GPIO GMAC1 TXD3 Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_txd3_syscon(&self) -> &PADCFG_GMAC1_TXD3_SYSCON { - unsafe { &*(self as *const Self).cast::().add(119usize).cast() } + unsafe { &*(self as *const Self).cast::().add(119).cast() } } #[doc = "0x78 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 56-59 DOUT"] #[inline(always)] pub const fn gpo_dout56_59(&self) -> &GPO_DOUT56_59 { - unsafe { &*(self as *const Self).cast::().add(120usize).cast() } + unsafe { &*(self as *const Self).cast::().add(120).cast() } } #[doc = "0x7b - GPIO GMAC1 TXEN Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_txen_syscon(&self) -> &PADCFG_GMAC1_TXEN_SYSCON { - unsafe { &*(self as *const Self).cast::().add(123usize).cast() } + unsafe { &*(self as *const Self).cast::().add(123).cast() } } #[doc = "0x7c - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 60-63 DOUT"] #[inline(always)] pub const fn gpo_dout60_63(&self) -> &GPO_DOUT60_63 { - unsafe { &*(self as *const Self).cast::().add(124usize).cast() } + unsafe { &*(self as *const Self).cast::().add(124).cast() } } #[doc = "0x7f - GPIO GMAC1 TXC Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_txc_syscon(&self) -> &PADCFG_GMAC1_TXC_SYSCON { - unsafe { &*(self as *const Self).cast::().add(127usize).cast() } + unsafe { &*(self as *const Self).cast::().add(127).cast() } } #[doc = "0x80 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 0 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] #[inline(always)] pub const fn gpi0(&self) -> &GPI0 { - unsafe { &*(self as *const Self).cast::().add(128usize).cast() } + unsafe { &*(self as *const Self).cast::().add(128).cast() } + } + #[doc = "0x84 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 4 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi4(&self) -> &GPI4 { + &self.gpi4 + } + #[doc = "0x88 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 8 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi8(&self) -> &GPI8 { + &self.gpi8 + } + #[doc = "0x8c - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 12 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi12(&self) -> &GPI12 { + &self.gpi12 + } + #[doc = "0x90 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 16 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi16(&self) -> &GPI16 { + &self.gpi16 + } + #[doc = "0x94 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 20 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi20(&self) -> &GPI20 { + &self.gpi20 + } + #[doc = "0x98 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 24 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi24(&self) -> &GPI24 { + &self.gpi24 + } + #[doc = "0x9c - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 28 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi28(&self) -> &GPI28 { + &self.gpi28 + } + #[doc = "0xa0 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 32 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi32(&self) -> &GPI32 { + &self.gpi32 + } + #[doc = "0xa4 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 36 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi36(&self) -> &GPI36 { + &self.gpi36 + } + #[doc = "0xa8 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 40 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi40(&self) -> &GPI40 { + &self.gpi40 + } + #[doc = "0xac - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 44 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi44(&self) -> &GPI44 { + &self.gpi44 + } + #[doc = "0xb0 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 48 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi48(&self) -> &GPI48 { + &self.gpi48 + } + #[doc = "0xb4 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 52 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi52(&self) -> &GPI52 { + &self.gpi52 + } + #[doc = "0xb8 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 56 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi56(&self) -> &GPI56 { + &self.gpi56 + } + #[doc = "0xbc - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 60 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi60(&self) -> &GPI60 { + &self.gpi60 + } + #[doc = "0xc0 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 64 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi64(&self) -> &GPI64 { + &self.gpi64 + } + #[doc = "0xc4 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 68 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi68(&self) -> &GPI68 { + &self.gpi68 + } + #[doc = "0xc8 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 72 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi72(&self) -> &GPI72 { + &self.gpi72 + } + #[doc = "0xcc - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 76 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi76(&self) -> &GPI76 { + &self.gpi76 + } + #[doc = "0xd0 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 80 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi80(&self) -> &GPI80 { + &self.gpi80 + } + #[doc = "0xd4 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 84 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi84(&self) -> &GPI84 { + &self.gpi84 + } + #[doc = "0xd8 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 88 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi88(&self) -> &GPI88 { + &self.gpi88 + } + #[doc = "0xdc - Enable GPIO IRQ function"] + #[inline(always)] + pub const fn ioirq0(&self) -> &IOIRQ0 { + &self.ioirq0 + } + #[doc = "0x120 - SYS IOMUX CFG SAIF SYSCFG PADCFG 288: GPIO0"] + #[inline(always)] + pub const fn padcfg_gpio0(&self) -> &PADCFG_GPIO0 { + &self.padcfg_gpio0 + } + #[doc = "0x124 - SYS IOMUX CFG SAIF SYSCFG PADCFG 292: GPIO1"] + #[inline(always)] + pub const fn padcfg_gpio1(&self) -> &PADCFG_GPIO1 { + &self.padcfg_gpio1 + } + #[doc = "0x128 - SYS IOMUX CFG SAIF SYSCFG PADCFG 296: GPIO2"] + #[inline(always)] + pub const fn padcfg_gpio2(&self) -> &PADCFG_GPIO2 { + &self.padcfg_gpio2 + } + #[doc = "0x12c - SYS IOMUX CFG SAIF SYSCFG PADCFG 300: GPIO3"] + #[inline(always)] + pub const fn padcfg_gpio3(&self) -> &PADCFG_GPIO3 { + &self.padcfg_gpio3 + } + #[doc = "0x130 - SYS IOMUX CFG SAIF SYSCFG PADCFG 304: GPIO4"] + #[inline(always)] + pub const fn padcfg_gpio4(&self) -> &PADCFG_GPIO4 { + &self.padcfg_gpio4 + } + #[doc = "0x134 - SYS IOMUX CFG SAIF SYSCFG PADCFG 308: GPIO5"] + #[inline(always)] + pub const fn padcfg_gpio5(&self) -> &PADCFG_GPIO5 { + &self.padcfg_gpio5 + } + #[doc = "0x138 - SYS IOMUX CFG SAIF SYSCFG PADCFG 312: GPIO6"] + #[inline(always)] + pub const fn padcfg_gpio6(&self) -> &PADCFG_GPIO6 { + &self.padcfg_gpio6 + } + #[doc = "0x13c - SYS IOMUX CFG SAIF SYSCFG PADCFG 316: GPIO7"] + #[inline(always)] + pub const fn padcfg_gpio7(&self) -> &PADCFG_GPIO7 { + &self.padcfg_gpio7 + } + #[doc = "0x140 - SYS IOMUX CFG SAIF SYSCFG PADCFG 320: GPIO8"] + #[inline(always)] + pub const fn padcfg_gpio8(&self) -> &PADCFG_GPIO8 { + &self.padcfg_gpio8 + } + #[doc = "0x144 - SYS IOMUX CFG SAIF SYSCFG PADCFG 324: GPIO9"] + #[inline(always)] + pub const fn padcfg_gpio9(&self) -> &PADCFG_GPIO9 { + &self.padcfg_gpio9 + } + #[doc = "0x148 - SYS IOMUX CFG SAIF SYSCFG PADCFG 328: GPIO10"] + #[inline(always)] + pub const fn padcfg_gpio10(&self) -> &PADCFG_GPIO10 { + &self.padcfg_gpio10 + } + #[doc = "0x14c - SYS IOMUX CFG SAIF SYSCFG PADCFG 332: GPIO11"] + #[inline(always)] + pub const fn padcfg_gpio11(&self) -> &PADCFG_GPIO11 { + &self.padcfg_gpio11 + } + #[doc = "0x150 - SYS IOMUX CFG SAIF SYSCFG PADCFG 336: GPIO12"] + #[inline(always)] + pub const fn padcfg_gpio12(&self) -> &PADCFG_GPIO12 { + &self.padcfg_gpio12 + } + #[doc = "0x154 - SYS IOMUX CFG SAIF SYSCFG PADCFG 340: GPIO13"] + #[inline(always)] + pub const fn padcfg_gpio13(&self) -> &PADCFG_GPIO13 { + &self.padcfg_gpio13 + } + #[doc = "0x158 - SYS IOMUX CFG SAIF SYSCFG PADCFG 344: GPIO14"] + #[inline(always)] + pub const fn padcfg_gpio14(&self) -> &PADCFG_GPIO14 { + &self.padcfg_gpio14 + } + #[doc = "0x15c - SYS IOMUX CFG SAIF SYSCFG PADCFG 348: GPIO15"] + #[inline(always)] + pub const fn padcfg_gpio15(&self) -> &PADCFG_GPIO15 { + &self.padcfg_gpio15 + } + #[doc = "0x160 - SYS IOMUX CFG SAIF SYSCFG PADCFG 352: GPIO16"] + #[inline(always)] + pub const fn padcfg_gpio16(&self) -> &PADCFG_GPIO16 { + &self.padcfg_gpio16 + } + #[doc = "0x164 - SYS IOMUX CFG SAIF SYSCFG PADCFG 356: GPIO17"] + #[inline(always)] + pub const fn padcfg_gpio17(&self) -> &PADCFG_GPIO17 { + &self.padcfg_gpio17 + } + #[doc = "0x168 - SYS IOMUX CFG SAIF SYSCFG PADCFG 360: GPIO18"] + #[inline(always)] + pub const fn padcfg_gpio18(&self) -> &PADCFG_GPIO18 { + &self.padcfg_gpio18 + } + #[doc = "0x16c - SYS IOMUX CFG SAIF SYSCFG PADCFG 364: GPIO19"] + #[inline(always)] + pub const fn padcfg_gpio19(&self) -> &PADCFG_GPIO19 { + &self.padcfg_gpio19 + } + #[doc = "0x170 - SYS IOMUX CFG SAIF SYSCFG PADCFG 368: GPIO20"] + #[inline(always)] + pub const fn padcfg_gpio20(&self) -> &PADCFG_GPIO20 { + &self.padcfg_gpio20 + } + #[doc = "0x174 - SYS IOMUX CFG SAIF SYSCFG PADCFG 372: GPIO21"] + #[inline(always)] + pub const fn padcfg_gpio21(&self) -> &PADCFG_GPIO21 { + &self.padcfg_gpio21 + } + #[doc = "0x178 - SYS IOMUX CFG SAIF SYSCFG PADCFG 376: GPIO22"] + #[inline(always)] + pub const fn padcfg_gpio22(&self) -> &PADCFG_GPIO22 { + &self.padcfg_gpio22 + } + #[doc = "0x17c - SYS IOMUX CFG SAIF SYSCFG PADCFG 380: GPIO23"] + #[inline(always)] + pub const fn padcfg_gpio23(&self) -> &PADCFG_GPIO23 { + &self.padcfg_gpio23 + } + #[doc = "0x180 - SYS IOMUX CFG SAIF SYSCFG PADCFG 384: GPIO24"] + #[inline(always)] + pub const fn padcfg_gpio24(&self) -> &PADCFG_GPIO24 { + &self.padcfg_gpio24 + } + #[doc = "0x184 - SYS IOMUX CFG SAIF SYSCFG PADCFG 388: GPIO25"] + #[inline(always)] + pub const fn padcfg_gpio25(&self) -> &PADCFG_GPIO25 { + &self.padcfg_gpio25 + } + #[doc = "0x188 - SYS IOMUX CFG SAIF SYSCFG PADCFG 392: GPIO26"] + #[inline(always)] + pub const fn padcfg_gpio26(&self) -> &PADCFG_GPIO26 { + &self.padcfg_gpio26 + } + #[doc = "0x18c - SYS IOMUX CFG SAIF SYSCFG PADCFG 396: GPIO27"] + #[inline(always)] + pub const fn padcfg_gpio27(&self) -> &PADCFG_GPIO27 { + &self.padcfg_gpio27 + } + #[doc = "0x190 - SYS IOMUX CFG SAIF SYSCFG PADCFG 400: GPIO28"] + #[inline(always)] + pub const fn padcfg_gpio28(&self) -> &PADCFG_GPIO28 { + &self.padcfg_gpio28 + } + #[doc = "0x194 - SYS IOMUX CFG SAIF SYSCFG PADCFG 404: GPIO29"] + #[inline(always)] + pub const fn padcfg_gpio29(&self) -> &PADCFG_GPIO29 { + &self.padcfg_gpio29 + } + #[doc = "0x198 - SYS IOMUX CFG SAIF SYSCFG PADCFG 408: GPIO30"] + #[inline(always)] + pub const fn padcfg_gpio30(&self) -> &PADCFG_GPIO30 { + &self.padcfg_gpio30 + } + #[doc = "0x19c - SYS IOMUX CFG SAIF SYSCFG PADCFG 412: GPIO31"] + #[inline(always)] + pub const fn padcfg_gpio31(&self) -> &PADCFG_GPIO31 { + &self.padcfg_gpio31 + } + #[doc = "0x1a0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 416: GPIO32"] + #[inline(always)] + pub const fn padcfg_gpio32(&self) -> &PADCFG_GPIO32 { + &self.padcfg_gpio32 + } + #[doc = "0x1a4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 420: GPIO33"] + #[inline(always)] + pub const fn padcfg_gpio33(&self) -> &PADCFG_GPIO33 { + &self.padcfg_gpio33 + } + #[doc = "0x1a8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 424: GPIO34"] + #[inline(always)] + pub const fn padcfg_gpio34(&self) -> &PADCFG_GPIO34 { + &self.padcfg_gpio34 + } + #[doc = "0x1ac - SYS IOMUX CFG SAIF SYSCFG PADCFG 428: GPIO35"] + #[inline(always)] + pub const fn padcfg_gpio35(&self) -> &PADCFG_GPIO35 { + &self.padcfg_gpio35 + } + #[doc = "0x1b0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 432: GPIO36"] + #[inline(always)] + pub const fn padcfg_gpio36(&self) -> &PADCFG_GPIO36 { + &self.padcfg_gpio36 + } + #[doc = "0x1b4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 436: GPIO37"] + #[inline(always)] + pub const fn padcfg_gpio37(&self) -> &PADCFG_GPIO37 { + &self.padcfg_gpio37 + } + #[doc = "0x1b8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 440: GPIO38"] + #[inline(always)] + pub const fn padcfg_gpio38(&self) -> &PADCFG_GPIO38 { + &self.padcfg_gpio38 + } + #[doc = "0x1bc - SYS IOMUX CFG SAIF SYSCFG PADCFG 444: GPIO39"] + #[inline(always)] + pub const fn padcfg_gpio39(&self) -> &PADCFG_GPIO39 { + &self.padcfg_gpio39 + } + #[doc = "0x1c0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 448: GPIO40"] + #[inline(always)] + pub const fn padcfg_gpio40(&self) -> &PADCFG_GPIO40 { + &self.padcfg_gpio40 + } + #[doc = "0x1c4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 452: GPIO41"] + #[inline(always)] + pub const fn padcfg_gpio41(&self) -> &PADCFG_GPIO41 { + &self.padcfg_gpio41 + } + #[doc = "0x1c8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 456: GPIO42"] + #[inline(always)] + pub const fn padcfg_gpio42(&self) -> &PADCFG_GPIO42 { + &self.padcfg_gpio42 + } + #[doc = "0x1cc - SYS IOMUX CFG SAIF SYSCFG PADCFG 460: GPIO43"] + #[inline(always)] + pub const fn padcfg_gpio43(&self) -> &PADCFG_GPIO43 { + &self.padcfg_gpio43 + } + #[doc = "0x1d0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 464: GPIO44"] + #[inline(always)] + pub const fn padcfg_gpio44(&self) -> &PADCFG_GPIO44 { + &self.padcfg_gpio44 + } + #[doc = "0x1d4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 468: GPIO45"] + #[inline(always)] + pub const fn padcfg_gpio45(&self) -> &PADCFG_GPIO45 { + &self.padcfg_gpio45 + } + #[doc = "0x1d8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 472: GPIO46"] + #[inline(always)] + pub const fn padcfg_gpio46(&self) -> &PADCFG_GPIO46 { + &self.padcfg_gpio46 + } + #[doc = "0x1dc - SYS IOMUX CFG SAIF SYSCFG PADCFG 476: GPIO47"] + #[inline(always)] + pub const fn padcfg_gpio47(&self) -> &PADCFG_GPIO47 { + &self.padcfg_gpio47 + } + #[doc = "0x1e0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 480: GPIO48"] + #[inline(always)] + pub const fn padcfg_gpio48(&self) -> &PADCFG_GPIO48 { + &self.padcfg_gpio48 + } + #[doc = "0x1e4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 484: GPIO49"] + #[inline(always)] + pub const fn padcfg_gpio49(&self) -> &PADCFG_GPIO49 { + &self.padcfg_gpio49 + } + #[doc = "0x1e8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 488: GPIO50"] + #[inline(always)] + pub const fn padcfg_gpio50(&self) -> &PADCFG_GPIO50 { + &self.padcfg_gpio50 + } + #[doc = "0x1ec - SYS IOMUX CFG SAIF SYSCFG PADCFG 492: GPIO51"] + #[inline(always)] + pub const fn padcfg_gpio51(&self) -> &PADCFG_GPIO51 { + &self.padcfg_gpio51 + } + #[doc = "0x1f0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 496: GPIO52"] + #[inline(always)] + pub const fn padcfg_gpio52(&self) -> &PADCFG_GPIO52 { + &self.padcfg_gpio52 + } + #[doc = "0x1f4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 500: GPIO53"] + #[inline(always)] + pub const fn padcfg_gpio53(&self) -> &PADCFG_GPIO53 { + &self.padcfg_gpio53 + } + #[doc = "0x1f8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 504: GPIO54"] + #[inline(always)] + pub const fn padcfg_gpio54(&self) -> &PADCFG_GPIO54 { + &self.padcfg_gpio54 + } + #[doc = "0x1fc - SYS IOMUX CFG SAIF SYSCFG PADCFG 508: GPIO55"] + #[inline(always)] + pub const fn padcfg_gpio55(&self) -> &PADCFG_GPIO55 { + &self.padcfg_gpio55 + } + #[doc = "0x200 - SYS IOMUX CFG SAIF SYSCFG PADCFG 512: GPIO56"] + #[inline(always)] + pub const fn padcfg_gpio56(&self) -> &PADCFG_GPIO56 { + &self.padcfg_gpio56 + } + #[doc = "0x204 - SYS IOMUX CFG SAIF SYSCFG PADCFG 516: GPIO57"] + #[inline(always)] + pub const fn padcfg_gpio57(&self) -> &PADCFG_GPIO57 { + &self.padcfg_gpio57 + } + #[doc = "0x208 - SYS IOMUX CFG SAIF SYSCFG PADCFG 520: GPIO58"] + #[inline(always)] + pub const fn padcfg_gpio58(&self) -> &PADCFG_GPIO58 { + &self.padcfg_gpio58 + } + #[doc = "0x20c - SYS IOMUX CFG SAIF SYSCFG PADCFG 524: GPIO59"] + #[inline(always)] + pub const fn padcfg_gpio59(&self) -> &PADCFG_GPIO59 { + &self.padcfg_gpio59 + } + #[doc = "0x210 - SYS IOMUX CFG SAIF SYSCFG PADCFG 528: GPIO60"] + #[inline(always)] + pub const fn padcfg_gpio60(&self) -> &PADCFG_GPIO60 { + &self.padcfg_gpio60 + } + #[doc = "0x214 - SYS IOMUX CFG SAIF SYSCFG PADCFG 532: GPIO61"] + #[inline(always)] + pub const fn padcfg_gpio61(&self) -> &PADCFG_GPIO61 { + &self.padcfg_gpio61 + } + #[doc = "0x218 - SYS IOMUX CFG SAIF SYSCFG PADCFG 536: GPIO62"] + #[inline(always)] + pub const fn padcfg_gpio62(&self) -> &PADCFG_GPIO62 { + &self.padcfg_gpio62 + } + #[doc = "0x21c - SYS IOMUX CFG SAIF SYSCFG PADCFG 540: GPIO63"] + #[inline(always)] + pub const fn padcfg_gpio63(&self) -> &PADCFG_GPIO63 { + &self.padcfg_gpio63 + } + #[doc = "0x220 - SYS IOMUX CFG SAIF SYSCFG PADCFG 544: SD0_CLK"] + #[inline(always)] + pub const fn padcfg_sd0_clk(&self) -> &PADCFG_SD0_CLK { + &self.padcfg_sd0_clk + } + #[doc = "0x224 - SYS IOMUX CFG SAIF SYSCFG PADCFG 548: SD0_CMD"] + #[inline(always)] + pub const fn padcfg_sd0_cmd(&self) -> &PADCFG_SD0_CMD { + &self.padcfg_sd0_cmd + } + #[doc = "0x228 - SYS IOMUX CFG SAIF SYSCFG PADCFG 552: SD0_DATA0"] + #[inline(always)] + pub const fn padcfg_sd0_data0(&self) -> &PADCFG_SD0_DATA0 { + &self.padcfg_sd0_data0 + } + #[doc = "0x238 - SYS IOMUX CFG SAIF SYSCFG PADCFG 568: SD0_DATA1"] + #[inline(always)] + pub const fn padcfg_sd0_data1(&self) -> &PADCFG_SD0_DATA1 { + &self.padcfg_sd0_data1 } #[doc = "0x248 - SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_STRB"] #[inline(always)] pub const fn padcfg_sd0_strb(&self) -> &PADCFG_SD0_STRB { - unsafe { &*(self as *const Self).cast::().add(584usize).cast() } + unsafe { &*(self as *const Self).cast::().add(584).cast() } } #[doc = "0x248 - SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_DATA2"] #[inline(always)] pub const fn padcfg_sd0_data2(&self) -> &PADCFG_SD0_DATA2 { - unsafe { &*(self as *const Self).cast::().add(584usize).cast() } + unsafe { &*(self as *const Self).cast::().add(584).cast() } + } + #[doc = "0x258 - SYS IOMUX CFG SAIF SYSCFG PADCFG 600: SD0_DATA3"] + #[inline(always)] + pub const fn padcfg_sd0_data3(&self) -> &PADCFG_SD0_DATA3 { + &self.padcfg_sd0_data3 + } + #[doc = "0x268 - SYS IOMUX CFG SAIF SYSCFG PADCFG 616: SD0_DATA4"] + #[inline(always)] + pub const fn padcfg_sd0_data4(&self) -> &PADCFG_SD0_DATA4 { + &self.padcfg_sd0_data4 + } + #[doc = "0x278 - SYS IOMUX CFG SAIF SYSCFG PADCFG 632: SD0_DATA5"] + #[inline(always)] + pub const fn padcfg_sd0_data5(&self) -> &PADCFG_SD0_DATA5 { + &self.padcfg_sd0_data5 + } + #[doc = "0x284 - SYS IOMUX CFG SAIF SYSCFG PADCFG 644: QSPI_SCLK"] + #[inline(always)] + pub const fn padcfg_qspi_sclk(&self) -> &PADCFG_QSPI_SCLK { + &self.padcfg_qspi_sclk } #[doc = "0x288 - SYS IOMUX CFG SAIF SYSCFG PADCFG 648: QSPI_CSN0"] #[inline(always)] pub const fn padcfg_qspi_csn0(&self) -> &PADCFG_QSPI_CSN0 { - unsafe { &*(self as *const Self).cast::().add(648usize).cast() } + unsafe { &*(self as *const Self).cast::().add(648).cast() } } #[doc = "0x288 - SYS IOMUX CFG SAIF SYSCFG PADCFG 648: SD0_DATA6"] #[inline(always)] pub const fn padcfg_sd0_data6(&self) -> &PADCFG_SD0_DATA6 { - unsafe { &*(self as *const Self).cast::().add(648usize).cast() } + unsafe { &*(self as *const Self).cast::().add(648).cast() } + } + #[doc = "0x28c - SYS IOMUX CFG SAIF SYSCFG PADCFG 652: QSPI_DATA0"] + #[inline(always)] + pub const fn padcfg_qspi_data0(&self) -> &PADCFG_QSPI_DATA0 { + &self.padcfg_qspi_data0 + } + #[doc = "0x298 - SYS IOMUX CFG SAIF SYSCFG PADCFG 664: SD0_DATA7"] + #[inline(always)] + pub const fn padcfg_sd0_data7(&self) -> &PADCFG_SD0_DATA7 { + &self.padcfg_sd0_data7 } #[doc = "0x29c - SYS IOMUX CFG SAIF SYSCFG 0"] #[inline(always)] pub const fn func_sel0(&self) -> &FUNC_SEL0 { - unsafe { &*(self as *const Self).cast::().add(668usize).cast() } + unsafe { &*(self as *const Self).cast::().add(668).cast() } } #[doc = "0x29c - SYS IOMUX CFG SAIF SYSCFG PADCFG 668: QSPI_DATA1"] #[inline(always)] pub const fn padcfg_qspi_data1(&self) -> &PADCFG_QSPI_DATA1 { - unsafe { &*(self as *const Self).cast::().add(668usize).cast() } + unsafe { &*(self as *const Self).cast::().add(668).cast() } + } + #[doc = "0x2a0 - SYS IOMUX CFG SAIF SYSCFG 1"] + #[inline(always)] + pub const fn func_sel1(&self) -> &FUNC_SEL1 { + &self.func_sel1 + } + #[doc = "0x2a4 - SYS IOMUX CFG SAIF SYSCFG 2"] + #[inline(always)] + pub const fn func_sel2(&self) -> &FUNC_SEL2 { + &self.func_sel2 + } + #[doc = "0x2a8 - SYS IOMUX CFG SAIF SYSCFG 3"] + #[inline(always)] + pub const fn func_sel3(&self) -> &FUNC_SEL3 { + &self.func_sel3 } #[doc = "0x2ac - SYS IOMUX CFG SAIF SYSCFG 4"] #[inline(always)] pub const fn func_sel4(&self) -> &FUNC_SEL4 { - unsafe { &*(self as *const Self).cast::().add(684usize).cast() } + unsafe { &*(self as *const Self).cast::().add(684).cast() } } #[doc = "0x2ac - SYS IOMUX CFG SAIF SYSCFG PADCFG 684: QSPI_DATA2"] #[inline(always)] pub const fn padcfg_qspi_data2(&self) -> &PADCFG_QSPI_DATA2 { - unsafe { &*(self as *const Self).cast::().add(684usize).cast() } + unsafe { &*(self as *const Self).cast::().add(684).cast() } + } + #[doc = "0x2b0 - SYS IOMUX CFG SAIF SYSCFG 5"] + #[inline(always)] + pub const fn func_sel5(&self) -> &FUNC_SEL5 { + &self.func_sel5 + } + #[doc = "0x2b4 - SYS IOMUX CFG SAIF SYSCFG 6"] + #[inline(always)] + pub const fn func_sel6(&self) -> &FUNC_SEL6 { + &self.func_sel6 + } + #[doc = "0x2bc - SYS IOMUX CFG SAIF SYSCFG PADCFG 700: QSPI_DATA3"] + #[inline(always)] + pub const fn padcfg_qspi_data3(&self) -> &PADCFG_QSPI_DATA3 { + &self.padcfg_qspi_data3 } } -#[doc = "gpo_doen0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 0 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen0`] +#[doc = "gpo_doen0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 0 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen0`] module"] pub type GPO_DOEN0 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 0 DOEN"] pub mod gpo_doen0; -#[doc = "gpo_doen1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 1 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen1`] +#[doc = "gpo_doen1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 1 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen1`] module"] pub type GPO_DOEN1 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 1 DOEN"] pub mod gpo_doen1; -#[doc = "gpo_doen2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 2 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen2`] +#[doc = "gpo_doen2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 2 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen2`] module"] pub type GPO_DOEN2 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 2 DOEN"] pub mod gpo_doen2; -#[doc = "gpo_doen3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 3 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen3`] +#[doc = "gpo_doen3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 3 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen3`] module"] pub type GPO_DOEN3 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 3 DOEN"] pub mod gpo_doen3; -#[doc = "gpo_doen4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 4 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen4`] +#[doc = "gpo_doen4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 4 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen4`] module"] pub type GPO_DOEN4 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 4 DOEN"] pub mod gpo_doen4; -#[doc = "gpo_doen5 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 5 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen5`] +#[doc = "gpo_doen5 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 5 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen5`] module"] pub type GPO_DOEN5 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 5 DOEN"] pub mod gpo_doen5; -#[doc = "gpo_doen6 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 6 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen6`] +#[doc = "gpo_doen6 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 6 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen6`] module"] pub type GPO_DOEN6 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 6 DOEN"] pub mod gpo_doen6; -#[doc = "gpo_doen7 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 7 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen7`] +#[doc = "gpo_doen7 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 7 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen7`] module"] pub type GPO_DOEN7 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 7 DOEN"] pub mod gpo_doen7; -#[doc = "gpo_doen8 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 8 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen8`] +#[doc = "gpo_doen8 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 8 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen8`] module"] pub type GPO_DOEN8 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 8 DOEN"] pub mod gpo_doen8; -#[doc = "gpo_doen9 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 9 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen9`] +#[doc = "gpo_doen9 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 9 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen9`] module"] pub type GPO_DOEN9 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 9 DOEN"] pub mod gpo_doen9; -#[doc = "gpo_doen10 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 10 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen10`] +#[doc = "gpo_doen10 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 10 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen10`] module"] pub type GPO_DOEN10 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 10 DOEN"] pub mod gpo_doen10; -#[doc = "gpo_doen11 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 11 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen11`] +#[doc = "gpo_doen11 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 11 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen11`] module"] pub type GPO_DOEN11 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 11 DOEN"] pub mod gpo_doen11; -#[doc = "gpo_doen12 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 12 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen12`] +#[doc = "gpo_doen12 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 12 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen12`] module"] pub type GPO_DOEN12 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 12 DOEN"] pub mod gpo_doen12; -#[doc = "gpo_doen13 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 13 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen13`] +#[doc = "gpo_doen13 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 13 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen13`] module"] pub type GPO_DOEN13 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 13 DOEN"] pub mod gpo_doen13; -#[doc = "gpo_doen14 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 14 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen14`] +#[doc = "gpo_doen14 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 14 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen14`] module"] pub type GPO_DOEN14 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 14 DOEN"] pub mod gpo_doen14; -#[doc = "gpo_doen15 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 15 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen15`] +#[doc = "gpo_doen15 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 15 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen15`] module"] pub type GPO_DOEN15 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 15 DOEN"] pub mod gpo_doen15; -#[doc = "gpo_dout0_3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 0-3 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout0_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout0_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout0_3`] +#[doc = "gpo_dout0_3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 0-3 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout0_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout0_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout0_3`] module"] pub type GPO_DOUT0_3 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 0-3 DOUT"] pub mod gpo_dout0_3; -#[doc = "gpo_dout4_7 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 4-7 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout4_7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout4_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout4_7`] +#[doc = "gpo_dout4_7 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 4-7 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout4_7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout4_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout4_7`] module"] pub type GPO_DOUT4_7 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 4-7 DOUT"] pub mod gpo_dout4_7; -#[doc = "gpo_dout8_11 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 8-11 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout8_11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout8_11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout8_11`] +#[doc = "gpo_dout8_11 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 8-11 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout8_11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout8_11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout8_11`] module"] pub type GPO_DOUT8_11 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 8-11 DOUT"] pub mod gpo_dout8_11; -#[doc = "gpo_dout12_15 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 12-15 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout12_15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout12_15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout12_15`] +#[doc = "gpo_dout12_15 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 12-15 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout12_15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout12_15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout12_15`] module"] pub type GPO_DOUT12_15 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 12-15 DOUT"] pub mod gpo_dout12_15; -#[doc = "gpo_dout16_19 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 16-19 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout16_19::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout16_19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout16_19`] +#[doc = "gpo_dout16_19 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 16-19 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout16_19::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout16_19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout16_19`] module"] pub type GPO_DOUT16_19 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 16-19 DOUT"] pub mod gpo_dout16_19; -#[doc = "gpo_dout20_23 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 20-23 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout20_23::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout20_23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout20_23`] +#[doc = "gpo_dout20_23 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 20-23 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout20_23::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout20_23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout20_23`] module"] pub type GPO_DOUT20_23 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 20-23 DOUT"] pub mod gpo_dout20_23; -#[doc = "gpo_dout24_27 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 24-27 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout24_27::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout24_27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout24_27`] +#[doc = "gpo_dout24_27 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 24-27 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout24_27::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout24_27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout24_27`] module"] pub type GPO_DOUT24_27 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 24-27 DOUT"] pub mod gpo_dout24_27; -#[doc = "gpo_dout28_31 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 28-31 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout28_31::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout28_31::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout28_31`] +#[doc = "gpo_dout28_31 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 28-31 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout28_31::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout28_31::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout28_31`] module"] pub type GPO_DOUT28_31 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 28-31 DOUT"] pub mod gpo_dout28_31; -#[doc = "gpo_dout32_35 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 32-35 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout32_35::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout32_35::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout32_35`] +#[doc = "gpo_dout32_35 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 32-35 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout32_35::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout32_35::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout32_35`] module"] pub type GPO_DOUT32_35 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 32-35 DOUT"] pub mod gpo_dout32_35; -#[doc = "gpo_dout36_39 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 36-39 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout36_39::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout36_39::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout36_39`] +#[doc = "gpo_dout36_39 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 36-39 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout36_39::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout36_39::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout36_39`] module"] pub type GPO_DOUT36_39 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 36-39 DOUT"] pub mod gpo_dout36_39; -#[doc = "gpo_dout40_43 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 40-43 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout40_43::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout40_43::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout40_43`] +#[doc = "gpo_dout40_43 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 40-43 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout40_43::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout40_43::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout40_43`] module"] pub type GPO_DOUT40_43 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 40-43 DOUT"] pub mod gpo_dout40_43; -#[doc = "gpo_dout44_47 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 44-47 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout44_47::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout44_47::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout44_47`] +#[doc = "gpo_dout44_47 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 44-47 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout44_47::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout44_47::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout44_47`] module"] pub type GPO_DOUT44_47 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 44-47 DOUT"] pub mod gpo_dout44_47; -#[doc = "gpo_dout48_51 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 48-51 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout48_51::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout48_51::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout48_51`] +#[doc = "gpo_dout48_51 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 48-51 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout48_51::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout48_51::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout48_51`] module"] pub type GPO_DOUT48_51 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 48-51 DOUT"] pub mod gpo_dout48_51; -#[doc = "gpo_dout52_55 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 52-55 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout52_55::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout52_55::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout52_55`] +#[doc = "gpo_dout52_55 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 52-55 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout52_55::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout52_55::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout52_55`] module"] pub type GPO_DOUT52_55 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 52-55 DOUT"] pub mod gpo_dout52_55; -#[doc = "gpo_dout56_59 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 56-59 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout56_59::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout56_59::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout56_59`] +#[doc = "gpo_dout56_59 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 56-59 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout56_59::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout56_59::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout56_59`] module"] pub type GPO_DOUT56_59 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 56-59 DOUT"] pub mod gpo_dout56_59; -#[doc = "gpo_dout60_63 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 60-63 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout60_63::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout60_63::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout60_63`] +#[doc = "gpo_dout60_63 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 60-63 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout60_63::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout60_63::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout60_63`] module"] pub type GPO_DOUT60_63 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 60-63 DOUT"] pub mod gpo_dout60_63; -#[doc = "gpi0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 0 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi0`] +#[doc = "gpi0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 0 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi0`] module"] pub type GPI0 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 0 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi0; -#[doc = "gpi4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 4 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi4`] +#[doc = "gpi4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 4 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi4`] module"] pub type GPI4 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 4 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi4; -#[doc = "gpi8 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 8 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi8`] +#[doc = "gpi8 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 8 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi8`] module"] pub type GPI8 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 8 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi8; -#[doc = "gpi12 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 12 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi12`] +#[doc = "gpi12 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 12 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi12`] module"] pub type GPI12 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 12 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi12; -#[doc = "gpi16 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 16 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi16`] +#[doc = "gpi16 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 16 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi16`] module"] pub type GPI16 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 16 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi16; -#[doc = "gpi20 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 20 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi20::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi20`] +#[doc = "gpi20 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 20 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi20::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi20`] module"] pub type GPI20 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 20 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi20; -#[doc = "gpi24 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 24 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi24::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi24`] +#[doc = "gpi24 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 24 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi24::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi24`] module"] pub type GPI24 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 24 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi24; -#[doc = "gpi28 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 28 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi28::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi28`] +#[doc = "gpi28 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 28 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi28::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi28`] module"] pub type GPI28 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 28 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi28; -#[doc = "gpi32 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 32 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi32::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi32`] +#[doc = "gpi32 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 32 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi32::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi32`] module"] pub type GPI32 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 32 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi32; -#[doc = "gpi36 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 36 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi36::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi36`] +#[doc = "gpi36 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 36 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi36::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi36`] module"] pub type GPI36 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 36 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi36; -#[doc = "gpi40 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 40 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi40::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi40`] +#[doc = "gpi40 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 40 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi40::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi40`] module"] pub type GPI40 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 40 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi40; -#[doc = "gpi44 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 44 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi44::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi44`] +#[doc = "gpi44 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 44 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi44::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi44`] module"] pub type GPI44 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 44 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi44; -#[doc = "gpi48 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 48 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi48::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi48`] +#[doc = "gpi48 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 48 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi48::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi48`] module"] pub type GPI48 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 48 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi48; -#[doc = "gpi52 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 52 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi52::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi52`] +#[doc = "gpi52 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 52 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi52::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi52`] module"] pub type GPI52 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 52 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi52; -#[doc = "gpi56 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 56 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi56::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi56`] +#[doc = "gpi56 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 56 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi56::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi56`] module"] pub type GPI56 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 56 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi56; -#[doc = "gpi60 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 60 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi60::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi60`] +#[doc = "gpi60 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 60 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi60::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi60`] module"] pub type GPI60 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 60 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi60; -#[doc = "gpi64 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 64 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi64::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi64`] +#[doc = "gpi64 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 64 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi64::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi64`] module"] pub type GPI64 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 64 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi64; -#[doc = "gpi68 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 68 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi68::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi68`] +#[doc = "gpi68 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 68 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi68::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi68`] module"] pub type GPI68 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 68 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi68; -#[doc = "gpi72 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 72 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi72::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi72::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi72`] +#[doc = "gpi72 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 72 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi72::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi72::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi72`] module"] pub type GPI72 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 72 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi72; -#[doc = "gpi76 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 76 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi76::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi76`] +#[doc = "gpi76 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 76 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi76::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi76`] module"] pub type GPI76 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 76 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi76; -#[doc = "gpi80 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 80 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi80::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi80::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi80`] +#[doc = "gpi80 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 80 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi80::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi80::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi80`] module"] pub type GPI80 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 80 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi80; -#[doc = "gpi84 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 84 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi84::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi84`] +#[doc = "gpi84 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 84 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi84::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi84`] module"] pub type GPI84 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 84 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi84; -#[doc = "gpi88 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 88 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi88::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi88`] +#[doc = "gpi88 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 88 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi88::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi88`] module"] pub type GPI88 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 88 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi88; -#[doc = "ioirq0 (rw) register accessor: Enable GPIO IRQ function\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq0`] +#[doc = "ioirq0 (rw) register accessor: Enable GPIO IRQ function\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq0`] module"] pub type IOIRQ0 = crate::Reg; #[doc = "Enable GPIO IRQ function"] pub mod ioirq0; -#[doc = "ioirq1 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 56: GPIO Interrupt Edge Trigger Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq1`] +#[doc = "ioirq1 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 56: GPIO Interrupt Edge Trigger Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq1`] module"] pub type IOIRQ1 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 56: GPIO Interrupt Edge Trigger Selector"] pub mod ioirq1; -#[doc = "ioirq2 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 57: GPIO Interrupt Edge Trigger Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq2`] +#[doc = "ioirq2 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 57: GPIO Interrupt Edge Trigger Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq2`] module"] pub type IOIRQ2 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 57: GPIO Interrupt Edge Trigger Selector"] pub mod ioirq2; -#[doc = "ioirq3 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 58: GPIO Interrupt Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq3`] +#[doc = "ioirq3 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 58: GPIO Interrupt Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq3`] module"] pub type IOIRQ3 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 58: GPIO Interrupt Clear"] pub mod ioirq3; -#[doc = "ioirq4 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 59: GPIO Interrupt Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq4`] +#[doc = "ioirq4 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 59: GPIO Interrupt Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq4`] module"] pub type IOIRQ4 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 59: GPIO Interrupt Clear"] pub mod ioirq4; -#[doc = "ioirq5 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 60: GPIO Interrupt Both Edge Trigger Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq5`] +#[doc = "ioirq5 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 60: GPIO Interrupt Both Edge Trigger Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq5`] module"] pub type IOIRQ5 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 60: GPIO Interrupt Both Edge Trigger Selector"] pub mod ioirq5; -#[doc = "ioirq6 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 61: GPIO Interrupt Both Edge Trigger Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq6`] +#[doc = "ioirq6 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 61: GPIO Interrupt Both Edge Trigger Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq6`] module"] pub type IOIRQ6 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 61: GPIO Interrupt Both Edge Trigger Selector"] pub mod ioirq6; -#[doc = "ioirq7 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 62: GPIO Interrupt Edge Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq7`] +#[doc = "ioirq7 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 62: GPIO Interrupt Edge Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq7`] module"] pub type IOIRQ7 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 62: GPIO Interrupt Edge Value"] pub mod ioirq7; -#[doc = "ioirq8 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 63: GPIO Interrupt Edge Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq8`] +#[doc = "ioirq8 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 63: GPIO Interrupt Edge Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq8`] module"] pub type IOIRQ8 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 63: GPIO Interrupt Edge Value"] pub mod ioirq8; -#[doc = "ioirq9 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 64: GPIO Interrupt Edge Mask Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq9`] +#[doc = "ioirq9 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 64: GPIO Interrupt Edge Mask Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq9`] module"] pub type IOIRQ9 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 64: GPIO Interrupt Edge Mask Selector"] pub mod ioirq9; -#[doc = "ioirq10 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 65: GPIO Interrupt Edge Mask Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq10`] +#[doc = "ioirq10 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 65: GPIO Interrupt Edge Mask Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq10`] module"] pub type IOIRQ10 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 65: GPIO Interrupt Edge Mask Selector"] pub mod ioirq10; -#[doc = "ioirq11 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 66: GPIO Register Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq11`] +#[doc = "ioirq11 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 66: GPIO Register Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq11`] module"] pub type IOIRQ11 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 66: GPIO Register Interrupt Status"] pub mod ioirq11; -#[doc = "ioirq12 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 67: GPIO Register Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq12`] +#[doc = "ioirq12 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 67: GPIO Register Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq12`] module"] pub type IOIRQ12 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 67: GPIO Register Interrupt Status"] pub mod ioirq12; -#[doc = "ioirq13 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 68: GPIO Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq13`] +#[doc = "ioirq13 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 68: GPIO Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq13`] module"] pub type IOIRQ13 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 68: GPIO Masked Interrupt Status"] pub mod ioirq13; -#[doc = "ioirq14 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 69: GPIO Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq14`] +#[doc = "ioirq14 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 69: GPIO Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq14`] module"] pub type IOIRQ14 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 69: GPIO Masked Interrupt Status"] pub mod ioirq14; -#[doc = "ioirq15 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 70: GPIO Synchronization Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq15`] +#[doc = "ioirq15 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 70: GPIO Synchronization Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq15`] module"] pub type IOIRQ15 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 70: GPIO Synchronization Status"] pub mod ioirq15; -#[doc = "ioirq16 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 71: GPIO Synchronization Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq16`] +#[doc = "ioirq16 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 71: GPIO Synchronization Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq16`] module"] pub type IOIRQ16 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 71: GPIO Synchronization Status"] pub mod ioirq16; -#[doc = "padcfg_gpio0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 288: GPIO0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio0`] +#[doc = "padcfg_gpio0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 288: GPIO0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio0`] module"] pub type PADCFG_GPIO0 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 288: GPIO0"] pub mod padcfg_gpio0; -#[doc = "padcfg_gpio1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 292: GPIO1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio1`] +#[doc = "padcfg_gpio1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 292: GPIO1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio1`] module"] pub type PADCFG_GPIO1 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 292: GPIO1"] pub mod padcfg_gpio1; -#[doc = "padcfg_gpio2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 296: GPIO2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio2`] +#[doc = "padcfg_gpio2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 296: GPIO2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio2`] module"] pub type PADCFG_GPIO2 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 296: GPIO2"] pub mod padcfg_gpio2; -#[doc = "padcfg_gpio3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 300: GPIO3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio3`] +#[doc = "padcfg_gpio3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 300: GPIO3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio3`] module"] pub type PADCFG_GPIO3 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 300: GPIO3"] pub mod padcfg_gpio3; -#[doc = "padcfg_gpio4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 304: GPIO4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio4`] +#[doc = "padcfg_gpio4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 304: GPIO4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio4`] module"] pub type PADCFG_GPIO4 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 304: GPIO4"] pub mod padcfg_gpio4; -#[doc = "padcfg_gpio5 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 308: GPIO5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio5`] +#[doc = "padcfg_gpio5 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 308: GPIO5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio5`] module"] pub type PADCFG_GPIO5 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 308: GPIO5"] pub mod padcfg_gpio5; -#[doc = "padcfg_gpio6 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 312: GPIO6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio6`] +#[doc = "padcfg_gpio6 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 312: GPIO6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio6`] module"] pub type PADCFG_GPIO6 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 312: GPIO6"] pub mod padcfg_gpio6; -#[doc = "padcfg_gpio7 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 316: GPIO7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio7`] +#[doc = "padcfg_gpio7 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 316: GPIO7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio7`] module"] pub type PADCFG_GPIO7 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 316: GPIO7"] pub mod padcfg_gpio7; -#[doc = "padcfg_gpio8 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 320: GPIO8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio8`] +#[doc = "padcfg_gpio8 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 320: GPIO8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio8`] module"] pub type PADCFG_GPIO8 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 320: GPIO8"] pub mod padcfg_gpio8; -#[doc = "padcfg_gpio9 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 324: GPIO9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio9`] +#[doc = "padcfg_gpio9 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 324: GPIO9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio9`] module"] pub type PADCFG_GPIO9 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 324: GPIO9"] pub mod padcfg_gpio9; -#[doc = "padcfg_gpio10 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 328: GPIO10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio10`] +#[doc = "padcfg_gpio10 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 328: GPIO10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio10`] module"] pub type PADCFG_GPIO10 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 328: GPIO10"] pub mod padcfg_gpio10; -#[doc = "padcfg_gpio11 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 332: GPIO11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio11`] +#[doc = "padcfg_gpio11 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 332: GPIO11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio11`] module"] pub type PADCFG_GPIO11 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 332: GPIO11"] pub mod padcfg_gpio11; -#[doc = "padcfg_gpio12 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 336: GPIO12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio12`] +#[doc = "padcfg_gpio12 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 336: GPIO12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio12`] module"] pub type PADCFG_GPIO12 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 336: GPIO12"] pub mod padcfg_gpio12; -#[doc = "padcfg_gpio13 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 340: GPIO13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio13`] +#[doc = "padcfg_gpio13 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 340: GPIO13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio13`] module"] pub type PADCFG_GPIO13 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 340: GPIO13"] pub mod padcfg_gpio13; -#[doc = "padcfg_gpio14 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 344: GPIO14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio14`] +#[doc = "padcfg_gpio14 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 344: GPIO14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio14`] module"] pub type PADCFG_GPIO14 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 344: GPIO14"] pub mod padcfg_gpio14; -#[doc = "padcfg_gpio15 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 348: GPIO15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio15`] +#[doc = "padcfg_gpio15 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 348: GPIO15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio15`] module"] pub type PADCFG_GPIO15 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 348: GPIO15"] pub mod padcfg_gpio15; -#[doc = "padcfg_gpio16 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 352: GPIO16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio16`] +#[doc = "padcfg_gpio16 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 352: GPIO16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio16`] module"] pub type PADCFG_GPIO16 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 352: GPIO16"] pub mod padcfg_gpio16; -#[doc = "padcfg_gpio17 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 356: GPIO17\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio17::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio17::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio17`] +#[doc = "padcfg_gpio17 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 356: GPIO17\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio17::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio17::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio17`] module"] pub type PADCFG_GPIO17 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 356: GPIO17"] pub mod padcfg_gpio17; -#[doc = "padcfg_gpio18 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 360: GPIO18\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio18::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio18::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio18`] +#[doc = "padcfg_gpio18 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 360: GPIO18\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio18::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio18::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio18`] module"] pub type PADCFG_GPIO18 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 360: GPIO18"] pub mod padcfg_gpio18; -#[doc = "padcfg_gpio19 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 364: GPIO19\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio19::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio19`] +#[doc = "padcfg_gpio19 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 364: GPIO19\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio19::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio19`] module"] pub type PADCFG_GPIO19 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 364: GPIO19"] pub mod padcfg_gpio19; -#[doc = "padcfg_gpio20 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 368: GPIO20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio20::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio20`] +#[doc = "padcfg_gpio20 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 368: GPIO20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio20::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio20`] module"] pub type PADCFG_GPIO20 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 368: GPIO20"] pub mod padcfg_gpio20; -#[doc = "padcfg_gpio21 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 372: GPIO21\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio21::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio21::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio21`] +#[doc = "padcfg_gpio21 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 372: GPIO21\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio21::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio21::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio21`] module"] pub type PADCFG_GPIO21 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 372: GPIO21"] pub mod padcfg_gpio21; -#[doc = "padcfg_gpio22 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 376: GPIO22\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio22::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio22::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio22`] +#[doc = "padcfg_gpio22 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 376: GPIO22\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio22::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio22::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio22`] module"] pub type PADCFG_GPIO22 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 376: GPIO22"] pub mod padcfg_gpio22; -#[doc = "padcfg_gpio23 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 380: GPIO23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio23::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio23`] +#[doc = "padcfg_gpio23 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 380: GPIO23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio23::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio23`] module"] pub type PADCFG_GPIO23 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 380: GPIO23"] pub mod padcfg_gpio23; -#[doc = "padcfg_gpio24 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 384: GPIO24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio24::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio24`] +#[doc = "padcfg_gpio24 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 384: GPIO24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio24::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio24`] module"] pub type PADCFG_GPIO24 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 384: GPIO24"] pub mod padcfg_gpio24; -#[doc = "padcfg_gpio25 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 388: GPIO25\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio25::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio25::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio25`] +#[doc = "padcfg_gpio25 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 388: GPIO25\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio25::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio25::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio25`] module"] pub type PADCFG_GPIO25 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 388: GPIO25"] pub mod padcfg_gpio25; -#[doc = "padcfg_gpio26 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 392: GPIO26\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio26::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio26::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio26`] +#[doc = "padcfg_gpio26 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 392: GPIO26\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio26::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio26::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio26`] module"] pub type PADCFG_GPIO26 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 392: GPIO26"] pub mod padcfg_gpio26; -#[doc = "padcfg_gpio27 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 396: GPIO27\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio27::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio27`] +#[doc = "padcfg_gpio27 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 396: GPIO27\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio27::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio27`] module"] pub type PADCFG_GPIO27 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 396: GPIO27"] pub mod padcfg_gpio27; -#[doc = "padcfg_gpio28 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 400: GPIO28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio28::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio28`] +#[doc = "padcfg_gpio28 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 400: GPIO28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio28::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio28`] module"] pub type PADCFG_GPIO28 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 400: GPIO28"] pub mod padcfg_gpio28; -#[doc = "padcfg_gpio29 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 404: GPIO29\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio29::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio29::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio29`] +#[doc = "padcfg_gpio29 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 404: GPIO29\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio29::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio29::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio29`] module"] pub type PADCFG_GPIO29 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 404: GPIO29"] pub mod padcfg_gpio29; -#[doc = "padcfg_gpio30 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 408: GPIO30\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio30::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio30::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio30`] +#[doc = "padcfg_gpio30 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 408: GPIO30\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio30::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio30::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio30`] module"] pub type PADCFG_GPIO30 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 408: GPIO30"] pub mod padcfg_gpio30; -#[doc = "padcfg_gpio31 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 412: GPIO31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio31::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio31::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio31`] +#[doc = "padcfg_gpio31 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 412: GPIO31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio31::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio31::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio31`] module"] pub type PADCFG_GPIO31 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 412: GPIO31"] pub mod padcfg_gpio31; -#[doc = "padcfg_gpio32 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 416: GPIO32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio32::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio32`] +#[doc = "padcfg_gpio32 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 416: GPIO32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio32::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio32`] module"] pub type PADCFG_GPIO32 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 416: GPIO32"] pub mod padcfg_gpio32; -#[doc = "padcfg_gpio33 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 420: GPIO33\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio33::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio33::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio33`] +#[doc = "padcfg_gpio33 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 420: GPIO33\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio33::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio33::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio33`] module"] pub type PADCFG_GPIO33 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 420: GPIO33"] pub mod padcfg_gpio33; -#[doc = "padcfg_gpio34 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 424: GPIO34\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio34::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio34::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio34`] +#[doc = "padcfg_gpio34 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 424: GPIO34\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio34::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio34::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio34`] module"] pub type PADCFG_GPIO34 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 424: GPIO34"] pub mod padcfg_gpio34; -#[doc = "padcfg_gpio35 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 428: GPIO35\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio35::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio35::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio35`] +#[doc = "padcfg_gpio35 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 428: GPIO35\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio35::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio35::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio35`] module"] pub type PADCFG_GPIO35 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 428: GPIO35"] pub mod padcfg_gpio35; -#[doc = "padcfg_gpio36 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 432: GPIO36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio36::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio36`] +#[doc = "padcfg_gpio36 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 432: GPIO36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio36::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio36`] module"] pub type PADCFG_GPIO36 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 432: GPIO36"] pub mod padcfg_gpio36; -#[doc = "padcfg_gpio37 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 436: GPIO37\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio37::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio37::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio37`] +#[doc = "padcfg_gpio37 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 436: GPIO37\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio37::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio37::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio37`] module"] pub type PADCFG_GPIO37 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 436: GPIO37"] pub mod padcfg_gpio37; -#[doc = "padcfg_gpio38 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 440: GPIO38\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio38::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio38::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio38`] +#[doc = "padcfg_gpio38 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 440: GPIO38\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio38::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio38::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio38`] module"] pub type PADCFG_GPIO38 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 440: GPIO38"] pub mod padcfg_gpio38; -#[doc = "padcfg_gpio39 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 444: GPIO39\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio39::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio39::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio39`] +#[doc = "padcfg_gpio39 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 444: GPIO39\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio39::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio39::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio39`] module"] pub type PADCFG_GPIO39 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 444: GPIO39"] pub mod padcfg_gpio39; -#[doc = "padcfg_gpio40 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 448: GPIO40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio40::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio40`] +#[doc = "padcfg_gpio40 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 448: GPIO40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio40::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio40`] module"] pub type PADCFG_GPIO40 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 448: GPIO40"] pub mod padcfg_gpio40; -#[doc = "padcfg_gpio41 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 452: GPIO41\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio41::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio41::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio41`] +#[doc = "padcfg_gpio41 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 452: GPIO41\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio41::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio41::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio41`] module"] pub type PADCFG_GPIO41 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 452: GPIO41"] pub mod padcfg_gpio41; -#[doc = "padcfg_gpio42 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 456: GPIO42\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio42::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio42::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio42`] +#[doc = "padcfg_gpio42 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 456: GPIO42\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio42::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio42::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio42`] module"] pub type PADCFG_GPIO42 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 456: GPIO42"] pub mod padcfg_gpio42; -#[doc = "padcfg_gpio43 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 460: GPIO43\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio43::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio43::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio43`] +#[doc = "padcfg_gpio43 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 460: GPIO43\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio43::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio43::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio43`] module"] pub type PADCFG_GPIO43 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 460: GPIO43"] pub mod padcfg_gpio43; -#[doc = "padcfg_gpio44 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 464: GPIO44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio44::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio44`] +#[doc = "padcfg_gpio44 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 464: GPIO44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio44::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio44`] module"] pub type PADCFG_GPIO44 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 464: GPIO44"] pub mod padcfg_gpio44; -#[doc = "padcfg_gpio45 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 468: GPIO45\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio45::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio45::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio45`] +#[doc = "padcfg_gpio45 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 468: GPIO45\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio45::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio45::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio45`] module"] pub type PADCFG_GPIO45 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 468: GPIO45"] pub mod padcfg_gpio45; -#[doc = "padcfg_gpio46 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 472: GPIO46\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio46::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio46::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio46`] +#[doc = "padcfg_gpio46 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 472: GPIO46\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio46::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio46::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio46`] module"] pub type PADCFG_GPIO46 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 472: GPIO46"] pub mod padcfg_gpio46; -#[doc = "padcfg_gpio47 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 476: GPIO47\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio47::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio47::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio47`] +#[doc = "padcfg_gpio47 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 476: GPIO47\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio47::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio47::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio47`] module"] pub type PADCFG_GPIO47 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 476: GPIO47"] pub mod padcfg_gpio47; -#[doc = "padcfg_gpio48 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 480: GPIO48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio48::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio48`] +#[doc = "padcfg_gpio48 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 480: GPIO48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio48::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio48`] module"] pub type PADCFG_GPIO48 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 480: GPIO48"] pub mod padcfg_gpio48; -#[doc = "padcfg_gpio49 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 484: GPIO49\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio49::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio49::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio49`] +#[doc = "padcfg_gpio49 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 484: GPIO49\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio49::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio49::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio49`] module"] pub type PADCFG_GPIO49 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 484: GPIO49"] pub mod padcfg_gpio49; -#[doc = "padcfg_gpio50 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 488: GPIO50\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio50::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio50::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio50`] +#[doc = "padcfg_gpio50 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 488: GPIO50\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio50::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio50::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio50`] module"] pub type PADCFG_GPIO50 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 488: GPIO50"] pub mod padcfg_gpio50; -#[doc = "padcfg_gpio51 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 492: GPIO51\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio51::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio51::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio51`] +#[doc = "padcfg_gpio51 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 492: GPIO51\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio51::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio51::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio51`] module"] pub type PADCFG_GPIO51 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 492: GPIO51"] pub mod padcfg_gpio51; -#[doc = "padcfg_gpio52 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 496: GPIO52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio52::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio52`] +#[doc = "padcfg_gpio52 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 496: GPIO52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio52::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio52`] module"] pub type PADCFG_GPIO52 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 496: GPIO52"] pub mod padcfg_gpio52; -#[doc = "padcfg_gpio53 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 500: GPIO53\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio53::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio53::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio53`] +#[doc = "padcfg_gpio53 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 500: GPIO53\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio53::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio53::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio53`] module"] pub type PADCFG_GPIO53 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 500: GPIO53"] pub mod padcfg_gpio53; -#[doc = "padcfg_gpio54 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 504: GPIO54\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio54::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio54::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio54`] +#[doc = "padcfg_gpio54 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 504: GPIO54\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio54::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio54::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio54`] module"] pub type PADCFG_GPIO54 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 504: GPIO54"] pub mod padcfg_gpio54; -#[doc = "padcfg_gpio55 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 508: GPIO55\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio55::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio55::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio55`] +#[doc = "padcfg_gpio55 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 508: GPIO55\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio55::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio55::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio55`] module"] pub type PADCFG_GPIO55 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 508: GPIO55"] pub mod padcfg_gpio55; -#[doc = "padcfg_gpio56 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 512: GPIO56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio56::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio56`] +#[doc = "padcfg_gpio56 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 512: GPIO56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio56::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio56`] module"] pub type PADCFG_GPIO56 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 512: GPIO56"] pub mod padcfg_gpio56; -#[doc = "padcfg_gpio57 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 516: GPIO57\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio57::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio57::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio57`] +#[doc = "padcfg_gpio57 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 516: GPIO57\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio57::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio57::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio57`] module"] pub type PADCFG_GPIO57 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 516: GPIO57"] pub mod padcfg_gpio57; -#[doc = "padcfg_gpio58 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 520: GPIO58\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio58::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio58::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio58`] +#[doc = "padcfg_gpio58 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 520: GPIO58\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio58::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio58::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio58`] module"] pub type PADCFG_GPIO58 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 520: GPIO58"] pub mod padcfg_gpio58; -#[doc = "padcfg_gpio59 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 524: GPIO59\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio59::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio59::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio59`] +#[doc = "padcfg_gpio59 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 524: GPIO59\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio59::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio59::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio59`] module"] pub type PADCFG_GPIO59 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 524: GPIO59"] pub mod padcfg_gpio59; -#[doc = "padcfg_gpio60 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 528: GPIO60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio60::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio60`] +#[doc = "padcfg_gpio60 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 528: GPIO60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio60::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio60`] module"] pub type PADCFG_GPIO60 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 528: GPIO60"] pub mod padcfg_gpio60; -#[doc = "padcfg_gpio61 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 532: GPIO61\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio61::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio61::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio61`] +#[doc = "padcfg_gpio61 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 532: GPIO61\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio61::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio61::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio61`] module"] pub type PADCFG_GPIO61 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 532: GPIO61"] pub mod padcfg_gpio61; -#[doc = "padcfg_gpio62 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 536: GPIO62\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio62::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio62::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio62`] +#[doc = "padcfg_gpio62 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 536: GPIO62\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio62::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio62::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio62`] module"] pub type PADCFG_GPIO62 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 536: GPIO62"] pub mod padcfg_gpio62; -#[doc = "padcfg_gpio63 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 540: GPIO63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio63::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio63::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio63`] +#[doc = "padcfg_gpio63 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 540: GPIO63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio63::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio63::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio63`] module"] pub type PADCFG_GPIO63 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 540: GPIO63"] pub mod padcfg_gpio63; -#[doc = "padcfg_sd0_clk (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 544: SD0_CLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_clk`] +#[doc = "padcfg_sd0_clk (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 544: SD0_CLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_clk`] module"] pub type PADCFG_SD0_CLK = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 544: SD0_CLK"] pub mod padcfg_sd0_clk; -#[doc = "padcfg_sd0_cmd (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 548: SD0_CMD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_cmd`] +#[doc = "padcfg_sd0_cmd (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 548: SD0_CMD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_cmd`] module"] pub type PADCFG_SD0_CMD = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 548: SD0_CMD"] pub mod padcfg_sd0_cmd; -#[doc = "padcfg_sd0_data0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 552: SD0_DATA0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_data0`] +#[doc = "padcfg_sd0_data0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 552: SD0_DATA0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_data0`] module"] pub type PADCFG_SD0_DATA0 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 552: SD0_DATA0"] pub mod padcfg_sd0_data0; -#[doc = "padcfg_sd0_data1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 568: SD0_DATA1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_data1`] +#[doc = "padcfg_sd0_data1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 568: SD0_DATA1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_data1`] module"] pub type PADCFG_SD0_DATA1 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 568: SD0_DATA1"] pub mod padcfg_sd0_data1; -#[doc = "padcfg_sd0_data2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_DATA2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_data2`] +#[doc = "padcfg_sd0_data2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_DATA2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_data2`] module"] pub type PADCFG_SD0_DATA2 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_DATA2"] pub mod padcfg_sd0_data2; -#[doc = "padcfg_sd0_data3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 600: SD0_DATA3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_data3`] +#[doc = "padcfg_sd0_data3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 600: SD0_DATA3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_data3`] module"] pub type PADCFG_SD0_DATA3 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 600: SD0_DATA3"] pub mod padcfg_sd0_data3; -#[doc = "padcfg_sd0_data4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 616: SD0_DATA4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_data4`] +#[doc = "padcfg_sd0_data4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 616: SD0_DATA4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_data4`] module"] pub type PADCFG_SD0_DATA4 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 616: SD0_DATA4"] pub mod padcfg_sd0_data4; -#[doc = "padcfg_sd0_data5 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 632: SD0_DATA5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_data5`] +#[doc = "padcfg_sd0_data5 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 632: SD0_DATA5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_data5`] module"] pub type PADCFG_SD0_DATA5 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 632: SD0_DATA5"] pub mod padcfg_sd0_data5; -#[doc = "padcfg_sd0_data6 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 648: SD0_DATA6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_data6`] +#[doc = "padcfg_sd0_data6 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 648: SD0_DATA6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_data6`] module"] pub type PADCFG_SD0_DATA6 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 648: SD0_DATA6"] pub mod padcfg_sd0_data6; -#[doc = "padcfg_sd0_data7 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 664: SD0_DATA7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_data7`] +#[doc = "padcfg_sd0_data7 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 664: SD0_DATA7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_data7`] module"] pub type PADCFG_SD0_DATA7 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 664: SD0_DATA7"] pub mod padcfg_sd0_data7; -#[doc = "padcfg_sd0_strb (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_STRB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_strb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_strb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_strb`] +#[doc = "padcfg_sd0_strb (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_STRB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_strb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_strb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_strb`] module"] pub type PADCFG_SD0_STRB = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_STRB"] pub mod padcfg_sd0_strb; -#[doc = "padcfg_gmac1_mdc_syscon (rw) register accessor: GPIO GMAC1 MDC Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_mdc_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_mdc_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_mdc_syscon`] +#[doc = "padcfg_gmac1_mdc_syscon (rw) register accessor: GPIO GMAC1 MDC Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_mdc_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_mdc_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_mdc_syscon`] module"] pub type PADCFG_GMAC1_MDC_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 MDC Pad Configuration"] pub mod padcfg_gmac1_mdc_syscon; -#[doc = "padcfg_gmac1_mdio_syscon (rw) register accessor: GPIO GMAC1 MDIO Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_mdio_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_mdio_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_mdio_syscon`] +#[doc = "padcfg_gmac1_mdio_syscon (rw) register accessor: GPIO GMAC1 MDIO Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_mdio_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_mdio_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_mdio_syscon`] module"] pub type PADCFG_GMAC1_MDIO_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 MDIO Pad Configuration"] pub mod padcfg_gmac1_mdio_syscon; -#[doc = "padcfg_gmac1_rxd0_syscon (rw) register accessor: GPIO GMAC1 RXD0 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxd0_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxd0_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_rxd0_syscon`] +#[doc = "padcfg_gmac1_rxd0_syscon (rw) register accessor: GPIO GMAC1 RXD0 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxd0_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxd0_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_rxd0_syscon`] module"] pub type PADCFG_GMAC1_RXD0_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 RXD0 Pad Configuration"] pub mod padcfg_gmac1_rxd0_syscon; -#[doc = "padcfg_gmac1_rxd1_syscon (rw) register accessor: GPIO GMAC1 RXD1 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxd1_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxd1_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_rxd1_syscon`] +#[doc = "padcfg_gmac1_rxd1_syscon (rw) register accessor: GPIO GMAC1 RXD1 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxd1_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxd1_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_rxd1_syscon`] module"] pub type PADCFG_GMAC1_RXD1_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 RXD1 Pad Configuration"] pub mod padcfg_gmac1_rxd1_syscon; -#[doc = "padcfg_gmac1_rxd2_syscon (rw) register accessor: GPIO GMAC1 RXD2 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxd2_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxd2_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_rxd2_syscon`] +#[doc = "padcfg_gmac1_rxd2_syscon (rw) register accessor: GPIO GMAC1 RXD2 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxd2_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxd2_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_rxd2_syscon`] module"] pub type PADCFG_GMAC1_RXD2_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 RXD2 Pad Configuration"] pub mod padcfg_gmac1_rxd2_syscon; -#[doc = "padcfg_gmac1_rxd3_syscon (rw) register accessor: GPIO GMAC1 RXD3 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxd3_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxd3_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_rxd3_syscon`] +#[doc = "padcfg_gmac1_rxd3_syscon (rw) register accessor: GPIO GMAC1 RXD3 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxd3_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxd3_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_rxd3_syscon`] module"] pub type PADCFG_GMAC1_RXD3_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 RXD3 Pad Configuration"] pub mod padcfg_gmac1_rxd3_syscon; -#[doc = "padcfg_gmac1_rxdv_syscon (rw) register accessor: GPIO GMAC1 RXDV Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxdv_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxdv_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_rxdv_syscon`] +#[doc = "padcfg_gmac1_rxdv_syscon (rw) register accessor: GPIO GMAC1 RXDV Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxdv_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxdv_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_rxdv_syscon`] module"] pub type PADCFG_GMAC1_RXDV_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 RXDV Pad Configuration"] pub mod padcfg_gmac1_rxdv_syscon; -#[doc = "padcfg_gmac1_rxc_syscon (rw) register accessor: GPIO GMAC1 RXC Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxc_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxc_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_rxc_syscon`] +#[doc = "padcfg_gmac1_rxc_syscon (rw) register accessor: GPIO GMAC1 RXC Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxc_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxc_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_rxc_syscon`] module"] pub type PADCFG_GMAC1_RXC_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 RXC Pad Configuration"] pub mod padcfg_gmac1_rxc_syscon; -#[doc = "padcfg_gmac1_txd0_syscon (rw) register accessor: GPIO GMAC1 TXD0 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txd0_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txd0_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_txd0_syscon`] +#[doc = "padcfg_gmac1_txd0_syscon (rw) register accessor: GPIO GMAC1 TXD0 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txd0_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txd0_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_txd0_syscon`] module"] pub type PADCFG_GMAC1_TXD0_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 TXD0 Pad Configuration"] pub mod padcfg_gmac1_txd0_syscon; -#[doc = "padcfg_gmac1_txd1_syscon (rw) register accessor: GPIO GMAC1 TXD1 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txd1_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txd1_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_txd1_syscon`] +#[doc = "padcfg_gmac1_txd1_syscon (rw) register accessor: GPIO GMAC1 TXD1 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txd1_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txd1_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_txd1_syscon`] module"] pub type PADCFG_GMAC1_TXD1_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 TXD1 Pad Configuration"] pub mod padcfg_gmac1_txd1_syscon; -#[doc = "padcfg_gmac1_txd2_syscon (rw) register accessor: GPIO GMAC1 TXD2 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txd2_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txd2_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_txd2_syscon`] +#[doc = "padcfg_gmac1_txd2_syscon (rw) register accessor: GPIO GMAC1 TXD2 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txd2_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txd2_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_txd2_syscon`] module"] pub type PADCFG_GMAC1_TXD2_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 TXD2 Pad Configuration"] pub mod padcfg_gmac1_txd2_syscon; -#[doc = "padcfg_gmac1_txd3_syscon (rw) register accessor: GPIO GMAC1 TXD3 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txd3_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txd3_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_txd3_syscon`] +#[doc = "padcfg_gmac1_txd3_syscon (rw) register accessor: GPIO GMAC1 TXD3 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txd3_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txd3_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_txd3_syscon`] module"] pub type PADCFG_GMAC1_TXD3_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 TXD3 Pad Configuration"] pub mod padcfg_gmac1_txd3_syscon; -#[doc = "padcfg_gmac1_txen_syscon (rw) register accessor: GPIO GMAC1 TXEN Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txen_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txen_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_txen_syscon`] +#[doc = "padcfg_gmac1_txen_syscon (rw) register accessor: GPIO GMAC1 TXEN Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txen_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txen_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_txen_syscon`] module"] pub type PADCFG_GMAC1_TXEN_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 TXEN Pad Configuration"] pub mod padcfg_gmac1_txen_syscon; -#[doc = "padcfg_gmac1_txc_syscon (rw) register accessor: GPIO GMAC1 TXC Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txc_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txc_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_txc_syscon`] +#[doc = "padcfg_gmac1_txc_syscon (rw) register accessor: GPIO GMAC1 TXC Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txc_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txc_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_txc_syscon`] module"] pub type PADCFG_GMAC1_TXC_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 TXC Pad Configuration"] pub mod padcfg_gmac1_txc_syscon; -#[doc = "padcfg_qspi_sclk (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 644: QSPI_SCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_sclk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_sclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_qspi_sclk`] +#[doc = "padcfg_qspi_sclk (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 644: QSPI_SCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_sclk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_sclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_qspi_sclk`] module"] pub type PADCFG_QSPI_SCLK = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 644: QSPI_SCLK"] pub mod padcfg_qspi_sclk; -#[doc = "padcfg_qspi_csn0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 648: QSPI_CSN0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_csn0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_csn0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_qspi_csn0`] +#[doc = "padcfg_qspi_csn0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 648: QSPI_CSN0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_csn0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_csn0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_qspi_csn0`] module"] pub type PADCFG_QSPI_CSN0 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 648: QSPI_CSN0"] pub mod padcfg_qspi_csn0; -#[doc = "padcfg_qspi_data0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 652: QSPI_DATA0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_data0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_data0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_qspi_data0`] +#[doc = "padcfg_qspi_data0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 652: QSPI_DATA0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_data0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_data0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_qspi_data0`] module"] pub type PADCFG_QSPI_DATA0 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 652: QSPI_DATA0"] pub mod padcfg_qspi_data0; -#[doc = "padcfg_qspi_data1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 668: QSPI_DATA1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_data1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_data1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_qspi_data1`] +#[doc = "padcfg_qspi_data1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 668: QSPI_DATA1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_data1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_data1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_qspi_data1`] module"] pub type PADCFG_QSPI_DATA1 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 668: QSPI_DATA1"] pub mod padcfg_qspi_data1; -#[doc = "padcfg_qspi_data2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 684: QSPI_DATA2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_data2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_data2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_qspi_data2`] +#[doc = "padcfg_qspi_data2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 684: QSPI_DATA2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_data2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_data2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_qspi_data2`] module"] pub type PADCFG_QSPI_DATA2 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 684: QSPI_DATA2"] pub mod padcfg_qspi_data2; -#[doc = "padcfg_qspi_data3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 700: QSPI_DATA3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_data3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_data3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_qspi_data3`] +#[doc = "padcfg_qspi_data3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 700: QSPI_DATA3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_data3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_data3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_qspi_data3`] module"] pub type PADCFG_QSPI_DATA3 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 700: QSPI_DATA3"] pub mod padcfg_qspi_data3; -#[doc = "func_sel0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`func_sel0`] +#[doc = "func_sel0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func_sel0`] module"] pub type FUNC_SEL0 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG 0"] pub mod func_sel0; -#[doc = "func_sel1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`func_sel1`] +#[doc = "func_sel1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func_sel1`] module"] pub type FUNC_SEL1 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG 1"] pub mod func_sel1; -#[doc = "func_sel2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`func_sel2`] +#[doc = "func_sel2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func_sel2`] module"] pub type FUNC_SEL2 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG 2"] pub mod func_sel2; -#[doc = "func_sel3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`func_sel3`] +#[doc = "func_sel3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func_sel3`] module"] pub type FUNC_SEL3 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG 3"] pub mod func_sel3; -#[doc = "func_sel4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`func_sel4`] +#[doc = "func_sel4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func_sel4`] module"] pub type FUNC_SEL4 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG 4"] pub mod func_sel4; -#[doc = "func_sel5 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`func_sel5`] +#[doc = "func_sel5 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func_sel5`] module"] pub type FUNC_SEL5 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG 5"] pub mod func_sel5; -#[doc = "func_sel6 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`func_sel6`] +#[doc = "func_sel6 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func_sel6`] module"] pub type FUNC_SEL6 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG 6"] diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel0.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel0.rs index 289f275..ba518ea 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel0.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel0.rs @@ -5,47 +5,47 @@ pub type W = crate::W; #[doc = "Field `pad_gmac1_rxc_func_sel` reader - Function selector of GMAC1_RXC: * Function 0: u0_sys_crg.clk_gmac1_rgmii_rx, * Function 1: u0_sys_crg.clk_gmac1_rmii_ref, * Function 2: None, * Function 3: None"] pub type PAD_GMAC1_RXC_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gmac1_rxc_func_sel` writer - Function selector of GMAC1_RXC: * Function 0: u0_sys_crg.clk_gmac1_rgmii_rx, * Function 1: u0_sys_crg.clk_gmac1_rmii_ref, * Function 2: None, * Function 3: None"] -pub type PAD_GMAC1_RXC_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PAD_GMAC1_RXC_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pad_gpio10_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO10_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio10_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO10_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO10_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio11_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO11_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio11_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO11_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO11_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio12_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO12_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio12_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO12_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO12_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio13_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO13_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio13_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO13_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO13_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio14_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO14_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio14_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO14_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO14_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio15_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO15_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio15_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO15_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO15_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio16_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO16_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio16_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO16_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO16_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio17_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO17_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio17_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO17_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO17_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio18_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO18_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio18_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO18_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO18_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio19_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO19_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio19_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO19_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO19_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:1 - Function selector of GMAC1_RXC: * Function 0: u0_sys_crg.clk_gmac1_rgmii_rx, * Function 1: u0_sys_crg.clk_gmac1_rmii_ref, * Function 2: None, * Function 3: None"] #[inline(always)] @@ -107,70 +107,74 @@ impl W { #[doc = "Bits 0:1 - Function selector of GMAC1_RXC: * Function 0: u0_sys_crg.clk_gmac1_rgmii_rx, * Function 1: u0_sys_crg.clk_gmac1_rmii_ref, * Function 2: None, * Function 3: None"] #[inline(always)] #[must_use] - pub fn pad_gmac1_rxc_func_sel(&mut self) -> PAD_GMAC1_RXC_FUNC_SEL_W { - PAD_GMAC1_RXC_FUNC_SEL_W::new(self) + pub fn pad_gmac1_rxc_func_sel(&mut self) -> PAD_GMAC1_RXC_FUNC_SEL_W { + PAD_GMAC1_RXC_FUNC_SEL_W::new(self, 0) } #[doc = "Bits 2:4 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio10_func_sel(&mut self) -> PAD_GPIO10_FUNC_SEL_W { - PAD_GPIO10_FUNC_SEL_W::new(self) + pub fn pad_gpio10_func_sel(&mut self) -> PAD_GPIO10_FUNC_SEL_W { + PAD_GPIO10_FUNC_SEL_W::new(self, 2) } #[doc = "Bits 5:7 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio11_func_sel(&mut self) -> PAD_GPIO11_FUNC_SEL_W { - PAD_GPIO11_FUNC_SEL_W::new(self) + pub fn pad_gpio11_func_sel(&mut self) -> PAD_GPIO11_FUNC_SEL_W { + PAD_GPIO11_FUNC_SEL_W::new(self, 5) } #[doc = "Bits 8:10 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio12_func_sel(&mut self) -> PAD_GPIO12_FUNC_SEL_W { - PAD_GPIO12_FUNC_SEL_W::new(self) + pub fn pad_gpio12_func_sel(&mut self) -> PAD_GPIO12_FUNC_SEL_W { + PAD_GPIO12_FUNC_SEL_W::new(self, 8) } #[doc = "Bits 11:13 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio13_func_sel(&mut self) -> PAD_GPIO13_FUNC_SEL_W { - PAD_GPIO13_FUNC_SEL_W::new(self) + pub fn pad_gpio13_func_sel(&mut self) -> PAD_GPIO13_FUNC_SEL_W { + PAD_GPIO13_FUNC_SEL_W::new(self, 11) } #[doc = "Bits 14:16 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio14_func_sel(&mut self) -> PAD_GPIO14_FUNC_SEL_W { - PAD_GPIO14_FUNC_SEL_W::new(self) + pub fn pad_gpio14_func_sel(&mut self) -> PAD_GPIO14_FUNC_SEL_W { + PAD_GPIO14_FUNC_SEL_W::new(self, 14) } #[doc = "Bits 17:19 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio15_func_sel(&mut self) -> PAD_GPIO15_FUNC_SEL_W { - PAD_GPIO15_FUNC_SEL_W::new(self) + pub fn pad_gpio15_func_sel(&mut self) -> PAD_GPIO15_FUNC_SEL_W { + PAD_GPIO15_FUNC_SEL_W::new(self, 17) } #[doc = "Bits 20:22 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio16_func_sel(&mut self) -> PAD_GPIO16_FUNC_SEL_W { - PAD_GPIO16_FUNC_SEL_W::new(self) + pub fn pad_gpio16_func_sel(&mut self) -> PAD_GPIO16_FUNC_SEL_W { + PAD_GPIO16_FUNC_SEL_W::new(self, 20) } #[doc = "Bits 23:25 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio17_func_sel(&mut self) -> PAD_GPIO17_FUNC_SEL_W { - PAD_GPIO17_FUNC_SEL_W::new(self) + pub fn pad_gpio17_func_sel(&mut self) -> PAD_GPIO17_FUNC_SEL_W { + PAD_GPIO17_FUNC_SEL_W::new(self, 23) } #[doc = "Bits 26:28 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio18_func_sel(&mut self) -> PAD_GPIO18_FUNC_SEL_W { - PAD_GPIO18_FUNC_SEL_W::new(self) + pub fn pad_gpio18_func_sel(&mut self) -> PAD_GPIO18_FUNC_SEL_W { + PAD_GPIO18_FUNC_SEL_W::new(self, 26) } #[doc = "Bits 29:31 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio19_func_sel(&mut self) -> PAD_GPIO19_FUNC_SEL_W { - PAD_GPIO19_FUNC_SEL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn pad_gpio19_func_sel(&mut self) -> PAD_GPIO19_FUNC_SEL_W { + PAD_GPIO19_FUNC_SEL_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel1.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel1.rs index 6ec694c..cd5a02b 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel1.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel1.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `pad_gpio20_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO20_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio20_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO20_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO20_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio21_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO21_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio21_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO21_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO21_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio22_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO22_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio22_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO22_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO22_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio23_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO23_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio23_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO23_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO23_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio24_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO24_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio24_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO24_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO24_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio25_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO25_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio25_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO25_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO25_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio26_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO26_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio26_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO26_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO26_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio27_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO27_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio27_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO27_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO27_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio28_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO28_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio28_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO28_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO28_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio29_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO29_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio29_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO29_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO29_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:2 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bits 0:2 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio20_func_sel(&mut self) -> PAD_GPIO20_FUNC_SEL_W { - PAD_GPIO20_FUNC_SEL_W::new(self) + pub fn pad_gpio20_func_sel(&mut self) -> PAD_GPIO20_FUNC_SEL_W { + PAD_GPIO20_FUNC_SEL_W::new(self, 0) } #[doc = "Bits 3:5 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio21_func_sel(&mut self) -> PAD_GPIO21_FUNC_SEL_W { - PAD_GPIO21_FUNC_SEL_W::new(self) + pub fn pad_gpio21_func_sel(&mut self) -> PAD_GPIO21_FUNC_SEL_W { + PAD_GPIO21_FUNC_SEL_W::new(self, 3) } #[doc = "Bits 6:8 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio22_func_sel(&mut self) -> PAD_GPIO22_FUNC_SEL_W { - PAD_GPIO22_FUNC_SEL_W::new(self) + pub fn pad_gpio22_func_sel(&mut self) -> PAD_GPIO22_FUNC_SEL_W { + PAD_GPIO22_FUNC_SEL_W::new(self, 6) } #[doc = "Bits 9:11 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio23_func_sel(&mut self) -> PAD_GPIO23_FUNC_SEL_W { - PAD_GPIO23_FUNC_SEL_W::new(self) + pub fn pad_gpio23_func_sel(&mut self) -> PAD_GPIO23_FUNC_SEL_W { + PAD_GPIO23_FUNC_SEL_W::new(self, 9) } #[doc = "Bits 12:14 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio24_func_sel(&mut self) -> PAD_GPIO24_FUNC_SEL_W { - PAD_GPIO24_FUNC_SEL_W::new(self) + pub fn pad_gpio24_func_sel(&mut self) -> PAD_GPIO24_FUNC_SEL_W { + PAD_GPIO24_FUNC_SEL_W::new(self, 12) } #[doc = "Bits 15:17 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio25_func_sel(&mut self) -> PAD_GPIO25_FUNC_SEL_W { - PAD_GPIO25_FUNC_SEL_W::new(self) + pub fn pad_gpio25_func_sel(&mut self) -> PAD_GPIO25_FUNC_SEL_W { + PAD_GPIO25_FUNC_SEL_W::new(self, 15) } #[doc = "Bits 18:20 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio26_func_sel(&mut self) -> PAD_GPIO26_FUNC_SEL_W { - PAD_GPIO26_FUNC_SEL_W::new(self) + pub fn pad_gpio26_func_sel(&mut self) -> PAD_GPIO26_FUNC_SEL_W { + PAD_GPIO26_FUNC_SEL_W::new(self, 18) } #[doc = "Bits 21:23 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio27_func_sel(&mut self) -> PAD_GPIO27_FUNC_SEL_W { - PAD_GPIO27_FUNC_SEL_W::new(self) + pub fn pad_gpio27_func_sel(&mut self) -> PAD_GPIO27_FUNC_SEL_W { + PAD_GPIO27_FUNC_SEL_W::new(self, 21) } #[doc = "Bits 24:26 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio28_func_sel(&mut self) -> PAD_GPIO28_FUNC_SEL_W { - PAD_GPIO28_FUNC_SEL_W::new(self) + pub fn pad_gpio28_func_sel(&mut self) -> PAD_GPIO28_FUNC_SEL_W { + PAD_GPIO28_FUNC_SEL_W::new(self, 24) } #[doc = "Bits 27:29 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio29_func_sel(&mut self) -> PAD_GPIO29_FUNC_SEL_W { - PAD_GPIO29_FUNC_SEL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn pad_gpio29_func_sel(&mut self) -> PAD_GPIO29_FUNC_SEL_W { + PAD_GPIO29_FUNC_SEL_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel2.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel2.rs index e2a9acb..ccc33b3 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel2.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel2.rs @@ -5,47 +5,47 @@ pub type W = crate::W; #[doc = "Field `pad_gpio30_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO30_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio30_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO30_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO30_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio31_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO31_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio31_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO31_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO31_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio32_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO32_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio32_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO32_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO32_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio33_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO33_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio33_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO33_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO33_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio34_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO34_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio34_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO34_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO34_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio35_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO35_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio35_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO35_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO35_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio36_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO36_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio36_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO36_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO36_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio37_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO37_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio37_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO37_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO37_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio38_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO38_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio38_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO38_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO38_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio39_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO39_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio39_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO39_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO39_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio40_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO40_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio40_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO40_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO40_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:2 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] @@ -107,70 +107,74 @@ impl W { #[doc = "Bits 0:2 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio30_func_sel(&mut self) -> PAD_GPIO30_FUNC_SEL_W { - PAD_GPIO30_FUNC_SEL_W::new(self) + pub fn pad_gpio30_func_sel(&mut self) -> PAD_GPIO30_FUNC_SEL_W { + PAD_GPIO30_FUNC_SEL_W::new(self, 0) } #[doc = "Bits 3:5 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio31_func_sel(&mut self) -> PAD_GPIO31_FUNC_SEL_W { - PAD_GPIO31_FUNC_SEL_W::new(self) + pub fn pad_gpio31_func_sel(&mut self) -> PAD_GPIO31_FUNC_SEL_W { + PAD_GPIO31_FUNC_SEL_W::new(self, 3) } #[doc = "Bits 6:8 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio32_func_sel(&mut self) -> PAD_GPIO32_FUNC_SEL_W { - PAD_GPIO32_FUNC_SEL_W::new(self) + pub fn pad_gpio32_func_sel(&mut self) -> PAD_GPIO32_FUNC_SEL_W { + PAD_GPIO32_FUNC_SEL_W::new(self, 6) } #[doc = "Bits 9:11 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio33_func_sel(&mut self) -> PAD_GPIO33_FUNC_SEL_W { - PAD_GPIO33_FUNC_SEL_W::new(self) + pub fn pad_gpio33_func_sel(&mut self) -> PAD_GPIO33_FUNC_SEL_W { + PAD_GPIO33_FUNC_SEL_W::new(self, 9) } #[doc = "Bits 12:14 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio34_func_sel(&mut self) -> PAD_GPIO34_FUNC_SEL_W { - PAD_GPIO34_FUNC_SEL_W::new(self) + pub fn pad_gpio34_func_sel(&mut self) -> PAD_GPIO34_FUNC_SEL_W { + PAD_GPIO34_FUNC_SEL_W::new(self, 12) } #[doc = "Bits 15:17 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio35_func_sel(&mut self) -> PAD_GPIO35_FUNC_SEL_W { - PAD_GPIO35_FUNC_SEL_W::new(self) + pub fn pad_gpio35_func_sel(&mut self) -> PAD_GPIO35_FUNC_SEL_W { + PAD_GPIO35_FUNC_SEL_W::new(self, 15) } #[doc = "Bits 18:20 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio36_func_sel(&mut self) -> PAD_GPIO36_FUNC_SEL_W { - PAD_GPIO36_FUNC_SEL_W::new(self) + pub fn pad_gpio36_func_sel(&mut self) -> PAD_GPIO36_FUNC_SEL_W { + PAD_GPIO36_FUNC_SEL_W::new(self, 18) } #[doc = "Bits 21:23 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio37_func_sel(&mut self) -> PAD_GPIO37_FUNC_SEL_W { - PAD_GPIO37_FUNC_SEL_W::new(self) + pub fn pad_gpio37_func_sel(&mut self) -> PAD_GPIO37_FUNC_SEL_W { + PAD_GPIO37_FUNC_SEL_W::new(self, 21) } #[doc = "Bits 24:26 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio38_func_sel(&mut self) -> PAD_GPIO38_FUNC_SEL_W { - PAD_GPIO38_FUNC_SEL_W::new(self) + pub fn pad_gpio38_func_sel(&mut self) -> PAD_GPIO38_FUNC_SEL_W { + PAD_GPIO38_FUNC_SEL_W::new(self, 24) } #[doc = "Bits 27:29 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio39_func_sel(&mut self) -> PAD_GPIO39_FUNC_SEL_W { - PAD_GPIO39_FUNC_SEL_W::new(self) + pub fn pad_gpio39_func_sel(&mut self) -> PAD_GPIO39_FUNC_SEL_W { + PAD_GPIO39_FUNC_SEL_W::new(self, 27) } #[doc = "Bits 30:32 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio40_func_sel(&mut self) -> PAD_GPIO40_FUNC_SEL_W { - PAD_GPIO40_FUNC_SEL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn pad_gpio40_func_sel(&mut self) -> PAD_GPIO40_FUNC_SEL_W { + PAD_GPIO40_FUNC_SEL_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel3.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel3.rs index bba5823..dea7ae5 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel3.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel3.rs @@ -5,47 +5,47 @@ pub type W = crate::W; #[doc = "Field `pad_gpio41_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO41_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio41_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO41_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO41_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio42_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO42_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio42_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO42_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO42_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio43_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO43_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio43_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO43_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO43_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio44_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO44_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio44_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO44_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO44_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio45_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO45_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio45_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO45_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO45_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio46_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO46_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio46_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO46_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO46_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio47_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO47_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio47_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO47_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO47_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio48_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO48_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio48_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO48_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO48_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio49_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO49_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio49_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO49_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO49_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio50_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO50_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio50_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO50_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO50_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio51_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO51_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio51_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO51_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO51_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:2 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] @@ -107,70 +107,74 @@ impl W { #[doc = "Bits 0:2 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio41_func_sel(&mut self) -> PAD_GPIO41_FUNC_SEL_W { - PAD_GPIO41_FUNC_SEL_W::new(self) + pub fn pad_gpio41_func_sel(&mut self) -> PAD_GPIO41_FUNC_SEL_W { + PAD_GPIO41_FUNC_SEL_W::new(self, 0) } #[doc = "Bits 3:5 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio42_func_sel(&mut self) -> PAD_GPIO42_FUNC_SEL_W { - PAD_GPIO42_FUNC_SEL_W::new(self) + pub fn pad_gpio42_func_sel(&mut self) -> PAD_GPIO42_FUNC_SEL_W { + PAD_GPIO42_FUNC_SEL_W::new(self, 3) } #[doc = "Bits 6:8 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio43_func_sel(&mut self) -> PAD_GPIO43_FUNC_SEL_W { - PAD_GPIO43_FUNC_SEL_W::new(self) + pub fn pad_gpio43_func_sel(&mut self) -> PAD_GPIO43_FUNC_SEL_W { + PAD_GPIO43_FUNC_SEL_W::new(self, 6) } #[doc = "Bits 9:11 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio44_func_sel(&mut self) -> PAD_GPIO44_FUNC_SEL_W { - PAD_GPIO44_FUNC_SEL_W::new(self) + pub fn pad_gpio44_func_sel(&mut self) -> PAD_GPIO44_FUNC_SEL_W { + PAD_GPIO44_FUNC_SEL_W::new(self, 9) } #[doc = "Bits 12:14 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio45_func_sel(&mut self) -> PAD_GPIO45_FUNC_SEL_W { - PAD_GPIO45_FUNC_SEL_W::new(self) + pub fn pad_gpio45_func_sel(&mut self) -> PAD_GPIO45_FUNC_SEL_W { + PAD_GPIO45_FUNC_SEL_W::new(self, 12) } #[doc = "Bits 15:17 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio46_func_sel(&mut self) -> PAD_GPIO46_FUNC_SEL_W { - PAD_GPIO46_FUNC_SEL_W::new(self) + pub fn pad_gpio46_func_sel(&mut self) -> PAD_GPIO46_FUNC_SEL_W { + PAD_GPIO46_FUNC_SEL_W::new(self, 15) } #[doc = "Bits 18:20 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio47_func_sel(&mut self) -> PAD_GPIO47_FUNC_SEL_W { - PAD_GPIO47_FUNC_SEL_W::new(self) + pub fn pad_gpio47_func_sel(&mut self) -> PAD_GPIO47_FUNC_SEL_W { + PAD_GPIO47_FUNC_SEL_W::new(self, 18) } #[doc = "Bits 21:23 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio48_func_sel(&mut self) -> PAD_GPIO48_FUNC_SEL_W { - PAD_GPIO48_FUNC_SEL_W::new(self) + pub fn pad_gpio48_func_sel(&mut self) -> PAD_GPIO48_FUNC_SEL_W { + PAD_GPIO48_FUNC_SEL_W::new(self, 21) } #[doc = "Bits 24:26 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio49_func_sel(&mut self) -> PAD_GPIO49_FUNC_SEL_W { - PAD_GPIO49_FUNC_SEL_W::new(self) + pub fn pad_gpio49_func_sel(&mut self) -> PAD_GPIO49_FUNC_SEL_W { + PAD_GPIO49_FUNC_SEL_W::new(self, 24) } #[doc = "Bits 27:29 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio50_func_sel(&mut self) -> PAD_GPIO50_FUNC_SEL_W { - PAD_GPIO50_FUNC_SEL_W::new(self) + pub fn pad_gpio50_func_sel(&mut self) -> PAD_GPIO50_FUNC_SEL_W { + PAD_GPIO50_FUNC_SEL_W::new(self, 27) } #[doc = "Bits 30:32 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio51_func_sel(&mut self) -> PAD_GPIO51_FUNC_SEL_W { - PAD_GPIO51_FUNC_SEL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn pad_gpio51_func_sel(&mut self) -> PAD_GPIO51_FUNC_SEL_W { + PAD_GPIO51_FUNC_SEL_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel4.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel4.rs index e564c59..4c65a27 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel4.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel4.rs @@ -5,47 +5,47 @@ pub type W = crate::W; #[doc = "Field `pad_gpio52_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO52_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio52_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO52_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PAD_GPIO52_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pad_gpio53_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO53_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio53_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO53_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PAD_GPIO53_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pad_gpio54_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO54_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio54_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO54_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PAD_GPIO54_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pad_gpio56_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO56_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio56_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO56_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO56_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio57_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO57_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio57_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO57_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO57_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio58_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO58_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio58_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO58_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO58_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio59_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO59_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio59_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO59_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO59_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio60_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO60_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio60_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO60_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO60_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio61_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO61_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio61_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO61_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO61_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio62_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO62_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio62_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO62_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO62_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio63_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO63_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio63_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO63_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PAD_GPIO63_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] @@ -107,70 +107,74 @@ impl W { #[doc = "Bits 0:1 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio52_func_sel(&mut self) -> PAD_GPIO52_FUNC_SEL_W { - PAD_GPIO52_FUNC_SEL_W::new(self) + pub fn pad_gpio52_func_sel(&mut self) -> PAD_GPIO52_FUNC_SEL_W { + PAD_GPIO52_FUNC_SEL_W::new(self, 0) } #[doc = "Bits 2:3 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio53_func_sel(&mut self) -> PAD_GPIO53_FUNC_SEL_W { - PAD_GPIO53_FUNC_SEL_W::new(self) + pub fn pad_gpio53_func_sel(&mut self) -> PAD_GPIO53_FUNC_SEL_W { + PAD_GPIO53_FUNC_SEL_W::new(self, 2) } #[doc = "Bits 4:5 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio54_func_sel(&mut self) -> PAD_GPIO54_FUNC_SEL_W { - PAD_GPIO54_FUNC_SEL_W::new(self) + pub fn pad_gpio54_func_sel(&mut self) -> PAD_GPIO54_FUNC_SEL_W { + PAD_GPIO54_FUNC_SEL_W::new(self, 4) } #[doc = "Bits 12:14 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio56_func_sel(&mut self) -> PAD_GPIO56_FUNC_SEL_W { - PAD_GPIO56_FUNC_SEL_W::new(self) + pub fn pad_gpio56_func_sel(&mut self) -> PAD_GPIO56_FUNC_SEL_W { + PAD_GPIO56_FUNC_SEL_W::new(self, 12) } #[doc = "Bits 15:17 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio57_func_sel(&mut self) -> PAD_GPIO57_FUNC_SEL_W { - PAD_GPIO57_FUNC_SEL_W::new(self) + pub fn pad_gpio57_func_sel(&mut self) -> PAD_GPIO57_FUNC_SEL_W { + PAD_GPIO57_FUNC_SEL_W::new(self, 15) } #[doc = "Bits 18:20 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio58_func_sel(&mut self) -> PAD_GPIO58_FUNC_SEL_W { - PAD_GPIO58_FUNC_SEL_W::new(self) + pub fn pad_gpio58_func_sel(&mut self) -> PAD_GPIO58_FUNC_SEL_W { + PAD_GPIO58_FUNC_SEL_W::new(self, 18) } #[doc = "Bits 21:23 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio59_func_sel(&mut self) -> PAD_GPIO59_FUNC_SEL_W { - PAD_GPIO59_FUNC_SEL_W::new(self) + pub fn pad_gpio59_func_sel(&mut self) -> PAD_GPIO59_FUNC_SEL_W { + PAD_GPIO59_FUNC_SEL_W::new(self, 21) } #[doc = "Bits 24:26 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio60_func_sel(&mut self) -> PAD_GPIO60_FUNC_SEL_W { - PAD_GPIO60_FUNC_SEL_W::new(self) + pub fn pad_gpio60_func_sel(&mut self) -> PAD_GPIO60_FUNC_SEL_W { + PAD_GPIO60_FUNC_SEL_W::new(self, 24) } #[doc = "Bits 27:29 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio61_func_sel(&mut self) -> PAD_GPIO61_FUNC_SEL_W { - PAD_GPIO61_FUNC_SEL_W::new(self) + pub fn pad_gpio61_func_sel(&mut self) -> PAD_GPIO61_FUNC_SEL_W { + PAD_GPIO61_FUNC_SEL_W::new(self, 27) } #[doc = "Bits 30:32 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio62_func_sel(&mut self) -> PAD_GPIO62_FUNC_SEL_W { - PAD_GPIO62_FUNC_SEL_W::new(self) + pub fn pad_gpio62_func_sel(&mut self) -> PAD_GPIO62_FUNC_SEL_W { + PAD_GPIO62_FUNC_SEL_W::new(self, 30) } #[doc = "Bits 30:31 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio63_func_sel(&mut self) -> PAD_GPIO63_FUNC_SEL_W { - PAD_GPIO63_FUNC_SEL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn pad_gpio63_func_sel(&mut self) -> PAD_GPIO63_FUNC_SEL_W { + PAD_GPIO63_FUNC_SEL_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel5.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel5.rs index be6fe81..1721cf4 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel5.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel5.rs @@ -5,54 +5,47 @@ pub type W = crate::W; #[doc = "Field `pad_gpio6_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO6_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio6_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO6_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PAD_GPIO6_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pad_gpio7_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO7_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio7_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO7_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO7_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio8_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO8_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio8_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO8_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO8_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio9_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO9_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio9_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO9_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO9_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c0_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c0_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c10_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c10_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c11_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c11_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c1_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c1_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c2_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c2_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c3_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c3_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c4_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c4_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:1 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] @@ -128,84 +121,88 @@ impl W { #[doc = "Bits 0:1 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio6_func_sel(&mut self) -> PAD_GPIO6_FUNC_SEL_W { - PAD_GPIO6_FUNC_SEL_W::new(self) + pub fn pad_gpio6_func_sel(&mut self) -> PAD_GPIO6_FUNC_SEL_W { + PAD_GPIO6_FUNC_SEL_W::new(self, 0) } #[doc = "Bits 3:5 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio7_func_sel(&mut self) -> PAD_GPIO7_FUNC_SEL_W { - PAD_GPIO7_FUNC_SEL_W::new(self) + pub fn pad_gpio7_func_sel(&mut self) -> PAD_GPIO7_FUNC_SEL_W { + PAD_GPIO7_FUNC_SEL_W::new(self, 3) } #[doc = "Bits 6:8 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio8_func_sel(&mut self) -> PAD_GPIO8_FUNC_SEL_W { - PAD_GPIO8_FUNC_SEL_W::new(self) + pub fn pad_gpio8_func_sel(&mut self) -> PAD_GPIO8_FUNC_SEL_W { + PAD_GPIO8_FUNC_SEL_W::new(self, 6) } #[doc = "Bits 9:11 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio9_func_sel(&mut self) -> PAD_GPIO9_FUNC_SEL_W { - PAD_GPIO9_FUNC_SEL_W::new(self) + pub fn pad_gpio9_func_sel(&mut self) -> PAD_GPIO9_FUNC_SEL_W { + PAD_GPIO9_FUNC_SEL_W::new(self, 9) } #[doc = "Bits 11:13 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c0_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_W::new(self, 11) } #[doc = "Bits 14:16 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c10_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_W::new(self, 14) } #[doc = "Bits 17:19 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c11_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_W::new(self, 17) } #[doc = "Bits 20:22 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c1_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_W::new(self, 20) } #[doc = "Bits 23:25 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c2_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_W::new(self, 23) } #[doc = "Bits 26:28 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c3_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_W::new(self, 26) } #[doc = "Bits 29:31 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c4_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel6.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel6.rs index e98f782..508e9f3 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel6.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/func_sel6.rs @@ -5,42 +5,35 @@ pub type W = crate::W; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c5_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c5_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c6_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c6_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c7_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c7_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c8_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c8_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c9_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c9_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_hvalid_c_func_sel` reader - Function Selector of DVP_HSYNC, see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_hvalid_c_func_sel` writer - Function Selector of DVP_HSYNC, see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_vvalid_c_func_sel` reader - Function Selector of DVP_VSYNC, see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_vvalid_c_func_sel` writer - Function Selector of DVP_VSYNC, see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_sys_crg_dvp_clk_func_sel` reader - Function Selector of DVP_CLK, see Function 2 for more information"] pub type U0_SYS_CRG_DVP_CLK_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_sys_crg_dvp_clk_func_sel` writer - Function Selector of DVP_CLK, see Function 2 for more information"] -pub type U0_SYS_CRG_DVP_CLK_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U0_SYS_CRG_DVP_CLK_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:2 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] @@ -103,66 +96,68 @@ impl W { #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c5_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_W::new(self, 0) } #[doc = "Bits 3:5 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c6_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_W::new(self, 3) } #[doc = "Bits 6:8 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c7_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_W::new(self, 6) } #[doc = "Bits 9:11 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c8_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_W::new(self, 9) } #[doc = "Bits 12:14 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c9_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_W::new(self, 12) } #[doc = "Bits 15:17 - Function Selector of DVP_HSYNC, see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_hvalid_c_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_W::new(self, 15) } #[doc = "Bits 18:20 - Function Selector of DVP_VSYNC, see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_vvalid_c_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_W::new(self, 18) } #[doc = "Bits 21:23 - Function Selector of DVP_CLK, see Function 2 for more information"] #[inline(always)] #[must_use] - pub fn u0_sys_crg_dvp_clk_func_sel( - &mut self, - ) -> U0_SYS_CRG_DVP_CLK_FUNC_SEL_W { - U0_SYS_CRG_DVP_CLK_FUNC_SEL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn u0_sys_crg_dvp_clk_func_sel(&mut self) -> U0_SYS_CRG_DVP_CLK_FUNC_SEL_W { + U0_SYS_CRG_DVP_CLK_FUNC_SEL_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi0.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi0.rs index 705d94b..1df2325 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi0.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi0.rs @@ -5,20 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_WAVE511_i_uart_rxsin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_WAVE511_I_UART_RXSIN_CFG_R = crate::FieldReader; #[doc = "Field `u0_WAVE511_i_uart_rxsin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_WAVE511_I_UART_RXSIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_WAVE511_I_UART_RXSIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_can_ctrl_rxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_CAN_CTRL_RXD_CFG_R = crate::FieldReader; #[doc = "Field `u0_can_ctrl_rxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_CAN_CTRL_RXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_CAN_CTRL_RXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_cdn_usb_over_current_n_io_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_CDN_USB_OVER_CURRENT_N_IO_CFG_R = crate::FieldReader; #[doc = "Field `u0_cdn_usb_over_current_n_io_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_CDN_USB_OVER_CURRENT_N_IO_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_CDN_USB_OVER_CURRENT_N_IO_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_cdns_spdif_spdi_fi_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_CDNS_SPDIF_SPDI_FI_CFG_R = crate::FieldReader; #[doc = "Field `u0_cdns_spdif_spdi_fi_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_CDNS_SPDIF_SPDI_FI_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_CDNS_SPDIF_SPDI_FI_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -45,30 +44,34 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_wave511_i_uart_rxsin_cfg(&mut self) -> U0_WAVE511_I_UART_RXSIN_CFG_W { - U0_WAVE511_I_UART_RXSIN_CFG_W::new(self) + pub fn u0_wave511_i_uart_rxsin_cfg(&mut self) -> U0_WAVE511_I_UART_RXSIN_CFG_W { + U0_WAVE511_I_UART_RXSIN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_can_ctrl_rxd_cfg(&mut self) -> U0_CAN_CTRL_RXD_CFG_W { - U0_CAN_CTRL_RXD_CFG_W::new(self) + pub fn u0_can_ctrl_rxd_cfg(&mut self) -> U0_CAN_CTRL_RXD_CFG_W { + U0_CAN_CTRL_RXD_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn u0_cdn_usb_over_current_n_io_cfg( &mut self, - ) -> U0_CDN_USB_OVER_CURRENT_N_IO_CFG_W { - U0_CDN_USB_OVER_CURRENT_N_IO_CFG_W::new(self) + ) -> U0_CDN_USB_OVER_CURRENT_N_IO_CFG_W { + U0_CDN_USB_OVER_CURRENT_N_IO_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_cdns_spdif_spdi_fi_cfg(&mut self) -> U0_CDNS_SPDIF_SPDI_FI_CFG_W { - U0_CDNS_SPDIF_SPDI_FI_CFG_W::new(self) + pub fn u0_cdns_spdif_spdi_fi_cfg(&mut self) -> U0_CDNS_SPDIF_SPDI_FI_CFG_W { + U0_CDNS_SPDIF_SPDI_FI_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi12.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi12.rs index 7e979fb..54b823b 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi12.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi12.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_sdio_card_int_n_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SDIO_CARD_INT_N_CFG_R = crate::FieldReader; #[doc = "Field `u0_sdio_card_int_n_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SDIO_CARD_INT_N_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SDIO_CARD_INT_N_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_sdio_card_write_prt_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SDIO_CARD_WRITE_PRT_CFG_R = crate::FieldReader; #[doc = "Field `u0_sdio_card_write_prt_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SDIO_CARD_WRITE_PRT_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SDIO_CARD_WRITE_PRT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_uart_sin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_UART_SIN_CFG_R = crate::FieldReader; #[doc = "Field `u0_uart_sin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_UART_SIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_UART_SIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_hifi4_jtck_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_HIFI4_JTCK_CFG_R = crate::FieldReader; #[doc = "Field `u0_hifi4_jtck_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_HIFI4_JTCK_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_HIFI4_JTCK_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sdio_card_int_n_cfg(&mut self) -> U0_SDIO_CARD_INT_N_CFG_W { - U0_SDIO_CARD_INT_N_CFG_W::new(self) + pub fn u0_sdio_card_int_n_cfg(&mut self) -> U0_SDIO_CARD_INT_N_CFG_W { + U0_SDIO_CARD_INT_N_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sdio_card_write_prt_cfg(&mut self) -> U0_SDIO_CARD_WRITE_PRT_CFG_W { - U0_SDIO_CARD_WRITE_PRT_CFG_W::new(self) + pub fn u0_sdio_card_write_prt_cfg(&mut self) -> U0_SDIO_CARD_WRITE_PRT_CFG_W { + U0_SDIO_CARD_WRITE_PRT_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_uart_sin_cfg(&mut self) -> U0_UART_SIN_CFG_W { - U0_UART_SIN_CFG_W::new(self) + pub fn u0_uart_sin_cfg(&mut self) -> U0_UART_SIN_CFG_W { + U0_UART_SIN_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_hifi4_jtck_cfg(&mut self) -> U0_HIFI4_JTCK_CFG_W { - U0_HIFI4_JTCK_CFG_W::new(self) + pub fn u0_hifi4_jtck_cfg(&mut self) -> U0_HIFI4_JTCK_CFG_W { + U0_HIFI4_JTCK_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi16.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi16.rs index 117acfd..6b6c6f6 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi16.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi16.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_hifi4_jtdi_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_HIFI4_JTDI_CFG_R = crate::FieldReader; #[doc = "Field `u0_hifi4_jtdi_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_HIFI4_JTDI_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_HIFI4_JTDI_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_hifi4_jtms_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_HIFI4_JTMS_CFG_R = crate::FieldReader; #[doc = "Field `u0_hifi4_jtms_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_HIFI4_JTMS_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_HIFI4_JTMS_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_hifi4_jtrstn_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_HIFI4_JTRSTN_CFG_R = crate::FieldReader; #[doc = "Field `u0_hifi4_jtrstn_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_HIFI4_JTRSTN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_HIFI4_JTRSTN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_jtag_certification_tdi_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_JTAG_CERTIFICATION_TDI_CFG_R = crate::FieldReader; #[doc = "Field `u0_jtag_certification_tdi_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_JTAG_CERTIFICATION_TDI_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_JTAG_CERTIFICATION_TDI_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,30 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_hifi4_jtdi_cfg(&mut self) -> U0_HIFI4_JTDI_CFG_W { - U0_HIFI4_JTDI_CFG_W::new(self) + pub fn u0_hifi4_jtdi_cfg(&mut self) -> U0_HIFI4_JTDI_CFG_W { + U0_HIFI4_JTDI_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_hifi4_jtms_cfg(&mut self) -> U0_HIFI4_JTMS_CFG_W { - U0_HIFI4_JTMS_CFG_W::new(self) + pub fn u0_hifi4_jtms_cfg(&mut self) -> U0_HIFI4_JTMS_CFG_W { + U0_HIFI4_JTMS_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_hifi4_jtrstn_cfg(&mut self) -> U0_HIFI4_JTRSTN_CFG_W { - U0_HIFI4_JTRSTN_CFG_W::new(self) + pub fn u0_hifi4_jtrstn_cfg(&mut self) -> U0_HIFI4_JTRSTN_CFG_W { + U0_HIFI4_JTRSTN_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_jtag_certification_tdi_cfg( - &mut self, - ) -> U0_JTAG_CERTIFICATION_TDI_CFG_W { - U0_JTAG_CERTIFICATION_TDI_CFG_W::new(self) + pub fn u0_jtag_certification_tdi_cfg(&mut self) -> U0_JTAG_CERTIFICATION_TDI_CFG_W { + U0_JTAG_CERTIFICATION_TDI_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi20.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi20.rs index 52b33cc..4b86ebd 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi20.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi20.rs @@ -5,20 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_jtag_certification_tms_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_JTAG_CERTIFICATION_TMS_CFG_R = crate::FieldReader; #[doc = "Field `u0_jtag_certification_tms_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_JTAG_CERTIFICATION_TMS_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_JTAG_CERTIFICATION_TMS_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_pdm_4mic_dmic0_din_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_PDM_4MIC_DMIC0_DIN_CFG_R = crate::FieldReader; #[doc = "Field `u0_pdm_4mic_dmic0_din_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_PDM_4MIC_DMIC0_DIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_PDM_4MIC_DMIC0_DIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_pdm_4mic_dmic1_din_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_PDM_4MIC_DMIC1_DIN_CFG_R = crate::FieldReader; #[doc = "Field `u0_pdm_4mic_dmic1_din_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_PDM_4MIC_DMIC1_DIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_PDM_4MIC_DMIC1_DIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_saif_audio_sdin_mux_i2srx_ext_sdin0_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0_CFG_R = crate::FieldReader; #[doc = "Field `u0_saif_audio_sdin_mux_i2srx_ext_sdin0_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -47,32 +46,34 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_jtag_certification_tms_cfg( - &mut self, - ) -> U0_JTAG_CERTIFICATION_TMS_CFG_W { - U0_JTAG_CERTIFICATION_TMS_CFG_W::new(self) + pub fn u0_jtag_certification_tms_cfg(&mut self) -> U0_JTAG_CERTIFICATION_TMS_CFG_W { + U0_JTAG_CERTIFICATION_TMS_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_pdm_4mic_dmic0_din_cfg(&mut self) -> U0_PDM_4MIC_DMIC0_DIN_CFG_W { - U0_PDM_4MIC_DMIC0_DIN_CFG_W::new(self) + pub fn u0_pdm_4mic_dmic0_din_cfg(&mut self) -> U0_PDM_4MIC_DMIC0_DIN_CFG_W { + U0_PDM_4MIC_DMIC0_DIN_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_pdm_4mic_dmic1_din_cfg(&mut self) -> U0_PDM_4MIC_DMIC1_DIN_CFG_W { - U0_PDM_4MIC_DMIC1_DIN_CFG_W::new(self) + pub fn u0_pdm_4mic_dmic1_din_cfg(&mut self) -> U0_PDM_4MIC_DMIC1_DIN_CFG_W { + U0_PDM_4MIC_DMIC1_DIN_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn u0_saif_audio_sdin_mux_i2srx_ext_sdin0_cfg( &mut self, - ) -> U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0_CFG_W { - U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0_CFG_W::new(self) + ) -> U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0_CFG_W { + U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi24.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi24.rs index 2a9380f..8e75e01 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi24.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi24.rs @@ -5,21 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_saif_audio_sdin_mux_i2srx_ext_sdin1_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1_CFG_R = crate::FieldReader; #[doc = "Field `u0_saif_audio_sdin_mux_i2srx_ext_sdin1_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_saif_audio_sdin_mux_i2srx_ext_sdin2_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2_CFG_R = crate::FieldReader; #[doc = "Field `u0_saif_audio_sdin_mux_i2srx_ext_sdin2_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_ssp_spi_sspclkin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SSP_SPI_SSPCLKIN_CFG_R = crate::FieldReader; #[doc = "Field `u0_ssp_spi_sspclkin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SSP_SPI_SSPCLKIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SSP_SPI_SSPCLKIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_ssp_spi_sspfssin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SSP_SPI_SSPFSSIN_CFG_R = crate::FieldReader; #[doc = "Field `u0_ssp_spi_sspfssin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SSP_SPI_SSPFSSIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SSP_SPI_SSPFSSIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -52,30 +50,34 @@ impl W { #[must_use] pub fn u0_saif_audio_sdin_mux_i2srx_ext_sdin1_cfg( &mut self, - ) -> U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1_CFG_W { - U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1_CFG_W::new(self) + ) -> U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1_CFG_W { + U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn u0_saif_audio_sdin_mux_i2srx_ext_sdin2_cfg( &mut self, - ) -> U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2_CFG_W { - U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2_CFG_W::new(self) + ) -> U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2_CFG_W { + U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_ssp_spi_sspclkin_cfg(&mut self) -> U0_SSP_SPI_SSPCLKIN_CFG_W { - U0_SSP_SPI_SSPCLKIN_CFG_W::new(self) + pub fn u0_ssp_spi_sspclkin_cfg(&mut self) -> U0_SSP_SPI_SSPCLKIN_CFG_W { + U0_SSP_SPI_SSPCLKIN_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_ssp_spi_sspfssin_cfg(&mut self) -> U0_SSP_SPI_SSPFSSIN_CFG_W { - U0_SSP_SPI_SSPFSSIN_CFG_W::new(self) + pub fn u0_ssp_spi_sspfssin_cfg(&mut self) -> U0_SSP_SPI_SSPFSSIN_CFG_W { + U0_SSP_SPI_SSPFSSIN_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi28.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi28.rs index 7383675..1de1e81 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi28.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi28.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_ssp_spi_ssprxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SSP_SPI_SSPRXD_CFG_R = crate::FieldReader; #[doc = "Field `u0_ssp_spi_ssprxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SSP_SPI_SSPRXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SSP_SPI_SSPRXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_sys_crg_clk_jtag_tck_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SYS_CRG_CLK_JTAG_TCK_CFG_R = crate::FieldReader; #[doc = "Field `u0_sys_crg_clk_jtag_tck_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SYS_CRG_CLK_JTAG_TCK_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SYS_CRG_CLK_JTAG_TCK_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_sys_crg_ext_mclk_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SYS_CRG_EXT_MCLK_CFG_R = crate::FieldReader; #[doc = "Field `u0_sys_crg_ext_mclk_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SYS_CRG_EXT_MCLK_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SYS_CRG_EXT_MCLK_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_sys_crg_i2srx_bclk_slv_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SYS_CRG_I2SRX_BCLK_SLV_CFG_R = crate::FieldReader; #[doc = "Field `u0_sys_crg_i2srx_bclk_slv_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SYS_CRG_I2SRX_BCLK_SLV_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SYS_CRG_I2SRX_BCLK_SLV_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,30 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_ssp_spi_ssprxd_cfg(&mut self) -> U0_SSP_SPI_SSPRXD_CFG_W { - U0_SSP_SPI_SSPRXD_CFG_W::new(self) + pub fn u0_ssp_spi_ssprxd_cfg(&mut self) -> U0_SSP_SPI_SSPRXD_CFG_W { + U0_SSP_SPI_SSPRXD_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sys_crg_clk_jtag_tck_cfg(&mut self) -> U0_SYS_CRG_CLK_JTAG_TCK_CFG_W { - U0_SYS_CRG_CLK_JTAG_TCK_CFG_W::new(self) + pub fn u0_sys_crg_clk_jtag_tck_cfg(&mut self) -> U0_SYS_CRG_CLK_JTAG_TCK_CFG_W { + U0_SYS_CRG_CLK_JTAG_TCK_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sys_crg_ext_mclk_cfg(&mut self) -> U0_SYS_CRG_EXT_MCLK_CFG_W { - U0_SYS_CRG_EXT_MCLK_CFG_W::new(self) + pub fn u0_sys_crg_ext_mclk_cfg(&mut self) -> U0_SYS_CRG_EXT_MCLK_CFG_W { + U0_SYS_CRG_EXT_MCLK_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sys_crg_i2srx_bclk_slv_cfg( - &mut self, - ) -> U0_SYS_CRG_I2SRX_BCLK_SLV_CFG_W { - U0_SYS_CRG_I2SRX_BCLK_SLV_CFG_W::new(self) + pub fn u0_sys_crg_i2srx_bclk_slv_cfg(&mut self) -> U0_SYS_CRG_I2SRX_BCLK_SLV_CFG_W { + U0_SYS_CRG_I2SRX_BCLK_SLV_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi32.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi32.rs index 04c2284..bc1c4a7 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi32.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi32.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_sys_crg_i2srx_lrck_slv_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SYS_CRG_I2SRX_LRCK_SLV_CFG_R = crate::FieldReader; #[doc = "Field `u0_sys_crg_i2srx_lrck_slv_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SYS_CRG_I2SRX_LRCK_SLV_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SYS_CRG_I2SRX_LRCK_SLV_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_sys_crg_i2stx_bclk_slv_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SYS_CRG_I2STX_BCLK_SLV_CFG_R = crate::FieldReader; #[doc = "Field `u0_sys_crg_i2stx_bclk_slv_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SYS_CRG_I2STX_BCLK_SLV_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SYS_CRG_I2STX_BCLK_SLV_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_sys_crg_i2stx_lrck_slv_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SYS_CRG_I2STX_LRCK_SLV_CFG_R = crate::FieldReader; #[doc = "Field `u0_sys_crg_i2stx_lrck_slv_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SYS_CRG_I2STX_LRCK_SLV_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SYS_CRG_I2STX_LRCK_SLV_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_sys_crg_tdm_clk_slv_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SYS_CRG_TDM_CLK_SLV_CFG_R = crate::FieldReader; #[doc = "Field `u0_sys_crg_tdm_clk_slv_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SYS_CRG_TDM_CLK_SLV_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SYS_CRG_TDM_CLK_SLV_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,34 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sys_crg_i2srx_lrck_slv_cfg( - &mut self, - ) -> U0_SYS_CRG_I2SRX_LRCK_SLV_CFG_W { - U0_SYS_CRG_I2SRX_LRCK_SLV_CFG_W::new(self) + pub fn u0_sys_crg_i2srx_lrck_slv_cfg(&mut self) -> U0_SYS_CRG_I2SRX_LRCK_SLV_CFG_W { + U0_SYS_CRG_I2SRX_LRCK_SLV_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sys_crg_i2stx_bclk_slv_cfg( - &mut self, - ) -> U0_SYS_CRG_I2STX_BCLK_SLV_CFG_W { - U0_SYS_CRG_I2STX_BCLK_SLV_CFG_W::new(self) + pub fn u0_sys_crg_i2stx_bclk_slv_cfg(&mut self) -> U0_SYS_CRG_I2STX_BCLK_SLV_CFG_W { + U0_SYS_CRG_I2STX_BCLK_SLV_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sys_crg_i2stx_lrck_slv_cfg( - &mut self, - ) -> U0_SYS_CRG_I2STX_LRCK_SLV_CFG_W { - U0_SYS_CRG_I2STX_LRCK_SLV_CFG_W::new(self) + pub fn u0_sys_crg_i2stx_lrck_slv_cfg(&mut self) -> U0_SYS_CRG_I2STX_LRCK_SLV_CFG_W { + U0_SYS_CRG_I2STX_LRCK_SLV_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sys_crg_tdm_clk_slv_cfg(&mut self) -> U0_SYS_CRG_TDM_CLK_SLV_CFG_W { - U0_SYS_CRG_TDM_CLK_SLV_CFG_W::new(self) + pub fn u0_sys_crg_tdm_clk_slv_cfg(&mut self) -> U0_SYS_CRG_TDM_CLK_SLV_CFG_W { + U0_SYS_CRG_TDM_CLK_SLV_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi36.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi36.rs index 7dc6816..4215463 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi36.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi36.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_tdm16slot_pcm_rxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_TDM16SLOT_PCM_RXD_CFG_R = crate::FieldReader; #[doc = "Field `u0_tdm16slot_pcm_rxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_TDM16SLOT_PCM_RXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_TDM16SLOT_PCM_RXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_tdm16slot_pcm_synon_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_TDM16SLOT_PCM_SYNON_CFG_R = crate::FieldReader; #[doc = "Field `u0_tdm16slot_pcm_synon_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_TDM16SLOT_PCM_SYNON_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_TDM16SLOT_PCM_SYNON_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_can_ctrl_rxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_CAN_CTRL_RXD_CFG_R = crate::FieldReader; #[doc = "Field `u1_can_ctrl_rxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_CAN_CTRL_RXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_CAN_CTRL_RXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_i2c_ic_clk_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_I2C_IC_CLK_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u1_i2c_ic_clk_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_I2C_IC_CLK_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_I2C_IC_CLK_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_tdm16slot_pcm_rxd_cfg(&mut self) -> U0_TDM16SLOT_PCM_RXD_CFG_W { - U0_TDM16SLOT_PCM_RXD_CFG_W::new(self) + pub fn u0_tdm16slot_pcm_rxd_cfg(&mut self) -> U0_TDM16SLOT_PCM_RXD_CFG_W { + U0_TDM16SLOT_PCM_RXD_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_tdm16slot_pcm_synon_cfg(&mut self) -> U0_TDM16SLOT_PCM_SYNON_CFG_W { - U0_TDM16SLOT_PCM_SYNON_CFG_W::new(self) + pub fn u0_tdm16slot_pcm_synon_cfg(&mut self) -> U0_TDM16SLOT_PCM_SYNON_CFG_W { + U0_TDM16SLOT_PCM_SYNON_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_can_ctrl_rxd_cfg(&mut self) -> U1_CAN_CTRL_RXD_CFG_W { - U1_CAN_CTRL_RXD_CFG_W::new(self) + pub fn u1_can_ctrl_rxd_cfg(&mut self) -> U1_CAN_CTRL_RXD_CFG_W { + U1_CAN_CTRL_RXD_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_i2c_ic_clk_in_a_cfg(&mut self) -> U1_I2C_IC_CLK_IN_A_CFG_W { - U1_I2C_IC_CLK_IN_A_CFG_W::new(self) + pub fn u1_i2c_ic_clk_in_a_cfg(&mut self) -> U1_I2C_IC_CLK_IN_A_CFG_W { + U1_I2C_IC_CLK_IN_A_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi4.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi4.rs index 4c2a437..86cefd5 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi4.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi4.rs @@ -5,23 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_clkrst_src_bypass_jtag_trstn_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_CLKRST_SRC_BYPASS_JTAG_TRSTN_CFG_R = crate::FieldReader; #[doc = "Field `u0_clkrst_src_bypass_jtag_trstn_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_CLKRST_SRC_BYPASS_JTAG_TRSTN_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_CLKRST_SRC_BYPASS_JTAG_TRSTN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_dom_vout_top_u0_hdmi_tx_pin_cec_sda_in_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN_CFG_R = crate::FieldReader; #[doc = "Field `u0_dom_vout_top_u0_hdmi_tx_pin_cec_sda_in_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_dom_vout_top_u0_hdmi_tx_pin_ddc_scl_in_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN_CFG_R = crate::FieldReader; #[doc = "Field `u0_dom_vout_top_u0_hdmi_tx_pin_ddc_scl_in_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_dom_vout_top_u0_hdmi_tx_pin_ddc_sda_in_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN_CFG_R = crate::FieldReader; #[doc = "Field `u0_dom_vout_top_u0_hdmi_tx_pin_ddc_sda_in_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -56,34 +52,38 @@ impl W { #[must_use] pub fn u0_clkrst_src_bypass_jtag_trstn_cfg( &mut self, - ) -> U0_CLKRST_SRC_BYPASS_JTAG_TRSTN_CFG_W { - U0_CLKRST_SRC_BYPASS_JTAG_TRSTN_CFG_W::new(self) + ) -> U0_CLKRST_SRC_BYPASS_JTAG_TRSTN_CFG_W { + U0_CLKRST_SRC_BYPASS_JTAG_TRSTN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn u0_dom_vout_top_u0_hdmi_tx_pin_cec_sda_in_cfg( &mut self, - ) -> U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN_CFG_W { - U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN_CFG_W::new(self) + ) -> U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN_CFG_W { + U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn u0_dom_vout_top_u0_hdmi_tx_pin_ddc_scl_in_cfg( &mut self, - ) -> U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN_CFG_W { - U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN_CFG_W::new(self) + ) -> U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN_CFG_W { + U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn u0_dom_vout_top_u0_hdmi_tx_pin_ddc_sda_in_cfg( &mut self, - ) -> U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN_CFG_W { - U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN_CFG_W::new(self) + ) -> U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN_CFG_W { + U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi40.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi40.rs index f5f4dc6..11bed88 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi40.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi40.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u1_i2c_ic_data_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_I2C_IC_DATA_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u1_i2c_ic_data_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_I2C_IC_DATA_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_I2C_IC_DATA_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_card_detect_n_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CARD_DETECT_N_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_card_detect_n_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CARD_DETECT_N_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CARD_DETECT_N_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_card_int_n_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CARD_INT_N_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_card_int_n_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CARD_INT_N_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CARD_INT_N_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_card_write_prt_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CARD_WRITE_PRT_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_card_write_prt_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CARD_WRITE_PRT_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CARD_WRITE_PRT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_i2c_ic_data_in_a_cfg(&mut self) -> U1_I2C_IC_DATA_IN_A_CFG_W { - U1_I2C_IC_DATA_IN_A_CFG_W::new(self) + pub fn u1_i2c_ic_data_in_a_cfg(&mut self) -> U1_I2C_IC_DATA_IN_A_CFG_W { + U1_I2C_IC_DATA_IN_A_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_card_detect_n_cfg(&mut self) -> U1_SDIO_CARD_DETECT_N_CFG_W { - U1_SDIO_CARD_DETECT_N_CFG_W::new(self) + pub fn u1_sdio_card_detect_n_cfg(&mut self) -> U1_SDIO_CARD_DETECT_N_CFG_W { + U1_SDIO_CARD_DETECT_N_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_card_int_n_cfg(&mut self) -> U1_SDIO_CARD_INT_N_CFG_W { - U1_SDIO_CARD_INT_N_CFG_W::new(self) + pub fn u1_sdio_card_int_n_cfg(&mut self) -> U1_SDIO_CARD_INT_N_CFG_W { + U1_SDIO_CARD_INT_N_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_card_write_prt_cfg(&mut self) -> U1_SDIO_CARD_WRITE_PRT_CFG_W { - U1_SDIO_CARD_WRITE_PRT_CFG_W::new(self) + pub fn u1_sdio_card_write_prt_cfg(&mut self) -> U1_SDIO_CARD_WRITE_PRT_CFG_W { + U1_SDIO_CARD_WRITE_PRT_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi44.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi44.rs index 12e3082..e3b363b 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi44.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi44.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u1_sdio_ccmd_in_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CCMD_IN_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_ccmd_in_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CCMD_IN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CCMD_IN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_cdata_in_0_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CDATA_IN_0_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_cdata_in_0_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CDATA_IN_0_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CDATA_IN_0_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_cdata_in_1_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CDATA_IN_1_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_cdata_in_1_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CDATA_IN_1_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CDATA_IN_1_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_cdata_in_2_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CDATA_IN_2_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_cdata_in_2_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CDATA_IN_2_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CDATA_IN_2_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_ccmd_in_cfg(&mut self) -> U1_SDIO_CCMD_IN_CFG_W { - U1_SDIO_CCMD_IN_CFG_W::new(self) + pub fn u1_sdio_ccmd_in_cfg(&mut self) -> U1_SDIO_CCMD_IN_CFG_W { + U1_SDIO_CCMD_IN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_cdata_in_0_cfg(&mut self) -> U1_SDIO_CDATA_IN_0_CFG_W { - U1_SDIO_CDATA_IN_0_CFG_W::new(self) + pub fn u1_sdio_cdata_in_0_cfg(&mut self) -> U1_SDIO_CDATA_IN_0_CFG_W { + U1_SDIO_CDATA_IN_0_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_cdata_in_1_cfg(&mut self) -> U1_SDIO_CDATA_IN_1_CFG_W { - U1_SDIO_CDATA_IN_1_CFG_W::new(self) + pub fn u1_sdio_cdata_in_1_cfg(&mut self) -> U1_SDIO_CDATA_IN_1_CFG_W { + U1_SDIO_CDATA_IN_1_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_cdata_in_2_cfg(&mut self) -> U1_SDIO_CDATA_IN_2_CFG_W { - U1_SDIO_CDATA_IN_2_CFG_W::new(self) + pub fn u1_sdio_cdata_in_2_cfg(&mut self) -> U1_SDIO_CDATA_IN_2_CFG_W { + U1_SDIO_CDATA_IN_2_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi48.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi48.rs index 94f4962..271a793 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi48.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi48.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u1_sdio_cdata_in_3_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CDATA_IN_3_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_cdata_in_3_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CDATA_IN_3_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CDATA_IN_3_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_cdata_in_4_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CDATA_IN_4_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_cdata_in_4_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CDATA_IN_4_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CDATA_IN_4_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_cdata_in_5_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CDATA_IN_5_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_cdata_in_5_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CDATA_IN_5_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CDATA_IN_5_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_cdata_in_6_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CDATA_IN_6_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_cdata_in_6_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CDATA_IN_6_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CDATA_IN_6_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_cdata_in_3_cfg(&mut self) -> U1_SDIO_CDATA_IN_3_CFG_W { - U1_SDIO_CDATA_IN_3_CFG_W::new(self) + pub fn u1_sdio_cdata_in_3_cfg(&mut self) -> U1_SDIO_CDATA_IN_3_CFG_W { + U1_SDIO_CDATA_IN_3_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_cdata_in_4_cfg(&mut self) -> U1_SDIO_CDATA_IN_4_CFG_W { - U1_SDIO_CDATA_IN_4_CFG_W::new(self) + pub fn u1_sdio_cdata_in_4_cfg(&mut self) -> U1_SDIO_CDATA_IN_4_CFG_W { + U1_SDIO_CDATA_IN_4_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_cdata_in_5_cfg(&mut self) -> U1_SDIO_CDATA_IN_5_CFG_W { - U1_SDIO_CDATA_IN_5_CFG_W::new(self) + pub fn u1_sdio_cdata_in_5_cfg(&mut self) -> U1_SDIO_CDATA_IN_5_CFG_W { + U1_SDIO_CDATA_IN_5_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_cdata_in_6_cfg(&mut self) -> U1_SDIO_CDATA_IN_6_CFG_W { - U1_SDIO_CDATA_IN_6_CFG_W::new(self) + pub fn u1_sdio_cdata_in_6_cfg(&mut self) -> U1_SDIO_CDATA_IN_6_CFG_W { + U1_SDIO_CDATA_IN_6_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi52.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi52.rs index aa2e6c9..f67ed50 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi52.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi52.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u1_sdio_cdata_in_7_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CDATA_IN_7_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_cdata_in_7_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CDATA_IN_7_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CDATA_IN_7_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_data_strobe_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_DATA_STROBE_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_data_strobe_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_DATA_STROBE_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_DATA_STROBE_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_uart_cts_n_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_UART_CTS_N_CFG_R = crate::FieldReader; #[doc = "Field `u1_uart_cts_n_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_UART_CTS_N_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_UART_CTS_N_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_uart_sin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_UART_SIN_CFG_R = crate::FieldReader; #[doc = "Field `u1_uart_sin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_UART_SIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_UART_SIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_cdata_in_7_cfg(&mut self) -> U1_SDIO_CDATA_IN_7_CFG_W { - U1_SDIO_CDATA_IN_7_CFG_W::new(self) + pub fn u1_sdio_cdata_in_7_cfg(&mut self) -> U1_SDIO_CDATA_IN_7_CFG_W { + U1_SDIO_CDATA_IN_7_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_data_strobe_cfg(&mut self) -> U1_SDIO_DATA_STROBE_CFG_W { - U1_SDIO_DATA_STROBE_CFG_W::new(self) + pub fn u1_sdio_data_strobe_cfg(&mut self) -> U1_SDIO_DATA_STROBE_CFG_W { + U1_SDIO_DATA_STROBE_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_uart_cts_n_cfg(&mut self) -> U1_UART_CTS_N_CFG_W { - U1_UART_CTS_N_CFG_W::new(self) + pub fn u1_uart_cts_n_cfg(&mut self) -> U1_UART_CTS_N_CFG_W { + U1_UART_CTS_N_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_uart_sin_cfg(&mut self) -> U1_UART_SIN_CFG_W { - U1_UART_SIN_CFG_W::new(self) + pub fn u1_uart_sin_cfg(&mut self) -> U1_UART_SIN_CFG_W { + U1_UART_SIN_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi56.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi56.rs index b368295..3bd8dde 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi56.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi56.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u1_ssp_spi_ssp_clkin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SSP_SPI_SSP_CLKIN_CFG_R = crate::FieldReader; #[doc = "Field `u1_ssp_spi_ssp_clkin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SSP_SPI_SSP_CLKIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SSP_SPI_SSP_CLKIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_ssp_spi_sspfssin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SSP_SPI_SSPFSSIN_CFG_R = crate::FieldReader; #[doc = "Field `u1_ssp_spi_sspfssin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SSP_SPI_SSPFSSIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SSP_SPI_SSPFSSIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_ssp_spi_ssprxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SSP_SPI_SSPRXD_CFG_R = crate::FieldReader; #[doc = "Field `u1_ssp_spi_ssprxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SSP_SPI_SSPRXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SSP_SPI_SSPRXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u2_i2c_ic_clk_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U2_I2C_IC_CLK_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u2_i2c_ic_clk_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U2_I2C_IC_CLK_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U2_I2C_IC_CLK_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_ssp_spi_ssp_clkin_cfg(&mut self) -> U1_SSP_SPI_SSP_CLKIN_CFG_W { - U1_SSP_SPI_SSP_CLKIN_CFG_W::new(self) + pub fn u1_ssp_spi_ssp_clkin_cfg(&mut self) -> U1_SSP_SPI_SSP_CLKIN_CFG_W { + U1_SSP_SPI_SSP_CLKIN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_ssp_spi_sspfssin_cfg(&mut self) -> U1_SSP_SPI_SSPFSSIN_CFG_W { - U1_SSP_SPI_SSPFSSIN_CFG_W::new(self) + pub fn u1_ssp_spi_sspfssin_cfg(&mut self) -> U1_SSP_SPI_SSPFSSIN_CFG_W { + U1_SSP_SPI_SSPFSSIN_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_ssp_spi_ssprxd_cfg(&mut self) -> U1_SSP_SPI_SSPRXD_CFG_W { - U1_SSP_SPI_SSPRXD_CFG_W::new(self) + pub fn u1_ssp_spi_ssprxd_cfg(&mut self) -> U1_SSP_SPI_SSPRXD_CFG_W { + U1_SSP_SPI_SSPRXD_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u2_i2c_ic_clk_in_a_cfg(&mut self) -> U2_I2C_IC_CLK_IN_A_CFG_W { - U2_I2C_IC_CLK_IN_A_CFG_W::new(self) + pub fn u2_i2c_ic_clk_in_a_cfg(&mut self) -> U2_I2C_IC_CLK_IN_A_CFG_W { + U2_I2C_IC_CLK_IN_A_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi60.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi60.rs index 5b55320..821d0f9 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi60.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi60.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u2_i2c_ic_data_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U2_I2C_IC_DATA_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u2_i2c_ic_data_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U2_I2C_IC_DATA_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U2_I2C_IC_DATA_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u2_uart_cts_n_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U2_UART_CTS_N_CFG_R = crate::FieldReader; #[doc = "Field `u2_uart_cts_n_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U2_UART_CTS_N_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U2_UART_CTS_N_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u2_uart_sin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U2_UART_SIN_CFG_R = crate::FieldReader; #[doc = "Field `u2_uart_sin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U2_UART_SIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U2_UART_SIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u2_ssp_spi_sspclkin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U2_SSP_SPI_SSPCLKIN_CFG_R = crate::FieldReader; #[doc = "Field `u2_ssp_spi_sspclkin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U2_SSP_SPI_SSPCLKIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U2_SSP_SPI_SSPCLKIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u2_i2c_ic_data_in_a_cfg(&mut self) -> U2_I2C_IC_DATA_IN_A_CFG_W { - U2_I2C_IC_DATA_IN_A_CFG_W::new(self) + pub fn u2_i2c_ic_data_in_a_cfg(&mut self) -> U2_I2C_IC_DATA_IN_A_CFG_W { + U2_I2C_IC_DATA_IN_A_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u2_uart_cts_n_cfg(&mut self) -> U2_UART_CTS_N_CFG_W { - U2_UART_CTS_N_CFG_W::new(self) + pub fn u2_uart_cts_n_cfg(&mut self) -> U2_UART_CTS_N_CFG_W { + U2_UART_CTS_N_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u2_uart_sin_cfg(&mut self) -> U2_UART_SIN_CFG_W { - U2_UART_SIN_CFG_W::new(self) + pub fn u2_uart_sin_cfg(&mut self) -> U2_UART_SIN_CFG_W { + U2_UART_SIN_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u2_ssp_spi_sspclkin_cfg(&mut self) -> U2_SSP_SPI_SSPCLKIN_CFG_W { - U2_SSP_SPI_SSPCLKIN_CFG_W::new(self) + pub fn u2_ssp_spi_sspclkin_cfg(&mut self) -> U2_SSP_SPI_SSPCLKIN_CFG_W { + U2_SSP_SPI_SSPCLKIN_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi64.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi64.rs index 417b4f5..2688fb2 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi64.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi64.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u2_ssp_spi_sspfssin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U2_SSP_SPI_SSPFSSIN_CFG_R = crate::FieldReader; #[doc = "Field `u2_ssp_spi_sspfssin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U2_SSP_SPI_SSPFSSIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U2_SSP_SPI_SSPFSSIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u2_ssp_spi_ssprxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U2_SSP_SPI_SSPRXD_CFG_R = crate::FieldReader; #[doc = "Field `u2_ssp_spi_ssprxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U2_SSP_SPI_SSPRXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U2_SSP_SPI_SSPRXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u3_i2c_ic_clk_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U3_I2C_IC_CLK_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u3_i2c_ic_clk_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U3_I2C_IC_CLK_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U3_I2C_IC_CLK_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u3_i2c_ic_data_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U3_I2C_IC_DATA_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u3_i2c_ic_data_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U3_I2C_IC_DATA_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U3_I2C_IC_DATA_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u2_ssp_spi_sspfssin_cfg(&mut self) -> U2_SSP_SPI_SSPFSSIN_CFG_W { - U2_SSP_SPI_SSPFSSIN_CFG_W::new(self) + pub fn u2_ssp_spi_sspfssin_cfg(&mut self) -> U2_SSP_SPI_SSPFSSIN_CFG_W { + U2_SSP_SPI_SSPFSSIN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u2_ssp_spi_ssprxd_cfg(&mut self) -> U2_SSP_SPI_SSPRXD_CFG_W { - U2_SSP_SPI_SSPRXD_CFG_W::new(self) + pub fn u2_ssp_spi_ssprxd_cfg(&mut self) -> U2_SSP_SPI_SSPRXD_CFG_W { + U2_SSP_SPI_SSPRXD_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u3_i2c_ic_clk_in_a_cfg(&mut self) -> U3_I2C_IC_CLK_IN_A_CFG_W { - U3_I2C_IC_CLK_IN_A_CFG_W::new(self) + pub fn u3_i2c_ic_clk_in_a_cfg(&mut self) -> U3_I2C_IC_CLK_IN_A_CFG_W { + U3_I2C_IC_CLK_IN_A_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u3_i2c_ic_data_in_a_cfg(&mut self) -> U3_I2C_IC_DATA_IN_A_CFG_W { - U3_I2C_IC_DATA_IN_A_CFG_W::new(self) + pub fn u3_i2c_ic_data_in_a_cfg(&mut self) -> U3_I2C_IC_DATA_IN_A_CFG_W { + U3_I2C_IC_DATA_IN_A_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi68.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi68.rs index afd8a13..da670a0 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi68.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi68.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u3_uart_sin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U3_UART_SIN_CFG_R = crate::FieldReader; #[doc = "Field `u3_uart_sin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U3_UART_SIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U3_UART_SIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u3_ssp_spi_sspclkin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U3_SSP_SPI_SSPCLKIN_CFG_R = crate::FieldReader; #[doc = "Field `u3_ssp_spi_sspclkin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U3_SSP_SPI_SSPCLKIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U3_SSP_SPI_SSPCLKIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u3_ssp_spi_sspfssin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U3_SSP_SPI_SSPFSSIN_CFG_R = crate::FieldReader; #[doc = "Field `u3_ssp_spi_sspfssin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U3_SSP_SPI_SSPFSSIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U3_SSP_SPI_SSPFSSIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u3_ssp_spi_ssprxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U3_SSP_SPI_SSPRXD_CFG_R = crate::FieldReader; #[doc = "Field `u3_ssp_spi_ssprxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U3_SSP_SPI_SSPRXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U3_SSP_SPI_SSPRXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u3_uart_sin_cfg(&mut self) -> U3_UART_SIN_CFG_W { - U3_UART_SIN_CFG_W::new(self) + pub fn u3_uart_sin_cfg(&mut self) -> U3_UART_SIN_CFG_W { + U3_UART_SIN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u3_ssp_spi_sspclkin_cfg(&mut self) -> U3_SSP_SPI_SSPCLKIN_CFG_W { - U3_SSP_SPI_SSPCLKIN_CFG_W::new(self) + pub fn u3_ssp_spi_sspclkin_cfg(&mut self) -> U3_SSP_SPI_SSPCLKIN_CFG_W { + U3_SSP_SPI_SSPCLKIN_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u3_ssp_spi_sspfssin_cfg(&mut self) -> U3_SSP_SPI_SSPFSSIN_CFG_W { - U3_SSP_SPI_SSPFSSIN_CFG_W::new(self) + pub fn u3_ssp_spi_sspfssin_cfg(&mut self) -> U3_SSP_SPI_SSPFSSIN_CFG_W { + U3_SSP_SPI_SSPFSSIN_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u3_ssp_spi_ssprxd_cfg(&mut self) -> U3_SSP_SPI_SSPRXD_CFG_W { - U3_SSP_SPI_SSPRXD_CFG_W::new(self) + pub fn u3_ssp_spi_ssprxd_cfg(&mut self) -> U3_SSP_SPI_SSPRXD_CFG_W { + U3_SSP_SPI_SSPRXD_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi72.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi72.rs index 3ddd0a5..e635fb1 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi72.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi72.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u4_i2c_ic_clk_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U4_I2C_IC_CLK_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u4_i2c_ic_clk_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U4_I2C_IC_CLK_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U4_I2C_IC_CLK_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u4_i2c_ic_data_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U4_I2C_IC_DATA_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u4_i2c_ic_data_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U4_I2C_IC_DATA_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U4_I2C_IC_DATA_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u4_uart_cts_n_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U4_UART_CTS_N_CFG_R = crate::FieldReader; #[doc = "Field `u4_uart_cts_n_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U4_UART_CTS_N_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U4_UART_CTS_N_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u4_uart_sin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U4_UART_SIN_CFG_R = crate::FieldReader; #[doc = "Field `u4_uart_sin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U4_UART_SIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U4_UART_SIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u4_i2c_ic_clk_in_a_cfg(&mut self) -> U4_I2C_IC_CLK_IN_A_CFG_W { - U4_I2C_IC_CLK_IN_A_CFG_W::new(self) + pub fn u4_i2c_ic_clk_in_a_cfg(&mut self) -> U4_I2C_IC_CLK_IN_A_CFG_W { + U4_I2C_IC_CLK_IN_A_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u4_i2c_ic_data_in_a_cfg(&mut self) -> U4_I2C_IC_DATA_IN_A_CFG_W { - U4_I2C_IC_DATA_IN_A_CFG_W::new(self) + pub fn u4_i2c_ic_data_in_a_cfg(&mut self) -> U4_I2C_IC_DATA_IN_A_CFG_W { + U4_I2C_IC_DATA_IN_A_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u4_uart_cts_n_cfg(&mut self) -> U4_UART_CTS_N_CFG_W { - U4_UART_CTS_N_CFG_W::new(self) + pub fn u4_uart_cts_n_cfg(&mut self) -> U4_UART_CTS_N_CFG_W { + U4_UART_CTS_N_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u4_uart_sin_cfg(&mut self) -> U4_UART_SIN_CFG_W { - U4_UART_SIN_CFG_W::new(self) + pub fn u4_uart_sin_cfg(&mut self) -> U4_UART_SIN_CFG_W { + U4_UART_SIN_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi76.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi76.rs index 4c808bf..29ec06b 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi76.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi76.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u4_ssp_spi_sspclkin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U4_SSP_SPI_SSPCLKIN_CFG_R = crate::FieldReader; #[doc = "Field `u4_ssp_spi_sspclkin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U4_SSP_SPI_SSPCLKIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U4_SSP_SPI_SSPCLKIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u4_ssp_spi_sspfssin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U4_SSP_SPI_SSPFSSIN_CFG_R = crate::FieldReader; #[doc = "Field `u4_ssp_spi_sspfssin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U4_SSP_SPI_SSPFSSIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U4_SSP_SPI_SSPFSSIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u4_ssp_spi_ssprxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U4_SSP_SPI_SSPRXD_CFG_R = crate::FieldReader; #[doc = "Field `u4_ssp_spi_ssprxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U4_SSP_SPI_SSPRXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U4_SSP_SPI_SSPRXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u5_i2c_ic_clk_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U5_I2C_IC_CLK_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u5_i2c_ic_clk_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U5_I2C_IC_CLK_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U5_I2C_IC_CLK_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u4_ssp_spi_sspclkin_cfg(&mut self) -> U4_SSP_SPI_SSPCLKIN_CFG_W { - U4_SSP_SPI_SSPCLKIN_CFG_W::new(self) + pub fn u4_ssp_spi_sspclkin_cfg(&mut self) -> U4_SSP_SPI_SSPCLKIN_CFG_W { + U4_SSP_SPI_SSPCLKIN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u4_ssp_spi_sspfssin_cfg(&mut self) -> U4_SSP_SPI_SSPFSSIN_CFG_W { - U4_SSP_SPI_SSPFSSIN_CFG_W::new(self) + pub fn u4_ssp_spi_sspfssin_cfg(&mut self) -> U4_SSP_SPI_SSPFSSIN_CFG_W { + U4_SSP_SPI_SSPFSSIN_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u4_ssp_spi_ssprxd_cfg(&mut self) -> U4_SSP_SPI_SSPRXD_CFG_W { - U4_SSP_SPI_SSPRXD_CFG_W::new(self) + pub fn u4_ssp_spi_ssprxd_cfg(&mut self) -> U4_SSP_SPI_SSPRXD_CFG_W { + U4_SSP_SPI_SSPRXD_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u5_i2c_ic_clk_in_a_cfg(&mut self) -> U5_I2C_IC_CLK_IN_A_CFG_W { - U5_I2C_IC_CLK_IN_A_CFG_W::new(self) + pub fn u5_i2c_ic_clk_in_a_cfg(&mut self) -> U5_I2C_IC_CLK_IN_A_CFG_W { + U5_I2C_IC_CLK_IN_A_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi8.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi8.rs index b08bd05..c232295 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi8.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi8.rs @@ -5,20 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_dom_vout_top_u0_hdmi_tx_pin_hpd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD_CFG_R = crate::FieldReader; #[doc = "Field `u0_dom_vout_top_u0_hdmi_tx_pin_hpd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_i2c_ic_clk_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_I2C_IC_CLK_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u0_i2c_ic_clk_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_I2C_IC_CLK_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_I2C_IC_CLK_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_i2c_ic_data_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_I2C_IC_DATA_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u0_i2c_ic_data_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_I2C_IC_DATA_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_I2C_IC_DATA_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_sdio_card_detect_n_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SDIO_CARD_DETECT_N_CFG_R = crate::FieldReader; #[doc = "Field `u0_sdio_card_detect_n_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SDIO_CARD_DETECT_N_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SDIO_CARD_DETECT_N_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -49,28 +48,32 @@ impl W { #[must_use] pub fn u0_dom_vout_top_u0_hdmi_tx_pin_hpd_cfg( &mut self, - ) -> U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD_CFG_W { - U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD_CFG_W::new(self) + ) -> U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD_CFG_W { + U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_i2c_ic_clk_in_a_cfg(&mut self) -> U0_I2C_IC_CLK_IN_A_CFG_W { - U0_I2C_IC_CLK_IN_A_CFG_W::new(self) + pub fn u0_i2c_ic_clk_in_a_cfg(&mut self) -> U0_I2C_IC_CLK_IN_A_CFG_W { + U0_I2C_IC_CLK_IN_A_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_i2c_ic_data_in_a_cfg(&mut self) -> U0_I2C_IC_DATA_IN_A_CFG_W { - U0_I2C_IC_DATA_IN_A_CFG_W::new(self) + pub fn u0_i2c_ic_data_in_a_cfg(&mut self) -> U0_I2C_IC_DATA_IN_A_CFG_W { + U0_I2C_IC_DATA_IN_A_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sdio_card_detect_n_cfg(&mut self) -> U0_SDIO_CARD_DETECT_N_CFG_W { - U0_SDIO_CARD_DETECT_N_CFG_W::new(self) + pub fn u0_sdio_card_detect_n_cfg(&mut self) -> U0_SDIO_CARD_DETECT_N_CFG_W { + U0_SDIO_CARD_DETECT_N_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi80.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi80.rs index d553591..b73a4ea 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi80.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi80.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u5_i2c_ic_data_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U5_I2C_IC_DATA_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u5_i2c_ic_data_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U5_I2C_IC_DATA_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U5_I2C_IC_DATA_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u5_uart_cts_n_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U5_UART_CTS_N_CFG_R = crate::FieldReader; #[doc = "Field `u5_uart_cts_n_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U5_UART_CTS_N_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U5_UART_CTS_N_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u5_uart_sin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U5_UART_SIN_CFG_R = crate::FieldReader; #[doc = "Field `u5_uart_sin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U5_UART_SIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U5_UART_SIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u5_ssp_spi_sspclkin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U5_SSP_SPI_SSPCLKIN_CFG_R = crate::FieldReader; #[doc = "Field `u5_ssp_spi_sspclkin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U5_SSP_SPI_SSPCLKIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U5_SSP_SPI_SSPCLKIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u5_i2c_ic_data_in_a_cfg(&mut self) -> U5_I2C_IC_DATA_IN_A_CFG_W { - U5_I2C_IC_DATA_IN_A_CFG_W::new(self) + pub fn u5_i2c_ic_data_in_a_cfg(&mut self) -> U5_I2C_IC_DATA_IN_A_CFG_W { + U5_I2C_IC_DATA_IN_A_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u5_uart_cts_n_cfg(&mut self) -> U5_UART_CTS_N_CFG_W { - U5_UART_CTS_N_CFG_W::new(self) + pub fn u5_uart_cts_n_cfg(&mut self) -> U5_UART_CTS_N_CFG_W { + U5_UART_CTS_N_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u5_uart_sin_cfg(&mut self) -> U5_UART_SIN_CFG_W { - U5_UART_SIN_CFG_W::new(self) + pub fn u5_uart_sin_cfg(&mut self) -> U5_UART_SIN_CFG_W { + U5_UART_SIN_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u5_ssp_spi_sspclkin_cfg(&mut self) -> U5_SSP_SPI_SSPCLKIN_CFG_W { - U5_SSP_SPI_SSPCLKIN_CFG_W::new(self) + pub fn u5_ssp_spi_sspclkin_cfg(&mut self) -> U5_SSP_SPI_SSPCLKIN_CFG_W { + U5_SSP_SPI_SSPCLKIN_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi84.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi84.rs index d9bf866..0105ddf 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi84.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi84.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u5_ssp_spi_sspfssin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U5_SSP_SPI_SSPFSSIN_CFG_R = crate::FieldReader; #[doc = "Field `u5_ssp_spi_sspfssin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U5_SSP_SPI_SSPFSSIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U5_SSP_SPI_SSPFSSIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u5_ssp_spi_ssprxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U5_SSP_SPI_SSPRXD_CFG_R = crate::FieldReader; #[doc = "Field `u5_ssp_spi_ssprxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U5_SSP_SPI_SSPRXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U5_SSP_SPI_SSPRXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u6_i2c_ic_clk_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U6_I2C_IC_CLK_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u6_i2c_ic_clk_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U6_I2C_IC_CLK_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U6_I2C_IC_CLK_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u6_i2c_ic_data_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U6_I2C_IC_DATA_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u6_i2c_ic_data_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U6_I2C_IC_DATA_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U6_I2C_IC_DATA_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u5_ssp_spi_sspfssin_cfg(&mut self) -> U5_SSP_SPI_SSPFSSIN_CFG_W { - U5_SSP_SPI_SSPFSSIN_CFG_W::new(self) + pub fn u5_ssp_spi_sspfssin_cfg(&mut self) -> U5_SSP_SPI_SSPFSSIN_CFG_W { + U5_SSP_SPI_SSPFSSIN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u5_ssp_spi_ssprxd_cfg(&mut self) -> U5_SSP_SPI_SSPRXD_CFG_W { - U5_SSP_SPI_SSPRXD_CFG_W::new(self) + pub fn u5_ssp_spi_ssprxd_cfg(&mut self) -> U5_SSP_SPI_SSPRXD_CFG_W { + U5_SSP_SPI_SSPRXD_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u6_i2c_ic_clk_in_a_cfg(&mut self) -> U6_I2C_IC_CLK_IN_A_CFG_W { - U6_I2C_IC_CLK_IN_A_CFG_W::new(self) + pub fn u6_i2c_ic_clk_in_a_cfg(&mut self) -> U6_I2C_IC_CLK_IN_A_CFG_W { + U6_I2C_IC_CLK_IN_A_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u6_i2c_ic_data_in_a_cfg(&mut self) -> U6_I2C_IC_DATA_IN_A_CFG_W { - U6_I2C_IC_DATA_IN_A_CFG_W::new(self) + pub fn u6_i2c_ic_data_in_a_cfg(&mut self) -> U6_I2C_IC_DATA_IN_A_CFG_W { + U6_I2C_IC_DATA_IN_A_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi88.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi88.rs index 434a4f8..24a4519 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi88.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpi88.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `u6_ssp_spi_sspclkin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U6_SSP_SPI_SSPCLKIN_CFG_R = crate::FieldReader; #[doc = "Field `u6_ssp_spi_sspclkin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U6_SSP_SPI_SSPCLKIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U6_SSP_SPI_SSPCLKIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u6_ssp_spi_sspfssin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U6_SSP_SPI_SSPFSSIN_CFG_R = crate::FieldReader; #[doc = "Field `u6_ssp_spi_sspfssin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U6_SSP_SPI_SSPFSSIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U6_SSP_SPI_SSPFSSIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u6_ssp_spi_ssprxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U6_SSP_SPI_SSPRXD_CFG_R = crate::FieldReader; #[doc = "Field `u6_ssp_spi_ssprxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U6_SSP_SPI_SSPRXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U6_SSP_SPI_SSPRXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u6_ssp_spi_sspclkin_cfg(&mut self) -> U6_SSP_SPI_SSPCLKIN_CFG_W { - U6_SSP_SPI_SSPCLKIN_CFG_W::new(self) + pub fn u6_ssp_spi_sspclkin_cfg(&mut self) -> U6_SSP_SPI_SSPCLKIN_CFG_W { + U6_SSP_SPI_SSPCLKIN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u6_ssp_spi_sspfssin_cfg(&mut self) -> U6_SSP_SPI_SSPFSSIN_CFG_W { - U6_SSP_SPI_SSPFSSIN_CFG_W::new(self) + pub fn u6_ssp_spi_sspfssin_cfg(&mut self) -> U6_SSP_SPI_SSPFSSIN_CFG_W { + U6_SSP_SPI_SSPFSSIN_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u6_ssp_spi_ssprxd_cfg(&mut self) -> U6_SSP_SPI_SSPRXD_CFG_W { - U6_SSP_SPI_SSPRXD_CFG_W::new(self) + pub fn u6_ssp_spi_ssprxd_cfg(&mut self) -> U6_SSP_SPI_SSPRXD_CFG_W { + U6_SSP_SPI_SSPRXD_CFG_W::new(self, 16) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen0.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen0.rs index 5611e71..b7112dd 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen0.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen0.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo0_doen` reader - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO0_DOEN_R = crate::FieldReader; #[doc = "Field `gpo0_doen` writer - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO0_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO0_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo1_doen` reader - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO1_DOEN_R = crate::FieldReader; #[doc = "Field `gpo1_doen` writer - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO1_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO1_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo2_doen` reader - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO2_DOEN_R = crate::FieldReader; #[doc = "Field `gpo2_doen` writer - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO2_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO2_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo3_doen` reader - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO3_DOEN_R = crate::FieldReader; #[doc = "Field `gpo3_doen` writer - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO3_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO3_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo0_doen(&mut self) -> GPO0_DOEN_W { - GPO0_DOEN_W::new(self) + pub fn gpo0_doen(&mut self) -> GPO0_DOEN_W { + GPO0_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo1_doen(&mut self) -> GPO1_DOEN_W { - GPO1_DOEN_W::new(self) + pub fn gpo1_doen(&mut self) -> GPO1_DOEN_W { + GPO1_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo2_doen(&mut self) -> GPO2_DOEN_W { - GPO2_DOEN_W::new(self) + pub fn gpo2_doen(&mut self) -> GPO2_DOEN_W { + GPO2_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo3_doen(&mut self) -> GPO3_DOEN_W { - GPO3_DOEN_W::new(self) + pub fn gpo3_doen(&mut self) -> GPO3_DOEN_W { + GPO3_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen1.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen1.rs index e207bda..01b3e21 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen1.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo4_doen` reader - The selected OEN signal for GPIO4. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO4_DOEN_R = crate::FieldReader; #[doc = "Field `gpo4_doen` writer - The selected OEN signal for GPIO4. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO4_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO4_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo5_doen` reader - The selected OEN signal for GPIO5. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO5_DOEN_R = crate::FieldReader; #[doc = "Field `gpo5_doen` writer - The selected OEN signal for GPIO5. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO5_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO5_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo6_doen` reader - The selected OEN signal for GPIO6. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO6_DOEN_R = crate::FieldReader; #[doc = "Field `gpo6_doen` writer - The selected OEN signal for GPIO6. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO6_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO6_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo7_doen` reader - The selected OEN signal for GPIO7. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO7_DOEN_R = crate::FieldReader; #[doc = "Field `gpo7_doen` writer - The selected OEN signal for GPIO7. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO7_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO7_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO4. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO4. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo4_doen(&mut self) -> GPO4_DOEN_W { - GPO4_DOEN_W::new(self) + pub fn gpo4_doen(&mut self) -> GPO4_DOEN_W { + GPO4_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO5. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo5_doen(&mut self) -> GPO5_DOEN_W { - GPO5_DOEN_W::new(self) + pub fn gpo5_doen(&mut self) -> GPO5_DOEN_W { + GPO5_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO6. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo6_doen(&mut self) -> GPO6_DOEN_W { - GPO6_DOEN_W::new(self) + pub fn gpo6_doen(&mut self) -> GPO6_DOEN_W { + GPO6_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO7. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo7_doen(&mut self) -> GPO7_DOEN_W { - GPO7_DOEN_W::new(self) + pub fn gpo7_doen(&mut self) -> GPO7_DOEN_W { + GPO7_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen10.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen10.rs index 7151d68..2b83644 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen10.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen10.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo40_doen` reader - The selected OEN signal for GPIO40. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO40_DOEN_R = crate::FieldReader; #[doc = "Field `gpo40_doen` writer - The selected OEN signal for GPIO40. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO40_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO40_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo41_doen` reader - The selected OEN signal for GPIO41. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO41_DOEN_R = crate::FieldReader; #[doc = "Field `gpo41_doen` writer - The selected OEN signal for GPIO41. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO41_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO41_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo42_doen` reader - The selected OEN signal for GPIO42. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO42_DOEN_R = crate::FieldReader; #[doc = "Field `gpo42_doen` writer - The selected OEN signal for GPIO42. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO42_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO42_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo43_doen` reader - The selected OEN signal for GPIO43. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO43_DOEN_R = crate::FieldReader; #[doc = "Field `gpo43_doen` writer - The selected OEN signal for GPIO43. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO43_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO43_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO40. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO40. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo40_doen(&mut self) -> GPO40_DOEN_W { - GPO40_DOEN_W::new(self) + pub fn gpo40_doen(&mut self) -> GPO40_DOEN_W { + GPO40_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO41. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo41_doen(&mut self) -> GPO41_DOEN_W { - GPO41_DOEN_W::new(self) + pub fn gpo41_doen(&mut self) -> GPO41_DOEN_W { + GPO41_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO42. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo42_doen(&mut self) -> GPO42_DOEN_W { - GPO42_DOEN_W::new(self) + pub fn gpo42_doen(&mut self) -> GPO42_DOEN_W { + GPO42_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO43. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo43_doen(&mut self) -> GPO43_DOEN_W { - GPO43_DOEN_W::new(self) + pub fn gpo43_doen(&mut self) -> GPO43_DOEN_W { + GPO43_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen11.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen11.rs index 8fca58e..01e66b1 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen11.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen11.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo44_doen` reader - The selected OEN signal for GPIO44. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO44_DOEN_R = crate::FieldReader; #[doc = "Field `gpo44_doen` writer - The selected OEN signal for GPIO44. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO44_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO44_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo45_doen` reader - The selected OEN signal for GPIO45. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO45_DOEN_R = crate::FieldReader; #[doc = "Field `gpo45_doen` writer - The selected OEN signal for GPIO45. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO45_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO45_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo46_doen` reader - The selected OEN signal for GPIO46. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO46_DOEN_R = crate::FieldReader; #[doc = "Field `gpo46_doen` writer - The selected OEN signal for GPIO46. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO46_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO46_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo47_doen` reader - The selected OEN signal for GPIO47. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO47_DOEN_R = crate::FieldReader; #[doc = "Field `gpo47_doen` writer - The selected OEN signal for GPIO47. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO47_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO47_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO44. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO44. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo44_doen(&mut self) -> GPO44_DOEN_W { - GPO44_DOEN_W::new(self) + pub fn gpo44_doen(&mut self) -> GPO44_DOEN_W { + GPO44_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO45. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo45_doen(&mut self) -> GPO45_DOEN_W { - GPO45_DOEN_W::new(self) + pub fn gpo45_doen(&mut self) -> GPO45_DOEN_W { + GPO45_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO46. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo46_doen(&mut self) -> GPO46_DOEN_W { - GPO46_DOEN_W::new(self) + pub fn gpo46_doen(&mut self) -> GPO46_DOEN_W { + GPO46_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO47. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo47_doen(&mut self) -> GPO47_DOEN_W { - GPO47_DOEN_W::new(self) + pub fn gpo47_doen(&mut self) -> GPO47_DOEN_W { + GPO47_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen12.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen12.rs index 9e4ea16..bf2ebe9 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen12.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen12.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo48_doen` reader - The selected OEN signal for GPIO48. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO48_DOEN_R = crate::FieldReader; #[doc = "Field `gpo48_doen` writer - The selected OEN signal for GPIO48. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO48_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO48_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo49_doen` reader - The selected OEN signal for GPIO49. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO49_DOEN_R = crate::FieldReader; #[doc = "Field `gpo49_doen` writer - The selected OEN signal for GPIO49. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO49_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO49_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo50_doen` reader - The selected OEN signal for GPIO50. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO50_DOEN_R = crate::FieldReader; #[doc = "Field `gpo50_doen` writer - The selected OEN signal for GPIO50. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO50_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO50_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo51_doen` reader - The selected OEN signal for GPIO51. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO51_DOEN_R = crate::FieldReader; #[doc = "Field `gpo51_doen` writer - The selected OEN signal for GPIO51. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO51_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO51_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO48. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO48. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo48_doen(&mut self) -> GPO48_DOEN_W { - GPO48_DOEN_W::new(self) + pub fn gpo48_doen(&mut self) -> GPO48_DOEN_W { + GPO48_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO49. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo49_doen(&mut self) -> GPO49_DOEN_W { - GPO49_DOEN_W::new(self) + pub fn gpo49_doen(&mut self) -> GPO49_DOEN_W { + GPO49_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO50. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo50_doen(&mut self) -> GPO50_DOEN_W { - GPO50_DOEN_W::new(self) + pub fn gpo50_doen(&mut self) -> GPO50_DOEN_W { + GPO50_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO51. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo51_doen(&mut self) -> GPO51_DOEN_W { - GPO51_DOEN_W::new(self) + pub fn gpo51_doen(&mut self) -> GPO51_DOEN_W { + GPO51_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen13.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen13.rs index b8ff102..c068311 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen13.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen13.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo52_doen` reader - The selected OEN signal for GPIO52. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO52_DOEN_R = crate::FieldReader; #[doc = "Field `gpo52_doen` writer - The selected OEN signal for GPIO52. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO52_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO52_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo53_doen` reader - The selected OEN signal for GPIO53. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO53_DOEN_R = crate::FieldReader; #[doc = "Field `gpo53_doen` writer - The selected OEN signal for GPIO53. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO53_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO53_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo54_doen` reader - The selected OEN signal for GPIO54. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO54_DOEN_R = crate::FieldReader; #[doc = "Field `gpo54_doen` writer - The selected OEN signal for GPIO54. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO54_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO54_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo55_doen` reader - The selected OEN signal for GPIO55. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO55_DOEN_R = crate::FieldReader; #[doc = "Field `gpo55_doen` writer - The selected OEN signal for GPIO55. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO55_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO55_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO52. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO52. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo52_doen(&mut self) -> GPO52_DOEN_W { - GPO52_DOEN_W::new(self) + pub fn gpo52_doen(&mut self) -> GPO52_DOEN_W { + GPO52_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO53. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo53_doen(&mut self) -> GPO53_DOEN_W { - GPO53_DOEN_W::new(self) + pub fn gpo53_doen(&mut self) -> GPO53_DOEN_W { + GPO53_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO54. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo54_doen(&mut self) -> GPO54_DOEN_W { - GPO54_DOEN_W::new(self) + pub fn gpo54_doen(&mut self) -> GPO54_DOEN_W { + GPO54_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO55. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo55_doen(&mut self) -> GPO55_DOEN_W { - GPO55_DOEN_W::new(self) + pub fn gpo55_doen(&mut self) -> GPO55_DOEN_W { + GPO55_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen14.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen14.rs index a188c89..e77e208 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen14.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen14.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo56_doen` reader - The selected OEN signal for GPIO56. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO56_DOEN_R = crate::FieldReader; #[doc = "Field `gpo56_doen` writer - The selected OEN signal for GPIO56. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO56_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO56_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo57_doen` reader - The selected OEN signal for GPIO57. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO57_DOEN_R = crate::FieldReader; #[doc = "Field `gpo57_doen` writer - The selected OEN signal for GPIO57. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO57_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO57_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo58_doen` reader - The selected OEN signal for GPIO58. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO58_DOEN_R = crate::FieldReader; #[doc = "Field `gpo58_doen` writer - The selected OEN signal for GPIO58. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO58_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO58_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo59_doen` reader - The selected OEN signal for GPIO59. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO59_DOEN_R = crate::FieldReader; #[doc = "Field `gpo59_doen` writer - The selected OEN signal for GPIO59. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO59_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO59_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO56. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO56. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo56_doen(&mut self) -> GPO56_DOEN_W { - GPO56_DOEN_W::new(self) + pub fn gpo56_doen(&mut self) -> GPO56_DOEN_W { + GPO56_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO57. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo57_doen(&mut self) -> GPO57_DOEN_W { - GPO57_DOEN_W::new(self) + pub fn gpo57_doen(&mut self) -> GPO57_DOEN_W { + GPO57_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO58. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo58_doen(&mut self) -> GPO58_DOEN_W { - GPO58_DOEN_W::new(self) + pub fn gpo58_doen(&mut self) -> GPO58_DOEN_W { + GPO58_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO59. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo59_doen(&mut self) -> GPO59_DOEN_W { - GPO59_DOEN_W::new(self) + pub fn gpo59_doen(&mut self) -> GPO59_DOEN_W { + GPO59_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen15.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen15.rs index cbb8548..72c085a 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen15.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen15.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo60_doen` reader - The selected OEN signal for GPIO60. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO60_DOEN_R = crate::FieldReader; #[doc = "Field `gpo60_doen` writer - The selected OEN signal for GPIO60. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO60_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO60_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo61_doen` reader - The selected OEN signal for GPIO61. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO61_DOEN_R = crate::FieldReader; #[doc = "Field `gpo61_doen` writer - The selected OEN signal for GPIO61. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO61_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO61_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo62_doen` reader - The selected OEN signal for GPIO62. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO62_DOEN_R = crate::FieldReader; #[doc = "Field `gpo62_doen` writer - The selected OEN signal for GPIO62. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO62_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO62_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo63_doen` reader - The selected OEN signal for GPIO63. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO63_DOEN_R = crate::FieldReader; #[doc = "Field `gpo63_doen` writer - The selected OEN signal for GPIO63. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO63_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO63_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO60. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO60. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo60_doen(&mut self) -> GPO60_DOEN_W { - GPO60_DOEN_W::new(self) + pub fn gpo60_doen(&mut self) -> GPO60_DOEN_W { + GPO60_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO61. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo61_doen(&mut self) -> GPO61_DOEN_W { - GPO61_DOEN_W::new(self) + pub fn gpo61_doen(&mut self) -> GPO61_DOEN_W { + GPO61_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO62. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo62_doen(&mut self) -> GPO62_DOEN_W { - GPO62_DOEN_W::new(self) + pub fn gpo62_doen(&mut self) -> GPO62_DOEN_W { + GPO62_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO63. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo63_doen(&mut self) -> GPO63_DOEN_W { - GPO63_DOEN_W::new(self) + pub fn gpo63_doen(&mut self) -> GPO63_DOEN_W { + GPO63_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen2.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen2.rs index 0ed4ed6..9d72adf 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen2.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen2.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo8_doen` reader - The selected OEN signal for GPIO8. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO8_DOEN_R = crate::FieldReader; #[doc = "Field `gpo8_doen` writer - The selected OEN signal for GPIO8. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO8_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO8_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo9_doen` reader - The selected OEN signal for GPIO9. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO9_DOEN_R = crate::FieldReader; #[doc = "Field `gpo9_doen` writer - The selected OEN signal for GPIO9. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO9_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO9_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo10_doen` reader - The selected OEN signal for GPIO10. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO10_DOEN_R = crate::FieldReader; #[doc = "Field `gpo10_doen` writer - The selected OEN signal for GPIO10. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO10_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO10_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo11_doen` reader - The selected OEN signal for GPIO11. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO11_DOEN_R = crate::FieldReader; #[doc = "Field `gpo11_doen` writer - The selected OEN signal for GPIO11. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO11_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO11_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO8. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO8. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo8_doen(&mut self) -> GPO8_DOEN_W { - GPO8_DOEN_W::new(self) + pub fn gpo8_doen(&mut self) -> GPO8_DOEN_W { + GPO8_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO9. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo9_doen(&mut self) -> GPO9_DOEN_W { - GPO9_DOEN_W::new(self) + pub fn gpo9_doen(&mut self) -> GPO9_DOEN_W { + GPO9_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO10. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo10_doen(&mut self) -> GPO10_DOEN_W { - GPO10_DOEN_W::new(self) + pub fn gpo10_doen(&mut self) -> GPO10_DOEN_W { + GPO10_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO11. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo11_doen(&mut self) -> GPO11_DOEN_W { - GPO11_DOEN_W::new(self) + pub fn gpo11_doen(&mut self) -> GPO11_DOEN_W { + GPO11_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen3.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen3.rs index 2042885..1d666a6 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen3.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen3.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo12_doen` reader - The selected OEN signal for GPIO12. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO12_DOEN_R = crate::FieldReader; #[doc = "Field `gpo12_doen` writer - The selected OEN signal for GPIO12. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO12_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO12_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo13_doen` reader - The selected OEN signal for GPIO13. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO13_DOEN_R = crate::FieldReader; #[doc = "Field `gpo13_doen` writer - The selected OEN signal for GPIO13. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO13_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO13_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo14_doen` reader - The selected OEN signal for GPIO14. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO14_DOEN_R = crate::FieldReader; #[doc = "Field `gpo14_doen` writer - The selected OEN signal for GPIO14. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO14_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO14_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo15_doen` reader - The selected OEN signal for GPIO15. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO15_DOEN_R = crate::FieldReader; #[doc = "Field `gpo15_doen` writer - The selected OEN signal for GPIO15. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO15_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO15_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO12. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO12. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo12_doen(&mut self) -> GPO12_DOEN_W { - GPO12_DOEN_W::new(self) + pub fn gpo12_doen(&mut self) -> GPO12_DOEN_W { + GPO12_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO13. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo13_doen(&mut self) -> GPO13_DOEN_W { - GPO13_DOEN_W::new(self) + pub fn gpo13_doen(&mut self) -> GPO13_DOEN_W { + GPO13_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO14. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo14_doen(&mut self) -> GPO14_DOEN_W { - GPO14_DOEN_W::new(self) + pub fn gpo14_doen(&mut self) -> GPO14_DOEN_W { + GPO14_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO15. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo15_doen(&mut self) -> GPO15_DOEN_W { - GPO15_DOEN_W::new(self) + pub fn gpo15_doen(&mut self) -> GPO15_DOEN_W { + GPO15_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen4.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen4.rs index fd8736f..f34eff2 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen4.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen4.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo16_doen` reader - The selected OEN signal for GPIO16. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO16_DOEN_R = crate::FieldReader; #[doc = "Field `gpo16_doen` writer - The selected OEN signal for GPIO16. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO16_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO16_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo17_doen` reader - The selected OEN signal for GPIO17. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO17_DOEN_R = crate::FieldReader; #[doc = "Field `gpo17_doen` writer - The selected OEN signal for GPIO17. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO17_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO17_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo18_doen` reader - The selected OEN signal for GPIO18. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO18_DOEN_R = crate::FieldReader; #[doc = "Field `gpo18_doen` writer - The selected OEN signal for GPIO18. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO18_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO18_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo19_doen` reader - The selected OEN signal for GPIO19. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO19_DOEN_R = crate::FieldReader; #[doc = "Field `gpo19_doen` writer - The selected OEN signal for GPIO19. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO19_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO19_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO16. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO16. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo16_doen(&mut self) -> GPO16_DOEN_W { - GPO16_DOEN_W::new(self) + pub fn gpo16_doen(&mut self) -> GPO16_DOEN_W { + GPO16_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO17. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo17_doen(&mut self) -> GPO17_DOEN_W { - GPO17_DOEN_W::new(self) + pub fn gpo17_doen(&mut self) -> GPO17_DOEN_W { + GPO17_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO18. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo18_doen(&mut self) -> GPO18_DOEN_W { - GPO18_DOEN_W::new(self) + pub fn gpo18_doen(&mut self) -> GPO18_DOEN_W { + GPO18_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO19. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo19_doen(&mut self) -> GPO19_DOEN_W { - GPO19_DOEN_W::new(self) + pub fn gpo19_doen(&mut self) -> GPO19_DOEN_W { + GPO19_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen5.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen5.rs index d43811a..d7c5e2d 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen5.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen5.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo20_doen` reader - The selected OEN signal for GPIO20. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO20_DOEN_R = crate::FieldReader; #[doc = "Field `gpo20_doen` writer - The selected OEN signal for GPIO20. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO20_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO20_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo21_doen` reader - The selected OEN signal for GPIO21. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO21_DOEN_R = crate::FieldReader; #[doc = "Field `gpo21_doen` writer - The selected OEN signal for GPIO21. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO21_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO21_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo22_doen` reader - The selected OEN signal for GPIO22. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO22_DOEN_R = crate::FieldReader; #[doc = "Field `gpo22_doen` writer - The selected OEN signal for GPIO22. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO22_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO22_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo23_doen` reader - The selected OEN signal for GPIO23. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO23_DOEN_R = crate::FieldReader; #[doc = "Field `gpo23_doen` writer - The selected OEN signal for GPIO23. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO23_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO23_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO20. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO20. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo20_doen(&mut self) -> GPO20_DOEN_W { - GPO20_DOEN_W::new(self) + pub fn gpo20_doen(&mut self) -> GPO20_DOEN_W { + GPO20_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO21. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo21_doen(&mut self) -> GPO21_DOEN_W { - GPO21_DOEN_W::new(self) + pub fn gpo21_doen(&mut self) -> GPO21_DOEN_W { + GPO21_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO22. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo22_doen(&mut self) -> GPO22_DOEN_W { - GPO22_DOEN_W::new(self) + pub fn gpo22_doen(&mut self) -> GPO22_DOEN_W { + GPO22_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO23. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo23_doen(&mut self) -> GPO23_DOEN_W { - GPO23_DOEN_W::new(self) + pub fn gpo23_doen(&mut self) -> GPO23_DOEN_W { + GPO23_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen6.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen6.rs index 268132c..4d11af1 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen6.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen6.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo24_doen` reader - The selected OEN signal for GPIO24. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO24_DOEN_R = crate::FieldReader; #[doc = "Field `gpo24_doen` writer - The selected OEN signal for GPIO24. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO24_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO24_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo25_doen` reader - The selected OEN signal for GPIO25. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO25_DOEN_R = crate::FieldReader; #[doc = "Field `gpo25_doen` writer - The selected OEN signal for GPIO25. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO25_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO25_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo26_doen` reader - The selected OEN signal for GPIO26. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO26_DOEN_R = crate::FieldReader; #[doc = "Field `gpo26_doen` writer - The selected OEN signal for GPIO26. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO26_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO26_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo27_doen` reader - The selected OEN signal for GPIO27. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO27_DOEN_R = crate::FieldReader; #[doc = "Field `gpo27_doen` writer - The selected OEN signal for GPIO27. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO27_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO27_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO24. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO24. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo24_doen(&mut self) -> GPO24_DOEN_W { - GPO24_DOEN_W::new(self) + pub fn gpo24_doen(&mut self) -> GPO24_DOEN_W { + GPO24_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO25. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo25_doen(&mut self) -> GPO25_DOEN_W { - GPO25_DOEN_W::new(self) + pub fn gpo25_doen(&mut self) -> GPO25_DOEN_W { + GPO25_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO26. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo26_doen(&mut self) -> GPO26_DOEN_W { - GPO26_DOEN_W::new(self) + pub fn gpo26_doen(&mut self) -> GPO26_DOEN_W { + GPO26_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO27. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo27_doen(&mut self) -> GPO27_DOEN_W { - GPO27_DOEN_W::new(self) + pub fn gpo27_doen(&mut self) -> GPO27_DOEN_W { + GPO27_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen7.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen7.rs index aba3198..daf7d4b 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen7.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen7.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo28_doen` reader - The selected OEN signal for GPIO28. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO28_DOEN_R = crate::FieldReader; #[doc = "Field `gpo28_doen` writer - The selected OEN signal for GPIO28. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO28_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO28_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo29_doen` reader - The selected OEN signal for GPIO29. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO29_DOEN_R = crate::FieldReader; #[doc = "Field `gpo29_doen` writer - The selected OEN signal for GPIO29. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO29_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO29_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo30_doen` reader - The selected OEN signal for GPIO30. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO30_DOEN_R = crate::FieldReader; #[doc = "Field `gpo30_doen` writer - The selected OEN signal for GPIO30. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO30_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO30_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo31_doen` reader - The selected OEN signal for GPIO31. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO31_DOEN_R = crate::FieldReader; #[doc = "Field `gpo31_doen` writer - The selected OEN signal for GPIO31. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO31_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO31_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO28. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO28. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo28_doen(&mut self) -> GPO28_DOEN_W { - GPO28_DOEN_W::new(self) + pub fn gpo28_doen(&mut self) -> GPO28_DOEN_W { + GPO28_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO29. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo29_doen(&mut self) -> GPO29_DOEN_W { - GPO29_DOEN_W::new(self) + pub fn gpo29_doen(&mut self) -> GPO29_DOEN_W { + GPO29_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO30. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo30_doen(&mut self) -> GPO30_DOEN_W { - GPO30_DOEN_W::new(self) + pub fn gpo30_doen(&mut self) -> GPO30_DOEN_W { + GPO30_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO31. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo31_doen(&mut self) -> GPO31_DOEN_W { - GPO31_DOEN_W::new(self) + pub fn gpo31_doen(&mut self) -> GPO31_DOEN_W { + GPO31_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen8.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen8.rs index 18a42cc..4699ba1 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen8.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen8.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo32_doen` reader - The selected OEN signal for GPIO32. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO32_DOEN_R = crate::FieldReader; #[doc = "Field `gpo32_doen` writer - The selected OEN signal for GPIO32. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO32_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO32_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo33_doen` reader - The selected OEN signal for GPIO33. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO33_DOEN_R = crate::FieldReader; #[doc = "Field `gpo33_doen` writer - The selected OEN signal for GPIO33. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO33_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO33_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo34_doen` reader - The selected OEN signal for GPIO34. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO34_DOEN_R = crate::FieldReader; #[doc = "Field `gpo34_doen` writer - The selected OEN signal for GPIO34. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO34_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO34_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo35_doen` reader - The selected OEN signal for GPIO35. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO35_DOEN_R = crate::FieldReader; #[doc = "Field `gpo35_doen` writer - The selected OEN signal for GPIO35. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO35_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO35_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO32. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO32. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo32_doen(&mut self) -> GPO32_DOEN_W { - GPO32_DOEN_W::new(self) + pub fn gpo32_doen(&mut self) -> GPO32_DOEN_W { + GPO32_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO33. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo33_doen(&mut self) -> GPO33_DOEN_W { - GPO33_DOEN_W::new(self) + pub fn gpo33_doen(&mut self) -> GPO33_DOEN_W { + GPO33_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO34. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo34_doen(&mut self) -> GPO34_DOEN_W { - GPO34_DOEN_W::new(self) + pub fn gpo34_doen(&mut self) -> GPO34_DOEN_W { + GPO34_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO35. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo35_doen(&mut self) -> GPO35_DOEN_W { - GPO35_DOEN_W::new(self) + pub fn gpo35_doen(&mut self) -> GPO35_DOEN_W { + GPO35_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen9.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen9.rs index 79e1f7c..bdf06c9 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen9.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_doen9.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo36_doen` reader - The selected OEN signal for GPIO36. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO36_DOEN_R = crate::FieldReader; #[doc = "Field `gpo36_doen` writer - The selected OEN signal for GPIO36. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO36_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO36_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo37_doen` reader - The selected OEN signal for GPIO37. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO37_DOEN_R = crate::FieldReader; #[doc = "Field `gpo37_doen` writer - The selected OEN signal for GPIO37. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO37_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO37_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo38_doen` reader - The selected OEN signal for GPIO38. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO38_DOEN_R = crate::FieldReader; #[doc = "Field `gpo38_doen` writer - The selected OEN signal for GPIO38. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO38_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO38_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo39_doen` reader - The selected OEN signal for GPIO39. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO39_DOEN_R = crate::FieldReader; #[doc = "Field `gpo39_doen` writer - The selected OEN signal for GPIO39. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO39_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO39_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO36. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO36. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo36_doen(&mut self) -> GPO36_DOEN_W { - GPO36_DOEN_W::new(self) + pub fn gpo36_doen(&mut self) -> GPO36_DOEN_W { + GPO36_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO37. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo37_doen(&mut self) -> GPO37_DOEN_W { - GPO37_DOEN_W::new(self) + pub fn gpo37_doen(&mut self) -> GPO37_DOEN_W { + GPO37_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO38. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo38_doen(&mut self) -> GPO38_DOEN_W { - GPO38_DOEN_W::new(self) + pub fn gpo38_doen(&mut self) -> GPO38_DOEN_W { + GPO38_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO39. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo39_doen(&mut self) -> GPO39_DOEN_W { - GPO39_DOEN_W::new(self) + pub fn gpo39_doen(&mut self) -> GPO39_DOEN_W { + GPO39_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout0_3.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout0_3.rs index c2c0374..d5e6dcc 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout0_3.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout0_3.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo0_dout` reader - The selected output signal for GPIO0. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO0_DOUT_R = crate::FieldReader; #[doc = "Field `gpo0_dout` writer - The selected output signal for GPIO0. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO0_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO0_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo1_dout` reader - The selected output signal for GPIO1. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO1_DOUT_R = crate::FieldReader; #[doc = "Field `gpo1_dout` writer - The selected output signal for GPIO1. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO1_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO1_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo2_dout` reader - The selected output signal for GPIO2. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO2_DOUT_R = crate::FieldReader; #[doc = "Field `gpo2_dout` writer - The selected output signal for GPIO2. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO2_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO2_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo3_dout` reader - The selected output signal for GPIO3. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO3_DOUT_R = crate::FieldReader; #[doc = "Field `gpo3_dout` writer - The selected output signal for GPIO3. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO3_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO3_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO0. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO0. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo0_dout(&mut self) -> GPO0_DOUT_W { - GPO0_DOUT_W::new(self) + pub fn gpo0_dout(&mut self) -> GPO0_DOUT_W { + GPO0_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO1. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo1_dout(&mut self) -> GPO1_DOUT_W { - GPO1_DOUT_W::new(self) + pub fn gpo1_dout(&mut self) -> GPO1_DOUT_W { + GPO1_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO2. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo2_dout(&mut self) -> GPO2_DOUT_W { - GPO2_DOUT_W::new(self) + pub fn gpo2_dout(&mut self) -> GPO2_DOUT_W { + GPO2_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO3. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo3_dout(&mut self) -> GPO3_DOUT_W { - GPO3_DOUT_W::new(self) + pub fn gpo3_dout(&mut self) -> GPO3_DOUT_W { + GPO3_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout12_15.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout12_15.rs index 69aeb9d..14a34aa 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout12_15.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout12_15.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo12_dout` reader - The selected output signal for GPIO12. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO12_DOUT_R = crate::FieldReader; #[doc = "Field `gpo12_dout` writer - The selected output signal for GPIO12. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO12_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO12_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo13_dout` reader - The selected output signal for GPIO13. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO13_DOUT_R = crate::FieldReader; #[doc = "Field `gpo13_dout` writer - The selected output signal for GPIO13. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO13_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO13_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo14_dout` reader - The selected output signal for GPIO14. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO14_DOUT_R = crate::FieldReader; #[doc = "Field `gpo14_dout` writer - The selected output signal for GPIO14. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO14_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO14_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo15_dout` reader - The selected output signal for GPIO15. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO15_DOUT_R = crate::FieldReader; #[doc = "Field `gpo15_dout` writer - The selected output signal for GPIO15. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO15_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO15_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO12. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO12. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo12_dout(&mut self) -> GPO12_DOUT_W { - GPO12_DOUT_W::new(self) + pub fn gpo12_dout(&mut self) -> GPO12_DOUT_W { + GPO12_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO13. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo13_dout(&mut self) -> GPO13_DOUT_W { - GPO13_DOUT_W::new(self) + pub fn gpo13_dout(&mut self) -> GPO13_DOUT_W { + GPO13_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO14. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo14_dout(&mut self) -> GPO14_DOUT_W { - GPO14_DOUT_W::new(self) + pub fn gpo14_dout(&mut self) -> GPO14_DOUT_W { + GPO14_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO15. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo15_dout(&mut self) -> GPO15_DOUT_W { - GPO15_DOUT_W::new(self) + pub fn gpo15_dout(&mut self) -> GPO15_DOUT_W { + GPO15_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout16_19.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout16_19.rs index 135d213..f1ed52a 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout16_19.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout16_19.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo16_dout` reader - The selected output signal for GPIO16. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO16_DOUT_R = crate::FieldReader; #[doc = "Field `gpo16_dout` writer - The selected output signal for GPIO16. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO16_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO16_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo17_dout` reader - The selected output signal for GPIO17. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO17_DOUT_R = crate::FieldReader; #[doc = "Field `gpo17_dout` writer - The selected output signal for GPIO17. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO17_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO17_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo18_dout` reader - The selected output signal for GPIO18. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO18_DOUT_R = crate::FieldReader; #[doc = "Field `gpo18_dout` writer - The selected output signal for GPIO18. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO18_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO18_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo19_dout` reader - The selected output signal for GPIO19. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO19_DOUT_R = crate::FieldReader; #[doc = "Field `gpo19_dout` writer - The selected output signal for GPIO19. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO19_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO19_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO16. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO16. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo16_dout(&mut self) -> GPO16_DOUT_W { - GPO16_DOUT_W::new(self) + pub fn gpo16_dout(&mut self) -> GPO16_DOUT_W { + GPO16_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO17. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo17_dout(&mut self) -> GPO17_DOUT_W { - GPO17_DOUT_W::new(self) + pub fn gpo17_dout(&mut self) -> GPO17_DOUT_W { + GPO17_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO18. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo18_dout(&mut self) -> GPO18_DOUT_W { - GPO18_DOUT_W::new(self) + pub fn gpo18_dout(&mut self) -> GPO18_DOUT_W { + GPO18_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO19. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo19_dout(&mut self) -> GPO19_DOUT_W { - GPO19_DOUT_W::new(self) + pub fn gpo19_dout(&mut self) -> GPO19_DOUT_W { + GPO19_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout20_23.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout20_23.rs index f25d49f..934ce6d 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout20_23.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout20_23.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo20_dout` reader - The selected output signal for GPIO20. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO20_DOUT_R = crate::FieldReader; #[doc = "Field `gpo20_dout` writer - The selected output signal for GPIO20. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO20_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO20_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo21_dout` reader - The selected output signal for GPIO21. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO21_DOUT_R = crate::FieldReader; #[doc = "Field `gpo21_dout` writer - The selected output signal for GPIO21. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO21_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO21_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo22_dout` reader - The selected output signal for GPIO22. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO22_DOUT_R = crate::FieldReader; #[doc = "Field `gpo22_dout` writer - The selected output signal for GPIO22. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO22_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO22_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo23_dout` reader - The selected output signal for GPIO23. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO23_DOUT_R = crate::FieldReader; #[doc = "Field `gpo23_dout` writer - The selected output signal for GPIO23. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO23_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO23_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO20. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO20. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo20_dout(&mut self) -> GPO20_DOUT_W { - GPO20_DOUT_W::new(self) + pub fn gpo20_dout(&mut self) -> GPO20_DOUT_W { + GPO20_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO21. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo21_dout(&mut self) -> GPO21_DOUT_W { - GPO21_DOUT_W::new(self) + pub fn gpo21_dout(&mut self) -> GPO21_DOUT_W { + GPO21_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO22. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo22_dout(&mut self) -> GPO22_DOUT_W { - GPO22_DOUT_W::new(self) + pub fn gpo22_dout(&mut self) -> GPO22_DOUT_W { + GPO22_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO23. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo23_dout(&mut self) -> GPO23_DOUT_W { - GPO23_DOUT_W::new(self) + pub fn gpo23_dout(&mut self) -> GPO23_DOUT_W { + GPO23_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout24_27.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout24_27.rs index 53f5b77..c726dc4 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout24_27.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout24_27.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo24_dout` reader - The selected output signal for GPIO24. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO24_DOUT_R = crate::FieldReader; #[doc = "Field `gpo24_dout` writer - The selected output signal for GPIO24. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO24_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO24_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo25_dout` reader - The selected output signal for GPIO25. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO25_DOUT_R = crate::FieldReader; #[doc = "Field `gpo25_dout` writer - The selected output signal for GPIO25. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO25_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO25_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo26_dout` reader - The selected output signal for GPIO26. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO26_DOUT_R = crate::FieldReader; #[doc = "Field `gpo26_dout` writer - The selected output signal for GPIO26. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO26_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO26_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo27_dout` reader - The selected output signal for GPIO27. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO27_DOUT_R = crate::FieldReader; #[doc = "Field `gpo27_dout` writer - The selected output signal for GPIO27. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO27_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO27_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO24. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO24. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo24_dout(&mut self) -> GPO24_DOUT_W { - GPO24_DOUT_W::new(self) + pub fn gpo24_dout(&mut self) -> GPO24_DOUT_W { + GPO24_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO25. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo25_dout(&mut self) -> GPO25_DOUT_W { - GPO25_DOUT_W::new(self) + pub fn gpo25_dout(&mut self) -> GPO25_DOUT_W { + GPO25_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO26. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo26_dout(&mut self) -> GPO26_DOUT_W { - GPO26_DOUT_W::new(self) + pub fn gpo26_dout(&mut self) -> GPO26_DOUT_W { + GPO26_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO27. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo27_dout(&mut self) -> GPO27_DOUT_W { - GPO27_DOUT_W::new(self) + pub fn gpo27_dout(&mut self) -> GPO27_DOUT_W { + GPO27_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout28_31.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout28_31.rs index 9a9ce42..a7602a2 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout28_31.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout28_31.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo28_dout` reader - The selected output signal for GPIO28. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO28_DOUT_R = crate::FieldReader; #[doc = "Field `gpo28_dout` writer - The selected output signal for GPIO28. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO28_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO28_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo29_dout` reader - The selected output signal for GPIO29. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO29_DOUT_R = crate::FieldReader; #[doc = "Field `gpo29_dout` writer - The selected output signal for GPIO29. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO29_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO29_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo30_dout` reader - The selected output signal for GPIO30. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO30_DOUT_R = crate::FieldReader; #[doc = "Field `gpo30_dout` writer - The selected output signal for GPIO30. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO30_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO30_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo31_dout` reader - The selected output signal for GPIO31. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO31_DOUT_R = crate::FieldReader; #[doc = "Field `gpo31_dout` writer - The selected output signal for GPIO31. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO31_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO31_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO28. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO28. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo28_dout(&mut self) -> GPO28_DOUT_W { - GPO28_DOUT_W::new(self) + pub fn gpo28_dout(&mut self) -> GPO28_DOUT_W { + GPO28_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO29. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo29_dout(&mut self) -> GPO29_DOUT_W { - GPO29_DOUT_W::new(self) + pub fn gpo29_dout(&mut self) -> GPO29_DOUT_W { + GPO29_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO30. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo30_dout(&mut self) -> GPO30_DOUT_W { - GPO30_DOUT_W::new(self) + pub fn gpo30_dout(&mut self) -> GPO30_DOUT_W { + GPO30_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO31. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo31_dout(&mut self) -> GPO31_DOUT_W { - GPO31_DOUT_W::new(self) + pub fn gpo31_dout(&mut self) -> GPO31_DOUT_W { + GPO31_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout32_35.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout32_35.rs index 9394568..fc44c0c 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout32_35.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout32_35.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo32_dout` reader - The selected output signal for GPIO32. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO32_DOUT_R = crate::FieldReader; #[doc = "Field `gpo32_dout` writer - The selected output signal for GPIO32. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO32_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO32_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo33_dout` reader - The selected output signal for GPIO33. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO33_DOUT_R = crate::FieldReader; #[doc = "Field `gpo33_dout` writer - The selected output signal for GPIO33. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO33_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO33_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo34_dout` reader - The selected output signal for GPIO34. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO34_DOUT_R = crate::FieldReader; #[doc = "Field `gpo34_dout` writer - The selected output signal for GPIO34. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO34_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO34_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo35_dout` reader - The selected output signal for GPIO35. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO35_DOUT_R = crate::FieldReader; #[doc = "Field `gpo35_dout` writer - The selected output signal for GPIO35. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO35_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO35_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO32. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO32. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo32_dout(&mut self) -> GPO32_DOUT_W { - GPO32_DOUT_W::new(self) + pub fn gpo32_dout(&mut self) -> GPO32_DOUT_W { + GPO32_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO33. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo33_dout(&mut self) -> GPO33_DOUT_W { - GPO33_DOUT_W::new(self) + pub fn gpo33_dout(&mut self) -> GPO33_DOUT_W { + GPO33_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO34. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo34_dout(&mut self) -> GPO34_DOUT_W { - GPO34_DOUT_W::new(self) + pub fn gpo34_dout(&mut self) -> GPO34_DOUT_W { + GPO34_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO35. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo35_dout(&mut self) -> GPO35_DOUT_W { - GPO35_DOUT_W::new(self) + pub fn gpo35_dout(&mut self) -> GPO35_DOUT_W { + GPO35_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout36_39.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout36_39.rs index 3559b5b..2680766 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout36_39.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout36_39.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo36_dout` reader - The selected output signal for GPIO36. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO36_DOUT_R = crate::FieldReader; #[doc = "Field `gpo36_dout` writer - The selected output signal for GPIO36. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO36_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO36_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo37_dout` reader - The selected output signal for GPIO37. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO37_DOUT_R = crate::FieldReader; #[doc = "Field `gpo37_dout` writer - The selected output signal for GPIO37. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO37_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO37_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo38_dout` reader - The selected output signal for GPIO38. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO38_DOUT_R = crate::FieldReader; #[doc = "Field `gpo38_dout` writer - The selected output signal for GPIO38. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO38_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO38_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo39_dout` reader - The selected output signal for GPIO39. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO39_DOUT_R = crate::FieldReader; #[doc = "Field `gpo39_dout` writer - The selected output signal for GPIO39. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO39_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO39_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO36. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO36. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo36_dout(&mut self) -> GPO36_DOUT_W { - GPO36_DOUT_W::new(self) + pub fn gpo36_dout(&mut self) -> GPO36_DOUT_W { + GPO36_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO37. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo37_dout(&mut self) -> GPO37_DOUT_W { - GPO37_DOUT_W::new(self) + pub fn gpo37_dout(&mut self) -> GPO37_DOUT_W { + GPO37_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO38. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo38_dout(&mut self) -> GPO38_DOUT_W { - GPO38_DOUT_W::new(self) + pub fn gpo38_dout(&mut self) -> GPO38_DOUT_W { + GPO38_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO39. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo39_dout(&mut self) -> GPO39_DOUT_W { - GPO39_DOUT_W::new(self) + pub fn gpo39_dout(&mut self) -> GPO39_DOUT_W { + GPO39_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout40_43.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout40_43.rs index 1327fa5..319a8f3 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout40_43.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout40_43.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo40_dout` reader - The selected output signal for GPIO40. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO40_DOUT_R = crate::FieldReader; #[doc = "Field `gpo40_dout` writer - The selected output signal for GPIO40. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO40_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO40_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo41_dout` reader - The selected output signal for GPIO41. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO41_DOUT_R = crate::FieldReader; #[doc = "Field `gpo41_dout` writer - The selected output signal for GPIO41. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO41_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO41_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo42_dout` reader - The selected output signal for GPIO42. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO42_DOUT_R = crate::FieldReader; #[doc = "Field `gpo42_dout` writer - The selected output signal for GPIO42. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO42_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO42_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo43_dout` reader - The selected output signal for GPIO43. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO43_DOUT_R = crate::FieldReader; #[doc = "Field `gpo43_dout` writer - The selected output signal for GPIO43. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO43_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO43_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO40. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO40. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo40_dout(&mut self) -> GPO40_DOUT_W { - GPO40_DOUT_W::new(self) + pub fn gpo40_dout(&mut self) -> GPO40_DOUT_W { + GPO40_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO41. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo41_dout(&mut self) -> GPO41_DOUT_W { - GPO41_DOUT_W::new(self) + pub fn gpo41_dout(&mut self) -> GPO41_DOUT_W { + GPO41_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO42. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo42_dout(&mut self) -> GPO42_DOUT_W { - GPO42_DOUT_W::new(self) + pub fn gpo42_dout(&mut self) -> GPO42_DOUT_W { + GPO42_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO43. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo43_dout(&mut self) -> GPO43_DOUT_W { - GPO43_DOUT_W::new(self) + pub fn gpo43_dout(&mut self) -> GPO43_DOUT_W { + GPO43_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout44_47.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout44_47.rs index 1c11381..c1e605b 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout44_47.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout44_47.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo44_dout` reader - The selected output signal for GPIO44. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO44_DOUT_R = crate::FieldReader; #[doc = "Field `gpo44_dout` writer - The selected output signal for GPIO44. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO44_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO44_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo45_dout` reader - The selected output signal for GPIO45. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO45_DOUT_R = crate::FieldReader; #[doc = "Field `gpo45_dout` writer - The selected output signal for GPIO45. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO45_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO45_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo46_dout` reader - The selected output signal for GPIO46. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO46_DOUT_R = crate::FieldReader; #[doc = "Field `gpo46_dout` writer - The selected output signal for GPIO46. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO46_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO46_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo47_dout` reader - The selected output signal for GPIO47. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO47_DOUT_R = crate::FieldReader; #[doc = "Field `gpo47_dout` writer - The selected output signal for GPIO47. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO47_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO47_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO44. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO44. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo44_dout(&mut self) -> GPO44_DOUT_W { - GPO44_DOUT_W::new(self) + pub fn gpo44_dout(&mut self) -> GPO44_DOUT_W { + GPO44_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO45. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo45_dout(&mut self) -> GPO45_DOUT_W { - GPO45_DOUT_W::new(self) + pub fn gpo45_dout(&mut self) -> GPO45_DOUT_W { + GPO45_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO46. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo46_dout(&mut self) -> GPO46_DOUT_W { - GPO46_DOUT_W::new(self) + pub fn gpo46_dout(&mut self) -> GPO46_DOUT_W { + GPO46_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO47. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo47_dout(&mut self) -> GPO47_DOUT_W { - GPO47_DOUT_W::new(self) + pub fn gpo47_dout(&mut self) -> GPO47_DOUT_W { + GPO47_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout48_51.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout48_51.rs index 4bfcc12..968917b 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout48_51.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout48_51.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo48_dout` reader - The selected output signal for GPIO48. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO48_DOUT_R = crate::FieldReader; #[doc = "Field `gpo48_dout` writer - The selected output signal for GPIO48. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO48_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO48_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo49_dout` reader - The selected output signal for GPIO49. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO49_DOUT_R = crate::FieldReader; #[doc = "Field `gpo49_dout` writer - The selected output signal for GPIO49. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO49_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO49_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo50_dout` reader - The selected output signal for GPIO50. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO50_DOUT_R = crate::FieldReader; #[doc = "Field `gpo50_dout` writer - The selected output signal for GPIO50. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO50_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO50_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo51_dout` reader - The selected output signal for GPIO51. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO51_DOUT_R = crate::FieldReader; #[doc = "Field `gpo51_dout` writer - The selected output signal for GPIO51. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO51_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO51_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO48. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO48. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo48_dout(&mut self) -> GPO48_DOUT_W { - GPO48_DOUT_W::new(self) + pub fn gpo48_dout(&mut self) -> GPO48_DOUT_W { + GPO48_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO49. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo49_dout(&mut self) -> GPO49_DOUT_W { - GPO49_DOUT_W::new(self) + pub fn gpo49_dout(&mut self) -> GPO49_DOUT_W { + GPO49_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO50. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo50_dout(&mut self) -> GPO50_DOUT_W { - GPO50_DOUT_W::new(self) + pub fn gpo50_dout(&mut self) -> GPO50_DOUT_W { + GPO50_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO51. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo51_dout(&mut self) -> GPO51_DOUT_W { - GPO51_DOUT_W::new(self) + pub fn gpo51_dout(&mut self) -> GPO51_DOUT_W { + GPO51_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout4_7.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout4_7.rs index aa20f2c..4b551a6 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout4_7.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout4_7.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo4_dout` reader - The selected output signal for GPIO4. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO4_DOUT_R = crate::FieldReader; #[doc = "Field `gpo4_dout` writer - The selected output signal for GPIO4. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO4_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO4_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo5_dout` reader - The selected output signal for GPIO5. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO5_DOUT_R = crate::FieldReader; #[doc = "Field `gpo5_dout` writer - The selected output signal for GPIO5. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO5_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO5_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo6_dout` reader - The selected output signal for GPIO6. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO6_DOUT_R = crate::FieldReader; #[doc = "Field `gpo6_dout` writer - The selected output signal for GPIO6. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO6_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO6_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo7_dout` reader - The selected output signal for GPIO7. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO7_DOUT_R = crate::FieldReader; #[doc = "Field `gpo7_dout` writer - The selected output signal for GPIO7. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO7_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO7_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO4. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO4. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo4_dout(&mut self) -> GPO4_DOUT_W { - GPO4_DOUT_W::new(self) + pub fn gpo4_dout(&mut self) -> GPO4_DOUT_W { + GPO4_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO5. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo5_dout(&mut self) -> GPO5_DOUT_W { - GPO5_DOUT_W::new(self) + pub fn gpo5_dout(&mut self) -> GPO5_DOUT_W { + GPO5_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO6. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo6_dout(&mut self) -> GPO6_DOUT_W { - GPO6_DOUT_W::new(self) + pub fn gpo6_dout(&mut self) -> GPO6_DOUT_W { + GPO6_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO7. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo7_dout(&mut self) -> GPO7_DOUT_W { - GPO7_DOUT_W::new(self) + pub fn gpo7_dout(&mut self) -> GPO7_DOUT_W { + GPO7_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout52_55.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout52_55.rs index 82a7b94..7c19921 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout52_55.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout52_55.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo52_dout` reader - The selected output signal for GPIO52. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO52_DOUT_R = crate::FieldReader; #[doc = "Field `gpo52_dout` writer - The selected output signal for GPIO52. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO52_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO52_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo53_dout` reader - The selected output signal for GPIO53. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO53_DOUT_R = crate::FieldReader; #[doc = "Field `gpo53_dout` writer - The selected output signal for GPIO53. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO53_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO53_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo54_dout` reader - The selected output signal for GPIO54. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO54_DOUT_R = crate::FieldReader; #[doc = "Field `gpo54_dout` writer - The selected output signal for GPIO54. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO54_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO54_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo55_dout` reader - The selected output signal for GPIO55. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO55_DOUT_R = crate::FieldReader; #[doc = "Field `gpo55_dout` writer - The selected output signal for GPIO55. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO55_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO55_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO52. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO52. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo52_dout(&mut self) -> GPO52_DOUT_W { - GPO52_DOUT_W::new(self) + pub fn gpo52_dout(&mut self) -> GPO52_DOUT_W { + GPO52_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO53. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo53_dout(&mut self) -> GPO53_DOUT_W { - GPO53_DOUT_W::new(self) + pub fn gpo53_dout(&mut self) -> GPO53_DOUT_W { + GPO53_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO54. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo54_dout(&mut self) -> GPO54_DOUT_W { - GPO54_DOUT_W::new(self) + pub fn gpo54_dout(&mut self) -> GPO54_DOUT_W { + GPO54_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO55. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo55_dout(&mut self) -> GPO55_DOUT_W { - GPO55_DOUT_W::new(self) + pub fn gpo55_dout(&mut self) -> GPO55_DOUT_W { + GPO55_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout56_59.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout56_59.rs index 3d26174..c5f9a92 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout56_59.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout56_59.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo56_dout` reader - The selected output signal for GPIO56. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO56_DOUT_R = crate::FieldReader; #[doc = "Field `gpo56_dout` writer - The selected output signal for GPIO56. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO56_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO56_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo57_dout` reader - The selected output signal for GPIO57. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO57_DOUT_R = crate::FieldReader; #[doc = "Field `gpo57_dout` writer - The selected output signal for GPIO57. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO57_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO57_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo58_dout` reader - The selected output signal for GPIO58. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO58_DOUT_R = crate::FieldReader; #[doc = "Field `gpo58_dout` writer - The selected output signal for GPIO58. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO58_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO58_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo59_dout` reader - The selected output signal for GPIO59. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO59_DOUT_R = crate::FieldReader; #[doc = "Field `gpo59_dout` writer - The selected output signal for GPIO59. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO59_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO59_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO56. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO56. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo56_dout(&mut self) -> GPO56_DOUT_W { - GPO56_DOUT_W::new(self) + pub fn gpo56_dout(&mut self) -> GPO56_DOUT_W { + GPO56_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO57. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo57_dout(&mut self) -> GPO57_DOUT_W { - GPO57_DOUT_W::new(self) + pub fn gpo57_dout(&mut self) -> GPO57_DOUT_W { + GPO57_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO58. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo58_dout(&mut self) -> GPO58_DOUT_W { - GPO58_DOUT_W::new(self) + pub fn gpo58_dout(&mut self) -> GPO58_DOUT_W { + GPO58_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO59. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo59_dout(&mut self) -> GPO59_DOUT_W { - GPO59_DOUT_W::new(self) + pub fn gpo59_dout(&mut self) -> GPO59_DOUT_W { + GPO59_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout60_63.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout60_63.rs index a194de2..ceccb90 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout60_63.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout60_63.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo60_dout` reader - The selected output signal for GPIO60. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO60_DOUT_R = crate::FieldReader; #[doc = "Field `gpo60_dout` writer - The selected output signal for GPIO60. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO60_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO60_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo61_dout` reader - The selected output signal for GPIO61. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO61_DOUT_R = crate::FieldReader; #[doc = "Field `gpo61_dout` writer - The selected output signal for GPIO61. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO61_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO61_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo62_dout` reader - The selected output signal for GPIO62. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO62_DOUT_R = crate::FieldReader; #[doc = "Field `gpo62_dout` writer - The selected output signal for GPIO62. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO62_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO62_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo63_dout` reader - The selected output signal for GPIO63. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO63_DOUT_R = crate::FieldReader; #[doc = "Field `gpo63_dout` writer - The selected output signal for GPIO63. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO63_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO63_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO60. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO60. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo60_dout(&mut self) -> GPO60_DOUT_W { - GPO60_DOUT_W::new(self) + pub fn gpo60_dout(&mut self) -> GPO60_DOUT_W { + GPO60_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO61. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo61_dout(&mut self) -> GPO61_DOUT_W { - GPO61_DOUT_W::new(self) + pub fn gpo61_dout(&mut self) -> GPO61_DOUT_W { + GPO61_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO62. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo62_dout(&mut self) -> GPO62_DOUT_W { - GPO62_DOUT_W::new(self) + pub fn gpo62_dout(&mut self) -> GPO62_DOUT_W { + GPO62_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO63. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo63_dout(&mut self) -> GPO63_DOUT_W { - GPO63_DOUT_W::new(self) + pub fn gpo63_dout(&mut self) -> GPO63_DOUT_W { + GPO63_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout8_11.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout8_11.rs index 88c763e..c03d2cb 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout8_11.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/gpo_dout8_11.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo8_dout` reader - The selected output signal for GPIO8. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO8_DOUT_R = crate::FieldReader; #[doc = "Field `gpo8_dout` writer - The selected output signal for GPIO8. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO8_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO8_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo9_dout` reader - The selected output signal for GPIO9. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO9_DOUT_R = crate::FieldReader; #[doc = "Field `gpo9_dout` writer - The selected output signal for GPIO9. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO9_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO9_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo10_dout` reader - The selected output signal for GPIO10. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO10_DOUT_R = crate::FieldReader; #[doc = "Field `gpo10_dout` writer - The selected output signal for GPIO10. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO10_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO10_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo11_dout` reader - The selected output signal for GPIO11. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO11_DOUT_R = crate::FieldReader; #[doc = "Field `gpo11_dout` writer - The selected output signal for GPIO11. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO11_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO11_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO8. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO8. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo8_dout(&mut self) -> GPO8_DOUT_W { - GPO8_DOUT_W::new(self) + pub fn gpo8_dout(&mut self) -> GPO8_DOUT_W { + GPO8_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO9. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo9_dout(&mut self) -> GPO9_DOUT_W { - GPO9_DOUT_W::new(self) + pub fn gpo9_dout(&mut self) -> GPO9_DOUT_W { + GPO9_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO10. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo10_dout(&mut self) -> GPO10_DOUT_W { - GPO10_DOUT_W::new(self) + pub fn gpo10_dout(&mut self) -> GPO10_DOUT_W { + GPO10_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO11. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo11_dout(&mut self) -> GPO11_DOUT_W { - GPO11_DOUT_W::new(self) + pub fn gpo11_dout(&mut self) -> GPO11_DOUT_W { + GPO11_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq0.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq0.rs index 5dabb1a..9c32a14 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq0.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioen0` reader - 1: Enable, 0: Disable"] pub type GPIOEN0_R = crate::BitReader; #[doc = "Field `gpioen0` writer - 1: Enable, 0: Disable"] -pub type GPIOEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GPIOEN0_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Enable, 0: Disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - 1: Enable, 0: Disable"] #[inline(always)] #[must_use] - pub fn gpioen0(&mut self) -> GPIOEN0_W { - GPIOEN0_W::new(self) + pub fn gpioen0(&mut self) -> GPIOEN0_W { + GPIOEN0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq1.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq1.rs index c4125fc..21e7c76 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq1.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq1.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpiois0` reader - 1: Edge trigger, 0: Level trigger"] pub type GPIOIS0_R = crate::FieldReader; #[doc = "Field `gpiois0` writer - 1: Edge trigger, 0: Level trigger"] -pub type GPIOIS0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIS0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Edge trigger, 0: Level trigger"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Edge trigger, 0: Level trigger"] #[inline(always)] #[must_use] - pub fn gpiois0(&mut self) -> GPIOIS0_W { - GPIOIS0_W::new(self) + pub fn gpiois0(&mut self) -> GPIOIS0_W { + GPIOIS0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq10.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq10.rs index 6d92d98..f7d0b50 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq10.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq10.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioie1` reader - 1: Unmask, 0: Mask"] pub type GPIOIE1_R = crate::FieldReader; #[doc = "Field `gpioie1` writer - 1: Unmask, 0: Mask"] -pub type GPIOIE1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIE1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Unmask, 0: Mask"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Unmask, 0: Mask"] #[inline(always)] #[must_use] - pub fn gpioie1(&mut self) -> GPIOIE1_W { - GPIOIE1_W::new(self) + pub fn gpioie1(&mut self) -> GPIOIE1_W { + GPIOIE1_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq11.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq11.rs index a803bb2..630d5ce 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq11.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq11.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq12.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq12.rs index aff6604..573a724 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq12.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq12.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq13.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq13.rs index 15ae39d..54fd284 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq13.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq13.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq14.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq14.rs index e7a78ea..282a5d5 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq14.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq14.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq15.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq15.rs index fa51ba0..37a81b6 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq15.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq15.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq16.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq16.rs index 96972ea..8702079 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq16.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq16.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq2.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq2.rs index ae2e69c..f9c0d5b 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq2.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq2.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpiois1` reader - 1: Edge trigger, 0: Level trigger"] pub type GPIOIS1_R = crate::FieldReader; #[doc = "Field `gpiois1` writer - 1: Edge trigger, 0: Level trigger"] -pub type GPIOIS1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIS1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Edge trigger, 0: Level trigger"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Edge trigger, 0: Level trigger"] #[inline(always)] #[must_use] - pub fn gpiois1(&mut self) -> GPIOIS1_W { - GPIOIS1_W::new(self) + pub fn gpiois1(&mut self) -> GPIOIS1_W { + GPIOIS1_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq3.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq3.rs index 0570e0f..66b771c 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq3.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq3.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioic0` reader - 1: Do not clear the register, 0: Clear the register"] pub type GPIOIC0_R = crate::FieldReader; #[doc = "Field `gpioic0` writer - 1: Do not clear the register, 0: Clear the register"] -pub type GPIOIC0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIC0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Do not clear the register, 0: Clear the register"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Do not clear the register, 0: Clear the register"] #[inline(always)] #[must_use] - pub fn gpioic0(&mut self) -> GPIOIC0_W { - GPIOIC0_W::new(self) + pub fn gpioic0(&mut self) -> GPIOIC0_W { + GPIOIC0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq4.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq4.rs index 117401a..3c70b23 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq4.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq4.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioic1` reader - 1: Do not clear the register, 0: Clear the register"] pub type GPIOIC1_R = crate::FieldReader; #[doc = "Field `gpioic1` writer - 1: Do not clear the register, 0: Clear the register"] -pub type GPIOIC1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIC1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Do not clear the register, 0: Clear the register"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Do not clear the register, 0: Clear the register"] #[inline(always)] #[must_use] - pub fn gpioic1(&mut self) -> GPIOIC1_W { - GPIOIC1_W::new(self) + pub fn gpioic1(&mut self) -> GPIOIC1_W { + GPIOIC1_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq5.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq5.rs index 2c4f469..c84f6be 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq5.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq5.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioibe0` reader - 1: Trigger on both edges, 0: Trigger on a single edge"] pub type GPIOIBE0_R = crate::FieldReader; #[doc = "Field `gpioibe0` writer - 1: Trigger on both edges, 0: Trigger on a single edge"] -pub type GPIOIBE0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIBE0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Trigger on both edges, 0: Trigger on a single edge"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Trigger on both edges, 0: Trigger on a single edge"] #[inline(always)] #[must_use] - pub fn gpioibe0(&mut self) -> GPIOIBE0_W { - GPIOIBE0_W::new(self) + pub fn gpioibe0(&mut self) -> GPIOIBE0_W { + GPIOIBE0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq6.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq6.rs index 35cdfc0..e819d84 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq6.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq6.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioibe1` reader - 1: Trigger on both edges, 0: Trigger on a single edge"] pub type GPIOIBE1_R = crate::FieldReader; #[doc = "Field `gpioibe1` writer - 1: Trigger on both edges, 0: Trigger on a single edge"] -pub type GPIOIBE1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIBE1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Trigger on both edges, 0: Trigger on a single edge"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Trigger on both edges, 0: Trigger on a single edge"] #[inline(always)] #[must_use] - pub fn gpioibe1(&mut self) -> GPIOIBE1_W { - GPIOIBE1_W::new(self) + pub fn gpioibe1(&mut self) -> GPIOIBE1_W { + GPIOIBE1_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq7.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq7.rs index d20e458..1457ca7 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq7.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq7.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioiev0` reader - 1: Positive/Low, 0: Negative/High"] pub type GPIOIEV0_R = crate::FieldReader; #[doc = "Field `gpioiev0` writer - 1: Positive/Low, 0: Negative/High"] -pub type GPIOIEV0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIEV0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Positive/Low, 0: Negative/High"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Positive/Low, 0: Negative/High"] #[inline(always)] #[must_use] - pub fn gpioiev0(&mut self) -> GPIOIEV0_W { - GPIOIEV0_W::new(self) + pub fn gpioiev0(&mut self) -> GPIOIEV0_W { + GPIOIEV0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq8.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq8.rs index 74f6862..d9affb5 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq8.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq8.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioiev1` reader - 1: Positive/Low, 0: Negative/High"] pub type GPIOIEV1_R = crate::FieldReader; #[doc = "Field `gpioiev1` writer - 1: Positive/Low, 0: Negative/High"] -pub type GPIOIEV1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIEV1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Positive/Low, 0: Negative/High"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Positive/Low, 0: Negative/High"] #[inline(always)] #[must_use] - pub fn gpioiev1(&mut self) -> GPIOIEV1_W { - GPIOIEV1_W::new(self) + pub fn gpioiev1(&mut self) -> GPIOIEV1_W { + GPIOIEV1_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq9.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq9.rs index 48825b8..0bd97f9 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq9.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/ioirq9.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioie0` reader - 1: Unmask, 0: Mask"] pub type GPIOIE0_R = crate::FieldReader; #[doc = "Field `gpioie0` writer - 1: Unmask, 0: Mask"] -pub type GPIOIE0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIE0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Unmask, 0: Mask"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Unmask, 0: Mask"] #[inline(always)] #[must_use] - pub fn gpioie0(&mut self) -> GPIOIE0_W { - GPIOIE0_W::new(self) + pub fn gpioie0(&mut self) -> GPIOIE0_W { + GPIOIE0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_mdc_syscon.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_mdc_syscon.rs index 3a9dede..a7811d1 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_mdc_syscon.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_mdc_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_mdc_syscon` reader - padcfg_pad_gmac1_mdc_syscon"] pub type PADCFG_PAD_GMAC1_MDC_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_mdc_syscon` writer - padcfg_pad_gmac1_mdc_syscon"] -pub type PADCFG_PAD_GMAC1_MDC_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_MDC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_mdc_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_mdc_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_MDC_SYSCON_W { - PADCFG_PAD_GMAC1_MDC_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_MDC_SYSCON_W { + PADCFG_PAD_GMAC1_MDC_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_mdio_syscon.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_mdio_syscon.rs index eb9b718..4af4342 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_mdio_syscon.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_mdio_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_mdio_syscon` reader - padcfg_pad_gmac1_mdio_syscon"] pub type PADCFG_PAD_GMAC1_MDIO_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_mdio_syscon` writer - padcfg_pad_gmac1_mdio_syscon"] -pub type PADCFG_PAD_GMAC1_MDIO_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_MDIO_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_mdio_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_mdio_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_MDIO_SYSCON_W { - PADCFG_PAD_GMAC1_MDIO_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_MDIO_SYSCON_W { + PADCFG_PAD_GMAC1_MDIO_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxc_syscon.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxc_syscon.rs index 0017a23..83d7c93 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxc_syscon.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxc_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_rxc_syscon` reader - padcfg_pad_gmac1_rxc_syscon"] pub type PADCFG_PAD_GMAC1_RXC_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_rxc_syscon` writer - padcfg_pad_gmac1_rxc_syscon"] -pub type PADCFG_PAD_GMAC1_RXC_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_RXC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_rxc_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_rxc_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_RXC_SYSCON_W { - PADCFG_PAD_GMAC1_RXC_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_RXC_SYSCON_W { + PADCFG_PAD_GMAC1_RXC_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxd0_syscon.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxd0_syscon.rs index abe22a6..f614bf5 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxd0_syscon.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxd0_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_rxd0_syscon` reader - padcfg_pad_gmac1_rxd0_syscon"] pub type PADCFG_PAD_GMAC1_RXD0_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_rxd0_syscon` writer - padcfg_pad_gmac1_rxd0_syscon"] -pub type PADCFG_PAD_GMAC1_RXD0_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_RXD0_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_rxd0_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_rxd0_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_RXD0_SYSCON_W { - PADCFG_PAD_GMAC1_RXD0_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_RXD0_SYSCON_W { + PADCFG_PAD_GMAC1_RXD0_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxd1_syscon.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxd1_syscon.rs index 8d2ac5b..0075b2e 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxd1_syscon.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxd1_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_rxd1_syscon` reader - padcfg_pad_gmac1_rxd1_syscon"] pub type PADCFG_PAD_GMAC1_RXD1_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_rxd1_syscon` writer - padcfg_pad_gmac1_rxd1_syscon"] -pub type PADCFG_PAD_GMAC1_RXD1_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_RXD1_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_rxd1_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_rxd1_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_RXD1_SYSCON_W { - PADCFG_PAD_GMAC1_RXD1_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_RXD1_SYSCON_W { + PADCFG_PAD_GMAC1_RXD1_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxd2_syscon.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxd2_syscon.rs index 9459921..ff441db 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxd2_syscon.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxd2_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_rxd2_syscon` reader - padcfg_pad_gmac1_rxd2_syscon"] pub type PADCFG_PAD_GMAC1_RXD2_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_rxd2_syscon` writer - padcfg_pad_gmac1_rxd2_syscon"] -pub type PADCFG_PAD_GMAC1_RXD2_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_RXD2_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_rxd2_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_rxd2_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_RXD2_SYSCON_W { - PADCFG_PAD_GMAC1_RXD2_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_RXD2_SYSCON_W { + PADCFG_PAD_GMAC1_RXD2_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxd3_syscon.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxd3_syscon.rs index 8b282dc..a9c8c83 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxd3_syscon.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxd3_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_rxd3_syscon` reader - padcfg_pad_gmac1_rxd3_syscon"] pub type PADCFG_PAD_GMAC1_RXD3_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_rxd3_syscon` writer - padcfg_pad_gmac1_rxd3_syscon"] -pub type PADCFG_PAD_GMAC1_RXD3_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_RXD3_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_rxd3_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_rxd3_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_RXD3_SYSCON_W { - PADCFG_PAD_GMAC1_RXD3_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_RXD3_SYSCON_W { + PADCFG_PAD_GMAC1_RXD3_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxdv_syscon.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxdv_syscon.rs index 7fac45f..e963403 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxdv_syscon.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_rxdv_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_rxdv_syscon` reader - padcfg_pad_gmac1_rxdv_syscon"] pub type PADCFG_PAD_GMAC1_RXDV_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_rxdv_syscon` writer - padcfg_pad_gmac1_rxdv_syscon"] -pub type PADCFG_PAD_GMAC1_RXDV_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_RXDV_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_rxdv_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_rxdv_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_RXDV_SYSCON_W { - PADCFG_PAD_GMAC1_RXDV_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_RXDV_SYSCON_W { + PADCFG_PAD_GMAC1_RXDV_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txc_syscon.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txc_syscon.rs index d90bd72..8154358 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txc_syscon.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txc_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_txc_syscon` reader - padcfg_pad_gmac1_txc_syscon"] pub type PADCFG_PAD_GMAC1_TXC_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_txc_syscon` writer - padcfg_pad_gmac1_txc_syscon"] -pub type PADCFG_PAD_GMAC1_TXC_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_TXC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_txc_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_txc_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_TXC_SYSCON_W { - PADCFG_PAD_GMAC1_TXC_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_TXC_SYSCON_W { + PADCFG_PAD_GMAC1_TXC_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txd0_syscon.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txd0_syscon.rs index 20f961f..0a1af38 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txd0_syscon.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txd0_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_txd0_syscon` reader - padcfg_pad_gmac1_txd0_syscon"] pub type PADCFG_PAD_GMAC1_TXD0_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_txd0_syscon` writer - padcfg_pad_gmac1_txd0_syscon"] -pub type PADCFG_PAD_GMAC1_TXD0_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_TXD0_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_txd0_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_txd0_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_TXD0_SYSCON_W { - PADCFG_PAD_GMAC1_TXD0_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_TXD0_SYSCON_W { + PADCFG_PAD_GMAC1_TXD0_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txd1_syscon.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txd1_syscon.rs index 74e37e5..b432eb5 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txd1_syscon.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txd1_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_txd1_syscon` reader - padcfg_pad_gmac1_txd1_syscon"] pub type PADCFG_PAD_GMAC1_TXD1_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_txd1_syscon` writer - padcfg_pad_gmac1_txd1_syscon"] -pub type PADCFG_PAD_GMAC1_TXD1_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_TXD1_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_txd1_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_txd1_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_TXD1_SYSCON_W { - PADCFG_PAD_GMAC1_TXD1_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_TXD1_SYSCON_W { + PADCFG_PAD_GMAC1_TXD1_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txd2_syscon.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txd2_syscon.rs index 945e0f8..346ec45 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txd2_syscon.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txd2_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_txd2_syscon` reader - padcfg_pad_gmac1_txd2_syscon"] pub type PADCFG_PAD_GMAC1_TXD2_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_txd2_syscon` writer - padcfg_pad_gmac1_txd2_syscon"] -pub type PADCFG_PAD_GMAC1_TXD2_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_TXD2_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_txd2_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_txd2_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_TXD2_SYSCON_W { - PADCFG_PAD_GMAC1_TXD2_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_TXD2_SYSCON_W { + PADCFG_PAD_GMAC1_TXD2_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txd3_syscon.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txd3_syscon.rs index f00aa6d..22946a5 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txd3_syscon.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txd3_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_txd3_syscon` reader - padcfg_pad_gmac1_txd3_syscon"] pub type PADCFG_PAD_GMAC1_TXD3_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_txd3_syscon` writer - padcfg_pad_gmac1_txd3_syscon"] -pub type PADCFG_PAD_GMAC1_TXD3_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_TXD3_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_txd3_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_txd3_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_TXD3_SYSCON_W { - PADCFG_PAD_GMAC1_TXD3_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_TXD3_SYSCON_W { + PADCFG_PAD_GMAC1_TXD3_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txen_syscon.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txen_syscon.rs index 2450d44..7855805 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txen_syscon.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gmac1_txen_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_txen_syscon` reader - padcfg_pad_gmac1_txen_syscon"] pub type PADCFG_PAD_GMAC1_TXEN_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_txen_syscon` writer - padcfg_pad_gmac1_txen_syscon"] -pub type PADCFG_PAD_GMAC1_TXEN_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_TXEN_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_txen_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_txen_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_TXEN_SYSCON_W { - PADCFG_PAD_GMAC1_TXEN_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_TXEN_SYSCON_W { + PADCFG_PAD_GMAC1_TXEN_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio0.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio0.rs index 96076c9..4fecea6 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio0.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio0.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio1.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio1.rs index 398124f..9dbb01e 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio1.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio1.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio10.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio10.rs index b4fe960..fada139 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio10.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio10.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio11.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio11.rs index f56fbe4..02676fe 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio11.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio11.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio12.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio12.rs index 530d06b..e70fcd3 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio12.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio12.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio13.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio13.rs index 264a66c..fb0c35a 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio13.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio13.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio14.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio14.rs index 95ba366..9b2e934 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio14.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio14.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio15.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio15.rs index 2e5014b..6b0bb17 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio15.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio15.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio16.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio16.rs index 917ae16..37b50b5 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio16.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio16.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio17.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio17.rs index 5c82ccc..6f52966 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio17.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio17.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio18.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio18.rs index 4856b14..ec88659 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio18.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio18.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio19.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio19.rs index 351dbde..3db4d43 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio19.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio19.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio2.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio2.rs index e0465f5..5e1dbd2 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio2.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio2.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio20.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio20.rs index cf5193c..ddd4039 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio20.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio20.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio21.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio21.rs index 417a861..45b58a6 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio21.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio21.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio22.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio22.rs index 3530238..cd81baa 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio22.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio22.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio23.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio23.rs index df9538b..6cd4d91 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio23.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio23.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio24.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio24.rs index 296d226..04893c0 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio24.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio24.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio25.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio25.rs index ade1493..52b9f8e 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio25.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio25.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio26.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio26.rs index 0f65f13..3d549bb 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio26.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio26.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio27.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio27.rs index 5fd7afb..a1f5441 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio27.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio27.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio28.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio28.rs index 18d687a..ec47f89 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio28.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio28.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio29.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio29.rs index 4dce15d..d4fbd43 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio29.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio29.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio3.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio3.rs index 0d6a2e2..d3504cc 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio3.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio3.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio30.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio30.rs index 0e192ff..903469d 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio30.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio30.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio31.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio31.rs index 4d9fce4..723cdae 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio31.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio31.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio32.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio32.rs index 2d304c0..6256178 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio32.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio32.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio33.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio33.rs index 7ba538f..15eb258 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio33.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio33.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio34.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio34.rs index cceb3ad..1d07aca 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio34.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio34.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio35.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio35.rs index 0d98ca3..e56e9c9 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio35.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio35.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio36.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio36.rs index 1802e23..222502f 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio36.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio36.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio37.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio37.rs index c674048..854f6bb 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio37.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio37.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio38.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio38.rs index 6259fac..01a3fa9 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio38.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio38.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio39.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio39.rs index 1d3b2dd..b45f291 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio39.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio39.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio4.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio4.rs index 6c3affc..ef51bec 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio4.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio4.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio40.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio40.rs index e739f38..af75995 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio40.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio40.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio41.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio41.rs index 21c345b..c9ed8ff 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio41.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio41.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio42.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio42.rs index dc402ba..c7bb4a7 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio42.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio42.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio43.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio43.rs index 70b48c4..bf61028 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio43.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio43.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio44.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio44.rs index d5de7b4..c98d823 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio44.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio44.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio45.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio45.rs index e25d49a..d6e5fc5 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio45.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio45.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio46.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio46.rs index ec4932c..a61ac4c 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio46.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio46.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio47.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio47.rs index 828e367..9482c04 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio47.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio47.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio48.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio48.rs index eedde59..16c6476 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio48.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio48.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio49.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio49.rs index b26f90a..95c23d1 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio49.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio49.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio5.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio5.rs index b5eb292..2395cea 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio5.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio5.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio50.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio50.rs index d7623f9..9e529ac 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio50.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio50.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio51.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio51.rs index e95fe49..989cda1 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio51.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio51.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio52.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio52.rs index 72a4c16..6b1dabb 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio52.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio52.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio53.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio53.rs index a3a0e2d..8ce1fd9 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio53.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio53.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio54.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio54.rs index 120852b..dcfdaa3 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio54.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio54.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio55.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio55.rs index 312caad..e56274f 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio55.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio55.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio56.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio56.rs index bc0e03b..9017da7 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio56.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio56.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio57.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio57.rs index 40fab1c..f1eaf55 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio57.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio57.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio58.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio58.rs index 9c56c39..46ffb54 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio58.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio58.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio59.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio59.rs index 1a9fb9d..475b711 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio59.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio59.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio6.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio6.rs index ee9de74..63fb99e 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio6.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio6.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio60.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio60.rs index 43ae2c3..3ed25bb 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio60.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio60.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio61.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio61.rs index 647d02d..bb7f31a 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio61.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio61.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio62.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio62.rs index d79cb93..9a0f5f9 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio62.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio62.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio63.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio63.rs index 422617f..999b142 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio63.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio63.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio7.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio7.rs index 02a90b4..41e3f3f 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio7.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio7.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio8.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio8.rs index e658599..9203dc3 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio8.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio8.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio9.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio9.rs index 426dad5..fc26681 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio9.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_gpio9.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_csn0.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_csn0.rs index d9febf2..1b00d56 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_csn0.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_csn0.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_data0.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_data0.rs index 95eb993..e6f00d5 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_data0.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_data0.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_data1.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_data1.rs index 6308875..d63b3e7 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_data1.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_data1.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_data2.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_data2.rs index f1000f7..2e5d58e 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_data2.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_data2.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_data3.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_data3.rs index d7adcd3..bf123f2 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_data3.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_data3.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_sclk.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_sclk.rs index 3ec3d57..14c49b8 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_sclk.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_qspi_sclk.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_clk.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_clk.rs index deb1be9..3cb752d 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_clk.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_clk.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_cmd.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_cmd.rs index aead87c..cb98e59 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_cmd.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_cmd.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data0.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data0.rs index 98bdcc0..77e4f5f 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data0.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data0.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data1.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data1.rs index f24d28a..1c0deae 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data1.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data1.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data2.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data2.rs index a687ed6..1e17981 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data2.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data2.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data3.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data3.rs index e2730ca..9b226ae 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data3.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data3.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data4.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data4.rs index f345187..a1cf301 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data4.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data4.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data5.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data5.rs index c9f3533..5cb5401 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data5.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data5.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data6.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data6.rs index 5c75958..8d7f00b 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data6.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data6.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data7.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data7.rs index b296372..46685b9 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data7.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_data7.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_strb.rs b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_strb.rs index fca4587..745ed13 100644 --- a/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_strb.rs +++ b/jh7110-vf2-12a-pac/src/sys_pinctrl/padcfg_sd0_strb.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon.rs b/jh7110-vf2-12a-pac/src/sys_syscon.rs index ac776c1..5d5a4a1 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon.rs @@ -1,312 +1,470 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + sys_sysconsaif_syscfg0: SYS_SYSCONSAIF_SYSCFG0, + sys_sysconsaif_syscfg4: SYS_SYSCONSAIF_SYSCFG4, + sys_sysconsaif_syscfg8: SYS_SYSCONSAIF_SYSCFG8, + sys_sysconsaif_syscfg12: SYS_SYSCONSAIF_SYSCFG12, + sys_sysconsaif_syscfg16: SYS_SYSCONSAIF_SYSCFG16, + sys_sysconsaif_syscfg20: SYS_SYSCONSAIF_SYSCFG20, + sys_sysconsaif_syscfg24: SYS_SYSCONSAIF_SYSCFG24, + sys_sysconsaif_syscfg28: SYS_SYSCONSAIF_SYSCFG28, + sys_sysconsaif_syscfg32: SYS_SYSCONSAIF_SYSCFG32, + sys_sysconsaif_syscfg36: SYS_SYSCONSAIF_SYSCFG36, + sys_sysconsaif_syscfg40: SYS_SYSCONSAIF_SYSCFG40, + sys_sysconsaif_syscfg44: SYS_SYSCONSAIF_SYSCFG44, + sys_sysconsaif_syscfg48: SYS_SYSCONSAIF_SYSCFG48, + sys_sysconsaif_syscfg52: SYS_SYSCONSAIF_SYSCFG52, + sys_sysconsaif_syscfg56: SYS_SYSCONSAIF_SYSCFG56, + sys_sysconsaif_syscfg60: SYS_SYSCONSAIF_SYSCFG60, + sys_sysconsaif_syscfg64: SYS_SYSCONSAIF_SYSCFG64, + sys_sysconsaif_syscfg68: SYS_SYSCONSAIF_SYSCFG68, + sys_sysconsaif_syscfg72: SYS_SYSCONSAIF_SYSCFG72, + sys_sysconsaif_syscfg76: SYS_SYSCONSAIF_SYSCFG76, + sys_sysconsaif_syscfg80: SYS_SYSCONSAIF_SYSCFG80, + sys_sysconsaif_syscfg84: SYS_SYSCONSAIF_SYSCFG84, + sys_sysconsaif_syscfg88: SYS_SYSCONSAIF_SYSCFG88, + sys_sysconsaif_syscfg92: SYS_SYSCONSAIF_SYSCFG92, + sys_sysconsaif_syscfg96: SYS_SYSCONSAIF_SYSCFG96, + sys_sysconsaif_syscfg100: SYS_SYSCONSAIF_SYSCFG100, + sys_sysconsaif_syscfg104: SYS_SYSCONSAIF_SYSCFG104, + sys_sysconsaif_syscfg108: SYS_SYSCONSAIF_SYSCFG108, + sys_sysconsaif_syscfg112: SYS_SYSCONSAIF_SYSCFG112, + sys_sysconsaif_syscfg116: SYS_SYSCONSAIF_SYSCFG116, + sys_sysconsaif_syscfg120: SYS_SYSCONSAIF_SYSCFG120, + sys_sysconsaif_syscfg124: SYS_SYSCONSAIF_SYSCFG124, + sys_sysconsaif_syscfg128: SYS_SYSCONSAIF_SYSCFG128, + _reserved33: [u8; 0x04], + sys_sysconsaif_syscfg136: SYS_SYSCONSAIF_SYSCFG136, + sys_sysconsaif_syscfg140: SYS_SYSCONSAIF_SYSCFG140, + sys_sysconsaif_syscfg144: SYS_SYSCONSAIF_SYSCFG144, + sys_sysconsaif_syscfg148: SYS_SYSCONSAIF_SYSCFG148, + sys_sysconsaif_syscfg152: SYS_SYSCONSAIF_SYSCFG152, + sys_sysconsaif_syscfg156: SYS_SYSCONSAIF_SYSCFG156, +} +impl RegisterBlock { #[doc = "0x00 - SYS SYSCONSAIF SYSCFG 0"] - pub sys_sysconsaif_syscfg0: SYS_SYSCONSAIF_SYSCFG0, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg0(&self) -> &SYS_SYSCONSAIF_SYSCFG0 { + &self.sys_sysconsaif_syscfg0 + } #[doc = "0x04 - SYS SYSCONSAIF SYSCFG 4"] - pub sys_sysconsaif_syscfg4: SYS_SYSCONSAIF_SYSCFG4, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg4(&self) -> &SYS_SYSCONSAIF_SYSCFG4 { + &self.sys_sysconsaif_syscfg4 + } #[doc = "0x08 - SYS SYSCONSAIF SYSCFG 8"] - pub sys_sysconsaif_syscfg8: SYS_SYSCONSAIF_SYSCFG8, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg8(&self) -> &SYS_SYSCONSAIF_SYSCFG8 { + &self.sys_sysconsaif_syscfg8 + } #[doc = "0x0c - SYS SYSCONSAIF SYSCFG 12: Set the GPIO voltage of all the 4 GPIO groups in this register"] - pub sys_sysconsaif_syscfg12: SYS_SYSCONSAIF_SYSCFG12, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg12(&self) -> &SYS_SYSCONSAIF_SYSCFG12 { + &self.sys_sysconsaif_syscfg12 + } #[doc = "0x10 - SYS SYSCONSAIF SYSCFG 16"] - pub sys_sysconsaif_syscfg16: SYS_SYSCONSAIF_SYSCFG16, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg16(&self) -> &SYS_SYSCONSAIF_SYSCFG16 { + &self.sys_sysconsaif_syscfg16 + } #[doc = "0x14 - SYS SYSCONSAIF SYSCFG 20"] - pub sys_sysconsaif_syscfg20: SYS_SYSCONSAIF_SYSCFG20, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg20(&self) -> &SYS_SYSCONSAIF_SYSCFG20 { + &self.sys_sysconsaif_syscfg20 + } #[doc = "0x18 - SYS SYSCONSAIF SYSCFG 24"] - pub sys_sysconsaif_syscfg24: SYS_SYSCONSAIF_SYSCFG24, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg24(&self) -> &SYS_SYSCONSAIF_SYSCFG24 { + &self.sys_sysconsaif_syscfg24 + } #[doc = "0x1c - SYS SYSCONSAIF SYSCFG 28"] - pub sys_sysconsaif_syscfg28: SYS_SYSCONSAIF_SYSCFG28, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg28(&self) -> &SYS_SYSCONSAIF_SYSCFG28 { + &self.sys_sysconsaif_syscfg28 + } #[doc = "0x20 - SYS SYSCONSAIF SYSCFG 32"] - pub sys_sysconsaif_syscfg32: SYS_SYSCONSAIF_SYSCFG32, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg32(&self) -> &SYS_SYSCONSAIF_SYSCFG32 { + &self.sys_sysconsaif_syscfg32 + } #[doc = "0x24 - SYS SYSCONSAIF SYSCFG 36"] - pub sys_sysconsaif_syscfg36: SYS_SYSCONSAIF_SYSCFG36, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg36(&self) -> &SYS_SYSCONSAIF_SYSCFG36 { + &self.sys_sysconsaif_syscfg36 + } #[doc = "0x28 - SYS SYSCONSAIF SYSCFG 40"] - pub sys_sysconsaif_syscfg40: SYS_SYSCONSAIF_SYSCFG40, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg40(&self) -> &SYS_SYSCONSAIF_SYSCFG40 { + &self.sys_sysconsaif_syscfg40 + } #[doc = "0x2c - SYS SYSCONSAIF SYSCFG 44"] - pub sys_sysconsaif_syscfg44: SYS_SYSCONSAIF_SYSCFG44, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg44(&self) -> &SYS_SYSCONSAIF_SYSCFG44 { + &self.sys_sysconsaif_syscfg44 + } #[doc = "0x30 - SYS SYSCONSAIF SYSCFG 48"] - pub sys_sysconsaif_syscfg48: SYS_SYSCONSAIF_SYSCFG48, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg48(&self) -> &SYS_SYSCONSAIF_SYSCFG48 { + &self.sys_sysconsaif_syscfg48 + } #[doc = "0x34 - SYS SYSCONSAIF SYSCFG 52"] - pub sys_sysconsaif_syscfg52: SYS_SYSCONSAIF_SYSCFG52, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg52(&self) -> &SYS_SYSCONSAIF_SYSCFG52 { + &self.sys_sysconsaif_syscfg52 + } #[doc = "0x38 - SYS SYSCONSAIF SYSCFG 56"] - pub sys_sysconsaif_syscfg56: SYS_SYSCONSAIF_SYSCFG56, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg56(&self) -> &SYS_SYSCONSAIF_SYSCFG56 { + &self.sys_sysconsaif_syscfg56 + } #[doc = "0x3c - SYS SYSCONSAIF SYSCFG 60"] - pub sys_sysconsaif_syscfg60: SYS_SYSCONSAIF_SYSCFG60, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg60(&self) -> &SYS_SYSCONSAIF_SYSCFG60 { + &self.sys_sysconsaif_syscfg60 + } #[doc = "0x40 - SYS SYSCONSAIF SYSCFG 64"] - pub sys_sysconsaif_syscfg64: SYS_SYSCONSAIF_SYSCFG64, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg64(&self) -> &SYS_SYSCONSAIF_SYSCFG64 { + &self.sys_sysconsaif_syscfg64 + } #[doc = "0x44 - SYS SYSCONSAIF SYSCFG 68"] - pub sys_sysconsaif_syscfg68: SYS_SYSCONSAIF_SYSCFG68, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg68(&self) -> &SYS_SYSCONSAIF_SYSCFG68 { + &self.sys_sysconsaif_syscfg68 + } #[doc = "0x48 - SYS SYSCONSAIF SYSCFG 72"] - pub sys_sysconsaif_syscfg72: SYS_SYSCONSAIF_SYSCFG72, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg72(&self) -> &SYS_SYSCONSAIF_SYSCFG72 { + &self.sys_sysconsaif_syscfg72 + } #[doc = "0x4c - SYS SYSCONSAIF SYSCFG 76"] - pub sys_sysconsaif_syscfg76: SYS_SYSCONSAIF_SYSCFG76, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg76(&self) -> &SYS_SYSCONSAIF_SYSCFG76 { + &self.sys_sysconsaif_syscfg76 + } #[doc = "0x50 - SYS SYSCONSAIF SYSCFG 80"] - pub sys_sysconsaif_syscfg80: SYS_SYSCONSAIF_SYSCFG80, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg80(&self) -> &SYS_SYSCONSAIF_SYSCFG80 { + &self.sys_sysconsaif_syscfg80 + } #[doc = "0x54 - SYS SYSCONSAIF SYSCFG 84"] - pub sys_sysconsaif_syscfg84: SYS_SYSCONSAIF_SYSCFG84, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg84(&self) -> &SYS_SYSCONSAIF_SYSCFG84 { + &self.sys_sysconsaif_syscfg84 + } #[doc = "0x58 - SYS SYSCONSAIF SYSCFG 88"] - pub sys_sysconsaif_syscfg88: SYS_SYSCONSAIF_SYSCFG88, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg88(&self) -> &SYS_SYSCONSAIF_SYSCFG88 { + &self.sys_sysconsaif_syscfg88 + } #[doc = "0x5c - SYS SYSCONSAIF SYSCFG 92"] - pub sys_sysconsaif_syscfg92: SYS_SYSCONSAIF_SYSCFG92, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg92(&self) -> &SYS_SYSCONSAIF_SYSCFG92 { + &self.sys_sysconsaif_syscfg92 + } #[doc = "0x60 - SYS SYSCONSAIF SYSCFG 96"] - pub sys_sysconsaif_syscfg96: SYS_SYSCONSAIF_SYSCFG96, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg96(&self) -> &SYS_SYSCONSAIF_SYSCFG96 { + &self.sys_sysconsaif_syscfg96 + } #[doc = "0x64 - SYS SYSCONSAIF SYSCFG 100"] - pub sys_sysconsaif_syscfg100: SYS_SYSCONSAIF_SYSCFG100, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg100(&self) -> &SYS_SYSCONSAIF_SYSCFG100 { + &self.sys_sysconsaif_syscfg100 + } #[doc = "0x68 - SYS SYSCONSAIF SYSCFG 104"] - pub sys_sysconsaif_syscfg104: SYS_SYSCONSAIF_SYSCFG104, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg104(&self) -> &SYS_SYSCONSAIF_SYSCFG104 { + &self.sys_sysconsaif_syscfg104 + } #[doc = "0x6c - SYS SYSCONSAIF SYSCFG 108"] - pub sys_sysconsaif_syscfg108: SYS_SYSCONSAIF_SYSCFG108, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg108(&self) -> &SYS_SYSCONSAIF_SYSCFG108 { + &self.sys_sysconsaif_syscfg108 + } #[doc = "0x70 - SYS SYSCONSAIF SYSCFG 112"] - pub sys_sysconsaif_syscfg112: SYS_SYSCONSAIF_SYSCFG112, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg112(&self) -> &SYS_SYSCONSAIF_SYSCFG112 { + &self.sys_sysconsaif_syscfg112 + } #[doc = "0x74 - SYS SYSCONSAIF SYSCFG 116"] - pub sys_sysconsaif_syscfg116: SYS_SYSCONSAIF_SYSCFG116, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg116(&self) -> &SYS_SYSCONSAIF_SYSCFG116 { + &self.sys_sysconsaif_syscfg116 + } #[doc = "0x78 - SYS SYSCONSAIF SYSCFG 120"] - pub sys_sysconsaif_syscfg120: SYS_SYSCONSAIF_SYSCFG120, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg120(&self) -> &SYS_SYSCONSAIF_SYSCFG120 { + &self.sys_sysconsaif_syscfg120 + } #[doc = "0x7c - SYS SYSCONSAIF SYSCFG 124"] - pub sys_sysconsaif_syscfg124: SYS_SYSCONSAIF_SYSCFG124, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg124(&self) -> &SYS_SYSCONSAIF_SYSCFG124 { + &self.sys_sysconsaif_syscfg124 + } #[doc = "0x80 - SYS SYSCONSAIF SYSCFG 128"] - pub sys_sysconsaif_syscfg128: SYS_SYSCONSAIF_SYSCFG128, - _reserved33: [u8; 0x04], + #[inline(always)] + pub const fn sys_sysconsaif_syscfg128(&self) -> &SYS_SYSCONSAIF_SYSCFG128 { + &self.sys_sysconsaif_syscfg128 + } #[doc = "0x88 - SYS SYSCONSAIF SYSCFG 136"] - pub sys_sysconsaif_syscfg136: SYS_SYSCONSAIF_SYSCFG136, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg136(&self) -> &SYS_SYSCONSAIF_SYSCFG136 { + &self.sys_sysconsaif_syscfg136 + } #[doc = "0x8c - SYS SYSCONSAIF SYSCFG 140"] - pub sys_sysconsaif_syscfg140: SYS_SYSCONSAIF_SYSCFG140, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg140(&self) -> &SYS_SYSCONSAIF_SYSCFG140 { + &self.sys_sysconsaif_syscfg140 + } #[doc = "0x90 - SYS SYSCONSAIF SYSCFG 144"] - pub sys_sysconsaif_syscfg144: SYS_SYSCONSAIF_SYSCFG144, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg144(&self) -> &SYS_SYSCONSAIF_SYSCFG144 { + &self.sys_sysconsaif_syscfg144 + } #[doc = "0x94 - SYS SYSCONSAIF SYSCFG 148"] - pub sys_sysconsaif_syscfg148: SYS_SYSCONSAIF_SYSCFG148, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg148(&self) -> &SYS_SYSCONSAIF_SYSCFG148 { + &self.sys_sysconsaif_syscfg148 + } #[doc = "0x98 - SYS SYSCONSAIF SYSCFG 152"] - pub sys_sysconsaif_syscfg152: SYS_SYSCONSAIF_SYSCFG152, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg152(&self) -> &SYS_SYSCONSAIF_SYSCFG152 { + &self.sys_sysconsaif_syscfg152 + } #[doc = "0x9c - SYS SYSCONSAIF SYSCFG 156"] - pub sys_sysconsaif_syscfg156: SYS_SYSCONSAIF_SYSCFG156, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg156(&self) -> &SYS_SYSCONSAIF_SYSCFG156 { + &self.sys_sysconsaif_syscfg156 + } } -#[doc = "sys_sysconsaif_syscfg0 (rw) register accessor: SYS SYSCONSAIF SYSCFG 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg0`] +#[doc = "sys_sysconsaif_syscfg0 (rw) register accessor: SYS SYSCONSAIF SYSCFG 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg0`] module"] pub type SYS_SYSCONSAIF_SYSCFG0 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 0"] pub mod sys_sysconsaif_syscfg0; -#[doc = "sys_sysconsaif_syscfg4 (rw) register accessor: SYS SYSCONSAIF SYSCFG 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg4`] +#[doc = "sys_sysconsaif_syscfg4 (rw) register accessor: SYS SYSCONSAIF SYSCFG 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg4`] module"] pub type SYS_SYSCONSAIF_SYSCFG4 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 4"] pub mod sys_sysconsaif_syscfg4; -#[doc = "sys_sysconsaif_syscfg8 (rw) register accessor: SYS SYSCONSAIF SYSCFG 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg8`] +#[doc = "sys_sysconsaif_syscfg8 (rw) register accessor: SYS SYSCONSAIF SYSCFG 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg8`] module"] pub type SYS_SYSCONSAIF_SYSCFG8 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 8"] pub mod sys_sysconsaif_syscfg8; -#[doc = "sys_sysconsaif_syscfg12 (rw) register accessor: SYS SYSCONSAIF SYSCFG 12: Set the GPIO voltage of all the 4 GPIO groups in this register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg12::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg12`] +#[doc = "sys_sysconsaif_syscfg12 (rw) register accessor: SYS SYSCONSAIF SYSCFG 12: Set the GPIO voltage of all the 4 GPIO groups in this register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg12::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg12`] module"] pub type SYS_SYSCONSAIF_SYSCFG12 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 12: Set the GPIO voltage of all the 4 GPIO groups in this register"] pub mod sys_sysconsaif_syscfg12; -#[doc = "sys_sysconsaif_syscfg16 (rw) register accessor: SYS SYSCONSAIF SYSCFG 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg16::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg16`] +#[doc = "sys_sysconsaif_syscfg16 (rw) register accessor: SYS SYSCONSAIF SYSCFG 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg16::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg16`] module"] pub type SYS_SYSCONSAIF_SYSCFG16 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 16"] pub mod sys_sysconsaif_syscfg16; -#[doc = "sys_sysconsaif_syscfg20 (rw) register accessor: SYS SYSCONSAIF SYSCFG 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg20::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg20`] +#[doc = "sys_sysconsaif_syscfg20 (rw) register accessor: SYS SYSCONSAIF SYSCFG 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg20::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg20`] module"] pub type SYS_SYSCONSAIF_SYSCFG20 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 20"] pub mod sys_sysconsaif_syscfg20; -#[doc = "sys_sysconsaif_syscfg24 (rw) register accessor: SYS SYSCONSAIF SYSCFG 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg24::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg24`] +#[doc = "sys_sysconsaif_syscfg24 (rw) register accessor: SYS SYSCONSAIF SYSCFG 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg24::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg24`] module"] pub type SYS_SYSCONSAIF_SYSCFG24 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 24"] pub mod sys_sysconsaif_syscfg24; -#[doc = "sys_sysconsaif_syscfg28 (rw) register accessor: SYS SYSCONSAIF SYSCFG 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg28::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg28`] +#[doc = "sys_sysconsaif_syscfg28 (rw) register accessor: SYS SYSCONSAIF SYSCFG 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg28::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg28`] module"] pub type SYS_SYSCONSAIF_SYSCFG28 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 28"] pub mod sys_sysconsaif_syscfg28; -#[doc = "sys_sysconsaif_syscfg32 (rw) register accessor: SYS SYSCONSAIF SYSCFG 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg32::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg32`] +#[doc = "sys_sysconsaif_syscfg32 (rw) register accessor: SYS SYSCONSAIF SYSCFG 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg32::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg32`] module"] pub type SYS_SYSCONSAIF_SYSCFG32 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 32"] pub mod sys_sysconsaif_syscfg32; -#[doc = "sys_sysconsaif_syscfg36 (rw) register accessor: SYS SYSCONSAIF SYSCFG 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg36::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg36`] +#[doc = "sys_sysconsaif_syscfg36 (rw) register accessor: SYS SYSCONSAIF SYSCFG 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg36::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg36`] module"] pub type SYS_SYSCONSAIF_SYSCFG36 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 36"] pub mod sys_sysconsaif_syscfg36; -#[doc = "sys_sysconsaif_syscfg40 (rw) register accessor: SYS SYSCONSAIF SYSCFG 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg40::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg40`] +#[doc = "sys_sysconsaif_syscfg40 (rw) register accessor: SYS SYSCONSAIF SYSCFG 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg40::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg40`] module"] pub type SYS_SYSCONSAIF_SYSCFG40 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 40"] pub mod sys_sysconsaif_syscfg40; -#[doc = "sys_sysconsaif_syscfg44 (rw) register accessor: SYS SYSCONSAIF SYSCFG 44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg44::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg44`] +#[doc = "sys_sysconsaif_syscfg44 (rw) register accessor: SYS SYSCONSAIF SYSCFG 44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg44::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg44`] module"] pub type SYS_SYSCONSAIF_SYSCFG44 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 44"] pub mod sys_sysconsaif_syscfg44; -#[doc = "sys_sysconsaif_syscfg48 (rw) register accessor: SYS SYSCONSAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg48`] +#[doc = "sys_sysconsaif_syscfg48 (rw) register accessor: SYS SYSCONSAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg48`] module"] pub type SYS_SYSCONSAIF_SYSCFG48 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 48"] pub mod sys_sysconsaif_syscfg48; -#[doc = "sys_sysconsaif_syscfg52 (rw) register accessor: SYS SYSCONSAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg52`] +#[doc = "sys_sysconsaif_syscfg52 (rw) register accessor: SYS SYSCONSAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg52`] module"] pub type SYS_SYSCONSAIF_SYSCFG52 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 52"] pub mod sys_sysconsaif_syscfg52; -#[doc = "sys_sysconsaif_syscfg56 (rw) register accessor: SYS SYSCONSAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg56`] +#[doc = "sys_sysconsaif_syscfg56 (rw) register accessor: SYS SYSCONSAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg56`] module"] pub type SYS_SYSCONSAIF_SYSCFG56 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 56"] pub mod sys_sysconsaif_syscfg56; -#[doc = "sys_sysconsaif_syscfg60 (rw) register accessor: SYS SYSCONSAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg60`] +#[doc = "sys_sysconsaif_syscfg60 (rw) register accessor: SYS SYSCONSAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg60`] module"] pub type SYS_SYSCONSAIF_SYSCFG60 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 60"] pub mod sys_sysconsaif_syscfg60; -#[doc = "sys_sysconsaif_syscfg64 (rw) register accessor: SYS SYSCONSAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg64`] +#[doc = "sys_sysconsaif_syscfg64 (rw) register accessor: SYS SYSCONSAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg64`] module"] pub type SYS_SYSCONSAIF_SYSCFG64 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 64"] pub mod sys_sysconsaif_syscfg64; -#[doc = "sys_sysconsaif_syscfg68 (rw) register accessor: SYS SYSCONSAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg68`] +#[doc = "sys_sysconsaif_syscfg68 (rw) register accessor: SYS SYSCONSAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg68`] module"] pub type SYS_SYSCONSAIF_SYSCFG68 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 68"] pub mod sys_sysconsaif_syscfg68; -#[doc = "sys_sysconsaif_syscfg72 (rw) register accessor: SYS SYSCONSAIF SYSCFG 72\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg72::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg72::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg72`] +#[doc = "sys_sysconsaif_syscfg72 (rw) register accessor: SYS SYSCONSAIF SYSCFG 72\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg72::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg72::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg72`] module"] pub type SYS_SYSCONSAIF_SYSCFG72 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 72"] pub mod sys_sysconsaif_syscfg72; -#[doc = "sys_sysconsaif_syscfg76 (rw) register accessor: SYS SYSCONSAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg76`] +#[doc = "sys_sysconsaif_syscfg76 (rw) register accessor: SYS SYSCONSAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg76`] module"] pub type SYS_SYSCONSAIF_SYSCFG76 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 76"] pub mod sys_sysconsaif_syscfg76; -#[doc = "sys_sysconsaif_syscfg80 (rw) register accessor: SYS SYSCONSAIF SYSCFG 80\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg80::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg80::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg80`] +#[doc = "sys_sysconsaif_syscfg80 (rw) register accessor: SYS SYSCONSAIF SYSCFG 80\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg80::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg80::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg80`] module"] pub type SYS_SYSCONSAIF_SYSCFG80 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 80"] pub mod sys_sysconsaif_syscfg80; -#[doc = "sys_sysconsaif_syscfg84 (rw) register accessor: SYS SYSCONSAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg84`] +#[doc = "sys_sysconsaif_syscfg84 (rw) register accessor: SYS SYSCONSAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg84`] module"] pub type SYS_SYSCONSAIF_SYSCFG84 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 84"] pub mod sys_sysconsaif_syscfg84; -#[doc = "sys_sysconsaif_syscfg88 (rw) register accessor: SYS SYSCONSAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg88`] +#[doc = "sys_sysconsaif_syscfg88 (rw) register accessor: SYS SYSCONSAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg88`] module"] pub type SYS_SYSCONSAIF_SYSCFG88 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 88"] pub mod sys_sysconsaif_syscfg88; -#[doc = "sys_sysconsaif_syscfg92 (rw) register accessor: SYS SYSCONSAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg92`] +#[doc = "sys_sysconsaif_syscfg92 (rw) register accessor: SYS SYSCONSAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg92`] module"] pub type SYS_SYSCONSAIF_SYSCFG92 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 92"] pub mod sys_sysconsaif_syscfg92; -#[doc = "sys_sysconsaif_syscfg96 (rw) register accessor: SYS SYSCONSAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg96`] +#[doc = "sys_sysconsaif_syscfg96 (rw) register accessor: SYS SYSCONSAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg96`] module"] pub type SYS_SYSCONSAIF_SYSCFG96 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 96"] pub mod sys_sysconsaif_syscfg96; -#[doc = "sys_sysconsaif_syscfg100 (rw) register accessor: SYS SYSCONSAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg100`] +#[doc = "sys_sysconsaif_syscfg100 (rw) register accessor: SYS SYSCONSAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg100`] module"] pub type SYS_SYSCONSAIF_SYSCFG100 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 100"] pub mod sys_sysconsaif_syscfg100; -#[doc = "sys_sysconsaif_syscfg104 (rw) register accessor: SYS SYSCONSAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg104`] +#[doc = "sys_sysconsaif_syscfg104 (rw) register accessor: SYS SYSCONSAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg104`] module"] pub type SYS_SYSCONSAIF_SYSCFG104 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 104"] pub mod sys_sysconsaif_syscfg104; -#[doc = "sys_sysconsaif_syscfg108 (rw) register accessor: SYS SYSCONSAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg108`] +#[doc = "sys_sysconsaif_syscfg108 (rw) register accessor: SYS SYSCONSAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg108`] module"] pub type SYS_SYSCONSAIF_SYSCFG108 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 108"] pub mod sys_sysconsaif_syscfg108; -#[doc = "sys_sysconsaif_syscfg112 (rw) register accessor: SYS SYSCONSAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg112`] +#[doc = "sys_sysconsaif_syscfg112 (rw) register accessor: SYS SYSCONSAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg112`] module"] pub type SYS_SYSCONSAIF_SYSCFG112 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 112"] pub mod sys_sysconsaif_syscfg112; -#[doc = "sys_sysconsaif_syscfg116 (rw) register accessor: SYS SYSCONSAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg116`] +#[doc = "sys_sysconsaif_syscfg116 (rw) register accessor: SYS SYSCONSAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg116`] module"] pub type SYS_SYSCONSAIF_SYSCFG116 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 116"] pub mod sys_sysconsaif_syscfg116; -#[doc = "sys_sysconsaif_syscfg120 (rw) register accessor: SYS SYSCONSAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg120`] +#[doc = "sys_sysconsaif_syscfg120 (rw) register accessor: SYS SYSCONSAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg120`] module"] pub type SYS_SYSCONSAIF_SYSCFG120 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 120"] pub mod sys_sysconsaif_syscfg120; -#[doc = "sys_sysconsaif_syscfg124 (rw) register accessor: SYS SYSCONSAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg124`] +#[doc = "sys_sysconsaif_syscfg124 (rw) register accessor: SYS SYSCONSAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg124`] module"] pub type SYS_SYSCONSAIF_SYSCFG124 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 124"] pub mod sys_sysconsaif_syscfg124; -#[doc = "sys_sysconsaif_syscfg128 (rw) register accessor: SYS SYSCONSAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg128`] +#[doc = "sys_sysconsaif_syscfg128 (rw) register accessor: SYS SYSCONSAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg128`] module"] pub type SYS_SYSCONSAIF_SYSCFG128 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 128"] pub mod sys_sysconsaif_syscfg128; -#[doc = "sys_sysconsaif_syscfg136 (rw) register accessor: SYS SYSCONSAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg136`] +#[doc = "sys_sysconsaif_syscfg136 (rw) register accessor: SYS SYSCONSAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg136`] module"] pub type SYS_SYSCONSAIF_SYSCFG136 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 136"] pub mod sys_sysconsaif_syscfg136; -#[doc = "sys_sysconsaif_syscfg140 (rw) register accessor: SYS SYSCONSAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg140::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg140::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg140`] +#[doc = "sys_sysconsaif_syscfg140 (rw) register accessor: SYS SYSCONSAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg140::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg140::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg140`] module"] pub type SYS_SYSCONSAIF_SYSCFG140 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 140"] pub mod sys_sysconsaif_syscfg140; -#[doc = "sys_sysconsaif_syscfg144 (rw) register accessor: SYS SYSCONSAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg144::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg144::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg144`] +#[doc = "sys_sysconsaif_syscfg144 (rw) register accessor: SYS SYSCONSAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg144::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg144::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg144`] module"] pub type SYS_SYSCONSAIF_SYSCFG144 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 144"] pub mod sys_sysconsaif_syscfg144; -#[doc = "sys_sysconsaif_syscfg148 (rw) register accessor: SYS SYSCONSAIF SYSCFG 148\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg148::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg148::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg148`] +#[doc = "sys_sysconsaif_syscfg148 (rw) register accessor: SYS SYSCONSAIF SYSCFG 148\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg148::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg148::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg148`] module"] pub type SYS_SYSCONSAIF_SYSCFG148 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 148"] pub mod sys_sysconsaif_syscfg148; -#[doc = "sys_sysconsaif_syscfg152 (rw) register accessor: SYS SYSCONSAIF SYSCFG 152\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg152::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg152::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg152`] +#[doc = "sys_sysconsaif_syscfg152 (rw) register accessor: SYS SYSCONSAIF SYSCFG 152\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg152::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg152::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg152`] module"] pub type SYS_SYSCONSAIF_SYSCFG152 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 152"] pub mod sys_sysconsaif_syscfg152; -#[doc = "sys_sysconsaif_syscfg156 (rw) register accessor: SYS SYSCONSAIF SYSCFG 156\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg156::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg156::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg156`] +#[doc = "sys_sysconsaif_syscfg156 (rw) register accessor: SYS SYSCONSAIF SYSCFG 156\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg156::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg156::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg156`] module"] pub type SYS_SYSCONSAIF_SYSCFG156 = crate::Reg; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg0.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg0.rs index d6622af..aee6cd6 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg0.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg0.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `scfg_e24_remap_haddr` reader - scfg_e24_remap_haddr"] pub type SCFG_E24_REMAP_HADDR_R = crate::FieldReader; #[doc = "Field `scfg_e24_remap_haddr` writer - scfg_e24_remap_haddr"] -pub type SCFG_E24_REMAP_HADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_E24_REMAP_HADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_hifi4_idma_remap_araddr` reader - scfg_hifi4_idma_remap_araddr"] pub type SCFG_HIFI4_IDMA_REMAP_ARADDR_R = crate::FieldReader; #[doc = "Field `scfg_hifi4_idma_remap_araddr` writer - scfg_hifi4_idma_remap_araddr"] -pub type SCFG_HIFI4_IDMA_REMAP_ARADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_HIFI4_IDMA_REMAP_ARADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_hifi4_idma_remap_awaddr` reader - scfg_hifi4_idma_remap_awaddr"] pub type SCFG_HIFI4_IDMA_REMAP_AWADDR_R = crate::FieldReader; #[doc = "Field `scfg_hifi4_idma_remap_awaddr` writer - scfg_hifi4_idma_remap_awaddr"] -pub type SCFG_HIFI4_IDMA_REMAP_AWADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_HIFI4_IDMA_REMAP_AWADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_hifi4_sys_remap_araddr` reader - scfg_hifi4_sys_remap_araddr"] pub type SCFG_HIFI4_SYS_REMAP_ARADDR_R = crate::FieldReader; #[doc = "Field `scfg_hifi4_sys_remap_araddr` writer - scfg_hifi4_sys_remap_araddr"] -pub type SCFG_HIFI4_SYS_REMAP_ARADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_HIFI4_SYS_REMAP_ARADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_hifi4_sys_remap_awaddr` reader - scfg_hifi4_sys_remap_awaddr"] pub type SCFG_HIFI4_SYS_REMAP_AWADDR_R = crate::FieldReader; #[doc = "Field `scfg_hifi4_sys_remap_awaddr` writer - scfg_hifi4_sys_remap_awaddr"] -pub type SCFG_HIFI4_SYS_REMAP_AWADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_HIFI4_SYS_REMAP_AWADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_jpg_remap_araddr` reader - scfg_jpg_remap_araddr"] pub type SCFG_JPG_REMAP_ARADDR_R = crate::FieldReader; #[doc = "Field `scfg_jpg_remap_araddr` writer - scfg_jpg_remap_araddr"] -pub type SCFG_JPG_REMAP_ARADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_JPG_REMAP_ARADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_jpg_remap_awaddr` reader - scfg_jpg_remap_awaddr"] pub type SCFG_JPG_REMAP_AWADDR_R = crate::FieldReader; #[doc = "Field `scfg_jpg_remap_awaddr` writer - scfg_jpg_remap_awaddr"] -pub type SCFG_JPG_REMAP_AWADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_JPG_REMAP_AWADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_sd0_remap_araddr` reader - scfg_sd0_remap_araddr"] pub type SCFG_SD0_REMAP_ARADDR_R = crate::FieldReader; #[doc = "Field `scfg_sd0_remap_araddr` writer - scfg_sd0_remap_araddr"] -pub type SCFG_SD0_REMAP_ARADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_SD0_REMAP_ARADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - scfg_e24_remap_haddr"] #[inline(always)] @@ -80,68 +80,70 @@ impl W { #[doc = "Bits 0:3 - scfg_e24_remap_haddr"] #[inline(always)] #[must_use] - pub fn scfg_e24_remap_haddr( - &mut self, - ) -> SCFG_E24_REMAP_HADDR_W { - SCFG_E24_REMAP_HADDR_W::new(self) + pub fn scfg_e24_remap_haddr(&mut self) -> SCFG_E24_REMAP_HADDR_W { + SCFG_E24_REMAP_HADDR_W::new(self, 0) } #[doc = "Bits 4:7 - scfg_hifi4_idma_remap_araddr"] #[inline(always)] #[must_use] pub fn scfg_hifi4_idma_remap_araddr( &mut self, - ) -> SCFG_HIFI4_IDMA_REMAP_ARADDR_W { - SCFG_HIFI4_IDMA_REMAP_ARADDR_W::new(self) + ) -> SCFG_HIFI4_IDMA_REMAP_ARADDR_W { + SCFG_HIFI4_IDMA_REMAP_ARADDR_W::new(self, 4) } #[doc = "Bits 8:11 - scfg_hifi4_idma_remap_awaddr"] #[inline(always)] #[must_use] pub fn scfg_hifi4_idma_remap_awaddr( &mut self, - ) -> SCFG_HIFI4_IDMA_REMAP_AWADDR_W { - SCFG_HIFI4_IDMA_REMAP_AWADDR_W::new(self) + ) -> SCFG_HIFI4_IDMA_REMAP_AWADDR_W { + SCFG_HIFI4_IDMA_REMAP_AWADDR_W::new(self, 8) } #[doc = "Bits 12:15 - scfg_hifi4_sys_remap_araddr"] #[inline(always)] #[must_use] pub fn scfg_hifi4_sys_remap_araddr( &mut self, - ) -> SCFG_HIFI4_SYS_REMAP_ARADDR_W { - SCFG_HIFI4_SYS_REMAP_ARADDR_W::new(self) + ) -> SCFG_HIFI4_SYS_REMAP_ARADDR_W { + SCFG_HIFI4_SYS_REMAP_ARADDR_W::new(self, 12) } #[doc = "Bits 16:19 - scfg_hifi4_sys_remap_awaddr"] #[inline(always)] #[must_use] pub fn scfg_hifi4_sys_remap_awaddr( &mut self, - ) -> SCFG_HIFI4_SYS_REMAP_AWADDR_W { - SCFG_HIFI4_SYS_REMAP_AWADDR_W::new(self) + ) -> SCFG_HIFI4_SYS_REMAP_AWADDR_W { + SCFG_HIFI4_SYS_REMAP_AWADDR_W::new(self, 16) } #[doc = "Bits 20:23 - scfg_jpg_remap_araddr"] #[inline(always)] #[must_use] pub fn scfg_jpg_remap_araddr( &mut self, - ) -> SCFG_JPG_REMAP_ARADDR_W { - SCFG_JPG_REMAP_ARADDR_W::new(self) + ) -> SCFG_JPG_REMAP_ARADDR_W { + SCFG_JPG_REMAP_ARADDR_W::new(self, 20) } #[doc = "Bits 24:27 - scfg_jpg_remap_awaddr"] #[inline(always)] #[must_use] pub fn scfg_jpg_remap_awaddr( &mut self, - ) -> SCFG_JPG_REMAP_AWADDR_W { - SCFG_JPG_REMAP_AWADDR_W::new(self) + ) -> SCFG_JPG_REMAP_AWADDR_W { + SCFG_JPG_REMAP_AWADDR_W::new(self, 24) } #[doc = "Bits 28:31 - scfg_sd0_remap_araddr"] #[inline(always)] #[must_use] pub fn scfg_sd0_remap_araddr( &mut self, - ) -> SCFG_SD0_REMAP_ARADDR_W { - SCFG_SD0_REMAP_ARADDR_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> SCFG_SD0_REMAP_ARADDR_W { + SCFG_SD0_REMAP_ARADDR_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg100.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg100.rs index 7c1d8e1..952c6cb 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg100.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg100.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_trace_mtx_scfg_c3_in0_ctl` reader - u0_trace_mtx_scfg_c3_in0_ctl"] pub type U0_TRACE_MTX_SCFG_C3_IN0_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c3_in0_ctl` writer - u0_trace_mtx_scfg_c3_in0_ctl"] -pub type U0_TRACE_MTX_SCFG_C3_IN0_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C3_IN0_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_trace_mtx_scfg_c3_in1_ctl` reader - u0_trace_mtx_scfg_c3_in1_ctl"] pub type U0_TRACE_MTX_SCFG_C3_IN1_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c3_in1_ctl` writer - u0_trace_mtx_scfg_c3_in1_ctl"] -pub type U0_TRACE_MTX_SCFG_C3_IN1_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C3_IN1_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_trace_mtx_scfg_c4_in0_ctl` reader - u0_trace_mtx_scfg_c4_in0_ctl"] pub type U0_TRACE_MTX_SCFG_C4_IN0_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c4_in0_ctl` writer - u0_trace_mtx_scfg_c4_in0_ctl"] -pub type U0_TRACE_MTX_SCFG_C4_IN0_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C4_IN0_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_trace_mtx_scfg_c4_in1_ctl` reader - u0_trace_mtx_scfg_c4_in1_ctl"] pub type U0_TRACE_MTX_SCFG_C4_IN1_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c4_in1_ctl` writer - u0_trace_mtx_scfg_c4_in1_ctl"] -pub type U0_TRACE_MTX_SCFG_C4_IN1_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C4_IN1_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_u7mc_sft7110_cease_from_tile_0` reader - u0_u7mc_sft7110_cease_from_tile_0"] pub type U0_U7MC_SFT7110_CEASE_FROM_TILE_0_R = crate::BitReader; #[doc = "Field `u0_u7mc_sft7110_cease_from_tile_1` reader - u0_u7mc_sft7110_cease_from_tile_1"] @@ -116,34 +116,38 @@ impl W { #[must_use] pub fn u0_trace_mtx_scfg_c3_in0_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C3_IN0_CTL_W { - U0_TRACE_MTX_SCFG_C3_IN0_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C3_IN0_CTL_W { + U0_TRACE_MTX_SCFG_C3_IN0_CTL_W::new(self, 0) } #[doc = "Bits 5:9 - u0_trace_mtx_scfg_c3_in1_ctl"] #[inline(always)] #[must_use] pub fn u0_trace_mtx_scfg_c3_in1_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C3_IN1_CTL_W { - U0_TRACE_MTX_SCFG_C3_IN1_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C3_IN1_CTL_W { + U0_TRACE_MTX_SCFG_C3_IN1_CTL_W::new(self, 5) } #[doc = "Bits 10:14 - u0_trace_mtx_scfg_c4_in0_ctl"] #[inline(always)] #[must_use] pub fn u0_trace_mtx_scfg_c4_in0_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C4_IN0_CTL_W { - U0_TRACE_MTX_SCFG_C4_IN0_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C4_IN0_CTL_W { + U0_TRACE_MTX_SCFG_C4_IN0_CTL_W::new(self, 10) } #[doc = "Bits 15:19 - u0_trace_mtx_scfg_c4_in1_ctl"] #[inline(always)] #[must_use] pub fn u0_trace_mtx_scfg_c4_in1_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C4_IN1_CTL_W { - U0_TRACE_MTX_SCFG_C4_IN1_CTL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_TRACE_MTX_SCFG_C4_IN1_CTL_W { + U0_TRACE_MTX_SCFG_C4_IN1_CTL_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg104.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg104.rs index ab51c02..c2a5313 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg104.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg104.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_u7mc_sft7110_reset_vector_1_31_0` reader - u0_u7mc_sft7110_reset_vector_1_31_0"] pub type U0_U7MC_SFT7110_RESET_VECTOR_1_31_0_R = crate::FieldReader; #[doc = "Field `u0_u7mc_sft7110_reset_vector_1_31_0` writer - u0_u7mc_sft7110_reset_vector_1_31_0"] -pub type U0_U7MC_SFT7110_RESET_VECTOR_1_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_U7MC_SFT7110_RESET_VECTOR_1_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_u7mc_sft7110_reset_vector_1_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_u7mc_sft7110_reset_vector_1_31_0( &mut self, - ) -> U0_U7MC_SFT7110_RESET_VECTOR_1_31_0_W { - U0_U7MC_SFT7110_RESET_VECTOR_1_31_0_W::new(self) + ) -> U0_U7MC_SFT7110_RESET_VECTOR_1_31_0_W { + U0_U7MC_SFT7110_RESET_VECTOR_1_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg108.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg108.rs index 9056432..8c92258 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg108.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg108.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_u7mc_sft7110_reset_vector_1_35_32` reader - u0_u7mc_sft7110_reset_vector_1_35_32"] pub type U0_U7MC_SFT7110_RESET_VECTOR_1_35_32_R = crate::FieldReader; #[doc = "Field `u0_u7mc_sft7110_reset_vector_1_35_32` writer - u0_u7mc_sft7110_reset_vector_1_35_32"] -pub type U0_U7MC_SFT7110_RESET_VECTOR_1_35_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 4, O>; +pub type U0_U7MC_SFT7110_RESET_VECTOR_1_35_32_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - u0_u7mc_sft7110_reset_vector_1_35_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_u7mc_sft7110_reset_vector_1_35_32( &mut self, - ) -> U0_U7MC_SFT7110_RESET_VECTOR_1_35_32_W { - U0_U7MC_SFT7110_RESET_VECTOR_1_35_32_W::new(self) + ) -> U0_U7MC_SFT7110_RESET_VECTOR_1_35_32_W { + U0_U7MC_SFT7110_RESET_VECTOR_1_35_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg112.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg112.rs index 50c53b1..ebc4521 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg112.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg112.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_u7mc_sft7110_reset_vector_2_31_0` reader - u0_u7mc_sft7110_reset_vector_2_31_0"] pub type U0_U7MC_SFT7110_RESET_VECTOR_2_31_0_R = crate::FieldReader; #[doc = "Field `u0_u7mc_sft7110_reset_vector_2_31_0` writer - u0_u7mc_sft7110_reset_vector_2_31_0"] -pub type U0_U7MC_SFT7110_RESET_VECTOR_2_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_U7MC_SFT7110_RESET_VECTOR_2_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_u7mc_sft7110_reset_vector_2_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_u7mc_sft7110_reset_vector_2_31_0( &mut self, - ) -> U0_U7MC_SFT7110_RESET_VECTOR_2_31_0_W { - U0_U7MC_SFT7110_RESET_VECTOR_2_31_0_W::new(self) + ) -> U0_U7MC_SFT7110_RESET_VECTOR_2_31_0_W { + U0_U7MC_SFT7110_RESET_VECTOR_2_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg116.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg116.rs index a86dffc..0005df5 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg116.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg116.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_u7mc_sft7110_reset_vector_2_35_32` reader - u0_u7mc_sft7110_reset_vector_2_35_32"] pub type U0_U7MC_SFT7110_RESET_VECTOR_2_35_32_R = crate::FieldReader; #[doc = "Field `u0_u7mc_sft7110_reset_vector_2_35_32` writer - u0_u7mc_sft7110_reset_vector_2_35_32"] -pub type U0_U7MC_SFT7110_RESET_VECTOR_2_35_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 4, O>; +pub type U0_U7MC_SFT7110_RESET_VECTOR_2_35_32_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - u0_u7mc_sft7110_reset_vector_2_35_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_u7mc_sft7110_reset_vector_2_35_32( &mut self, - ) -> U0_U7MC_SFT7110_RESET_VECTOR_2_35_32_W { - U0_U7MC_SFT7110_RESET_VECTOR_2_35_32_W::new(self) + ) -> U0_U7MC_SFT7110_RESET_VECTOR_2_35_32_W { + U0_U7MC_SFT7110_RESET_VECTOR_2_35_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg12.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg12.rs index 5c95c93..58ab4be 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg12.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg12.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `scfg_vout0_remap_awaddr_gpio0` reader - 0: GPIO Group 0 (GPIO21-35) voltage select 3.3V, 1: GPIO Group 0 (GPIO21-35) voltage select 1.8V"] pub type SCFG_VOUT0_REMAP_AWADDR_GPIO0_R = crate::BitReader; #[doc = "Field `scfg_vout0_remap_awaddr_gpio0` writer - 0: GPIO Group 0 (GPIO21-35) voltage select 3.3V, 1: GPIO Group 0 (GPIO21-35) voltage select 1.8V"] -pub type SCFG_VOUT0_REMAP_AWADDR_GPIO0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SCFG_VOUT0_REMAP_AWADDR_GPIO0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scfg_vout0_remap_awaddr_gpio1` reader - 0: GPIO Group 1 (GPIO36-63) voltage select 3.3V, 1: GPIO Group 1 (GPIO36-63) voltage select 1.8V"] pub type SCFG_VOUT0_REMAP_AWADDR_GPIO1_R = crate::BitReader; #[doc = "Field `scfg_vout0_remap_awaddr_gpio1` writer - 0: GPIO Group 1 (GPIO36-63) voltage select 3.3V, 1: GPIO Group 1 (GPIO36-63) voltage select 1.8V"] -pub type SCFG_VOUT0_REMAP_AWADDR_GPIO1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SCFG_VOUT0_REMAP_AWADDR_GPIO1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scfg_vout0_remap_awaddr_gpio2` reader - 0: GPIO Group 2 (GPIO0-6) voltage select 3.3V, 1: GPIO Group 2 (GPIO0-6) voltage select 1.8V"] pub type SCFG_VOUT0_REMAP_AWADDR_GPIO2_R = crate::BitReader; #[doc = "Field `scfg_vout0_remap_awaddr_gpio2` writer - 0: GPIO Group 2 (GPIO0-6) voltage select 3.3V, 1: GPIO Group 2 (GPIO0-6) voltage select 1.8V"] -pub type SCFG_VOUT0_REMAP_AWADDR_GPIO2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SCFG_VOUT0_REMAP_AWADDR_GPIO2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scfg_vout0_remap_awaddr_gpio3` reader - 0: GPIO Group 3 (GPIO7-20) voltage select 3.3V, 1: GPIO Group 3 (GPIO7-20) voltage select 1.8V"] pub type SCFG_VOUT0_REMAP_AWADDR_GPIO3_R = crate::BitReader; #[doc = "Field `scfg_vout0_remap_awaddr_gpio3` writer - 0: GPIO Group 3 (GPIO7-20) voltage select 3.3V, 1: GPIO Group 3 (GPIO7-20) voltage select 1.8V"] -pub type SCFG_VOUT0_REMAP_AWADDR_GPIO3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SCFG_VOUT0_REMAP_AWADDR_GPIO3_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 0: GPIO Group 0 (GPIO21-35) voltage select 3.3V, 1: GPIO Group 0 (GPIO21-35) voltage select 1.8V"] #[inline(always)] @@ -46,34 +46,38 @@ impl W { #[must_use] pub fn scfg_vout0_remap_awaddr_gpio0( &mut self, - ) -> SCFG_VOUT0_REMAP_AWADDR_GPIO0_W { - SCFG_VOUT0_REMAP_AWADDR_GPIO0_W::new(self) + ) -> SCFG_VOUT0_REMAP_AWADDR_GPIO0_W { + SCFG_VOUT0_REMAP_AWADDR_GPIO0_W::new(self, 0) } #[doc = "Bit 1 - 0: GPIO Group 1 (GPIO36-63) voltage select 3.3V, 1: GPIO Group 1 (GPIO36-63) voltage select 1.8V"] #[inline(always)] #[must_use] pub fn scfg_vout0_remap_awaddr_gpio1( &mut self, - ) -> SCFG_VOUT0_REMAP_AWADDR_GPIO1_W { - SCFG_VOUT0_REMAP_AWADDR_GPIO1_W::new(self) + ) -> SCFG_VOUT0_REMAP_AWADDR_GPIO1_W { + SCFG_VOUT0_REMAP_AWADDR_GPIO1_W::new(self, 1) } #[doc = "Bit 2 - 0: GPIO Group 2 (GPIO0-6) voltage select 3.3V, 1: GPIO Group 2 (GPIO0-6) voltage select 1.8V"] #[inline(always)] #[must_use] pub fn scfg_vout0_remap_awaddr_gpio2( &mut self, - ) -> SCFG_VOUT0_REMAP_AWADDR_GPIO2_W { - SCFG_VOUT0_REMAP_AWADDR_GPIO2_W::new(self) + ) -> SCFG_VOUT0_REMAP_AWADDR_GPIO2_W { + SCFG_VOUT0_REMAP_AWADDR_GPIO2_W::new(self, 2) } #[doc = "Bit 3 - 0: GPIO Group 3 (GPIO7-20) voltage select 3.3V, 1: GPIO Group 3 (GPIO7-20) voltage select 1.8V"] #[inline(always)] #[must_use] pub fn scfg_vout0_remap_awaddr_gpio3( &mut self, - ) -> SCFG_VOUT0_REMAP_AWADDR_GPIO3_W { - SCFG_VOUT0_REMAP_AWADDR_GPIO3_W::new(self) + ) -> SCFG_VOUT0_REMAP_AWADDR_GPIO3_W { + SCFG_VOUT0_REMAP_AWADDR_GPIO3_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg120.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg120.rs index 0854306..653b656 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg120.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg120.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_u7mc_sft7110_reset_vector_3_31_0` reader - u0_u7mc_sft7110_reset_vector_3_31_0"] pub type U0_U7MC_SFT7110_RESET_VECTOR_3_31_0_R = crate::FieldReader; #[doc = "Field `u0_u7mc_sft7110_reset_vector_3_31_0` writer - u0_u7mc_sft7110_reset_vector_3_31_0"] -pub type U0_U7MC_SFT7110_RESET_VECTOR_3_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_U7MC_SFT7110_RESET_VECTOR_3_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_u7mc_sft7110_reset_vector_3_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_u7mc_sft7110_reset_vector_3_31_0( &mut self, - ) -> U0_U7MC_SFT7110_RESET_VECTOR_3_31_0_W { - U0_U7MC_SFT7110_RESET_VECTOR_3_31_0_W::new(self) + ) -> U0_U7MC_SFT7110_RESET_VECTOR_3_31_0_W { + U0_U7MC_SFT7110_RESET_VECTOR_3_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg124.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg124.rs index dacd7e6..0356df5 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg124.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg124.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_u7mc_sft7110_reset_vector_3_35_32` reader - u0_u7mc_sft7110_reset_vector_3_35_32"] pub type U0_U7MC_SFT7110_RESET_VECTOR_3_35_32_R = crate::FieldReader; #[doc = "Field `u0_u7mc_sft7110_reset_vector_3_35_32` writer - u0_u7mc_sft7110_reset_vector_3_35_32"] -pub type U0_U7MC_SFT7110_RESET_VECTOR_3_35_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 4, O>; +pub type U0_U7MC_SFT7110_RESET_VECTOR_3_35_32_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - u0_u7mc_sft7110_reset_vector_3_35_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_u7mc_sft7110_reset_vector_3_35_32( &mut self, - ) -> U0_U7MC_SFT7110_RESET_VECTOR_3_35_32_W { - U0_U7MC_SFT7110_RESET_VECTOR_3_35_32_W::new(self) + ) -> U0_U7MC_SFT7110_RESET_VECTOR_3_35_32_W { + U0_U7MC_SFT7110_RESET_VECTOR_3_35_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg128.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg128.rs index da52f0c..369726c 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg128.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg128.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_u7mc_sft7110_reset_vector_4_31_0` reader - u0_u7mc_sft7110_reset_vector_4_31_0"] pub type U0_U7MC_SFT7110_RESET_VECTOR_4_31_0_R = crate::FieldReader; #[doc = "Field `u0_u7mc_sft7110_reset_vector_4_31_0` writer - u0_u7mc_sft7110_reset_vector_4_31_0"] -pub type U0_U7MC_SFT7110_RESET_VECTOR_4_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_U7MC_SFT7110_RESET_VECTOR_4_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_u7mc_sft7110_reset_vector_4_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_u7mc_sft7110_reset_vector_4_31_0( &mut self, - ) -> U0_U7MC_SFT7110_RESET_VECTOR_4_31_0_W { - U0_U7MC_SFT7110_RESET_VECTOR_4_31_0_W::new(self) + ) -> U0_U7MC_SFT7110_RESET_VECTOR_4_31_0_W { + U0_U7MC_SFT7110_RESET_VECTOR_4_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg136.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg136.rs index 3a367e8..d7bd89f 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg136.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg136.rs @@ -5,63 +5,57 @@ pub type W = crate::W; #[doc = "Field `u0_venc_intsram_sram_config_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] pub type U0_VENC_INTSRAM_SRAM_CONFIG_SLP_R = crate::BitReader; #[doc = "Field `u0_venc_intsram_sram_config_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] -pub type U0_VENC_INTSRAM_SRAM_CONFIG_SLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_VENC_INTSRAM_SRAM_CONFIG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_venc_intsram_sram_config_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] pub type U0_VENC_INTSRAM_SRAM_CONFIG_SRAM_CONFIG_SD_R = crate::BitReader; #[doc = "Field `u0_venc_intsram_sram_config_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] -pub type U0_VENC_INTSRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_VENC_INTSRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_venc_intsram_sram_config_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_VENC_INTSRAM_SRAM_CONFIG_RTSEL_R = crate::FieldReader; #[doc = "Field `u0_venc_intsram_sram_config_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_VENC_INTSRAM_SRAM_CONFIG_RTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_VENC_INTSRAM_SRAM_CONFIG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_venc_intsram_sram_config_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_VENC_INTSRAM_SRAM_CONFIG_PTSEL_R = crate::FieldReader; #[doc = "Field `u0_venc_intsram_sram_config_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_VENC_INTSRAM_SRAM_CONFIG_PTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_VENC_INTSRAM_SRAM_CONFIG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_venc_intsram_sram_config_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] pub type U0_VENC_INTSRAM_SRAM_CONFIG_TRB_R = crate::FieldReader; #[doc = "Field `u0_venc_intsram_sram_config_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] -pub type U0_VENC_INTSRAM_SRAM_CONFIG_TRB_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_VENC_INTSRAM_SRAM_CONFIG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_venc_intsram_sram_config_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_VENC_INTSRAM_SRAM_CONFIG_WTSEL_R = crate::FieldReader; #[doc = "Field `u0_venc_intsram_sram_config_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_VENC_INTSRAM_SRAM_CONFIG_WTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_VENC_INTSRAM_SRAM_CONFIG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_venc_intsram_sram_config_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] pub type U0_VENC_INTSRAM_SRAM_CONFIG_VS_R = crate::BitReader; #[doc = "Field `u0_venc_intsram_sram_config_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] -pub type U0_VENC_INTSRAM_SRAM_CONFIG_VS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_VENC_INTSRAM_SRAM_CONFIG_VS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_venc_intsram_sram_config_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] pub type U0_VENC_INTSRAM_SRAM_CONFIG_VG_R = crate::BitReader; #[doc = "Field `u0_venc_intsram_sram_config_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] -pub type U0_VENC_INTSRAM_SRAM_CONFIG_VG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_VENC_INTSRAM_SRAM_CONFIG_VG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_wave420l_i_ipu_current_buffer` reader - This signal indicates which buffer is currently active so that the VPU can correctly use the ipu_end_of_row signal for row counter."] pub type U0_WAVE420L_I_IPU_CURRENT_BUFFER_R = crate::FieldReader; #[doc = "Field `u0_wave420l_i_ipu_current_buffer` writer - This signal indicates which buffer is currently active so that the VPU can correctly use the ipu_end_of_row signal for row counter."] -pub type U0_WAVE420L_I_IPU_CURRENT_BUFFER_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_WAVE420L_I_IPU_CURRENT_BUFFER_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_wave420l_i_ipu_end_of_row` reader - This signal is flipped every time when the IPU completes writing a row."] pub type U0_WAVE420L_I_IPU_END_OF_ROW_R = crate::BitReader; #[doc = "Field `u0_wave420l_i_ipu_end_of_row` writer - This signal is flipped every time when the IPU completes writing a row."] -pub type U0_WAVE420L_I_IPU_END_OF_ROW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_WAVE420L_I_IPU_END_OF_ROW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_wave420l_i_ipu_new_frame` reader - This signal is flipped every time when the IPU completes writing a new frame."] pub type U0_WAVE420L_I_IPU_NEW_FRAME_R = crate::BitReader; #[doc = "Field `u0_wave420l_i_ipu_new_frame` writer - This signal is flipped every time when the IPU completes writing a new frame."] -pub type U0_WAVE420L_I_IPU_NEW_FRAME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_WAVE420L_I_IPU_NEW_FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_wave420l_o_vpu_idle` reader - VPU monitoring signal. This signal gives out an opposite value of VPU_BUSY register."] pub type U0_WAVE420L_O_VPU_IDLE_R = crate::BitReader; #[doc = "Field `u1_can_ctrl_can_fd_enable` reader - u1_can_ctrl_can_fd_enable"] pub type U1_CAN_CTRL_CAN_FD_ENABLE_R = crate::BitReader; #[doc = "Field `u1_can_ctrl_can_fd_enable` writer - u1_can_ctrl_can_fd_enable"] -pub type U1_CAN_CTRL_CAN_FD_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_CAN_CTRL_CAN_FD_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_can_ctrl_host_ecc_disable` reader - u1_can_ctrl_host_ecc_disable"] pub type U1_CAN_CTRL_HOST_ECC_DISABLE_R = crate::BitReader; #[doc = "Field `u1_can_ctrl_host_ecc_disable` writer - u1_can_ctrl_host_ecc_disable"] -pub type U1_CAN_CTRL_HOST_ECC_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_CAN_CTRL_HOST_ECC_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] #[inline(always)] @@ -142,106 +136,110 @@ impl W { #[must_use] pub fn u0_venc_intsram_sram_config_slp( &mut self, - ) -> U0_VENC_INTSRAM_SRAM_CONFIG_SLP_W { - U0_VENC_INTSRAM_SRAM_CONFIG_SLP_W::new(self) + ) -> U0_VENC_INTSRAM_SRAM_CONFIG_SLP_W { + U0_VENC_INTSRAM_SRAM_CONFIG_SLP_W::new(self, 0) } #[doc = "Bit 1 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_venc_intsram_sram_config_sram_config_sd( &mut self, - ) -> U0_VENC_INTSRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W { - U0_VENC_INTSRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self) + ) -> U0_VENC_INTSRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W { + U0_VENC_INTSRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self, 1) } #[doc = "Bits 2:3 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_venc_intsram_sram_config_rtsel( &mut self, - ) -> U0_VENC_INTSRAM_SRAM_CONFIG_RTSEL_W { - U0_VENC_INTSRAM_SRAM_CONFIG_RTSEL_W::new(self) + ) -> U0_VENC_INTSRAM_SRAM_CONFIG_RTSEL_W { + U0_VENC_INTSRAM_SRAM_CONFIG_RTSEL_W::new(self, 2) } #[doc = "Bits 4:5 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_venc_intsram_sram_config_ptsel( &mut self, - ) -> U0_VENC_INTSRAM_SRAM_CONFIG_PTSEL_W { - U0_VENC_INTSRAM_SRAM_CONFIG_PTSEL_W::new(self) + ) -> U0_VENC_INTSRAM_SRAM_CONFIG_PTSEL_W { + U0_VENC_INTSRAM_SRAM_CONFIG_PTSEL_W::new(self, 4) } #[doc = "Bits 6:7 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_venc_intsram_sram_config_trb( &mut self, - ) -> U0_VENC_INTSRAM_SRAM_CONFIG_TRB_W { - U0_VENC_INTSRAM_SRAM_CONFIG_TRB_W::new(self) + ) -> U0_VENC_INTSRAM_SRAM_CONFIG_TRB_W { + U0_VENC_INTSRAM_SRAM_CONFIG_TRB_W::new(self, 6) } #[doc = "Bits 8:9 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_venc_intsram_sram_config_wtsel( &mut self, - ) -> U0_VENC_INTSRAM_SRAM_CONFIG_WTSEL_W { - U0_VENC_INTSRAM_SRAM_CONFIG_WTSEL_W::new(self) + ) -> U0_VENC_INTSRAM_SRAM_CONFIG_WTSEL_W { + U0_VENC_INTSRAM_SRAM_CONFIG_WTSEL_W::new(self, 8) } #[doc = "Bit 10 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_venc_intsram_sram_config_vs( &mut self, - ) -> U0_VENC_INTSRAM_SRAM_CONFIG_VS_W { - U0_VENC_INTSRAM_SRAM_CONFIG_VS_W::new(self) + ) -> U0_VENC_INTSRAM_SRAM_CONFIG_VS_W { + U0_VENC_INTSRAM_SRAM_CONFIG_VS_W::new(self, 10) } #[doc = "Bit 11 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_venc_intsram_sram_config_vg( &mut self, - ) -> U0_VENC_INTSRAM_SRAM_CONFIG_VG_W { - U0_VENC_INTSRAM_SRAM_CONFIG_VG_W::new(self) + ) -> U0_VENC_INTSRAM_SRAM_CONFIG_VG_W { + U0_VENC_INTSRAM_SRAM_CONFIG_VG_W::new(self, 11) } #[doc = "Bits 12:14 - This signal indicates which buffer is currently active so that the VPU can correctly use the ipu_end_of_row signal for row counter."] #[inline(always)] #[must_use] pub fn u0_wave420l_i_ipu_current_buffer( &mut self, - ) -> U0_WAVE420L_I_IPU_CURRENT_BUFFER_W { - U0_WAVE420L_I_IPU_CURRENT_BUFFER_W::new(self) + ) -> U0_WAVE420L_I_IPU_CURRENT_BUFFER_W { + U0_WAVE420L_I_IPU_CURRENT_BUFFER_W::new(self, 12) } #[doc = "Bit 15 - This signal is flipped every time when the IPU completes writing a row."] #[inline(always)] #[must_use] pub fn u0_wave420l_i_ipu_end_of_row( &mut self, - ) -> U0_WAVE420L_I_IPU_END_OF_ROW_W { - U0_WAVE420L_I_IPU_END_OF_ROW_W::new(self) + ) -> U0_WAVE420L_I_IPU_END_OF_ROW_W { + U0_WAVE420L_I_IPU_END_OF_ROW_W::new(self, 15) } #[doc = "Bit 16 - This signal is flipped every time when the IPU completes writing a new frame."] #[inline(always)] #[must_use] pub fn u0_wave420l_i_ipu_new_frame( &mut self, - ) -> U0_WAVE420L_I_IPU_NEW_FRAME_W { - U0_WAVE420L_I_IPU_NEW_FRAME_W::new(self) + ) -> U0_WAVE420L_I_IPU_NEW_FRAME_W { + U0_WAVE420L_I_IPU_NEW_FRAME_W::new(self, 16) } #[doc = "Bit 18 - u1_can_ctrl_can_fd_enable"] #[inline(always)] #[must_use] pub fn u1_can_ctrl_can_fd_enable( &mut self, - ) -> U1_CAN_CTRL_CAN_FD_ENABLE_W { - U1_CAN_CTRL_CAN_FD_ENABLE_W::new(self) + ) -> U1_CAN_CTRL_CAN_FD_ENABLE_W { + U1_CAN_CTRL_CAN_FD_ENABLE_W::new(self, 18) } #[doc = "Bit 19 - u1_can_ctrl_host_ecc_disable"] #[inline(always)] #[must_use] pub fn u1_can_ctrl_host_ecc_disable( &mut self, - ) -> U1_CAN_CTRL_HOST_ECC_DISABLE_W { - U1_CAN_CTRL_HOST_ECC_DISABLE_W::new(self) + ) -> U1_CAN_CTRL_HOST_ECC_DISABLE_W { + U1_CAN_CTRL_HOST_ECC_DISABLE_W::new(self, 19) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg140.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg140.rs index 53acc9c..93c9a11 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg140.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg140.rs @@ -7,40 +7,35 @@ pub type U1_CAN_CTRL_HOST_IF_R = crate::FieldReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_SLP_R = crate::BitReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] -pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_SLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_R = crate::BitReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] -pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_R = crate::FieldReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_R = crate::FieldReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_TRB_R = crate::FieldReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] -pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_TRB_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_R = crate::FieldReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_VS_R = crate::BitReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] -pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_VS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_VS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_VG_R = crate::BitReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] -pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_VG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_VG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:18 - u1_can_ctrl_host_if"] #[inline(always)] @@ -96,66 +91,70 @@ impl W { #[must_use] pub fn u1_gmac5_axi64_scfg_ram_cfg_slp( &mut self, - ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_SLP_W { - U1_GMAC5_AXI64_SCFG_RAM_CFG_SLP_W::new(self) + ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_SLP_W { + U1_GMAC5_AXI64_SCFG_RAM_CFG_SLP_W::new(self, 19) } #[doc = "Bit 20 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u1_gmac5_axi64_scfg_ram_cfg_sram_config_sd( &mut self, - ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W { - U1_GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W::new(self) + ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W { + U1_GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W::new(self, 20) } #[doc = "Bits 21:22 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u1_gmac5_axi64_scfg_ram_cfg_rtsel( &mut self, - ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W { - U1_GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W::new(self) + ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W { + U1_GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W::new(self, 21) } #[doc = "Bits 23:24 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u1_gmac5_axi64_scfg_ram_cfg_ptsel( &mut self, - ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W { - U1_GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W::new(self) + ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W { + U1_GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W::new(self, 23) } #[doc = "Bits 25:26 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u1_gmac5_axi64_scfg_ram_cfg_trb( &mut self, - ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_TRB_W { - U1_GMAC5_AXI64_SCFG_RAM_CFG_TRB_W::new(self) + ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_TRB_W { + U1_GMAC5_AXI64_SCFG_RAM_CFG_TRB_W::new(self, 25) } #[doc = "Bits 27:28 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u1_gmac5_axi64_scfg_ram_cfg_wtsel( &mut self, - ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W { - U1_GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W::new(self) + ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W { + U1_GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W::new(self, 27) } #[doc = "Bit 29 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u1_gmac5_axi64_scfg_ram_cfg_vs( &mut self, - ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_VS_W { - U1_GMAC5_AXI64_SCFG_RAM_CFG_VS_W::new(self) + ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_VS_W { + U1_GMAC5_AXI64_SCFG_RAM_CFG_VS_W::new(self, 29) } #[doc = "Bit 30 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u1_gmac5_axi64_scfg_ram_cfg_vg( &mut self, - ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_VG_W { - U1_GMAC5_AXI64_SCFG_RAM_CFG_VG_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_VG_W { + U1_GMAC5_AXI64_SCFG_RAM_CFG_VG_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg144.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg144.rs index 9d929e0..f2ea1a5 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg144.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg144.rs @@ -7,7 +7,7 @@ pub type U1_GMAC5_AXI64_MAC_SPEED_0_R = crate::FieldReader; #[doc = "Field `u1_gmac5_axi64_phy_intf_sel_i` reader - Active PHY Selected | When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. | Values: 0x0:(GMII or MII), 0x01:RGMII, 0x2:SGMII, 0x3:TBI, 0x4:RMII, 0x5:RTBI, 0x6:SMII, 0x7:REVMII"] pub type U1_GMAC5_AXI64_PHY_INTF_SEL_I_R = crate::FieldReader; #[doc = "Field `u1_gmac5_axi64_phy_intf_sel_i` writer - Active PHY Selected | When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. | Values: 0x0:(GMII or MII), 0x01:RGMII, 0x2:SGMII, 0x3:TBI, 0x4:RMII, 0x5:RTBI, 0x6:SMII, 0x7:REVMII"] -pub type U1_GMAC5_AXI64_PHY_INTF_SEL_I_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U1_GMAC5_AXI64_PHY_INTF_SEL_I_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:1 - u1_gmac5_axi64_mac_speed_0"] #[inline(always)] @@ -26,10 +26,14 @@ impl W { #[must_use] pub fn u1_gmac5_axi64_phy_intf_sel_i( &mut self, - ) -> U1_GMAC5_AXI64_PHY_INTF_SEL_I_W { - U1_GMAC5_AXI64_PHY_INTF_SEL_I_W::new(self) + ) -> U1_GMAC5_AXI64_PHY_INTF_SEL_I_W { + U1_GMAC5_AXI64_PHY_INTF_SEL_I_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg148.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg148.rs index 8066569..db39868 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg148.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg148.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg152.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg152.rs index 7a1a21a..4e5bf6c 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg152.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg152.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg156.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg156.rs index 1dcfd12..d5ac3c2 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg156.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg156.rs @@ -7,25 +7,25 @@ pub type U1_I2C_IC_EN_R = crate::BitReader; #[doc = "Field `u1_sdio_data_strobe_phase_ctrl` reader - Data strobe delay chain select."] pub type U1_SDIO_DATA_STROBE_PHASE_CTRL_R = crate::FieldReader; #[doc = "Field `u1_sdio_data_strobe_phase_ctrl` writer - Data strobe delay chain select."] -pub type U1_SDIO_DATA_STROBE_PHASE_CTRL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U1_SDIO_DATA_STROBE_PHASE_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u1_sdio_hbig_endian` reader - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] pub type U1_SDIO_HBIG_ENDIAN_R = crate::BitReader; #[doc = "Field `u1_sdio_hbig_endian` writer - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] -pub type U1_SDIO_HBIG_ENDIAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_SDIO_HBIG_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_sdio_m_hbig_endian` reader - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] pub type U1_SDIO_M_HBIG_ENDIAN_R = crate::BitReader; #[doc = "Field `u1_sdio_m_hbig_endian` writer - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] -pub type U1_SDIO_M_HBIG_ENDIAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_SDIO_M_HBIG_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_reset_ctrl_clr_reset_status` reader - u1_reset_ctrl_clr_reset_status"] pub type U1_RESET_CTRL_CLR_RESET_STATUS_R = crate::BitReader; #[doc = "Field `u1_reset_ctrl_clr_reset_status` writer - u1_reset_ctrl_clr_reset_status"] -pub type U1_RESET_CTRL_CLR_RESET_STATUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_RESET_CTRL_CLR_RESET_STATUS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_reset_ctrl_pll_timecnt_finish` reader - u1_reset_ctrl_pll_timecnt_finish"] pub type U1_RESET_CTRL_PLL_TIMECNT_FINISH_R = crate::BitReader; #[doc = "Field `u1_reset_ctrl_rstn_sw` reader - u1_reset_ctrl_rstn_sw"] pub type U1_RESET_CTRL_RSTN_SW_R = crate::BitReader; #[doc = "Field `u1_reset_ctrl_rstn_sw` writer - u1_reset_ctrl_rstn_sw"] -pub type U1_RESET_CTRL_RSTN_SW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_RESET_CTRL_RSTN_SW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_reset_ctrl_sys_reset_status` reader - u1_reset_ctrl_sys_reset_status"] pub type U1_RESET_CTRL_SYS_RESET_STATUS_R = crate::FieldReader; #[doc = "Field `u2_i2c_ic_en` reader - I2C interface enable."] @@ -111,42 +111,44 @@ impl W { #[must_use] pub fn u1_sdio_data_strobe_phase_ctrl( &mut self, - ) -> U1_SDIO_DATA_STROBE_PHASE_CTRL_W { - U1_SDIO_DATA_STROBE_PHASE_CTRL_W::new(self) + ) -> U1_SDIO_DATA_STROBE_PHASE_CTRL_W { + U1_SDIO_DATA_STROBE_PHASE_CTRL_W::new(self, 1) } #[doc = "Bit 6 - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] #[inline(always)] #[must_use] - pub fn u1_sdio_hbig_endian( - &mut self, - ) -> U1_SDIO_HBIG_ENDIAN_W { - U1_SDIO_HBIG_ENDIAN_W::new(self) + pub fn u1_sdio_hbig_endian(&mut self) -> U1_SDIO_HBIG_ENDIAN_W { + U1_SDIO_HBIG_ENDIAN_W::new(self, 6) } #[doc = "Bit 7 - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] #[inline(always)] #[must_use] pub fn u1_sdio_m_hbig_endian( &mut self, - ) -> U1_SDIO_M_HBIG_ENDIAN_W { - U1_SDIO_M_HBIG_ENDIAN_W::new(self) + ) -> U1_SDIO_M_HBIG_ENDIAN_W { + U1_SDIO_M_HBIG_ENDIAN_W::new(self, 7) } #[doc = "Bit 8 - u1_reset_ctrl_clr_reset_status"] #[inline(always)] #[must_use] pub fn u1_reset_ctrl_clr_reset_status( &mut self, - ) -> U1_RESET_CTRL_CLR_RESET_STATUS_W { - U1_RESET_CTRL_CLR_RESET_STATUS_W::new(self) + ) -> U1_RESET_CTRL_CLR_RESET_STATUS_W { + U1_RESET_CTRL_CLR_RESET_STATUS_W::new(self, 8) } #[doc = "Bit 10 - u1_reset_ctrl_rstn_sw"] #[inline(always)] #[must_use] pub fn u1_reset_ctrl_rstn_sw( &mut self, - ) -> U1_RESET_CTRL_RSTN_SW_W { - U1_RESET_CTRL_RSTN_SW_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U1_RESET_CTRL_RSTN_SW_W { + U1_RESET_CTRL_RSTN_SW_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg16.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg16.rs index 4b51d61..462d45a 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg16.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg16.rs @@ -9,11 +9,11 @@ pub type U0_WAVE511_O_VPU_IDLE_R = crate::BitReader; #[doc = "Field `u0_can_ctrl_can_fd_enable` reader - u0_can_ctrl_can_fd_enable"] pub type U0_CAN_CTRL_CAN_FD_ENABLE_R = crate::BitReader; #[doc = "Field `u0_can_ctrl_can_fd_enable` writer - u0_can_ctrl_can_fd_enable"] -pub type U0_CAN_CTRL_CAN_FD_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CAN_CTRL_CAN_FD_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_can_ctrl_host_ecc_disable` reader - u0_can_ctrl_host_ecc_disable"] pub type U0_CAN_CTRL_HOST_ECC_DISABLE_R = crate::BitReader; #[doc = "Field `u0_can_ctrl_host_ecc_disable` writer - u0_can_ctrl_host_ecc_disable"] -pub type U0_CAN_CTRL_HOST_ECC_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CAN_CTRL_HOST_ECC_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_can_ctrl_host_if` reader - u0_can_ctrl_host_if"] pub type U0_CAN_CTRL_HOST_IF_R = crate::FieldReader; #[doc = "Field `u0_cdns_qspi_scfg_qspi_sclk_dlychain_sel` reader - des_qspi_sclk_dla: clock delay"] @@ -58,18 +58,22 @@ impl W { #[must_use] pub fn u0_can_ctrl_can_fd_enable( &mut self, - ) -> U0_CAN_CTRL_CAN_FD_ENABLE_W { - U0_CAN_CTRL_CAN_FD_ENABLE_W::new(self) + ) -> U0_CAN_CTRL_CAN_FD_ENABLE_W { + U0_CAN_CTRL_CAN_FD_ENABLE_W::new(self, 3) } #[doc = "Bit 4 - u0_can_ctrl_host_ecc_disable"] #[inline(always)] #[must_use] pub fn u0_can_ctrl_host_ecc_disable( &mut self, - ) -> U0_CAN_CTRL_HOST_ECC_DISABLE_W { - U0_CAN_CTRL_HOST_ECC_DISABLE_W::new(self) + ) -> U0_CAN_CTRL_HOST_ECC_DISABLE_W { + U0_CAN_CTRL_HOST_ECC_DISABLE_W::new(self, 4) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg20.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg20.rs index 7978cba..834cd83 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg20.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg20.rs @@ -5,77 +5,67 @@ pub type W = crate::W; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SLP_R = crate::BitReader; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] -pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_R = crate::BitReader; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] -pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_RTSEL_R = crate::FieldReader; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_RTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_PTSEL_R = crate::FieldReader; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_PTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_TRB_R = crate::FieldReader; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] -pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_TRB_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_WTSEL_R = crate::FieldReader; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_WTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VS_R = crate::BitReader; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] -pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VG_R = crate::BitReader; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] -pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SLP_R = crate::BitReader; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] -pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_R = crate::BitReader; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] -pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_RTSEL_R = crate::FieldReader; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_RTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_PTSEL_R = crate::FieldReader; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_PTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_TRB_R = crate::FieldReader; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] -pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_TRB_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_WTSEL_R = crate::FieldReader; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_WTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VS_R = crate::BitReader; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] -pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VG_R = crate::BitReader; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] -pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdns_spdif_trmodeo` reader - 1 for transmitter 0 for receiver"] pub type U0_CDNS_SPDIF_TRMODEO_R = crate::BitReader; #[doc = "Field `u0_i2c_ic_en` reader - I2C interface enable"] @@ -83,11 +73,11 @@ pub type U0_I2C_IC_EN_R = crate::BitReader; #[doc = "Field `u0_sdio_data_strobe_phase_ctrl` reader - Data strobe delay chain select"] pub type U0_SDIO_DATA_STROBE_PHASE_CTRL_R = crate::FieldReader; #[doc = "Field `u0_sdio_data_strobe_phase_ctrl` writer - Data strobe delay chain select"] -pub type U0_SDIO_DATA_STROBE_PHASE_CTRL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_SDIO_DATA_STROBE_PHASE_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_sdio_hbig_endian` reader - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] pub type U0_SDIO_HBIG_ENDIAN_R = crate::BitReader; #[doc = "Field `u0_sdio_hbig_endian` writer - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] -pub type U0_SDIO_HBIG_ENDIAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_SDIO_HBIG_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] #[inline(always)] @@ -200,146 +190,148 @@ impl W { #[must_use] pub fn u0_cdns_qspi_scfg_sram_config_slp( &mut self, - ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SLP_W { - U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SLP_W::new(self) + ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SLP_W { + U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SLP_W::new(self, 0) } #[doc = "Bit 1 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_cdns_qspi_scfg_sram_config_sram_config_sd( &mut self, - ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W { - U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self) + ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W { + U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self, 1) } #[doc = "Bits 2:3 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_cdns_qspi_scfg_sram_config_rtsel( &mut self, - ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_RTSEL_W { - U0_CDNS_QSPI_SCFG_SRAM_CONFIG_RTSEL_W::new(self) + ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_RTSEL_W { + U0_CDNS_QSPI_SCFG_SRAM_CONFIG_RTSEL_W::new(self, 2) } #[doc = "Bits 4:5 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_cdns_qspi_scfg_sram_config_ptsel( &mut self, - ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_PTSEL_W { - U0_CDNS_QSPI_SCFG_SRAM_CONFIG_PTSEL_W::new(self) + ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_PTSEL_W { + U0_CDNS_QSPI_SCFG_SRAM_CONFIG_PTSEL_W::new(self, 4) } #[doc = "Bits 6:7 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_cdns_qspi_scfg_sram_config_trb( &mut self, - ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_TRB_W { - U0_CDNS_QSPI_SCFG_SRAM_CONFIG_TRB_W::new(self) + ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_TRB_W { + U0_CDNS_QSPI_SCFG_SRAM_CONFIG_TRB_W::new(self, 6) } #[doc = "Bits 8:9 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_cdns_qspi_scfg_sram_config_wtsel( &mut self, - ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_WTSEL_W { - U0_CDNS_QSPI_SCFG_SRAM_CONFIG_WTSEL_W::new(self) + ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_WTSEL_W { + U0_CDNS_QSPI_SCFG_SRAM_CONFIG_WTSEL_W::new(self, 8) } #[doc = "Bit 10 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_cdns_qspi_scfg_sram_config_vs( &mut self, - ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VS_W { - U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VS_W::new(self) + ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VS_W { + U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VS_W::new(self, 10) } #[doc = "Bit 11 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_cdns_qspi_scfg_sram_config_vg( &mut self, - ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VG_W { - U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VG_W::new(self) + ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VG_W { + U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VG_W::new(self, 11) } #[doc = "Bit 12 - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_cdns_spdif_scfg_sram_config_slp( &mut self, - ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SLP_W { - U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SLP_W::new(self) + ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SLP_W { + U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SLP_W::new(self, 12) } #[doc = "Bit 13 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_cdns_spdif_scfg_sram_config_sram_config_sd( &mut self, - ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W { - U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self) + ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W { + U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self, 13) } #[doc = "Bits 14:15 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_cdns_spdif_scfg_sram_config_rtsel( &mut self, - ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_RTSEL_W { - U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_RTSEL_W::new(self) + ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_RTSEL_W { + U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_RTSEL_W::new(self, 14) } #[doc = "Bits 16:17 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_cdns_spdif_scfg_sram_config_ptsel( &mut self, - ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_PTSEL_W { - U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_PTSEL_W::new(self) + ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_PTSEL_W { + U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_PTSEL_W::new(self, 16) } #[doc = "Bits 18:19 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_cdns_spdif_scfg_sram_config_trb( &mut self, - ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_TRB_W { - U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_TRB_W::new(self) + ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_TRB_W { + U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_TRB_W::new(self, 18) } #[doc = "Bits 20:21 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_cdns_spdif_scfg_sram_config_wtsel( &mut self, - ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_WTSEL_W { - U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_WTSEL_W::new(self) + ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_WTSEL_W { + U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_WTSEL_W::new(self, 20) } #[doc = "Bit 22 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_cdns_spdif_scfg_sram_config_vs( &mut self, - ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VS_W { - U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VS_W::new(self) + ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VS_W { + U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VS_W::new(self, 22) } #[doc = "Bit 23 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_cdns_spdif_scfg_sram_config_vg( &mut self, - ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VG_W { - U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VG_W::new(self) + ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VG_W { + U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VG_W::new(self, 23) } #[doc = "Bits 26:30 - Data strobe delay chain select"] #[inline(always)] #[must_use] pub fn u0_sdio_data_strobe_phase_ctrl( &mut self, - ) -> U0_SDIO_DATA_STROBE_PHASE_CTRL_W { - U0_SDIO_DATA_STROBE_PHASE_CTRL_W::new(self) + ) -> U0_SDIO_DATA_STROBE_PHASE_CTRL_W { + U0_SDIO_DATA_STROBE_PHASE_CTRL_W::new(self, 26) } #[doc = "Bit 31 - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] #[inline(always)] #[must_use] - pub fn u0_sdio_hbig_endian( - &mut self, - ) -> U0_SDIO_HBIG_ENDIAN_W { - U0_SDIO_HBIG_ENDIAN_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn u0_sdio_hbig_endian(&mut self) -> U0_SDIO_HBIG_ENDIAN_W { + U0_SDIO_HBIG_ENDIAN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg24.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg24.rs index a290cdf..5cc5c44 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg24.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg24.rs @@ -5,80 +5,75 @@ pub type W = crate::W; #[doc = "Field `u0_sdio_m_hbig_endian` reader - AHB master bus interface endianess: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] pub type U0_SDIO_M_HBIG_ENDIAN_R = crate::BitReader; #[doc = "Field `u0_sdio_m_hbig_endian` writer - AHB master bus interface endianess: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] -pub type U0_SDIO_M_HBIG_ENDIAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_SDIO_M_HBIG_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_i2srx_3ch_adc_ena` reader - u0_i2srx_3ch_adc_ena"] pub type U0_I2SRX_3CH_ADC_ENA_R = crate::BitReader; #[doc = "Field `u0_i2srx_3ch_adc_ena` writer - u0_i2srx_3ch_adc_ena"] -pub type U0_I2SRX_3CH_ADC_ENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_I2SRX_3CH_ADC_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_intmem_rom_sram_scfg_disable_rom` reader - u0_intmem_rom_sram_scfg_disable_rom"] pub type U0_INTMEM_ROM_SRAM_SCFG_DISABLE_ROM_R = crate::BitReader; #[doc = "Field `u0_intmem_rom_sram_scfg_disable_rom` writer - u0_intmem_rom_sram_scfg_disable_rom"] -pub type U0_INTMEM_ROM_SRAM_SCFG_DISABLE_ROM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_INTMEM_ROM_SRAM_SCFG_DISABLE_ROM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_intmem_rom_sram_sram_config_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SLP_R = crate::BitReader; #[doc = "Field `u0_intmem_rom_sram_sram_config_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] -pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_intmem_rom_sram_sram_config_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SRAM_CONFIG_SD_R = crate::BitReader; #[doc = "Field `u0_intmem_rom_sram_sram_config_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] -pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_intmem_rom_sram_sram_config_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_RTSEL_R = crate::FieldReader; #[doc = "Field `u0_intmem_rom_sram_sram_config_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_RTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_intmem_rom_sram_sram_config_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_PTSEL_R = crate::FieldReader; #[doc = "Field `u0_intmem_rom_sram_sram_config_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_PTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_intmem_rom_sram_sram_config_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_TRB_R = crate::FieldReader; #[doc = "Field `u0_intmem_rom_sram_sram_config_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] -pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_TRB_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_intmem_rom_sram_sram_config_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_WTSEL_R = crate::FieldReader; #[doc = "Field `u0_intmem_rom_sram_sram_config_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_WTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_intmem_rom_sram_sram_config_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VS_R = crate::BitReader; #[doc = "Field `u0_intmem_rom_sram_sram_config_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] -pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_intmem_rom_sram_sram_config_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VG_R = crate::BitReader; #[doc = "Field `u0_intmem_rom_sram_sram_config_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] -pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_jtag_daisy_chain_jtag_en_0` reader - u0_jtag_daisy_chain_jtag_en_0"] pub type U0_JTAG_DAISY_CHAIN_JTAG_EN_0_R = crate::BitReader; #[doc = "Field `u0_jtag_daisy_chain_jtag_en_0` writer - u0_jtag_daisy_chain_jtag_en_0"] -pub type U0_JTAG_DAISY_CHAIN_JTAG_EN_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_JTAG_DAISY_CHAIN_JTAG_EN_0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_jtag_daisy_chain_jtag_en_1` reader - u0_jtag_daisy_chain_jtag_en_1"] pub type U0_JTAG_DAISY_CHAIN_JTAG_EN_1_R = crate::BitReader; #[doc = "Field `u0_jtag_daisy_chain_jtag_en_1` writer - u0_jtag_daisy_chain_jtag_en_1"] -pub type U0_JTAG_DAISY_CHAIN_JTAG_EN_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_JTAG_DAISY_CHAIN_JTAG_EN_1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pdrstn_split_sw_usbpipe_plugen` reader - u0_pdrstn_split_sw_usbpipe_plugen"] pub type U0_PDRSTN_SPLIT_SW_USBPIPE_PLUGEN_R = crate::BitReader; #[doc = "Field `u0_pdrstn_split_sw_usbpipe_plugen` writer - u0_pdrstn_split_sw_usbpipe_plugen"] -pub type U0_PDRSTN_SPLIT_SW_USBPIPE_PLUGEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PDRSTN_SPLIT_SW_USBPIPE_PLUGEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll0_cpi_bias` reader - u0_pll_wrap_pll0_cpi_bias"] pub type U0_PLL_WRAP_PLL0_CPI_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_cpi_bias` writer - u0_pll_wrap_pll0_cpi_bias"] -pub type U0_PLL_WRAP_PLL0_CPI_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U0_PLL_WRAP_PLL0_CPI_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_pll_wrap_pll0_cpp_bias` reader - u0_pll_wrap_pll0_cpp_bias"] pub type U0_PLL_WRAP_PLL0_CPP_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_cpp_bias` writer - u0_pll_wrap_pll0_cpp_bias"] -pub type U0_PLL_WRAP_PLL0_CPP_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U0_PLL_WRAP_PLL0_CPP_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_pll_wrap_pll0_dacpd` reader - u0_pll_wrap_pll0_dacpd"] pub type U0_PLL_WRAP_PLL0_DACPD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll0_dacpd` writer - u0_pll_wrap_pll0_dacpd"] -pub type U0_PLL_WRAP_PLL0_DACPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL0_DACPD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll0_dsmpd` reader - u0_pll_wrap_pll0_dsmpd"] pub type U0_PLL_WRAP_PLL0_DSMPD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll0_dsmpd` writer - u0_pll_wrap_pll0_dsmpd"] -pub type U0_PLL_WRAP_PLL0_DSMPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL0_DSMPD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - AHB master bus interface endianess: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] #[inline(always)] @@ -179,146 +174,148 @@ impl W { #[must_use] pub fn u0_sdio_m_hbig_endian( &mut self, - ) -> U0_SDIO_M_HBIG_ENDIAN_W { - U0_SDIO_M_HBIG_ENDIAN_W::new(self) + ) -> U0_SDIO_M_HBIG_ENDIAN_W { + U0_SDIO_M_HBIG_ENDIAN_W::new(self, 0) } #[doc = "Bit 1 - u0_i2srx_3ch_adc_ena"] #[inline(always)] #[must_use] - pub fn u0_i2srx_3ch_adc_ena( - &mut self, - ) -> U0_I2SRX_3CH_ADC_ENA_W { - U0_I2SRX_3CH_ADC_ENA_W::new(self) + pub fn u0_i2srx_3ch_adc_ena(&mut self) -> U0_I2SRX_3CH_ADC_ENA_W { + U0_I2SRX_3CH_ADC_ENA_W::new(self, 1) } #[doc = "Bit 2 - u0_intmem_rom_sram_scfg_disable_rom"] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_scfg_disable_rom( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SCFG_DISABLE_ROM_W { - U0_INTMEM_ROM_SRAM_SCFG_DISABLE_ROM_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SCFG_DISABLE_ROM_W { + U0_INTMEM_ROM_SRAM_SCFG_DISABLE_ROM_W::new(self, 2) } #[doc = "Bit 3 - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_sram_config_slp( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SLP_W { - U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SLP_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SLP_W { + U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SLP_W::new(self, 3) } #[doc = "Bit 4 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_sram_config_sram_config_sd( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W { - U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W { + U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self, 4) } #[doc = "Bits 5:6 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_sram_config_rtsel( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_RTSEL_W { - U0_INTMEM_ROM_SRAM_SRAM_CONFIG_RTSEL_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_RTSEL_W { + U0_INTMEM_ROM_SRAM_SRAM_CONFIG_RTSEL_W::new(self, 5) } #[doc = "Bits 7:8 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_sram_config_ptsel( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_PTSEL_W { - U0_INTMEM_ROM_SRAM_SRAM_CONFIG_PTSEL_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_PTSEL_W { + U0_INTMEM_ROM_SRAM_SRAM_CONFIG_PTSEL_W::new(self, 7) } #[doc = "Bits 9:10 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_sram_config_trb( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_TRB_W { - U0_INTMEM_ROM_SRAM_SRAM_CONFIG_TRB_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_TRB_W { + U0_INTMEM_ROM_SRAM_SRAM_CONFIG_TRB_W::new(self, 9) } #[doc = "Bits 11:12 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_sram_config_wtsel( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_WTSEL_W { - U0_INTMEM_ROM_SRAM_SRAM_CONFIG_WTSEL_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_WTSEL_W { + U0_INTMEM_ROM_SRAM_SRAM_CONFIG_WTSEL_W::new(self, 11) } #[doc = "Bit 13 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_sram_config_vs( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VS_W { - U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VS_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VS_W { + U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VS_W::new(self, 13) } #[doc = "Bit 14 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_sram_config_vg( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VG_W { - U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VG_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VG_W { + U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VG_W::new(self, 14) } #[doc = "Bit 15 - u0_jtag_daisy_chain_jtag_en_0"] #[inline(always)] #[must_use] pub fn u0_jtag_daisy_chain_jtag_en_0( &mut self, - ) -> U0_JTAG_DAISY_CHAIN_JTAG_EN_0_W { - U0_JTAG_DAISY_CHAIN_JTAG_EN_0_W::new(self) + ) -> U0_JTAG_DAISY_CHAIN_JTAG_EN_0_W { + U0_JTAG_DAISY_CHAIN_JTAG_EN_0_W::new(self, 15) } #[doc = "Bit 16 - u0_jtag_daisy_chain_jtag_en_1"] #[inline(always)] #[must_use] pub fn u0_jtag_daisy_chain_jtag_en_1( &mut self, - ) -> U0_JTAG_DAISY_CHAIN_JTAG_EN_1_W { - U0_JTAG_DAISY_CHAIN_JTAG_EN_1_W::new(self) + ) -> U0_JTAG_DAISY_CHAIN_JTAG_EN_1_W { + U0_JTAG_DAISY_CHAIN_JTAG_EN_1_W::new(self, 16) } #[doc = "Bit 17 - u0_pdrstn_split_sw_usbpipe_plugen"] #[inline(always)] #[must_use] pub fn u0_pdrstn_split_sw_usbpipe_plugen( &mut self, - ) -> U0_PDRSTN_SPLIT_SW_USBPIPE_PLUGEN_W { - U0_PDRSTN_SPLIT_SW_USBPIPE_PLUGEN_W::new(self) + ) -> U0_PDRSTN_SPLIT_SW_USBPIPE_PLUGEN_W { + U0_PDRSTN_SPLIT_SW_USBPIPE_PLUGEN_W::new(self, 17) } #[doc = "Bits 18:20 - u0_pll_wrap_pll0_cpi_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_cpi_bias( &mut self, - ) -> U0_PLL_WRAP_PLL0_CPI_BIAS_W { - U0_PLL_WRAP_PLL0_CPI_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL0_CPI_BIAS_W { + U0_PLL_WRAP_PLL0_CPI_BIAS_W::new(self, 18) } #[doc = "Bits 21:23 - u0_pll_wrap_pll0_cpp_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_cpp_bias( &mut self, - ) -> U0_PLL_WRAP_PLL0_CPP_BIAS_W { - U0_PLL_WRAP_PLL0_CPP_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL0_CPP_BIAS_W { + U0_PLL_WRAP_PLL0_CPP_BIAS_W::new(self, 21) } #[doc = "Bit 24 - u0_pll_wrap_pll0_dacpd"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_dacpd( &mut self, - ) -> U0_PLL_WRAP_PLL0_DACPD_W { - U0_PLL_WRAP_PLL0_DACPD_W::new(self) + ) -> U0_PLL_WRAP_PLL0_DACPD_W { + U0_PLL_WRAP_PLL0_DACPD_W::new(self, 24) } #[doc = "Bit 25 - u0_pll_wrap_pll0_dsmpd"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_dsmpd( &mut self, - ) -> U0_PLL_WRAP_PLL0_DSMPD_W { - U0_PLL_WRAP_PLL0_DSMPD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_PLL_WRAP_PLL0_DSMPD_W { + U0_PLL_WRAP_PLL0_DSMPD_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg28.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg28.rs index 8506aef..e1ca1b3 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg28.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg28.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_pll_wrap_pll0_fbdiv` reader - u0_pll_wrap_pll0_fbdiv"] pub type U0_PLL_WRAP_PLL0_FBDIV_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_fbdiv` writer - u0_pll_wrap_pll0_fbdiv"] -pub type U0_PLL_WRAP_PLL0_FBDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; +pub type U0_PLL_WRAP_PLL0_FBDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; impl R { #[doc = "Bits 0:11 - u0_pll_wrap_pll0_fbdiv"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn u0_pll_wrap_pll0_fbdiv( &mut self, - ) -> U0_PLL_WRAP_PLL0_FBDIV_W { - U0_PLL_WRAP_PLL0_FBDIV_W::new(self) + ) -> U0_PLL_WRAP_PLL0_FBDIV_W { + U0_PLL_WRAP_PLL0_FBDIV_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg32.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg32.rs index 016cbee..9866f9c 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg32.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg32.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `u0_pll_wrap_pll0_frac` reader - u0_pll_wrap_pll0_frac"] pub type U0_PLL_WRAP_PLL0_FRAC_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_frac` writer - u0_pll_wrap_pll0_frac"] -pub type U0_PLL_WRAP_PLL0_FRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type U0_PLL_WRAP_PLL0_FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `u0_pll_wrap_pll0_gvco_bias` reader - u0_pll_wrap_pll0_gvco_bias"] pub type U0_PLL_WRAP_PLL0_GVCO_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_gvco_bias` writer - u0_pll_wrap_pll0_gvco_bias"] -pub type U0_PLL_WRAP_PLL0_GVCO_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL0_GVCO_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_pll0_lock` reader - u0_pll_wrap_pll0_lock"] pub type U0_PLL_WRAP_PLL0_LOCK_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll0_pd` reader - u0_pll_wrap_pll0_pd"] pub type U0_PLL_WRAP_PLL0_PD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll0_pd` writer - u0_pll_wrap_pll0_pd"] -pub type U0_PLL_WRAP_PLL0_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL0_PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll0_postdiv1` reader - u0_pll_wrap_pll0_postdiv1"] pub type U0_PLL_WRAP_PLL0_POSTDIV1_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_postdiv1` writer - u0_pll_wrap_pll0_postdiv1"] -pub type U0_PLL_WRAP_PLL0_POSTDIV1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL0_POSTDIV1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_pll0_postdiv2` reader - u0_pll_wrap_pll0_postdiv2"] pub type U0_PLL_WRAP_PLL0_POSTDIV2_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_postdiv2` writer - u0_pll_wrap_pll0_postdiv2"] -pub type U0_PLL_WRAP_PLL0_POSTDIV2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL0_POSTDIV2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:23 - u0_pll_wrap_pll0_frac"] #[inline(always)] @@ -62,42 +62,44 @@ impl W { #[must_use] pub fn u0_pll_wrap_pll0_frac( &mut self, - ) -> U0_PLL_WRAP_PLL0_FRAC_W { - U0_PLL_WRAP_PLL0_FRAC_W::new(self) + ) -> U0_PLL_WRAP_PLL0_FRAC_W { + U0_PLL_WRAP_PLL0_FRAC_W::new(self, 0) } #[doc = "Bits 24:25 - u0_pll_wrap_pll0_gvco_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_gvco_bias( &mut self, - ) -> U0_PLL_WRAP_PLL0_GVCO_BIAS_W { - U0_PLL_WRAP_PLL0_GVCO_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL0_GVCO_BIAS_W { + U0_PLL_WRAP_PLL0_GVCO_BIAS_W::new(self, 24) } #[doc = "Bit 27 - u0_pll_wrap_pll0_pd"] #[inline(always)] #[must_use] - pub fn u0_pll_wrap_pll0_pd( - &mut self, - ) -> U0_PLL_WRAP_PLL0_PD_W { - U0_PLL_WRAP_PLL0_PD_W::new(self) + pub fn u0_pll_wrap_pll0_pd(&mut self) -> U0_PLL_WRAP_PLL0_PD_W { + U0_PLL_WRAP_PLL0_PD_W::new(self, 27) } #[doc = "Bits 28:29 - u0_pll_wrap_pll0_postdiv1"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_postdiv1( &mut self, - ) -> U0_PLL_WRAP_PLL0_POSTDIV1_W { - U0_PLL_WRAP_PLL0_POSTDIV1_W::new(self) + ) -> U0_PLL_WRAP_PLL0_POSTDIV1_W { + U0_PLL_WRAP_PLL0_POSTDIV1_W::new(self, 28) } #[doc = "Bits 30:31 - u0_pll_wrap_pll0_postdiv2"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_postdiv2( &mut self, - ) -> U0_PLL_WRAP_PLL0_POSTDIV2_W { - U0_PLL_WRAP_PLL0_POSTDIV2_W::new(self) + ) -> U0_PLL_WRAP_PLL0_POSTDIV2_W { + U0_PLL_WRAP_PLL0_POSTDIV2_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg36.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg36.rs index 0cafa85..3a46591 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg36.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg36.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `u0_pll_wrap_pll0_prediv` reader - u0_pll_wrap_pll0_prediv"] pub type U0_PLL_WRAP_PLL0_PREDIV_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_prediv` writer - u0_pll_wrap_pll0_prediv"] -pub type U0_PLL_WRAP_PLL0_PREDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type U0_PLL_WRAP_PLL0_PREDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `u0_pll_wrap_pll0_testen` reader - u0_pll_wrap_pll0_testen"] pub type U0_PLL_WRAP_PLL0_TESTEN_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll0_testen` writer - u0_pll_wrap_pll0_testen"] -pub type U0_PLL_WRAP_PLL0_TESTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL0_TESTEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll0_testsel` reader - u0_pll_wrap_pll0_testsel"] pub type U0_PLL_WRAP_PLL0_TESTSEL_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_testsel` writer - u0_pll_wrap_pll0_testsel"] -pub type U0_PLL_WRAP_PLL0_TESTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL0_TESTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_pll1_cpi_bias` reader - u0_pll_wrap_pll1_cpi_bias"] pub type U0_PLL_WRAP_PLL1_CPI_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_cpi_bias` writer - u0_pll_wrap_pll1_cpi_bias"] -pub type U0_PLL_WRAP_PLL1_CPI_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U0_PLL_WRAP_PLL1_CPI_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_pll_wrap_pll1_cpp_bias` reader - u0_pll_wrap_pll1_cpp_bias"] pub type U0_PLL_WRAP_PLL1_CPP_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_cpp_bias` writer - u0_pll_wrap_pll1_cpp_bias"] -pub type U0_PLL_WRAP_PLL1_CPP_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U0_PLL_WRAP_PLL1_CPP_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_pll_wrap_pll1_dacpd` reader - u0_pll_wrap_pll1_dacpd"] pub type U0_PLL_WRAP_PLL1_DACPD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll1_dacpd` writer - u0_pll_wrap_pll1_dacpd"] -pub type U0_PLL_WRAP_PLL1_DACPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL1_DACPD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll1_dsmpd` reader - u0_pll_wrap_pll1_dsmpd"] pub type U0_PLL_WRAP_PLL1_DSMPD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll1_dsmpd` writer - u0_pll_wrap_pll1_dsmpd"] -pub type U0_PLL_WRAP_PLL1_DSMPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL1_DSMPD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll1_fbdiv` reader - u0_pll_wrap_pll1_fbdiv"] pub type U0_PLL_WRAP_PLL1_FBDIV_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_fbdiv` writer - u0_pll_wrap_pll1_fbdiv"] -pub type U0_PLL_WRAP_PLL1_FBDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; +pub type U0_PLL_WRAP_PLL1_FBDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; impl R { #[doc = "Bits 0:5 - u0_pll_wrap_pll0_prediv"] #[inline(always)] @@ -82,66 +82,70 @@ impl W { #[must_use] pub fn u0_pll_wrap_pll0_prediv( &mut self, - ) -> U0_PLL_WRAP_PLL0_PREDIV_W { - U0_PLL_WRAP_PLL0_PREDIV_W::new(self) + ) -> U0_PLL_WRAP_PLL0_PREDIV_W { + U0_PLL_WRAP_PLL0_PREDIV_W::new(self, 0) } #[doc = "Bit 6 - u0_pll_wrap_pll0_testen"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_testen( &mut self, - ) -> U0_PLL_WRAP_PLL0_TESTEN_W { - U0_PLL_WRAP_PLL0_TESTEN_W::new(self) + ) -> U0_PLL_WRAP_PLL0_TESTEN_W { + U0_PLL_WRAP_PLL0_TESTEN_W::new(self, 6) } #[doc = "Bits 7:8 - u0_pll_wrap_pll0_testsel"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_testsel( &mut self, - ) -> U0_PLL_WRAP_PLL0_TESTSEL_W { - U0_PLL_WRAP_PLL0_TESTSEL_W::new(self) + ) -> U0_PLL_WRAP_PLL0_TESTSEL_W { + U0_PLL_WRAP_PLL0_TESTSEL_W::new(self, 7) } #[doc = "Bits 9:11 - u0_pll_wrap_pll1_cpi_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_cpi_bias( &mut self, - ) -> U0_PLL_WRAP_PLL1_CPI_BIAS_W { - U0_PLL_WRAP_PLL1_CPI_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL1_CPI_BIAS_W { + U0_PLL_WRAP_PLL1_CPI_BIAS_W::new(self, 9) } #[doc = "Bits 12:14 - u0_pll_wrap_pll1_cpp_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_cpp_bias( &mut self, - ) -> U0_PLL_WRAP_PLL1_CPP_BIAS_W { - U0_PLL_WRAP_PLL1_CPP_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL1_CPP_BIAS_W { + U0_PLL_WRAP_PLL1_CPP_BIAS_W::new(self, 12) } #[doc = "Bit 15 - u0_pll_wrap_pll1_dacpd"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_dacpd( &mut self, - ) -> U0_PLL_WRAP_PLL1_DACPD_W { - U0_PLL_WRAP_PLL1_DACPD_W::new(self) + ) -> U0_PLL_WRAP_PLL1_DACPD_W { + U0_PLL_WRAP_PLL1_DACPD_W::new(self, 15) } #[doc = "Bit 16 - u0_pll_wrap_pll1_dsmpd"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_dsmpd( &mut self, - ) -> U0_PLL_WRAP_PLL1_DSMPD_W { - U0_PLL_WRAP_PLL1_DSMPD_W::new(self) + ) -> U0_PLL_WRAP_PLL1_DSMPD_W { + U0_PLL_WRAP_PLL1_DSMPD_W::new(self, 16) } #[doc = "Bits 17:28 - u0_pll_wrap_pll1_fbdiv"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_fbdiv( &mut self, - ) -> U0_PLL_WRAP_PLL1_FBDIV_W { - U0_PLL_WRAP_PLL1_FBDIV_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_PLL_WRAP_PLL1_FBDIV_W { + U0_PLL_WRAP_PLL1_FBDIV_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg4.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg4.rs index ec469be..6b0c18f 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg4.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg4.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `scfg_sd1_remap_awaddr` reader - scfg_sd1_remap_awaddr"] pub type SCFG_SD1_REMAP_AWADDR_R = crate::FieldReader; #[doc = "Field `scfg_sd1_remap_awaddr` writer - scfg_sd1_remap_awaddr"] -pub type SCFG_SD1_REMAP_AWADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_SD1_REMAP_AWADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_sec_haddr_remap` reader - scfg_sec_haddr_remap"] pub type SCFG_SEC_HADDR_REMAP_R = crate::FieldReader; #[doc = "Field `scfg_sec_haddr_remap` writer - scfg_sec_haddr_remap"] -pub type SCFG_SEC_HADDR_REMAP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_SEC_HADDR_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_usb_araddr_remap` reader - scfg_usb_araddr_remap"] pub type SCFG_USB_ARADDR_REMAP_R = crate::FieldReader; #[doc = "Field `scfg_usb_araddr_remap` writer - scfg_usb_araddr_remap"] -pub type SCFG_USB_ARADDR_REMAP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_USB_ARADDR_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_usb_awaddr_remap` reader - scfg_usb_awaddr_remap"] pub type SCFG_USB_AWADDR_REMAP_R = crate::FieldReader; #[doc = "Field `scfg_usb_awaddr_remap` writer - scfg_usb_awaddr_remap"] -pub type SCFG_USB_AWADDR_REMAP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_USB_AWADDR_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_vdec_remap_awaddr` reader - scfg_vdec_remap_awaddr"] pub type SCFG_VDEC_REMAP_AWADDR_R = crate::FieldReader; #[doc = "Field `scfg_vdec_remap_awaddr` writer - scfg_vdec_remap_awaddr"] -pub type SCFG_VDEC_REMAP_AWADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_VDEC_REMAP_AWADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_venc_remap_araddr` reader - scfg_venc_remap_araddr"] pub type SCFG_VENC_REMAP_ARADDR_R = crate::FieldReader; #[doc = "Field `scfg_venc_remap_araddr` writer - scfg_venc_remap_araddr"] -pub type SCFG_VENC_REMAP_ARADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_VENC_REMAP_ARADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_venc_remap_awaddr` reader - scfg_venc_remap_awaddr"] pub type SCFG_VENC_REMAP_AWADDR_R = crate::FieldReader; #[doc = "Field `scfg_venc_remap_awaddr` writer - scfg_venc_remap_awaddr"] -pub type SCFG_VENC_REMAP_AWADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_VENC_REMAP_AWADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_vout0_remap_araddr` reader - scfg_vout0_remap_araddr"] pub type SCFG_VOUT0_REMAP_ARADDR_R = crate::FieldReader; #[doc = "Field `scfg_vout0_remap_araddr` writer - scfg_vout0_remap_araddr"] -pub type SCFG_VOUT0_REMAP_ARADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_VOUT0_REMAP_ARADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - scfg_sd1_remap_awaddr"] #[inline(always)] @@ -82,66 +82,68 @@ impl W { #[must_use] pub fn scfg_sd1_remap_awaddr( &mut self, - ) -> SCFG_SD1_REMAP_AWADDR_W { - SCFG_SD1_REMAP_AWADDR_W::new(self) + ) -> SCFG_SD1_REMAP_AWADDR_W { + SCFG_SD1_REMAP_AWADDR_W::new(self, 0) } #[doc = "Bits 4:7 - scfg_sec_haddr_remap"] #[inline(always)] #[must_use] - pub fn scfg_sec_haddr_remap( - &mut self, - ) -> SCFG_SEC_HADDR_REMAP_W { - SCFG_SEC_HADDR_REMAP_W::new(self) + pub fn scfg_sec_haddr_remap(&mut self) -> SCFG_SEC_HADDR_REMAP_W { + SCFG_SEC_HADDR_REMAP_W::new(self, 4) } #[doc = "Bits 8:11 - scfg_usb_araddr_remap"] #[inline(always)] #[must_use] pub fn scfg_usb_araddr_remap( &mut self, - ) -> SCFG_USB_ARADDR_REMAP_W { - SCFG_USB_ARADDR_REMAP_W::new(self) + ) -> SCFG_USB_ARADDR_REMAP_W { + SCFG_USB_ARADDR_REMAP_W::new(self, 8) } #[doc = "Bits 12:15 - scfg_usb_awaddr_remap"] #[inline(always)] #[must_use] pub fn scfg_usb_awaddr_remap( &mut self, - ) -> SCFG_USB_AWADDR_REMAP_W { - SCFG_USB_AWADDR_REMAP_W::new(self) + ) -> SCFG_USB_AWADDR_REMAP_W { + SCFG_USB_AWADDR_REMAP_W::new(self, 12) } #[doc = "Bits 16:19 - scfg_vdec_remap_awaddr"] #[inline(always)] #[must_use] pub fn scfg_vdec_remap_awaddr( &mut self, - ) -> SCFG_VDEC_REMAP_AWADDR_W { - SCFG_VDEC_REMAP_AWADDR_W::new(self) + ) -> SCFG_VDEC_REMAP_AWADDR_W { + SCFG_VDEC_REMAP_AWADDR_W::new(self, 16) } #[doc = "Bits 20:23 - scfg_venc_remap_araddr"] #[inline(always)] #[must_use] pub fn scfg_venc_remap_araddr( &mut self, - ) -> SCFG_VENC_REMAP_ARADDR_W { - SCFG_VENC_REMAP_ARADDR_W::new(self) + ) -> SCFG_VENC_REMAP_ARADDR_W { + SCFG_VENC_REMAP_ARADDR_W::new(self, 20) } #[doc = "Bits 24:27 - scfg_venc_remap_awaddr"] #[inline(always)] #[must_use] pub fn scfg_venc_remap_awaddr( &mut self, - ) -> SCFG_VENC_REMAP_AWADDR_W { - SCFG_VENC_REMAP_AWADDR_W::new(self) + ) -> SCFG_VENC_REMAP_AWADDR_W { + SCFG_VENC_REMAP_AWADDR_W::new(self, 24) } #[doc = "Bits 28:31 - scfg_vout0_remap_araddr"] #[inline(always)] #[must_use] pub fn scfg_vout0_remap_araddr( &mut self, - ) -> SCFG_VOUT0_REMAP_ARADDR_W { - SCFG_VOUT0_REMAP_ARADDR_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> SCFG_VOUT0_REMAP_ARADDR_W { + SCFG_VOUT0_REMAP_ARADDR_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg40.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg40.rs index 94aa69a..d8a16eb 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg40.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg40.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `u0_pll_wrap_pll1_frac` reader - u0_pll_wrap_pll1_frac"] pub type U0_PLL_WRAP_PLL1_FRAC_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_frac` writer - u0_pll_wrap_pll1_frac"] -pub type U0_PLL_WRAP_PLL1_FRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type U0_PLL_WRAP_PLL1_FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `u0_pll_wrap_pll1_gvco_bias` reader - u0_pll_wrap_pll1_gvco_bias"] pub type U0_PLL_WRAP_PLL1_GVCO_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_gvco_bias` writer - u0_pll_wrap_pll1_gvco_bias"] -pub type U0_PLL_WRAP_PLL1_GVCO_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL1_GVCO_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_pll1_lock` reader - u0_pll_wrap_pll1_lock"] pub type U0_PLL_WRAP_PLL1_LOCK_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll1_pd` reader - u0_pll_wrap_pll1_pd"] pub type U0_PLL_WRAP_PLL1_PD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll1_pd` writer - u0_pll_wrap_pll1_pd"] -pub type U0_PLL_WRAP_PLL1_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL1_PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll1_postdiv1` reader - u0_pll_wrap_pll1_postdiv1"] pub type U0_PLL_WRAP_PLL1_POSTDIV1_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_postdiv1` writer - u0_pll_wrap_pll1_postdiv1"] -pub type U0_PLL_WRAP_PLL1_POSTDIV1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL1_POSTDIV1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_pll1_postdiv2` reader - u0_pll_wrap_pll1_postdiv2"] pub type U0_PLL_WRAP_PLL1_POSTDIV2_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_postdiv2` writer - u0_pll_wrap_pll1_postdiv2"] -pub type U0_PLL_WRAP_PLL1_POSTDIV2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL1_POSTDIV2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:23 - u0_pll_wrap_pll1_frac"] #[inline(always)] @@ -62,42 +62,44 @@ impl W { #[must_use] pub fn u0_pll_wrap_pll1_frac( &mut self, - ) -> U0_PLL_WRAP_PLL1_FRAC_W { - U0_PLL_WRAP_PLL1_FRAC_W::new(self) + ) -> U0_PLL_WRAP_PLL1_FRAC_W { + U0_PLL_WRAP_PLL1_FRAC_W::new(self, 0) } #[doc = "Bits 24:25 - u0_pll_wrap_pll1_gvco_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_gvco_bias( &mut self, - ) -> U0_PLL_WRAP_PLL1_GVCO_BIAS_W { - U0_PLL_WRAP_PLL1_GVCO_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL1_GVCO_BIAS_W { + U0_PLL_WRAP_PLL1_GVCO_BIAS_W::new(self, 24) } #[doc = "Bit 27 - u0_pll_wrap_pll1_pd"] #[inline(always)] #[must_use] - pub fn u0_pll_wrap_pll1_pd( - &mut self, - ) -> U0_PLL_WRAP_PLL1_PD_W { - U0_PLL_WRAP_PLL1_PD_W::new(self) + pub fn u0_pll_wrap_pll1_pd(&mut self) -> U0_PLL_WRAP_PLL1_PD_W { + U0_PLL_WRAP_PLL1_PD_W::new(self, 27) } #[doc = "Bits 28:29 - u0_pll_wrap_pll1_postdiv1"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_postdiv1( &mut self, - ) -> U0_PLL_WRAP_PLL1_POSTDIV1_W { - U0_PLL_WRAP_PLL1_POSTDIV1_W::new(self) + ) -> U0_PLL_WRAP_PLL1_POSTDIV1_W { + U0_PLL_WRAP_PLL1_POSTDIV1_W::new(self, 28) } #[doc = "Bits 30:31 - u0_pll_wrap_pll1_postdiv2"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_postdiv2( &mut self, - ) -> U0_PLL_WRAP_PLL1_POSTDIV2_W { - U0_PLL_WRAP_PLL1_POSTDIV2_W::new(self) + ) -> U0_PLL_WRAP_PLL1_POSTDIV2_W { + U0_PLL_WRAP_PLL1_POSTDIV2_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg44.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg44.rs index fec59da..b921ff3 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg44.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg44.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `u0_pll_wrap_pll1_prediv` reader - u0_pll_wrap_pll1_prediv"] pub type U0_PLL_WRAP_PLL1_PREDIV_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_prediv` writer - u0_pll_wrap_pll1_prediv"] -pub type U0_PLL_WRAP_PLL1_PREDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type U0_PLL_WRAP_PLL1_PREDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `u0_pll_wrap_pll1_testen` reader - u0_pll_wrap_pll1_testen"] pub type U0_PLL_WRAP_PLL1_TESTEN_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll1_testen` writer - u0_pll_wrap_pll1_testen"] -pub type U0_PLL_WRAP_PLL1_TESTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL1_TESTEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll1_testsel` reader - u0_pll_wrap_pll1_testsel"] pub type U0_PLL_WRAP_PLL1_TESTSEL_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_testsel` writer - u0_pll_wrap_pll1_testsel"] -pub type U0_PLL_WRAP_PLL1_TESTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL1_TESTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_pll2_cpi_bias` reader - u0_pll_wrap_pll2_cpi_bias"] pub type U0_PLL_WRAP_PLL2_CPI_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_cpi_bias` writer - u0_pll_wrap_pll2_cpi_bias"] -pub type U0_PLL_WRAP_PLL2_CPI_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U0_PLL_WRAP_PLL2_CPI_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_pll_wrap_pll2_cpp_bias` reader - u0_pll_wrap_pll2_cpp_bias"] pub type U0_PLL_WRAP_PLL2_CPP_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_cpp_bias` writer - u0_pll_wrap_pll2_cpp_bias"] -pub type U0_PLL_WRAP_PLL2_CPP_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U0_PLL_WRAP_PLL2_CPP_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_pll_wrap_pll2_dacpd` reader - u0_pll_wrap_pll2_dacpd"] pub type U0_PLL_WRAP_PLL2_DACPD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll2_dacpd` writer - u0_pll_wrap_pll2_dacpd"] -pub type U0_PLL_WRAP_PLL2_DACPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL2_DACPD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll2_dsmpd` reader - u0_pll_wrap_pll2_dsmpd"] pub type U0_PLL_WRAP_PLL2_DSMPD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll2_dsmpd` writer - u0_pll_wrap_pll2_dsmpd"] -pub type U0_PLL_WRAP_PLL2_DSMPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL2_DSMPD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll2_fbdiv` reader - u0_pll_wrap_pll2_fbdiv"] pub type U0_PLL_WRAP_PLL2_FBDIV_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_fbdiv` writer - u0_pll_wrap_pll2_fbdiv"] -pub type U0_PLL_WRAP_PLL2_FBDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; +pub type U0_PLL_WRAP_PLL2_FBDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; impl R { #[doc = "Bits 0:5 - u0_pll_wrap_pll1_prediv"] #[inline(always)] @@ -82,66 +82,70 @@ impl W { #[must_use] pub fn u0_pll_wrap_pll1_prediv( &mut self, - ) -> U0_PLL_WRAP_PLL1_PREDIV_W { - U0_PLL_WRAP_PLL1_PREDIV_W::new(self) + ) -> U0_PLL_WRAP_PLL1_PREDIV_W { + U0_PLL_WRAP_PLL1_PREDIV_W::new(self, 0) } #[doc = "Bit 6 - u0_pll_wrap_pll1_testen"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_testen( &mut self, - ) -> U0_PLL_WRAP_PLL1_TESTEN_W { - U0_PLL_WRAP_PLL1_TESTEN_W::new(self) + ) -> U0_PLL_WRAP_PLL1_TESTEN_W { + U0_PLL_WRAP_PLL1_TESTEN_W::new(self, 6) } #[doc = "Bits 7:8 - u0_pll_wrap_pll1_testsel"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_testsel( &mut self, - ) -> U0_PLL_WRAP_PLL1_TESTSEL_W { - U0_PLL_WRAP_PLL1_TESTSEL_W::new(self) + ) -> U0_PLL_WRAP_PLL1_TESTSEL_W { + U0_PLL_WRAP_PLL1_TESTSEL_W::new(self, 7) } #[doc = "Bits 9:11 - u0_pll_wrap_pll2_cpi_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_cpi_bias( &mut self, - ) -> U0_PLL_WRAP_PLL2_CPI_BIAS_W { - U0_PLL_WRAP_PLL2_CPI_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL2_CPI_BIAS_W { + U0_PLL_WRAP_PLL2_CPI_BIAS_W::new(self, 9) } #[doc = "Bits 12:14 - u0_pll_wrap_pll2_cpp_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_cpp_bias( &mut self, - ) -> U0_PLL_WRAP_PLL2_CPP_BIAS_W { - U0_PLL_WRAP_PLL2_CPP_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL2_CPP_BIAS_W { + U0_PLL_WRAP_PLL2_CPP_BIAS_W::new(self, 12) } #[doc = "Bit 15 - u0_pll_wrap_pll2_dacpd"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_dacpd( &mut self, - ) -> U0_PLL_WRAP_PLL2_DACPD_W { - U0_PLL_WRAP_PLL2_DACPD_W::new(self) + ) -> U0_PLL_WRAP_PLL2_DACPD_W { + U0_PLL_WRAP_PLL2_DACPD_W::new(self, 15) } #[doc = "Bit 16 - u0_pll_wrap_pll2_dsmpd"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_dsmpd( &mut self, - ) -> U0_PLL_WRAP_PLL2_DSMPD_W { - U0_PLL_WRAP_PLL2_DSMPD_W::new(self) + ) -> U0_PLL_WRAP_PLL2_DSMPD_W { + U0_PLL_WRAP_PLL2_DSMPD_W::new(self, 16) } #[doc = "Bits 17:28 - u0_pll_wrap_pll2_fbdiv"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_fbdiv( &mut self, - ) -> U0_PLL_WRAP_PLL2_FBDIV_W { - U0_PLL_WRAP_PLL2_FBDIV_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_PLL_WRAP_PLL2_FBDIV_W { + U0_PLL_WRAP_PLL2_FBDIV_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg48.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg48.rs index afbc5f1..5f098de 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg48.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg48.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `u0_pll_wrap_pll2_frac` reader - u0_pll_wrap_pll2_frac"] pub type U0_PLL_WRAP_PLL2_FRAC_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_frac` writer - u0_pll_wrap_pll2_frac"] -pub type U0_PLL_WRAP_PLL2_FRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type U0_PLL_WRAP_PLL2_FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `u0_pll_wrap_pll2_gvco_bias` reader - u0_pll_wrap_pll2_gvco_bias"] pub type U0_PLL_WRAP_PLL2_GVCO_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_gvco_bias` writer - u0_pll_wrap_pll2_gvco_bias"] -pub type U0_PLL_WRAP_PLL2_GVCO_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL2_GVCO_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_pll2_lock` reader - u0_pll_wrap_pll2_lock"] pub type U0_PLL_WRAP_PLL2_LOCK_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll2_pd` reader - u0_pll_wrap_pll2_pd"] pub type U0_PLL_WRAP_PLL2_PD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll2_pd` writer - u0_pll_wrap_pll2_pd"] -pub type U0_PLL_WRAP_PLL2_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL2_PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll2_postdiv1` reader - u0_pll_wrap_pll2_postdiv1"] pub type U0_PLL_WRAP_PLL2_POSTDIV1_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_postdiv1` writer - u0_pll_wrap_pll2_postdiv1"] -pub type U0_PLL_WRAP_PLL2_POSTDIV1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL2_POSTDIV1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_pll2_postdiv2` reader - u0_pll_wrap_pll2_postdiv2"] pub type U0_PLL_WRAP_PLL2_POSTDIV2_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_postdiv2` writer - u0_pll_wrap_pll2_postdiv2"] -pub type U0_PLL_WRAP_PLL2_POSTDIV2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL2_POSTDIV2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:23 - u0_pll_wrap_pll2_frac"] #[inline(always)] @@ -62,42 +62,44 @@ impl W { #[must_use] pub fn u0_pll_wrap_pll2_frac( &mut self, - ) -> U0_PLL_WRAP_PLL2_FRAC_W { - U0_PLL_WRAP_PLL2_FRAC_W::new(self) + ) -> U0_PLL_WRAP_PLL2_FRAC_W { + U0_PLL_WRAP_PLL2_FRAC_W::new(self, 0) } #[doc = "Bits 24:25 - u0_pll_wrap_pll2_gvco_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_gvco_bias( &mut self, - ) -> U0_PLL_WRAP_PLL2_GVCO_BIAS_W { - U0_PLL_WRAP_PLL2_GVCO_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL2_GVCO_BIAS_W { + U0_PLL_WRAP_PLL2_GVCO_BIAS_W::new(self, 24) } #[doc = "Bit 27 - u0_pll_wrap_pll2_pd"] #[inline(always)] #[must_use] - pub fn u0_pll_wrap_pll2_pd( - &mut self, - ) -> U0_PLL_WRAP_PLL2_PD_W { - U0_PLL_WRAP_PLL2_PD_W::new(self) + pub fn u0_pll_wrap_pll2_pd(&mut self) -> U0_PLL_WRAP_PLL2_PD_W { + U0_PLL_WRAP_PLL2_PD_W::new(self, 27) } #[doc = "Bits 28:29 - u0_pll_wrap_pll2_postdiv1"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_postdiv1( &mut self, - ) -> U0_PLL_WRAP_PLL2_POSTDIV1_W { - U0_PLL_WRAP_PLL2_POSTDIV1_W::new(self) + ) -> U0_PLL_WRAP_PLL2_POSTDIV1_W { + U0_PLL_WRAP_PLL2_POSTDIV1_W::new(self, 28) } #[doc = "Bits 30:31 - u0_pll_wrap_pll2_postdiv2"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_postdiv2( &mut self, - ) -> U0_PLL_WRAP_PLL2_POSTDIV2_W { - U0_PLL_WRAP_PLL2_POSTDIV2_W::new(self) + ) -> U0_PLL_WRAP_PLL2_POSTDIV2_W { + U0_PLL_WRAP_PLL2_POSTDIV2_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg52.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg52.rs index ed93b66..a542c31 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg52.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg52.rs @@ -5,75 +5,67 @@ pub type W = crate::W; #[doc = "Field `u0_pll_wrap_pll2_prediv` reader - u0_pll_wrap_pll2_prediv"] pub type U0_PLL_WRAP_PLL2_PREDIV_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_prediv` writer - u0_pll_wrap_pll2_prediv"] -pub type U0_PLL_WRAP_PLL2_PREDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type U0_PLL_WRAP_PLL2_PREDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `u0_pll_wrap_pll2_testen` reader - u0_pll_wrap_pll2_testen"] pub type U0_PLL_WRAP_PLL2_TESTEN_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll2_testen` writer - u0_pll_wrap_pll2_testen"] -pub type U0_PLL_WRAP_PLL2_TESTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL2_TESTEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll2_testsel` reader - u0_pll_wrap_pll2_testsel"] pub type U0_PLL_WRAP_PLL2_TESTSEL_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_testsel` writer - u0_pll_wrap_pll2_testsel"] -pub type U0_PLL_WRAP_PLL2_TESTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL2_TESTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_syscfg_test_pll_mode` reader - PLL test mode, only used for PLL BIST through jtag2apb"] pub type U0_PLL_WRAP_SYSCFG_TEST_PLL_MODE_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_syscfg_test_pll_mode` writer - PLL test mode, only used for PLL BIST through jtag2apb"] -pub type U0_PLL_WRAP_SYSCFG_TEST_PLL_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_SYSCFG_TEST_PLL_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_saif_audio_sdin_mux_scfg_i2sdin_sel` reader - u0_saif_audio_sdin_mux_scfg_i2sdin_sel"] pub type U0_SAIF_AUDIO_SDIN_MUX_SCFG_I2SDIN_SEL_R = crate::FieldReader; #[doc = "Field `u0_saif_audio_sdin_mux_scfg_i2sdin_sel` writer - u0_saif_audio_sdin_mux_scfg_i2sdin_sel"] -pub type U0_SAIF_AUDIO_SDIN_MUX_SCFG_I2SDIN_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 8, O>; +pub type U0_SAIF_AUDIO_SDIN_MUX_SCFG_I2SDIN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `u0_sft7110_noc_bus_clock_gating_off` reader - u0_sft7110_noc_bus_clock_gating_off"] pub type U0_SFT7110_NOC_BUS_CLOCK_GATING_OFF_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_clock_gating_off` writer - u0_sft7110_noc_bus_clock_gating_off"] -pub type U0_SFT7110_NOC_BUS_CLOCK_GATING_OFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_CLOCK_GATING_OFF_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_0_start` reader - u0_sft7110_noc_bus_oic_evemon_0_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_0_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_0_start` writer - u0_sft7110_noc_bus_oic_evemon_0_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_0_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_0_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_0_trigger` reader - u0_sft7110_noc_bus_oic_evemon_0_trigger"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_0_TRIGGER_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_1_start` reader - u0_sft7110_noc_bus_oic_evemon_1_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_1_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_1_start` writer - u0_sft7110_noc_bus_oic_evemon_1_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_1_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_1_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_1_trigger` reader - u0_sft7110_noc_bus_oic_evemon_1_trigger"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_1_TRIGGER_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_2_start` reader - u0_sft7110_noc_bus_oic_evemon_2_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_2_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_2_start` writer - u0_sft7110_noc_bus_oic_evemon_2_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_2_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_2_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_2_trigger` reader - u0_sft7110_noc_bus_oic_evemon_2_trigger"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_2_TRIGGER_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_3_start` reader - u0_sft7110_noc_bus_oic_evemon_3_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_3_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_3_start` writer - u0_sft7110_noc_bus_oic_evemon_3_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_3_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_3_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_3_trigger` reader - u0_sft7110_noc_bus_oic_evemon_3_trigger"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_3_TRIGGER_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_4_start` reader - u0_sft7110_noc_bus_oic_evemon_4_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_4_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_4_start` writer - u0_sft7110_noc_bus_oic_evemon_4_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_4_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_4_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_4_trigger` reader - u0_sft7110_noc_bus_oic_evemon_4_trigger"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_4_TRIGGER_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_5_start` reader - u0_sft7110_noc_bus_oic_evemon_5_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_5_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_5_start` writer - u0_sft7110_noc_bus_oic_evemon_5_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_5_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_5_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_5_trigger` reader - u0_sft7110_noc_bus_oic_evemon_5_trigger"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_5_TRIGGER_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_6_start` reader - u0_sft7110_noc_bus_oic_evemon_6_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_6_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_6_start` writer - u0_sft7110_noc_bus_oic_evemon_6_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_6_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_6_START_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:5 - u0_pll_wrap_pll2_prediv"] #[inline(always)] @@ -191,106 +183,110 @@ impl W { #[must_use] pub fn u0_pll_wrap_pll2_prediv( &mut self, - ) -> U0_PLL_WRAP_PLL2_PREDIV_W { - U0_PLL_WRAP_PLL2_PREDIV_W::new(self) + ) -> U0_PLL_WRAP_PLL2_PREDIV_W { + U0_PLL_WRAP_PLL2_PREDIV_W::new(self, 0) } #[doc = "Bit 6 - u0_pll_wrap_pll2_testen"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_testen( &mut self, - ) -> U0_PLL_WRAP_PLL2_TESTEN_W { - U0_PLL_WRAP_PLL2_TESTEN_W::new(self) + ) -> U0_PLL_WRAP_PLL2_TESTEN_W { + U0_PLL_WRAP_PLL2_TESTEN_W::new(self, 6) } #[doc = "Bits 7:8 - u0_pll_wrap_pll2_testsel"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_testsel( &mut self, - ) -> U0_PLL_WRAP_PLL2_TESTSEL_W { - U0_PLL_WRAP_PLL2_TESTSEL_W::new(self) + ) -> U0_PLL_WRAP_PLL2_TESTSEL_W { + U0_PLL_WRAP_PLL2_TESTSEL_W::new(self, 7) } #[doc = "Bit 9 - PLL test mode, only used for PLL BIST through jtag2apb"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_syscfg_test_pll_mode( &mut self, - ) -> U0_PLL_WRAP_SYSCFG_TEST_PLL_MODE_W { - U0_PLL_WRAP_SYSCFG_TEST_PLL_MODE_W::new(self) + ) -> U0_PLL_WRAP_SYSCFG_TEST_PLL_MODE_W { + U0_PLL_WRAP_SYSCFG_TEST_PLL_MODE_W::new(self, 9) } #[doc = "Bits 10:17 - u0_saif_audio_sdin_mux_scfg_i2sdin_sel"] #[inline(always)] #[must_use] pub fn u0_saif_audio_sdin_mux_scfg_i2sdin_sel( &mut self, - ) -> U0_SAIF_AUDIO_SDIN_MUX_SCFG_I2SDIN_SEL_W { - U0_SAIF_AUDIO_SDIN_MUX_SCFG_I2SDIN_SEL_W::new(self) + ) -> U0_SAIF_AUDIO_SDIN_MUX_SCFG_I2SDIN_SEL_W { + U0_SAIF_AUDIO_SDIN_MUX_SCFG_I2SDIN_SEL_W::new(self, 10) } #[doc = "Bit 18 - u0_sft7110_noc_bus_clock_gating_off"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_clock_gating_off( &mut self, - ) -> U0_SFT7110_NOC_BUS_CLOCK_GATING_OFF_W { - U0_SFT7110_NOC_BUS_CLOCK_GATING_OFF_W::new(self) + ) -> U0_SFT7110_NOC_BUS_CLOCK_GATING_OFF_W { + U0_SFT7110_NOC_BUS_CLOCK_GATING_OFF_W::new(self, 18) } #[doc = "Bit 19 - u0_sft7110_noc_bus_oic_evemon_0_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_0_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_0_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_0_START_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_0_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_0_START_W::new(self, 19) } #[doc = "Bit 21 - u0_sft7110_noc_bus_oic_evemon_1_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_1_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_1_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_1_START_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_1_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_1_START_W::new(self, 21) } #[doc = "Bit 23 - u0_sft7110_noc_bus_oic_evemon_2_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_2_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_2_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_2_START_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_2_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_2_START_W::new(self, 23) } #[doc = "Bit 25 - u0_sft7110_noc_bus_oic_evemon_3_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_3_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_3_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_3_START_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_3_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_3_START_W::new(self, 25) } #[doc = "Bit 27 - u0_sft7110_noc_bus_oic_evemon_4_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_4_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_4_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_4_START_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_4_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_4_START_W::new(self, 27) } #[doc = "Bit 29 - u0_sft7110_noc_bus_oic_evemon_5_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_5_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_5_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_5_START_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_5_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_5_START_W::new(self, 29) } #[doc = "Bit 31 - u0_sft7110_noc_bus_oic_evemon_6_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_6_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_6_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_6_START_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_6_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_6_START_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg56.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg56.rs index a1ceebe..f637eb8 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg56.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg56.rs @@ -7,40 +7,33 @@ pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_6_TRIGGER_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_0` reader - u0_sft7110_noc_bus_oic_ignore_modifiable_0"] pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_0_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_0` writer - u0_sft7110_noc_bus_oic_ignore_modifiable_0"] -pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_0_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_1` reader - u0_sft7110_noc_bus_oic_ignore_modifiable_1"] pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_1_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_1` writer - u0_sft7110_noc_bus_oic_ignore_modifiable_1"] -pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_1_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_2` reader - u0_sft7110_noc_bus_oic_ignore_modifiable_2"] pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_2_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_2` writer - u0_sft7110_noc_bus_oic_ignore_modifiable_2"] -pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_2_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_3` reader - u0_sft7110_noc_bus_oic_ignore_modifiable_3"] pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_3_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_3` writer - u0_sft7110_noc_bus_oic_ignore_modifiable_3"] -pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_3_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_3_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_4` reader - u0_sft7110_noc_bus_oic_ignore_modifiable_4"] pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_4_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_4` writer - u0_sft7110_noc_bus_oic_ignore_modifiable_4"] -pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_4_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_4_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_7_start` reader - u0_sft7110_noc_bus_oic_evemon_7_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_7_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_7_start` writer - u0_sft7110_noc_bus_oic_evemon_7_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_7_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_7_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_7_trigger` reader - u0_sft7110_noc_bus_oic_evemon_7_trigger"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_7_TRIGGER_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_8_start` reader - u0_sft7110_noc_bus_oic_evemon_8_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_8_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_8_start` writer - u0_sft7110_noc_bus_oic_evemon_8_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_8_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_8_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_8_trigger` reader - u0_sft7110_noc_bus_oic_evemon_8_trigger"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_8_TRIGGER_R = crate::BitReader; impl R { @@ -117,58 +110,62 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_ignore_modifiable_0( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_0_W { - U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_0_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_0_W { + U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_0_W::new(self, 5) } #[doc = "Bit 6 - u0_sft7110_noc_bus_oic_ignore_modifiable_1"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_ignore_modifiable_1( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_1_W { - U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_1_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_1_W { + U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_1_W::new(self, 6) } #[doc = "Bit 7 - u0_sft7110_noc_bus_oic_ignore_modifiable_2"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_ignore_modifiable_2( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_2_W { - U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_2_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_2_W { + U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_2_W::new(self, 7) } #[doc = "Bit 8 - u0_sft7110_noc_bus_oic_ignore_modifiable_3"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_ignore_modifiable_3( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_3_W { - U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_3_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_3_W { + U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_3_W::new(self, 8) } #[doc = "Bit 9 - u0_sft7110_noc_bus_oic_ignore_modifiable_4"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_ignore_modifiable_4( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_4_W { - U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_4_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_4_W { + U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_4_W::new(self, 9) } #[doc = "Bit 15 - u0_sft7110_noc_bus_oic_evemon_7_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_7_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_7_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_7_START_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_7_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_7_START_W::new(self, 15) } #[doc = "Bit 17 - u0_sft7110_noc_bus_oic_evemon_8_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_8_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_8_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_8_START_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_8_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_8_START_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg60.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg60.rs index 39b1d8b..b97b06c 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg60.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg60.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_0_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_0_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_0_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_0_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_0_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg64.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg64.rs index 49420eb..94c764c 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg64.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg64.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_1_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_1_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_1_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_1_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_1_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_1_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_1_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg68.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg68.rs index cc52112..81fd95e 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg68.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg68.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_2_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_2_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_2_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_2_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_2_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_2_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_2_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg72.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg72.rs index f09b603..ddcbe13 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg72.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg72.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_3_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_3_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_3_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_3_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_3_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_3_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_3_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg76.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg76.rs index 271084e..1f33d71 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg76.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg76.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_4_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_4_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_4_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_4_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_4_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_4_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_4_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg8.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg8.rs index 4d8c810..a7e4743 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg8.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg8.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `scfg_vout0_remap_awaddr` reader - scfg_vout0_remap_awaddr"] pub type SCFG_VOUT0_REMAP_AWADDR_R = crate::FieldReader; #[doc = "Field `scfg_vout0_remap_awaddr` writer - scfg_vout0_remap_awaddr"] -pub type SCFG_VOUT0_REMAP_AWADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_VOUT0_REMAP_AWADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_vout1_remap_araddr` reader - scfg_vout1_remap_araddr"] pub type SCFG_VOUT1_REMAP_ARADDR_R = crate::FieldReader; #[doc = "Field `scfg_vout1_remap_araddr` writer - scfg_vout1_remap_araddr"] -pub type SCFG_VOUT1_REMAP_ARADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_VOUT1_REMAP_ARADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_vout1_remap_awaddr` reader - scfg_vout1_remap_awaddr"] pub type SCFG_VOUT1_REMAP_AWADDR_R = crate::FieldReader; #[doc = "Field `scfg_vout1_remap_awaddr` writer - scfg_vout1_remap_awaddr"] -pub type SCFG_VOUT1_REMAP_AWADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_VOUT1_REMAP_AWADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - scfg_vout0_remap_awaddr"] #[inline(always)] @@ -37,26 +37,30 @@ impl W { #[must_use] pub fn scfg_vout0_remap_awaddr( &mut self, - ) -> SCFG_VOUT0_REMAP_AWADDR_W { - SCFG_VOUT0_REMAP_AWADDR_W::new(self) + ) -> SCFG_VOUT0_REMAP_AWADDR_W { + SCFG_VOUT0_REMAP_AWADDR_W::new(self, 0) } #[doc = "Bits 4:7 - scfg_vout1_remap_araddr"] #[inline(always)] #[must_use] pub fn scfg_vout1_remap_araddr( &mut self, - ) -> SCFG_VOUT1_REMAP_ARADDR_W { - SCFG_VOUT1_REMAP_ARADDR_W::new(self) + ) -> SCFG_VOUT1_REMAP_ARADDR_W { + SCFG_VOUT1_REMAP_ARADDR_W::new(self, 4) } #[doc = "Bits 8:11 - scfg_vout1_remap_awaddr"] #[inline(always)] #[must_use] pub fn scfg_vout1_remap_awaddr( &mut self, - ) -> SCFG_VOUT1_REMAP_AWADDR_W { - SCFG_VOUT1_REMAP_AWADDR_W::new(self) + ) -> SCFG_VOUT1_REMAP_AWADDR_W { + SCFG_VOUT1_REMAP_AWADDR_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg80.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg80.rs index c029f58..4e441f1 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg80.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg80.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_5_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_5_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_5_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_5_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_5_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_5_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_5_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg84.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg84.rs index 36eb861..e2bb714 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg84.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg84.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_6_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_6_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_6_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_6_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_6_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_6_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_6_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg88.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg88.rs index 432ab5e..0dd9ee1 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg88.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg88.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_7_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_7_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_7_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_7_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_7_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_7_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_7_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg92.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg92.rs index 99964b1..0f09a22 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg92.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg92.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_8_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_8_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_8_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_8_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_8_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_8_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_8_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg96.rs b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg96.rs index 305193e..a20fe51 100644 --- a/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg96.rs +++ b/jh7110-vf2-12a-pac/src/sys_syscon/sys_sysconsaif_syscfg96.rs @@ -9,27 +9,27 @@ pub type U0_TDM16SLOT_PCM_MS_R = crate::BitReader; #[doc = "Field `u0_trace_mtx_scfg_c0_in0_ctl` reader - u0_trace_mtx_scfg_c0_in0_ctl"] pub type U0_TRACE_MTX_SCFG_C0_IN0_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c0_in0_ctl` writer - u0_trace_mtx_scfg_c0_in0_ctl"] -pub type U0_TRACE_MTX_SCFG_C0_IN0_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C0_IN0_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_trace_mtx_scfg_c0_in1_ctl` reader - u0_trace_mtx_scfg_c0_in1_ctl"] pub type U0_TRACE_MTX_SCFG_C0_IN1_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c0_in1_ctl` writer - u0_trace_mtx_scfg_c0_in1_ctl"] -pub type U0_TRACE_MTX_SCFG_C0_IN1_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C0_IN1_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_trace_mtx_scfg_c1_in0_ctl` reader - u0_trace_mtx_scfg_c1_in0_ctl"] pub type U0_TRACE_MTX_SCFG_C1_IN0_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c1_in0_ctl` writer - u0_trace_mtx_scfg_c1_in0_ctl"] -pub type U0_TRACE_MTX_SCFG_C1_IN0_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C1_IN0_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_trace_mtx_scfg_c1_in1_ctl` reader - u0_trace_mtx_scfg_c1_in1_ctl"] pub type U0_TRACE_MTX_SCFG_C1_IN1_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c1_in1_ctl` writer - u0_trace_mtx_scfg_c1_in1_ctl"] -pub type U0_TRACE_MTX_SCFG_C1_IN1_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C1_IN1_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_trace_mtx_scfg_c2_in0_ctl` reader - u0_trace_mtx_scfg_c2_in0_ctl"] pub type U0_TRACE_MTX_SCFG_C2_IN0_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c2_in0_ctl` writer - u0_trace_mtx_scfg_c2_in0_ctl"] -pub type U0_TRACE_MTX_SCFG_C2_IN0_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C2_IN0_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_trace_mtx_scfg_c2_in1_ctl` reader - u0_trace_mtx_scfg_c2_in1_ctl"] pub type U0_TRACE_MTX_SCFG_C2_IN1_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c2_in1_ctl` writer - u0_trace_mtx_scfg_c2_in1_ctl"] -pub type U0_TRACE_MTX_SCFG_C2_IN1_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C2_IN1_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; impl R { #[doc = "Bit 0 - u0_tdm16slot_clkpol"] #[inline(always)] @@ -78,50 +78,54 @@ impl W { #[must_use] pub fn u0_trace_mtx_scfg_c0_in0_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C0_IN0_CTL_W { - U0_TRACE_MTX_SCFG_C0_IN0_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C0_IN0_CTL_W { + U0_TRACE_MTX_SCFG_C0_IN0_CTL_W::new(self, 2) } #[doc = "Bits 7:11 - u0_trace_mtx_scfg_c0_in1_ctl"] #[inline(always)] #[must_use] pub fn u0_trace_mtx_scfg_c0_in1_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C0_IN1_CTL_W { - U0_TRACE_MTX_SCFG_C0_IN1_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C0_IN1_CTL_W { + U0_TRACE_MTX_SCFG_C0_IN1_CTL_W::new(self, 7) } #[doc = "Bits 12:16 - u0_trace_mtx_scfg_c1_in0_ctl"] #[inline(always)] #[must_use] pub fn u0_trace_mtx_scfg_c1_in0_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C1_IN0_CTL_W { - U0_TRACE_MTX_SCFG_C1_IN0_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C1_IN0_CTL_W { + U0_TRACE_MTX_SCFG_C1_IN0_CTL_W::new(self, 12) } #[doc = "Bits 17:21 - u0_trace_mtx_scfg_c1_in1_ctl"] #[inline(always)] #[must_use] pub fn u0_trace_mtx_scfg_c1_in1_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C1_IN1_CTL_W { - U0_TRACE_MTX_SCFG_C1_IN1_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C1_IN1_CTL_W { + U0_TRACE_MTX_SCFG_C1_IN1_CTL_W::new(self, 17) } #[doc = "Bits 22:26 - u0_trace_mtx_scfg_c2_in0_ctl"] #[inline(always)] #[must_use] pub fn u0_trace_mtx_scfg_c2_in0_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C2_IN0_CTL_W { - U0_TRACE_MTX_SCFG_C2_IN0_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C2_IN0_CTL_W { + U0_TRACE_MTX_SCFG_C2_IN0_CTL_W::new(self, 22) } #[doc = "Bits 27:31 - u0_trace_mtx_scfg_c2_in1_ctl"] #[inline(always)] #[must_use] pub fn u0_trace_mtx_scfg_c2_in1_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C2_IN1_CTL_W { - U0_TRACE_MTX_SCFG_C2_IN1_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C2_IN1_CTL_W { + U0_TRACE_MTX_SCFG_C2_IN1_CTL_W::new(self, 27) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg.rs b/jh7110-vf2-12a-pac/src/syscrg.rs index 7c82f4a..8ff6910 100644 --- a/jh7110-vf2-12a-pac/src/syscrg.rs +++ b/jh7110-vf2-12a-pac/src/syscrg.rs @@ -1,1405 +1,2206 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + clk_cpu_root: CLK_CPU_ROOT, + clk_cpu_core: CLK_CPU_CORE, + clk_cpu_bus: CLK_CPU_BUS, + clk_gpu_root: CLK_GPU_ROOT, + clk_peripheral_root: CLK_PERIPHERAL_ROOT, + clk_bus_root: CLK_BUS_ROOT, + clk_nocstg_bus: CLK_NOCSTG_BUS, + clk_axi_cfg0: CLK_AXI_CFG0, + clk_stg_axiahb: CLK_STG_AXIAHB, + clk_ahb0: CLK_AHB0, + clk_ahb1: CLK_AHB1, + clk_apb_bus: CLK_APB_BUS, + clk_apb0: CLK_APB0, + clk_pll0_div2: CLK_PLL0_DIV2, + clk_pll1_div2: CLK_PLL1_DIV2, + clk_pll2_div2: CLK_PLL2_DIV2, + clk_audio_root: CLK_AUDIO_ROOT, + clk_mclk_inner: CLK_MCLK_INNER, + clk_mclk: CLK_MCLK, + clk_mclk_out: CLK_MCLK_OUT, + clk_isp_2x: CLK_ISP_2X, + clk_isp_axi: CLK_ISP_AXI, + clk_gclk0: CLK_GCLK0, + clk_gclk1: CLK_GCLK1, + clk_gclk2: CLK_GCLK2, + clk_u7mc_core0: CLK_U7MC_CORE0, + clk_u7mc_core1: CLK_U7MC_CORE1, + clk_u7mc_core2: CLK_U7MC_CORE2, + clk_u7mc_core3: CLK_U7MC_CORE3, + clk_u7mc_core4: CLK_U7MC_CORE4, + clk_u7mc_debug: CLK_U7MC_DEBUG, + u7mc_rtc_toggle: U7MC_RTC_TOGGLE, + clk_u7mc_trace0: CLK_U7MC_TRACE0, + clk_u7mc_trace1: CLK_U7MC_TRACE1, + clk_u7mc_trace2: CLK_U7MC_TRACE2, + clk_u7mc_trace3: CLK_U7MC_TRACE3, + clk_u7mc_trace4: CLK_U7MC_TRACE4, + clk_u7mc_trace_com: CLK_U7MC_TRACE_COM, + clk_u0_sft7110_noc_bus_clk_cpu_axi: CLK_U0_SFT7110_NOC_BUS_CLK_CPU_AXI, + clk_u0_sft7110_noc_bus_clk_axicfg0_axi: CLK_U0_SFT7110_NOC_BUS_CLK_AXICFG0_AXI, + clk_osc_div2: CLK_OSC_DIV2, + clk_pll1_div4: CLK_PLL1_DIV4, + clk_pll1_div8: CLK_PLL1_DIV8, + clk_ddr_bus: CLK_DDR_BUS, + clk_u0_ddr_sft7110_clk_axi: CLK_U0_DDR_SFT7110_CLK_AXI, + clk_gpu_core: CLK_GPU_CORE, + clk_u0_img_gpu_core_clk: CLK_U0_IMG_GPU_CORE_CLK, + clk_u0_img_gpu_sys_clk: CLK_U0_IMG_GPU_SYS_CLK, + clk_u0_img_gpu_clk_apb: CLK_U0_IMG_GPU_CLK_APB, + clk_u0_gpu_rtc_toggle: CLK_U0_GPU_RTC_TOGGLE, + clk_u0_sft7110_noc_bus_clk_gpu_axi: CLK_U0_SFT7110_NOC_BUS_CLK_GPU_AXI, + clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x: + CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISPCORE_2X, + clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi: CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISP_AXI, + clk_u0_sft7110_noc_bux_clk_isp_axi: CLK_U0_SFT7110_NOC_BUX_CLK_ISP_AXI, + clk_hifi4_core: CLK_HIFI4_CORE, + clk_hifi4_axi: CLK_HIFI4_AXI, + clk_u0_axi_cfg1_dec_clk_main: CLK_U0_AXI_CFG1_DEC_CLK_MAIN, + clk_u0_axi_cfg1_dec_clk_ahb: CLK_U0_AXI_CFG1_DEC_CLK_AHB, + clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src: + CLK_U0_DOM_VOUT_TOP_CLK_DOM_VOUT_TOP_CLK_VOUT_SRC, + clk_vout_axi_divcfg: CLK_VOUT_AXI_DIVCFG, + clk_noc_display_axi: CLK_NOC_DISPLAY_AXI, + clk_vout_ahb: CLK_VOUT_AHB, + clk_vout_axi_icg: CLK_VOUT_AXI_ICG, + clk_vout_hdmi_tx0_mclk: CLK_VOUT_HDMI_TX0_MCLK, + clk_vout_mipi_phy: CLK_VOUT_MIPI_PHY, + clk_jpeg_codec_axi: CLK_JPEG_CODEC_AXI, + clk_codaj12_axi: CLK_CODAJ12_AXI, + clk_codaj12_core: CLK_CODAJ12_CORE, + clk_codaj12_apb: CLK_CODAJ12_APB, + clk_vdec_axi: CLK_VDEC_AXI, + clk_wave511_axi: CLK_WAVE511_AXI, + clk_wave511_bpu: CLK_WAVE511_BPU, + clk_wave511_vce: CLK_WAVE511_VCE, + clk_wave511_apb: CLK_WAVE511_APB, + clk_wave511_jpg_arb: CLK_WAVE511_JPG_ARB, + clk_wave511_jpg_main: CLK_WAVE511_JPG_MAIN, + clk_noc_vdec_axi: CLK_NOC_VDEC_AXI, + clk_venc_axi: CLK_VENC_AXI, + clk_wave420l_axi: CLK_WAVE420L_AXI, + clk_wave420l_bpu: CLK_WAVE420L_BPU, + clk_wave420l_vce: CLK_WAVE420L_VCE, + clk_wave420l_apb: CLK_WAVE420L_APB, + clk_noc_venc_axi: CLK_NOC_VENC_AXI, + clk_axi_cfg0_dec_main_div: CLK_AXI_CFG0_DEC_MAIN_DIV, + clk_axi_cfg0_dec_main: CLK_AXI_CFG0_DEC_MAIN, + clk_axi_cfg0_dec_hifi4: CLK_AXI_CFG0_DEC_HIFI4, + clk_aximem_128b_axi: CLK_AXIMEM_128B_AXI, + clk_qspi_ahb: CLK_QSPI_AHB, + clk_qspi_apb: CLK_QSPI_APB, + clk_qspi_ref_src: CLK_QSPI_REF_SRC, + clk_qspi_ref: CLK_QSPI_REF, + clk_u0_sd_ahb: CLK_U0_SD_AHB, + clk_u1_sd_ahb: CLK_U1_SD_AHB, + clk_u0_sd_card: CLK_U0_SD_CARD, + clk_u1_sd_card: CLK_U1_SD_CARD, + clk_usb_125m: CLK_USB_125M, + clk_noc_stg_axi: CLK_NOC_STG_AXI, + clk_gmac5_axi64_ahb: CLK_GMAC5_AXI64_AHB, + clk_gmac5_axi64_axi: CLK_GMAC5_AXI64_AXI, + clk_gmac_src: CLK_GMAC_SRC, + clk_gmac1_gtx: CLK_GMAC1_GTX, + clk_gmac1_rmii_rtx: CLK_GMAC1_RMII_RTX, + clk_gmac5_axi64_ptp: CLK_GMAC5_AXI64_PTP, + clk_gmac5_axi64_rx: CLK_GMAC5_AXI64_RX, + clk_gmac5_axi64_rxi: CLK_GMAC5_AXI64_RXI, + clk_gmac5_axi64_tx: CLK_GMAC5_AXI64_TX, + clk_gmac5_axi64_txi: CLK_GMAC5_AXI64_TXI, + clk_gmac1_gtxclk: CLK_GMAC1_GTXCLK, + clk_gmac0_gtx: CLK_GMAC0_GTX, + clk_gmac0_ptp: CLK_GMAC0_PTP, + clk_gmac_phy: CLK_GMAC_PHY, + clk_gmac0_gtxclk: CLK_GMAC0_GTXCLK, + clk_sys_iomux_pclk: CLK_SYS_IOMUX_PCLK, + clk_mbox_apb: CLK_MBOX_APB, + clk_internal_ctrl_apb: CLK_INTERNAL_CTRL_APB, + clk_u0_can_ctrl_apb: CLK_U0_CAN_CTRL_APB, + clk_u0_can_ctrl_tim: CLK_U0_CAN_CTRL_TIM, + clk_u0_can_ctrl_can: CLK_U0_CAN_CTRL_CAN, + clk_u1_can_ctrl_apb: CLK_U1_CAN_CTRL_APB, + clk_u1_can_ctrl_tim: CLK_U1_CAN_CTRL_TIM, + clk_u1_can_ctrl_can: CLK_U1_CAN_CTRL_CAN, + clk_pwm_apb: CLK_PWM_APB, + clk_wdt_apb: CLK_WDT_APB, + clk_wdt: CLK_WDT, + clk_tim_apb: CLK_TIM_APB, + clk_tim0: CLK_TIM0, + clk_tim1: CLK_TIM1, + clk_tim2: CLK_TIM2, + clk_tim3: CLK_TIM3, + clk_temp_sensor_apb: CLK_TEMP_SENSOR_APB, + clk_temp_sensor: CLK_TEMP_SENSOR, + clk_u0_spi_apb: CLK_U0_SPI_APB, + clk_u1_spi_apb: CLK_U1_SPI_APB, + clk_u2_spi_apb: CLK_U2_SPI_APB, + clk_u3_spi_apb: CLK_U3_SPI_APB, + clk_u4_spi_apb: CLK_U4_SPI_APB, + clk_u5_spi_apb: CLK_U5_SPI_APB, + clk_u6_spi_apb: CLK_U6_SPI_APB, + clk_u0_i2c_apb: CLK_U0_I2C_APB, + clk_u1_i2c_apb: CLK_U1_I2C_APB, + clk_u2_i2c_apb: CLK_U2_I2C_APB, + clk_u3_i2c_apb: CLK_U3_I2C_APB, + clk_u4_i2c_apb: CLK_U4_I2C_APB, + clk_u5_i2c_apb: CLK_U5_I2C_APB, + clk_u6_i2c_apb: CLK_U6_I2C_APB, + clk_u0_uart_apb: CLK_U0_UART_APB, + clk_u0_uart_core: CLK_U0_UART_CORE, + clk_u1_uart_apb: CLK_U1_UART_APB, + clk_u1_uart_core: CLK_U1_UART_CORE, + clk_u2_uart_apb: CLK_U2_UART_APB, + clk_u2_uart_core: CLK_U2_UART_CORE, + clk_u3_uart_apb: CLK_U3_UART_APB, + clk_u3_uart_core: CLK_U3_UART_CORE, + clk_u4_uart_apb: CLK_U4_UART_APB, + clk_u4_uart_core: CLK_U4_UART_CORE, + clk_u5_uart_apb: CLK_U5_UART_APB, + clk_u5_uart_core: CLK_U5_UART_CORE, + clk_pwmdac_apb: CLK_PWMDAC_APB, + clk_pwmdac_core: CLK_PWMDAC_CORE, + clk_spdif_apb: CLK_SPDIF_APB, + clk_spdif_core: CLK_SPDIF_CORE, + clk_u0_i2s_tx_apb: CLK_U0_I2S_TX_APB, + clk_u0_i2stx_4ch0_bclk_mst: CLK_U0_I2STX_4CH0_BCLK_MST, + clk_u0_i2stx_4ch0_bclk_mst_inv: CLK_U0_I2STX_4CH0_BCLK_MST_INV, + clk_i2stx0_lrck_mst: CLK_I2STX0_LRCK_MST, + clk_u0_i2stx_bclk: CLK_U0_I2STX_BCLK, + clk_u0_i2stx_bclk_neg: CLK_U0_I2STX_BCLK_NEG, + clk_u0_i2stx_lrck: CLK_U0_I2STX_LRCK, + clk_u1_i2s_tx_apb: CLK_U1_I2S_TX_APB, + clk_u1_i2stx_4ch1_bclk_mst: CLK_U1_I2STX_4CH1_BCLK_MST, + clk_u1_i2stx_4ch1_bclk_mst_inv: CLK_U1_I2STX_4CH1_BCLK_MST_INV, + clk_i2stx1_lrck_mst: CLK_I2STX1_LRCK_MST, + clk_u1_i2stx_bclk: CLK_U1_I2STX_BCLK, + clk_u1_i2stx_bclk_neg: CLK_U1_I2STX_BCLK_NEG, + clk_u1_i2stx_lrck: CLK_U1_I2STX_LRCK, + clk_i2s_apb: CLK_I2S_APB, + clk_i2s_bclk_mst: CLK_I2S_BCLK_MST, + clk_i2s_bclk_mst_inv: CLK_I2S_BCLK_MST_INV, + clk_i2s_lrck_mst: CLK_I2S_LRCK_MST, + clk_i2s_bclk: CLK_I2S_BCLK, + clk_i2s_bclk_neg: CLK_I2S_BCLK_NEG, + clk_i2s_lrck: CLK_I2S_LRCK, + clk_pdm_dmic: CLK_PDM_DMIC, + clk_pdm_apb: CLK_PDM_APB, + clk_tdm_ahb: CLK_TDM_AHB, + clk_tdm_apb: CLK_TDM_APB, + clk_tdm_internal: CLK_TDM_INTERNAL, + clk_tdm: CLK_TDM, + clk_tdm_neg: CLK_TDM_NEG, + clk_jtag_cert_trng: CLK_JTAG_CERT_TRNG, + soft_rst0_addr_sel: SOFT_RST0_ADDR_SEL, + soft_rst1_addr_sel: SOFT_RST1_ADDR_SEL, + soft_rst2_addr_sel: SOFT_RST2_ADDR_SEL, + soft_rst3_addr_sel: SOFT_RST3_ADDR_SEL, + syscrg_rst0_status: SYSCRG_RST0_STATUS, + syscrg_rst1_status: SYSCRG_RST1_STATUS, + syscrg_rst2_status: SYSCRG_RST2_STATUS, + syscrg_rst3_status: SYSCRG_RST3_STATUS, +} +impl RegisterBlock { #[doc = "0x00 - Clock CPU Root"] - pub clk_cpu_root: CLK_CPU_ROOT, + #[inline(always)] + pub const fn clk_cpu_root(&self) -> &CLK_CPU_ROOT { + &self.clk_cpu_root + } #[doc = "0x04 - Clock CPU Core"] - pub clk_cpu_core: CLK_CPU_CORE, + #[inline(always)] + pub const fn clk_cpu_core(&self) -> &CLK_CPU_CORE { + &self.clk_cpu_core + } #[doc = "0x08 - Clock CPU Bus"] - pub clk_cpu_bus: CLK_CPU_BUS, + #[inline(always)] + pub const fn clk_cpu_bus(&self) -> &CLK_CPU_BUS { + &self.clk_cpu_bus + } #[doc = "0x0c - Clock GPU Root"] - pub clk_gpu_root: CLK_GPU_ROOT, + #[inline(always)] + pub const fn clk_gpu_root(&self) -> &CLK_GPU_ROOT { + &self.clk_gpu_root + } #[doc = "0x10 - Clock Peripheral Root"] - pub clk_peripheral_root: CLK_PERIPHERAL_ROOT, + #[inline(always)] + pub const fn clk_peripheral_root(&self) -> &CLK_PERIPHERAL_ROOT { + &self.clk_peripheral_root + } #[doc = "0x14 - Clock Bus Root"] - pub clk_bus_root: CLK_BUS_ROOT, + #[inline(always)] + pub const fn clk_bus_root(&self) -> &CLK_BUS_ROOT { + &self.clk_bus_root + } #[doc = "0x18 - Clock NOCSTG Bus"] - pub clk_nocstg_bus: CLK_NOCSTG_BUS, + #[inline(always)] + pub const fn clk_nocstg_bus(&self) -> &CLK_NOCSTG_BUS { + &self.clk_nocstg_bus + } #[doc = "0x1c - Clock AXI Configuration 0"] - pub clk_axi_cfg0: CLK_AXI_CFG0, + #[inline(always)] + pub const fn clk_axi_cfg0(&self) -> &CLK_AXI_CFG0 { + &self.clk_axi_cfg0 + } #[doc = "0x20 - Clock STG AXI AHB"] - pub clk_stg_axiahb: CLK_STG_AXIAHB, + #[inline(always)] + pub const fn clk_stg_axiahb(&self) -> &CLK_STG_AXIAHB { + &self.clk_stg_axiahb + } #[doc = "0x24 - Clock AHB 0"] - pub clk_ahb0: CLK_AHB0, + #[inline(always)] + pub const fn clk_ahb0(&self) -> &CLK_AHB0 { + &self.clk_ahb0 + } #[doc = "0x28 - Clock AHB 1"] - pub clk_ahb1: CLK_AHB1, + #[inline(always)] + pub const fn clk_ahb1(&self) -> &CLK_AHB1 { + &self.clk_ahb1 + } #[doc = "0x2c - Clock APB Bus"] - pub clk_apb_bus: CLK_APB_BUS, + #[inline(always)] + pub const fn clk_apb_bus(&self) -> &CLK_APB_BUS { + &self.clk_apb_bus + } #[doc = "0x30 - Clock APB 0"] - pub clk_apb0: CLK_APB0, + #[inline(always)] + pub const fn clk_apb0(&self) -> &CLK_APB0 { + &self.clk_apb0 + } #[doc = "0x34 - Clock PLL 0 Divider 2"] - pub clk_pll0_div2: CLK_PLL0_DIV2, + #[inline(always)] + pub const fn clk_pll0_div2(&self) -> &CLK_PLL0_DIV2 { + &self.clk_pll0_div2 + } #[doc = "0x38 - Clock PLL 1 Divider 2"] - pub clk_pll1_div2: CLK_PLL1_DIV2, + #[inline(always)] + pub const fn clk_pll1_div2(&self) -> &CLK_PLL1_DIV2 { + &self.clk_pll1_div2 + } #[doc = "0x3c - Clock PLL 2 Divider 2"] - pub clk_pll2_div2: CLK_PLL2_DIV2, + #[inline(always)] + pub const fn clk_pll2_div2(&self) -> &CLK_PLL2_DIV2 { + &self.clk_pll2_div2 + } #[doc = "0x40 - Clock Audio Root"] - pub clk_audio_root: CLK_AUDIO_ROOT, + #[inline(always)] + pub const fn clk_audio_root(&self) -> &CLK_AUDIO_ROOT { + &self.clk_audio_root + } #[doc = "0x44 - Clock MCLK Inner"] - pub clk_mclk_inner: CLK_MCLK_INNER, + #[inline(always)] + pub const fn clk_mclk_inner(&self) -> &CLK_MCLK_INNER { + &self.clk_mclk_inner + } #[doc = "0x48 - Clock MCLK"] - pub clk_mclk: CLK_MCLK, + #[inline(always)] + pub const fn clk_mclk(&self) -> &CLK_MCLK { + &self.clk_mclk + } #[doc = "0x4c - Clock MCLK Out"] - pub clk_mclk_out: CLK_MCLK_OUT, + #[inline(always)] + pub const fn clk_mclk_out(&self) -> &CLK_MCLK_OUT { + &self.clk_mclk_out + } #[doc = "0x50 - Clock ISP 2x"] - pub clk_isp_2x: CLK_ISP_2X, + #[inline(always)] + pub const fn clk_isp_2x(&self) -> &CLK_ISP_2X { + &self.clk_isp_2x + } #[doc = "0x54 - Clock ISP AXI"] - pub clk_isp_axi: CLK_ISP_AXI, + #[inline(always)] + pub const fn clk_isp_axi(&self) -> &CLK_ISP_AXI { + &self.clk_isp_axi + } #[doc = "0x58 - Clock GCLK 0"] - pub clk_gclk0: CLK_GCLK0, + #[inline(always)] + pub const fn clk_gclk0(&self) -> &CLK_GCLK0 { + &self.clk_gclk0 + } #[doc = "0x5c - Clock GCLK 1"] - pub clk_gclk1: CLK_GCLK1, + #[inline(always)] + pub const fn clk_gclk1(&self) -> &CLK_GCLK1 { + &self.clk_gclk1 + } #[doc = "0x60 - Clock GCLK 2"] - pub clk_gclk2: CLK_GCLK2, + #[inline(always)] + pub const fn clk_gclk2(&self) -> &CLK_GCLK2 { + &self.clk_gclk2 + } #[doc = "0x64 - U7MC Core Clock 0"] - pub clk_u7mc_core0: CLK_U7MC_CORE0, + #[inline(always)] + pub const fn clk_u7mc_core0(&self) -> &CLK_U7MC_CORE0 { + &self.clk_u7mc_core0 + } #[doc = "0x68 - U7MC Core Clock 1"] - pub clk_u7mc_core1: CLK_U7MC_CORE1, + #[inline(always)] + pub const fn clk_u7mc_core1(&self) -> &CLK_U7MC_CORE1 { + &self.clk_u7mc_core1 + } #[doc = "0x6c - U7MC Core Clock 2"] - pub clk_u7mc_core2: CLK_U7MC_CORE2, + #[inline(always)] + pub const fn clk_u7mc_core2(&self) -> &CLK_U7MC_CORE2 { + &self.clk_u7mc_core2 + } #[doc = "0x70 - U7MC Core Clock 3"] - pub clk_u7mc_core3: CLK_U7MC_CORE3, + #[inline(always)] + pub const fn clk_u7mc_core3(&self) -> &CLK_U7MC_CORE3 { + &self.clk_u7mc_core3 + } #[doc = "0x74 - U7MC Core Clock 4"] - pub clk_u7mc_core4: CLK_U7MC_CORE4, + #[inline(always)] + pub const fn clk_u7mc_core4(&self) -> &CLK_U7MC_CORE4 { + &self.clk_u7mc_core4 + } #[doc = "0x78 - U7MC Debug Clock"] - pub clk_u7mc_debug: CLK_U7MC_DEBUG, + #[inline(always)] + pub const fn clk_u7mc_debug(&self) -> &CLK_U7MC_DEBUG { + &self.clk_u7mc_debug + } #[doc = "0x7c - U7MC RTC Toggle"] - pub u7mc_rtc_toggle: U7MC_RTC_TOGGLE, + #[inline(always)] + pub const fn u7mc_rtc_toggle(&self) -> &U7MC_RTC_TOGGLE { + &self.u7mc_rtc_toggle + } #[doc = "0x80 - U7MC Trace Clock 0"] - pub clk_u7mc_trace0: CLK_U7MC_TRACE0, + #[inline(always)] + pub const fn clk_u7mc_trace0(&self) -> &CLK_U7MC_TRACE0 { + &self.clk_u7mc_trace0 + } #[doc = "0x84 - U7MC Trace Clock 1"] - pub clk_u7mc_trace1: CLK_U7MC_TRACE1, + #[inline(always)] + pub const fn clk_u7mc_trace1(&self) -> &CLK_U7MC_TRACE1 { + &self.clk_u7mc_trace1 + } #[doc = "0x88 - U7MC Trace Clock 2"] - pub clk_u7mc_trace2: CLK_U7MC_TRACE2, + #[inline(always)] + pub const fn clk_u7mc_trace2(&self) -> &CLK_U7MC_TRACE2 { + &self.clk_u7mc_trace2 + } #[doc = "0x8c - U7MC Trace Clock 3"] - pub clk_u7mc_trace3: CLK_U7MC_TRACE3, + #[inline(always)] + pub const fn clk_u7mc_trace3(&self) -> &CLK_U7MC_TRACE3 { + &self.clk_u7mc_trace3 + } #[doc = "0x90 - U7MC Trace Clock 4"] - pub clk_u7mc_trace4: CLK_U7MC_TRACE4, + #[inline(always)] + pub const fn clk_u7mc_trace4(&self) -> &CLK_U7MC_TRACE4 { + &self.clk_u7mc_trace4 + } #[doc = "0x94 - U7MC Trace Clock COM"] - pub clk_u7mc_trace_com: CLK_U7MC_TRACE_COM, + #[inline(always)] + pub const fn clk_u7mc_trace_com(&self) -> &CLK_U7MC_TRACE_COM { + &self.clk_u7mc_trace_com + } #[doc = "0x98 - clk_u0_sft7110_noc_bus_clk_cpu_axi"] - pub clk_u0_sft7110_noc_bus_clk_cpu_axi: CLK_U0_SFT7110_NOC_BUS_CLK_CPU_AXI, + #[inline(always)] + pub const fn clk_u0_sft7110_noc_bus_clk_cpu_axi(&self) -> &CLK_U0_SFT7110_NOC_BUS_CLK_CPU_AXI { + &self.clk_u0_sft7110_noc_bus_clk_cpu_axi + } #[doc = "0x9c - clk_u0_sft7110_noc_bus_clk_axicfg0_axi"] - pub clk_u0_sft7110_noc_bus_clk_axicfg0_axi: CLK_U0_SFT7110_NOC_BUS_CLK_AXICFG0_AXI, + #[inline(always)] + pub const fn clk_u0_sft7110_noc_bus_clk_axicfg0_axi( + &self, + ) -> &CLK_U0_SFT7110_NOC_BUS_CLK_AXICFG0_AXI { + &self.clk_u0_sft7110_noc_bus_clk_axicfg0_axi + } #[doc = "0xa0 - clk_osc_div2"] - pub clk_osc_div2: CLK_OSC_DIV2, + #[inline(always)] + pub const fn clk_osc_div2(&self) -> &CLK_OSC_DIV2 { + &self.clk_osc_div2 + } #[doc = "0xa4 - clk_pll1_div4"] - pub clk_pll1_div4: CLK_PLL1_DIV4, + #[inline(always)] + pub const fn clk_pll1_div4(&self) -> &CLK_PLL1_DIV4 { + &self.clk_pll1_div4 + } #[doc = "0xa8 - clk_pll1_div8"] - pub clk_pll1_div8: CLK_PLL1_DIV8, + #[inline(always)] + pub const fn clk_pll1_div8(&self) -> &CLK_PLL1_DIV8 { + &self.clk_pll1_div8 + } #[doc = "0xac - clk_ddr_bus"] - pub clk_ddr_bus: CLK_DDR_BUS, + #[inline(always)] + pub const fn clk_ddr_bus(&self) -> &CLK_DDR_BUS { + &self.clk_ddr_bus + } #[doc = "0xb0 - clk_u0_ddr_sfft7110_clk_axi"] - pub clk_u0_ddr_sft7110_clk_axi: CLK_U0_DDR_SFT7110_CLK_AXI, + #[inline(always)] + pub const fn clk_u0_ddr_sft7110_clk_axi(&self) -> &CLK_U0_DDR_SFT7110_CLK_AXI { + &self.clk_u0_ddr_sft7110_clk_axi + } #[doc = "0xb4 - clk_gpu_core"] - pub clk_gpu_core: CLK_GPU_CORE, + #[inline(always)] + pub const fn clk_gpu_core(&self) -> &CLK_GPU_CORE { + &self.clk_gpu_core + } #[doc = "0xb8 - clk_u0_img_gpu_core_clk"] - pub clk_u0_img_gpu_core_clk: CLK_U0_IMG_GPU_CORE_CLK, + #[inline(always)] + pub const fn clk_u0_img_gpu_core_clk(&self) -> &CLK_U0_IMG_GPU_CORE_CLK { + &self.clk_u0_img_gpu_core_clk + } #[doc = "0xbc - clk_u0_img_gpu_sys_clk"] - pub clk_u0_img_gpu_sys_clk: CLK_U0_IMG_GPU_SYS_CLK, + #[inline(always)] + pub const fn clk_u0_img_gpu_sys_clk(&self) -> &CLK_U0_IMG_GPU_SYS_CLK { + &self.clk_u0_img_gpu_sys_clk + } #[doc = "0xc0 - clk_u0_img_gpu_clk_apb"] - pub clk_u0_img_gpu_clk_apb: CLK_U0_IMG_GPU_CLK_APB, + #[inline(always)] + pub const fn clk_u0_img_gpu_clk_apb(&self) -> &CLK_U0_IMG_GPU_CLK_APB { + &self.clk_u0_img_gpu_clk_apb + } #[doc = "0xc4 - clk_u0_gpu_rtc_toggle"] - pub clk_u0_gpu_rtc_toggle: CLK_U0_GPU_RTC_TOGGLE, + #[inline(always)] + pub const fn clk_u0_gpu_rtc_toggle(&self) -> &CLK_U0_GPU_RTC_TOGGLE { + &self.clk_u0_gpu_rtc_toggle + } #[doc = "0xc8 - clk_u0_sft7110_noc_bus_clk_gpu_axi"] - pub clk_u0_sft7110_noc_bus_clk_gpu_axi: CLK_U0_SFT7110_NOC_BUS_CLK_GPU_AXI, + #[inline(always)] + pub const fn clk_u0_sft7110_noc_bus_clk_gpu_axi(&self) -> &CLK_U0_SFT7110_NOC_BUS_CLK_GPU_AXI { + &self.clk_u0_sft7110_noc_bus_clk_gpu_axi + } #[doc = "0xcc - clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x"] - pub clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x: - CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISPCORE_2X, + #[inline(always)] + pub const fn clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x( + &self, + ) -> &CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISPCORE_2X { + &self.clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x + } #[doc = "0xd0 - clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi"] - pub clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi: - CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISP_AXI, + #[inline(always)] + pub const fn clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi( + &self, + ) -> &CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISP_AXI { + &self.clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi + } #[doc = "0xd4 - clk_u0_sft7110_noc_bux_clk_isp_axi"] - pub clk_u0_sft7110_noc_bux_clk_isp_axi: CLK_U0_SFT7110_NOC_BUX_CLK_ISP_AXI, + #[inline(always)] + pub const fn clk_u0_sft7110_noc_bux_clk_isp_axi(&self) -> &CLK_U0_SFT7110_NOC_BUX_CLK_ISP_AXI { + &self.clk_u0_sft7110_noc_bux_clk_isp_axi + } #[doc = "0xd8 - clk_hifi4_core"] - pub clk_hifi4_core: CLK_HIFI4_CORE, + #[inline(always)] + pub const fn clk_hifi4_core(&self) -> &CLK_HIFI4_CORE { + &self.clk_hifi4_core + } #[doc = "0xdc - clk_hifi4_axi"] - pub clk_hifi4_axi: CLK_HIFI4_AXI, + #[inline(always)] + pub const fn clk_hifi4_axi(&self) -> &CLK_HIFI4_AXI { + &self.clk_hifi4_axi + } #[doc = "0xe0 - clk_u0_axi_cfg1_dec_clk_main"] - pub clk_u0_axi_cfg1_dec_clk_main: CLK_U0_AXI_CFG1_DEC_CLK_MAIN, + #[inline(always)] + pub const fn clk_u0_axi_cfg1_dec_clk_main(&self) -> &CLK_U0_AXI_CFG1_DEC_CLK_MAIN { + &self.clk_u0_axi_cfg1_dec_clk_main + } #[doc = "0xe4 - clk_u0_axi_cfg1_dec_clk_ahb"] - pub clk_u0_axi_cfg1_dec_clk_ahb: CLK_U0_AXI_CFG1_DEC_CLK_AHB, + #[inline(always)] + pub const fn clk_u0_axi_cfg1_dec_clk_ahb(&self) -> &CLK_U0_AXI_CFG1_DEC_CLK_AHB { + &self.clk_u0_axi_cfg1_dec_clk_ahb + } #[doc = "0xe8 - clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src"] - pub clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src: - CLK_U0_DOM_VOUT_TOP_CLK_DOM_VOUT_TOP_CLK_VOUT_SRC, + #[inline(always)] + pub const fn clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src( + &self, + ) -> &CLK_U0_DOM_VOUT_TOP_CLK_DOM_VOUT_TOP_CLK_VOUT_SRC { + &self.clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src + } #[doc = "0xec - Clock Video Output AXI DIVCFG"] - pub clk_vout_axi_divcfg: CLK_VOUT_AXI_DIVCFG, + #[inline(always)] + pub const fn clk_vout_axi_divcfg(&self) -> &CLK_VOUT_AXI_DIVCFG { + &self.clk_vout_axi_divcfg + } #[doc = "0xf0 - Clock NOC Display AXI"] - pub clk_noc_display_axi: CLK_NOC_DISPLAY_AXI, + #[inline(always)] + pub const fn clk_noc_display_axi(&self) -> &CLK_NOC_DISPLAY_AXI { + &self.clk_noc_display_axi + } #[doc = "0xf4 - Clock Video Output AHB"] - pub clk_vout_ahb: CLK_VOUT_AHB, + #[inline(always)] + pub const fn clk_vout_ahb(&self) -> &CLK_VOUT_AHB { + &self.clk_vout_ahb + } #[doc = "0xf8 - Clock Video Output AXI ICG"] - pub clk_vout_axi_icg: CLK_VOUT_AXI_ICG, + #[inline(always)] + pub const fn clk_vout_axi_icg(&self) -> &CLK_VOUT_AXI_ICG { + &self.clk_vout_axi_icg + } #[doc = "0xfc - Clock Video Output HDMI TX0 MCLK"] - pub clk_vout_hdmi_tx0_mclk: CLK_VOUT_HDMI_TX0_MCLK, + #[inline(always)] + pub const fn clk_vout_hdmi_tx0_mclk(&self) -> &CLK_VOUT_HDMI_TX0_MCLK { + &self.clk_vout_hdmi_tx0_mclk + } #[doc = "0x100 - Clock Video Output MIPI PHY Reference"] - pub clk_vout_mipi_phy: CLK_VOUT_MIPI_PHY, + #[inline(always)] + pub const fn clk_vout_mipi_phy(&self) -> &CLK_VOUT_MIPI_PHY { + &self.clk_vout_mipi_phy + } #[doc = "0x104 - Clock JPEG Codec AXI"] - pub clk_jpeg_codec_axi: CLK_JPEG_CODEC_AXI, + #[inline(always)] + pub const fn clk_jpeg_codec_axi(&self) -> &CLK_JPEG_CODEC_AXI { + &self.clk_jpeg_codec_axi + } #[doc = "0x108 - CODAJ12 Clock AXI"] - pub clk_codaj12_axi: CLK_CODAJ12_AXI, + #[inline(always)] + pub const fn clk_codaj12_axi(&self) -> &CLK_CODAJ12_AXI { + &self.clk_codaj12_axi + } #[doc = "0x10c - CODAJ12 Clock Core"] - pub clk_codaj12_core: CLK_CODAJ12_CORE, + #[inline(always)] + pub const fn clk_codaj12_core(&self) -> &CLK_CODAJ12_CORE { + &self.clk_codaj12_core + } #[doc = "0x110 - CODAJ12 Clock APB"] - pub clk_codaj12_apb: CLK_CODAJ12_APB, + #[inline(always)] + pub const fn clk_codaj12_apb(&self) -> &CLK_CODAJ12_APB { + &self.clk_codaj12_apb + } #[doc = "0x114 - Clock Video Decoder AXI"] - pub clk_vdec_axi: CLK_VDEC_AXI, + #[inline(always)] + pub const fn clk_vdec_axi(&self) -> &CLK_VDEC_AXI { + &self.clk_vdec_axi + } #[doc = "0x118 - Clock WAVE511 AXI"] - pub clk_wave511_axi: CLK_WAVE511_AXI, + #[inline(always)] + pub const fn clk_wave511_axi(&self) -> &CLK_WAVE511_AXI { + &self.clk_wave511_axi + } #[doc = "0x11c - Clock WAVE511 BPU"] - pub clk_wave511_bpu: CLK_WAVE511_BPU, + #[inline(always)] + pub const fn clk_wave511_bpu(&self) -> &CLK_WAVE511_BPU { + &self.clk_wave511_bpu + } #[doc = "0x120 - Clock WAVE511 VCE"] - pub clk_wave511_vce: CLK_WAVE511_VCE, + #[inline(always)] + pub const fn clk_wave511_vce(&self) -> &CLK_WAVE511_VCE { + &self.clk_wave511_vce + } #[doc = "0x124 - Clock WAVE511 APB"] - pub clk_wave511_apb: CLK_WAVE511_APB, + #[inline(always)] + pub const fn clk_wave511_apb(&self) -> &CLK_WAVE511_APB { + &self.clk_wave511_apb + } #[doc = "0x128 - Clock WAVE511 JPG ARB"] - pub clk_wave511_jpg_arb: CLK_WAVE511_JPG_ARB, + #[inline(always)] + pub const fn clk_wave511_jpg_arb(&self) -> &CLK_WAVE511_JPG_ARB { + &self.clk_wave511_jpg_arb + } #[doc = "0x12c - Clock WAVE511 JPG Main"] - pub clk_wave511_jpg_main: CLK_WAVE511_JPG_MAIN, + #[inline(always)] + pub const fn clk_wave511_jpg_main(&self) -> &CLK_WAVE511_JPG_MAIN { + &self.clk_wave511_jpg_main + } #[doc = "0x130 - Clock NOC Video Decoder AXI"] - pub clk_noc_vdec_axi: CLK_NOC_VDEC_AXI, + #[inline(always)] + pub const fn clk_noc_vdec_axi(&self) -> &CLK_NOC_VDEC_AXI { + &self.clk_noc_vdec_axi + } #[doc = "0x134 - Clock Video Encoder AXI"] - pub clk_venc_axi: CLK_VENC_AXI, + #[inline(always)] + pub const fn clk_venc_axi(&self) -> &CLK_VENC_AXI { + &self.clk_venc_axi + } #[doc = "0x138 - Clock WAVE420L AXI"] - pub clk_wave420l_axi: CLK_WAVE420L_AXI, + #[inline(always)] + pub const fn clk_wave420l_axi(&self) -> &CLK_WAVE420L_AXI { + &self.clk_wave420l_axi + } #[doc = "0x13c - Clock WAVE420L BPU"] - pub clk_wave420l_bpu: CLK_WAVE420L_BPU, + #[inline(always)] + pub const fn clk_wave420l_bpu(&self) -> &CLK_WAVE420L_BPU { + &self.clk_wave420l_bpu + } #[doc = "0x140 - Clock WAVE420L VCE"] - pub clk_wave420l_vce: CLK_WAVE420L_VCE, + #[inline(always)] + pub const fn clk_wave420l_vce(&self) -> &CLK_WAVE420L_VCE { + &self.clk_wave420l_vce + } #[doc = "0x144 - Clock WAVE420L APB"] - pub clk_wave420l_apb: CLK_WAVE420L_APB, + #[inline(always)] + pub const fn clk_wave420l_apb(&self) -> &CLK_WAVE420L_APB { + &self.clk_wave420l_apb + } #[doc = "0x148 - Clock NOC Video Encoder AXI"] - pub clk_noc_venc_axi: CLK_NOC_VENC_AXI, + #[inline(always)] + pub const fn clk_noc_venc_axi(&self) -> &CLK_NOC_VENC_AXI { + &self.clk_noc_venc_axi + } #[doc = "0x14c - Clock AXI Config 0 DEC Main Divider"] - pub clk_axi_cfg0_dec_main_div: CLK_AXI_CFG0_DEC_MAIN_DIV, + #[inline(always)] + pub const fn clk_axi_cfg0_dec_main_div(&self) -> &CLK_AXI_CFG0_DEC_MAIN_DIV { + &self.clk_axi_cfg0_dec_main_div + } #[doc = "0x150 - Clock AXI Config 0 DEC Main"] - pub clk_axi_cfg0_dec_main: CLK_AXI_CFG0_DEC_MAIN, + #[inline(always)] + pub const fn clk_axi_cfg0_dec_main(&self) -> &CLK_AXI_CFG0_DEC_MAIN { + &self.clk_axi_cfg0_dec_main + } #[doc = "0x154 - Clock AXI Config 0 DEC HIFI4"] - pub clk_axi_cfg0_dec_hifi4: CLK_AXI_CFG0_DEC_HIFI4, + #[inline(always)] + pub const fn clk_axi_cfg0_dec_hifi4(&self) -> &CLK_AXI_CFG0_DEC_HIFI4 { + &self.clk_axi_cfg0_dec_hifi4 + } #[doc = "0x158 - Clock AXIMEM 128B AXI"] - pub clk_aximem_128b_axi: CLK_AXIMEM_128B_AXI, + #[inline(always)] + pub const fn clk_aximem_128b_axi(&self) -> &CLK_AXIMEM_128B_AXI { + &self.clk_aximem_128b_axi + } #[doc = "0x15c - Clock QSPI AHB"] - pub clk_qspi_ahb: CLK_QSPI_AHB, + #[inline(always)] + pub const fn clk_qspi_ahb(&self) -> &CLK_QSPI_AHB { + &self.clk_qspi_ahb + } #[doc = "0x160 - Clock QSPI APB"] - pub clk_qspi_apb: CLK_QSPI_APB, + #[inline(always)] + pub const fn clk_qspi_apb(&self) -> &CLK_QSPI_APB { + &self.clk_qspi_apb + } #[doc = "0x164 - Clock QSPI Reference Source"] - pub clk_qspi_ref_src: CLK_QSPI_REF_SRC, + #[inline(always)] + pub const fn clk_qspi_ref_src(&self) -> &CLK_QSPI_REF_SRC { + &self.clk_qspi_ref_src + } #[doc = "0x168 - Clock QSPI Reference"] - pub clk_qspi_ref: CLK_QSPI_REF, + #[inline(always)] + pub const fn clk_qspi_ref(&self) -> &CLK_QSPI_REF { + &self.clk_qspi_ref + } #[doc = "0x16c - U0 SD Clock AHB"] - pub clk_u0_sd_ahb: CLK_U0_SD_AHB, + #[inline(always)] + pub const fn clk_u0_sd_ahb(&self) -> &CLK_U0_SD_AHB { + &self.clk_u0_sd_ahb + } #[doc = "0x170 - U1 SD Clock AHB"] - pub clk_u1_sd_ahb: CLK_U1_SD_AHB, + #[inline(always)] + pub const fn clk_u1_sd_ahb(&self) -> &CLK_U1_SD_AHB { + &self.clk_u1_sd_ahb + } #[doc = "0x174 - U0 SD Card Clock"] - pub clk_u0_sd_card: CLK_U0_SD_CARD, + #[inline(always)] + pub const fn clk_u0_sd_card(&self) -> &CLK_U0_SD_CARD { + &self.clk_u0_sd_card + } #[doc = "0x178 - U1 SD Card Clock"] - pub clk_u1_sd_card: CLK_U1_SD_CARD, + #[inline(always)] + pub const fn clk_u1_sd_card(&self) -> &CLK_U1_SD_CARD { + &self.clk_u1_sd_card + } #[doc = "0x17c - Clock USB 125M"] - pub clk_usb_125m: CLK_USB_125M, + #[inline(always)] + pub const fn clk_usb_125m(&self) -> &CLK_USB_125M { + &self.clk_usb_125m + } #[doc = "0x180 - Clock NOC STG AXI"] - pub clk_noc_stg_axi: CLK_NOC_STG_AXI, + #[inline(always)] + pub const fn clk_noc_stg_axi(&self) -> &CLK_NOC_STG_AXI { + &self.clk_noc_stg_axi + } #[doc = "0x184 - Clock GMAC 5 AXI 64 AHB"] - pub clk_gmac5_axi64_ahb: CLK_GMAC5_AXI64_AHB, + #[inline(always)] + pub const fn clk_gmac5_axi64_ahb(&self) -> &CLK_GMAC5_AXI64_AHB { + &self.clk_gmac5_axi64_ahb + } #[doc = "0x188 - Clock GMAC 5 AXI 64 AXI"] - pub clk_gmac5_axi64_axi: CLK_GMAC5_AXI64_AXI, + #[inline(always)] + pub const fn clk_gmac5_axi64_axi(&self) -> &CLK_GMAC5_AXI64_AXI { + &self.clk_gmac5_axi64_axi + } #[doc = "0x18c - Clock GMAC Source"] - pub clk_gmac_src: CLK_GMAC_SRC, + #[inline(always)] + pub const fn clk_gmac_src(&self) -> &CLK_GMAC_SRC { + &self.clk_gmac_src + } #[doc = "0x190 - Clock GMAC 1 GTX"] - pub clk_gmac1_gtx: CLK_GMAC1_GTX, + #[inline(always)] + pub const fn clk_gmac1_gtx(&self) -> &CLK_GMAC1_GTX { + &self.clk_gmac1_gtx + } #[doc = "0x194 - Clock GMAC 1 RMII RTX"] - pub clk_gmac1_rmii_rtx: CLK_GMAC1_RMII_RTX, + #[inline(always)] + pub const fn clk_gmac1_rmii_rtx(&self) -> &CLK_GMAC1_RMII_RTX { + &self.clk_gmac1_rmii_rtx + } #[doc = "0x198 - Clock GMAC 5 AXI 64 PTP"] - pub clk_gmac5_axi64_ptp: CLK_GMAC5_AXI64_PTP, + #[inline(always)] + pub const fn clk_gmac5_axi64_ptp(&self) -> &CLK_GMAC5_AXI64_PTP { + &self.clk_gmac5_axi64_ptp + } #[doc = "0x19c - Clock GMAC 5 AXI 64 RX"] - pub clk_gmac5_axi64_rx: CLK_GMAC5_AXI64_RX, + #[inline(always)] + pub const fn clk_gmac5_axi64_rx(&self) -> &CLK_GMAC5_AXI64_RX { + &self.clk_gmac5_axi64_rx + } #[doc = "0x1a0 - Clock GMAC 5 AXI 64 RX Inverter"] - pub clk_gmac5_axi64_rxi: CLK_GMAC5_AXI64_RXI, + #[inline(always)] + pub const fn clk_gmac5_axi64_rxi(&self) -> &CLK_GMAC5_AXI64_RXI { + &self.clk_gmac5_axi64_rxi + } #[doc = "0x1a4 - Clock GMAC 5 AXI 64 TX"] - pub clk_gmac5_axi64_tx: CLK_GMAC5_AXI64_TX, + #[inline(always)] + pub const fn clk_gmac5_axi64_tx(&self) -> &CLK_GMAC5_AXI64_TX { + &self.clk_gmac5_axi64_tx + } #[doc = "0x1a8 - Clock GMAC 5 AXI 64 TX Inverter"] - pub clk_gmac5_axi64_txi: CLK_GMAC5_AXI64_TXI, + #[inline(always)] + pub const fn clk_gmac5_axi64_txi(&self) -> &CLK_GMAC5_AXI64_TXI { + &self.clk_gmac5_axi64_txi + } #[doc = "0x1ac - Clock GMAC 1 GTXC"] - pub clk_gmac1_gtxclk: CLK_GMAC1_GTXCLK, + #[inline(always)] + pub const fn clk_gmac1_gtxclk(&self) -> &CLK_GMAC1_GTXCLK { + &self.clk_gmac1_gtxclk + } #[doc = "0x1b0 - Clock GMAC 0 GTX"] - pub clk_gmac0_gtx: CLK_GMAC0_GTX, + #[inline(always)] + pub const fn clk_gmac0_gtx(&self) -> &CLK_GMAC0_GTX { + &self.clk_gmac0_gtx + } #[doc = "0x1b4 - Clock GMAC 0 PTP"] - pub clk_gmac0_ptp: CLK_GMAC0_PTP, + #[inline(always)] + pub const fn clk_gmac0_ptp(&self) -> &CLK_GMAC0_PTP { + &self.clk_gmac0_ptp + } #[doc = "0x1b8 - Clock GMAC PHY"] - pub clk_gmac_phy: CLK_GMAC_PHY, + #[inline(always)] + pub const fn clk_gmac_phy(&self) -> &CLK_GMAC_PHY { + &self.clk_gmac_phy + } #[doc = "0x1bc - Clock GMAC 0 GTXC"] - pub clk_gmac0_gtxclk: CLK_GMAC0_GTXCLK, + #[inline(always)] + pub const fn clk_gmac0_gtxclk(&self) -> &CLK_GMAC0_GTXCLK { + &self.clk_gmac0_gtxclk + } #[doc = "0x1c0 - Clock SYS IOMUX PCLK"] - pub clk_sys_iomux_pclk: CLK_SYS_IOMUX_PCLK, + #[inline(always)] + pub const fn clk_sys_iomux_pclk(&self) -> &CLK_SYS_IOMUX_PCLK { + &self.clk_sys_iomux_pclk + } #[doc = "0x1c4 - Clock Mailbox APB"] - pub clk_mbox_apb: CLK_MBOX_APB, + #[inline(always)] + pub const fn clk_mbox_apb(&self) -> &CLK_MBOX_APB { + &self.clk_mbox_apb + } #[doc = "0x1c8 - Clock Internal Controller APB"] - pub clk_internal_ctrl_apb: CLK_INTERNAL_CTRL_APB, + #[inline(always)] + pub const fn clk_internal_ctrl_apb(&self) -> &CLK_INTERNAL_CTRL_APB { + &self.clk_internal_ctrl_apb + } #[doc = "0x1cc - U0 Clock CAN Controller APB"] - pub clk_u0_can_ctrl_apb: CLK_U0_CAN_CTRL_APB, + #[inline(always)] + pub const fn clk_u0_can_ctrl_apb(&self) -> &CLK_U0_CAN_CTRL_APB { + &self.clk_u0_can_ctrl_apb + } #[doc = "0x1d0 - U0 Clock CAN Controller Timer"] - pub clk_u0_can_ctrl_tim: CLK_U0_CAN_CTRL_TIM, + #[inline(always)] + pub const fn clk_u0_can_ctrl_tim(&self) -> &CLK_U0_CAN_CTRL_TIM { + &self.clk_u0_can_ctrl_tim + } #[doc = "0x1d4 - U0 Clock CAN Controller CAN"] - pub clk_u0_can_ctrl_can: CLK_U0_CAN_CTRL_CAN, + #[inline(always)] + pub const fn clk_u0_can_ctrl_can(&self) -> &CLK_U0_CAN_CTRL_CAN { + &self.clk_u0_can_ctrl_can + } #[doc = "0x1d8 - U1 Clock CAN Controller APB"] - pub clk_u1_can_ctrl_apb: CLK_U1_CAN_CTRL_APB, + #[inline(always)] + pub const fn clk_u1_can_ctrl_apb(&self) -> &CLK_U1_CAN_CTRL_APB { + &self.clk_u1_can_ctrl_apb + } #[doc = "0x1dc - U1 Clock CAN Controller Timer"] - pub clk_u1_can_ctrl_tim: CLK_U1_CAN_CTRL_TIM, + #[inline(always)] + pub const fn clk_u1_can_ctrl_tim(&self) -> &CLK_U1_CAN_CTRL_TIM { + &self.clk_u1_can_ctrl_tim + } #[doc = "0x1e0 - U1 Clock CAN Controller CAN"] - pub clk_u1_can_ctrl_can: CLK_U1_CAN_CTRL_CAN, + #[inline(always)] + pub const fn clk_u1_can_ctrl_can(&self) -> &CLK_U1_CAN_CTRL_CAN { + &self.clk_u1_can_ctrl_can + } #[doc = "0x1e4 - Clock PWM APB"] - pub clk_pwm_apb: CLK_PWM_APB, + #[inline(always)] + pub const fn clk_pwm_apb(&self) -> &CLK_PWM_APB { + &self.clk_pwm_apb + } #[doc = "0x1e8 - Clock WDT APB"] - pub clk_wdt_apb: CLK_WDT_APB, + #[inline(always)] + pub const fn clk_wdt_apb(&self) -> &CLK_WDT_APB { + &self.clk_wdt_apb + } #[doc = "0x1ec - Clock WDT"] - pub clk_wdt: CLK_WDT, + #[inline(always)] + pub const fn clk_wdt(&self) -> &CLK_WDT { + &self.clk_wdt + } #[doc = "0x1f0 - Clock Timer APB"] - pub clk_tim_apb: CLK_TIM_APB, + #[inline(always)] + pub const fn clk_tim_apb(&self) -> &CLK_TIM_APB { + &self.clk_tim_apb + } #[doc = "0x1f4 - Clock Timer 0"] - pub clk_tim0: CLK_TIM0, + #[inline(always)] + pub const fn clk_tim0(&self) -> &CLK_TIM0 { + &self.clk_tim0 + } #[doc = "0x1f8 - Clock Timer 1"] - pub clk_tim1: CLK_TIM1, + #[inline(always)] + pub const fn clk_tim1(&self) -> &CLK_TIM1 { + &self.clk_tim1 + } #[doc = "0x1fc - Clock Timer 2"] - pub clk_tim2: CLK_TIM2, + #[inline(always)] + pub const fn clk_tim2(&self) -> &CLK_TIM2 { + &self.clk_tim2 + } #[doc = "0x200 - Clock Timer 3"] - pub clk_tim3: CLK_TIM3, + #[inline(always)] + pub const fn clk_tim3(&self) -> &CLK_TIM3 { + &self.clk_tim3 + } #[doc = "0x204 - Clock Temperature Sensor APB"] - pub clk_temp_sensor_apb: CLK_TEMP_SENSOR_APB, + #[inline(always)] + pub const fn clk_temp_sensor_apb(&self) -> &CLK_TEMP_SENSOR_APB { + &self.clk_temp_sensor_apb + } #[doc = "0x208 - Clock Temperature Sensor"] - pub clk_temp_sensor: CLK_TEMP_SENSOR, + #[inline(always)] + pub const fn clk_temp_sensor(&self) -> &CLK_TEMP_SENSOR { + &self.clk_temp_sensor + } #[doc = "0x20c - U0 Clock SPI APB"] - pub clk_u0_spi_apb: CLK_U0_SPI_APB, + #[inline(always)] + pub const fn clk_u0_spi_apb(&self) -> &CLK_U0_SPI_APB { + &self.clk_u0_spi_apb + } #[doc = "0x210 - U1 Clock SPI APB"] - pub clk_u1_spi_apb: CLK_U1_SPI_APB, + #[inline(always)] + pub const fn clk_u1_spi_apb(&self) -> &CLK_U1_SPI_APB { + &self.clk_u1_spi_apb + } #[doc = "0x214 - U2 Clock SPI APB"] - pub clk_u2_spi_apb: CLK_U2_SPI_APB, + #[inline(always)] + pub const fn clk_u2_spi_apb(&self) -> &CLK_U2_SPI_APB { + &self.clk_u2_spi_apb + } #[doc = "0x218 - U3 Clock SPI APB"] - pub clk_u3_spi_apb: CLK_U3_SPI_APB, + #[inline(always)] + pub const fn clk_u3_spi_apb(&self) -> &CLK_U3_SPI_APB { + &self.clk_u3_spi_apb + } #[doc = "0x21c - U4 Clock SPI APB"] - pub clk_u4_spi_apb: CLK_U4_SPI_APB, + #[inline(always)] + pub const fn clk_u4_spi_apb(&self) -> &CLK_U4_SPI_APB { + &self.clk_u4_spi_apb + } #[doc = "0x220 - U5 Clock SPI APB"] - pub clk_u5_spi_apb: CLK_U5_SPI_APB, + #[inline(always)] + pub const fn clk_u5_spi_apb(&self) -> &CLK_U5_SPI_APB { + &self.clk_u5_spi_apb + } #[doc = "0x224 - U6 Clock SPI APB"] - pub clk_u6_spi_apb: CLK_U6_SPI_APB, + #[inline(always)] + pub const fn clk_u6_spi_apb(&self) -> &CLK_U6_SPI_APB { + &self.clk_u6_spi_apb + } #[doc = "0x228 - U0 Clock I2C APB"] - pub clk_u0_i2c_apb: CLK_U0_I2C_APB, + #[inline(always)] + pub const fn clk_u0_i2c_apb(&self) -> &CLK_U0_I2C_APB { + &self.clk_u0_i2c_apb + } #[doc = "0x22c - U1 Clock I2C APB"] - pub clk_u1_i2c_apb: CLK_U1_I2C_APB, + #[inline(always)] + pub const fn clk_u1_i2c_apb(&self) -> &CLK_U1_I2C_APB { + &self.clk_u1_i2c_apb + } #[doc = "0x230 - U2 Clock I2C APB"] - pub clk_u2_i2c_apb: CLK_U2_I2C_APB, + #[inline(always)] + pub const fn clk_u2_i2c_apb(&self) -> &CLK_U2_I2C_APB { + &self.clk_u2_i2c_apb + } #[doc = "0x234 - U3 Clock I2C APB"] - pub clk_u3_i2c_apb: CLK_U3_I2C_APB, + #[inline(always)] + pub const fn clk_u3_i2c_apb(&self) -> &CLK_U3_I2C_APB { + &self.clk_u3_i2c_apb + } #[doc = "0x238 - U4 Clock I2C APB"] - pub clk_u4_i2c_apb: CLK_U4_I2C_APB, + #[inline(always)] + pub const fn clk_u4_i2c_apb(&self) -> &CLK_U4_I2C_APB { + &self.clk_u4_i2c_apb + } #[doc = "0x23c - U5 Clock I2C APB"] - pub clk_u5_i2c_apb: CLK_U5_I2C_APB, + #[inline(always)] + pub const fn clk_u5_i2c_apb(&self) -> &CLK_U5_I2C_APB { + &self.clk_u5_i2c_apb + } #[doc = "0x240 - U6 Clock I2C APB"] - pub clk_u6_i2c_apb: CLK_U6_I2C_APB, + #[inline(always)] + pub const fn clk_u6_i2c_apb(&self) -> &CLK_U6_I2C_APB { + &self.clk_u6_i2c_apb + } #[doc = "0x244 - U0 Clock UART APB"] - pub clk_u0_uart_apb: CLK_U0_UART_APB, + #[inline(always)] + pub const fn clk_u0_uart_apb(&self) -> &CLK_U0_UART_APB { + &self.clk_u0_uart_apb + } #[doc = "0x248 - U0 Clock UART Core"] - pub clk_u0_uart_core: CLK_U0_UART_CORE, + #[inline(always)] + pub const fn clk_u0_uart_core(&self) -> &CLK_U0_UART_CORE { + &self.clk_u0_uart_core + } #[doc = "0x24c - U1 Clock UART APB"] - pub clk_u1_uart_apb: CLK_U1_UART_APB, + #[inline(always)] + pub const fn clk_u1_uart_apb(&self) -> &CLK_U1_UART_APB { + &self.clk_u1_uart_apb + } #[doc = "0x250 - U1 Clock UART Core"] - pub clk_u1_uart_core: CLK_U1_UART_CORE, + #[inline(always)] + pub const fn clk_u1_uart_core(&self) -> &CLK_U1_UART_CORE { + &self.clk_u1_uart_core + } #[doc = "0x254 - U2 Clock UART APB"] - pub clk_u2_uart_apb: CLK_U2_UART_APB, + #[inline(always)] + pub const fn clk_u2_uart_apb(&self) -> &CLK_U2_UART_APB { + &self.clk_u2_uart_apb + } #[doc = "0x258 - U2 Clock UART Core"] - pub clk_u2_uart_core: CLK_U2_UART_CORE, + #[inline(always)] + pub const fn clk_u2_uart_core(&self) -> &CLK_U2_UART_CORE { + &self.clk_u2_uart_core + } #[doc = "0x25c - U3 Clock UART APB"] - pub clk_u3_uart_apb: CLK_U3_UART_APB, + #[inline(always)] + pub const fn clk_u3_uart_apb(&self) -> &CLK_U3_UART_APB { + &self.clk_u3_uart_apb + } #[doc = "0x260 - U3 Clock UART Core"] - pub clk_u3_uart_core: CLK_U3_UART_CORE, + #[inline(always)] + pub const fn clk_u3_uart_core(&self) -> &CLK_U3_UART_CORE { + &self.clk_u3_uart_core + } #[doc = "0x264 - U4 Clock UART APB"] - pub clk_u4_uart_apb: CLK_U4_UART_APB, + #[inline(always)] + pub const fn clk_u4_uart_apb(&self) -> &CLK_U4_UART_APB { + &self.clk_u4_uart_apb + } #[doc = "0x268 - U4 Clock UART Core"] - pub clk_u4_uart_core: CLK_U4_UART_CORE, + #[inline(always)] + pub const fn clk_u4_uart_core(&self) -> &CLK_U4_UART_CORE { + &self.clk_u4_uart_core + } #[doc = "0x26c - U5 Clock UART APB"] - pub clk_u5_uart_apb: CLK_U5_UART_APB, + #[inline(always)] + pub const fn clk_u5_uart_apb(&self) -> &CLK_U5_UART_APB { + &self.clk_u5_uart_apb + } #[doc = "0x270 - U5 Clock UART Core"] - pub clk_u5_uart_core: CLK_U5_UART_CORE, + #[inline(always)] + pub const fn clk_u5_uart_core(&self) -> &CLK_U5_UART_CORE { + &self.clk_u5_uart_core + } #[doc = "0x274 - Clock PWMDAC APB"] - pub clk_pwmdac_apb: CLK_PWMDAC_APB, + #[inline(always)] + pub const fn clk_pwmdac_apb(&self) -> &CLK_PWMDAC_APB { + &self.clk_pwmdac_apb + } #[doc = "0x278 - Clock PWMDAC Core"] - pub clk_pwmdac_core: CLK_PWMDAC_CORE, + #[inline(always)] + pub const fn clk_pwmdac_core(&self) -> &CLK_PWMDAC_CORE { + &self.clk_pwmdac_core + } #[doc = "0x27c - Clock SPDIF APB"] - pub clk_spdif_apb: CLK_SPDIF_APB, + #[inline(always)] + pub const fn clk_spdif_apb(&self) -> &CLK_SPDIF_APB { + &self.clk_spdif_apb + } #[doc = "0x280 - Clock SPDIF Core"] - pub clk_spdif_core: CLK_SPDIF_CORE, + #[inline(always)] + pub const fn clk_spdif_core(&self) -> &CLK_SPDIF_CORE { + &self.clk_spdif_core + } #[doc = "0x284 - U0 Clock I2S TX APB"] - pub clk_u0_i2s_tx_apb: CLK_U0_I2S_TX_APB, + #[inline(always)] + pub const fn clk_u0_i2s_tx_apb(&self) -> &CLK_U0_I2S_TX_APB { + &self.clk_u0_i2s_tx_apb + } #[doc = "0x288 - U0 Clock I2S TX 0 BCLK MST"] - pub clk_u0_i2stx_4ch0_bclk_mst: CLK_U0_I2STX_4CH0_BCLK_MST, + #[inline(always)] + pub const fn clk_u0_i2stx_4ch0_bclk_mst(&self) -> &CLK_U0_I2STX_4CH0_BCLK_MST { + &self.clk_u0_i2stx_4ch0_bclk_mst + } #[doc = "0x28c - U0 Clock I2S TX 0 BCLK MST Inverter"] - pub clk_u0_i2stx_4ch0_bclk_mst_inv: CLK_U0_I2STX_4CH0_BCLK_MST_INV, + #[inline(always)] + pub const fn clk_u0_i2stx_4ch0_bclk_mst_inv(&self) -> &CLK_U0_I2STX_4CH0_BCLK_MST_INV { + &self.clk_u0_i2stx_4ch0_bclk_mst_inv + } #[doc = "0x290 - Clock I2S TX 0 LRCK MST"] - pub clk_i2stx0_lrck_mst: CLK_I2STX0_LRCK_MST, + #[inline(always)] + pub const fn clk_i2stx0_lrck_mst(&self) -> &CLK_I2STX0_LRCK_MST { + &self.clk_i2stx0_lrck_mst + } #[doc = "0x294 - U0 Clock I2S TX BCLK"] - pub clk_u0_i2stx_bclk: CLK_U0_I2STX_BCLK, + #[inline(always)] + pub const fn clk_u0_i2stx_bclk(&self) -> &CLK_U0_I2STX_BCLK { + &self.clk_u0_i2stx_bclk + } #[doc = "0x298 - U0 Clock I2S TX BCLK Negative"] - pub clk_u0_i2stx_bclk_neg: CLK_U0_I2STX_BCLK_NEG, + #[inline(always)] + pub const fn clk_u0_i2stx_bclk_neg(&self) -> &CLK_U0_I2STX_BCLK_NEG { + &self.clk_u0_i2stx_bclk_neg + } #[doc = "0x29c - U0 Clock I2S TX LRCK"] - pub clk_u0_i2stx_lrck: CLK_U0_I2STX_LRCK, + #[inline(always)] + pub const fn clk_u0_i2stx_lrck(&self) -> &CLK_U0_I2STX_LRCK { + &self.clk_u0_i2stx_lrck + } #[doc = "0x2a0 - U1 Clock I2S TX APB"] - pub clk_u1_i2s_tx_apb: CLK_U1_I2S_TX_APB, + #[inline(always)] + pub const fn clk_u1_i2s_tx_apb(&self) -> &CLK_U1_I2S_TX_APB { + &self.clk_u1_i2s_tx_apb + } #[doc = "0x2a4 - U1 Clock I2S TX 1 BCLK MST"] - pub clk_u1_i2stx_4ch1_bclk_mst: CLK_U1_I2STX_4CH1_BCLK_MST, + #[inline(always)] + pub const fn clk_u1_i2stx_4ch1_bclk_mst(&self) -> &CLK_U1_I2STX_4CH1_BCLK_MST { + &self.clk_u1_i2stx_4ch1_bclk_mst + } #[doc = "0x2a8 - U1 Clock I2S TX 1 BCLK MST Inverter"] - pub clk_u1_i2stx_4ch1_bclk_mst_inv: CLK_U1_I2STX_4CH1_BCLK_MST_INV, + #[inline(always)] + pub const fn clk_u1_i2stx_4ch1_bclk_mst_inv(&self) -> &CLK_U1_I2STX_4CH1_BCLK_MST_INV { + &self.clk_u1_i2stx_4ch1_bclk_mst_inv + } #[doc = "0x2ac - Clock I2S TX 1 LRCK MST"] - pub clk_i2stx1_lrck_mst: CLK_I2STX1_LRCK_MST, + #[inline(always)] + pub const fn clk_i2stx1_lrck_mst(&self) -> &CLK_I2STX1_LRCK_MST { + &self.clk_i2stx1_lrck_mst + } #[doc = "0x2b0 - U1 Clock I2S TX BCLK"] - pub clk_u1_i2stx_bclk: CLK_U1_I2STX_BCLK, + #[inline(always)] + pub const fn clk_u1_i2stx_bclk(&self) -> &CLK_U1_I2STX_BCLK { + &self.clk_u1_i2stx_bclk + } #[doc = "0x2b4 - U1 Clock I2S TX BCLK Negative"] - pub clk_u1_i2stx_bclk_neg: CLK_U1_I2STX_BCLK_NEG, + #[inline(always)] + pub const fn clk_u1_i2stx_bclk_neg(&self) -> &CLK_U1_I2STX_BCLK_NEG { + &self.clk_u1_i2stx_bclk_neg + } #[doc = "0x2b8 - U1 Clock I2S TX LRCK"] - pub clk_u1_i2stx_lrck: CLK_U1_I2STX_LRCK, + #[inline(always)] + pub const fn clk_u1_i2stx_lrck(&self) -> &CLK_U1_I2STX_LRCK { + &self.clk_u1_i2stx_lrck + } #[doc = "0x2bc - Clock I2S APB"] - pub clk_i2s_apb: CLK_I2S_APB, + #[inline(always)] + pub const fn clk_i2s_apb(&self) -> &CLK_I2S_APB { + &self.clk_i2s_apb + } #[doc = "0x2c0 - Clock I2S BCLK MST"] - pub clk_i2s_bclk_mst: CLK_I2S_BCLK_MST, + #[inline(always)] + pub const fn clk_i2s_bclk_mst(&self) -> &CLK_I2S_BCLK_MST { + &self.clk_i2s_bclk_mst + } #[doc = "0x2c4 - Clock I2S BCLK MST Inverter"] - pub clk_i2s_bclk_mst_inv: CLK_I2S_BCLK_MST_INV, + #[inline(always)] + pub const fn clk_i2s_bclk_mst_inv(&self) -> &CLK_I2S_BCLK_MST_INV { + &self.clk_i2s_bclk_mst_inv + } #[doc = "0x2c8 - Clock I2S LRCK MST"] - pub clk_i2s_lrck_mst: CLK_I2S_LRCK_MST, + #[inline(always)] + pub const fn clk_i2s_lrck_mst(&self) -> &CLK_I2S_LRCK_MST { + &self.clk_i2s_lrck_mst + } #[doc = "0x2cc - Clock I2S BCLK"] - pub clk_i2s_bclk: CLK_I2S_BCLK, + #[inline(always)] + pub const fn clk_i2s_bclk(&self) -> &CLK_I2S_BCLK { + &self.clk_i2s_bclk + } #[doc = "0x2d0 - Clock I2S BCLK Negative"] - pub clk_i2s_bclk_neg: CLK_I2S_BCLK_NEG, + #[inline(always)] + pub const fn clk_i2s_bclk_neg(&self) -> &CLK_I2S_BCLK_NEG { + &self.clk_i2s_bclk_neg + } #[doc = "0x2d4 - Clock I2S LRCK"] - pub clk_i2s_lrck: CLK_I2S_LRCK, + #[inline(always)] + pub const fn clk_i2s_lrck(&self) -> &CLK_I2S_LRCK { + &self.clk_i2s_lrck + } #[doc = "0x2d8 - Clock PDM DMIC"] - pub clk_pdm_dmic: CLK_PDM_DMIC, + #[inline(always)] + pub const fn clk_pdm_dmic(&self) -> &CLK_PDM_DMIC { + &self.clk_pdm_dmic + } #[doc = "0x2dc - Clock PDM APB"] - pub clk_pdm_apb: CLK_PDM_APB, + #[inline(always)] + pub const fn clk_pdm_apb(&self) -> &CLK_PDM_APB { + &self.clk_pdm_apb + } #[doc = "0x2e0 - Clock TDM AHB"] - pub clk_tdm_ahb: CLK_TDM_AHB, + #[inline(always)] + pub const fn clk_tdm_ahb(&self) -> &CLK_TDM_AHB { + &self.clk_tdm_ahb + } #[doc = "0x2e4 - Clock TDM APB"] - pub clk_tdm_apb: CLK_TDM_APB, + #[inline(always)] + pub const fn clk_tdm_apb(&self) -> &CLK_TDM_APB { + &self.clk_tdm_apb + } #[doc = "0x2e8 - Clock TDM Internal"] - pub clk_tdm_internal: CLK_TDM_INTERNAL, + #[inline(always)] + pub const fn clk_tdm_internal(&self) -> &CLK_TDM_INTERNAL { + &self.clk_tdm_internal + } #[doc = "0x2ec - Clock TDM"] - pub clk_tdm: CLK_TDM, + #[inline(always)] + pub const fn clk_tdm(&self) -> &CLK_TDM { + &self.clk_tdm + } #[doc = "0x2f0 - Clock TDM Negative"] - pub clk_tdm_neg: CLK_TDM_NEG, + #[inline(always)] + pub const fn clk_tdm_neg(&self) -> &CLK_TDM_NEG { + &self.clk_tdm_neg + } #[doc = "0x2f4 - Clock JTAG Certification TRNG"] - pub clk_jtag_cert_trng: CLK_JTAG_CERT_TRNG, + #[inline(always)] + pub const fn clk_jtag_cert_trng(&self) -> &CLK_JTAG_CERT_TRNG { + &self.clk_jtag_cert_trng + } #[doc = "0x2f8 - Software RESET 0 Address Selector"] - pub soft_rst0_addr_sel: SOFT_RST0_ADDR_SEL, + #[inline(always)] + pub const fn soft_rst0_addr_sel(&self) -> &SOFT_RST0_ADDR_SEL { + &self.soft_rst0_addr_sel + } #[doc = "0x2fc - Software RESET 1 Address Selector"] - pub soft_rst1_addr_sel: SOFT_RST1_ADDR_SEL, + #[inline(always)] + pub const fn soft_rst1_addr_sel(&self) -> &SOFT_RST1_ADDR_SEL { + &self.soft_rst1_addr_sel + } #[doc = "0x300 - Software RESET 2 Address Selector"] - pub soft_rst2_addr_sel: SOFT_RST2_ADDR_SEL, + #[inline(always)] + pub const fn soft_rst2_addr_sel(&self) -> &SOFT_RST2_ADDR_SEL { + &self.soft_rst2_addr_sel + } #[doc = "0x304 - Software RESET 3 Address Selector"] - pub soft_rst3_addr_sel: SOFT_RST3_ADDR_SEL, + #[inline(always)] + pub const fn soft_rst3_addr_sel(&self) -> &SOFT_RST3_ADDR_SEL { + &self.soft_rst3_addr_sel + } #[doc = "0x308 - SYSCRG RESET Status 0"] - pub syscrg_rst0_status: SYSCRG_RST0_STATUS, + #[inline(always)] + pub const fn syscrg_rst0_status(&self) -> &SYSCRG_RST0_STATUS { + &self.syscrg_rst0_status + } #[doc = "0x30c - SYSCRG RESET Status 1"] - pub syscrg_rst1_status: SYSCRG_RST1_STATUS, + #[inline(always)] + pub const fn syscrg_rst1_status(&self) -> &SYSCRG_RST1_STATUS { + &self.syscrg_rst1_status + } #[doc = "0x310 - SYSCRG RESET Status 2"] - pub syscrg_rst2_status: SYSCRG_RST2_STATUS, + #[inline(always)] + pub const fn syscrg_rst2_status(&self) -> &SYSCRG_RST2_STATUS { + &self.syscrg_rst2_status + } #[doc = "0x314 - SYSCRG RESET Status 3"] - pub syscrg_rst3_status: SYSCRG_RST3_STATUS, + #[inline(always)] + pub const fn syscrg_rst3_status(&self) -> &SYSCRG_RST3_STATUS { + &self.syscrg_rst3_status + } } -#[doc = "clk_cpu_root (rw) register accessor: Clock CPU Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cpu_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cpu_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_cpu_root`] +#[doc = "clk_cpu_root (rw) register accessor: Clock CPU Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cpu_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cpu_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_cpu_root`] module"] pub type CLK_CPU_ROOT = crate::Reg; #[doc = "Clock CPU Root"] pub mod clk_cpu_root; -#[doc = "clk_cpu_core (rw) register accessor: Clock CPU Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cpu_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cpu_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_cpu_core`] +#[doc = "clk_cpu_core (rw) register accessor: Clock CPU Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cpu_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cpu_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_cpu_core`] module"] pub type CLK_CPU_CORE = crate::Reg; #[doc = "Clock CPU Core"] pub mod clk_cpu_core; -#[doc = "clk_cpu_bus (rw) register accessor: Clock CPU Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cpu_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cpu_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_cpu_bus`] +#[doc = "clk_cpu_bus (rw) register accessor: Clock CPU Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cpu_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cpu_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_cpu_bus`] module"] pub type CLK_CPU_BUS = crate::Reg; #[doc = "Clock CPU Bus"] pub mod clk_cpu_bus; -#[doc = "clk_gpu_root (rw) register accessor: Clock GPU Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gpu_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpu_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gpu_root`] +#[doc = "clk_gpu_root (rw) register accessor: Clock GPU Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gpu_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpu_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gpu_root`] module"] pub type CLK_GPU_ROOT = crate::Reg; #[doc = "Clock GPU Root"] pub mod clk_gpu_root; -#[doc = "clk_peripheral_root (rw) register accessor: Clock Peripheral Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_peripheral_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_peripheral_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_peripheral_root`] +#[doc = "clk_peripheral_root (rw) register accessor: Clock Peripheral Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_peripheral_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_peripheral_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_peripheral_root`] module"] pub type CLK_PERIPHERAL_ROOT = crate::Reg; #[doc = "Clock Peripheral Root"] pub mod clk_peripheral_root; -#[doc = "clk_bus_root (rw) register accessor: Clock Bus Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_bus_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_bus_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_bus_root`] +#[doc = "clk_bus_root (rw) register accessor: Clock Bus Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_bus_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_bus_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_bus_root`] module"] pub type CLK_BUS_ROOT = crate::Reg; #[doc = "Clock Bus Root"] pub mod clk_bus_root; -#[doc = "clk_nocstg_bus (rw) register accessor: Clock NOCSTG Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_nocstg_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_nocstg_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_nocstg_bus`] +#[doc = "clk_nocstg_bus (rw) register accessor: Clock NOCSTG Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_nocstg_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_nocstg_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_nocstg_bus`] module"] pub type CLK_NOCSTG_BUS = crate::Reg; #[doc = "Clock NOCSTG Bus"] pub mod clk_nocstg_bus; -#[doc = "clk_axi_cfg0 (rw) register accessor: Clock AXI Configuration 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_cfg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_axi_cfg0`] +#[doc = "clk_axi_cfg0 (rw) register accessor: Clock AXI Configuration 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_cfg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_axi_cfg0`] module"] pub type CLK_AXI_CFG0 = crate::Reg; #[doc = "Clock AXI Configuration 0"] pub mod clk_axi_cfg0; -#[doc = "clk_stg_axiahb (rw) register accessor: Clock STG AXI AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_axiahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_axiahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_stg_axiahb`] +#[doc = "clk_stg_axiahb (rw) register accessor: Clock STG AXI AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_axiahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_axiahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_stg_axiahb`] module"] pub type CLK_STG_AXIAHB = crate::Reg; #[doc = "Clock STG AXI AHB"] pub mod clk_stg_axiahb; -#[doc = "clk_ahb0 (rw) register accessor: Clock AHB 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ahb0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ahb0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_ahb0`] +#[doc = "clk_ahb0 (rw) register accessor: Clock AHB 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ahb0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ahb0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_ahb0`] module"] pub type CLK_AHB0 = crate::Reg; #[doc = "Clock AHB 0"] pub mod clk_ahb0; -#[doc = "clk_ahb1 (rw) register accessor: Clock AHB 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ahb1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ahb1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_ahb1`] +#[doc = "clk_ahb1 (rw) register accessor: Clock AHB 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ahb1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ahb1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_ahb1`] module"] pub type CLK_AHB1 = crate::Reg; #[doc = "Clock AHB 1"] pub mod clk_ahb1; -#[doc = "clk_apb_bus (rw) register accessor: Clock APB Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_apb_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_apb_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_apb_bus`] +#[doc = "clk_apb_bus (rw) register accessor: Clock APB Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_apb_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_apb_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_apb_bus`] module"] pub type CLK_APB_BUS = crate::Reg; #[doc = "Clock APB Bus"] pub mod clk_apb_bus; -#[doc = "clk_apb0 (rw) register accessor: Clock APB 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_apb0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_apb0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_apb0`] +#[doc = "clk_apb0 (rw) register accessor: Clock APB 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_apb0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_apb0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_apb0`] module"] pub type CLK_APB0 = crate::Reg; #[doc = "Clock APB 0"] pub mod clk_apb0; -#[doc = "clk_pll0_div2 (rw) register accessor: Clock PLL 0 Divider 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll0_div2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll0_div2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pll0_div2`] +#[doc = "clk_pll0_div2 (rw) register accessor: Clock PLL 0 Divider 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll0_div2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll0_div2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pll0_div2`] module"] pub type CLK_PLL0_DIV2 = crate::Reg; #[doc = "Clock PLL 0 Divider 2"] pub mod clk_pll0_div2; -#[doc = "clk_pll1_div2 (rw) register accessor: Clock PLL 1 Divider 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll1_div2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll1_div2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pll1_div2`] +#[doc = "clk_pll1_div2 (rw) register accessor: Clock PLL 1 Divider 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll1_div2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll1_div2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pll1_div2`] module"] pub type CLK_PLL1_DIV2 = crate::Reg; #[doc = "Clock PLL 1 Divider 2"] pub mod clk_pll1_div2; -#[doc = "clk_pll2_div2 (rw) register accessor: Clock PLL 2 Divider 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll2_div2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll2_div2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pll2_div2`] +#[doc = "clk_pll2_div2 (rw) register accessor: Clock PLL 2 Divider 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll2_div2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll2_div2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pll2_div2`] module"] pub type CLK_PLL2_DIV2 = crate::Reg; #[doc = "Clock PLL 2 Divider 2"] pub mod clk_pll2_div2; -#[doc = "clk_audio_root (rw) register accessor: Clock Audio Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_audio_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_audio_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_audio_root`] +#[doc = "clk_audio_root (rw) register accessor: Clock Audio Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_audio_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_audio_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_audio_root`] module"] pub type CLK_AUDIO_ROOT = crate::Reg; #[doc = "Clock Audio Root"] pub mod clk_audio_root; -#[doc = "clk_mclk_inner (rw) register accessor: Clock MCLK Inner\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_mclk_inner::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_mclk_inner::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_mclk_inner`] +#[doc = "clk_mclk_inner (rw) register accessor: Clock MCLK Inner\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_mclk_inner::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_mclk_inner::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_mclk_inner`] module"] pub type CLK_MCLK_INNER = crate::Reg; #[doc = "Clock MCLK Inner"] pub mod clk_mclk_inner; -#[doc = "clk_mclk (rw) register accessor: Clock MCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_mclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_mclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_mclk`] +#[doc = "clk_mclk (rw) register accessor: Clock MCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_mclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_mclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_mclk`] module"] pub type CLK_MCLK = crate::Reg; #[doc = "Clock MCLK"] pub mod clk_mclk; -#[doc = "clk_mclk_out (rw) register accessor: Clock MCLK Out\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_mclk_out::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_mclk_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_mclk_out`] +#[doc = "clk_mclk_out (rw) register accessor: Clock MCLK Out\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_mclk_out::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_mclk_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_mclk_out`] module"] pub type CLK_MCLK_OUT = crate::Reg; #[doc = "Clock MCLK Out"] pub mod clk_mclk_out; -#[doc = "clk_isp_2x (rw) register accessor: Clock ISP 2x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_isp_2x::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_isp_2x::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_isp_2x`] +#[doc = "clk_isp_2x (rw) register accessor: Clock ISP 2x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_isp_2x::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_isp_2x::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_isp_2x`] module"] pub type CLK_ISP_2X = crate::Reg; #[doc = "Clock ISP 2x"] pub mod clk_isp_2x; -#[doc = "clk_isp_axi (rw) register accessor: Clock ISP AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_isp_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_isp_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_isp_axi`] +#[doc = "clk_isp_axi (rw) register accessor: Clock ISP AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_isp_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_isp_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_isp_axi`] module"] pub type CLK_ISP_AXI = crate::Reg; #[doc = "Clock ISP AXI"] pub mod clk_isp_axi; -#[doc = "clk_gclk0 (rw) register accessor: Clock GCLK 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gclk0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gclk0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gclk0`] +#[doc = "clk_gclk0 (rw) register accessor: Clock GCLK 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gclk0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gclk0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gclk0`] module"] pub type CLK_GCLK0 = crate::Reg; #[doc = "Clock GCLK 0"] pub mod clk_gclk0; -#[doc = "clk_gclk1 (rw) register accessor: Clock GCLK 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gclk1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gclk1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gclk1`] +#[doc = "clk_gclk1 (rw) register accessor: Clock GCLK 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gclk1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gclk1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gclk1`] module"] pub type CLK_GCLK1 = crate::Reg; #[doc = "Clock GCLK 1"] pub mod clk_gclk1; -#[doc = "clk_gclk2 (rw) register accessor: Clock GCLK 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gclk2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gclk2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gclk2`] +#[doc = "clk_gclk2 (rw) register accessor: Clock GCLK 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gclk2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gclk2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gclk2`] module"] pub type CLK_GCLK2 = crate::Reg; #[doc = "Clock GCLK 2"] pub mod clk_gclk2; -#[doc = "clk_u7mc_core0 (rw) register accessor: U7MC Core Clock 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_core0`] +#[doc = "clk_u7mc_core0 (rw) register accessor: U7MC Core Clock 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_core0`] module"] pub type CLK_U7MC_CORE0 = crate::Reg; #[doc = "U7MC Core Clock 0"] pub mod clk_u7mc_core0; -#[doc = "clk_u7mc_core1 (rw) register accessor: U7MC Core Clock 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_core1`] +#[doc = "clk_u7mc_core1 (rw) register accessor: U7MC Core Clock 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_core1`] module"] pub type CLK_U7MC_CORE1 = crate::Reg; #[doc = "U7MC Core Clock 1"] pub mod clk_u7mc_core1; -#[doc = "clk_u7mc_core2 (rw) register accessor: U7MC Core Clock 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_core2`] +#[doc = "clk_u7mc_core2 (rw) register accessor: U7MC Core Clock 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_core2`] module"] pub type CLK_U7MC_CORE2 = crate::Reg; #[doc = "U7MC Core Clock 2"] pub mod clk_u7mc_core2; -#[doc = "clk_u7mc_core3 (rw) register accessor: U7MC Core Clock 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_core3`] +#[doc = "clk_u7mc_core3 (rw) register accessor: U7MC Core Clock 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_core3`] module"] pub type CLK_U7MC_CORE3 = crate::Reg; #[doc = "U7MC Core Clock 3"] pub mod clk_u7mc_core3; -#[doc = "clk_u7mc_core4 (rw) register accessor: U7MC Core Clock 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_core4`] +#[doc = "clk_u7mc_core4 (rw) register accessor: U7MC Core Clock 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_core4`] module"] pub type CLK_U7MC_CORE4 = crate::Reg; #[doc = "U7MC Core Clock 4"] pub mod clk_u7mc_core4; -#[doc = "clk_u7mc_debug (rw) register accessor: U7MC Debug Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_debug::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_debug::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_debug`] +#[doc = "clk_u7mc_debug (rw) register accessor: U7MC Debug Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_debug::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_debug::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_debug`] module"] pub type CLK_U7MC_DEBUG = crate::Reg; #[doc = "U7MC Debug Clock"] pub mod clk_u7mc_debug; -#[doc = "u7mc_rtc_toggle (rw) register accessor: U7MC RTC Toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u7mc_rtc_toggle::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u7mc_rtc_toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`u7mc_rtc_toggle`] +#[doc = "u7mc_rtc_toggle (rw) register accessor: U7MC RTC Toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u7mc_rtc_toggle::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u7mc_rtc_toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@u7mc_rtc_toggle`] module"] pub type U7MC_RTC_TOGGLE = crate::Reg; #[doc = "U7MC RTC Toggle"] pub mod u7mc_rtc_toggle; -#[doc = "clk_u7mc_trace0 (rw) register accessor: U7MC Trace Clock 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_trace0`] +#[doc = "clk_u7mc_trace0 (rw) register accessor: U7MC Trace Clock 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_trace0`] module"] pub type CLK_U7MC_TRACE0 = crate::Reg; #[doc = "U7MC Trace Clock 0"] pub mod clk_u7mc_trace0; -#[doc = "clk_u7mc_trace1 (rw) register accessor: U7MC Trace Clock 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_trace1`] +#[doc = "clk_u7mc_trace1 (rw) register accessor: U7MC Trace Clock 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_trace1`] module"] pub type CLK_U7MC_TRACE1 = crate::Reg; #[doc = "U7MC Trace Clock 1"] pub mod clk_u7mc_trace1; -#[doc = "clk_u7mc_trace2 (rw) register accessor: U7MC Trace Clock 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_trace2`] +#[doc = "clk_u7mc_trace2 (rw) register accessor: U7MC Trace Clock 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_trace2`] module"] pub type CLK_U7MC_TRACE2 = crate::Reg; #[doc = "U7MC Trace Clock 2"] pub mod clk_u7mc_trace2; -#[doc = "clk_u7mc_trace3 (rw) register accessor: U7MC Trace Clock 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_trace3`] +#[doc = "clk_u7mc_trace3 (rw) register accessor: U7MC Trace Clock 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_trace3`] module"] pub type CLK_U7MC_TRACE3 = crate::Reg; #[doc = "U7MC Trace Clock 3"] pub mod clk_u7mc_trace3; -#[doc = "clk_u7mc_trace4 (rw) register accessor: U7MC Trace Clock 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_trace4`] +#[doc = "clk_u7mc_trace4 (rw) register accessor: U7MC Trace Clock 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_trace4`] module"] pub type CLK_U7MC_TRACE4 = crate::Reg; #[doc = "U7MC Trace Clock 4"] pub mod clk_u7mc_trace4; -#[doc = "clk_u7mc_trace_com (rw) register accessor: U7MC Trace Clock COM\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace_com::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace_com::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_trace_com`] +#[doc = "clk_u7mc_trace_com (rw) register accessor: U7MC Trace Clock COM\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace_com::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace_com::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_trace_com`] module"] pub type CLK_U7MC_TRACE_COM = crate::Reg; #[doc = "U7MC Trace Clock COM"] pub mod clk_u7mc_trace_com; -#[doc = "clk_u0_sft7110_noc_bus_clk_cpu_axi (rw) register accessor: clk_u0_sft7110_noc_bus_clk_cpu_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sft7110_noc_bus_clk_cpu_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sft7110_noc_bus_clk_cpu_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_sft7110_noc_bus_clk_cpu_axi`] +#[doc = "clk_u0_sft7110_noc_bus_clk_cpu_axi (rw) register accessor: clk_u0_sft7110_noc_bus_clk_cpu_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sft7110_noc_bus_clk_cpu_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sft7110_noc_bus_clk_cpu_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_sft7110_noc_bus_clk_cpu_axi`] module"] pub type CLK_U0_SFT7110_NOC_BUS_CLK_CPU_AXI = crate::Reg; #[doc = "clk_u0_sft7110_noc_bus_clk_cpu_axi"] pub mod clk_u0_sft7110_noc_bus_clk_cpu_axi; -#[doc = "clk_u0_sft7110_noc_bus_clk_axicfg0_axi (rw) register accessor: clk_u0_sft7110_noc_bus_clk_axicfg0_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sft7110_noc_bus_clk_axicfg0_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sft7110_noc_bus_clk_axicfg0_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_sft7110_noc_bus_clk_axicfg0_axi`] +#[doc = "clk_u0_sft7110_noc_bus_clk_axicfg0_axi (rw) register accessor: clk_u0_sft7110_noc_bus_clk_axicfg0_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sft7110_noc_bus_clk_axicfg0_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sft7110_noc_bus_clk_axicfg0_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_sft7110_noc_bus_clk_axicfg0_axi`] module"] pub type CLK_U0_SFT7110_NOC_BUS_CLK_AXICFG0_AXI = crate::Reg; #[doc = "clk_u0_sft7110_noc_bus_clk_axicfg0_axi"] pub mod clk_u0_sft7110_noc_bus_clk_axicfg0_axi; -#[doc = "clk_osc_div2 (rw) register accessor: clk_osc_div2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_osc_div2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_osc_div2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_osc_div2`] +#[doc = "clk_osc_div2 (rw) register accessor: clk_osc_div2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_osc_div2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_osc_div2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_osc_div2`] module"] pub type CLK_OSC_DIV2 = crate::Reg; #[doc = "clk_osc_div2"] pub mod clk_osc_div2; -#[doc = "clk_pll1_div4 (rw) register accessor: clk_pll1_div4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll1_div4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll1_div4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pll1_div4`] +#[doc = "clk_pll1_div4 (rw) register accessor: clk_pll1_div4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll1_div4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll1_div4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pll1_div4`] module"] pub type CLK_PLL1_DIV4 = crate::Reg; #[doc = "clk_pll1_div4"] pub mod clk_pll1_div4; -#[doc = "clk_pll1_div8 (rw) register accessor: clk_pll1_div8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll1_div8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll1_div8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pll1_div8`] +#[doc = "clk_pll1_div8 (rw) register accessor: clk_pll1_div8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll1_div8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll1_div8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pll1_div8`] module"] pub type CLK_PLL1_DIV8 = crate::Reg; #[doc = "clk_pll1_div8"] pub mod clk_pll1_div8; -#[doc = "clk_ddr_bus (rw) register accessor: clk_ddr_bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ddr_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ddr_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_ddr_bus`] +#[doc = "clk_ddr_bus (rw) register accessor: clk_ddr_bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ddr_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ddr_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_ddr_bus`] module"] pub type CLK_DDR_BUS = crate::Reg; #[doc = "clk_ddr_bus"] pub mod clk_ddr_bus; -#[doc = "clk_u0_ddr_sft7110_clk_axi (rw) register accessor: clk_u0_ddr_sfft7110_clk_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_ddr_sft7110_clk_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_ddr_sft7110_clk_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_ddr_sft7110_clk_axi`] +#[doc = "clk_u0_ddr_sft7110_clk_axi (rw) register accessor: clk_u0_ddr_sfft7110_clk_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_ddr_sft7110_clk_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_ddr_sft7110_clk_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_ddr_sft7110_clk_axi`] module"] pub type CLK_U0_DDR_SFT7110_CLK_AXI = crate::Reg; #[doc = "clk_u0_ddr_sfft7110_clk_axi"] pub mod clk_u0_ddr_sft7110_clk_axi; -#[doc = "clk_gpu_core (rw) register accessor: clk_gpu_core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gpu_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpu_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gpu_core`] +#[doc = "clk_gpu_core (rw) register accessor: clk_gpu_core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gpu_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpu_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gpu_core`] module"] pub type CLK_GPU_CORE = crate::Reg; #[doc = "clk_gpu_core"] pub mod clk_gpu_core; -#[doc = "clk_u0_img_gpu_core_clk (rw) register accessor: clk_u0_img_gpu_core_clk\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_img_gpu_core_clk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_img_gpu_core_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_img_gpu_core_clk`] +#[doc = "clk_u0_img_gpu_core_clk (rw) register accessor: clk_u0_img_gpu_core_clk\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_img_gpu_core_clk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_img_gpu_core_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_img_gpu_core_clk`] module"] pub type CLK_U0_IMG_GPU_CORE_CLK = crate::Reg; #[doc = "clk_u0_img_gpu_core_clk"] pub mod clk_u0_img_gpu_core_clk; -#[doc = "clk_u0_img_gpu_sys_clk (rw) register accessor: clk_u0_img_gpu_sys_clk\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_img_gpu_sys_clk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_img_gpu_sys_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_img_gpu_sys_clk`] +#[doc = "clk_u0_img_gpu_sys_clk (rw) register accessor: clk_u0_img_gpu_sys_clk\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_img_gpu_sys_clk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_img_gpu_sys_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_img_gpu_sys_clk`] module"] pub type CLK_U0_IMG_GPU_SYS_CLK = crate::Reg; #[doc = "clk_u0_img_gpu_sys_clk"] pub mod clk_u0_img_gpu_sys_clk; -#[doc = "clk_u0_img_gpu_clk_apb (rw) register accessor: clk_u0_img_gpu_clk_apb\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_img_gpu_clk_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_img_gpu_clk_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_img_gpu_clk_apb`] +#[doc = "clk_u0_img_gpu_clk_apb (rw) register accessor: clk_u0_img_gpu_clk_apb\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_img_gpu_clk_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_img_gpu_clk_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_img_gpu_clk_apb`] module"] pub type CLK_U0_IMG_GPU_CLK_APB = crate::Reg; #[doc = "clk_u0_img_gpu_clk_apb"] pub mod clk_u0_img_gpu_clk_apb; -#[doc = "clk_u0_gpu_rtc_toggle (rw) register accessor: clk_u0_gpu_rtc_toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_gpu_rtc_toggle::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_gpu_rtc_toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_gpu_rtc_toggle`] +#[doc = "clk_u0_gpu_rtc_toggle (rw) register accessor: clk_u0_gpu_rtc_toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_gpu_rtc_toggle::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_gpu_rtc_toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_gpu_rtc_toggle`] module"] pub type CLK_U0_GPU_RTC_TOGGLE = crate::Reg; #[doc = "clk_u0_gpu_rtc_toggle"] pub mod clk_u0_gpu_rtc_toggle; -#[doc = "clk_u0_sft7110_noc_bus_clk_gpu_axi (rw) register accessor: clk_u0_sft7110_noc_bus_clk_gpu_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sft7110_noc_bus_clk_gpu_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sft7110_noc_bus_clk_gpu_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_sft7110_noc_bus_clk_gpu_axi`] +#[doc = "clk_u0_sft7110_noc_bus_clk_gpu_axi (rw) register accessor: clk_u0_sft7110_noc_bus_clk_gpu_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sft7110_noc_bus_clk_gpu_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sft7110_noc_bus_clk_gpu_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_sft7110_noc_bus_clk_gpu_axi`] module"] pub type CLK_U0_SFT7110_NOC_BUS_CLK_GPU_AXI = crate::Reg; #[doc = "clk_u0_sft7110_noc_bus_clk_gpu_axi"] pub mod clk_u0_sft7110_noc_bus_clk_gpu_axi; -#[doc = "clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x (rw) register accessor: clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x`] +#[doc = "clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x (rw) register accessor: clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x`] module"] pub type CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISPCORE_2X = crate :: Reg < clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x :: CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISPCORE_2X_SPEC > ; #[doc = "clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x"] pub mod clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x; -#[doc = "clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi (rw) register accessor: clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi`] +#[doc = "clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi (rw) register accessor: clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi`] module"] pub type CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISP_AXI = crate :: Reg < clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi :: CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISP_AXI_SPEC > ; #[doc = "clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi"] pub mod clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi; -#[doc = "clk_u0_sft7110_noc_bux_clk_isp_axi (rw) register accessor: clk_u0_sft7110_noc_bux_clk_isp_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sft7110_noc_bux_clk_isp_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sft7110_noc_bux_clk_isp_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_sft7110_noc_bux_clk_isp_axi`] +#[doc = "clk_u0_sft7110_noc_bux_clk_isp_axi (rw) register accessor: clk_u0_sft7110_noc_bux_clk_isp_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sft7110_noc_bux_clk_isp_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sft7110_noc_bux_clk_isp_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_sft7110_noc_bux_clk_isp_axi`] module"] pub type CLK_U0_SFT7110_NOC_BUX_CLK_ISP_AXI = crate::Reg; #[doc = "clk_u0_sft7110_noc_bux_clk_isp_axi"] pub mod clk_u0_sft7110_noc_bux_clk_isp_axi; -#[doc = "clk_hifi4_core (rw) register accessor: clk_hifi4_core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_hifi4_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_hifi4_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_hifi4_core`] +#[doc = "clk_hifi4_core (rw) register accessor: clk_hifi4_core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_hifi4_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_hifi4_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_hifi4_core`] module"] pub type CLK_HIFI4_CORE = crate::Reg; #[doc = "clk_hifi4_core"] pub mod clk_hifi4_core; -#[doc = "clk_hifi4_axi (rw) register accessor: clk_hifi4_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_hifi4_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_hifi4_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_hifi4_axi`] +#[doc = "clk_hifi4_axi (rw) register accessor: clk_hifi4_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_hifi4_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_hifi4_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_hifi4_axi`] module"] pub type CLK_HIFI4_AXI = crate::Reg; #[doc = "clk_hifi4_axi"] pub mod clk_hifi4_axi; -#[doc = "clk_u0_axi_cfg1_dec_clk_main (rw) register accessor: clk_u0_axi_cfg1_dec_clk_main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_axi_cfg1_dec_clk_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_axi_cfg1_dec_clk_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_axi_cfg1_dec_clk_main`] +#[doc = "clk_u0_axi_cfg1_dec_clk_main (rw) register accessor: clk_u0_axi_cfg1_dec_clk_main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_axi_cfg1_dec_clk_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_axi_cfg1_dec_clk_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_axi_cfg1_dec_clk_main`] module"] pub type CLK_U0_AXI_CFG1_DEC_CLK_MAIN = crate::Reg; #[doc = "clk_u0_axi_cfg1_dec_clk_main"] pub mod clk_u0_axi_cfg1_dec_clk_main; -#[doc = "clk_u0_axi_cfg1_dec_clk_ahb (rw) register accessor: clk_u0_axi_cfg1_dec_clk_ahb\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_axi_cfg1_dec_clk_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_axi_cfg1_dec_clk_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_axi_cfg1_dec_clk_ahb`] +#[doc = "clk_u0_axi_cfg1_dec_clk_ahb (rw) register accessor: clk_u0_axi_cfg1_dec_clk_ahb\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_axi_cfg1_dec_clk_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_axi_cfg1_dec_clk_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_axi_cfg1_dec_clk_ahb`] module"] pub type CLK_U0_AXI_CFG1_DEC_CLK_AHB = crate::Reg; #[doc = "clk_u0_axi_cfg1_dec_clk_ahb"] pub mod clk_u0_axi_cfg1_dec_clk_ahb; -#[doc = "clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src (rw) register accessor: clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src`] +#[doc = "clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src (rw) register accessor: clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src`] module"] pub type CLK_U0_DOM_VOUT_TOP_CLK_DOM_VOUT_TOP_CLK_VOUT_SRC = crate :: Reg < clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src :: CLK_U0_DOM_VOUT_TOP_CLK_DOM_VOUT_TOP_CLK_VOUT_SRC_SPEC > ; #[doc = "clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src"] pub mod clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src; -#[doc = "clk_vout_axi_divcfg (rw) register accessor: Clock Video Output AXI DIVCFG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_axi_divcfg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_axi_divcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_vout_axi_divcfg`] +#[doc = "clk_vout_axi_divcfg (rw) register accessor: Clock Video Output AXI DIVCFG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_axi_divcfg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_axi_divcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_vout_axi_divcfg`] module"] pub type CLK_VOUT_AXI_DIVCFG = crate::Reg; #[doc = "Clock Video Output AXI DIVCFG"] pub mod clk_vout_axi_divcfg; -#[doc = "clk_noc_display_axi (rw) register accessor: Clock NOC Display AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_noc_display_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_noc_display_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_noc_display_axi`] +#[doc = "clk_noc_display_axi (rw) register accessor: Clock NOC Display AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_noc_display_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_noc_display_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_noc_display_axi`] module"] pub type CLK_NOC_DISPLAY_AXI = crate::Reg; #[doc = "Clock NOC Display AXI"] pub mod clk_noc_display_axi; -#[doc = "clk_vout_ahb (rw) register accessor: Clock Video Output AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_vout_ahb`] +#[doc = "clk_vout_ahb (rw) register accessor: Clock Video Output AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_vout_ahb`] module"] pub type CLK_VOUT_AHB = crate::Reg; #[doc = "Clock Video Output AHB"] pub mod clk_vout_ahb; -#[doc = "clk_vout_axi_icg (rw) register accessor: Clock Video Output AXI ICG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_axi_icg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_axi_icg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_vout_axi_icg`] +#[doc = "clk_vout_axi_icg (rw) register accessor: Clock Video Output AXI ICG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_axi_icg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_axi_icg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_vout_axi_icg`] module"] pub type CLK_VOUT_AXI_ICG = crate::Reg; #[doc = "Clock Video Output AXI ICG"] pub mod clk_vout_axi_icg; -#[doc = "clk_vout_hdmi_tx0_mclk (rw) register accessor: Clock Video Output HDMI TX0 MCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_hdmi_tx0_mclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_hdmi_tx0_mclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_vout_hdmi_tx0_mclk`] +#[doc = "clk_vout_hdmi_tx0_mclk (rw) register accessor: Clock Video Output HDMI TX0 MCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_hdmi_tx0_mclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_hdmi_tx0_mclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_vout_hdmi_tx0_mclk`] module"] pub type CLK_VOUT_HDMI_TX0_MCLK = crate::Reg; #[doc = "Clock Video Output HDMI TX0 MCLK"] pub mod clk_vout_hdmi_tx0_mclk; -#[doc = "clk_vout_mipi_phy (rw) register accessor: Clock Video Output MIPI PHY Reference\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_mipi_phy::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_mipi_phy::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_vout_mipi_phy`] +#[doc = "clk_vout_mipi_phy (rw) register accessor: Clock Video Output MIPI PHY Reference\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_mipi_phy::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_mipi_phy::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_vout_mipi_phy`] module"] pub type CLK_VOUT_MIPI_PHY = crate::Reg; #[doc = "Clock Video Output MIPI PHY Reference"] pub mod clk_vout_mipi_phy; -#[doc = "clk_jpeg_codec_axi (rw) register accessor: Clock JPEG Codec AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_jpeg_codec_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_jpeg_codec_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_jpeg_codec_axi`] +#[doc = "clk_jpeg_codec_axi (rw) register accessor: Clock JPEG Codec AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_jpeg_codec_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_jpeg_codec_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_jpeg_codec_axi`] module"] pub type CLK_JPEG_CODEC_AXI = crate::Reg; #[doc = "Clock JPEG Codec AXI"] pub mod clk_jpeg_codec_axi; -#[doc = "clk_codaj12_axi (rw) register accessor: CODAJ12 Clock AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_codaj12_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_codaj12_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_codaj12_axi`] +#[doc = "clk_codaj12_axi (rw) register accessor: CODAJ12 Clock AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_codaj12_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_codaj12_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_codaj12_axi`] module"] pub type CLK_CODAJ12_AXI = crate::Reg; #[doc = "CODAJ12 Clock AXI"] pub mod clk_codaj12_axi; -#[doc = "clk_codaj12_core (rw) register accessor: CODAJ12 Clock Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_codaj12_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_codaj12_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_codaj12_core`] +#[doc = "clk_codaj12_core (rw) register accessor: CODAJ12 Clock Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_codaj12_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_codaj12_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_codaj12_core`] module"] pub type CLK_CODAJ12_CORE = crate::Reg; #[doc = "CODAJ12 Clock Core"] pub mod clk_codaj12_core; -#[doc = "clk_codaj12_apb (rw) register accessor: CODAJ12 Clock APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_codaj12_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_codaj12_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_codaj12_apb`] +#[doc = "clk_codaj12_apb (rw) register accessor: CODAJ12 Clock APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_codaj12_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_codaj12_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_codaj12_apb`] module"] pub type CLK_CODAJ12_APB = crate::Reg; #[doc = "CODAJ12 Clock APB"] pub mod clk_codaj12_apb; -#[doc = "clk_vdec_axi (rw) register accessor: Clock Video Decoder AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vdec_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vdec_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_vdec_axi`] +#[doc = "clk_vdec_axi (rw) register accessor: Clock Video Decoder AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vdec_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vdec_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_vdec_axi`] module"] pub type CLK_VDEC_AXI = crate::Reg; #[doc = "Clock Video Decoder AXI"] pub mod clk_vdec_axi; -#[doc = "clk_wave511_axi (rw) register accessor: Clock WAVE511 AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave511_axi`] +#[doc = "clk_wave511_axi (rw) register accessor: Clock WAVE511 AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave511_axi`] module"] pub type CLK_WAVE511_AXI = crate::Reg; #[doc = "Clock WAVE511 AXI"] pub mod clk_wave511_axi; -#[doc = "clk_wave511_bpu (rw) register accessor: Clock WAVE511 BPU\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_bpu::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_bpu::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave511_bpu`] +#[doc = "clk_wave511_bpu (rw) register accessor: Clock WAVE511 BPU\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_bpu::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_bpu::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave511_bpu`] module"] pub type CLK_WAVE511_BPU = crate::Reg; #[doc = "Clock WAVE511 BPU"] pub mod clk_wave511_bpu; -#[doc = "clk_wave511_vce (rw) register accessor: Clock WAVE511 VCE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_vce::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_vce::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave511_vce`] +#[doc = "clk_wave511_vce (rw) register accessor: Clock WAVE511 VCE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_vce::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_vce::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave511_vce`] module"] pub type CLK_WAVE511_VCE = crate::Reg; #[doc = "Clock WAVE511 VCE"] pub mod clk_wave511_vce; -#[doc = "clk_wave511_apb (rw) register accessor: Clock WAVE511 APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave511_apb`] +#[doc = "clk_wave511_apb (rw) register accessor: Clock WAVE511 APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave511_apb`] module"] pub type CLK_WAVE511_APB = crate::Reg; #[doc = "Clock WAVE511 APB"] pub mod clk_wave511_apb; -#[doc = "clk_wave511_jpg_arb (rw) register accessor: Clock WAVE511 JPG ARB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_jpg_arb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_jpg_arb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave511_jpg_arb`] +#[doc = "clk_wave511_jpg_arb (rw) register accessor: Clock WAVE511 JPG ARB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_jpg_arb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_jpg_arb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave511_jpg_arb`] module"] pub type CLK_WAVE511_JPG_ARB = crate::Reg; #[doc = "Clock WAVE511 JPG ARB"] pub mod clk_wave511_jpg_arb; -#[doc = "clk_wave511_jpg_main (rw) register accessor: Clock WAVE511 JPG Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_jpg_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_jpg_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave511_jpg_main`] +#[doc = "clk_wave511_jpg_main (rw) register accessor: Clock WAVE511 JPG Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_jpg_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_jpg_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave511_jpg_main`] module"] pub type CLK_WAVE511_JPG_MAIN = crate::Reg; #[doc = "Clock WAVE511 JPG Main"] pub mod clk_wave511_jpg_main; -#[doc = "clk_noc_vdec_axi (rw) register accessor: Clock NOC Video Decoder AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_noc_vdec_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_noc_vdec_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_noc_vdec_axi`] +#[doc = "clk_noc_vdec_axi (rw) register accessor: Clock NOC Video Decoder AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_noc_vdec_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_noc_vdec_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_noc_vdec_axi`] module"] pub type CLK_NOC_VDEC_AXI = crate::Reg; #[doc = "Clock NOC Video Decoder AXI"] pub mod clk_noc_vdec_axi; -#[doc = "clk_venc_axi (rw) register accessor: Clock Video Encoder AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_venc_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_venc_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_venc_axi`] +#[doc = "clk_venc_axi (rw) register accessor: Clock Video Encoder AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_venc_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_venc_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_venc_axi`] module"] pub type CLK_VENC_AXI = crate::Reg; #[doc = "Clock Video Encoder AXI"] pub mod clk_venc_axi; -#[doc = "clk_wave420l_axi (rw) register accessor: Clock WAVE420L AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave420l_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave420l_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave420l_axi`] +#[doc = "clk_wave420l_axi (rw) register accessor: Clock WAVE420L AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave420l_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave420l_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave420l_axi`] module"] pub type CLK_WAVE420L_AXI = crate::Reg; #[doc = "Clock WAVE420L AXI"] pub mod clk_wave420l_axi; -#[doc = "clk_wave420l_bpu (rw) register accessor: Clock WAVE420L BPU\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave420l_bpu::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave420l_bpu::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave420l_bpu`] +#[doc = "clk_wave420l_bpu (rw) register accessor: Clock WAVE420L BPU\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave420l_bpu::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave420l_bpu::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave420l_bpu`] module"] pub type CLK_WAVE420L_BPU = crate::Reg; #[doc = "Clock WAVE420L BPU"] pub mod clk_wave420l_bpu; -#[doc = "clk_wave420l_vce (rw) register accessor: Clock WAVE420L VCE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave420l_vce::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave420l_vce::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave420l_vce`] +#[doc = "clk_wave420l_vce (rw) register accessor: Clock WAVE420L VCE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave420l_vce::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave420l_vce::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave420l_vce`] module"] pub type CLK_WAVE420L_VCE = crate::Reg; #[doc = "Clock WAVE420L VCE"] pub mod clk_wave420l_vce; -#[doc = "clk_wave420l_apb (rw) register accessor: Clock WAVE420L APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave420l_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave420l_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave420l_apb`] +#[doc = "clk_wave420l_apb (rw) register accessor: Clock WAVE420L APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave420l_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave420l_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave420l_apb`] module"] pub type CLK_WAVE420L_APB = crate::Reg; #[doc = "Clock WAVE420L APB"] pub mod clk_wave420l_apb; -#[doc = "clk_noc_venc_axi (rw) register accessor: Clock NOC Video Encoder AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_noc_venc_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_noc_venc_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_noc_venc_axi`] +#[doc = "clk_noc_venc_axi (rw) register accessor: Clock NOC Video Encoder AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_noc_venc_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_noc_venc_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_noc_venc_axi`] module"] pub type CLK_NOC_VENC_AXI = crate::Reg; #[doc = "Clock NOC Video Encoder AXI"] pub mod clk_noc_venc_axi; -#[doc = "clk_axi_cfg0_dec_main_div (rw) register accessor: Clock AXI Config 0 DEC Main Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_cfg0_dec_main_div::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_cfg0_dec_main_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_axi_cfg0_dec_main_div`] +#[doc = "clk_axi_cfg0_dec_main_div (rw) register accessor: Clock AXI Config 0 DEC Main Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_cfg0_dec_main_div::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_cfg0_dec_main_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_axi_cfg0_dec_main_div`] module"] pub type CLK_AXI_CFG0_DEC_MAIN_DIV = crate::Reg; #[doc = "Clock AXI Config 0 DEC Main Divider"] pub mod clk_axi_cfg0_dec_main_div; -#[doc = "clk_axi_cfg0_dec_main (rw) register accessor: Clock AXI Config 0 DEC Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_cfg0_dec_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_cfg0_dec_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_axi_cfg0_dec_main`] +#[doc = "clk_axi_cfg0_dec_main (rw) register accessor: Clock AXI Config 0 DEC Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_cfg0_dec_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_cfg0_dec_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_axi_cfg0_dec_main`] module"] pub type CLK_AXI_CFG0_DEC_MAIN = crate::Reg; #[doc = "Clock AXI Config 0 DEC Main"] pub mod clk_axi_cfg0_dec_main; -#[doc = "clk_axi_cfg0_dec_hifi4 (rw) register accessor: Clock AXI Config 0 DEC HIFI4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_cfg0_dec_hifi4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_cfg0_dec_hifi4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_axi_cfg0_dec_hifi4`] +#[doc = "clk_axi_cfg0_dec_hifi4 (rw) register accessor: Clock AXI Config 0 DEC HIFI4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_cfg0_dec_hifi4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_cfg0_dec_hifi4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_axi_cfg0_dec_hifi4`] module"] pub type CLK_AXI_CFG0_DEC_HIFI4 = crate::Reg; #[doc = "Clock AXI Config 0 DEC HIFI4"] pub mod clk_axi_cfg0_dec_hifi4; -#[doc = "clk_aximem_128b_axi (rw) register accessor: Clock AXIMEM 128B AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_aximem_128b_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_aximem_128b_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_aximem_128b_axi`] +#[doc = "clk_aximem_128b_axi (rw) register accessor: Clock AXIMEM 128B AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_aximem_128b_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_aximem_128b_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_aximem_128b_axi`] module"] pub type CLK_AXIMEM_128B_AXI = crate::Reg; #[doc = "Clock AXIMEM 128B AXI"] pub mod clk_aximem_128b_axi; -#[doc = "clk_qspi_ahb (rw) register accessor: Clock QSPI AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_qspi_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_qspi_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_qspi_ahb`] +#[doc = "clk_qspi_ahb (rw) register accessor: Clock QSPI AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_qspi_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_qspi_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_qspi_ahb`] module"] pub type CLK_QSPI_AHB = crate::Reg; #[doc = "Clock QSPI AHB"] pub mod clk_qspi_ahb; -#[doc = "clk_qspi_apb (rw) register accessor: Clock QSPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_qspi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_qspi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_qspi_apb`] +#[doc = "clk_qspi_apb (rw) register accessor: Clock QSPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_qspi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_qspi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_qspi_apb`] module"] pub type CLK_QSPI_APB = crate::Reg; #[doc = "Clock QSPI APB"] pub mod clk_qspi_apb; -#[doc = "clk_qspi_ref_src (rw) register accessor: Clock QSPI Reference Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_qspi_ref_src::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_qspi_ref_src::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_qspi_ref_src`] +#[doc = "clk_qspi_ref_src (rw) register accessor: Clock QSPI Reference Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_qspi_ref_src::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_qspi_ref_src::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_qspi_ref_src`] module"] pub type CLK_QSPI_REF_SRC = crate::Reg; #[doc = "Clock QSPI Reference Source"] pub mod clk_qspi_ref_src; -#[doc = "clk_qspi_ref (rw) register accessor: Clock QSPI Reference\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_qspi_ref::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_qspi_ref::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_qspi_ref`] +#[doc = "clk_qspi_ref (rw) register accessor: Clock QSPI Reference\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_qspi_ref::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_qspi_ref::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_qspi_ref`] module"] pub type CLK_QSPI_REF = crate::Reg; #[doc = "Clock QSPI Reference"] pub mod clk_qspi_ref; -#[doc = "clk_u0_sd_ahb (rw) register accessor: U0 SD Clock AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sd_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sd_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_sd_ahb`] +#[doc = "clk_u0_sd_ahb (rw) register accessor: U0 SD Clock AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sd_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sd_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_sd_ahb`] module"] pub type CLK_U0_SD_AHB = crate::Reg; #[doc = "U0 SD Clock AHB"] pub mod clk_u0_sd_ahb; -#[doc = "clk_u1_sd_ahb (rw) register accessor: U1 SD Clock AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_sd_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_sd_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_sd_ahb`] +#[doc = "clk_u1_sd_ahb (rw) register accessor: U1 SD Clock AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_sd_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_sd_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_sd_ahb`] module"] pub type CLK_U1_SD_AHB = crate::Reg; #[doc = "U1 SD Clock AHB"] pub mod clk_u1_sd_ahb; -#[doc = "clk_u0_sd_card (rw) register accessor: U0 SD Card Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sd_card::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sd_card::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_sd_card`] +#[doc = "clk_u0_sd_card (rw) register accessor: U0 SD Card Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sd_card::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sd_card::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_sd_card`] module"] pub type CLK_U0_SD_CARD = crate::Reg; #[doc = "U0 SD Card Clock"] pub mod clk_u0_sd_card; -#[doc = "clk_u1_sd_card (rw) register accessor: U1 SD Card Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_sd_card::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_sd_card::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_sd_card`] +#[doc = "clk_u1_sd_card (rw) register accessor: U1 SD Card Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_sd_card::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_sd_card::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_sd_card`] module"] pub type CLK_U1_SD_CARD = crate::Reg; #[doc = "U1 SD Card Clock"] pub mod clk_u1_sd_card; -#[doc = "clk_usb_125m (rw) register accessor: Clock USB 125M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_125m::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_125m::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_usb_125m`] +#[doc = "clk_usb_125m (rw) register accessor: Clock USB 125M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_125m::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_125m::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_usb_125m`] module"] pub type CLK_USB_125M = crate::Reg; #[doc = "Clock USB 125M"] pub mod clk_usb_125m; -#[doc = "clk_noc_stg_axi (rw) register accessor: Clock NOC STG AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_noc_stg_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_noc_stg_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_noc_stg_axi`] +#[doc = "clk_noc_stg_axi (rw) register accessor: Clock NOC STG AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_noc_stg_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_noc_stg_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_noc_stg_axi`] module"] pub type CLK_NOC_STG_AXI = crate::Reg; #[doc = "Clock NOC STG AXI"] pub mod clk_noc_stg_axi; -#[doc = "clk_gmac5_axi64_ahb (rw) register accessor: Clock GMAC 5 AXI 64 AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_ahb`] +#[doc = "clk_gmac5_axi64_ahb (rw) register accessor: Clock GMAC 5 AXI 64 AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_ahb`] module"] pub type CLK_GMAC5_AXI64_AHB = crate::Reg; #[doc = "Clock GMAC 5 AXI 64 AHB"] pub mod clk_gmac5_axi64_ahb; -#[doc = "clk_gmac5_axi64_axi (rw) register accessor: Clock GMAC 5 AXI 64 AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_axi`] +#[doc = "clk_gmac5_axi64_axi (rw) register accessor: Clock GMAC 5 AXI 64 AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_axi`] module"] pub type CLK_GMAC5_AXI64_AXI = crate::Reg; #[doc = "Clock GMAC 5 AXI 64 AXI"] pub mod clk_gmac5_axi64_axi; -#[doc = "clk_gmac_src (rw) register accessor: Clock GMAC Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac_src::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac_src::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac_src`] +#[doc = "clk_gmac_src (rw) register accessor: Clock GMAC Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac_src::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac_src::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac_src`] module"] pub type CLK_GMAC_SRC = crate::Reg; #[doc = "Clock GMAC Source"] pub mod clk_gmac_src; -#[doc = "clk_gmac1_gtx (rw) register accessor: Clock GMAC 1 GTX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac1_gtx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac1_gtx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac1_gtx`] +#[doc = "clk_gmac1_gtx (rw) register accessor: Clock GMAC 1 GTX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac1_gtx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac1_gtx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac1_gtx`] module"] pub type CLK_GMAC1_GTX = crate::Reg; #[doc = "Clock GMAC 1 GTX"] pub mod clk_gmac1_gtx; -#[doc = "clk_gmac1_rmii_rtx (rw) register accessor: Clock GMAC 1 RMII RTX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac1_rmii_rtx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac1_rmii_rtx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac1_rmii_rtx`] +#[doc = "clk_gmac1_rmii_rtx (rw) register accessor: Clock GMAC 1 RMII RTX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac1_rmii_rtx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac1_rmii_rtx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac1_rmii_rtx`] module"] pub type CLK_GMAC1_RMII_RTX = crate::Reg; #[doc = "Clock GMAC 1 RMII RTX"] pub mod clk_gmac1_rmii_rtx; -#[doc = "clk_gmac5_axi64_ptp (rw) register accessor: Clock GMAC 5 AXI 64 PTP\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_ptp::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_ptp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_ptp`] +#[doc = "clk_gmac5_axi64_ptp (rw) register accessor: Clock GMAC 5 AXI 64 PTP\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_ptp::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_ptp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_ptp`] module"] pub type CLK_GMAC5_AXI64_PTP = crate::Reg; #[doc = "Clock GMAC 5 AXI 64 PTP"] pub mod clk_gmac5_axi64_ptp; -#[doc = "clk_gmac5_axi64_rx (rw) register accessor: Clock GMAC 5 AXI 64 RX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_rx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_rx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_rx`] +#[doc = "clk_gmac5_axi64_rx (rw) register accessor: Clock GMAC 5 AXI 64 RX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_rx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_rx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_rx`] module"] pub type CLK_GMAC5_AXI64_RX = crate::Reg; #[doc = "Clock GMAC 5 AXI 64 RX"] pub mod clk_gmac5_axi64_rx; -#[doc = "clk_gmac5_axi64_rxi (rw) register accessor: Clock GMAC 5 AXI 64 RX Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_rxi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_rxi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_rxi`] +#[doc = "clk_gmac5_axi64_rxi (rw) register accessor: Clock GMAC 5 AXI 64 RX Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_rxi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_rxi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_rxi`] module"] pub type CLK_GMAC5_AXI64_RXI = crate::Reg; #[doc = "Clock GMAC 5 AXI 64 RX Inverter"] pub mod clk_gmac5_axi64_rxi; -#[doc = "clk_gmac5_axi64_tx (rw) register accessor: Clock GMAC 5 AXI 64 TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_tx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_tx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_tx`] +#[doc = "clk_gmac5_axi64_tx (rw) register accessor: Clock GMAC 5 AXI 64 TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_tx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_tx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_tx`] module"] pub type CLK_GMAC5_AXI64_TX = crate::Reg; #[doc = "Clock GMAC 5 AXI 64 TX"] pub mod clk_gmac5_axi64_tx; -#[doc = "clk_gmac5_axi64_txi (rw) register accessor: Clock GMAC 5 AXI 64 TX Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_txi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_txi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_txi`] +#[doc = "clk_gmac5_axi64_txi (rw) register accessor: Clock GMAC 5 AXI 64 TX Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_txi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_txi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_txi`] module"] pub type CLK_GMAC5_AXI64_TXI = crate::Reg; #[doc = "Clock GMAC 5 AXI 64 TX Inverter"] pub mod clk_gmac5_axi64_txi; -#[doc = "clk_gmac1_gtxclk (rw) register accessor: Clock GMAC 1 GTXC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac1_gtxclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac1_gtxclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac1_gtxclk`] +#[doc = "clk_gmac1_gtxclk (rw) register accessor: Clock GMAC 1 GTXC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac1_gtxclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac1_gtxclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac1_gtxclk`] module"] pub type CLK_GMAC1_GTXCLK = crate::Reg; #[doc = "Clock GMAC 1 GTXC"] pub mod clk_gmac1_gtxclk; -#[doc = "clk_gmac0_gtx (rw) register accessor: Clock GMAC 0 GTX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac0_gtx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac0_gtx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac0_gtx`] +#[doc = "clk_gmac0_gtx (rw) register accessor: Clock GMAC 0 GTX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac0_gtx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac0_gtx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac0_gtx`] module"] pub type CLK_GMAC0_GTX = crate::Reg; #[doc = "Clock GMAC 0 GTX"] pub mod clk_gmac0_gtx; -#[doc = "clk_gmac0_ptp (rw) register accessor: Clock GMAC 0 PTP\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac0_ptp::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac0_ptp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac0_ptp`] +#[doc = "clk_gmac0_ptp (rw) register accessor: Clock GMAC 0 PTP\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac0_ptp::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac0_ptp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac0_ptp`] module"] pub type CLK_GMAC0_PTP = crate::Reg; #[doc = "Clock GMAC 0 PTP"] pub mod clk_gmac0_ptp; -#[doc = "clk_gmac_phy (rw) register accessor: Clock GMAC PHY\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac_phy::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac_phy::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac_phy`] +#[doc = "clk_gmac_phy (rw) register accessor: Clock GMAC PHY\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac_phy::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac_phy::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac_phy`] module"] pub type CLK_GMAC_PHY = crate::Reg; #[doc = "Clock GMAC PHY"] pub mod clk_gmac_phy; -#[doc = "clk_gmac0_gtxclk (rw) register accessor: Clock GMAC 0 GTXC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac0_gtxclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac0_gtxclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac0_gtxclk`] +#[doc = "clk_gmac0_gtxclk (rw) register accessor: Clock GMAC 0 GTXC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac0_gtxclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac0_gtxclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac0_gtxclk`] module"] pub type CLK_GMAC0_GTXCLK = crate::Reg; #[doc = "Clock GMAC 0 GTXC"] pub mod clk_gmac0_gtxclk; -#[doc = "clk_sys_iomux_pclk (rw) register accessor: Clock SYS IOMUX PCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_iomux_pclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_iomux_pclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_sys_iomux_pclk`] +#[doc = "clk_sys_iomux_pclk (rw) register accessor: Clock SYS IOMUX PCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_iomux_pclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_iomux_pclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_sys_iomux_pclk`] module"] pub type CLK_SYS_IOMUX_PCLK = crate::Reg; #[doc = "Clock SYS IOMUX PCLK"] pub mod clk_sys_iomux_pclk; -#[doc = "clk_mbox_apb (rw) register accessor: Clock Mailbox APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_mbox_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_mbox_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_mbox_apb`] +#[doc = "clk_mbox_apb (rw) register accessor: Clock Mailbox APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_mbox_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_mbox_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_mbox_apb`] module"] pub type CLK_MBOX_APB = crate::Reg; #[doc = "Clock Mailbox APB"] pub mod clk_mbox_apb; -#[doc = "clk_internal_ctrl_apb (rw) register accessor: Clock Internal Controller APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_internal_ctrl_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_internal_ctrl_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_internal_ctrl_apb`] +#[doc = "clk_internal_ctrl_apb (rw) register accessor: Clock Internal Controller APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_internal_ctrl_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_internal_ctrl_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_internal_ctrl_apb`] module"] pub type CLK_INTERNAL_CTRL_APB = crate::Reg; #[doc = "Clock Internal Controller APB"] pub mod clk_internal_ctrl_apb; -#[doc = "clk_u0_can_ctrl_apb (rw) register accessor: U0 Clock CAN Controller APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_can_ctrl_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_can_ctrl_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_can_ctrl_apb`] +#[doc = "clk_u0_can_ctrl_apb (rw) register accessor: U0 Clock CAN Controller APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_can_ctrl_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_can_ctrl_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_can_ctrl_apb`] module"] pub type CLK_U0_CAN_CTRL_APB = crate::Reg; #[doc = "U0 Clock CAN Controller APB"] pub mod clk_u0_can_ctrl_apb; -#[doc = "clk_u0_can_ctrl_tim (rw) register accessor: U0 Clock CAN Controller Timer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_can_ctrl_tim::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_can_ctrl_tim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_can_ctrl_tim`] +#[doc = "clk_u0_can_ctrl_tim (rw) register accessor: U0 Clock CAN Controller Timer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_can_ctrl_tim::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_can_ctrl_tim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_can_ctrl_tim`] module"] pub type CLK_U0_CAN_CTRL_TIM = crate::Reg; #[doc = "U0 Clock CAN Controller Timer"] pub mod clk_u0_can_ctrl_tim; -#[doc = "clk_u0_can_ctrl_can (rw) register accessor: U0 Clock CAN Controller CAN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_can_ctrl_can::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_can_ctrl_can::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_can_ctrl_can`] +#[doc = "clk_u0_can_ctrl_can (rw) register accessor: U0 Clock CAN Controller CAN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_can_ctrl_can::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_can_ctrl_can::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_can_ctrl_can`] module"] pub type CLK_U0_CAN_CTRL_CAN = crate::Reg; #[doc = "U0 Clock CAN Controller CAN"] pub mod clk_u0_can_ctrl_can; -#[doc = "clk_u1_can_ctrl_apb (rw) register accessor: U1 Clock CAN Controller APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_can_ctrl_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_can_ctrl_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_can_ctrl_apb`] +#[doc = "clk_u1_can_ctrl_apb (rw) register accessor: U1 Clock CAN Controller APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_can_ctrl_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_can_ctrl_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_can_ctrl_apb`] module"] pub type CLK_U1_CAN_CTRL_APB = crate::Reg; #[doc = "U1 Clock CAN Controller APB"] pub mod clk_u1_can_ctrl_apb; -#[doc = "clk_u1_can_ctrl_tim (rw) register accessor: U1 Clock CAN Controller Timer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_can_ctrl_tim::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_can_ctrl_tim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_can_ctrl_tim`] +#[doc = "clk_u1_can_ctrl_tim (rw) register accessor: U1 Clock CAN Controller Timer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_can_ctrl_tim::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_can_ctrl_tim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_can_ctrl_tim`] module"] pub type CLK_U1_CAN_CTRL_TIM = crate::Reg; #[doc = "U1 Clock CAN Controller Timer"] pub mod clk_u1_can_ctrl_tim; -#[doc = "clk_u1_can_ctrl_can (rw) register accessor: U1 Clock CAN Controller CAN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_can_ctrl_can::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_can_ctrl_can::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_can_ctrl_can`] +#[doc = "clk_u1_can_ctrl_can (rw) register accessor: U1 Clock CAN Controller CAN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_can_ctrl_can::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_can_ctrl_can::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_can_ctrl_can`] module"] pub type CLK_U1_CAN_CTRL_CAN = crate::Reg; #[doc = "U1 Clock CAN Controller CAN"] pub mod clk_u1_can_ctrl_can; -#[doc = "clk_pwm_apb (rw) register accessor: Clock PWM APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pwm_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pwm_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pwm_apb`] +#[doc = "clk_pwm_apb (rw) register accessor: Clock PWM APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pwm_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pwm_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pwm_apb`] module"] pub type CLK_PWM_APB = crate::Reg; #[doc = "Clock PWM APB"] pub mod clk_pwm_apb; -#[doc = "clk_wdt_apb (rw) register accessor: Clock WDT APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wdt_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wdt_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wdt_apb`] +#[doc = "clk_wdt_apb (rw) register accessor: Clock WDT APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wdt_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wdt_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wdt_apb`] module"] pub type CLK_WDT_APB = crate::Reg; #[doc = "Clock WDT APB"] pub mod clk_wdt_apb; -#[doc = "clk_wdt (rw) register accessor: Clock WDT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wdt::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wdt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wdt`] +#[doc = "clk_wdt (rw) register accessor: Clock WDT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wdt::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wdt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wdt`] module"] pub type CLK_WDT = crate::Reg; #[doc = "Clock WDT"] pub mod clk_wdt; -#[doc = "clk_tim_apb (rw) register accessor: Clock Timer APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tim_apb`] +#[doc = "clk_tim_apb (rw) register accessor: Clock Timer APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tim_apb`] module"] pub type CLK_TIM_APB = crate::Reg; #[doc = "Clock Timer APB"] pub mod clk_tim_apb; -#[doc = "clk_tim0 (rw) register accessor: Clock Timer 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tim0`] +#[doc = "clk_tim0 (rw) register accessor: Clock Timer 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tim0`] module"] pub type CLK_TIM0 = crate::Reg; #[doc = "Clock Timer 0"] pub mod clk_tim0; -#[doc = "clk_tim1 (rw) register accessor: Clock Timer 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tim1`] +#[doc = "clk_tim1 (rw) register accessor: Clock Timer 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tim1`] module"] pub type CLK_TIM1 = crate::Reg; #[doc = "Clock Timer 1"] pub mod clk_tim1; -#[doc = "clk_tim2 (rw) register accessor: Clock Timer 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tim2`] +#[doc = "clk_tim2 (rw) register accessor: Clock Timer 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tim2`] module"] pub type CLK_TIM2 = crate::Reg; #[doc = "Clock Timer 2"] pub mod clk_tim2; -#[doc = "clk_tim3 (rw) register accessor: Clock Timer 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tim3`] +#[doc = "clk_tim3 (rw) register accessor: Clock Timer 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tim3`] module"] pub type CLK_TIM3 = crate::Reg; #[doc = "Clock Timer 3"] pub mod clk_tim3; -#[doc = "clk_temp_sensor_apb (rw) register accessor: Clock Temperature Sensor APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_temp_sensor_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_temp_sensor_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_temp_sensor_apb`] +#[doc = "clk_temp_sensor_apb (rw) register accessor: Clock Temperature Sensor APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_temp_sensor_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_temp_sensor_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_temp_sensor_apb`] module"] pub type CLK_TEMP_SENSOR_APB = crate::Reg; #[doc = "Clock Temperature Sensor APB"] pub mod clk_temp_sensor_apb; -#[doc = "clk_temp_sensor (rw) register accessor: Clock Temperature Sensor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_temp_sensor::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_temp_sensor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_temp_sensor`] +#[doc = "clk_temp_sensor (rw) register accessor: Clock Temperature Sensor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_temp_sensor::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_temp_sensor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_temp_sensor`] module"] pub type CLK_TEMP_SENSOR = crate::Reg; #[doc = "Clock Temperature Sensor"] pub mod clk_temp_sensor; -#[doc = "clk_u0_spi_apb (rw) register accessor: U0 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_spi_apb`] +#[doc = "clk_u0_spi_apb (rw) register accessor: U0 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_spi_apb`] module"] pub type CLK_U0_SPI_APB = crate::Reg; #[doc = "U0 Clock SPI APB"] pub mod clk_u0_spi_apb; -#[doc = "clk_u1_spi_apb (rw) register accessor: U1 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_spi_apb`] +#[doc = "clk_u1_spi_apb (rw) register accessor: U1 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_spi_apb`] module"] pub type CLK_U1_SPI_APB = crate::Reg; #[doc = "U1 Clock SPI APB"] pub mod clk_u1_spi_apb; -#[doc = "clk_u2_spi_apb (rw) register accessor: U2 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u2_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u2_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u2_spi_apb`] +#[doc = "clk_u2_spi_apb (rw) register accessor: U2 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u2_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u2_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u2_spi_apb`] module"] pub type CLK_U2_SPI_APB = crate::Reg; #[doc = "U2 Clock SPI APB"] pub mod clk_u2_spi_apb; -#[doc = "clk_u3_spi_apb (rw) register accessor: U3 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u3_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u3_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u3_spi_apb`] +#[doc = "clk_u3_spi_apb (rw) register accessor: U3 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u3_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u3_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u3_spi_apb`] module"] pub type CLK_U3_SPI_APB = crate::Reg; #[doc = "U3 Clock SPI APB"] pub mod clk_u3_spi_apb; -#[doc = "clk_u4_spi_apb (rw) register accessor: U4 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u4_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u4_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u4_spi_apb`] +#[doc = "clk_u4_spi_apb (rw) register accessor: U4 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u4_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u4_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u4_spi_apb`] module"] pub type CLK_U4_SPI_APB = crate::Reg; #[doc = "U4 Clock SPI APB"] pub mod clk_u4_spi_apb; -#[doc = "clk_u5_spi_apb (rw) register accessor: U5 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u5_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u5_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u5_spi_apb`] +#[doc = "clk_u5_spi_apb (rw) register accessor: U5 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u5_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u5_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u5_spi_apb`] module"] pub type CLK_U5_SPI_APB = crate::Reg; #[doc = "U5 Clock SPI APB"] pub mod clk_u5_spi_apb; -#[doc = "clk_u6_spi_apb (rw) register accessor: U6 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u6_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u6_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u6_spi_apb`] +#[doc = "clk_u6_spi_apb (rw) register accessor: U6 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u6_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u6_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u6_spi_apb`] module"] pub type CLK_U6_SPI_APB = crate::Reg; #[doc = "U6 Clock SPI APB"] pub mod clk_u6_spi_apb; -#[doc = "clk_u0_i2c_apb (rw) register accessor: U0 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_i2c_apb`] +#[doc = "clk_u0_i2c_apb (rw) register accessor: U0 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_i2c_apb`] module"] pub type CLK_U0_I2C_APB = crate::Reg; #[doc = "U0 Clock I2C APB"] pub mod clk_u0_i2c_apb; -#[doc = "clk_u1_i2c_apb (rw) register accessor: U1 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_i2c_apb`] +#[doc = "clk_u1_i2c_apb (rw) register accessor: U1 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_i2c_apb`] module"] pub type CLK_U1_I2C_APB = crate::Reg; #[doc = "U1 Clock I2C APB"] pub mod clk_u1_i2c_apb; -#[doc = "clk_u2_i2c_apb (rw) register accessor: U2 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u2_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u2_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u2_i2c_apb`] +#[doc = "clk_u2_i2c_apb (rw) register accessor: U2 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u2_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u2_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u2_i2c_apb`] module"] pub type CLK_U2_I2C_APB = crate::Reg; #[doc = "U2 Clock I2C APB"] pub mod clk_u2_i2c_apb; -#[doc = "clk_u3_i2c_apb (rw) register accessor: U3 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u3_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u3_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u3_i2c_apb`] +#[doc = "clk_u3_i2c_apb (rw) register accessor: U3 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u3_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u3_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u3_i2c_apb`] module"] pub type CLK_U3_I2C_APB = crate::Reg; #[doc = "U3 Clock I2C APB"] pub mod clk_u3_i2c_apb; -#[doc = "clk_u4_i2c_apb (rw) register accessor: U4 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u4_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u4_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u4_i2c_apb`] +#[doc = "clk_u4_i2c_apb (rw) register accessor: U4 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u4_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u4_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u4_i2c_apb`] module"] pub type CLK_U4_I2C_APB = crate::Reg; #[doc = "U4 Clock I2C APB"] pub mod clk_u4_i2c_apb; -#[doc = "clk_u5_i2c_apb (rw) register accessor: U5 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u5_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u5_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u5_i2c_apb`] +#[doc = "clk_u5_i2c_apb (rw) register accessor: U5 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u5_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u5_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u5_i2c_apb`] module"] pub type CLK_U5_I2C_APB = crate::Reg; #[doc = "U5 Clock I2C APB"] pub mod clk_u5_i2c_apb; -#[doc = "clk_u6_i2c_apb (rw) register accessor: U6 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u6_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u6_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u6_i2c_apb`] +#[doc = "clk_u6_i2c_apb (rw) register accessor: U6 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u6_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u6_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u6_i2c_apb`] module"] pub type CLK_U6_I2C_APB = crate::Reg; #[doc = "U6 Clock I2C APB"] pub mod clk_u6_i2c_apb; -#[doc = "clk_u0_uart_apb (rw) register accessor: U0 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_uart_apb`] +#[doc = "clk_u0_uart_apb (rw) register accessor: U0 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_uart_apb`] module"] pub type CLK_U0_UART_APB = crate::Reg; #[doc = "U0 Clock UART APB"] pub mod clk_u0_uart_apb; -#[doc = "clk_u0_uart_core (rw) register accessor: U0 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_uart_core`] +#[doc = "clk_u0_uart_core (rw) register accessor: U0 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_uart_core`] module"] pub type CLK_U0_UART_CORE = crate::Reg; #[doc = "U0 Clock UART Core"] pub mod clk_u0_uart_core; -#[doc = "clk_u1_uart_apb (rw) register accessor: U1 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_uart_apb`] +#[doc = "clk_u1_uart_apb (rw) register accessor: U1 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_uart_apb`] module"] pub type CLK_U1_UART_APB = crate::Reg; #[doc = "U1 Clock UART APB"] pub mod clk_u1_uart_apb; -#[doc = "clk_u1_uart_core (rw) register accessor: U1 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_uart_core`] +#[doc = "clk_u1_uart_core (rw) register accessor: U1 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_uart_core`] module"] pub type CLK_U1_UART_CORE = crate::Reg; #[doc = "U1 Clock UART Core"] pub mod clk_u1_uart_core; -#[doc = "clk_u2_uart_apb (rw) register accessor: U2 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u2_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u2_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u2_uart_apb`] +#[doc = "clk_u2_uart_apb (rw) register accessor: U2 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u2_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u2_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u2_uart_apb`] module"] pub type CLK_U2_UART_APB = crate::Reg; #[doc = "U2 Clock UART APB"] pub mod clk_u2_uart_apb; -#[doc = "clk_u2_uart_core (rw) register accessor: U2 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u2_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u2_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u2_uart_core`] +#[doc = "clk_u2_uart_core (rw) register accessor: U2 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u2_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u2_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u2_uart_core`] module"] pub type CLK_U2_UART_CORE = crate::Reg; #[doc = "U2 Clock UART Core"] pub mod clk_u2_uart_core; -#[doc = "clk_u3_uart_apb (rw) register accessor: U3 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u3_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u3_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u3_uart_apb`] +#[doc = "clk_u3_uart_apb (rw) register accessor: U3 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u3_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u3_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u3_uart_apb`] module"] pub type CLK_U3_UART_APB = crate::Reg; #[doc = "U3 Clock UART APB"] pub mod clk_u3_uart_apb; -#[doc = "clk_u3_uart_core (rw) register accessor: U3 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u3_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u3_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u3_uart_core`] +#[doc = "clk_u3_uart_core (rw) register accessor: U3 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u3_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u3_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u3_uart_core`] module"] pub type CLK_U3_UART_CORE = crate::Reg; #[doc = "U3 Clock UART Core"] pub mod clk_u3_uart_core; -#[doc = "clk_u4_uart_apb (rw) register accessor: U4 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u4_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u4_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u4_uart_apb`] +#[doc = "clk_u4_uart_apb (rw) register accessor: U4 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u4_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u4_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u4_uart_apb`] module"] pub type CLK_U4_UART_APB = crate::Reg; #[doc = "U4 Clock UART APB"] pub mod clk_u4_uart_apb; -#[doc = "clk_u4_uart_core (rw) register accessor: U4 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u4_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u4_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u4_uart_core`] +#[doc = "clk_u4_uart_core (rw) register accessor: U4 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u4_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u4_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u4_uart_core`] module"] pub type CLK_U4_UART_CORE = crate::Reg; #[doc = "U4 Clock UART Core"] pub mod clk_u4_uart_core; -#[doc = "clk_u5_uart_apb (rw) register accessor: U5 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u5_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u5_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u5_uart_apb`] +#[doc = "clk_u5_uart_apb (rw) register accessor: U5 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u5_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u5_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u5_uart_apb`] module"] pub type CLK_U5_UART_APB = crate::Reg; #[doc = "U5 Clock UART APB"] pub mod clk_u5_uart_apb; -#[doc = "clk_u5_uart_core (rw) register accessor: U5 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u5_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u5_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u5_uart_core`] +#[doc = "clk_u5_uart_core (rw) register accessor: U5 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u5_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u5_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u5_uart_core`] module"] pub type CLK_U5_UART_CORE = crate::Reg; #[doc = "U5 Clock UART Core"] pub mod clk_u5_uart_core; -#[doc = "clk_pwmdac_apb (rw) register accessor: Clock PWMDAC APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pwmdac_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pwmdac_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pwmdac_apb`] +#[doc = "clk_pwmdac_apb (rw) register accessor: Clock PWMDAC APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pwmdac_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pwmdac_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pwmdac_apb`] module"] pub type CLK_PWMDAC_APB = crate::Reg; #[doc = "Clock PWMDAC APB"] pub mod clk_pwmdac_apb; -#[doc = "clk_pwmdac_core (rw) register accessor: Clock PWMDAC Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pwmdac_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pwmdac_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pwmdac_core`] +#[doc = "clk_pwmdac_core (rw) register accessor: Clock PWMDAC Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pwmdac_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pwmdac_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pwmdac_core`] module"] pub type CLK_PWMDAC_CORE = crate::Reg; #[doc = "Clock PWMDAC Core"] pub mod clk_pwmdac_core; -#[doc = "clk_spdif_apb (rw) register accessor: Clock SPDIF APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_spdif_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_spdif_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_spdif_apb`] +#[doc = "clk_spdif_apb (rw) register accessor: Clock SPDIF APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_spdif_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_spdif_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_spdif_apb`] module"] pub type CLK_SPDIF_APB = crate::Reg; #[doc = "Clock SPDIF APB"] pub mod clk_spdif_apb; -#[doc = "clk_spdif_core (rw) register accessor: Clock SPDIF Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_spdif_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_spdif_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_spdif_core`] +#[doc = "clk_spdif_core (rw) register accessor: Clock SPDIF Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_spdif_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_spdif_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_spdif_core`] module"] pub type CLK_SPDIF_CORE = crate::Reg; #[doc = "Clock SPDIF Core"] pub mod clk_spdif_core; -#[doc = "clk_u0_i2s_tx_apb (rw) register accessor: U0 Clock I2S TX APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2s_tx_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2s_tx_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_i2s_tx_apb`] +#[doc = "clk_u0_i2s_tx_apb (rw) register accessor: U0 Clock I2S TX APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2s_tx_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2s_tx_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_i2s_tx_apb`] module"] pub type CLK_U0_I2S_TX_APB = crate::Reg; #[doc = "U0 Clock I2S TX APB"] pub mod clk_u0_i2s_tx_apb; -#[doc = "clk_u0_i2stx_4ch0_bclk_mst (rw) register accessor: U0 Clock I2S TX 0 BCLK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_4ch0_bclk_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_4ch0_bclk_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_i2stx_4ch0_bclk_mst`] +#[doc = "clk_u0_i2stx_4ch0_bclk_mst (rw) register accessor: U0 Clock I2S TX 0 BCLK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_4ch0_bclk_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_4ch0_bclk_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_i2stx_4ch0_bclk_mst`] module"] pub type CLK_U0_I2STX_4CH0_BCLK_MST = crate::Reg; #[doc = "U0 Clock I2S TX 0 BCLK MST"] pub mod clk_u0_i2stx_4ch0_bclk_mst; -#[doc = "clk_u0_i2stx_4ch0_bclk_mst_inv (rw) register accessor: U0 Clock I2S TX 0 BCLK MST Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_4ch0_bclk_mst_inv::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_4ch0_bclk_mst_inv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_i2stx_4ch0_bclk_mst_inv`] +#[doc = "clk_u0_i2stx_4ch0_bclk_mst_inv (rw) register accessor: U0 Clock I2S TX 0 BCLK MST Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_4ch0_bclk_mst_inv::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_4ch0_bclk_mst_inv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_i2stx_4ch0_bclk_mst_inv`] module"] pub type CLK_U0_I2STX_4CH0_BCLK_MST_INV = crate::Reg; #[doc = "U0 Clock I2S TX 0 BCLK MST Inverter"] pub mod clk_u0_i2stx_4ch0_bclk_mst_inv; -#[doc = "clk_i2stx0_lrck_mst (rw) register accessor: Clock I2S TX 0 LRCK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2stx0_lrck_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2stx0_lrck_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2stx0_lrck_mst`] +#[doc = "clk_i2stx0_lrck_mst (rw) register accessor: Clock I2S TX 0 LRCK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2stx0_lrck_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2stx0_lrck_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2stx0_lrck_mst`] module"] pub type CLK_I2STX0_LRCK_MST = crate::Reg; #[doc = "Clock I2S TX 0 LRCK MST"] pub mod clk_i2stx0_lrck_mst; -#[doc = "clk_u0_i2stx_bclk (rw) register accessor: U0 Clock I2S TX BCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_bclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_bclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_i2stx_bclk`] +#[doc = "clk_u0_i2stx_bclk (rw) register accessor: U0 Clock I2S TX BCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_bclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_bclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_i2stx_bclk`] module"] pub type CLK_U0_I2STX_BCLK = crate::Reg; #[doc = "U0 Clock I2S TX BCLK"] pub mod clk_u0_i2stx_bclk; -#[doc = "clk_u0_i2stx_bclk_neg (rw) register accessor: U0 Clock I2S TX BCLK Negative\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_bclk_neg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_bclk_neg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_i2stx_bclk_neg`] +#[doc = "clk_u0_i2stx_bclk_neg (rw) register accessor: U0 Clock I2S TX BCLK Negative\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_bclk_neg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_bclk_neg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_i2stx_bclk_neg`] module"] pub type CLK_U0_I2STX_BCLK_NEG = crate::Reg; #[doc = "U0 Clock I2S TX BCLK Negative"] pub mod clk_u0_i2stx_bclk_neg; -#[doc = "clk_u0_i2stx_lrck (rw) register accessor: U0 Clock I2S TX LRCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_lrck::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_lrck::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_i2stx_lrck`] +#[doc = "clk_u0_i2stx_lrck (rw) register accessor: U0 Clock I2S TX LRCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_lrck::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_lrck::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_i2stx_lrck`] module"] pub type CLK_U0_I2STX_LRCK = crate::Reg; #[doc = "U0 Clock I2S TX LRCK"] pub mod clk_u0_i2stx_lrck; -#[doc = "clk_u1_i2s_tx_apb (rw) register accessor: U1 Clock I2S TX APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2s_tx_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2s_tx_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_i2s_tx_apb`] +#[doc = "clk_u1_i2s_tx_apb (rw) register accessor: U1 Clock I2S TX APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2s_tx_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2s_tx_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_i2s_tx_apb`] module"] pub type CLK_U1_I2S_TX_APB = crate::Reg; #[doc = "U1 Clock I2S TX APB"] pub mod clk_u1_i2s_tx_apb; -#[doc = "clk_u1_i2stx_4ch1_bclk_mst (rw) register accessor: U1 Clock I2S TX 1 BCLK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_4ch1_bclk_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_4ch1_bclk_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_i2stx_4ch1_bclk_mst`] +#[doc = "clk_u1_i2stx_4ch1_bclk_mst (rw) register accessor: U1 Clock I2S TX 1 BCLK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_4ch1_bclk_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_4ch1_bclk_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_i2stx_4ch1_bclk_mst`] module"] pub type CLK_U1_I2STX_4CH1_BCLK_MST = crate::Reg; #[doc = "U1 Clock I2S TX 1 BCLK MST"] pub mod clk_u1_i2stx_4ch1_bclk_mst; -#[doc = "clk_u1_i2stx_4ch1_bclk_mst_inv (rw) register accessor: U1 Clock I2S TX 1 BCLK MST Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_4ch1_bclk_mst_inv::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_4ch1_bclk_mst_inv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_i2stx_4ch1_bclk_mst_inv`] +#[doc = "clk_u1_i2stx_4ch1_bclk_mst_inv (rw) register accessor: U1 Clock I2S TX 1 BCLK MST Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_4ch1_bclk_mst_inv::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_4ch1_bclk_mst_inv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_i2stx_4ch1_bclk_mst_inv`] module"] pub type CLK_U1_I2STX_4CH1_BCLK_MST_INV = crate::Reg; #[doc = "U1 Clock I2S TX 1 BCLK MST Inverter"] pub mod clk_u1_i2stx_4ch1_bclk_mst_inv; -#[doc = "clk_i2stx1_lrck_mst (rw) register accessor: Clock I2S TX 1 LRCK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2stx1_lrck_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2stx1_lrck_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2stx1_lrck_mst`] +#[doc = "clk_i2stx1_lrck_mst (rw) register accessor: Clock I2S TX 1 LRCK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2stx1_lrck_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2stx1_lrck_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2stx1_lrck_mst`] module"] pub type CLK_I2STX1_LRCK_MST = crate::Reg; #[doc = "Clock I2S TX 1 LRCK MST"] pub mod clk_i2stx1_lrck_mst; -#[doc = "clk_u1_i2stx_bclk (rw) register accessor: U1 Clock I2S TX BCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_bclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_bclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_i2stx_bclk`] +#[doc = "clk_u1_i2stx_bclk (rw) register accessor: U1 Clock I2S TX BCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_bclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_bclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_i2stx_bclk`] module"] pub type CLK_U1_I2STX_BCLK = crate::Reg; #[doc = "U1 Clock I2S TX BCLK"] pub mod clk_u1_i2stx_bclk; -#[doc = "clk_u1_i2stx_bclk_neg (rw) register accessor: U1 Clock I2S TX BCLK Negative\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_bclk_neg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_bclk_neg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_i2stx_bclk_neg`] +#[doc = "clk_u1_i2stx_bclk_neg (rw) register accessor: U1 Clock I2S TX BCLK Negative\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_bclk_neg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_bclk_neg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_i2stx_bclk_neg`] module"] pub type CLK_U1_I2STX_BCLK_NEG = crate::Reg; #[doc = "U1 Clock I2S TX BCLK Negative"] pub mod clk_u1_i2stx_bclk_neg; -#[doc = "clk_u1_i2stx_lrck (rw) register accessor: U1 Clock I2S TX LRCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_lrck::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_lrck::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_i2stx_lrck`] +#[doc = "clk_u1_i2stx_lrck (rw) register accessor: U1 Clock I2S TX LRCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_lrck::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_lrck::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_i2stx_lrck`] module"] pub type CLK_U1_I2STX_LRCK = crate::Reg; #[doc = "U1 Clock I2S TX LRCK"] pub mod clk_u1_i2stx_lrck; -#[doc = "clk_i2s_apb (rw) register accessor: Clock I2S APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2s_apb`] +#[doc = "clk_i2s_apb (rw) register accessor: Clock I2S APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2s_apb`] module"] pub type CLK_I2S_APB = crate::Reg; #[doc = "Clock I2S APB"] pub mod clk_i2s_apb; -#[doc = "clk_i2s_bclk_mst (rw) register accessor: Clock I2S BCLK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_bclk_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_bclk_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2s_bclk_mst`] +#[doc = "clk_i2s_bclk_mst (rw) register accessor: Clock I2S BCLK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_bclk_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_bclk_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2s_bclk_mst`] module"] pub type CLK_I2S_BCLK_MST = crate::Reg; #[doc = "Clock I2S BCLK MST"] pub mod clk_i2s_bclk_mst; -#[doc = "clk_i2s_bclk_mst_inv (rw) register accessor: Clock I2S BCLK MST Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_bclk_mst_inv::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_bclk_mst_inv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2s_bclk_mst_inv`] +#[doc = "clk_i2s_bclk_mst_inv (rw) register accessor: Clock I2S BCLK MST Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_bclk_mst_inv::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_bclk_mst_inv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2s_bclk_mst_inv`] module"] pub type CLK_I2S_BCLK_MST_INV = crate::Reg; #[doc = "Clock I2S BCLK MST Inverter"] pub mod clk_i2s_bclk_mst_inv; -#[doc = "clk_i2s_lrck_mst (rw) register accessor: Clock I2S LRCK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_lrck_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_lrck_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2s_lrck_mst`] +#[doc = "clk_i2s_lrck_mst (rw) register accessor: Clock I2S LRCK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_lrck_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_lrck_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2s_lrck_mst`] module"] pub type CLK_I2S_LRCK_MST = crate::Reg; #[doc = "Clock I2S LRCK MST"] pub mod clk_i2s_lrck_mst; -#[doc = "clk_i2s_bclk (rw) register accessor: Clock I2S BCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_bclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_bclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2s_bclk`] +#[doc = "clk_i2s_bclk (rw) register accessor: Clock I2S BCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_bclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_bclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2s_bclk`] module"] pub type CLK_I2S_BCLK = crate::Reg; #[doc = "Clock I2S BCLK"] pub mod clk_i2s_bclk; -#[doc = "clk_i2s_bclk_neg (rw) register accessor: Clock I2S BCLK Negative\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_bclk_neg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_bclk_neg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2s_bclk_neg`] +#[doc = "clk_i2s_bclk_neg (rw) register accessor: Clock I2S BCLK Negative\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_bclk_neg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_bclk_neg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2s_bclk_neg`] module"] pub type CLK_I2S_BCLK_NEG = crate::Reg; #[doc = "Clock I2S BCLK Negative"] pub mod clk_i2s_bclk_neg; -#[doc = "clk_i2s_lrck (rw) register accessor: Clock I2S LRCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_lrck::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_lrck::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2s_lrck`] +#[doc = "clk_i2s_lrck (rw) register accessor: Clock I2S LRCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_lrck::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_lrck::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2s_lrck`] module"] pub type CLK_I2S_LRCK = crate::Reg; #[doc = "Clock I2S LRCK"] pub mod clk_i2s_lrck; -#[doc = "clk_pdm_dmic (rw) register accessor: Clock PDM DMIC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pdm_dmic::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pdm_dmic::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pdm_dmic`] +#[doc = "clk_pdm_dmic (rw) register accessor: Clock PDM DMIC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pdm_dmic::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pdm_dmic::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pdm_dmic`] module"] pub type CLK_PDM_DMIC = crate::Reg; #[doc = "Clock PDM DMIC"] pub mod clk_pdm_dmic; -#[doc = "clk_pdm_apb (rw) register accessor: Clock PDM APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pdm_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pdm_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pdm_apb`] +#[doc = "clk_pdm_apb (rw) register accessor: Clock PDM APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pdm_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pdm_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pdm_apb`] module"] pub type CLK_PDM_APB = crate::Reg; #[doc = "Clock PDM APB"] pub mod clk_pdm_apb; -#[doc = "clk_tdm_ahb (rw) register accessor: Clock TDM AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tdm_ahb`] +#[doc = "clk_tdm_ahb (rw) register accessor: Clock TDM AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tdm_ahb`] module"] pub type CLK_TDM_AHB = crate::Reg; #[doc = "Clock TDM AHB"] pub mod clk_tdm_ahb; -#[doc = "clk_tdm_apb (rw) register accessor: Clock TDM APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tdm_apb`] +#[doc = "clk_tdm_apb (rw) register accessor: Clock TDM APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tdm_apb`] module"] pub type CLK_TDM_APB = crate::Reg; #[doc = "Clock TDM APB"] pub mod clk_tdm_apb; -#[doc = "clk_tdm_internal (rw) register accessor: Clock TDM Internal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm_internal::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm_internal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tdm_internal`] +#[doc = "clk_tdm_internal (rw) register accessor: Clock TDM Internal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm_internal::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm_internal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tdm_internal`] module"] pub type CLK_TDM_INTERNAL = crate::Reg; #[doc = "Clock TDM Internal"] pub mod clk_tdm_internal; -#[doc = "clk_tdm (rw) register accessor: Clock TDM\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tdm`] +#[doc = "clk_tdm (rw) register accessor: Clock TDM\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tdm`] module"] pub type CLK_TDM = crate::Reg; #[doc = "Clock TDM"] pub mod clk_tdm; -#[doc = "clk_tdm_neg (rw) register accessor: Clock TDM Negative\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm_neg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm_neg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tdm_neg`] +#[doc = "clk_tdm_neg (rw) register accessor: Clock TDM Negative\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm_neg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm_neg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tdm_neg`] module"] pub type CLK_TDM_NEG = crate::Reg; #[doc = "Clock TDM Negative"] pub mod clk_tdm_neg; -#[doc = "clk_jtag_cert_trng (rw) register accessor: Clock JTAG Certification TRNG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_jtag_cert_trng::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_jtag_cert_trng::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_jtag_cert_trng`] +#[doc = "clk_jtag_cert_trng (rw) register accessor: Clock JTAG Certification TRNG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_jtag_cert_trng::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_jtag_cert_trng::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_jtag_cert_trng`] module"] pub type CLK_JTAG_CERT_TRNG = crate::Reg; #[doc = "Clock JTAG Certification TRNG"] pub mod clk_jtag_cert_trng; -#[doc = "soft_rst0_addr_sel (rw) register accessor: Software RESET 0 Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst0_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst0_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_rst0_addr_sel`] +#[doc = "soft_rst0_addr_sel (rw) register accessor: Software RESET 0 Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst0_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst0_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_rst0_addr_sel`] module"] pub type SOFT_RST0_ADDR_SEL = crate::Reg; #[doc = "Software RESET 0 Address Selector"] pub mod soft_rst0_addr_sel; -#[doc = "soft_rst1_addr_sel (rw) register accessor: Software RESET 1 Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst1_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst1_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_rst1_addr_sel`] +#[doc = "soft_rst1_addr_sel (rw) register accessor: Software RESET 1 Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst1_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst1_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_rst1_addr_sel`] module"] pub type SOFT_RST1_ADDR_SEL = crate::Reg; #[doc = "Software RESET 1 Address Selector"] pub mod soft_rst1_addr_sel; -#[doc = "soft_rst2_addr_sel (rw) register accessor: Software RESET 2 Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst2_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst2_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_rst2_addr_sel`] +#[doc = "soft_rst2_addr_sel (rw) register accessor: Software RESET 2 Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst2_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst2_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_rst2_addr_sel`] module"] pub type SOFT_RST2_ADDR_SEL = crate::Reg; #[doc = "Software RESET 2 Address Selector"] pub mod soft_rst2_addr_sel; -#[doc = "soft_rst3_addr_sel (rw) register accessor: Software RESET 3 Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst3_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst3_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_rst3_addr_sel`] +#[doc = "soft_rst3_addr_sel (rw) register accessor: Software RESET 3 Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst3_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst3_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_rst3_addr_sel`] module"] pub type SOFT_RST3_ADDR_SEL = crate::Reg; #[doc = "Software RESET 3 Address Selector"] pub mod soft_rst3_addr_sel; -#[doc = "syscrg_rst0_status (rw) register accessor: SYSCRG RESET Status 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscrg_rst0_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscrg_rst0_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`syscrg_rst0_status`] +#[doc = "syscrg_rst0_status (rw) register accessor: SYSCRG RESET Status 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscrg_rst0_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscrg_rst0_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syscrg_rst0_status`] module"] pub type SYSCRG_RST0_STATUS = crate::Reg; #[doc = "SYSCRG RESET Status 0"] pub mod syscrg_rst0_status; -#[doc = "syscrg_rst1_status (rw) register accessor: SYSCRG RESET Status 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscrg_rst1_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscrg_rst1_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`syscrg_rst1_status`] +#[doc = "syscrg_rst1_status (rw) register accessor: SYSCRG RESET Status 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscrg_rst1_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscrg_rst1_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syscrg_rst1_status`] module"] pub type SYSCRG_RST1_STATUS = crate::Reg; #[doc = "SYSCRG RESET Status 1"] pub mod syscrg_rst1_status; -#[doc = "syscrg_rst2_status (rw) register accessor: SYSCRG RESET Status 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscrg_rst2_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscrg_rst2_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`syscrg_rst2_status`] +#[doc = "syscrg_rst2_status (rw) register accessor: SYSCRG RESET Status 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscrg_rst2_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscrg_rst2_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syscrg_rst2_status`] module"] pub type SYSCRG_RST2_STATUS = crate::Reg; #[doc = "SYSCRG RESET Status 2"] pub mod syscrg_rst2_status; -#[doc = "syscrg_rst3_status (rw) register accessor: SYSCRG RESET Status 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscrg_rst3_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscrg_rst3_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`syscrg_rst3_status`] +#[doc = "syscrg_rst3_status (rw) register accessor: SYSCRG RESET Status 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscrg_rst3_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscrg_rst3_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syscrg_rst3_status`] module"] pub type SYSCRG_RST3_STATUS = crate::Reg; #[doc = "SYSCRG RESET Status 3"] diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_ahb0.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_ahb0.rs index 91788fe..a85782e 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_ahb0.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_ahb0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_ahb1.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_ahb1.rs index ad10aff..bcca7f9 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_ahb1.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_ahb1.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_apb0.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_apb0.rs index 9c05437..78dba35 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_apb0.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_apb0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_apb_bus.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_apb_bus.rs index e966b6f..a9cba95 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_apb_bus.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_apb_bus.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=8, Default=4, Min=4, Typical=4"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=8, Default=4, Min=4, Typical=4"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=8, Default=4, Min=4, Typical=4"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=8, Default=4, Min=4, Typical=4"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_audio_root.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_audio_root.rs index 75c8d95..9125669 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_audio_root.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_audio_root.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0.rs index 4dce62b..6c54140 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0_dec_hifi4.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0_dec_hifi4.rs index c890675..373d243 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0_dec_hifi4.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0_dec_hifi4.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0_dec_main.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0_dec_main.rs index 76e506a..f0065f2 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0_dec_main.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0_dec_main.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0_dec_main_div.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0_dec_main_div.rs index 6f8f14f..863b387 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0_dec_main_div.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_axi_cfg0_dec_main_div.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_aximem_128b_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_aximem_128b_axi.rs index 47a418f..6e444cb 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_aximem_128b_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_aximem_128b_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_bus_root.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_bus_root.rs index 86e92ad..2d6e4b1 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_bus_root.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_bus_root.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_osc, clk_pll2"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_osc, clk_pll2"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc, clk_pll2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc, clk_pll2"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_codaj12_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_codaj12_apb.rs index 2a4af22..600ba47 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_codaj12_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_codaj12_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_codaj12_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_codaj12_axi.rs index c580dd2..6606a92 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_codaj12_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_codaj12_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_codaj12_core.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_codaj12_core.rs index f89dfcd..3357d7f 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_codaj12_core.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_codaj12_core.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_cpu_bus.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_cpu_bus.rs index 26be7e4..7a7d6eb 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_cpu_bus.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_cpu_bus.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_cpu_core.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_cpu_core.rs index 384f907..9c38337 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_cpu_core.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_cpu_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=7, Default=1, Min=1, Typical=1"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=7, Default=1, Min=1, Typical=1"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=1, Min=1, Typical=1"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=1, Min=1, Typical=1"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_cpu_root.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_cpu_root.rs index 82bc559..266f212 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_cpu_root.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_cpu_root.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_osc, clk_pll0"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_osc, clk_pll0"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc, clk_pll0"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc, clk_pll0"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_ddr_bus.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_ddr_bus.rs index 137a83a..2e27aa6 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_ddr_bus.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_ddr_bus.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_osc_div2, clk_pll1_div4, clk_pll1_div8"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_osc_div2, clk_pll1_div4, clk_pll1_div8"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc_div2, clk_pll1_div4, clk_pll1_div8"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc_div2, clk_pll1_div4, clk_pll1_div8"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gclk0.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gclk0.rs index 75b6bb8..72b3b30 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gclk0.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gclk0.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=62, Default=20, Min=16, Typical=20"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=62, Default=20, Min=16, Typical=20"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=62, Default=20, Min=16, Typical=20"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=62, Default=20, Min=16, Typical=20"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gclk1.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gclk1.rs index 5a6bb9a..15bdaa3 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gclk1.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gclk1.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=62, Default=16, Min=16, Typical=16"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=62, Default=16, Min=16, Typical=16"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=62, Default=16, Min=16, Typical=16"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=62, Default=16, Min=16, Typical=16"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gclk2.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gclk2.rs index a8d8c4f..117e6fc 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gclk2.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gclk2.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=62, Default=12, Min=12, Typical=12"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=62, Default=12, Min=12, Typical=12"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=62, Default=12, Min=12, Typical=12"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=62, Default=12, Min=12, Typical=12"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac0_gtx.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac0_gtx.rs index 34c7c0b..d82deb0 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac0_gtx.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac0_gtx.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac0_gtxclk.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac0_gtxclk.rs index 97b4fb7..ac2076f 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac0_gtxclk.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac0_gtxclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `dly_chain_sel` reader - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] pub type DLY_CHAIN_SEL_R = crate::FieldReader; #[doc = "Field `dly_chain_sel` writer - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] -pub type DLY_CHAIN_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type DLY_CHAIN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] #[inline(always)] #[must_use] - pub fn dly_chain_sel(&mut self) -> DLY_CHAIN_SEL_W { - DLY_CHAIN_SEL_W::new(self) + pub fn dly_chain_sel(&mut self) -> DLY_CHAIN_SEL_W { + DLY_CHAIN_SEL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac0_ptp.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac0_ptp.rs index 88a3a57..b187a1a 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac0_ptp.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac0_ptp.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac1_gtx.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac1_gtx.rs index 6a5b29a..b68f2f3 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac1_gtx.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac1_gtx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac1_gtxclk.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac1_gtxclk.rs index 0f9d180..b9d1c17 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac1_gtxclk.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac1_gtxclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `dly_chain_sel` reader - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] pub type DLY_CHAIN_SEL_R = crate::FieldReader; #[doc = "Field `dly_chain_sel` writer - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] -pub type DLY_CHAIN_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type DLY_CHAIN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] #[inline(always)] #[must_use] - pub fn dly_chain_sel(&mut self) -> DLY_CHAIN_SEL_W { - DLY_CHAIN_SEL_W::new(self) + pub fn dly_chain_sel(&mut self) -> DLY_CHAIN_SEL_W { + DLY_CHAIN_SEL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac1_rmii_rtx.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac1_rmii_rtx.rs index 70b2160..e3dc263 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac1_rmii_rtx.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac1_rmii_rtx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_ahb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_ahb.rs index 862dd40..fbadb98 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_ahb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_axi.rs index e651602..f0d4aea 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_ptp.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_ptp.rs index fb3b1d1..9b633b1 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_ptp.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_ptp.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=10"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=10"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=10"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=10"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_rx.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_rx.rs index 93a41ff..c855d81 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_rx.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_rx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `dly_chain_sel` reader - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] pub type DLY_CHAIN_SEL_R = crate::FieldReader; #[doc = "Field `dly_chain_sel` writer - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] -pub type DLY_CHAIN_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type DLY_CHAIN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] #[inline(always)] #[must_use] - pub fn dly_chain_sel(&mut self) -> DLY_CHAIN_SEL_W { - DLY_CHAIN_SEL_W::new(self) + pub fn dly_chain_sel(&mut self) -> DLY_CHAIN_SEL_W { + DLY_CHAIN_SEL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_rxi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_rxi.rs index d6319fd..c25f010 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_rxi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_rxi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_tx.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_tx.rs index 2c32863..3a26f2e 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_tx.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_tx.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_gmac1_gtxclk, clk_gmac1_rmii_rtx"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_gmac1_gtxclk, clk_gmac1_rmii_rtx"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_gmac1_gtxclk, clk_gmac1_rmii_rtx"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_gmac1_gtxclk, clk_gmac1_rmii_rtx"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_txi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_txi.rs index cdf4136..644dbbf 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_txi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac5_axi64_txi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac_phy.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac_phy.rs index 2ec54ad..fb7d26b 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac_phy.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac_phy.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac_src.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac_src.rs index d6c5f28..84f0e8a 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gmac_src.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gmac_src.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gpu_core.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gpu_core.rs index 66e7b9c..eaed536 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gpu_core.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gpu_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_gpu_root.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_gpu_root.rs index bdf56a7..1fd5f7d 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_gpu_root.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_gpu_root.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_pll2, clk_pll1"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_pll2, clk_pll1"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_pll2, clk_pll1"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_pll2, clk_pll1"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_hifi4_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_hifi4_axi.rs index 2365a5a..924caf4 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_hifi4_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_hifi4_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_hifi4_core.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_hifi4_core.rs index f50cf93..1d615cb 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_hifi4_core.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_hifi4_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=3, Min=3, Typical=3"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=3, Min=3, Typical=3"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=3, Min=3, Typical=3"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=3, Min=3, Typical=3"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_apb.rs index c45c6ba..8a79cd7 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk.rs index b110e16..96f3475 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2srx_3ch_bclk_mst, clk_i2srx_3ch_bclk_ext"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2srx_3ch_bclk_mst, clk_i2srx_3ch_bclk_ext"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2srx_3ch_bclk_mst, clk_i2srx_3ch_bclk_ext"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2srx_3ch_bclk_mst, clk_i2srx_3ch_bclk_ext"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk_mst.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk_mst.rs index c3e862f..e153a25 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk_mst.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk_mst.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk_mst_inv.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk_mst_inv.rs index fff0423..cfe8e93 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk_mst_inv.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk_mst_inv.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk_neg.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk_neg.rs index 161efa0..dc75f6a 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk_neg.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_bclk_neg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_lrck.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_lrck.rs index 3ba9dcc..665875a 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_lrck.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_lrck.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2srx_3ch_lrck_mst, clk_i2srx_3ch_lrck_ext"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2srx_3ch_lrck_mst, clk_i2srx_3ch_lrck_ext"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2srx_3ch_lrck_mst, clk_i2srx_3ch_lrck_ext"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2srx_3ch_lrck_mst, clk_i2srx_3ch_lrck_ext"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_lrck_mst.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_lrck_mst.rs index 9acee21..f7f1804 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_lrck_mst.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_i2s_lrck_mst.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2srx_3ch_bclk_mst_inv, clk_i2srx_3ch_bclk_mst"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2srx_3ch_bclk_mst_inv, clk_i2srx_3ch_bclk_mst"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2srx_3ch_bclk_mst_inv, clk_i2srx_3ch_bclk_mst"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_i2stx0_lrck_mst.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_i2stx0_lrck_mst.rs index fb410b5..5c877fd 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_i2stx0_lrck_mst.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_i2stx0_lrck_mst.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_i2stx1_lrck_mst.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_i2stx1_lrck_mst.rs index 2c819c1..e5dbd15 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_i2stx1_lrck_mst.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_i2stx1_lrck_mst.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_internal_ctrl_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_internal_ctrl_apb.rs index dcc67ea..712100c 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_internal_ctrl_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_internal_ctrl_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_isp_2x.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_isp_2x.rs index 6fc6124..206776d 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_isp_2x.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_isp_2x.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_pll2, clk_pll1"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_pll2, clk_pll1"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bits 24:29 - Clock multiplexing selector: clk_pll2, clk_pll1"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_isp_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_isp_axi.rs index 7a88458..9d1b58b 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_isp_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_isp_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=4, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=4, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=4, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=4, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_jpeg_codec_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_jpeg_codec_axi.rs index e41037b..f76afb3 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_jpeg_codec_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_jpeg_codec_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_jtag_cert_trng.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_jtag_cert_trng.rs index 26aebd6..bfdcc02 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_jtag_cert_trng.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_jtag_cert_trng.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_mbox_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_mbox_apb.rs index 2941b9d..7c5f0d5 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_mbox_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_mbox_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_mclk.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_mclk.rs index 3929cc8..86cc786 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_mclk.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_mclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_mclk_inner, clk_mclk_ext"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_mclk_inner, clk_mclk_ext"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_mclk_inner, clk_mclk_ext"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_mclk_inner, clk_mclk_ext"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_mclk_inner.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_mclk_inner.rs index 20c8df0..62e7801 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_mclk_inner.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_mclk_inner.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=64, Default=12, Min=12, Typical=12"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=64, Default=12, Min=12, Typical=12"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=12, Min=12, Typical=12"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=12, Min=12, Typical=12"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_mclk_out.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_mclk_out.rs index 31e1208..acd5d99 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_mclk_out.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_mclk_out.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_noc_display_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_noc_display_axi.rs index a6af042..885c675 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_noc_display_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_noc_display_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_noc_stg_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_noc_stg_axi.rs index d3cfb48..1f39705 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_noc_stg_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_noc_stg_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_noc_vdec_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_noc_vdec_axi.rs index c01c84d..593406b 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_noc_vdec_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_noc_vdec_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_noc_venc_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_noc_venc_axi.rs index 247d421..92b6791 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_noc_venc_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_noc_venc_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_nocstg_bus.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_nocstg_bus.rs index ae169fe..a2c2324 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_nocstg_bus.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_nocstg_bus.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_osc_div2.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_osc_div2.rs index d444e83..3bff3e8 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_osc_div2.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_osc_div2.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_pdm_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_pdm_apb.rs index ecbe03c..cc6aa36 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_pdm_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_pdm_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_pdm_dmic.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_pdm_dmic.rs index 5146d36..639e7a2 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_pdm_dmic.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_pdm_dmic.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=64, Default=8, Min=8, Typical=8"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=64, Default=8, Min=8, Typical=8"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=8, Min=8, Typical=8"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=8, Min=8, Typical=8"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_peripheral_root.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_peripheral_root.rs index a827f45..b5240dc 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_peripheral_root.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_peripheral_root.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_pll0, clk_pll2"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_pll0, clk_pll2"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bits 24:29 - Clock multiplexing selector: clk_pll0, clk_pll2"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_pll0_div2.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_pll0_div2.rs index 7334a5d..18ce371 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_pll0_div2.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_pll0_div2.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_pll1_div2.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_pll1_div2.rs index 82cf36d..3a3e98f 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_pll1_div2.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_pll1_div2.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_pll1_div4.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_pll1_div4.rs index 2886366..8f89227 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_pll1_div4.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_pll1_div4.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_pll1_div8.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_pll1_div8.rs index fa50861..4772516 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_pll1_div8.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_pll1_div8.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_pll2_div2.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_pll2_div2.rs index 0821186..cba9c86 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_pll2_div2.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_pll2_div2.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_pwm_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_pwm_apb.rs index 0ae7144..1fb7ce7 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_pwm_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_pwm_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_pwmdac_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_pwmdac_apb.rs index c255e14..50b0199 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_pwmdac_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_pwmdac_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_pwmdac_core.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_pwmdac_core.rs index 645b7f9..7f98f4f 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_pwmdac_core.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_pwmdac_core.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=256, Default=12, Min=12, Typical=12"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=256, Default=12, Min=12, Typical=12"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=256, Default=12, Min=12, Typical=12"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=256, Default=12, Min=12, Typical=12"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_qspi_ahb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_qspi_ahb.rs index 7745b73..4a38f05 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_qspi_ahb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_qspi_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_qspi_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_qspi_apb.rs index d3e51fd..388a0e9 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_qspi_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_qspi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_qspi_ref.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_qspi_ref.rs index 7074e20..66dabfb 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_qspi_ref.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_qspi_ref.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_osc, clk_qspi_ref_src"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_osc, clk_qspi_ref_src"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc, clk_qspi_ref_src"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc, clk_qspi_ref_src"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_qspi_ref_src.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_qspi_ref_src.rs index 2c3d475..fa61839 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_qspi_ref_src.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_qspi_ref_src.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=16, Default=10, Min=10, Typical=10"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=16, Default=10, Min=10, Typical=10"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=16, Default=10, Min=10, Typical=10"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=16, Default=10, Min=10, Typical=10"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_spdif_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_spdif_apb.rs index f874dc9..3e085ec 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_spdif_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_spdif_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_spdif_core.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_spdif_core.rs index baa6b5b..908827f 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_spdif_core.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_spdif_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_stg_axiahb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_stg_axiahb.rs index cf74983..29d6a58 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_stg_axiahb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_stg_axiahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_sys_iomux_pclk.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_sys_iomux_pclk.rs index 4e5836b..e382eb1 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_sys_iomux_pclk.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_sys_iomux_pclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_tdm.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_tdm.rs index 8d1fe67..81c8d42 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_tdm.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_tdm.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_tdm_internal, clk_tdm_ext"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_tdm_internal, clk_tdm_ext"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_tdm_internal, clk_tdm_ext"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_tdm_internal, clk_tdm_ext"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_tdm_ahb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_tdm_ahb.rs index a2f9e3a..b19c0ff 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_tdm_ahb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_tdm_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_tdm_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_tdm_apb.rs index a5cd1f0..6c73d4f 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_tdm_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_tdm_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_tdm_internal.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_tdm_internal.rs index b873e2b..e9ece3d 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_tdm_internal.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_tdm_internal.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=64, Default=1, Min=1, Typical=1"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=64, Default=1, Min=1, Typical=1"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=1, Min=1, Typical=1"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=1, Min=1, Typical=1"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_tdm_neg.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_tdm_neg.rs index 5174acf..439912c 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_tdm_neg.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_tdm_neg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_temp_sensor.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_temp_sensor.rs index 25bc858..b5c0cdd 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_temp_sensor.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_temp_sensor.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_temp_sensor_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_temp_sensor_apb.rs index bbabdca..2e83527 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_temp_sensor_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_temp_sensor_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_tim0.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_tim0.rs index 25d210d..5721d03 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_tim0.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_tim0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_tim1.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_tim1.rs index e8b9a9e..13d1e57 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_tim1.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_tim1.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_tim2.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_tim2.rs index f7e9121..6ecbe54 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_tim2.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_tim2.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_tim3.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_tim3.rs index 370f7c9..3488ff6 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_tim3.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_tim3.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_tim_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_tim_apb.rs index 9599c08..6e573c8 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_tim_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_tim_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_axi_cfg1_dec_clk_ahb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_axi_cfg1_dec_clk_ahb.rs index d3653f5..f721a34 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_axi_cfg1_dec_clk_ahb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_axi_cfg1_dec_clk_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_axi_cfg1_dec_clk_main.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_axi_cfg1_dec_clk_main.rs index 1411af5..fa92ab9 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_axi_cfg1_dec_clk_main.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_axi_cfg1_dec_clk_main.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_can_ctrl_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_can_ctrl_apb.rs index d0ebbc7..559c564 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_can_ctrl_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_can_ctrl_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_can_ctrl_can.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_can_ctrl_can.rs index 0d6e20b..bd42b8f 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_can_ctrl_can.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_can_ctrl_can.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_can_ctrl_tim.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_can_ctrl_tim.rs index 73074d0..db6bf3f 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_can_ctrl_tim.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_can_ctrl_tim.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_ddr_sft7110_clk_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_ddr_sft7110_clk_axi.rs index c628428..26f2529 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_ddr_sft7110_clk_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_ddr_sft7110_clk_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi.rs index 9beca33..267dffb 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,12 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg( - &mut self, - ) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x.rs index bec791a..244ea1b 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,12 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg( - &mut self, - ) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src.rs index 264349f..f60e500 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,12 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg( - &mut self, - ) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_gpu_rtc_toggle.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_gpu_rtc_toggle.rs index 853225e..5a49875 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_gpu_rtc_toggle.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_gpu_rtc_toggle.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=12, Default=12, Min=12, Typical=12"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=12, Default=12, Min=12, Typical=12"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=12, Default=12, Min=12, Typical=12"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=12, Default=12, Min=12, Typical=12"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2c_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2c_apb.rs index 9adb97c..551c406 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2c_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2c_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2s_tx_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2s_tx_apb.rs index 040b2d5..1afffd0 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2s_tx_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2s_tx_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_4ch0_bclk_mst.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_4ch0_bclk_mst.rs index d987243..4607fac 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_4ch0_bclk_mst.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_4ch0_bclk_mst.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_4ch0_bclk_mst_inv.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_4ch0_bclk_mst_inv.rs index 63baebd..7a7f775 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_4ch0_bclk_mst_inv.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_4ch0_bclk_mst_inv.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_bclk.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_bclk.rs index f23af1e..ee403e4 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_bclk.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_bclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst, clk_i2stx_bclk_ext"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst, clk_i2stx_bclk_ext"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst, clk_i2stx_bclk_ext"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst, clk_i2stx_bclk_ext"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_bclk_neg.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_bclk_neg.rs index 612bd4a..84eec10 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_bclk_neg.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_bclk_neg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_lrck.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_lrck.rs index 0c6a39f..c0e3740 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_lrck.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_i2stx_lrck.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2stx_4ch0_lrck_mst, clk_i2stx_lrck_ext"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2stx_4ch0_lrck_mst, clk_i2stx_lrck_ext"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch0_lrck_mst, clk_i2stx_lrck_ext"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch0_lrck_mst, clk_i2stx_lrck_ext"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_img_gpu_clk_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_img_gpu_clk_apb.rs index 837ea93..f7ed7bc 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_img_gpu_clk_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_img_gpu_clk_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_img_gpu_core_clk.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_img_gpu_core_clk.rs index ca73d06..2f382ce 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_img_gpu_core_clk.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_img_gpu_core_clk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_img_gpu_sys_clk.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_img_gpu_sys_clk.rs index e8ac3ae..9519339 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_img_gpu_sys_clk.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_img_gpu_sys_clk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sd_ahb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sd_ahb.rs index ffbc74f..3beb073 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sd_ahb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sd_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sd_card.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sd_card.rs index 913e591..214fe35 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sd_card.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sd_card.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_axicfg0_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_axicfg0_axi.rs index 14ec464..5576c9b 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_axicfg0_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_axicfg0_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_cpu_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_cpu_axi.rs index e9ffd14..06eac91 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_cpu_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_cpu_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_gpu_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_gpu_axi.rs index eecfbf6..d87b04e 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_gpu_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_gpu_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sft7110_noc_bux_clk_isp_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sft7110_noc_bux_clk_isp_axi.rs index 97bda8c..f8da2c3 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sft7110_noc_bux_clk_isp_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_sft7110_noc_bux_clk_isp_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_spi_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_spi_apb.rs index f629ac4..c8a8c3d 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_spi_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_spi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_uart_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_uart_apb.rs index 14f94d3..b6254b1 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_uart_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_uart_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_uart_core.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_uart_core.rs index d03321e..af24d86 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u0_uart_core.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u0_uart_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_can_ctrl_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_can_ctrl_apb.rs index 2d3ddc1..91bb2df 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_can_ctrl_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_can_ctrl_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_can_ctrl_can.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_can_ctrl_can.rs index f3ef999..1d6597c 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_can_ctrl_can.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_can_ctrl_can.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_can_ctrl_tim.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_can_ctrl_tim.rs index 59fda4d..baa9a9d 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_can_ctrl_tim.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_can_ctrl_tim.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2c_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2c_apb.rs index b109d7b..7eacf9c 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2c_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2c_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2s_tx_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2s_tx_apb.rs index 08fb166..2c64a0e 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2s_tx_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2s_tx_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_4ch1_bclk_mst.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_4ch1_bclk_mst.rs index 3311c15..8bb7661 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_4ch1_bclk_mst.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_4ch1_bclk_mst.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_4ch1_bclk_mst_inv.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_4ch1_bclk_mst_inv.rs index 6f33044..34a7fdf 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_4ch1_bclk_mst_inv.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_4ch1_bclk_mst_inv.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_bclk.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_bclk.rs index 2b90c32..751c872 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_bclk.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_bclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2stx_4ch1_bclk_mst, clk_i2stx_bclk_ext"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2stx_4ch1_bclk_mst, clk_i2stx_bclk_ext"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch1_bclk_mst, clk_i2stx_bclk_ext"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch1_bclk_mst, clk_i2stx_bclk_ext"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_bclk_neg.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_bclk_neg.rs index c69854f..52a542b 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_bclk_neg.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_bclk_neg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_lrck.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_lrck.rs index 1296825..c699878 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_lrck.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_i2stx_lrck.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2stx_4ch1_lrck_mst, clk_i2stx_lrck_ext"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2stx_4ch1_lrck_mst, clk_i2stx_lrck_ext"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch1_lrck_mst, clk_i2stx_lrck_ext"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch1_lrck_mst, clk_i2stx_lrck_ext"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_sd_ahb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_sd_ahb.rs index db57421..721548e 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_sd_ahb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_sd_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_sd_card.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_sd_card.rs index 381ffaf..99c4303 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_sd_card.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_sd_card.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_spi_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_spi_apb.rs index be9e4ee..79c5d4d 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_spi_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_spi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_uart_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_uart_apb.rs index 41da55e..a0dba7b 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_uart_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_uart_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_uart_core.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_uart_core.rs index be0fea1..84b7e7e 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u1_uart_core.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u1_uart_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u2_i2c_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u2_i2c_apb.rs index 844d1ee..ba1619e 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u2_i2c_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u2_i2c_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u2_spi_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u2_spi_apb.rs index 8e02071..5678f49 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u2_spi_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u2_spi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u2_uart_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u2_uart_apb.rs index 3def501..8ffe72c 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u2_uart_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u2_uart_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u2_uart_core.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u2_uart_core.rs index 1651273..558493f 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u2_uart_core.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u2_uart_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u3_i2c_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u3_i2c_apb.rs index 358bfe5..0c7fbe7 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u3_i2c_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u3_i2c_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u3_spi_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u3_spi_apb.rs index e88cbe1..e6ae423 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u3_spi_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u3_spi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u3_uart_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u3_uart_apb.rs index 79be0b1..09f186a 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u3_uart_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u3_uart_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u3_uart_core.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u3_uart_core.rs index 1f6c1fd..c7b7e79 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u3_uart_core.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u3_uart_core.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u4_i2c_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u4_i2c_apb.rs index 06c8bea..c276ad5 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u4_i2c_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u4_i2c_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u4_spi_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u4_spi_apb.rs index 9ea42ec..a597aa8 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u4_spi_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u4_spi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u4_uart_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u4_uart_apb.rs index 0897ec6..8f3aae2 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u4_uart_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u4_uart_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u4_uart_core.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u4_uart_core.rs index 39c3884..8a40590 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u4_uart_core.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u4_uart_core.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u5_i2c_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u5_i2c_apb.rs index 7c427b4..f33be86 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u5_i2c_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u5_i2c_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u5_spi_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u5_spi_apb.rs index bf7775c..cdab8dc 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u5_spi_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u5_spi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u5_uart_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u5_uart_apb.rs index 6692b1e..35f37a4 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u5_uart_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u5_uart_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u5_uart_core.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u5_uart_core.rs index bcbddb6..61d5279 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u5_uart_core.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u5_uart_core.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u6_i2c_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u6_i2c_apb.rs index 0e59082..ba496ed 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u6_i2c_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u6_i2c_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u6_spi_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u6_spi_apb.rs index 6fc3721..150f5f4 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u6_spi_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u6_spi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core0.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core0.rs index eda1657..3d1a8b0 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core0.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core1.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core1.rs index bca30e8..37797ad 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core1.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core1.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core2.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core2.rs index 58a976e..2051161 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core2.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core2.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core3.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core3.rs index acfefac..7f225e6 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core3.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core3.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core4.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core4.rs index ad29b28..1fc5258 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core4.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_core4.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_debug.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_debug.rs index 2cc9043..550262b 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_debug.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_debug.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace0.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace0.rs index 4745687..f7e648d 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace0.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace1.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace1.rs index 2eb77fa..6633efe 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace1.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace1.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace2.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace2.rs index 3768a89..1803426 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace2.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace2.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace3.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace3.rs index 8407a97..a7766ea 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace3.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace3.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace4.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace4.rs index fb02b26..1089592 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace4.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace4.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace_com.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace_com.rs index 48f2b75..106673f 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace_com.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_u7mc_trace_com.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_usb_125m.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_usb_125m.rs index cf1b913..3add98d 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_usb_125m.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_usb_125m.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_vdec_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_vdec_axi.rs index 8e3dc27..d3e92d5 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_vdec_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_vdec_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_venc_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_venc_axi.rs index d6daec4..6ba93e4 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_venc_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_venc_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_vout_ahb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_vout_ahb.rs index 4928864..f908152 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_vout_ahb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_vout_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_vout_axi_divcfg.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_vout_axi_divcfg.rs index 24e0339..0470524 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_vout_axi_divcfg.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_vout_axi_divcfg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_vout_axi_icg.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_vout_axi_icg.rs index d6c6b97..c79dccb 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_vout_axi_icg.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_vout_axi_icg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_vout_hdmi_tx0_mclk.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_vout_hdmi_tx0_mclk.rs index afe7731..de966b9 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_vout_hdmi_tx0_mclk.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_vout_hdmi_tx0_mclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_vout_mipi_phy.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_vout_mipi_phy.rs index 6b66d29..0eea4b3 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_vout_mipi_phy.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_vout_mipi_phy.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_wave420l_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_wave420l_apb.rs index 04791a2..321eb6f 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_wave420l_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_wave420l_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_wave420l_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_wave420l_axi.rs index 634fc09..bbc3254 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_wave420l_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_wave420l_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_wave420l_bpu.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_wave420l_bpu.rs index 88776c7..36ed24b 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_wave420l_bpu.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_wave420l_bpu.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_wave420l_vce.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_wave420l_vce.rs index 38f4298..28baaf9 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_wave420l_vce.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_wave420l_vce.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_apb.rs index 2f1e92d..ca4a7ec 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_axi.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_axi.rs index 7d01fe2..1eb107c 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_axi.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_bpu.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_bpu.rs index 4b1344d..aff7c45 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_bpu.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_bpu.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_jpg_arb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_jpg_arb.rs index da0bce6..18aaf68 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_jpg_arb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_jpg_arb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_jpg_main.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_jpg_main.rs index d54a5cd..2d6395d 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_jpg_main.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_jpg_main.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_vce.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_vce.rs index 2c1957b..6bb2382 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_vce.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_wave511_vce.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=7, Default=2, Min=3, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=7, Default=2, Min=3, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=2, Min=3, Typical=2"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=2, Min=3, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_wdt.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_wdt.rs index 416a9cd..dfd64d0 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_wdt.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_wdt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/clk_wdt_apb.rs b/jh7110-vf2-12a-pac/src/syscrg/clk_wdt_apb.rs index 558e6b7..4b63ed5 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/clk_wdt_apb.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/clk_wdt_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/soft_rst0_addr_sel.rs b/jh7110-vf2-12a-pac/src/syscrg/soft_rst0_addr_sel.rs index 05e5c2a..1690ed5 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/soft_rst0_addr_sel.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/soft_rst0_addr_sel.rs @@ -5,140 +5,131 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_jtag2apb_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_JTAG2APB_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_jtag2apb_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_JTAG2APB_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_JTAG2APB_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_sys_syscon_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SYS_SYSCON_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_sys_syscon_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SYS_SYSCON_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SYS_SYSCON_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_sys_iomux_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SYS_IOMUX_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_sys_iomux_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SYS_IOMUX_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SYS_IOMUX_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_bus` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_BUS_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_bus` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_BUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_BUS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_debug_reset` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_DEBUG_RESET_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_debug_reset` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_DEBUG_RESET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_DEBUG_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core0` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE0_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core1` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE1_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core1` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core2` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE2_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core2` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core3` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE3_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core3` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE3_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core4` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE4_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core4` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE4_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core0_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE0_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core0_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE0_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core1_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE1_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core1_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE1_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core2_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE2_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core2_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE2_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core3_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE3_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core3_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE3_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE3_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core4_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE4_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core4_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE4_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE4_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst0` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST0_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst1` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST1_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst1` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst2` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST2_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst2` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst3` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST3_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst3` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST3_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst4` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST4_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst4` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST4_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_com_rst` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_COM_RST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_com_rst` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_COM_RST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_COM_RST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_img_gpu_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_IMG_GPU_RSTN_APB_R = crate::BitReader; #[doc = "Field `rst_u0_img_gpu_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_IMG_GPU_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_IMG_GPU_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_img_gpu_rstn_doma` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_IMG_GPU_RSTN_DOMA_R = crate::BitReader; #[doc = "Field `rst_u0_img_gpu_rstn_doma` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_IMG_GPU_RSTN_DOMA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_IMG_GPU_RSTN_DOMA_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_apb_bus_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_apb_bus_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_axicfg0_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_axicfg0_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_cpu_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_cpu_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_disp_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_disp_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_gpu_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_gpu_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_isp_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_isp_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_ddrc_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_ddrc_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_stg_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_stg_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_vdec_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_vdec_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -325,258 +316,262 @@ impl W { #[must_use] pub fn rstn_u0_jtag2apb_presetn( &mut self, - ) -> RSTN_U0_JTAG2APB_PRESETN_W { - RSTN_U0_JTAG2APB_PRESETN_W::new(self) + ) -> RSTN_U0_JTAG2APB_PRESETN_W { + RSTN_U0_JTAG2APB_PRESETN_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_sys_syscon_presetn( &mut self, - ) -> RSTN_U0_SYS_SYSCON_PRESETN_W { - RSTN_U0_SYS_SYSCON_PRESETN_W::new(self) + ) -> RSTN_U0_SYS_SYSCON_PRESETN_W { + RSTN_U0_SYS_SYSCON_PRESETN_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_sys_iomux_presetn( &mut self, - ) -> RSTN_U0_SYS_IOMUX_PRESETN_W { - RSTN_U0_SYS_IOMUX_PRESETN_W::new(self) + ) -> RSTN_U0_SYS_IOMUX_PRESETN_W { + RSTN_U0_SYS_IOMUX_PRESETN_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_bus( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_BUS_W { - RST_U0_U7MC_SFT7110_RST_BUS_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_BUS_W { + RST_U0_U7MC_SFT7110_RST_BUS_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_debug_reset( &mut self, - ) -> RST_U0_U7MC_SFT7110_DEBUG_RESET_W { - RST_U0_U7MC_SFT7110_DEBUG_RESET_W::new(self) + ) -> RST_U0_U7MC_SFT7110_DEBUG_RESET_W { + RST_U0_U7MC_SFT7110_DEBUG_RESET_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core0( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE0_W { - RST_U0_U7MC_SFT7110_RST_CORE0_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE0_W { + RST_U0_U7MC_SFT7110_RST_CORE0_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core1( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE1_W { - RST_U0_U7MC_SFT7110_RST_CORE1_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE1_W { + RST_U0_U7MC_SFT7110_RST_CORE1_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core2( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE2_W { - RST_U0_U7MC_SFT7110_RST_CORE2_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE2_W { + RST_U0_U7MC_SFT7110_RST_CORE2_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core3( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE3_W { - RST_U0_U7MC_SFT7110_RST_CORE3_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE3_W { + RST_U0_U7MC_SFT7110_RST_CORE3_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core4( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE4_W { - RST_U0_U7MC_SFT7110_RST_CORE4_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE4_W { + RST_U0_U7MC_SFT7110_RST_CORE4_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core0_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE0_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE0_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE0_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE0_ST_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core1_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE1_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE1_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE1_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE1_ST_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core2_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE2_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE2_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE2_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE2_ST_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core3_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE3_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE3_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE3_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE3_ST_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core4_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE4_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE4_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE4_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE4_ST_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst0( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST0_W { - RST_U0_U7MC_SFT7110_TRACE_RST0_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST0_W { + RST_U0_U7MC_SFT7110_TRACE_RST0_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst1( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST1_W { - RST_U0_U7MC_SFT7110_TRACE_RST1_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST1_W { + RST_U0_U7MC_SFT7110_TRACE_RST1_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst2( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST2_W { - RST_U0_U7MC_SFT7110_TRACE_RST2_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST2_W { + RST_U0_U7MC_SFT7110_TRACE_RST2_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst3( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST3_W { - RST_U0_U7MC_SFT7110_TRACE_RST3_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST3_W { + RST_U0_U7MC_SFT7110_TRACE_RST3_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst4( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST4_W { - RST_U0_U7MC_SFT7110_TRACE_RST4_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST4_W { + RST_U0_U7MC_SFT7110_TRACE_RST4_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_com_rst( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_COM_RST_W { - RST_U0_U7MC_SFT7110_TRACE_COM_RST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_COM_RST_W { + RST_U0_U7MC_SFT7110_TRACE_COM_RST_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_img_gpu_rstn_apb( &mut self, - ) -> RST_U0_IMG_GPU_RSTN_APB_W { - RST_U0_IMG_GPU_RSTN_APB_W::new(self) + ) -> RST_U0_IMG_GPU_RSTN_APB_W { + RST_U0_IMG_GPU_RSTN_APB_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_img_gpu_rstn_doma( &mut self, - ) -> RST_U0_IMG_GPU_RSTN_DOMA_W { - RST_U0_IMG_GPU_RSTN_DOMA_W::new(self) + ) -> RST_U0_IMG_GPU_RSTN_DOMA_W { + RST_U0_IMG_GPU_RSTN_DOMA_W::new(self, 22) } #[doc = "Bit 23 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_apb_bus_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W::new(self, 23) } #[doc = "Bit 24 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_axicfg0_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W::new(self, 24) } #[doc = "Bit 25 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_cpu_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W::new(self, 25) } #[doc = "Bit 26 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_disp_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W::new(self, 26) } #[doc = "Bit 27 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_gpu_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W::new(self, 27) } #[doc = "Bit 28 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_isp_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W::new(self, 28) } #[doc = "Bit 29 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_ddrc_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W::new(self, 29) } #[doc = "Bit 30 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_stg_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W::new(self, 30) } #[doc = "Bit 31 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_vdec_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/soft_rst1_addr_sel.rs b/jh7110-vf2-12a-pac/src/syscrg/soft_rst1_addr_sel.rs index d3a8ec9..704da18 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/soft_rst1_addr_sel.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/soft_rst1_addr_sel.rs @@ -5,135 +5,132 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_sft7100_noc_bus_reset_venc_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_R = crate::BitReader; #[doc = "Field `rstn_u0_sft7100_noc_bus_reset_venc_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg1_dec_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg1_dec_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg1_dec_rstn_main` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg1_dec_rstn_main` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_main` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_main` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_main_div` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_main_div` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_hifi4` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_hifi4` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DDR_SFT7110_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DDR_SFT7110_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DDR_SFT7110_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_osc` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DDR_SFT7110_RSTN_OSC_R = crate::BitReader; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_osc` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DDR_SFT7110_RSTN_OSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DDR_SFT7110_RSTN_OSC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DDR_SFT7110_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DDR_SFT7110_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DDR_SFT7110_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dom_isp_top_rstn_dom_isp_top_ip_top_reset_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_R = crate::BitReader; #[doc = "Field `rstn_u0_dom_isp_top_rstn_dom_isp_top_ip_top_reset_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dom_isp_top_rstn_dom_isp_top_rstn_isp_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_dom_isp_top_rstn_dom_isp_top_rstn_isp_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_R = crate::BitReader; #[doc = "Field `rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W<'a, REG> = + crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_codaj12_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CODAJ12_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_codaj12_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CODAJ12_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CODAJ12_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_codaj12_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CODAJ12_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u0_codaj12_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CODAJ12_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CODAJ12_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_codaj12_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CODAJ12_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_codaj12_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CODAJ12_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CODAJ12_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave511_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE511_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_wave511_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE511_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE511_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave511_rstn_bpu` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE511_RSTN_BPU_R = crate::BitReader; #[doc = "Field `rstn_u0_wave511_rstn_bpu` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE511_RSTN_BPU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE511_RSTN_BPU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave511_rstn_vce` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE511_RSTN_VCE_R = crate::BitReader; #[doc = "Field `rstn_u0_wave511_rstn_vce` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE511_RSTN_VCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE511_RSTN_VCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave511_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE511_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_wave511_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE511_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE511_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_vdec_jpg_arb_jpgresetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_VDEC_JPG_ARB_JPGRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_vdec_jpg_arb_jpgresetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_vdec_jpg_arb_mainresetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_VDEC_JPG_ARB_MAINRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_vdec_jpg_arb_mainresetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_aximem_128b_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXIMEM_128B_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_aximem_128b_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXIMEM_128B_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXIMEM_128B_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave420l_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE420L_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_wave420l_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE420L_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE420L_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave420l_rstn_bpu` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE420L_RSTN_BPU_R = crate::BitReader; #[doc = "Field `rstn_u0_wave420l_rstn_bpu` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE420L_RSTN_BPU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE420L_RSTN_BPU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave420l_rstn_vce` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE420L_RSTN_VCE_R = crate::BitReader; #[doc = "Field `rstn_u0_wave420l_rstn_vce` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE420L_RSTN_VCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE420L_RSTN_VCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave420l_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE420L_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_wave420l_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE420L_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE420L_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_aximem_128b_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_AXIMEM_128B_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u1_aximem_128b_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_AXIMEM_128B_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_AXIMEM_128B_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_aximem_128b_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_AXIMEM_128B_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u2_aximem_128b_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_AXIMEM_128B_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_AXIMEM_128B_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_intmem_rom_sram_rstn_rom` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_R = crate::BitReader; #[doc = "Field `rstn_u0_intmem_rom_sram_rstn_rom` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdns_qspi_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDNS_QSPI_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdns_qspi_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDNS_QSPI_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDNS_QSPI_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdns_qspi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDNS_QSPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdns_qspi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDNS_QSPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDNS_QSPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdns_qspi_rstn_ref` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDNS_QSPI_RSTN_REF_R = crate::BitReader; #[doc = "Field `rstn_u0_cdns_qspi_rstn_ref` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDNS_QSPI_RSTN_REF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDNS_QSPI_RSTN_REF_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -310,258 +307,262 @@ impl W { #[must_use] pub fn rstn_u0_sft7100_noc_bus_reset_venc_axi_n( &mut self, - ) -> RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W { - RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W::new(self) + ) -> RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W { + RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg1_dec_rstn_ahb( &mut self, - ) -> RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W { - RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W::new(self) + ) -> RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W { + RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg1_dec_rstn_main( &mut self, - ) -> RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W { - RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W::new(self) + ) -> RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W { + RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg0_dec_rstn_main( &mut self, - ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W { - RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W::new(self) + ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W { + RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg0_dec_rstn_main_div( &mut self, - ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W { - RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W::new(self) + ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W { + RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg0_dec_rstn_hifi4( &mut self, - ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W { - RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W::new(self) + ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W { + RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_ddr_sft7110_rstn_axi( &mut self, - ) -> RSTN_U0_DDR_SFT7110_RSTN_AXI_W { - RSTN_U0_DDR_SFT7110_RSTN_AXI_W::new(self) + ) -> RSTN_U0_DDR_SFT7110_RSTN_AXI_W { + RSTN_U0_DDR_SFT7110_RSTN_AXI_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_ddr_sft7110_rstn_osc( &mut self, - ) -> RSTN_U0_DDR_SFT7110_RSTN_OSC_W { - RSTN_U0_DDR_SFT7110_RSTN_OSC_W::new(self) + ) -> RSTN_U0_DDR_SFT7110_RSTN_OSC_W { + RSTN_U0_DDR_SFT7110_RSTN_OSC_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_ddr_sft7110_rstn_apb( &mut self, - ) -> RSTN_U0_DDR_SFT7110_RSTN_APB_W { - RSTN_U0_DDR_SFT7110_RSTN_APB_W::new(self) + ) -> RSTN_U0_DDR_SFT7110_RSTN_APB_W { + RSTN_U0_DDR_SFT7110_RSTN_APB_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dom_isp_top_rstn_dom_isp_top_ip_top_reset_n( &mut self, - ) -> RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W { - RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W::new(self) + ) -> RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W { + RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dom_isp_top_rstn_dom_isp_top_rstn_isp_axi( &mut self, - ) -> RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W { - RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W::new(self) + ) -> RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W { + RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src( &mut self, - ) -> RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W { - RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W::new(self) + ) -> RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W { + RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_codaj12_rstn_axi( &mut self, - ) -> RSTN_U0_CODAJ12_RSTN_AXI_W { - RSTN_U0_CODAJ12_RSTN_AXI_W::new(self) + ) -> RSTN_U0_CODAJ12_RSTN_AXI_W { + RSTN_U0_CODAJ12_RSTN_AXI_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_codaj12_rstn_core( &mut self, - ) -> RSTN_U0_CODAJ12_RSTN_CORE_W { - RSTN_U0_CODAJ12_RSTN_CORE_W::new(self) + ) -> RSTN_U0_CODAJ12_RSTN_CORE_W { + RSTN_U0_CODAJ12_RSTN_CORE_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_codaj12_rstn_apb( &mut self, - ) -> RSTN_U0_CODAJ12_RSTN_APB_W { - RSTN_U0_CODAJ12_RSTN_APB_W::new(self) + ) -> RSTN_U0_CODAJ12_RSTN_APB_W { + RSTN_U0_CODAJ12_RSTN_APB_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave511_rstn_axi( &mut self, - ) -> RSTN_U0_WAVE511_RSTN_AXI_W { - RSTN_U0_WAVE511_RSTN_AXI_W::new(self) + ) -> RSTN_U0_WAVE511_RSTN_AXI_W { + RSTN_U0_WAVE511_RSTN_AXI_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave511_rstn_bpu( &mut self, - ) -> RSTN_U0_WAVE511_RSTN_BPU_W { - RSTN_U0_WAVE511_RSTN_BPU_W::new(self) + ) -> RSTN_U0_WAVE511_RSTN_BPU_W { + RSTN_U0_WAVE511_RSTN_BPU_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave511_rstn_vce( &mut self, - ) -> RSTN_U0_WAVE511_RSTN_VCE_W { - RSTN_U0_WAVE511_RSTN_VCE_W::new(self) + ) -> RSTN_U0_WAVE511_RSTN_VCE_W { + RSTN_U0_WAVE511_RSTN_VCE_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave511_rstn_apb( &mut self, - ) -> RSTN_U0_WAVE511_RSTN_APB_W { - RSTN_U0_WAVE511_RSTN_APB_W::new(self) + ) -> RSTN_U0_WAVE511_RSTN_APB_W { + RSTN_U0_WAVE511_RSTN_APB_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_vdec_jpg_arb_jpgresetn( &mut self, - ) -> RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W { - RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W::new(self) + ) -> RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W { + RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_vdec_jpg_arb_mainresetn( &mut self, - ) -> RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W { - RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W::new(self) + ) -> RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W { + RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_aximem_128b_rstn_axi( &mut self, - ) -> RSTN_U0_AXIMEM_128B_RSTN_AXI_W { - RSTN_U0_AXIMEM_128B_RSTN_AXI_W::new(self) + ) -> RSTN_U0_AXIMEM_128B_RSTN_AXI_W { + RSTN_U0_AXIMEM_128B_RSTN_AXI_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave420l_rstn_axi( &mut self, - ) -> RSTN_U0_WAVE420L_RSTN_AXI_W { - RSTN_U0_WAVE420L_RSTN_AXI_W::new(self) + ) -> RSTN_U0_WAVE420L_RSTN_AXI_W { + RSTN_U0_WAVE420L_RSTN_AXI_W::new(self, 22) } #[doc = "Bit 23 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave420l_rstn_bpu( &mut self, - ) -> RSTN_U0_WAVE420L_RSTN_BPU_W { - RSTN_U0_WAVE420L_RSTN_BPU_W::new(self) + ) -> RSTN_U0_WAVE420L_RSTN_BPU_W { + RSTN_U0_WAVE420L_RSTN_BPU_W::new(self, 23) } #[doc = "Bit 24 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave420l_rstn_vce( &mut self, - ) -> RSTN_U0_WAVE420L_RSTN_VCE_W { - RSTN_U0_WAVE420L_RSTN_VCE_W::new(self) + ) -> RSTN_U0_WAVE420L_RSTN_VCE_W { + RSTN_U0_WAVE420L_RSTN_VCE_W::new(self, 24) } #[doc = "Bit 25 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave420l_rstn_apb( &mut self, - ) -> RSTN_U0_WAVE420L_RSTN_APB_W { - RSTN_U0_WAVE420L_RSTN_APB_W::new(self) + ) -> RSTN_U0_WAVE420L_RSTN_APB_W { + RSTN_U0_WAVE420L_RSTN_APB_W::new(self, 25) } #[doc = "Bit 26 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_aximem_128b_rstn_axi( &mut self, - ) -> RSTN_U1_AXIMEM_128B_RSTN_AXI_W { - RSTN_U1_AXIMEM_128B_RSTN_AXI_W::new(self) + ) -> RSTN_U1_AXIMEM_128B_RSTN_AXI_W { + RSTN_U1_AXIMEM_128B_RSTN_AXI_W::new(self, 26) } #[doc = "Bit 27 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u2_aximem_128b_rstn_axi( &mut self, - ) -> RSTN_U2_AXIMEM_128B_RSTN_AXI_W { - RSTN_U2_AXIMEM_128B_RSTN_AXI_W::new(self) + ) -> RSTN_U2_AXIMEM_128B_RSTN_AXI_W { + RSTN_U2_AXIMEM_128B_RSTN_AXI_W::new(self, 27) } #[doc = "Bit 28 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_intmem_rom_sram_rstn_rom( &mut self, - ) -> RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W { - RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W::new(self) + ) -> RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W { + RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W::new(self, 28) } #[doc = "Bit 29 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdns_qspi_rstn_ahb( &mut self, - ) -> RSTN_U0_CDNS_QSPI_RSTN_AHB_W { - RSTN_U0_CDNS_QSPI_RSTN_AHB_W::new(self) + ) -> RSTN_U0_CDNS_QSPI_RSTN_AHB_W { + RSTN_U0_CDNS_QSPI_RSTN_AHB_W::new(self, 29) } #[doc = "Bit 30 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdns_qspi_rstn_apb( &mut self, - ) -> RSTN_U0_CDNS_QSPI_RSTN_APB_W { - RSTN_U0_CDNS_QSPI_RSTN_APB_W::new(self) + ) -> RSTN_U0_CDNS_QSPI_RSTN_APB_W { + RSTN_U0_CDNS_QSPI_RSTN_APB_W::new(self, 30) } #[doc = "Bit 31 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdns_qspi_rstn_ref( &mut self, - ) -> RSTN_U0_CDNS_QSPI_RSTN_REF_W { - RSTN_U0_CDNS_QSPI_RSTN_REF_W::new(self) + ) -> RSTN_U0_CDNS_QSPI_RSTN_REF_W { + RSTN_U0_CDNS_QSPI_RSTN_REF_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/soft_rst2_addr_sel.rs b/jh7110-vf2-12a-pac/src/syscrg/soft_rst2_addr_sel.rs index a9a2df4..28f2199 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/soft_rst2_addr_sel.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/soft_rst2_addr_sel.rs @@ -5,131 +5,131 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_sdio_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SDIO_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_sdio_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SDIO_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SDIO_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_sdi_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_SDI_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u1_sdi_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_SDI_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_SDI_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_gmac5_axi64_aresetn_i` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_GMAC5_AXI64_ARESETN_I_R = crate::BitReader; #[doc = "Field `rstn_u1_gmac5_axi64_aresetn_i` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_GMAC5_AXI64_ARESETN_I_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_GMAC5_AXI64_ARESETN_I_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_gmac5_axi64_hresetn_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_GMAC5_AXI64_HRESETN_N_R = crate::BitReader; #[doc = "Field `rstn_u1_gmac5_axi64_hresetn_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_GMAC5_AXI64_HRESETN_N_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_GMAC5_AXI64_HRESETN_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_mailbox_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_MAILBOX_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_mailbox_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_MAILBOX_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_MAILBOX_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u2_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u3_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U3_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u3_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U3_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U3_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u4_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U4_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u4_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U4_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U4_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u5_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U5_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u5_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U5_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U5_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u6_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U6_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u6_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U6_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U6_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u2_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u3_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U3_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u3_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U3_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U3_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u4_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U4_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u4_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U4_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U4_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u5_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U5_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u5_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U5_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U5_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u6_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U6_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u6_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U6_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U6_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u0_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u1_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u2_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u2_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u3_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U3_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u3_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U3_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U3_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u3_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U3_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u3_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U3_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U3_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u4_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U4_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u4_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U4_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U4_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u4_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U4_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u4_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U4_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U4_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u5_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U5_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u5_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U5_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U5_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u6_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U6_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u6_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U6_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U6_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdns_spdif_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDNS_SPDIF_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdns_spdif_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDNS_SPDIF_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDNS_SPDIF_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -296,242 +296,222 @@ impl W { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_sdio_rstn_ahb(&mut self) -> RSTN_U0_SDIO_RSTN_AHB_W { - RSTN_U0_SDIO_RSTN_AHB_W::new(self) + pub fn rstn_u0_sdio_rstn_ahb(&mut self) -> RSTN_U0_SDIO_RSTN_AHB_W { + RSTN_U0_SDIO_RSTN_AHB_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u1_sdi_rstn_ahb(&mut self) -> RSTN_U1_SDI_RSTN_AHB_W { - RSTN_U1_SDI_RSTN_AHB_W::new(self) + pub fn rstn_u1_sdi_rstn_ahb(&mut self) -> RSTN_U1_SDI_RSTN_AHB_W { + RSTN_U1_SDI_RSTN_AHB_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_gmac5_axi64_aresetn_i( &mut self, - ) -> RSTN_U1_GMAC5_AXI64_ARESETN_I_W { - RSTN_U1_GMAC5_AXI64_ARESETN_I_W::new(self) + ) -> RSTN_U1_GMAC5_AXI64_ARESETN_I_W { + RSTN_U1_GMAC5_AXI64_ARESETN_I_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_gmac5_axi64_hresetn_n( &mut self, - ) -> RSTN_U1_GMAC5_AXI64_HRESETN_N_W { - RSTN_U1_GMAC5_AXI64_HRESETN_N_W::new(self) + ) -> RSTN_U1_GMAC5_AXI64_HRESETN_N_W { + RSTN_U1_GMAC5_AXI64_HRESETN_N_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_mailbox_presetn( &mut self, - ) -> RSTN_U0_MAILBOX_PRESETN_W { - RSTN_U0_MAILBOX_PRESETN_W::new(self) + ) -> RSTN_U0_MAILBOX_PRESETN_W { + RSTN_U0_MAILBOX_PRESETN_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U0_SSP_SPI_RSTN_APB_W { - RSTN_U0_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U0_SSP_SPI_RSTN_APB_W { + RSTN_U0_SSP_SPI_RSTN_APB_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U1_SSP_SPI_RSTN_APB_W { - RSTN_U1_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U1_SSP_SPI_RSTN_APB_W { + RSTN_U1_SSP_SPI_RSTN_APB_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u2_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U2_SSP_SPI_RSTN_APB_W { - RSTN_U2_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U2_SSP_SPI_RSTN_APB_W { + RSTN_U2_SSP_SPI_RSTN_APB_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u3_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U3_SSP_SPI_RSTN_APB_W { - RSTN_U3_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U3_SSP_SPI_RSTN_APB_W { + RSTN_U3_SSP_SPI_RSTN_APB_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u4_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U4_SSP_SPI_RSTN_APB_W { - RSTN_U4_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U4_SSP_SPI_RSTN_APB_W { + RSTN_U4_SSP_SPI_RSTN_APB_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u5_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U5_SSP_SPI_RSTN_APB_W { - RSTN_U5_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U5_SSP_SPI_RSTN_APB_W { + RSTN_U5_SSP_SPI_RSTN_APB_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u6_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U6_SSP_SPI_RSTN_APB_W { - RSTN_U6_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U6_SSP_SPI_RSTN_APB_W { + RSTN_U6_SSP_SPI_RSTN_APB_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_i2c_rstn_apb(&mut self) -> RSTN_U0_I2C_RSTN_APB_W { - RSTN_U0_I2C_RSTN_APB_W::new(self) + pub fn rstn_u0_i2c_rstn_apb(&mut self) -> RSTN_U0_I2C_RSTN_APB_W { + RSTN_U0_I2C_RSTN_APB_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u1_i2c_rstn_apb(&mut self) -> RSTN_U1_I2C_RSTN_APB_W { - RSTN_U1_I2C_RSTN_APB_W::new(self) + pub fn rstn_u1_i2c_rstn_apb(&mut self) -> RSTN_U1_I2C_RSTN_APB_W { + RSTN_U1_I2C_RSTN_APB_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u2_i2c_rstn_apb(&mut self) -> RSTN_U2_I2C_RSTN_APB_W { - RSTN_U2_I2C_RSTN_APB_W::new(self) + pub fn rstn_u2_i2c_rstn_apb(&mut self) -> RSTN_U2_I2C_RSTN_APB_W { + RSTN_U2_I2C_RSTN_APB_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u3_i2c_rstn_apb(&mut self) -> RSTN_U3_I2C_RSTN_APB_W { - RSTN_U3_I2C_RSTN_APB_W::new(self) + pub fn rstn_u3_i2c_rstn_apb(&mut self) -> RSTN_U3_I2C_RSTN_APB_W { + RSTN_U3_I2C_RSTN_APB_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u4_i2c_rstn_apb(&mut self) -> RSTN_U4_I2C_RSTN_APB_W { - RSTN_U4_I2C_RSTN_APB_W::new(self) + pub fn rstn_u4_i2c_rstn_apb(&mut self) -> RSTN_U4_I2C_RSTN_APB_W { + RSTN_U4_I2C_RSTN_APB_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u5_i2c_rstn_apb(&mut self) -> RSTN_U5_I2C_RSTN_APB_W { - RSTN_U5_I2C_RSTN_APB_W::new(self) + pub fn rstn_u5_i2c_rstn_apb(&mut self) -> RSTN_U5_I2C_RSTN_APB_W { + RSTN_U5_I2C_RSTN_APB_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u6_i2c_rstn_apb(&mut self) -> RSTN_U6_I2C_RSTN_APB_W { - RSTN_U6_I2C_RSTN_APB_W::new(self) + pub fn rstn_u6_i2c_rstn_apb(&mut self) -> RSTN_U6_I2C_RSTN_APB_W { + RSTN_U6_I2C_RSTN_APB_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_uart_rstn_apb( - &mut self, - ) -> RSTN_U0_UART_RSTN_APB_W { - RSTN_U0_UART_RSTN_APB_W::new(self) + pub fn rstn_u0_uart_rstn_apb(&mut self) -> RSTN_U0_UART_RSTN_APB_W { + RSTN_U0_UART_RSTN_APB_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_uart_rstn_core( - &mut self, - ) -> RSTN_U0_UART_RSTN_CORE_W { - RSTN_U0_UART_RSTN_CORE_W::new(self) + pub fn rstn_u0_uart_rstn_core(&mut self) -> RSTN_U0_UART_RSTN_CORE_W { + RSTN_U0_UART_RSTN_CORE_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u1_uart_rstn_apb( - &mut self, - ) -> RSTN_U1_UART_RSTN_APB_W { - RSTN_U1_UART_RSTN_APB_W::new(self) + pub fn rstn_u1_uart_rstn_apb(&mut self) -> RSTN_U1_UART_RSTN_APB_W { + RSTN_U1_UART_RSTN_APB_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u1_uart_rstn_core( - &mut self, - ) -> RSTN_U1_UART_RSTN_CORE_W { - RSTN_U1_UART_RSTN_CORE_W::new(self) + pub fn rstn_u1_uart_rstn_core(&mut self) -> RSTN_U1_UART_RSTN_CORE_W { + RSTN_U1_UART_RSTN_CORE_W::new(self, 22) } #[doc = "Bit 23 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u2_uart_rstn_apb( - &mut self, - ) -> RSTN_U2_UART_RSTN_APB_W { - RSTN_U2_UART_RSTN_APB_W::new(self) + pub fn rstn_u2_uart_rstn_apb(&mut self) -> RSTN_U2_UART_RSTN_APB_W { + RSTN_U2_UART_RSTN_APB_W::new(self, 23) } #[doc = "Bit 24 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u2_uart_rstn_core( - &mut self, - ) -> RSTN_U2_UART_RSTN_CORE_W { - RSTN_U2_UART_RSTN_CORE_W::new(self) + pub fn rstn_u2_uart_rstn_core(&mut self) -> RSTN_U2_UART_RSTN_CORE_W { + RSTN_U2_UART_RSTN_CORE_W::new(self, 24) } #[doc = "Bit 25 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u3_uart_rstn_apb( - &mut self, - ) -> RSTN_U3_UART_RSTN_APB_W { - RSTN_U3_UART_RSTN_APB_W::new(self) + pub fn rstn_u3_uart_rstn_apb(&mut self) -> RSTN_U3_UART_RSTN_APB_W { + RSTN_U3_UART_RSTN_APB_W::new(self, 25) } #[doc = "Bit 26 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u3_uart_rstn_core( - &mut self, - ) -> RSTN_U3_UART_RSTN_CORE_W { - RSTN_U3_UART_RSTN_CORE_W::new(self) + pub fn rstn_u3_uart_rstn_core(&mut self) -> RSTN_U3_UART_RSTN_CORE_W { + RSTN_U3_UART_RSTN_CORE_W::new(self, 26) } #[doc = "Bit 27 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u4_uart_rstn_apb( - &mut self, - ) -> RSTN_U4_UART_RSTN_APB_W { - RSTN_U4_UART_RSTN_APB_W::new(self) + pub fn rstn_u4_uart_rstn_apb(&mut self) -> RSTN_U4_UART_RSTN_APB_W { + RSTN_U4_UART_RSTN_APB_W::new(self, 27) } #[doc = "Bit 28 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u4_uart_rstn_core( - &mut self, - ) -> RSTN_U4_UART_RSTN_CORE_W { - RSTN_U4_UART_RSTN_CORE_W::new(self) + pub fn rstn_u4_uart_rstn_core(&mut self) -> RSTN_U4_UART_RSTN_CORE_W { + RSTN_U4_UART_RSTN_CORE_W::new(self, 28) } #[doc = "Bit 29 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u5_uart_rstn_apb( - &mut self, - ) -> RSTN_U5_UART_RSTN_APB_W { - RSTN_U5_UART_RSTN_APB_W::new(self) + pub fn rstn_u5_uart_rstn_apb(&mut self) -> RSTN_U5_UART_RSTN_APB_W { + RSTN_U5_UART_RSTN_APB_W::new(self, 29) } #[doc = "Bit 30 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u6_uart_rstn_core( - &mut self, - ) -> RSTN_U6_UART_RSTN_CORE_W { - RSTN_U6_UART_RSTN_CORE_W::new(self) + pub fn rstn_u6_uart_rstn_core(&mut self) -> RSTN_U6_UART_RSTN_CORE_W { + RSTN_U6_UART_RSTN_CORE_W::new(self, 30) } #[doc = "Bit 31 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdns_spdif_rstn_apb( &mut self, - ) -> RSTN_U0_CDNS_SPDIF_RSTN_APB_W { - RSTN_U0_CDNS_SPDIF_RSTN_APB_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> RSTN_U0_CDNS_SPDIF_RSTN_APB_W { + RSTN_U0_CDNS_SPDIF_RSTN_APB_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/soft_rst3_addr_sel.rs b/jh7110-vf2-12a-pac/src/syscrg/soft_rst3_addr_sel.rs index bd0d372..2127cd6 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/soft_rst3_addr_sel.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/soft_rst3_addr_sel.rs @@ -5,123 +5,123 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_pwmdac_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PWMDAC_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_pwmdac_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PWMDAC_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PWMDAC_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_pdm_4mic_rstn_dmic` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PDM_4MIC_RSTN_DMIC_R = crate::BitReader; #[doc = "Field `rstn_u0_pdm_4mic_rstn_dmic` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PDM_4MIC_RSTN_DMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PDM_4MIC_RSTN_DMIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_pdm_4mic_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PDM_4MIC_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_pdm_4mic_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PDM_4MIC_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PDM_4MIC_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2srx_3ch_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2SRX_3CH_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_i2srx_3ch_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2SRX_3CH_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2SRX_3CH_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2srx_3ch_rstn_bclk` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2SRX_3CH_RSTN_BCLK_R = crate::BitReader; #[doc = "Field `rstn_u0_i2srx_3ch_rstn_bclk` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2SRX_3CH_RSTN_BCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2SRX_3CH_RSTN_BCLK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2stx_4ch_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2STX_4CH_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_i2stx_4ch_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2STX_4CH_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2STX_4CH_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2stx_4ch_rstn_bclk` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2STX_4CH_RSTN_BCLK_R = crate::BitReader; #[doc = "Field `rstn_u0_i2stx_4ch_rstn_bclk` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2STX_4CH_RSTN_BCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2STX_4CH_RSTN_BCLK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_i2stx_4ch_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_I2STX_4CH_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_i2stx_4ch_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_I2STX_4CH_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_I2STX_4CH_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_i2stx_4ch_rstn_bclk` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_I2STX_4CH_RSTN_BCLK_R = crate::BitReader; #[doc = "Field `rstn_u1_i2stx_4ch_rstn_bclk` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_I2STX_4CH_RSTN_BCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_I2STX_4CH_RSTN_BCLK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_tdm16slot_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TDM16SLOT_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_tdm16slot_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TDM16SLOT_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TDM16SLOT_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_tdm16slot_rstn_tdm` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TDM16SLOT_RSTN_TDM_R = crate::BitReader; #[doc = "Field `rstn_u0_tdm16slot_rstn_tdm` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TDM16SLOT_RSTN_TDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TDM16SLOT_RSTN_TDM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_tdm16slot_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TDM16SLOT_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_tdm16slot_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TDM16SLOT_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TDM16SLOT_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_pwm_8ch_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PWM_8CH_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_pwm_8ch_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PWM_8CH_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PWM_8CH_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dskit_wdt_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DSKIT_WDT_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_dskit_wdt_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DSKIT_WDT_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DSKIT_WDT_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dskit_wdt_rstn_wdt` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DSKIT_WDT_RSTN_WDT_R = crate::BitReader; #[doc = "Field `rstn_u0_dskit_wdt_rstn_wdt` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DSKIT_WDT_RSTN_WDT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DSKIT_WDT_RSTN_WDT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_can_ctrl_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CAN_CTRL_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_can_ctrl_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CAN_CTRL_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CAN_CTRL_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_can_ctrl_rstn_can` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CAN_CTRL_RSTN_CAN_R = crate::BitReader; #[doc = "Field `rstn_u0_can_ctrl_rstn_can` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CAN_CTRL_RSTN_CAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CAN_CTRL_RSTN_CAN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_can_ctrl_rstn_timer` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CAN_CTRL_RSTN_TIMER_R = crate::BitReader; #[doc = "Field `rstn_u0_can_ctrl_rstn_timer` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CAN_CTRL_RSTN_TIMER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CAN_CTRL_RSTN_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_can_ctrl_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_CAN_CTRL_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_can_ctrl_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_CAN_CTRL_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_CAN_CTRL_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_can_ctrl_rstn_can` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_CAN_CTRL_RSTN_CAN_R = crate::BitReader; #[doc = "Field `rstn_u1_can_ctrl_rstn_can` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_CAN_CTRL_RSTN_CAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_CAN_CTRL_RSTN_CAN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_can_ctrl_rstn_timer` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_CAN_CTRL_RSTN_TIMER_R = crate::BitReader; #[doc = "Field `rstn_u1_can_ctrl_rstn_timer` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_CAN_CTRL_RSTN_TIMER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_CAN_CTRL_RSTN_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_timer0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_TIMER0_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_timer0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_TIMER0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_TIMER0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_time10` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_TIME10_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_time10` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_TIME10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_TIME10_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_timer2` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_TIMER2_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_timer2` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_TIMER2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_TIMER2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_timer3` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_TIMER3_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_timer3` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_TIMER3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_TIMER3_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_int_ctrl_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_INT_CTRL_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_int_ctrl_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_INT_CTRL_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_INT_CTRL_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_temp_sensor_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TEMP_SENSOR_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_temp_sensor_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TEMP_SENSOR_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TEMP_SENSOR_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_temp_sensor_rstn_temp` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TEMP_SENSOR_RSTN_TEMP_R = crate::BitReader; #[doc = "Field `rstn_u0_temp_sensor_rstn_temp` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_jtag_certification_rst_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_JTAG_CERTIFICATION_RST_N_R = crate::BitReader; #[doc = "Field `rstn_u0_jtag_certification_rst_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_JTAG_CERTIFICATION_RST_N_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_JTAG_CERTIFICATION_RST_N_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -280,242 +280,246 @@ impl W { #[must_use] pub fn rstn_u0_pwmdac_rstn_apb( &mut self, - ) -> RSTN_U0_PWMDAC_RSTN_APB_W { - RSTN_U0_PWMDAC_RSTN_APB_W::new(self) + ) -> RSTN_U0_PWMDAC_RSTN_APB_W { + RSTN_U0_PWMDAC_RSTN_APB_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_pdm_4mic_rstn_dmic( &mut self, - ) -> RSTN_U0_PDM_4MIC_RSTN_DMIC_W { - RSTN_U0_PDM_4MIC_RSTN_DMIC_W::new(self) + ) -> RSTN_U0_PDM_4MIC_RSTN_DMIC_W { + RSTN_U0_PDM_4MIC_RSTN_DMIC_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_pdm_4mic_rstn_apb( &mut self, - ) -> RSTN_U0_PDM_4MIC_RSTN_APB_W { - RSTN_U0_PDM_4MIC_RSTN_APB_W::new(self) + ) -> RSTN_U0_PDM_4MIC_RSTN_APB_W { + RSTN_U0_PDM_4MIC_RSTN_APB_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_i2srx_3ch_rstn_apb( &mut self, - ) -> RSTN_U0_I2SRX_3CH_RSTN_APB_W { - RSTN_U0_I2SRX_3CH_RSTN_APB_W::new(self) + ) -> RSTN_U0_I2SRX_3CH_RSTN_APB_W { + RSTN_U0_I2SRX_3CH_RSTN_APB_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_i2srx_3ch_rstn_bclk( &mut self, - ) -> RSTN_U0_I2SRX_3CH_RSTN_BCLK_W { - RSTN_U0_I2SRX_3CH_RSTN_BCLK_W::new(self) + ) -> RSTN_U0_I2SRX_3CH_RSTN_BCLK_W { + RSTN_U0_I2SRX_3CH_RSTN_BCLK_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_i2stx_4ch_rstn_apb( &mut self, - ) -> RSTN_U0_I2STX_4CH_RSTN_APB_W { - RSTN_U0_I2STX_4CH_RSTN_APB_W::new(self) + ) -> RSTN_U0_I2STX_4CH_RSTN_APB_W { + RSTN_U0_I2STX_4CH_RSTN_APB_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_i2stx_4ch_rstn_bclk( &mut self, - ) -> RSTN_U0_I2STX_4CH_RSTN_BCLK_W { - RSTN_U0_I2STX_4CH_RSTN_BCLK_W::new(self) + ) -> RSTN_U0_I2STX_4CH_RSTN_BCLK_W { + RSTN_U0_I2STX_4CH_RSTN_BCLK_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_i2stx_4ch_rstn_apb( &mut self, - ) -> RSTN_U1_I2STX_4CH_RSTN_APB_W { - RSTN_U1_I2STX_4CH_RSTN_APB_W::new(self) + ) -> RSTN_U1_I2STX_4CH_RSTN_APB_W { + RSTN_U1_I2STX_4CH_RSTN_APB_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_i2stx_4ch_rstn_bclk( &mut self, - ) -> RSTN_U1_I2STX_4CH_RSTN_BCLK_W { - RSTN_U1_I2STX_4CH_RSTN_BCLK_W::new(self) + ) -> RSTN_U1_I2STX_4CH_RSTN_BCLK_W { + RSTN_U1_I2STX_4CH_RSTN_BCLK_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_tdm16slot_rstn_ahb( &mut self, - ) -> RSTN_U0_TDM16SLOT_RSTN_AHB_W { - RSTN_U0_TDM16SLOT_RSTN_AHB_W::new(self) + ) -> RSTN_U0_TDM16SLOT_RSTN_AHB_W { + RSTN_U0_TDM16SLOT_RSTN_AHB_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_tdm16slot_rstn_tdm( &mut self, - ) -> RSTN_U0_TDM16SLOT_RSTN_TDM_W { - RSTN_U0_TDM16SLOT_RSTN_TDM_W::new(self) + ) -> RSTN_U0_TDM16SLOT_RSTN_TDM_W { + RSTN_U0_TDM16SLOT_RSTN_TDM_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_tdm16slot_rstn_apb( &mut self, - ) -> RSTN_U0_TDM16SLOT_RSTN_APB_W { - RSTN_U0_TDM16SLOT_RSTN_APB_W::new(self) + ) -> RSTN_U0_TDM16SLOT_RSTN_APB_W { + RSTN_U0_TDM16SLOT_RSTN_APB_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_pwm_8ch_rstn_apb( &mut self, - ) -> RSTN_U0_PWM_8CH_RSTN_APB_W { - RSTN_U0_PWM_8CH_RSTN_APB_W::new(self) + ) -> RSTN_U0_PWM_8CH_RSTN_APB_W { + RSTN_U0_PWM_8CH_RSTN_APB_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dskit_wdt_rstn_apb( &mut self, - ) -> RSTN_U0_DSKIT_WDT_RSTN_APB_W { - RSTN_U0_DSKIT_WDT_RSTN_APB_W::new(self) + ) -> RSTN_U0_DSKIT_WDT_RSTN_APB_W { + RSTN_U0_DSKIT_WDT_RSTN_APB_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dskit_wdt_rstn_wdt( &mut self, - ) -> RSTN_U0_DSKIT_WDT_RSTN_WDT_W { - RSTN_U0_DSKIT_WDT_RSTN_WDT_W::new(self) + ) -> RSTN_U0_DSKIT_WDT_RSTN_WDT_W { + RSTN_U0_DSKIT_WDT_RSTN_WDT_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_can_ctrl_rstn_apb( &mut self, - ) -> RSTN_U0_CAN_CTRL_RSTN_APB_W { - RSTN_U0_CAN_CTRL_RSTN_APB_W::new(self) + ) -> RSTN_U0_CAN_CTRL_RSTN_APB_W { + RSTN_U0_CAN_CTRL_RSTN_APB_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_can_ctrl_rstn_can( &mut self, - ) -> RSTN_U0_CAN_CTRL_RSTN_CAN_W { - RSTN_U0_CAN_CTRL_RSTN_CAN_W::new(self) + ) -> RSTN_U0_CAN_CTRL_RSTN_CAN_W { + RSTN_U0_CAN_CTRL_RSTN_CAN_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_can_ctrl_rstn_timer( &mut self, - ) -> RSTN_U0_CAN_CTRL_RSTN_TIMER_W { - RSTN_U0_CAN_CTRL_RSTN_TIMER_W::new(self) + ) -> RSTN_U0_CAN_CTRL_RSTN_TIMER_W { + RSTN_U0_CAN_CTRL_RSTN_TIMER_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_can_ctrl_rstn_apb( &mut self, - ) -> RSTN_U1_CAN_CTRL_RSTN_APB_W { - RSTN_U1_CAN_CTRL_RSTN_APB_W::new(self) + ) -> RSTN_U1_CAN_CTRL_RSTN_APB_W { + RSTN_U1_CAN_CTRL_RSTN_APB_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_can_ctrl_rstn_can( &mut self, - ) -> RSTN_U1_CAN_CTRL_RSTN_CAN_W { - RSTN_U1_CAN_CTRL_RSTN_CAN_W::new(self) + ) -> RSTN_U1_CAN_CTRL_RSTN_CAN_W { + RSTN_U1_CAN_CTRL_RSTN_CAN_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_can_ctrl_rstn_timer( &mut self, - ) -> RSTN_U1_CAN_CTRL_RSTN_TIMER_W { - RSTN_U1_CAN_CTRL_RSTN_TIMER_W::new(self) + ) -> RSTN_U1_CAN_CTRL_RSTN_TIMER_W { + RSTN_U1_CAN_CTRL_RSTN_TIMER_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_apb( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_APB_W { - RSTN_U0_SI5_TIMER_RSTN_APB_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_APB_W { + RSTN_U0_SI5_TIMER_RSTN_APB_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_timer0( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER0_W { - RSTN_U0_SI5_TIMER_RSTN_TIMER0_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER0_W { + RSTN_U0_SI5_TIMER_RSTN_TIMER0_W::new(self, 22) } #[doc = "Bit 23 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_time10( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_TIME10_W { - RSTN_U0_SI5_TIMER_RSTN_TIME10_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_TIME10_W { + RSTN_U0_SI5_TIMER_RSTN_TIME10_W::new(self, 23) } #[doc = "Bit 24 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_timer2( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER2_W { - RSTN_U0_SI5_TIMER_RSTN_TIMER2_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER2_W { + RSTN_U0_SI5_TIMER_RSTN_TIMER2_W::new(self, 24) } #[doc = "Bit 25 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_timer3( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER3_W { - RSTN_U0_SI5_TIMER_RSTN_TIMER3_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER3_W { + RSTN_U0_SI5_TIMER_RSTN_TIMER3_W::new(self, 25) } #[doc = "Bit 26 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_int_ctrl_rstn_apb( &mut self, - ) -> RSTN_U0_INT_CTRL_RSTN_APB_W { - RSTN_U0_INT_CTRL_RSTN_APB_W::new(self) + ) -> RSTN_U0_INT_CTRL_RSTN_APB_W { + RSTN_U0_INT_CTRL_RSTN_APB_W::new(self, 26) } #[doc = "Bit 27 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_temp_sensor_rstn_apb( &mut self, - ) -> RSTN_U0_TEMP_SENSOR_RSTN_APB_W { - RSTN_U0_TEMP_SENSOR_RSTN_APB_W::new(self) + ) -> RSTN_U0_TEMP_SENSOR_RSTN_APB_W { + RSTN_U0_TEMP_SENSOR_RSTN_APB_W::new(self, 27) } #[doc = "Bit 28 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_temp_sensor_rstn_temp( &mut self, - ) -> RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W { - RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W::new(self) + ) -> RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W { + RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W::new(self, 28) } #[doc = "Bit 29 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_jtag_certification_rst_n( &mut self, - ) -> RSTN_U0_JTAG_CERTIFICATION_RST_N_W { - RSTN_U0_JTAG_CERTIFICATION_RST_N_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> RSTN_U0_JTAG_CERTIFICATION_RST_N_W { + RSTN_U0_JTAG_CERTIFICATION_RST_N_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/syscrg_rst0_status.rs b/jh7110-vf2-12a-pac/src/syscrg/syscrg_rst0_status.rs index 5fa6e96..4d11058 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/syscrg_rst0_status.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/syscrg_rst0_status.rs @@ -5,140 +5,131 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_jtag2apb_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_JTAG2APB_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_jtag2apb_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_JTAG2APB_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_JTAG2APB_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_sys_syscon_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SYS_SYSCON_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_sys_syscon_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SYS_SYSCON_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SYS_SYSCON_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_sys_iomux_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SYS_IOMUX_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_sys_iomux_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SYS_IOMUX_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SYS_IOMUX_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_bus` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_BUS_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_bus` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_BUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_BUS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_debug_reset` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_DEBUG_RESET_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_debug_reset` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_DEBUG_RESET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_DEBUG_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core0` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE0_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core1` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE1_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core1` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core2` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE2_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core2` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core3` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE3_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core3` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE3_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core4` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE4_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core4` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE4_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core0_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE0_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core0_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE0_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core1_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE1_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core1_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE1_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core2_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE2_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core2_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE2_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core3_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE3_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core3_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE3_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE3_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core4_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE4_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core4_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE4_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE4_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst0` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST0_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst1` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST1_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst1` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst2` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST2_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst2` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst3` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST3_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst3` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST3_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst4` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST4_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst4` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST4_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_com_rst` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_COM_RST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_com_rst` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_COM_RST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_COM_RST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_img_gpu_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_IMG_GPU_RSTN_APB_R = crate::BitReader; #[doc = "Field `rst_u0_img_gpu_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_IMG_GPU_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_IMG_GPU_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_img_gpu_rstn_doma` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_IMG_GPU_RSTN_DOMA_R = crate::BitReader; #[doc = "Field `rst_u0_img_gpu_rstn_doma` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_IMG_GPU_RSTN_DOMA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_IMG_GPU_RSTN_DOMA_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_apb_bus_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_apb_bus_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_axicfg0_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_axicfg0_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_cpu_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_cpu_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_disp_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_disp_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_gpu_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_gpu_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_isp_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_isp_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_ddrc_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_ddrc_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_stg_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_stg_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_vdec_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_vdec_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -325,258 +316,262 @@ impl W { #[must_use] pub fn rstn_u0_jtag2apb_presetn( &mut self, - ) -> RSTN_U0_JTAG2APB_PRESETN_W { - RSTN_U0_JTAG2APB_PRESETN_W::new(self) + ) -> RSTN_U0_JTAG2APB_PRESETN_W { + RSTN_U0_JTAG2APB_PRESETN_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_sys_syscon_presetn( &mut self, - ) -> RSTN_U0_SYS_SYSCON_PRESETN_W { - RSTN_U0_SYS_SYSCON_PRESETN_W::new(self) + ) -> RSTN_U0_SYS_SYSCON_PRESETN_W { + RSTN_U0_SYS_SYSCON_PRESETN_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_sys_iomux_presetn( &mut self, - ) -> RSTN_U0_SYS_IOMUX_PRESETN_W { - RSTN_U0_SYS_IOMUX_PRESETN_W::new(self) + ) -> RSTN_U0_SYS_IOMUX_PRESETN_W { + RSTN_U0_SYS_IOMUX_PRESETN_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_bus( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_BUS_W { - RST_U0_U7MC_SFT7110_RST_BUS_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_BUS_W { + RST_U0_U7MC_SFT7110_RST_BUS_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_debug_reset( &mut self, - ) -> RST_U0_U7MC_SFT7110_DEBUG_RESET_W { - RST_U0_U7MC_SFT7110_DEBUG_RESET_W::new(self) + ) -> RST_U0_U7MC_SFT7110_DEBUG_RESET_W { + RST_U0_U7MC_SFT7110_DEBUG_RESET_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core0( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE0_W { - RST_U0_U7MC_SFT7110_RST_CORE0_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE0_W { + RST_U0_U7MC_SFT7110_RST_CORE0_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core1( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE1_W { - RST_U0_U7MC_SFT7110_RST_CORE1_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE1_W { + RST_U0_U7MC_SFT7110_RST_CORE1_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core2( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE2_W { - RST_U0_U7MC_SFT7110_RST_CORE2_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE2_W { + RST_U0_U7MC_SFT7110_RST_CORE2_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core3( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE3_W { - RST_U0_U7MC_SFT7110_RST_CORE3_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE3_W { + RST_U0_U7MC_SFT7110_RST_CORE3_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core4( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE4_W { - RST_U0_U7MC_SFT7110_RST_CORE4_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE4_W { + RST_U0_U7MC_SFT7110_RST_CORE4_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core0_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE0_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE0_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE0_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE0_ST_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core1_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE1_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE1_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE1_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE1_ST_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core2_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE2_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE2_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE2_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE2_ST_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core3_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE3_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE3_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE3_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE3_ST_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core4_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE4_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE4_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE4_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE4_ST_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst0( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST0_W { - RST_U0_U7MC_SFT7110_TRACE_RST0_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST0_W { + RST_U0_U7MC_SFT7110_TRACE_RST0_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst1( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST1_W { - RST_U0_U7MC_SFT7110_TRACE_RST1_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST1_W { + RST_U0_U7MC_SFT7110_TRACE_RST1_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst2( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST2_W { - RST_U0_U7MC_SFT7110_TRACE_RST2_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST2_W { + RST_U0_U7MC_SFT7110_TRACE_RST2_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst3( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST3_W { - RST_U0_U7MC_SFT7110_TRACE_RST3_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST3_W { + RST_U0_U7MC_SFT7110_TRACE_RST3_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst4( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST4_W { - RST_U0_U7MC_SFT7110_TRACE_RST4_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST4_W { + RST_U0_U7MC_SFT7110_TRACE_RST4_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_com_rst( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_COM_RST_W { - RST_U0_U7MC_SFT7110_TRACE_COM_RST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_COM_RST_W { + RST_U0_U7MC_SFT7110_TRACE_COM_RST_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_img_gpu_rstn_apb( &mut self, - ) -> RST_U0_IMG_GPU_RSTN_APB_W { - RST_U0_IMG_GPU_RSTN_APB_W::new(self) + ) -> RST_U0_IMG_GPU_RSTN_APB_W { + RST_U0_IMG_GPU_RSTN_APB_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_img_gpu_rstn_doma( &mut self, - ) -> RST_U0_IMG_GPU_RSTN_DOMA_W { - RST_U0_IMG_GPU_RSTN_DOMA_W::new(self) + ) -> RST_U0_IMG_GPU_RSTN_DOMA_W { + RST_U0_IMG_GPU_RSTN_DOMA_W::new(self, 22) } #[doc = "Bit 23 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_apb_bus_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W::new(self, 23) } #[doc = "Bit 24 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_axicfg0_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W::new(self, 24) } #[doc = "Bit 25 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_cpu_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W::new(self, 25) } #[doc = "Bit 26 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_disp_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W::new(self, 26) } #[doc = "Bit 27 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_gpu_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W::new(self, 27) } #[doc = "Bit 28 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_isp_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W::new(self, 28) } #[doc = "Bit 29 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_ddrc_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W::new(self, 29) } #[doc = "Bit 30 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_stg_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W::new(self, 30) } #[doc = "Bit 31 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_vdec_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/syscrg_rst1_status.rs b/jh7110-vf2-12a-pac/src/syscrg/syscrg_rst1_status.rs index 5eabcc1..8c45e48 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/syscrg_rst1_status.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/syscrg_rst1_status.rs @@ -5,135 +5,132 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_sft7100_noc_bus_reset_venc_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_R = crate::BitReader; #[doc = "Field `rstn_u0_sft7100_noc_bus_reset_venc_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg1_dec_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg1_dec_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg1_dec_rstn_main` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg1_dec_rstn_main` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_main` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_main` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_main_div` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_main_div` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_hifi4` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_hifi4` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DDR_SFT7110_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DDR_SFT7110_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DDR_SFT7110_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_osc` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DDR_SFT7110_RSTN_OSC_R = crate::BitReader; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_osc` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DDR_SFT7110_RSTN_OSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DDR_SFT7110_RSTN_OSC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DDR_SFT7110_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DDR_SFT7110_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DDR_SFT7110_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dom_isp_top_rstn_dom_isp_top_ip_top_reset_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_R = crate::BitReader; #[doc = "Field `rstn_u0_dom_isp_top_rstn_dom_isp_top_ip_top_reset_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dom_isp_top_rstn_dom_isp_top_rstn_isp_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_dom_isp_top_rstn_dom_isp_top_rstn_isp_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_R = crate::BitReader; #[doc = "Field `rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W<'a, REG> = + crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_codaj12_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CODAJ12_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_codaj12_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CODAJ12_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CODAJ12_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_codaj12_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CODAJ12_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u0_codaj12_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CODAJ12_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CODAJ12_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_codaj12_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CODAJ12_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_codaj12_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CODAJ12_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CODAJ12_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave511_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE511_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_wave511_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE511_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE511_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave511_rstn_bpu` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE511_RSTN_BPU_R = crate::BitReader; #[doc = "Field `rstn_u0_wave511_rstn_bpu` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE511_RSTN_BPU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE511_RSTN_BPU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave511_rstn_vce` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE511_RSTN_VCE_R = crate::BitReader; #[doc = "Field `rstn_u0_wave511_rstn_vce` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE511_RSTN_VCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE511_RSTN_VCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave511_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE511_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_wave511_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE511_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE511_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_vdec_jpg_arb_jpgresetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_VDEC_JPG_ARB_JPGRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_vdec_jpg_arb_jpgresetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_vdec_jpg_arb_mainresetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_VDEC_JPG_ARB_MAINRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_vdec_jpg_arb_mainresetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_aximem_128b_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXIMEM_128B_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_aximem_128b_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXIMEM_128B_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXIMEM_128B_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave420l_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE420L_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_wave420l_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE420L_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE420L_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave420l_rstn_bpu` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE420L_RSTN_BPU_R = crate::BitReader; #[doc = "Field `rstn_u0_wave420l_rstn_bpu` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE420L_RSTN_BPU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE420L_RSTN_BPU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave420l_rstn_vce` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE420L_RSTN_VCE_R = crate::BitReader; #[doc = "Field `rstn_u0_wave420l_rstn_vce` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE420L_RSTN_VCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE420L_RSTN_VCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave420l_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE420L_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_wave420l_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE420L_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE420L_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_aximem_128b_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_AXIMEM_128B_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u1_aximem_128b_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_AXIMEM_128B_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_AXIMEM_128B_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_aximem_128b_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_AXIMEM_128B_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u2_aximem_128b_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_AXIMEM_128B_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_AXIMEM_128B_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_intmem_rom_sram_rstn_rom` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_R = crate::BitReader; #[doc = "Field `rstn_u0_intmem_rom_sram_rstn_rom` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdns_qspi_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDNS_QSPI_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdns_qspi_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDNS_QSPI_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDNS_QSPI_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdns_qspi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDNS_QSPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdns_qspi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDNS_QSPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDNS_QSPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdns_qspi_rstn_ref` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDNS_QSPI_RSTN_REF_R = crate::BitReader; #[doc = "Field `rstn_u0_cdns_qspi_rstn_ref` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDNS_QSPI_RSTN_REF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDNS_QSPI_RSTN_REF_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -310,258 +307,262 @@ impl W { #[must_use] pub fn rstn_u0_sft7100_noc_bus_reset_venc_axi_n( &mut self, - ) -> RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W { - RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W::new(self) + ) -> RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W { + RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg1_dec_rstn_ahb( &mut self, - ) -> RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W { - RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W::new(self) + ) -> RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W { + RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg1_dec_rstn_main( &mut self, - ) -> RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W { - RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W::new(self) + ) -> RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W { + RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg0_dec_rstn_main( &mut self, - ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W { - RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W::new(self) + ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W { + RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg0_dec_rstn_main_div( &mut self, - ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W { - RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W::new(self) + ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W { + RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg0_dec_rstn_hifi4( &mut self, - ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W { - RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W::new(self) + ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W { + RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_ddr_sft7110_rstn_axi( &mut self, - ) -> RSTN_U0_DDR_SFT7110_RSTN_AXI_W { - RSTN_U0_DDR_SFT7110_RSTN_AXI_W::new(self) + ) -> RSTN_U0_DDR_SFT7110_RSTN_AXI_W { + RSTN_U0_DDR_SFT7110_RSTN_AXI_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_ddr_sft7110_rstn_osc( &mut self, - ) -> RSTN_U0_DDR_SFT7110_RSTN_OSC_W { - RSTN_U0_DDR_SFT7110_RSTN_OSC_W::new(self) + ) -> RSTN_U0_DDR_SFT7110_RSTN_OSC_W { + RSTN_U0_DDR_SFT7110_RSTN_OSC_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_ddr_sft7110_rstn_apb( &mut self, - ) -> RSTN_U0_DDR_SFT7110_RSTN_APB_W { - RSTN_U0_DDR_SFT7110_RSTN_APB_W::new(self) + ) -> RSTN_U0_DDR_SFT7110_RSTN_APB_W { + RSTN_U0_DDR_SFT7110_RSTN_APB_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dom_isp_top_rstn_dom_isp_top_ip_top_reset_n( &mut self, - ) -> RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W { - RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W::new(self) + ) -> RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W { + RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dom_isp_top_rstn_dom_isp_top_rstn_isp_axi( &mut self, - ) -> RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W { - RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W::new(self) + ) -> RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W { + RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src( &mut self, - ) -> RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W { - RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W::new(self) + ) -> RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W { + RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_codaj12_rstn_axi( &mut self, - ) -> RSTN_U0_CODAJ12_RSTN_AXI_W { - RSTN_U0_CODAJ12_RSTN_AXI_W::new(self) + ) -> RSTN_U0_CODAJ12_RSTN_AXI_W { + RSTN_U0_CODAJ12_RSTN_AXI_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_codaj12_rstn_core( &mut self, - ) -> RSTN_U0_CODAJ12_RSTN_CORE_W { - RSTN_U0_CODAJ12_RSTN_CORE_W::new(self) + ) -> RSTN_U0_CODAJ12_RSTN_CORE_W { + RSTN_U0_CODAJ12_RSTN_CORE_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_codaj12_rstn_apb( &mut self, - ) -> RSTN_U0_CODAJ12_RSTN_APB_W { - RSTN_U0_CODAJ12_RSTN_APB_W::new(self) + ) -> RSTN_U0_CODAJ12_RSTN_APB_W { + RSTN_U0_CODAJ12_RSTN_APB_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave511_rstn_axi( &mut self, - ) -> RSTN_U0_WAVE511_RSTN_AXI_W { - RSTN_U0_WAVE511_RSTN_AXI_W::new(self) + ) -> RSTN_U0_WAVE511_RSTN_AXI_W { + RSTN_U0_WAVE511_RSTN_AXI_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave511_rstn_bpu( &mut self, - ) -> RSTN_U0_WAVE511_RSTN_BPU_W { - RSTN_U0_WAVE511_RSTN_BPU_W::new(self) + ) -> RSTN_U0_WAVE511_RSTN_BPU_W { + RSTN_U0_WAVE511_RSTN_BPU_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave511_rstn_vce( &mut self, - ) -> RSTN_U0_WAVE511_RSTN_VCE_W { - RSTN_U0_WAVE511_RSTN_VCE_W::new(self) + ) -> RSTN_U0_WAVE511_RSTN_VCE_W { + RSTN_U0_WAVE511_RSTN_VCE_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave511_rstn_apb( &mut self, - ) -> RSTN_U0_WAVE511_RSTN_APB_W { - RSTN_U0_WAVE511_RSTN_APB_W::new(self) + ) -> RSTN_U0_WAVE511_RSTN_APB_W { + RSTN_U0_WAVE511_RSTN_APB_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_vdec_jpg_arb_jpgresetn( &mut self, - ) -> RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W { - RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W::new(self) + ) -> RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W { + RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_vdec_jpg_arb_mainresetn( &mut self, - ) -> RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W { - RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W::new(self) + ) -> RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W { + RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_aximem_128b_rstn_axi( &mut self, - ) -> RSTN_U0_AXIMEM_128B_RSTN_AXI_W { - RSTN_U0_AXIMEM_128B_RSTN_AXI_W::new(self) + ) -> RSTN_U0_AXIMEM_128B_RSTN_AXI_W { + RSTN_U0_AXIMEM_128B_RSTN_AXI_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave420l_rstn_axi( &mut self, - ) -> RSTN_U0_WAVE420L_RSTN_AXI_W { - RSTN_U0_WAVE420L_RSTN_AXI_W::new(self) + ) -> RSTN_U0_WAVE420L_RSTN_AXI_W { + RSTN_U0_WAVE420L_RSTN_AXI_W::new(self, 22) } #[doc = "Bit 23 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave420l_rstn_bpu( &mut self, - ) -> RSTN_U0_WAVE420L_RSTN_BPU_W { - RSTN_U0_WAVE420L_RSTN_BPU_W::new(self) + ) -> RSTN_U0_WAVE420L_RSTN_BPU_W { + RSTN_U0_WAVE420L_RSTN_BPU_W::new(self, 23) } #[doc = "Bit 24 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave420l_rstn_vce( &mut self, - ) -> RSTN_U0_WAVE420L_RSTN_VCE_W { - RSTN_U0_WAVE420L_RSTN_VCE_W::new(self) + ) -> RSTN_U0_WAVE420L_RSTN_VCE_W { + RSTN_U0_WAVE420L_RSTN_VCE_W::new(self, 24) } #[doc = "Bit 25 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave420l_rstn_apb( &mut self, - ) -> RSTN_U0_WAVE420L_RSTN_APB_W { - RSTN_U0_WAVE420L_RSTN_APB_W::new(self) + ) -> RSTN_U0_WAVE420L_RSTN_APB_W { + RSTN_U0_WAVE420L_RSTN_APB_W::new(self, 25) } #[doc = "Bit 26 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_aximem_128b_rstn_axi( &mut self, - ) -> RSTN_U1_AXIMEM_128B_RSTN_AXI_W { - RSTN_U1_AXIMEM_128B_RSTN_AXI_W::new(self) + ) -> RSTN_U1_AXIMEM_128B_RSTN_AXI_W { + RSTN_U1_AXIMEM_128B_RSTN_AXI_W::new(self, 26) } #[doc = "Bit 27 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u2_aximem_128b_rstn_axi( &mut self, - ) -> RSTN_U2_AXIMEM_128B_RSTN_AXI_W { - RSTN_U2_AXIMEM_128B_RSTN_AXI_W::new(self) + ) -> RSTN_U2_AXIMEM_128B_RSTN_AXI_W { + RSTN_U2_AXIMEM_128B_RSTN_AXI_W::new(self, 27) } #[doc = "Bit 28 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_intmem_rom_sram_rstn_rom( &mut self, - ) -> RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W { - RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W::new(self) + ) -> RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W { + RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W::new(self, 28) } #[doc = "Bit 29 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdns_qspi_rstn_ahb( &mut self, - ) -> RSTN_U0_CDNS_QSPI_RSTN_AHB_W { - RSTN_U0_CDNS_QSPI_RSTN_AHB_W::new(self) + ) -> RSTN_U0_CDNS_QSPI_RSTN_AHB_W { + RSTN_U0_CDNS_QSPI_RSTN_AHB_W::new(self, 29) } #[doc = "Bit 30 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdns_qspi_rstn_apb( &mut self, - ) -> RSTN_U0_CDNS_QSPI_RSTN_APB_W { - RSTN_U0_CDNS_QSPI_RSTN_APB_W::new(self) + ) -> RSTN_U0_CDNS_QSPI_RSTN_APB_W { + RSTN_U0_CDNS_QSPI_RSTN_APB_W::new(self, 30) } #[doc = "Bit 31 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdns_qspi_rstn_ref( &mut self, - ) -> RSTN_U0_CDNS_QSPI_RSTN_REF_W { - RSTN_U0_CDNS_QSPI_RSTN_REF_W::new(self) + ) -> RSTN_U0_CDNS_QSPI_RSTN_REF_W { + RSTN_U0_CDNS_QSPI_RSTN_REF_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/syscrg_rst2_status.rs b/jh7110-vf2-12a-pac/src/syscrg/syscrg_rst2_status.rs index f224d7e..34bfc81 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/syscrg_rst2_status.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/syscrg_rst2_status.rs @@ -5,131 +5,131 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_sdio_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SDIO_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_sdio_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SDIO_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SDIO_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_sdi_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_SDI_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u1_sdi_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_SDI_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_SDI_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_gmac5_axi64_aresetn_i` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_GMAC5_AXI64_ARESETN_I_R = crate::BitReader; #[doc = "Field `rstn_u1_gmac5_axi64_aresetn_i` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_GMAC5_AXI64_ARESETN_I_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_GMAC5_AXI64_ARESETN_I_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_gmac5_axi64_hresetn_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_GMAC5_AXI64_HRESETN_N_R = crate::BitReader; #[doc = "Field `rstn_u1_gmac5_axi64_hresetn_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_GMAC5_AXI64_HRESETN_N_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_GMAC5_AXI64_HRESETN_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_mailbox_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_MAILBOX_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_mailbox_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_MAILBOX_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_MAILBOX_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u2_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u3_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U3_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u3_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U3_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U3_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u4_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U4_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u4_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U4_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U4_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u5_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U5_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u5_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U5_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U5_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u6_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U6_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u6_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U6_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U6_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u2_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u3_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U3_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u3_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U3_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U3_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u4_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U4_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u4_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U4_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U4_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u5_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U5_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u5_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U5_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U5_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u6_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U6_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u6_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U6_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U6_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u0_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u1_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u2_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u2_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u3_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U3_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u3_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U3_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U3_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u3_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U3_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u3_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U3_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U3_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u4_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U4_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u4_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U4_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U4_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u4_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U4_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u4_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U4_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U4_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u5_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U5_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u5_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U5_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U5_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u6_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U6_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u6_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U6_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U6_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdns_spdif_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDNS_SPDIF_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdns_spdif_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDNS_SPDIF_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDNS_SPDIF_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -296,242 +296,222 @@ impl W { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_sdio_rstn_ahb(&mut self) -> RSTN_U0_SDIO_RSTN_AHB_W { - RSTN_U0_SDIO_RSTN_AHB_W::new(self) + pub fn rstn_u0_sdio_rstn_ahb(&mut self) -> RSTN_U0_SDIO_RSTN_AHB_W { + RSTN_U0_SDIO_RSTN_AHB_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u1_sdi_rstn_ahb(&mut self) -> RSTN_U1_SDI_RSTN_AHB_W { - RSTN_U1_SDI_RSTN_AHB_W::new(self) + pub fn rstn_u1_sdi_rstn_ahb(&mut self) -> RSTN_U1_SDI_RSTN_AHB_W { + RSTN_U1_SDI_RSTN_AHB_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_gmac5_axi64_aresetn_i( &mut self, - ) -> RSTN_U1_GMAC5_AXI64_ARESETN_I_W { - RSTN_U1_GMAC5_AXI64_ARESETN_I_W::new(self) + ) -> RSTN_U1_GMAC5_AXI64_ARESETN_I_W { + RSTN_U1_GMAC5_AXI64_ARESETN_I_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_gmac5_axi64_hresetn_n( &mut self, - ) -> RSTN_U1_GMAC5_AXI64_HRESETN_N_W { - RSTN_U1_GMAC5_AXI64_HRESETN_N_W::new(self) + ) -> RSTN_U1_GMAC5_AXI64_HRESETN_N_W { + RSTN_U1_GMAC5_AXI64_HRESETN_N_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_mailbox_presetn( &mut self, - ) -> RSTN_U0_MAILBOX_PRESETN_W { - RSTN_U0_MAILBOX_PRESETN_W::new(self) + ) -> RSTN_U0_MAILBOX_PRESETN_W { + RSTN_U0_MAILBOX_PRESETN_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U0_SSP_SPI_RSTN_APB_W { - RSTN_U0_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U0_SSP_SPI_RSTN_APB_W { + RSTN_U0_SSP_SPI_RSTN_APB_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U1_SSP_SPI_RSTN_APB_W { - RSTN_U1_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U1_SSP_SPI_RSTN_APB_W { + RSTN_U1_SSP_SPI_RSTN_APB_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u2_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U2_SSP_SPI_RSTN_APB_W { - RSTN_U2_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U2_SSP_SPI_RSTN_APB_W { + RSTN_U2_SSP_SPI_RSTN_APB_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u3_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U3_SSP_SPI_RSTN_APB_W { - RSTN_U3_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U3_SSP_SPI_RSTN_APB_W { + RSTN_U3_SSP_SPI_RSTN_APB_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u4_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U4_SSP_SPI_RSTN_APB_W { - RSTN_U4_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U4_SSP_SPI_RSTN_APB_W { + RSTN_U4_SSP_SPI_RSTN_APB_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u5_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U5_SSP_SPI_RSTN_APB_W { - RSTN_U5_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U5_SSP_SPI_RSTN_APB_W { + RSTN_U5_SSP_SPI_RSTN_APB_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u6_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U6_SSP_SPI_RSTN_APB_W { - RSTN_U6_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U6_SSP_SPI_RSTN_APB_W { + RSTN_U6_SSP_SPI_RSTN_APB_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_i2c_rstn_apb(&mut self) -> RSTN_U0_I2C_RSTN_APB_W { - RSTN_U0_I2C_RSTN_APB_W::new(self) + pub fn rstn_u0_i2c_rstn_apb(&mut self) -> RSTN_U0_I2C_RSTN_APB_W { + RSTN_U0_I2C_RSTN_APB_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u1_i2c_rstn_apb(&mut self) -> RSTN_U1_I2C_RSTN_APB_W { - RSTN_U1_I2C_RSTN_APB_W::new(self) + pub fn rstn_u1_i2c_rstn_apb(&mut self) -> RSTN_U1_I2C_RSTN_APB_W { + RSTN_U1_I2C_RSTN_APB_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u2_i2c_rstn_apb(&mut self) -> RSTN_U2_I2C_RSTN_APB_W { - RSTN_U2_I2C_RSTN_APB_W::new(self) + pub fn rstn_u2_i2c_rstn_apb(&mut self) -> RSTN_U2_I2C_RSTN_APB_W { + RSTN_U2_I2C_RSTN_APB_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u3_i2c_rstn_apb(&mut self) -> RSTN_U3_I2C_RSTN_APB_W { - RSTN_U3_I2C_RSTN_APB_W::new(self) + pub fn rstn_u3_i2c_rstn_apb(&mut self) -> RSTN_U3_I2C_RSTN_APB_W { + RSTN_U3_I2C_RSTN_APB_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u4_i2c_rstn_apb(&mut self) -> RSTN_U4_I2C_RSTN_APB_W { - RSTN_U4_I2C_RSTN_APB_W::new(self) + pub fn rstn_u4_i2c_rstn_apb(&mut self) -> RSTN_U4_I2C_RSTN_APB_W { + RSTN_U4_I2C_RSTN_APB_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u5_i2c_rstn_apb(&mut self) -> RSTN_U5_I2C_RSTN_APB_W { - RSTN_U5_I2C_RSTN_APB_W::new(self) + pub fn rstn_u5_i2c_rstn_apb(&mut self) -> RSTN_U5_I2C_RSTN_APB_W { + RSTN_U5_I2C_RSTN_APB_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u6_i2c_rstn_apb(&mut self) -> RSTN_U6_I2C_RSTN_APB_W { - RSTN_U6_I2C_RSTN_APB_W::new(self) + pub fn rstn_u6_i2c_rstn_apb(&mut self) -> RSTN_U6_I2C_RSTN_APB_W { + RSTN_U6_I2C_RSTN_APB_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_uart_rstn_apb( - &mut self, - ) -> RSTN_U0_UART_RSTN_APB_W { - RSTN_U0_UART_RSTN_APB_W::new(self) + pub fn rstn_u0_uart_rstn_apb(&mut self) -> RSTN_U0_UART_RSTN_APB_W { + RSTN_U0_UART_RSTN_APB_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_uart_rstn_core( - &mut self, - ) -> RSTN_U0_UART_RSTN_CORE_W { - RSTN_U0_UART_RSTN_CORE_W::new(self) + pub fn rstn_u0_uart_rstn_core(&mut self) -> RSTN_U0_UART_RSTN_CORE_W { + RSTN_U0_UART_RSTN_CORE_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u1_uart_rstn_apb( - &mut self, - ) -> RSTN_U1_UART_RSTN_APB_W { - RSTN_U1_UART_RSTN_APB_W::new(self) + pub fn rstn_u1_uart_rstn_apb(&mut self) -> RSTN_U1_UART_RSTN_APB_W { + RSTN_U1_UART_RSTN_APB_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u1_uart_rstn_core( - &mut self, - ) -> RSTN_U1_UART_RSTN_CORE_W { - RSTN_U1_UART_RSTN_CORE_W::new(self) + pub fn rstn_u1_uart_rstn_core(&mut self) -> RSTN_U1_UART_RSTN_CORE_W { + RSTN_U1_UART_RSTN_CORE_W::new(self, 22) } #[doc = "Bit 23 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u2_uart_rstn_apb( - &mut self, - ) -> RSTN_U2_UART_RSTN_APB_W { - RSTN_U2_UART_RSTN_APB_W::new(self) + pub fn rstn_u2_uart_rstn_apb(&mut self) -> RSTN_U2_UART_RSTN_APB_W { + RSTN_U2_UART_RSTN_APB_W::new(self, 23) } #[doc = "Bit 24 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u2_uart_rstn_core( - &mut self, - ) -> RSTN_U2_UART_RSTN_CORE_W { - RSTN_U2_UART_RSTN_CORE_W::new(self) + pub fn rstn_u2_uart_rstn_core(&mut self) -> RSTN_U2_UART_RSTN_CORE_W { + RSTN_U2_UART_RSTN_CORE_W::new(self, 24) } #[doc = "Bit 25 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u3_uart_rstn_apb( - &mut self, - ) -> RSTN_U3_UART_RSTN_APB_W { - RSTN_U3_UART_RSTN_APB_W::new(self) + pub fn rstn_u3_uart_rstn_apb(&mut self) -> RSTN_U3_UART_RSTN_APB_W { + RSTN_U3_UART_RSTN_APB_W::new(self, 25) } #[doc = "Bit 26 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u3_uart_rstn_core( - &mut self, - ) -> RSTN_U3_UART_RSTN_CORE_W { - RSTN_U3_UART_RSTN_CORE_W::new(self) + pub fn rstn_u3_uart_rstn_core(&mut self) -> RSTN_U3_UART_RSTN_CORE_W { + RSTN_U3_UART_RSTN_CORE_W::new(self, 26) } #[doc = "Bit 27 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u4_uart_rstn_apb( - &mut self, - ) -> RSTN_U4_UART_RSTN_APB_W { - RSTN_U4_UART_RSTN_APB_W::new(self) + pub fn rstn_u4_uart_rstn_apb(&mut self) -> RSTN_U4_UART_RSTN_APB_W { + RSTN_U4_UART_RSTN_APB_W::new(self, 27) } #[doc = "Bit 28 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u4_uart_rstn_core( - &mut self, - ) -> RSTN_U4_UART_RSTN_CORE_W { - RSTN_U4_UART_RSTN_CORE_W::new(self) + pub fn rstn_u4_uart_rstn_core(&mut self) -> RSTN_U4_UART_RSTN_CORE_W { + RSTN_U4_UART_RSTN_CORE_W::new(self, 28) } #[doc = "Bit 29 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u5_uart_rstn_apb( - &mut self, - ) -> RSTN_U5_UART_RSTN_APB_W { - RSTN_U5_UART_RSTN_APB_W::new(self) + pub fn rstn_u5_uart_rstn_apb(&mut self) -> RSTN_U5_UART_RSTN_APB_W { + RSTN_U5_UART_RSTN_APB_W::new(self, 29) } #[doc = "Bit 30 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u6_uart_rstn_core( - &mut self, - ) -> RSTN_U6_UART_RSTN_CORE_W { - RSTN_U6_UART_RSTN_CORE_W::new(self) + pub fn rstn_u6_uart_rstn_core(&mut self) -> RSTN_U6_UART_RSTN_CORE_W { + RSTN_U6_UART_RSTN_CORE_W::new(self, 30) } #[doc = "Bit 31 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdns_spdif_rstn_apb( &mut self, - ) -> RSTN_U0_CDNS_SPDIF_RSTN_APB_W { - RSTN_U0_CDNS_SPDIF_RSTN_APB_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> RSTN_U0_CDNS_SPDIF_RSTN_APB_W { + RSTN_U0_CDNS_SPDIF_RSTN_APB_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/syscrg_rst3_status.rs b/jh7110-vf2-12a-pac/src/syscrg/syscrg_rst3_status.rs index 1017bc5..30c9c71 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/syscrg_rst3_status.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/syscrg_rst3_status.rs @@ -5,123 +5,123 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_pwmdac_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PWMDAC_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_pwmdac_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PWMDAC_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PWMDAC_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_pdm_4mic_rstn_dmic` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PDM_4MIC_RSTN_DMIC_R = crate::BitReader; #[doc = "Field `rstn_u0_pdm_4mic_rstn_dmic` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PDM_4MIC_RSTN_DMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PDM_4MIC_RSTN_DMIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_pdm_4mic_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PDM_4MIC_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_pdm_4mic_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PDM_4MIC_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PDM_4MIC_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2srx_3ch_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2SRX_3CH_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_i2srx_3ch_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2SRX_3CH_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2SRX_3CH_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2srx_3ch_rstn_bclk` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2SRX_3CH_RSTN_BCLK_R = crate::BitReader; #[doc = "Field `rstn_u0_i2srx_3ch_rstn_bclk` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2SRX_3CH_RSTN_BCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2SRX_3CH_RSTN_BCLK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2stx_4ch_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2STX_4CH_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_i2stx_4ch_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2STX_4CH_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2STX_4CH_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2stx_4ch_rstn_bclk` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2STX_4CH_RSTN_BCLK_R = crate::BitReader; #[doc = "Field `rstn_u0_i2stx_4ch_rstn_bclk` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2STX_4CH_RSTN_BCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2STX_4CH_RSTN_BCLK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_i2stx_4ch_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_I2STX_4CH_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_i2stx_4ch_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_I2STX_4CH_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_I2STX_4CH_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_i2stx_4ch_rstn_bclk` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_I2STX_4CH_RSTN_BCLK_R = crate::BitReader; #[doc = "Field `rstn_u1_i2stx_4ch_rstn_bclk` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_I2STX_4CH_RSTN_BCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_I2STX_4CH_RSTN_BCLK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_tdm16slot_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TDM16SLOT_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_tdm16slot_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TDM16SLOT_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TDM16SLOT_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_tdm16slot_rstn_tdm` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TDM16SLOT_RSTN_TDM_R = crate::BitReader; #[doc = "Field `rstn_u0_tdm16slot_rstn_tdm` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TDM16SLOT_RSTN_TDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TDM16SLOT_RSTN_TDM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_tdm16slot_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TDM16SLOT_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_tdm16slot_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TDM16SLOT_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TDM16SLOT_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_pwm_8ch_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PWM_8CH_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_pwm_8ch_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PWM_8CH_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PWM_8CH_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dskit_wdt_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DSKIT_WDT_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_dskit_wdt_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DSKIT_WDT_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DSKIT_WDT_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dskit_wdt_rstn_wdt` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DSKIT_WDT_RSTN_WDT_R = crate::BitReader; #[doc = "Field `rstn_u0_dskit_wdt_rstn_wdt` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DSKIT_WDT_RSTN_WDT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DSKIT_WDT_RSTN_WDT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_can_ctrl_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CAN_CTRL_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_can_ctrl_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CAN_CTRL_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CAN_CTRL_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_can_ctrl_rstn_can` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CAN_CTRL_RSTN_CAN_R = crate::BitReader; #[doc = "Field `rstn_u0_can_ctrl_rstn_can` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CAN_CTRL_RSTN_CAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CAN_CTRL_RSTN_CAN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_can_ctrl_rstn_timer` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CAN_CTRL_RSTN_TIMER_R = crate::BitReader; #[doc = "Field `rstn_u0_can_ctrl_rstn_timer` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CAN_CTRL_RSTN_TIMER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CAN_CTRL_RSTN_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_can_ctrl_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_CAN_CTRL_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_can_ctrl_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_CAN_CTRL_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_CAN_CTRL_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_can_ctrl_rstn_can` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_CAN_CTRL_RSTN_CAN_R = crate::BitReader; #[doc = "Field `rstn_u1_can_ctrl_rstn_can` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_CAN_CTRL_RSTN_CAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_CAN_CTRL_RSTN_CAN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_can_ctrl_rstn_timer` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_CAN_CTRL_RSTN_TIMER_R = crate::BitReader; #[doc = "Field `rstn_u1_can_ctrl_rstn_timer` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_CAN_CTRL_RSTN_TIMER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_CAN_CTRL_RSTN_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_timer0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_TIMER0_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_timer0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_TIMER0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_TIMER0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_time10` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_TIME10_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_time10` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_TIME10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_TIME10_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_timer2` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_TIMER2_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_timer2` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_TIMER2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_TIMER2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_timer3` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_TIMER3_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_timer3` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_TIMER3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_TIMER3_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_int_ctrl_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_INT_CTRL_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_int_ctrl_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_INT_CTRL_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_INT_CTRL_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_temp_sensor_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TEMP_SENSOR_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_temp_sensor_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TEMP_SENSOR_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TEMP_SENSOR_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_temp_sensor_rstn_temp` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TEMP_SENSOR_RSTN_TEMP_R = crate::BitReader; #[doc = "Field `rstn_u0_temp_sensor_rstn_temp` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_jtag_certification_rst_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_JTAG_CERTIFICATION_RST_N_R = crate::BitReader; #[doc = "Field `rstn_u0_jtag_certification_rst_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_JTAG_CERTIFICATION_RST_N_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_JTAG_CERTIFICATION_RST_N_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -280,242 +280,246 @@ impl W { #[must_use] pub fn rstn_u0_pwmdac_rstn_apb( &mut self, - ) -> RSTN_U0_PWMDAC_RSTN_APB_W { - RSTN_U0_PWMDAC_RSTN_APB_W::new(self) + ) -> RSTN_U0_PWMDAC_RSTN_APB_W { + RSTN_U0_PWMDAC_RSTN_APB_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_pdm_4mic_rstn_dmic( &mut self, - ) -> RSTN_U0_PDM_4MIC_RSTN_DMIC_W { - RSTN_U0_PDM_4MIC_RSTN_DMIC_W::new(self) + ) -> RSTN_U0_PDM_4MIC_RSTN_DMIC_W { + RSTN_U0_PDM_4MIC_RSTN_DMIC_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_pdm_4mic_rstn_apb( &mut self, - ) -> RSTN_U0_PDM_4MIC_RSTN_APB_W { - RSTN_U0_PDM_4MIC_RSTN_APB_W::new(self) + ) -> RSTN_U0_PDM_4MIC_RSTN_APB_W { + RSTN_U0_PDM_4MIC_RSTN_APB_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_i2srx_3ch_rstn_apb( &mut self, - ) -> RSTN_U0_I2SRX_3CH_RSTN_APB_W { - RSTN_U0_I2SRX_3CH_RSTN_APB_W::new(self) + ) -> RSTN_U0_I2SRX_3CH_RSTN_APB_W { + RSTN_U0_I2SRX_3CH_RSTN_APB_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_i2srx_3ch_rstn_bclk( &mut self, - ) -> RSTN_U0_I2SRX_3CH_RSTN_BCLK_W { - RSTN_U0_I2SRX_3CH_RSTN_BCLK_W::new(self) + ) -> RSTN_U0_I2SRX_3CH_RSTN_BCLK_W { + RSTN_U0_I2SRX_3CH_RSTN_BCLK_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_i2stx_4ch_rstn_apb( &mut self, - ) -> RSTN_U0_I2STX_4CH_RSTN_APB_W { - RSTN_U0_I2STX_4CH_RSTN_APB_W::new(self) + ) -> RSTN_U0_I2STX_4CH_RSTN_APB_W { + RSTN_U0_I2STX_4CH_RSTN_APB_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_i2stx_4ch_rstn_bclk( &mut self, - ) -> RSTN_U0_I2STX_4CH_RSTN_BCLK_W { - RSTN_U0_I2STX_4CH_RSTN_BCLK_W::new(self) + ) -> RSTN_U0_I2STX_4CH_RSTN_BCLK_W { + RSTN_U0_I2STX_4CH_RSTN_BCLK_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_i2stx_4ch_rstn_apb( &mut self, - ) -> RSTN_U1_I2STX_4CH_RSTN_APB_W { - RSTN_U1_I2STX_4CH_RSTN_APB_W::new(self) + ) -> RSTN_U1_I2STX_4CH_RSTN_APB_W { + RSTN_U1_I2STX_4CH_RSTN_APB_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_i2stx_4ch_rstn_bclk( &mut self, - ) -> RSTN_U1_I2STX_4CH_RSTN_BCLK_W { - RSTN_U1_I2STX_4CH_RSTN_BCLK_W::new(self) + ) -> RSTN_U1_I2STX_4CH_RSTN_BCLK_W { + RSTN_U1_I2STX_4CH_RSTN_BCLK_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_tdm16slot_rstn_ahb( &mut self, - ) -> RSTN_U0_TDM16SLOT_RSTN_AHB_W { - RSTN_U0_TDM16SLOT_RSTN_AHB_W::new(self) + ) -> RSTN_U0_TDM16SLOT_RSTN_AHB_W { + RSTN_U0_TDM16SLOT_RSTN_AHB_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_tdm16slot_rstn_tdm( &mut self, - ) -> RSTN_U0_TDM16SLOT_RSTN_TDM_W { - RSTN_U0_TDM16SLOT_RSTN_TDM_W::new(self) + ) -> RSTN_U0_TDM16SLOT_RSTN_TDM_W { + RSTN_U0_TDM16SLOT_RSTN_TDM_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_tdm16slot_rstn_apb( &mut self, - ) -> RSTN_U0_TDM16SLOT_RSTN_APB_W { - RSTN_U0_TDM16SLOT_RSTN_APB_W::new(self) + ) -> RSTN_U0_TDM16SLOT_RSTN_APB_W { + RSTN_U0_TDM16SLOT_RSTN_APB_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_pwm_8ch_rstn_apb( &mut self, - ) -> RSTN_U0_PWM_8CH_RSTN_APB_W { - RSTN_U0_PWM_8CH_RSTN_APB_W::new(self) + ) -> RSTN_U0_PWM_8CH_RSTN_APB_W { + RSTN_U0_PWM_8CH_RSTN_APB_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dskit_wdt_rstn_apb( &mut self, - ) -> RSTN_U0_DSKIT_WDT_RSTN_APB_W { - RSTN_U0_DSKIT_WDT_RSTN_APB_W::new(self) + ) -> RSTN_U0_DSKIT_WDT_RSTN_APB_W { + RSTN_U0_DSKIT_WDT_RSTN_APB_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dskit_wdt_rstn_wdt( &mut self, - ) -> RSTN_U0_DSKIT_WDT_RSTN_WDT_W { - RSTN_U0_DSKIT_WDT_RSTN_WDT_W::new(self) + ) -> RSTN_U0_DSKIT_WDT_RSTN_WDT_W { + RSTN_U0_DSKIT_WDT_RSTN_WDT_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_can_ctrl_rstn_apb( &mut self, - ) -> RSTN_U0_CAN_CTRL_RSTN_APB_W { - RSTN_U0_CAN_CTRL_RSTN_APB_W::new(self) + ) -> RSTN_U0_CAN_CTRL_RSTN_APB_W { + RSTN_U0_CAN_CTRL_RSTN_APB_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_can_ctrl_rstn_can( &mut self, - ) -> RSTN_U0_CAN_CTRL_RSTN_CAN_W { - RSTN_U0_CAN_CTRL_RSTN_CAN_W::new(self) + ) -> RSTN_U0_CAN_CTRL_RSTN_CAN_W { + RSTN_U0_CAN_CTRL_RSTN_CAN_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_can_ctrl_rstn_timer( &mut self, - ) -> RSTN_U0_CAN_CTRL_RSTN_TIMER_W { - RSTN_U0_CAN_CTRL_RSTN_TIMER_W::new(self) + ) -> RSTN_U0_CAN_CTRL_RSTN_TIMER_W { + RSTN_U0_CAN_CTRL_RSTN_TIMER_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_can_ctrl_rstn_apb( &mut self, - ) -> RSTN_U1_CAN_CTRL_RSTN_APB_W { - RSTN_U1_CAN_CTRL_RSTN_APB_W::new(self) + ) -> RSTN_U1_CAN_CTRL_RSTN_APB_W { + RSTN_U1_CAN_CTRL_RSTN_APB_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_can_ctrl_rstn_can( &mut self, - ) -> RSTN_U1_CAN_CTRL_RSTN_CAN_W { - RSTN_U1_CAN_CTRL_RSTN_CAN_W::new(self) + ) -> RSTN_U1_CAN_CTRL_RSTN_CAN_W { + RSTN_U1_CAN_CTRL_RSTN_CAN_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_can_ctrl_rstn_timer( &mut self, - ) -> RSTN_U1_CAN_CTRL_RSTN_TIMER_W { - RSTN_U1_CAN_CTRL_RSTN_TIMER_W::new(self) + ) -> RSTN_U1_CAN_CTRL_RSTN_TIMER_W { + RSTN_U1_CAN_CTRL_RSTN_TIMER_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_apb( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_APB_W { - RSTN_U0_SI5_TIMER_RSTN_APB_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_APB_W { + RSTN_U0_SI5_TIMER_RSTN_APB_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_timer0( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER0_W { - RSTN_U0_SI5_TIMER_RSTN_TIMER0_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER0_W { + RSTN_U0_SI5_TIMER_RSTN_TIMER0_W::new(self, 22) } #[doc = "Bit 23 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_time10( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_TIME10_W { - RSTN_U0_SI5_TIMER_RSTN_TIME10_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_TIME10_W { + RSTN_U0_SI5_TIMER_RSTN_TIME10_W::new(self, 23) } #[doc = "Bit 24 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_timer2( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER2_W { - RSTN_U0_SI5_TIMER_RSTN_TIMER2_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER2_W { + RSTN_U0_SI5_TIMER_RSTN_TIMER2_W::new(self, 24) } #[doc = "Bit 25 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_timer3( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER3_W { - RSTN_U0_SI5_TIMER_RSTN_TIMER3_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER3_W { + RSTN_U0_SI5_TIMER_RSTN_TIMER3_W::new(self, 25) } #[doc = "Bit 26 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_int_ctrl_rstn_apb( &mut self, - ) -> RSTN_U0_INT_CTRL_RSTN_APB_W { - RSTN_U0_INT_CTRL_RSTN_APB_W::new(self) + ) -> RSTN_U0_INT_CTRL_RSTN_APB_W { + RSTN_U0_INT_CTRL_RSTN_APB_W::new(self, 26) } #[doc = "Bit 27 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_temp_sensor_rstn_apb( &mut self, - ) -> RSTN_U0_TEMP_SENSOR_RSTN_APB_W { - RSTN_U0_TEMP_SENSOR_RSTN_APB_W::new(self) + ) -> RSTN_U0_TEMP_SENSOR_RSTN_APB_W { + RSTN_U0_TEMP_SENSOR_RSTN_APB_W::new(self, 27) } #[doc = "Bit 28 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_temp_sensor_rstn_temp( &mut self, - ) -> RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W { - RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W::new(self) + ) -> RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W { + RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W::new(self, 28) } #[doc = "Bit 29 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_jtag_certification_rst_n( &mut self, - ) -> RSTN_U0_JTAG_CERTIFICATION_RST_N_W { - RSTN_U0_JTAG_CERTIFICATION_RST_N_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> RSTN_U0_JTAG_CERTIFICATION_RST_N_W { + RSTN_U0_JTAG_CERTIFICATION_RST_N_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/syscrg/u7mc_rtc_toggle.rs b/jh7110-vf2-12a-pac/src/syscrg/u7mc_rtc_toggle.rs index 71fbc84..d031079 100644 --- a/jh7110-vf2-12a-pac/src/syscrg/u7mc_rtc_toggle.rs +++ b/jh7110-vf2-12a-pac/src/syscrg/u7mc_rtc_toggle.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=6, Default=6, Min=6, Typical=6"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=6, Default=6, Min=6, Typical=6"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=6, Default=6, Min=6, Typical=6"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=6, Default=6, Min=6, Typical=6"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/trng.rs b/jh7110-vf2-12a-pac/src/trng.rs index c4fa9aa..3f9616e 100644 --- a/jh7110-vf2-12a-pac/src/trng.rs +++ b/jh7110-vf2-12a-pac/src/trng.rs @@ -1,117 +1,183 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + ctrl: CTRL, + stat: STAT, + mode: MODE, + smode: SMODE, + ie: IE, + istat: ISTAT, + _reserved6: [u8; 0x08], + rand0: RAND0, + rand1: RAND1, + rand2: RAND2, + rand3: RAND3, + rand4: RAND4, + rand5: RAND5, + rand6: RAND6, + rand7: RAND7, + _reserved14: [u8; 0x20], + auto_rqsts: AUTO_RQSTS, + auto_age: AUTO_AGE, +} +impl RegisterBlock { #[doc = "0x00 - TRNG CTRL Register"] - pub ctrl: CTRL, + #[inline(always)] + pub const fn ctrl(&self) -> &CTRL { + &self.ctrl + } #[doc = "0x04 - TRNG STAT Register"] - pub stat: STAT, + #[inline(always)] + pub const fn stat(&self) -> &STAT { + &self.stat + } #[doc = "0x08 - TRNG MODE Register"] - pub mode: MODE, + #[inline(always)] + pub const fn mode(&self) -> &MODE { + &self.mode + } #[doc = "0x0c - TRNG SMODE Register"] - pub smode: SMODE, + #[inline(always)] + pub const fn smode(&self) -> &SMODE { + &self.smode + } #[doc = "0x10 - TRNG Interrupt Enable Register"] - pub ie: IE, + #[inline(always)] + pub const fn ie(&self) -> &IE { + &self.ie + } #[doc = "0x14 - TRNG Interrupt Status Register"] - pub istat: ISTAT, - _reserved6: [u8; 0x08], + #[inline(always)] + pub const fn istat(&self) -> &ISTAT { + &self.istat + } #[doc = "0x20 - TRNG RAND 0 Status Register"] - pub rand0: RAND0, + #[inline(always)] + pub const fn rand0(&self) -> &RAND0 { + &self.rand0 + } #[doc = "0x24 - TRNG RAND 1 Status Register"] - pub rand1: RAND1, + #[inline(always)] + pub const fn rand1(&self) -> &RAND1 { + &self.rand1 + } #[doc = "0x28 - TRNG RAND 2 Status Register"] - pub rand2: RAND2, + #[inline(always)] + pub const fn rand2(&self) -> &RAND2 { + &self.rand2 + } #[doc = "0x2c - TRNG RAND 3 Status Register"] - pub rand3: RAND3, + #[inline(always)] + pub const fn rand3(&self) -> &RAND3 { + &self.rand3 + } #[doc = "0x30 - TRNG RAND 4 Status Register"] - pub rand4: RAND4, + #[inline(always)] + pub const fn rand4(&self) -> &RAND4 { + &self.rand4 + } #[doc = "0x34 - TRNG RAND 5 Status Register"] - pub rand5: RAND5, + #[inline(always)] + pub const fn rand5(&self) -> &RAND5 { + &self.rand5 + } #[doc = "0x38 - TRNG RAND 6 Status Register"] - pub rand6: RAND6, + #[inline(always)] + pub const fn rand6(&self) -> &RAND6 { + &self.rand6 + } #[doc = "0x3c - TRNG RAND 7 Status Register"] - pub rand7: RAND7, - _reserved14: [u8; 0x20], + #[inline(always)] + pub const fn rand7(&self) -> &RAND7 { + &self.rand7 + } #[doc = "0x60 - Auto-reseeding after random number requests by host reaches specified counter: 0 - disable counter, other - reload value for internal counter"] - pub auto_rqsts: AUTO_RQSTS, + #[inline(always)] + pub const fn auto_rqsts(&self) -> &AUTO_RQSTS { + &self.auto_rqsts + } #[doc = "0x64 - Auto-reseeding after specified timer countdowns to 0: 0 - disable timer, other - reload value for internal timer"] - pub auto_age: AUTO_AGE, + #[inline(always)] + pub const fn auto_age(&self) -> &AUTO_AGE { + &self.auto_age + } } -#[doc = "ctrl (rw) register accessor: TRNG CTRL Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctrl`] +#[doc = "ctrl (rw) register accessor: TRNG CTRL Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] pub type CTRL = crate::Reg; #[doc = "TRNG CTRL Register"] pub mod ctrl; -#[doc = "stat (rw) register accessor: TRNG STAT Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stat`] +#[doc = "stat (rw) register accessor: TRNG STAT Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] module"] pub type STAT = crate::Reg; #[doc = "TRNG STAT Register"] pub mod stat; -#[doc = "mode (rw) register accessor: TRNG MODE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mode`] +#[doc = "mode (rw) register accessor: TRNG MODE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode`] module"] pub type MODE = crate::Reg; #[doc = "TRNG MODE Register"] pub mod mode; -#[doc = "smode (rw) register accessor: TRNG SMODE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smode::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`smode`] +#[doc = "smode (rw) register accessor: TRNG SMODE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smode::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smode`] module"] pub type SMODE = crate::Reg; #[doc = "TRNG SMODE Register"] pub mod smode; -#[doc = "ie (rw) register accessor: TRNG Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ie::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ie::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ie`] +#[doc = "ie (rw) register accessor: TRNG Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ie::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ie::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ie`] module"] pub type IE = crate::Reg; #[doc = "TRNG Interrupt Enable Register"] pub mod ie; -#[doc = "istat (rw) register accessor: TRNG Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`istat::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`istat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`istat`] +#[doc = "istat (rw) register accessor: TRNG Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`istat::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`istat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@istat`] module"] pub type ISTAT = crate::Reg; #[doc = "TRNG Interrupt Status Register"] pub mod istat; -#[doc = "rand0 (rw) register accessor: TRNG RAND 0 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand0`] +#[doc = "rand0 (rw) register accessor: TRNG RAND 0 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rand0`] module"] pub type RAND0 = crate::Reg; #[doc = "TRNG RAND 0 Status Register"] pub mod rand0; -#[doc = "rand1 (rw) register accessor: TRNG RAND 1 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand1`] +#[doc = "rand1 (rw) register accessor: TRNG RAND 1 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rand1`] module"] pub type RAND1 = crate::Reg; #[doc = "TRNG RAND 1 Status Register"] pub mod rand1; -#[doc = "rand2 (rw) register accessor: TRNG RAND 2 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand2`] +#[doc = "rand2 (rw) register accessor: TRNG RAND 2 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rand2`] module"] pub type RAND2 = crate::Reg; #[doc = "TRNG RAND 2 Status Register"] pub mod rand2; -#[doc = "rand3 (rw) register accessor: TRNG RAND 3 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand3`] +#[doc = "rand3 (rw) register accessor: TRNG RAND 3 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rand3`] module"] pub type RAND3 = crate::Reg; #[doc = "TRNG RAND 3 Status Register"] pub mod rand3; -#[doc = "rand4 (rw) register accessor: TRNG RAND 4 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand4`] +#[doc = "rand4 (rw) register accessor: TRNG RAND 4 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rand4`] module"] pub type RAND4 = crate::Reg; #[doc = "TRNG RAND 4 Status Register"] pub mod rand4; -#[doc = "rand5 (rw) register accessor: TRNG RAND 5 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand5`] +#[doc = "rand5 (rw) register accessor: TRNG RAND 5 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rand5`] module"] pub type RAND5 = crate::Reg; #[doc = "TRNG RAND 5 Status Register"] pub mod rand5; -#[doc = "rand6 (rw) register accessor: TRNG RAND 6 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand6::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand6`] +#[doc = "rand6 (rw) register accessor: TRNG RAND 6 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand6::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rand6`] module"] pub type RAND6 = crate::Reg; #[doc = "TRNG RAND 6 Status Register"] pub mod rand6; -#[doc = "rand7 (rw) register accessor: TRNG RAND 7 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand7::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand7`] +#[doc = "rand7 (rw) register accessor: TRNG RAND 7 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand7::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rand7`] module"] pub type RAND7 = crate::Reg; #[doc = "TRNG RAND 7 Status Register"] pub mod rand7; -#[doc = "auto_rqsts (rw) register accessor: Auto-reseeding after random number requests by host reaches specified counter: 0 - disable counter, other - reload value for internal counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`auto_rqsts::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`auto_rqsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`auto_rqsts`] +#[doc = "auto_rqsts (rw) register accessor: Auto-reseeding after random number requests by host reaches specified counter: 0 - disable counter, other - reload value for internal counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`auto_rqsts::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`auto_rqsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@auto_rqsts`] module"] pub type AUTO_RQSTS = crate::Reg; #[doc = "Auto-reseeding after random number requests by host reaches specified counter: 0 - disable counter, other - reload value for internal counter"] pub mod auto_rqsts; -#[doc = "auto_age (rw) register accessor: Auto-reseeding after specified timer countdowns to 0: 0 - disable timer, other - reload value for internal timer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`auto_age::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`auto_age::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`auto_age`] +#[doc = "auto_age (rw) register accessor: Auto-reseeding after specified timer countdowns to 0: 0 - disable timer, other - reload value for internal timer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`auto_age::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`auto_age::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@auto_age`] module"] pub type AUTO_AGE = crate::Reg; #[doc = "Auto-reseeding after specified timer countdowns to 0: 0 - disable timer, other - reload value for internal timer"] diff --git a/jh7110-vf2-12a-pac/src/trng/auto_age.rs b/jh7110-vf2-12a-pac/src/trng/auto_age.rs index a711c39..3bd24b7 100644 --- a/jh7110-vf2-12a-pac/src/trng/auto_age.rs +++ b/jh7110-vf2-12a-pac/src/trng/auto_age.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `age` reader - Countdown value for auto-reseed timer"] pub type AGE_R = crate::FieldReader; #[doc = "Field `age` writer - Countdown value for auto-reseed timer"] -pub type AGE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type AGE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - Countdown value for auto-reseed timer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - Countdown value for auto-reseed timer"] #[inline(always)] #[must_use] - pub fn age(&mut self) -> AGE_W { - AGE_W::new(self) + pub fn age(&mut self) -> AGE_W { + AGE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/trng/auto_rqsts.rs b/jh7110-vf2-12a-pac/src/trng/auto_rqsts.rs index d6bb092..eae5c89 100644 --- a/jh7110-vf2-12a-pac/src/trng/auto_rqsts.rs +++ b/jh7110-vf2-12a-pac/src/trng/auto_rqsts.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rqsts` reader - Threshold number of reseed requests for auto-reseed counter"] pub type RQSTS_R = crate::FieldReader; #[doc = "Field `rqsts` writer - Threshold number of reseed requests for auto-reseed counter"] -pub type RQSTS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RQSTS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - Threshold number of reseed requests for auto-reseed counter"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - Threshold number of reseed requests for auto-reseed counter"] #[inline(always)] #[must_use] - pub fn rqsts(&mut self) -> RQSTS_W { - RQSTS_W::new(self) + pub fn rqsts(&mut self) -> RQSTS_W { + RQSTS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/trng/ctrl.rs b/jh7110-vf2-12a-pac/src/trng/ctrl.rs index 17511a1..62dea09 100644 --- a/jh7110-vf2-12a-pac/src/trng/ctrl.rs +++ b/jh7110-vf2-12a-pac/src/trng/ctrl.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `exec_nop` reader - Execute a NOP instruction"] pub type EXEC_NOP_R = crate::BitReader; #[doc = "Field `exec_nop` writer - Execute a NOP instruction"] -pub type EXEC_NOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EXEC_NOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gene_randnum` reader - Generate a random number"] pub type GENE_RANDNUM_R = crate::BitReader; #[doc = "Field `gene_randnum` writer - Generate a random number"] -pub type GENE_RANDNUM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GENE_RANDNUM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `exec_randreseed` reader - Reseed the TRNG from noise sources"] pub type EXEC_RANDRESEED_R = crate::BitReader; #[doc = "Field `exec_randreseed` writer - Reseed the TRNG from noise sources"] -pub type EXEC_RANDRESEED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EXEC_RANDRESEED_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Execute a NOP instruction"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bit 0 - Execute a NOP instruction"] #[inline(always)] #[must_use] - pub fn exec_nop(&mut self) -> EXEC_NOP_W { - EXEC_NOP_W::new(self) + pub fn exec_nop(&mut self) -> EXEC_NOP_W { + EXEC_NOP_W::new(self, 0) } #[doc = "Bit 1 - Generate a random number"] #[inline(always)] #[must_use] - pub fn gene_randnum(&mut self) -> GENE_RANDNUM_W { - GENE_RANDNUM_W::new(self) + pub fn gene_randnum(&mut self) -> GENE_RANDNUM_W { + GENE_RANDNUM_W::new(self, 1) } #[doc = "Bit 2 - Reseed the TRNG from noise sources"] #[inline(always)] #[must_use] - pub fn exec_randreseed(&mut self) -> EXEC_RANDRESEED_W { - EXEC_RANDRESEED_W::new(self) + pub fn exec_randreseed(&mut self) -> EXEC_RANDRESEED_W { + EXEC_RANDRESEED_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/trng/ie.rs b/jh7110-vf2-12a-pac/src/trng/ie.rs index dee70fe..8fdd65b 100644 --- a/jh7110-vf2-12a-pac/src/trng/ie.rs +++ b/jh7110-vf2-12a-pac/src/trng/ie.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `rand_rdy_en` reader - RAND Ready Enable"] pub type RAND_RDY_EN_R = crate::BitReader; #[doc = "Field `rand_rdy_en` writer - RAND Ready Enable"] -pub type RAND_RDY_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RAND_RDY_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `seed_done_en` reader - Seed Done Enable"] pub type SEED_DONE_EN_R = crate::BitReader; #[doc = "Field `seed_done_en` writer - Seed Done Enable"] -pub type SEED_DONE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SEED_DONE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `lfsr_lockup_en` reader - LFSR Lockup Enable"] pub type LFSR_LOCKUP_EN_R = crate::BitReader; #[doc = "Field `lfsr_lockup_en` writer - LFSR Lockup Enable"] -pub type LFSR_LOCKUP_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LFSR_LOCKUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `glbl_en` reader - Global Enable"] pub type GLBL_EN_R = crate::BitReader; #[doc = "Field `glbl_en` writer - Global Enable"] -pub type GLBL_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GLBL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RAND Ready Enable"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - RAND Ready Enable"] #[inline(always)] #[must_use] - pub fn rand_rdy_en(&mut self) -> RAND_RDY_EN_W { - RAND_RDY_EN_W::new(self) + pub fn rand_rdy_en(&mut self) -> RAND_RDY_EN_W { + RAND_RDY_EN_W::new(self, 0) } #[doc = "Bit 1 - Seed Done Enable"] #[inline(always)] #[must_use] - pub fn seed_done_en(&mut self) -> SEED_DONE_EN_W { - SEED_DONE_EN_W::new(self) + pub fn seed_done_en(&mut self) -> SEED_DONE_EN_W { + SEED_DONE_EN_W::new(self, 1) } #[doc = "Bit 4 - LFSR Lockup Enable"] #[inline(always)] #[must_use] - pub fn lfsr_lockup_en(&mut self) -> LFSR_LOCKUP_EN_W { - LFSR_LOCKUP_EN_W::new(self) + pub fn lfsr_lockup_en(&mut self) -> LFSR_LOCKUP_EN_W { + LFSR_LOCKUP_EN_W::new(self, 4) } #[doc = "Bit 31 - Global Enable"] #[inline(always)] #[must_use] - pub fn glbl_en(&mut self) -> GLBL_EN_W { - GLBL_EN_W::new(self) + pub fn glbl_en(&mut self) -> GLBL_EN_W { + GLBL_EN_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/trng/istat.rs b/jh7110-vf2-12a-pac/src/trng/istat.rs index d17bc57..a3c0bc6 100644 --- a/jh7110-vf2-12a-pac/src/trng/istat.rs +++ b/jh7110-vf2-12a-pac/src/trng/istat.rs @@ -26,7 +26,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/trng/mode.rs b/jh7110-vf2-12a-pac/src/trng/mode.rs index 0483fcb..2178579 100644 --- a/jh7110-vf2-12a-pac/src/trng/mode.rs +++ b/jh7110-vf2-12a-pac/src/trng/mode.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `r256` reader - 256-bit operation mode: 0 - 128-bit mode, 1 - 256-bit mode"] pub type R256_R = crate::BitReader; #[doc = "Field `r256` writer - 256-bit operation mode: 0 - 128-bit mode, 1 - 256-bit mode"] -pub type R256_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type R256_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 3 - 256-bit operation mode: 0 - 128-bit mode, 1 - 256-bit mode"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 3 - 256-bit operation mode: 0 - 128-bit mode, 1 - 256-bit mode"] #[inline(always)] #[must_use] - pub fn r256(&mut self) -> R256_W { - R256_W::new(self) + pub fn r256(&mut self) -> R256_W { + R256_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/trng/rand0.rs b/jh7110-vf2-12a-pac/src/trng/rand0.rs index 8d640b8..a99f590 100644 --- a/jh7110-vf2-12a-pac/src/trng/rand0.rs +++ b/jh7110-vf2-12a-pac/src/trng/rand0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/trng/rand1.rs b/jh7110-vf2-12a-pac/src/trng/rand1.rs index 02759fc..8779d7f 100644 --- a/jh7110-vf2-12a-pac/src/trng/rand1.rs +++ b/jh7110-vf2-12a-pac/src/trng/rand1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/trng/rand2.rs b/jh7110-vf2-12a-pac/src/trng/rand2.rs index 9c12892..98e7722 100644 --- a/jh7110-vf2-12a-pac/src/trng/rand2.rs +++ b/jh7110-vf2-12a-pac/src/trng/rand2.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/trng/rand3.rs b/jh7110-vf2-12a-pac/src/trng/rand3.rs index 3cf673c..aa3cd17 100644 --- a/jh7110-vf2-12a-pac/src/trng/rand3.rs +++ b/jh7110-vf2-12a-pac/src/trng/rand3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/trng/rand4.rs b/jh7110-vf2-12a-pac/src/trng/rand4.rs index 053c800..594d125 100644 --- a/jh7110-vf2-12a-pac/src/trng/rand4.rs +++ b/jh7110-vf2-12a-pac/src/trng/rand4.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/trng/rand5.rs b/jh7110-vf2-12a-pac/src/trng/rand5.rs index 2c3614a..2a30aee 100644 --- a/jh7110-vf2-12a-pac/src/trng/rand5.rs +++ b/jh7110-vf2-12a-pac/src/trng/rand5.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/trng/rand6.rs b/jh7110-vf2-12a-pac/src/trng/rand6.rs index 62ff145..a852096 100644 --- a/jh7110-vf2-12a-pac/src/trng/rand6.rs +++ b/jh7110-vf2-12a-pac/src/trng/rand6.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/trng/rand7.rs b/jh7110-vf2-12a-pac/src/trng/rand7.rs index ae12b01..2a3f62d 100644 --- a/jh7110-vf2-12a-pac/src/trng/rand7.rs +++ b/jh7110-vf2-12a-pac/src/trng/rand7.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/trng/smode.rs b/jh7110-vf2-12a-pac/src/trng/smode.rs index 23f0a12..35d99e4 100644 --- a/jh7110-vf2-12a-pac/src/trng/smode.rs +++ b/jh7110-vf2-12a-pac/src/trng/smode.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `nonce_mode` reader - Nonce operation mode"] pub type NONCE_MODE_R = crate::BitReader; #[doc = "Field `nonce_mode` writer - Nonce operation mode"] -pub type NONCE_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type NONCE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mission_mode` reader - Mission operation mode"] pub type MISSION_MODE_R = crate::BitReader; #[doc = "Field `mission_mode` writer - Mission operation mode"] -pub type MISSION_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MISSION_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `max_rejects` reader - TRNG Maximum Rejects"] pub type MAX_REJECTS_R = crate::FieldReader; #[doc = "Field `max_rejects` writer - TRNG Maximum Rejects"] -pub type MAX_REJECTS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type MAX_REJECTS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bit 2 - Nonce operation mode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bit 2 - Nonce operation mode"] #[inline(always)] #[must_use] - pub fn nonce_mode(&mut self) -> NONCE_MODE_W { - NONCE_MODE_W::new(self) + pub fn nonce_mode(&mut self) -> NONCE_MODE_W { + NONCE_MODE_W::new(self, 2) } #[doc = "Bit 8 - Mission operation mode"] #[inline(always)] #[must_use] - pub fn mission_mode(&mut self) -> MISSION_MODE_W { - MISSION_MODE_W::new(self) + pub fn mission_mode(&mut self) -> MISSION_MODE_W { + MISSION_MODE_W::new(self, 8) } #[doc = "Bits 16:31 - TRNG Maximum Rejects"] #[inline(always)] #[must_use] - pub fn max_rejects(&mut self) -> MAX_REJECTS_W { - MAX_REJECTS_W::new(self) + pub fn max_rejects(&mut self) -> MAX_REJECTS_W { + MAX_REJECTS_W::new(self, 16) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/trng/stat.rs b/jh7110-vf2-12a-pac/src/trng/stat.rs index afc22a4..73ae28b 100644 --- a/jh7110-vf2-12a-pac/src/trng/stat.rs +++ b/jh7110-vf2-12a-pac/src/trng/stat.rs @@ -110,7 +110,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0.rs b/jh7110-vf2-12a-pac/src/uart0.rs index c462fbf..8a5f089 100644 --- a/jh7110-vf2-12a-pac/src/uart0.rs +++ b/jh7110-vf2-12a-pac/src/uart0.rs @@ -4,20 +4,13 @@ pub struct RegisterBlock { _reserved_0_dll: [u8; 0x04], _reserved_1_dlh: [u8; 0x04], _reserved_2_fcr: [u8; 0x04], - #[doc = "0x0c - Line Control Register"] - pub lcr: LCR, - #[doc = "0x10 - Modem Control Register"] - pub mcr: MCR, - #[doc = "0x14 - Line Status Register"] - pub lsr: LSR, - #[doc = "0x18 - Line Status Register"] - pub msr: MSR, - #[doc = "0x1c - Scratch Pad Register"] - pub scr: SCR, - #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdll: LPDLL, - #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdlh: LPDLH, + lcr: LCR, + mcr: MCR, + lsr: LSR, + msr: MSR, + scr: SCR, + lpdll: LPDLL, + lpdlh: LPDLH, _reserved10: [u8; 0x08], _reserved_10_srbr0: [u8; 0x04], _reserved_11_srbr1: [u8; 0x04], @@ -35,564 +28,663 @@ pub struct RegisterBlock { _reserved_23_srbr13: [u8; 0x04], _reserved_24_srbr14: [u8; 0x04], _reserved_25_srbr15: [u8; 0x04], - #[doc = "0x70 - FIFO Access Register"] - pub far: FAR, - #[doc = "0x74 - Transmit FIFO Read"] - pub tfr: TFR, - #[doc = "0x78 - Receive FIFO Write"] - pub rfw: RFW, - #[doc = "0x7c - UART Status Register"] - pub usr: USR, - #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub tfl: TFL, - #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub rfl: RFL, - #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srr: SRR, - #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srts: SRTS, - #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sbcr: SBCR, - #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sdmam: SDMAM, - #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sfe: SFE, - #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srt: SRT, - #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub stet: STET, - #[doc = "0xa4 - Halt TX"] - pub htx: HTX, - #[doc = "0xa8 - DMA Software Acknowledge"] - pub dmasa: DMASA, + far: FAR, + tfr: TFR, + rfw: RFW, + usr: USR, + tfl: TFL, + rfl: RFL, + srr: SRR, + srts: SRTS, + sbcr: SBCR, + sdmam: SDMAM, + sfe: SFE, + srt: SRT, + stet: STET, + htx: HTX, + dmasa: DMASA, _reserved41: [u8; 0x48], - #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] - pub cpr: CPR, + cpr: CPR, _reserved_42_ctr: [u8; 0x04], } impl RegisterBlock { #[doc = "0x00 - Divisor Latch Low"] #[inline(always)] pub const fn dll(&self) -> &DLL { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Transmit Holding Register"] #[inline(always)] pub const fn thr(&self) -> &THR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Receive Buffer Register"] #[inline(always)] pub const fn rbr(&self) -> &RBR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x04 - Interrupt Enable Register"] #[inline(always)] pub const fn ier(&self) -> &IER { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x04 - Divisor Latch High"] #[inline(always)] pub const fn dlh(&self) -> &DLH { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x08 - FIFO Control Register"] #[inline(always)] pub const fn fcr(&self) -> &FCR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } } #[doc = "0x08 - Interrupt Identity Register"] #[inline(always)] pub const fn iir(&self) -> &IIR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } + } + #[doc = "0x0c - Line Control Register"] + #[inline(always)] + pub const fn lcr(&self) -> &LCR { + &self.lcr + } + #[doc = "0x10 - Modem Control Register"] + #[inline(always)] + pub const fn mcr(&self) -> &MCR { + &self.mcr + } + #[doc = "0x14 - Line Status Register"] + #[inline(always)] + pub const fn lsr(&self) -> &LSR { + &self.lsr + } + #[doc = "0x18 - Line Status Register"] + #[inline(always)] + pub const fn msr(&self) -> &MSR { + &self.msr + } + #[doc = "0x1c - Scratch Pad Register"] + #[inline(always)] + pub const fn scr(&self) -> &SCR { + &self.scr + } + #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdll(&self) -> &LPDLL { + &self.lpdll + } + #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdlh(&self) -> &LPDLH { + &self.lpdlh } #[doc = "0x30 - Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr0(&self) -> &STHR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x30 - Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr0(&self) -> &SRBR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x34 - Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr1(&self) -> &STHR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x34 - Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr1(&self) -> &SRBR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x38 - Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr2(&self) -> &STHR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x38 - Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr2(&self) -> &SRBR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x3c - Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr3(&self) -> &STHR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x3c - Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr3(&self) -> &SRBR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x40 - Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr4(&self) -> &STHR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x40 - Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr4(&self) -> &SRBR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x44 - Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr5(&self) -> &STHR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x44 - Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr5(&self) -> &SRBR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x48 - Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr6(&self) -> &STHR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x48 - Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr6(&self) -> &SRBR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x4c - Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr7(&self) -> &STHR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x4c - Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr7(&self) -> &SRBR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x50 - Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr8(&self) -> &STHR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x50 - Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr8(&self) -> &SRBR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x54 - Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr9(&self) -> &STHR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x54 - Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr9(&self) -> &SRBR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x58 - Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr10(&self) -> &STHR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x58 - Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr10(&self) -> &SRBR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x5c - Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr11(&self) -> &STHR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x5c - Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr11(&self) -> &SRBR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x60 - Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr12(&self) -> &STHR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x60 - Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr12(&self) -> &SRBR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x64 - Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr13(&self) -> &STHR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x64 - Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr13(&self) -> &SRBR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x68 - Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr14(&self) -> &STHR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x68 - Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr14(&self) -> &SRBR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x6c - Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr15(&self) -> &STHR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } } #[doc = "0x6c - Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr15(&self) -> &SRBR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } + } + #[doc = "0x70 - FIFO Access Register"] + #[inline(always)] + pub const fn far(&self) -> &FAR { + &self.far + } + #[doc = "0x74 - Transmit FIFO Read"] + #[inline(always)] + pub const fn tfr(&self) -> &TFR { + &self.tfr + } + #[doc = "0x78 - Receive FIFO Write"] + #[inline(always)] + pub const fn rfw(&self) -> &RFW { + &self.rfw + } + #[doc = "0x7c - UART Status Register"] + #[inline(always)] + pub const fn usr(&self) -> &USR { + &self.usr + } + #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn tfl(&self) -> &TFL { + &self.tfl + } + #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn rfl(&self) -> &RFL { + &self.rfl + } + #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srr(&self) -> &SRR { + &self.srr + } + #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srts(&self) -> &SRTS { + &self.srts + } + #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sbcr(&self) -> &SBCR { + &self.sbcr + } + #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sdmam(&self) -> &SDMAM { + &self.sdmam + } + #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sfe(&self) -> &SFE { + &self.sfe + } + #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srt(&self) -> &SRT { + &self.srt + } + #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn stet(&self) -> &STET { + &self.stet + } + #[doc = "0xa4 - Halt TX"] + #[inline(always)] + pub const fn htx(&self) -> &HTX { + &self.htx + } + #[doc = "0xa8 - DMA Software Acknowledge"] + #[inline(always)] + pub const fn dmasa(&self) -> &DMASA { + &self.dmasa + } + #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn cpr(&self) -> &CPR { + &self.cpr } #[doc = "0xf8 - Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ctr(&self) -> &CTR { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } #[doc = "0xf8 - UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ucv(&self) -> &UCV { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } } -#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rbr`] +#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbr`] module"] pub type RBR = crate::Reg; #[doc = "Receive Buffer Register"] pub mod rbr; -#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`thr`] +#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thr`] module"] pub type THR = crate::Reg; #[doc = "Transmit Holding Register"] pub mod thr; -#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dll`] +#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll`] module"] pub type DLL = crate::Reg; #[doc = "Divisor Latch Low"] pub mod dll; -#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dlh`] +#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlh`] module"] pub type DLH = crate::Reg; #[doc = "Divisor Latch High"] pub mod dlh; -#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`iir`] +#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] module"] pub type IIR = crate::Reg; #[doc = "Interrupt Identity Register"] pub mod iir; -#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fcr`] +#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"] pub type FCR = crate::Reg; #[doc = "FIFO Control Register"] pub mod fcr; -#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lcr`] +#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] module"] pub type LCR = crate::Reg; #[doc = "Line Control Register"] pub mod lcr; -#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mcr`] +#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] pub type MCR = crate::Reg; #[doc = "Modem Control Register"] pub mod mcr; -#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lsr`] +#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] module"] pub type LSR = crate::Reg; #[doc = "Line Status Register"] pub mod lsr; -#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msr`] +#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"] pub type MSR = crate::Reg; #[doc = "Line Status Register"] pub mod msr; -#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scr`] +#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`] module"] pub type SCR = crate::Reg; #[doc = "Scratch Pad Register"] pub mod scr; -#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdll`] +#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdll`] module"] pub type LPDLL = crate::Reg; #[doc = "Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdll; -#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdlh`] +#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdlh`] module"] pub type LPDLH = crate::Reg; #[doc = "Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdlh; -#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr0`] +#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr0`] module"] pub type SRBR0 = crate::Reg; #[doc = "Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr0; -#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr0`] +#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr0`] module"] pub type STHR0 = crate::Reg; #[doc = "Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr0; -#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr1`] +#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr1`] module"] pub type SRBR1 = crate::Reg; #[doc = "Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr1; -#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr1`] +#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr1`] module"] pub type STHR1 = crate::Reg; #[doc = "Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr1; -#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr2`] +#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr2`] module"] pub type SRBR2 = crate::Reg; #[doc = "Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr2; -#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr2`] +#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr2`] module"] pub type STHR2 = crate::Reg; #[doc = "Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr2; -#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr3`] +#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr3`] module"] pub type SRBR3 = crate::Reg; #[doc = "Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr3; -#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr3`] +#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr3`] module"] pub type STHR3 = crate::Reg; #[doc = "Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr3; -#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr4`] +#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr4`] module"] pub type SRBR4 = crate::Reg; #[doc = "Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr4; -#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr4`] +#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr4`] module"] pub type STHR4 = crate::Reg; #[doc = "Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr4; -#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr5`] +#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr5`] module"] pub type SRBR5 = crate::Reg; #[doc = "Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr5; -#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr5`] +#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr5`] module"] pub type STHR5 = crate::Reg; #[doc = "Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr5; -#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr6`] +#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr6`] module"] pub type SRBR6 = crate::Reg; #[doc = "Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr6; -#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr6`] +#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr6`] module"] pub type STHR6 = crate::Reg; #[doc = "Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr6; -#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr7`] +#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr7`] module"] pub type SRBR7 = crate::Reg; #[doc = "Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr7; -#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr7`] +#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr7`] module"] pub type STHR7 = crate::Reg; #[doc = "Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr7; -#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr8`] +#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr8`] module"] pub type SRBR8 = crate::Reg; #[doc = "Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr8; -#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr8`] +#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr8`] module"] pub type STHR8 = crate::Reg; #[doc = "Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr8; -#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr9`] +#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr9`] module"] pub type SRBR9 = crate::Reg; #[doc = "Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr9; -#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr9`] +#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr9`] module"] pub type STHR9 = crate::Reg; #[doc = "Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr9; -#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr10`] +#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr10`] module"] pub type SRBR10 = crate::Reg; #[doc = "Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr10; -#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr10`] +#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr10`] module"] pub type STHR10 = crate::Reg; #[doc = "Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr10; -#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr11`] +#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr11`] module"] pub type SRBR11 = crate::Reg; #[doc = "Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr11; -#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr11`] +#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr11`] module"] pub type STHR11 = crate::Reg; #[doc = "Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr11; -#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr12`] +#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr12`] module"] pub type SRBR12 = crate::Reg; #[doc = "Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr12; -#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr12`] +#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr12`] module"] pub type STHR12 = crate::Reg; #[doc = "Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr12; -#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr13`] +#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr13`] module"] pub type SRBR13 = crate::Reg; #[doc = "Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr13; -#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr13`] +#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr13`] module"] pub type STHR13 = crate::Reg; #[doc = "Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr13; -#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr14`] +#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr14`] module"] pub type SRBR14 = crate::Reg; #[doc = "Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr14; -#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr14`] +#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr14`] module"] pub type STHR14 = crate::Reg; #[doc = "Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr14; -#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr15`] +#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr15`] module"] pub type SRBR15 = crate::Reg; #[doc = "Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr15; -#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr15`] +#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr15`] module"] pub type STHR15 = crate::Reg; #[doc = "Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr15; -#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`far`] +#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@far`] module"] pub type FAR = crate::Reg; #[doc = "FIFO Access Register"] pub mod far; -#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfr`] +#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfr`] module"] pub type TFR = crate::Reg; #[doc = "Transmit FIFO Read"] pub mod tfr; -#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfw`] +#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfw`] module"] pub type RFW = crate::Reg; #[doc = "Receive FIFO Write"] pub mod rfw; -#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`usr`] +#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usr`] module"] pub type USR = crate::Reg; #[doc = "UART Status Register"] pub mod usr; -#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfl`] +#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfl`] module"] pub type TFL = crate::Reg; #[doc = "Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod tfl; -#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfl`] +#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfl`] module"] pub type RFL = crate::Reg; #[doc = "Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod rfl; -#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srr`] +#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srr`] module"] pub type SRR = crate::Reg; #[doc = "Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srr; -#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srts`] +#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srts`] module"] pub type SRTS = crate::Reg; #[doc = "Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srts; -#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sbcr`] +#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sbcr`] module"] pub type SBCR = crate::Reg; #[doc = "Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sbcr; -#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sdmam`] +#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdmam`] module"] pub type SDMAM = crate::Reg; #[doc = "Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sdmam; -#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sfe`] +#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfe`] module"] pub type SFE = crate::Reg; #[doc = "Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sfe; -#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srt`] +#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srt`] module"] pub type SRT = crate::Reg; #[doc = "Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srt; -#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stet`] +#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stet`] module"] pub type STET = crate::Reg; #[doc = "Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod stet; -#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`htx`] +#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@htx`] module"] pub type HTX = crate::Reg; #[doc = "Halt TX"] pub mod htx; -#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dmasa`] +#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasa`] module"] pub type DMASA = crate::Reg; #[doc = "DMA Software Acknowledge"] pub mod dmasa; -#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cpr`] +#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpr`] module"] pub type CPR = crate::Reg; #[doc = "Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] pub mod cpr; -#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ucv`] +#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucv`] module"] pub type UCV = crate::Reg; #[doc = "UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] pub mod ucv; -#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctr`] +#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"] pub type CTR = crate::Reg; #[doc = "Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] diff --git a/jh7110-vf2-12a-pac/src/uart0/cpr.rs b/jh7110-vf2-12a-pac/src/uart0/cpr.rs index 4807519..332b584 100644 --- a/jh7110-vf2-12a-pac/src/uart0/cpr.rs +++ b/jh7110-vf2-12a-pac/src/uart0/cpr.rs @@ -89,7 +89,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/ctr.rs b/jh7110-vf2-12a-pac/src/uart0/ctr.rs index c3760d5..ac70194 100644 --- a/jh7110-vf2-12a-pac/src/uart0/ctr.rs +++ b/jh7110-vf2-12a-pac/src/uart0/ctr.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/dlh.rs b/jh7110-vf2-12a-pac/src/uart0/dlh.rs index 3257a2d..2a788c1 100644 --- a/jh7110-vf2-12a-pac/src/uart0/dlh.rs +++ b/jh7110-vf2-12a-pac/src/uart0/dlh.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLH_R = crate::FieldReader; #[doc = "Field `dlh` writer - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dlh(&mut self) -> DLH_W { - DLH_W::new(self) + pub fn dlh(&mut self) -> DLH_W { + DLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/dll.rs b/jh7110-vf2-12a-pac/src/uart0/dll.rs index 9c9daff..1c9d765 100644 --- a/jh7110-vf2-12a-pac/src/uart0/dll.rs +++ b/jh7110-vf2-12a-pac/src/uart0/dll.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLL_R = crate::FieldReader; #[doc = "Field `dll` writer - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dll(&mut self) -> DLL_W { - DLL_W::new(self) + pub fn dll(&mut self) -> DLL_W { + DLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/dmasa.rs b/jh7110-vf2-12a-pac/src/uart0/dmasa.rs index 7bcfb26..2fc4e6d 100644 --- a/jh7110-vf2-12a-pac/src/uart0/dmasa.rs +++ b/jh7110-vf2-12a-pac/src/uart0/dmasa.rs @@ -3,15 +3,19 @@ pub type R = crate::R; #[doc = "Register `dmasa` writer"] pub type W = crate::W; #[doc = "Field `dmasa` writer - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type DMASA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMASA_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn dmasa(&mut self) -> DMASA_W { - DMASA_W::new(self) + pub fn dmasa(&mut self) -> DMASA_W { + DMASA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/far.rs b/jh7110-vf2-12a-pac/src/uart0/far.rs index 3b3bcb1..d52059a 100644 --- a/jh7110-vf2-12a-pac/src/uart0/far.rs +++ b/jh7110-vf2-12a-pac/src/uart0/far.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `far` reader - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] pub type FAR_R = crate::BitReader; #[doc = "Field `far` writer - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] -pub type FAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FAR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] #[must_use] - pub fn far(&mut self) -> FAR_W { - FAR_W::new(self) + pub fn far(&mut self) -> FAR_W { + FAR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/fcr.rs b/jh7110-vf2-12a-pac/src/uart0/fcr.rs index 4fbb499..a64a60b 100644 --- a/jh7110-vf2-12a-pac/src/uart0/fcr.rs +++ b/jh7110-vf2-12a-pac/src/uart0/fcr.rs @@ -3,55 +3,59 @@ pub type R = crate::R; #[doc = "Register `fcr` writer"] pub type W = crate::W; #[doc = "Field `fifoe` writer - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] -pub type FIFOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIFOE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfifor` writer - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfifor` writer - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dmam` writer - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] -pub type DMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMAM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tet` writer - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type TET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `rt` writer - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type RT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type RT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl W { #[doc = "Bit 0 - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] #[inline(always)] #[must_use] - pub fn fifoe(&mut self) -> FIFOE_W { - FIFOE_W::new(self) + pub fn fifoe(&mut self) -> FIFOE_W { + FIFOE_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfifor(&mut self) -> RFIFOR_W { - RFIFOR_W::new(self) + pub fn rfifor(&mut self) -> RFIFOR_W { + RFIFOR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfifor(&mut self) -> XFIFOR_W { - XFIFOR_W::new(self) + pub fn xfifor(&mut self) -> XFIFOR_W { + XFIFOR_W::new(self, 2) } #[doc = "Bit 3 - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn dmam(&mut self) -> DMAM_W { - DMAM_W::new(self) + pub fn dmam(&mut self) -> DMAM_W { + DMAM_W::new(self, 3) } #[doc = "Bits 4:5 - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn tet(&mut self) -> TET_W { - TET_W::new(self) + pub fn tet(&mut self) -> TET_W { + TET_W::new(self, 4) } #[doc = "Bits 6:7 - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn rt(&mut self) -> RT_W { - RT_W::new(self) + pub fn rt(&mut self) -> RT_W { + RT_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/htx.rs b/jh7110-vf2-12a-pac/src/uart0/htx.rs index ad027bd..fc82325 100644 --- a/jh7110-vf2-12a-pac/src/uart0/htx.rs +++ b/jh7110-vf2-12a-pac/src/uart0/htx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `htx` reader - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] pub type HTX_R = crate::BitReader; #[doc = "Field `htx` writer - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] -pub type HTX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HTX_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] #[must_use] - pub fn htx(&mut self) -> HTX_W { - HTX_W::new(self) + pub fn htx(&mut self) -> HTX_W { + HTX_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/ier.rs b/jh7110-vf2-12a-pac/src/uart0/ier.rs index 006fbea..3cf3d7f 100644 --- a/jh7110-vf2-12a-pac/src/uart0/ier.rs +++ b/jh7110-vf2-12a-pac/src/uart0/ier.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `erbfi` reader - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] pub type ERBFI_R = crate::BitReader; #[doc = "Field `erbfi` writer - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] -pub type ERBFI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ERBFI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `etbei` reader - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] pub type ETBEI_R = crate::BitReader; #[doc = "Field `etbei` writer - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ETBEI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ETBEI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `elsi` reader - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] pub type ELSI_R = crate::BitReader; #[doc = "Field `elsi` writer - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ELSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ELSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `edssi` reader - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] pub type EDSSI_R = crate::BitReader; #[doc = "Field `edssi` writer - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] -pub type EDSSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EDSSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ptime` reader - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] pub type PTIME_R = crate::BitReader; #[doc = "Field `ptime` writer - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] -pub type PTIME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PTIME_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn erbfi(&mut self) -> ERBFI_W { - ERBFI_W::new(self) + pub fn erbfi(&mut self) -> ERBFI_W { + ERBFI_W::new(self, 0) } #[doc = "Bit 1 - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn etbei(&mut self) -> ETBEI_W { - ETBEI_W::new(self) + pub fn etbei(&mut self) -> ETBEI_W { + ETBEI_W::new(self, 1) } #[doc = "Bit 2 - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn elsi(&mut self) -> ELSI_W { - ELSI_W::new(self) + pub fn elsi(&mut self) -> ELSI_W { + ELSI_W::new(self, 2) } #[doc = "Bit 3 - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn edssi(&mut self) -> EDSSI_W { - EDSSI_W::new(self) + pub fn edssi(&mut self) -> EDSSI_W { + EDSSI_W::new(self, 3) } #[doc = "Bit 7 - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn ptime(&mut self) -> PTIME_W { - PTIME_W::new(self) + pub fn ptime(&mut self) -> PTIME_W { + PTIME_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/iir.rs b/jh7110-vf2-12a-pac/src/uart0/iir.rs index c90daa5..c949f03 100644 --- a/jh7110-vf2-12a-pac/src/uart0/iir.rs +++ b/jh7110-vf2-12a-pac/src/uart0/iir.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/lcr.rs b/jh7110-vf2-12a-pac/src/uart0/lcr.rs index acd83ee..3bc10c2 100644 --- a/jh7110-vf2-12a-pac/src/uart0/lcr.rs +++ b/jh7110-vf2-12a-pac/src/uart0/lcr.rs @@ -7,7 +7,7 @@ is zero), always readable. This is used to select the number of data bits per ch pub type DLS_R = crate::FieldReader; #[doc = "Field `dls` writer - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] -pub type DLS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DLS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `stop` reader - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] @@ -15,31 +15,31 @@ pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pen` reader - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] pub type PEN_R = crate::BitReader; #[doc = "Field `pen` writer - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] -pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `eps` reader - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] pub type EPS_R = crate::BitReader; #[doc = "Field `eps` writer - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] -pub type EPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EPS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bc` reader - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] pub type BC_R = crate::BitReader; #[doc = "Field `bc` writer - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] -pub type BC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dlab` reader - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] pub type DLAB_R = crate::BitReader; #[doc = "Field `dlab` writer - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] -pub type DLAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DLAB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:1 - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] @@ -84,46 +84,50 @@ impl W { is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] #[inline(always)] #[must_use] - pub fn dls(&mut self) -> DLS_W { - DLS_W::new(self) + pub fn dls(&mut self) -> DLS_W { + DLS_W::new(self, 0) } #[doc = "Bit 2 - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 2) } #[doc = "Bit 3 - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W { - PEN_W::new(self) + pub fn pen(&mut self) -> PEN_W { + PEN_W::new(self, 3) } #[doc = "Bit 4 - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] #[inline(always)] #[must_use] - pub fn eps(&mut self) -> EPS_W { - EPS_W::new(self) + pub fn eps(&mut self) -> EPS_W { + EPS_W::new(self, 4) } #[doc = "Bit 6 - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] #[inline(always)] #[must_use] - pub fn bc(&mut self) -> BC_W { - BC_W::new(self) + pub fn bc(&mut self) -> BC_W { + BC_W::new(self, 6) } #[doc = "Bit 7 - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] #[inline(always)] #[must_use] - pub fn dlab(&mut self) -> DLAB_W { - DLAB_W::new(self) + pub fn dlab(&mut self) -> DLAB_W { + DLAB_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/lpdlh.rs b/jh7110-vf2-12a-pac/src/uart0/lpdlh.rs index 8a910c8..095afa9 100644 --- a/jh7110-vf2-12a-pac/src/uart0/lpdlh.rs +++ b/jh7110-vf2-12a-pac/src/uart0/lpdlh.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdlh` reader - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] pub type LPDLH_R = crate::FieldReader; #[doc = "Field `lpdlh` writer - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] -pub type LPDLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] #[must_use] - pub fn lpdlh(&mut self) -> LPDLH_W { - LPDLH_W::new(self) + pub fn lpdlh(&mut self) -> LPDLH_W { + LPDLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/lpdll.rs b/jh7110-vf2-12a-pac/src/uart0/lpdll.rs index 7780651..21d0018 100644 --- a/jh7110-vf2-12a-pac/src/uart0/lpdll.rs +++ b/jh7110-vf2-12a-pac/src/uart0/lpdll.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdll` reader - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] pub type LPDLL_R = crate::FieldReader; #[doc = "Field `lpdll` writer - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type LPDLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn lpdll(&mut self) -> LPDLL_W { - LPDLL_W::new(self) + pub fn lpdll(&mut self) -> LPDLL_W { + LPDLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/lsr.rs b/jh7110-vf2-12a-pac/src/uart0/lsr.rs index f576c10..ff2ab48 100644 --- a/jh7110-vf2-12a-pac/src/uart0/lsr.rs +++ b/jh7110-vf2-12a-pac/src/uart0/lsr.rs @@ -73,7 +73,11 @@ set to one). This is used to indicate if there is at least one parity error, fra } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/mcr.rs b/jh7110-vf2-12a-pac/src/uart0/mcr.rs index 6932ee7..9c93108 100644 --- a/jh7110-vf2-12a-pac/src/uart0/mcr.rs +++ b/jh7110-vf2-12a-pac/src/uart0/mcr.rs @@ -7,7 +7,7 @@ set to one), the dtr_n output is held inactive high while the value of this loca pub type DTR_R = crate::BitReader; #[doc = "Field `dtr` writer - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type DTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rts` reader - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR\\[5\\] @@ -23,19 +23,19 @@ set to one) and FIFOs enable (FCR\\[0\\] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR\\[1\\] is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out1` reader - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT1_R = crate::BitReader; #[doc = "Field `out1` writer - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out2` reader - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT2_R = crate::BitReader; #[doc = "Field `out2` writer - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `lb` reader - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] @@ -43,15 +43,15 @@ pub type LB_R = crate::BitReader; #[doc = "Field `lb` writer - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] -pub type LB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `afce` reader - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] pub type AFCE_R = crate::BitReader; #[doc = "Field `afce` writer - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] -pub type AFCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AFCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sire` reader - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] pub type SIRE_R = crate::BitReader; #[doc = "Field `sire` writer - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] -pub type SIRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SIRE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] @@ -105,8 +105,8 @@ impl W { set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn dtr(&mut self) -> DTR_W { - DTR_W::new(self) + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 0) } #[doc = "Bit 1 - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] @@ -117,44 +117,48 @@ is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W { - RTS_W::new(self) + pub fn rts(&mut self) -> RTS_W { + RTS_W::new(self, 1) } #[doc = "Bit 2 - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out1(&mut self) -> OUT1_W { - OUT1_W::new(self) + pub fn out1(&mut self) -> OUT1_W { + OUT1_W::new(self, 2) } #[doc = "Bit 3 - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out2(&mut self) -> OUT2_W { - OUT2_W::new(self) + pub fn out2(&mut self) -> OUT2_W { + OUT2_W::new(self, 3) } #[doc = "Bit 4 - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] #[inline(always)] #[must_use] - pub fn lb(&mut self) -> LB_W { - LB_W::new(self) + pub fn lb(&mut self) -> LB_W { + LB_W::new(self, 4) } #[doc = "Bit 5 - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] #[inline(always)] #[must_use] - pub fn afce(&mut self) -> AFCE_W { - AFCE_W::new(self) + pub fn afce(&mut self) -> AFCE_W { + AFCE_W::new(self, 5) } #[doc = "Bit 6 - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] #[inline(always)] #[must_use] - pub fn sire(&mut self) -> SIRE_W { - SIRE_W::new(self) + pub fn sire(&mut self) -> SIRE_W { + SIRE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/msr.rs b/jh7110-vf2-12a-pac/src/uart0/msr.rs index 65c526b..b54fc38 100644 --- a/jh7110-vf2-12a-pac/src/uart0/msr.rs +++ b/jh7110-vf2-12a-pac/src/uart0/msr.rs @@ -93,7 +93,11 @@ set to one), DCD is the same as MCR\\[3\\] } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/rbr.rs b/jh7110-vf2-12a-pac/src/uart0/rbr.rs index 03003ed..403adcf 100644 --- a/jh7110-vf2-12a-pac/src/uart0/rbr.rs +++ b/jh7110-vf2-12a-pac/src/uart0/rbr.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/rfl.rs b/jh7110-vf2-12a-pac/src/uart0/rfl.rs index 2aea928..59355cb 100644 --- a/jh7110-vf2-12a-pac/src/uart0/rfl.rs +++ b/jh7110-vf2-12a-pac/src/uart0/rfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/rfw.rs b/jh7110-vf2-12a-pac/src/uart0/rfw.rs index 7b917de..490472d 100644 --- a/jh7110-vf2-12a-pac/src/uart0/rfw.rs +++ b/jh7110-vf2-12a-pac/src/uart0/rfw.rs @@ -4,36 +4,40 @@ pub type R = crate::R; pub type W = crate::W; #[doc = "Field `rfwd` writer - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] -pub type RFWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type RFWD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `rfpe` writer - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] -pub type RFPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFPE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rffe` writer - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] -pub type RFFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bits 0:7 - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] #[inline(always)] #[must_use] - pub fn rfwd(&mut self) -> RFWD_W { - RFWD_W::new(self) + pub fn rfwd(&mut self) -> RFWD_W { + RFWD_W::new(self, 0) } #[doc = "Bit 8 - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rfpe(&mut self) -> RFPE_W { - RFPE_W::new(self) + pub fn rfpe(&mut self) -> RFPE_W { + RFPE_W::new(self, 8) } #[doc = "Bit 9 - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rffe(&mut self) -> RFFE_W { - RFFE_W::new(self) + pub fn rffe(&mut self) -> RFFE_W { + RFFE_W::new(self, 9) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sbcr.rs b/jh7110-vf2-12a-pac/src/uart0/sbcr.rs index 73914e9..5a120c0 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sbcr.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sbcr.rs @@ -7,7 +7,7 @@ pub type W = crate::W; pub type SBCR_R = crate::BitReader; #[doc = "Field `sbcr` writer - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] -pub type SBCR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SBCR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] @@ -21,10 +21,14 @@ impl W { = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] #[inline(always)] #[must_use] - pub fn sbcr(&mut self) -> SBCR_W { - SBCR_W::new(self) + pub fn sbcr(&mut self) -> SBCR_W { + SBCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/scr.rs b/jh7110-vf2-12a-pac/src/uart0/scr.rs index 744352e..f46ba21 100644 --- a/jh7110-vf2-12a-pac/src/uart0/scr.rs +++ b/jh7110-vf2-12a-pac/src/uart0/scr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `scr` reader - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sdmam.rs b/jh7110-vf2-12a-pac/src/uart0/sdmam.rs index 684377c..4be4fa2 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sdmam.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sdmam.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sdmam` reader - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] pub type SDMAM_R = crate::BitReader; #[doc = "Field `sdmam` writer - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] -pub type SDMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SDMAM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn sdmam(&mut self) -> SDMAM_W { - SDMAM_W::new(self) + pub fn sdmam(&mut self) -> SDMAM_W { + SDMAM_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sfe.rs b/jh7110-vf2-12a-pac/src/uart0/sfe.rs index e68b088..ed26fee 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sfe.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sfe.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sfe` reader - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] pub type SFE_R = crate::BitReader; #[doc = "Field `sfe` writer - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] -pub type SFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] #[must_use] - pub fn sfe(&mut self) -> SFE_W { - SFE_W::new(self) + pub fn sfe(&mut self) -> SFE_W { + SFE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srbr0.rs b/jh7110-vf2-12a-pac/src/uart0/srbr0.rs index 4076661..4e44d1a 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srbr0.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srbr0.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srbr1.rs b/jh7110-vf2-12a-pac/src/uart0/srbr1.rs index 2f31b75..46bc479 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srbr1.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srbr1.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srbr10.rs b/jh7110-vf2-12a-pac/src/uart0/srbr10.rs index 3639d65..70297bf 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srbr10.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srbr10.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srbr11.rs b/jh7110-vf2-12a-pac/src/uart0/srbr11.rs index 92d29b1..28d0277 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srbr11.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srbr11.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srbr12.rs b/jh7110-vf2-12a-pac/src/uart0/srbr12.rs index 52e795e..3eccd9a 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srbr12.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srbr12.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srbr13.rs b/jh7110-vf2-12a-pac/src/uart0/srbr13.rs index 50aae40..e47e4e4 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srbr13.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srbr13.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srbr14.rs b/jh7110-vf2-12a-pac/src/uart0/srbr14.rs index cb25819..8f23662 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srbr14.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srbr14.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srbr15.rs b/jh7110-vf2-12a-pac/src/uart0/srbr15.rs index b25ae46..1dac092 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srbr15.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srbr15.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srbr2.rs b/jh7110-vf2-12a-pac/src/uart0/srbr2.rs index 9f3236c..afb0617 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srbr2.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srbr2.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srbr3.rs b/jh7110-vf2-12a-pac/src/uart0/srbr3.rs index 5c1edda..0ff3650 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srbr3.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srbr3.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srbr4.rs b/jh7110-vf2-12a-pac/src/uart0/srbr4.rs index e6bee93..59560c4 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srbr4.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srbr4.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srbr5.rs b/jh7110-vf2-12a-pac/src/uart0/srbr5.rs index e599009..763e341 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srbr5.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srbr5.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srbr6.rs b/jh7110-vf2-12a-pac/src/uart0/srbr6.rs index b0155b3..78e2a40 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srbr6.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srbr6.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srbr7.rs b/jh7110-vf2-12a-pac/src/uart0/srbr7.rs index b8f9b88..0723ff0 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srbr7.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srbr7.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srbr8.rs b/jh7110-vf2-12a-pac/src/uart0/srbr8.rs index f57b044..4702cd9 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srbr8.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srbr8.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srbr9.rs b/jh7110-vf2-12a-pac/src/uart0/srbr9.rs index 3a160aa..e1a262e 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srbr9.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srbr9.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srr.rs b/jh7110-vf2-12a-pac/src/uart0/srr.rs index 6671199..fdb0c0a 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srr.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srr.rs @@ -3,31 +3,35 @@ pub type R = crate::R; #[doc = "Register `srr` writer"] pub type W = crate::W; #[doc = "Field `ur` writer - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] -pub type UR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type UR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfr` writer - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfr` writer - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFR_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] #[inline(always)] #[must_use] - pub fn ur(&mut self) -> UR_W { - UR_W::new(self) + pub fn ur(&mut self) -> UR_W { + UR_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfr(&mut self) -> RFR_W { - RFR_W::new(self) + pub fn rfr(&mut self) -> RFR_W { + RFR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfr(&mut self) -> XFR_W { - XFR_W::new(self) + pub fn xfr(&mut self) -> XFR_W { + XFR_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srt.rs b/jh7110-vf2-12a-pac/src/uart0/srt.rs index fed4f1f..da909fd 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srt.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `srt` reader - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] pub type SRT_R = crate::FieldReader; #[doc = "Field `srt` writer - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type SRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SRT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn srt(&mut self) -> SRT_W { - SRT_W::new(self) + pub fn srt(&mut self) -> SRT_W { + SRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/srts.rs b/jh7110-vf2-12a-pac/src/uart0/srts.rs index ceb0ee4..cf1e2a9 100644 --- a/jh7110-vf2-12a-pac/src/uart0/srts.rs +++ b/jh7110-vf2-12a-pac/src/uart0/srts.rs @@ -15,7 +15,7 @@ pub type SRTS_R = crate::BitReader; = 1) and FIFOs enable (FCR\\[0\\] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR\\[4\\] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] -pub type SRTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SRTS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Request to Send. This is a shadow register for the RTS bit (MCR\\[1\\]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] = 0), the rts_n signal is set low by programming MCR\\[1\\] @@ -37,10 +37,14 @@ impl W { = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn srts(&mut self) -> SRTS_W { - SRTS_W::new(self) + pub fn srts(&mut self) -> SRTS_W { + SRTS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/stet.rs b/jh7110-vf2-12a-pac/src/uart0/stet.rs index acb8ba1..503dc8a 100644 --- a/jh7110-vf2-12a-pac/src/uart0/stet.rs +++ b/jh7110-vf2-12a-pac/src/uart0/stet.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `stet` reader - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] pub type STET_R = crate::FieldReader; #[doc = "Field `stet` writer - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type STET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type STET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn stet(&mut self) -> STET_W { - STET_W::new(self) + pub fn stet(&mut self) -> STET_W { + STET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sthr0.rs b/jh7110-vf2-12a-pac/src/uart0/sthr0.rs index bfd277a..764ff05 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sthr0.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sthr0.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sthr1.rs b/jh7110-vf2-12a-pac/src/uart0/sthr1.rs index cc79733..5d58855 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sthr1.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sthr1.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sthr10.rs b/jh7110-vf2-12a-pac/src/uart0/sthr10.rs index be2659d..ffc38ff 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sthr10.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sthr10.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sthr11.rs b/jh7110-vf2-12a-pac/src/uart0/sthr11.rs index 8613dd5..1f8147f 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sthr11.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sthr11.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sthr12.rs b/jh7110-vf2-12a-pac/src/uart0/sthr12.rs index b354b10..7d816f3 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sthr12.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sthr12.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sthr13.rs b/jh7110-vf2-12a-pac/src/uart0/sthr13.rs index 06df4bc..9283b6a 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sthr13.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sthr13.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sthr14.rs b/jh7110-vf2-12a-pac/src/uart0/sthr14.rs index e181dd0..2daf622 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sthr14.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sthr14.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sthr15.rs b/jh7110-vf2-12a-pac/src/uart0/sthr15.rs index 4825778..f70715e 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sthr15.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sthr15.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sthr2.rs b/jh7110-vf2-12a-pac/src/uart0/sthr2.rs index d390f10..f1a9c77 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sthr2.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sthr2.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sthr3.rs b/jh7110-vf2-12a-pac/src/uart0/sthr3.rs index a74fdf0..06aab9e 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sthr3.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sthr3.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sthr4.rs b/jh7110-vf2-12a-pac/src/uart0/sthr4.rs index 1ee6b87..f6e7944 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sthr4.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sthr4.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sthr5.rs b/jh7110-vf2-12a-pac/src/uart0/sthr5.rs index ca360fe..7873a53 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sthr5.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sthr5.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sthr6.rs b/jh7110-vf2-12a-pac/src/uart0/sthr6.rs index 18e6fac..87c81df 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sthr6.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sthr6.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sthr7.rs b/jh7110-vf2-12a-pac/src/uart0/sthr7.rs index 27072a3..9928b3d 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sthr7.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sthr7.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sthr8.rs b/jh7110-vf2-12a-pac/src/uart0/sthr8.rs index 15060b8..565cb1d 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sthr8.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sthr8.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/sthr9.rs b/jh7110-vf2-12a-pac/src/uart0/sthr9.rs index 58af642..e64fece 100644 --- a/jh7110-vf2-12a-pac/src/uart0/sthr9.rs +++ b/jh7110-vf2-12a-pac/src/uart0/sthr9.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/tfl.rs b/jh7110-vf2-12a-pac/src/uart0/tfl.rs index e1faba6..db09fe3 100644 --- a/jh7110-vf2-12a-pac/src/uart0/tfl.rs +++ b/jh7110-vf2-12a-pac/src/uart0/tfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/tfr.rs b/jh7110-vf2-12a-pac/src/uart0/tfr.rs index 8e9ad91..714deff 100644 --- a/jh7110-vf2-12a-pac/src/uart0/tfr.rs +++ b/jh7110-vf2-12a-pac/src/uart0/tfr.rs @@ -14,7 +14,11 @@ is set to one). When FIFOs are implemented and enabled, reading this register gi } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/thr.rs b/jh7110-vf2-12a-pac/src/uart0/thr.rs index f910bd8..7845232 100644 --- a/jh7110-vf2-12a-pac/src/uart0/thr.rs +++ b/jh7110-vf2-12a-pac/src/uart0/thr.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `thr` writer - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type THR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type THR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn thr(&mut self) -> THR_W { - THR_W::new(self) + pub fn thr(&mut self) -> THR_W { + THR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/ucv.rs b/jh7110-vf2-12a-pac/src/uart0/ucv.rs index 8a3be91..6497a08 100644 --- a/jh7110-vf2-12a-pac/src/uart0/ucv.rs +++ b/jh7110-vf2-12a-pac/src/uart0/ucv.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart0/usr.rs b/jh7110-vf2-12a-pac/src/uart0/usr.rs index 445a085..b96417d 100644 --- a/jh7110-vf2-12a-pac/src/uart0/usr.rs +++ b/jh7110-vf2-12a-pac/src/uart0/usr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1.rs b/jh7110-vf2-12a-pac/src/uart1.rs index c462fbf..8a5f089 100644 --- a/jh7110-vf2-12a-pac/src/uart1.rs +++ b/jh7110-vf2-12a-pac/src/uart1.rs @@ -4,20 +4,13 @@ pub struct RegisterBlock { _reserved_0_dll: [u8; 0x04], _reserved_1_dlh: [u8; 0x04], _reserved_2_fcr: [u8; 0x04], - #[doc = "0x0c - Line Control Register"] - pub lcr: LCR, - #[doc = "0x10 - Modem Control Register"] - pub mcr: MCR, - #[doc = "0x14 - Line Status Register"] - pub lsr: LSR, - #[doc = "0x18 - Line Status Register"] - pub msr: MSR, - #[doc = "0x1c - Scratch Pad Register"] - pub scr: SCR, - #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdll: LPDLL, - #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdlh: LPDLH, + lcr: LCR, + mcr: MCR, + lsr: LSR, + msr: MSR, + scr: SCR, + lpdll: LPDLL, + lpdlh: LPDLH, _reserved10: [u8; 0x08], _reserved_10_srbr0: [u8; 0x04], _reserved_11_srbr1: [u8; 0x04], @@ -35,564 +28,663 @@ pub struct RegisterBlock { _reserved_23_srbr13: [u8; 0x04], _reserved_24_srbr14: [u8; 0x04], _reserved_25_srbr15: [u8; 0x04], - #[doc = "0x70 - FIFO Access Register"] - pub far: FAR, - #[doc = "0x74 - Transmit FIFO Read"] - pub tfr: TFR, - #[doc = "0x78 - Receive FIFO Write"] - pub rfw: RFW, - #[doc = "0x7c - UART Status Register"] - pub usr: USR, - #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub tfl: TFL, - #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub rfl: RFL, - #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srr: SRR, - #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srts: SRTS, - #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sbcr: SBCR, - #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sdmam: SDMAM, - #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sfe: SFE, - #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srt: SRT, - #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub stet: STET, - #[doc = "0xa4 - Halt TX"] - pub htx: HTX, - #[doc = "0xa8 - DMA Software Acknowledge"] - pub dmasa: DMASA, + far: FAR, + tfr: TFR, + rfw: RFW, + usr: USR, + tfl: TFL, + rfl: RFL, + srr: SRR, + srts: SRTS, + sbcr: SBCR, + sdmam: SDMAM, + sfe: SFE, + srt: SRT, + stet: STET, + htx: HTX, + dmasa: DMASA, _reserved41: [u8; 0x48], - #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] - pub cpr: CPR, + cpr: CPR, _reserved_42_ctr: [u8; 0x04], } impl RegisterBlock { #[doc = "0x00 - Divisor Latch Low"] #[inline(always)] pub const fn dll(&self) -> &DLL { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Transmit Holding Register"] #[inline(always)] pub const fn thr(&self) -> &THR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Receive Buffer Register"] #[inline(always)] pub const fn rbr(&self) -> &RBR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x04 - Interrupt Enable Register"] #[inline(always)] pub const fn ier(&self) -> &IER { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x04 - Divisor Latch High"] #[inline(always)] pub const fn dlh(&self) -> &DLH { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x08 - FIFO Control Register"] #[inline(always)] pub const fn fcr(&self) -> &FCR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } } #[doc = "0x08 - Interrupt Identity Register"] #[inline(always)] pub const fn iir(&self) -> &IIR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } + } + #[doc = "0x0c - Line Control Register"] + #[inline(always)] + pub const fn lcr(&self) -> &LCR { + &self.lcr + } + #[doc = "0x10 - Modem Control Register"] + #[inline(always)] + pub const fn mcr(&self) -> &MCR { + &self.mcr + } + #[doc = "0x14 - Line Status Register"] + #[inline(always)] + pub const fn lsr(&self) -> &LSR { + &self.lsr + } + #[doc = "0x18 - Line Status Register"] + #[inline(always)] + pub const fn msr(&self) -> &MSR { + &self.msr + } + #[doc = "0x1c - Scratch Pad Register"] + #[inline(always)] + pub const fn scr(&self) -> &SCR { + &self.scr + } + #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdll(&self) -> &LPDLL { + &self.lpdll + } + #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdlh(&self) -> &LPDLH { + &self.lpdlh } #[doc = "0x30 - Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr0(&self) -> &STHR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x30 - Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr0(&self) -> &SRBR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x34 - Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr1(&self) -> &STHR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x34 - Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr1(&self) -> &SRBR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x38 - Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr2(&self) -> &STHR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x38 - Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr2(&self) -> &SRBR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x3c - Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr3(&self) -> &STHR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x3c - Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr3(&self) -> &SRBR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x40 - Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr4(&self) -> &STHR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x40 - Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr4(&self) -> &SRBR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x44 - Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr5(&self) -> &STHR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x44 - Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr5(&self) -> &SRBR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x48 - Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr6(&self) -> &STHR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x48 - Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr6(&self) -> &SRBR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x4c - Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr7(&self) -> &STHR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x4c - Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr7(&self) -> &SRBR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x50 - Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr8(&self) -> &STHR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x50 - Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr8(&self) -> &SRBR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x54 - Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr9(&self) -> &STHR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x54 - Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr9(&self) -> &SRBR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x58 - Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr10(&self) -> &STHR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x58 - Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr10(&self) -> &SRBR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x5c - Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr11(&self) -> &STHR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x5c - Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr11(&self) -> &SRBR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x60 - Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr12(&self) -> &STHR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x60 - Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr12(&self) -> &SRBR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x64 - Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr13(&self) -> &STHR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x64 - Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr13(&self) -> &SRBR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x68 - Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr14(&self) -> &STHR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x68 - Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr14(&self) -> &SRBR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x6c - Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr15(&self) -> &STHR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } } #[doc = "0x6c - Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr15(&self) -> &SRBR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } + } + #[doc = "0x70 - FIFO Access Register"] + #[inline(always)] + pub const fn far(&self) -> &FAR { + &self.far + } + #[doc = "0x74 - Transmit FIFO Read"] + #[inline(always)] + pub const fn tfr(&self) -> &TFR { + &self.tfr + } + #[doc = "0x78 - Receive FIFO Write"] + #[inline(always)] + pub const fn rfw(&self) -> &RFW { + &self.rfw + } + #[doc = "0x7c - UART Status Register"] + #[inline(always)] + pub const fn usr(&self) -> &USR { + &self.usr + } + #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn tfl(&self) -> &TFL { + &self.tfl + } + #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn rfl(&self) -> &RFL { + &self.rfl + } + #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srr(&self) -> &SRR { + &self.srr + } + #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srts(&self) -> &SRTS { + &self.srts + } + #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sbcr(&self) -> &SBCR { + &self.sbcr + } + #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sdmam(&self) -> &SDMAM { + &self.sdmam + } + #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sfe(&self) -> &SFE { + &self.sfe + } + #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srt(&self) -> &SRT { + &self.srt + } + #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn stet(&self) -> &STET { + &self.stet + } + #[doc = "0xa4 - Halt TX"] + #[inline(always)] + pub const fn htx(&self) -> &HTX { + &self.htx + } + #[doc = "0xa8 - DMA Software Acknowledge"] + #[inline(always)] + pub const fn dmasa(&self) -> &DMASA { + &self.dmasa + } + #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn cpr(&self) -> &CPR { + &self.cpr } #[doc = "0xf8 - Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ctr(&self) -> &CTR { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } #[doc = "0xf8 - UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ucv(&self) -> &UCV { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } } -#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rbr`] +#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbr`] module"] pub type RBR = crate::Reg; #[doc = "Receive Buffer Register"] pub mod rbr; -#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`thr`] +#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thr`] module"] pub type THR = crate::Reg; #[doc = "Transmit Holding Register"] pub mod thr; -#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dll`] +#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll`] module"] pub type DLL = crate::Reg; #[doc = "Divisor Latch Low"] pub mod dll; -#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dlh`] +#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlh`] module"] pub type DLH = crate::Reg; #[doc = "Divisor Latch High"] pub mod dlh; -#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`iir`] +#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] module"] pub type IIR = crate::Reg; #[doc = "Interrupt Identity Register"] pub mod iir; -#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fcr`] +#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"] pub type FCR = crate::Reg; #[doc = "FIFO Control Register"] pub mod fcr; -#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lcr`] +#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] module"] pub type LCR = crate::Reg; #[doc = "Line Control Register"] pub mod lcr; -#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mcr`] +#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] pub type MCR = crate::Reg; #[doc = "Modem Control Register"] pub mod mcr; -#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lsr`] +#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] module"] pub type LSR = crate::Reg; #[doc = "Line Status Register"] pub mod lsr; -#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msr`] +#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"] pub type MSR = crate::Reg; #[doc = "Line Status Register"] pub mod msr; -#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scr`] +#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`] module"] pub type SCR = crate::Reg; #[doc = "Scratch Pad Register"] pub mod scr; -#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdll`] +#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdll`] module"] pub type LPDLL = crate::Reg; #[doc = "Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdll; -#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdlh`] +#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdlh`] module"] pub type LPDLH = crate::Reg; #[doc = "Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdlh; -#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr0`] +#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr0`] module"] pub type SRBR0 = crate::Reg; #[doc = "Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr0; -#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr0`] +#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr0`] module"] pub type STHR0 = crate::Reg; #[doc = "Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr0; -#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr1`] +#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr1`] module"] pub type SRBR1 = crate::Reg; #[doc = "Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr1; -#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr1`] +#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr1`] module"] pub type STHR1 = crate::Reg; #[doc = "Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr1; -#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr2`] +#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr2`] module"] pub type SRBR2 = crate::Reg; #[doc = "Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr2; -#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr2`] +#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr2`] module"] pub type STHR2 = crate::Reg; #[doc = "Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr2; -#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr3`] +#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr3`] module"] pub type SRBR3 = crate::Reg; #[doc = "Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr3; -#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr3`] +#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr3`] module"] pub type STHR3 = crate::Reg; #[doc = "Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr3; -#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr4`] +#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr4`] module"] pub type SRBR4 = crate::Reg; #[doc = "Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr4; -#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr4`] +#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr4`] module"] pub type STHR4 = crate::Reg; #[doc = "Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr4; -#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr5`] +#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr5`] module"] pub type SRBR5 = crate::Reg; #[doc = "Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr5; -#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr5`] +#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr5`] module"] pub type STHR5 = crate::Reg; #[doc = "Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr5; -#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr6`] +#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr6`] module"] pub type SRBR6 = crate::Reg; #[doc = "Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr6; -#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr6`] +#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr6`] module"] pub type STHR6 = crate::Reg; #[doc = "Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr6; -#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr7`] +#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr7`] module"] pub type SRBR7 = crate::Reg; #[doc = "Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr7; -#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr7`] +#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr7`] module"] pub type STHR7 = crate::Reg; #[doc = "Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr7; -#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr8`] +#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr8`] module"] pub type SRBR8 = crate::Reg; #[doc = "Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr8; -#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr8`] +#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr8`] module"] pub type STHR8 = crate::Reg; #[doc = "Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr8; -#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr9`] +#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr9`] module"] pub type SRBR9 = crate::Reg; #[doc = "Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr9; -#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr9`] +#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr9`] module"] pub type STHR9 = crate::Reg; #[doc = "Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr9; -#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr10`] +#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr10`] module"] pub type SRBR10 = crate::Reg; #[doc = "Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr10; -#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr10`] +#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr10`] module"] pub type STHR10 = crate::Reg; #[doc = "Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr10; -#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr11`] +#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr11`] module"] pub type SRBR11 = crate::Reg; #[doc = "Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr11; -#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr11`] +#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr11`] module"] pub type STHR11 = crate::Reg; #[doc = "Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr11; -#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr12`] +#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr12`] module"] pub type SRBR12 = crate::Reg; #[doc = "Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr12; -#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr12`] +#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr12`] module"] pub type STHR12 = crate::Reg; #[doc = "Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr12; -#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr13`] +#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr13`] module"] pub type SRBR13 = crate::Reg; #[doc = "Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr13; -#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr13`] +#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr13`] module"] pub type STHR13 = crate::Reg; #[doc = "Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr13; -#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr14`] +#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr14`] module"] pub type SRBR14 = crate::Reg; #[doc = "Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr14; -#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr14`] +#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr14`] module"] pub type STHR14 = crate::Reg; #[doc = "Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr14; -#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr15`] +#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr15`] module"] pub type SRBR15 = crate::Reg; #[doc = "Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr15; -#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr15`] +#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr15`] module"] pub type STHR15 = crate::Reg; #[doc = "Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr15; -#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`far`] +#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@far`] module"] pub type FAR = crate::Reg; #[doc = "FIFO Access Register"] pub mod far; -#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfr`] +#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfr`] module"] pub type TFR = crate::Reg; #[doc = "Transmit FIFO Read"] pub mod tfr; -#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfw`] +#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfw`] module"] pub type RFW = crate::Reg; #[doc = "Receive FIFO Write"] pub mod rfw; -#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`usr`] +#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usr`] module"] pub type USR = crate::Reg; #[doc = "UART Status Register"] pub mod usr; -#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfl`] +#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfl`] module"] pub type TFL = crate::Reg; #[doc = "Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod tfl; -#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfl`] +#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfl`] module"] pub type RFL = crate::Reg; #[doc = "Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod rfl; -#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srr`] +#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srr`] module"] pub type SRR = crate::Reg; #[doc = "Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srr; -#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srts`] +#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srts`] module"] pub type SRTS = crate::Reg; #[doc = "Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srts; -#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sbcr`] +#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sbcr`] module"] pub type SBCR = crate::Reg; #[doc = "Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sbcr; -#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sdmam`] +#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdmam`] module"] pub type SDMAM = crate::Reg; #[doc = "Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sdmam; -#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sfe`] +#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfe`] module"] pub type SFE = crate::Reg; #[doc = "Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sfe; -#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srt`] +#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srt`] module"] pub type SRT = crate::Reg; #[doc = "Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srt; -#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stet`] +#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stet`] module"] pub type STET = crate::Reg; #[doc = "Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod stet; -#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`htx`] +#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@htx`] module"] pub type HTX = crate::Reg; #[doc = "Halt TX"] pub mod htx; -#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dmasa`] +#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasa`] module"] pub type DMASA = crate::Reg; #[doc = "DMA Software Acknowledge"] pub mod dmasa; -#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cpr`] +#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpr`] module"] pub type CPR = crate::Reg; #[doc = "Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] pub mod cpr; -#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ucv`] +#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucv`] module"] pub type UCV = crate::Reg; #[doc = "UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] pub mod ucv; -#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctr`] +#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"] pub type CTR = crate::Reg; #[doc = "Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] diff --git a/jh7110-vf2-12a-pac/src/uart1/cpr.rs b/jh7110-vf2-12a-pac/src/uart1/cpr.rs index 4807519..332b584 100644 --- a/jh7110-vf2-12a-pac/src/uart1/cpr.rs +++ b/jh7110-vf2-12a-pac/src/uart1/cpr.rs @@ -89,7 +89,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/ctr.rs b/jh7110-vf2-12a-pac/src/uart1/ctr.rs index c3760d5..ac70194 100644 --- a/jh7110-vf2-12a-pac/src/uart1/ctr.rs +++ b/jh7110-vf2-12a-pac/src/uart1/ctr.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/dlh.rs b/jh7110-vf2-12a-pac/src/uart1/dlh.rs index 3257a2d..2a788c1 100644 --- a/jh7110-vf2-12a-pac/src/uart1/dlh.rs +++ b/jh7110-vf2-12a-pac/src/uart1/dlh.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLH_R = crate::FieldReader; #[doc = "Field `dlh` writer - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dlh(&mut self) -> DLH_W { - DLH_W::new(self) + pub fn dlh(&mut self) -> DLH_W { + DLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/dll.rs b/jh7110-vf2-12a-pac/src/uart1/dll.rs index 9c9daff..1c9d765 100644 --- a/jh7110-vf2-12a-pac/src/uart1/dll.rs +++ b/jh7110-vf2-12a-pac/src/uart1/dll.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLL_R = crate::FieldReader; #[doc = "Field `dll` writer - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dll(&mut self) -> DLL_W { - DLL_W::new(self) + pub fn dll(&mut self) -> DLL_W { + DLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/dmasa.rs b/jh7110-vf2-12a-pac/src/uart1/dmasa.rs index 7bcfb26..2fc4e6d 100644 --- a/jh7110-vf2-12a-pac/src/uart1/dmasa.rs +++ b/jh7110-vf2-12a-pac/src/uart1/dmasa.rs @@ -3,15 +3,19 @@ pub type R = crate::R; #[doc = "Register `dmasa` writer"] pub type W = crate::W; #[doc = "Field `dmasa` writer - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type DMASA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMASA_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn dmasa(&mut self) -> DMASA_W { - DMASA_W::new(self) + pub fn dmasa(&mut self) -> DMASA_W { + DMASA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/far.rs b/jh7110-vf2-12a-pac/src/uart1/far.rs index 3b3bcb1..d52059a 100644 --- a/jh7110-vf2-12a-pac/src/uart1/far.rs +++ b/jh7110-vf2-12a-pac/src/uart1/far.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `far` reader - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] pub type FAR_R = crate::BitReader; #[doc = "Field `far` writer - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] -pub type FAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FAR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] #[must_use] - pub fn far(&mut self) -> FAR_W { - FAR_W::new(self) + pub fn far(&mut self) -> FAR_W { + FAR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/fcr.rs b/jh7110-vf2-12a-pac/src/uart1/fcr.rs index 4fbb499..a64a60b 100644 --- a/jh7110-vf2-12a-pac/src/uart1/fcr.rs +++ b/jh7110-vf2-12a-pac/src/uart1/fcr.rs @@ -3,55 +3,59 @@ pub type R = crate::R; #[doc = "Register `fcr` writer"] pub type W = crate::W; #[doc = "Field `fifoe` writer - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] -pub type FIFOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIFOE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfifor` writer - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfifor` writer - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dmam` writer - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] -pub type DMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMAM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tet` writer - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type TET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `rt` writer - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type RT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type RT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl W { #[doc = "Bit 0 - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] #[inline(always)] #[must_use] - pub fn fifoe(&mut self) -> FIFOE_W { - FIFOE_W::new(self) + pub fn fifoe(&mut self) -> FIFOE_W { + FIFOE_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfifor(&mut self) -> RFIFOR_W { - RFIFOR_W::new(self) + pub fn rfifor(&mut self) -> RFIFOR_W { + RFIFOR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfifor(&mut self) -> XFIFOR_W { - XFIFOR_W::new(self) + pub fn xfifor(&mut self) -> XFIFOR_W { + XFIFOR_W::new(self, 2) } #[doc = "Bit 3 - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn dmam(&mut self) -> DMAM_W { - DMAM_W::new(self) + pub fn dmam(&mut self) -> DMAM_W { + DMAM_W::new(self, 3) } #[doc = "Bits 4:5 - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn tet(&mut self) -> TET_W { - TET_W::new(self) + pub fn tet(&mut self) -> TET_W { + TET_W::new(self, 4) } #[doc = "Bits 6:7 - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn rt(&mut self) -> RT_W { - RT_W::new(self) + pub fn rt(&mut self) -> RT_W { + RT_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/htx.rs b/jh7110-vf2-12a-pac/src/uart1/htx.rs index ad027bd..fc82325 100644 --- a/jh7110-vf2-12a-pac/src/uart1/htx.rs +++ b/jh7110-vf2-12a-pac/src/uart1/htx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `htx` reader - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] pub type HTX_R = crate::BitReader; #[doc = "Field `htx` writer - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] -pub type HTX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HTX_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] #[must_use] - pub fn htx(&mut self) -> HTX_W { - HTX_W::new(self) + pub fn htx(&mut self) -> HTX_W { + HTX_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/ier.rs b/jh7110-vf2-12a-pac/src/uart1/ier.rs index 006fbea..3cf3d7f 100644 --- a/jh7110-vf2-12a-pac/src/uart1/ier.rs +++ b/jh7110-vf2-12a-pac/src/uart1/ier.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `erbfi` reader - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] pub type ERBFI_R = crate::BitReader; #[doc = "Field `erbfi` writer - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] -pub type ERBFI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ERBFI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `etbei` reader - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] pub type ETBEI_R = crate::BitReader; #[doc = "Field `etbei` writer - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ETBEI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ETBEI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `elsi` reader - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] pub type ELSI_R = crate::BitReader; #[doc = "Field `elsi` writer - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ELSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ELSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `edssi` reader - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] pub type EDSSI_R = crate::BitReader; #[doc = "Field `edssi` writer - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] -pub type EDSSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EDSSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ptime` reader - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] pub type PTIME_R = crate::BitReader; #[doc = "Field `ptime` writer - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] -pub type PTIME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PTIME_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn erbfi(&mut self) -> ERBFI_W { - ERBFI_W::new(self) + pub fn erbfi(&mut self) -> ERBFI_W { + ERBFI_W::new(self, 0) } #[doc = "Bit 1 - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn etbei(&mut self) -> ETBEI_W { - ETBEI_W::new(self) + pub fn etbei(&mut self) -> ETBEI_W { + ETBEI_W::new(self, 1) } #[doc = "Bit 2 - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn elsi(&mut self) -> ELSI_W { - ELSI_W::new(self) + pub fn elsi(&mut self) -> ELSI_W { + ELSI_W::new(self, 2) } #[doc = "Bit 3 - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn edssi(&mut self) -> EDSSI_W { - EDSSI_W::new(self) + pub fn edssi(&mut self) -> EDSSI_W { + EDSSI_W::new(self, 3) } #[doc = "Bit 7 - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn ptime(&mut self) -> PTIME_W { - PTIME_W::new(self) + pub fn ptime(&mut self) -> PTIME_W { + PTIME_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/iir.rs b/jh7110-vf2-12a-pac/src/uart1/iir.rs index c90daa5..c949f03 100644 --- a/jh7110-vf2-12a-pac/src/uart1/iir.rs +++ b/jh7110-vf2-12a-pac/src/uart1/iir.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/lcr.rs b/jh7110-vf2-12a-pac/src/uart1/lcr.rs index acd83ee..3bc10c2 100644 --- a/jh7110-vf2-12a-pac/src/uart1/lcr.rs +++ b/jh7110-vf2-12a-pac/src/uart1/lcr.rs @@ -7,7 +7,7 @@ is zero), always readable. This is used to select the number of data bits per ch pub type DLS_R = crate::FieldReader; #[doc = "Field `dls` writer - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] -pub type DLS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DLS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `stop` reader - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] @@ -15,31 +15,31 @@ pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pen` reader - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] pub type PEN_R = crate::BitReader; #[doc = "Field `pen` writer - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] -pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `eps` reader - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] pub type EPS_R = crate::BitReader; #[doc = "Field `eps` writer - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] -pub type EPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EPS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bc` reader - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] pub type BC_R = crate::BitReader; #[doc = "Field `bc` writer - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] -pub type BC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dlab` reader - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] pub type DLAB_R = crate::BitReader; #[doc = "Field `dlab` writer - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] -pub type DLAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DLAB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:1 - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] @@ -84,46 +84,50 @@ impl W { is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] #[inline(always)] #[must_use] - pub fn dls(&mut self) -> DLS_W { - DLS_W::new(self) + pub fn dls(&mut self) -> DLS_W { + DLS_W::new(self, 0) } #[doc = "Bit 2 - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 2) } #[doc = "Bit 3 - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W { - PEN_W::new(self) + pub fn pen(&mut self) -> PEN_W { + PEN_W::new(self, 3) } #[doc = "Bit 4 - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] #[inline(always)] #[must_use] - pub fn eps(&mut self) -> EPS_W { - EPS_W::new(self) + pub fn eps(&mut self) -> EPS_W { + EPS_W::new(self, 4) } #[doc = "Bit 6 - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] #[inline(always)] #[must_use] - pub fn bc(&mut self) -> BC_W { - BC_W::new(self) + pub fn bc(&mut self) -> BC_W { + BC_W::new(self, 6) } #[doc = "Bit 7 - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] #[inline(always)] #[must_use] - pub fn dlab(&mut self) -> DLAB_W { - DLAB_W::new(self) + pub fn dlab(&mut self) -> DLAB_W { + DLAB_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/lpdlh.rs b/jh7110-vf2-12a-pac/src/uart1/lpdlh.rs index 8a910c8..095afa9 100644 --- a/jh7110-vf2-12a-pac/src/uart1/lpdlh.rs +++ b/jh7110-vf2-12a-pac/src/uart1/lpdlh.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdlh` reader - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] pub type LPDLH_R = crate::FieldReader; #[doc = "Field `lpdlh` writer - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] -pub type LPDLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] #[must_use] - pub fn lpdlh(&mut self) -> LPDLH_W { - LPDLH_W::new(self) + pub fn lpdlh(&mut self) -> LPDLH_W { + LPDLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/lpdll.rs b/jh7110-vf2-12a-pac/src/uart1/lpdll.rs index 7780651..21d0018 100644 --- a/jh7110-vf2-12a-pac/src/uart1/lpdll.rs +++ b/jh7110-vf2-12a-pac/src/uart1/lpdll.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdll` reader - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] pub type LPDLL_R = crate::FieldReader; #[doc = "Field `lpdll` writer - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type LPDLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn lpdll(&mut self) -> LPDLL_W { - LPDLL_W::new(self) + pub fn lpdll(&mut self) -> LPDLL_W { + LPDLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/lsr.rs b/jh7110-vf2-12a-pac/src/uart1/lsr.rs index f576c10..ff2ab48 100644 --- a/jh7110-vf2-12a-pac/src/uart1/lsr.rs +++ b/jh7110-vf2-12a-pac/src/uart1/lsr.rs @@ -73,7 +73,11 @@ set to one). This is used to indicate if there is at least one parity error, fra } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/mcr.rs b/jh7110-vf2-12a-pac/src/uart1/mcr.rs index 6932ee7..9c93108 100644 --- a/jh7110-vf2-12a-pac/src/uart1/mcr.rs +++ b/jh7110-vf2-12a-pac/src/uart1/mcr.rs @@ -7,7 +7,7 @@ set to one), the dtr_n output is held inactive high while the value of this loca pub type DTR_R = crate::BitReader; #[doc = "Field `dtr` writer - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type DTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rts` reader - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR\\[5\\] @@ -23,19 +23,19 @@ set to one) and FIFOs enable (FCR\\[0\\] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR\\[1\\] is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out1` reader - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT1_R = crate::BitReader; #[doc = "Field `out1` writer - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out2` reader - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT2_R = crate::BitReader; #[doc = "Field `out2` writer - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `lb` reader - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] @@ -43,15 +43,15 @@ pub type LB_R = crate::BitReader; #[doc = "Field `lb` writer - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] -pub type LB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `afce` reader - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] pub type AFCE_R = crate::BitReader; #[doc = "Field `afce` writer - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] -pub type AFCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AFCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sire` reader - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] pub type SIRE_R = crate::BitReader; #[doc = "Field `sire` writer - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] -pub type SIRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SIRE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] @@ -105,8 +105,8 @@ impl W { set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn dtr(&mut self) -> DTR_W { - DTR_W::new(self) + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 0) } #[doc = "Bit 1 - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] @@ -117,44 +117,48 @@ is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W { - RTS_W::new(self) + pub fn rts(&mut self) -> RTS_W { + RTS_W::new(self, 1) } #[doc = "Bit 2 - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out1(&mut self) -> OUT1_W { - OUT1_W::new(self) + pub fn out1(&mut self) -> OUT1_W { + OUT1_W::new(self, 2) } #[doc = "Bit 3 - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out2(&mut self) -> OUT2_W { - OUT2_W::new(self) + pub fn out2(&mut self) -> OUT2_W { + OUT2_W::new(self, 3) } #[doc = "Bit 4 - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] #[inline(always)] #[must_use] - pub fn lb(&mut self) -> LB_W { - LB_W::new(self) + pub fn lb(&mut self) -> LB_W { + LB_W::new(self, 4) } #[doc = "Bit 5 - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] #[inline(always)] #[must_use] - pub fn afce(&mut self) -> AFCE_W { - AFCE_W::new(self) + pub fn afce(&mut self) -> AFCE_W { + AFCE_W::new(self, 5) } #[doc = "Bit 6 - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] #[inline(always)] #[must_use] - pub fn sire(&mut self) -> SIRE_W { - SIRE_W::new(self) + pub fn sire(&mut self) -> SIRE_W { + SIRE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/msr.rs b/jh7110-vf2-12a-pac/src/uart1/msr.rs index 65c526b..b54fc38 100644 --- a/jh7110-vf2-12a-pac/src/uart1/msr.rs +++ b/jh7110-vf2-12a-pac/src/uart1/msr.rs @@ -93,7 +93,11 @@ set to one), DCD is the same as MCR\\[3\\] } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/rbr.rs b/jh7110-vf2-12a-pac/src/uart1/rbr.rs index 03003ed..403adcf 100644 --- a/jh7110-vf2-12a-pac/src/uart1/rbr.rs +++ b/jh7110-vf2-12a-pac/src/uart1/rbr.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/rfl.rs b/jh7110-vf2-12a-pac/src/uart1/rfl.rs index 2aea928..59355cb 100644 --- a/jh7110-vf2-12a-pac/src/uart1/rfl.rs +++ b/jh7110-vf2-12a-pac/src/uart1/rfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/rfw.rs b/jh7110-vf2-12a-pac/src/uart1/rfw.rs index 7b917de..490472d 100644 --- a/jh7110-vf2-12a-pac/src/uart1/rfw.rs +++ b/jh7110-vf2-12a-pac/src/uart1/rfw.rs @@ -4,36 +4,40 @@ pub type R = crate::R; pub type W = crate::W; #[doc = "Field `rfwd` writer - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] -pub type RFWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type RFWD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `rfpe` writer - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] -pub type RFPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFPE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rffe` writer - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] -pub type RFFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bits 0:7 - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] #[inline(always)] #[must_use] - pub fn rfwd(&mut self) -> RFWD_W { - RFWD_W::new(self) + pub fn rfwd(&mut self) -> RFWD_W { + RFWD_W::new(self, 0) } #[doc = "Bit 8 - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rfpe(&mut self) -> RFPE_W { - RFPE_W::new(self) + pub fn rfpe(&mut self) -> RFPE_W { + RFPE_W::new(self, 8) } #[doc = "Bit 9 - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rffe(&mut self) -> RFFE_W { - RFFE_W::new(self) + pub fn rffe(&mut self) -> RFFE_W { + RFFE_W::new(self, 9) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sbcr.rs b/jh7110-vf2-12a-pac/src/uart1/sbcr.rs index 73914e9..5a120c0 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sbcr.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sbcr.rs @@ -7,7 +7,7 @@ pub type W = crate::W; pub type SBCR_R = crate::BitReader; #[doc = "Field `sbcr` writer - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] -pub type SBCR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SBCR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] @@ -21,10 +21,14 @@ impl W { = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] #[inline(always)] #[must_use] - pub fn sbcr(&mut self) -> SBCR_W { - SBCR_W::new(self) + pub fn sbcr(&mut self) -> SBCR_W { + SBCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/scr.rs b/jh7110-vf2-12a-pac/src/uart1/scr.rs index 744352e..f46ba21 100644 --- a/jh7110-vf2-12a-pac/src/uart1/scr.rs +++ b/jh7110-vf2-12a-pac/src/uart1/scr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `scr` reader - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sdmam.rs b/jh7110-vf2-12a-pac/src/uart1/sdmam.rs index 684377c..4be4fa2 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sdmam.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sdmam.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sdmam` reader - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] pub type SDMAM_R = crate::BitReader; #[doc = "Field `sdmam` writer - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] -pub type SDMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SDMAM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn sdmam(&mut self) -> SDMAM_W { - SDMAM_W::new(self) + pub fn sdmam(&mut self) -> SDMAM_W { + SDMAM_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sfe.rs b/jh7110-vf2-12a-pac/src/uart1/sfe.rs index e68b088..ed26fee 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sfe.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sfe.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sfe` reader - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] pub type SFE_R = crate::BitReader; #[doc = "Field `sfe` writer - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] -pub type SFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] #[must_use] - pub fn sfe(&mut self) -> SFE_W { - SFE_W::new(self) + pub fn sfe(&mut self) -> SFE_W { + SFE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srbr0.rs b/jh7110-vf2-12a-pac/src/uart1/srbr0.rs index 4076661..4e44d1a 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srbr0.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srbr0.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srbr1.rs b/jh7110-vf2-12a-pac/src/uart1/srbr1.rs index 2f31b75..46bc479 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srbr1.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srbr1.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srbr10.rs b/jh7110-vf2-12a-pac/src/uart1/srbr10.rs index 3639d65..70297bf 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srbr10.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srbr10.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srbr11.rs b/jh7110-vf2-12a-pac/src/uart1/srbr11.rs index 92d29b1..28d0277 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srbr11.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srbr11.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srbr12.rs b/jh7110-vf2-12a-pac/src/uart1/srbr12.rs index 52e795e..3eccd9a 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srbr12.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srbr12.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srbr13.rs b/jh7110-vf2-12a-pac/src/uart1/srbr13.rs index 50aae40..e47e4e4 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srbr13.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srbr13.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srbr14.rs b/jh7110-vf2-12a-pac/src/uart1/srbr14.rs index cb25819..8f23662 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srbr14.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srbr14.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srbr15.rs b/jh7110-vf2-12a-pac/src/uart1/srbr15.rs index b25ae46..1dac092 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srbr15.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srbr15.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srbr2.rs b/jh7110-vf2-12a-pac/src/uart1/srbr2.rs index 9f3236c..afb0617 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srbr2.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srbr2.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srbr3.rs b/jh7110-vf2-12a-pac/src/uart1/srbr3.rs index 5c1edda..0ff3650 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srbr3.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srbr3.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srbr4.rs b/jh7110-vf2-12a-pac/src/uart1/srbr4.rs index e6bee93..59560c4 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srbr4.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srbr4.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srbr5.rs b/jh7110-vf2-12a-pac/src/uart1/srbr5.rs index e599009..763e341 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srbr5.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srbr5.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srbr6.rs b/jh7110-vf2-12a-pac/src/uart1/srbr6.rs index b0155b3..78e2a40 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srbr6.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srbr6.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srbr7.rs b/jh7110-vf2-12a-pac/src/uart1/srbr7.rs index b8f9b88..0723ff0 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srbr7.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srbr7.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srbr8.rs b/jh7110-vf2-12a-pac/src/uart1/srbr8.rs index f57b044..4702cd9 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srbr8.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srbr8.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srbr9.rs b/jh7110-vf2-12a-pac/src/uart1/srbr9.rs index 3a160aa..e1a262e 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srbr9.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srbr9.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srr.rs b/jh7110-vf2-12a-pac/src/uart1/srr.rs index 6671199..fdb0c0a 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srr.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srr.rs @@ -3,31 +3,35 @@ pub type R = crate::R; #[doc = "Register `srr` writer"] pub type W = crate::W; #[doc = "Field `ur` writer - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] -pub type UR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type UR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfr` writer - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfr` writer - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFR_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] #[inline(always)] #[must_use] - pub fn ur(&mut self) -> UR_W { - UR_W::new(self) + pub fn ur(&mut self) -> UR_W { + UR_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfr(&mut self) -> RFR_W { - RFR_W::new(self) + pub fn rfr(&mut self) -> RFR_W { + RFR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfr(&mut self) -> XFR_W { - XFR_W::new(self) + pub fn xfr(&mut self) -> XFR_W { + XFR_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srt.rs b/jh7110-vf2-12a-pac/src/uart1/srt.rs index fed4f1f..da909fd 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srt.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `srt` reader - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] pub type SRT_R = crate::FieldReader; #[doc = "Field `srt` writer - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type SRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SRT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn srt(&mut self) -> SRT_W { - SRT_W::new(self) + pub fn srt(&mut self) -> SRT_W { + SRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/srts.rs b/jh7110-vf2-12a-pac/src/uart1/srts.rs index ceb0ee4..cf1e2a9 100644 --- a/jh7110-vf2-12a-pac/src/uart1/srts.rs +++ b/jh7110-vf2-12a-pac/src/uart1/srts.rs @@ -15,7 +15,7 @@ pub type SRTS_R = crate::BitReader; = 1) and FIFOs enable (FCR\\[0\\] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR\\[4\\] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] -pub type SRTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SRTS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Request to Send. This is a shadow register for the RTS bit (MCR\\[1\\]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] = 0), the rts_n signal is set low by programming MCR\\[1\\] @@ -37,10 +37,14 @@ impl W { = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn srts(&mut self) -> SRTS_W { - SRTS_W::new(self) + pub fn srts(&mut self) -> SRTS_W { + SRTS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/stet.rs b/jh7110-vf2-12a-pac/src/uart1/stet.rs index acb8ba1..503dc8a 100644 --- a/jh7110-vf2-12a-pac/src/uart1/stet.rs +++ b/jh7110-vf2-12a-pac/src/uart1/stet.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `stet` reader - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] pub type STET_R = crate::FieldReader; #[doc = "Field `stet` writer - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type STET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type STET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn stet(&mut self) -> STET_W { - STET_W::new(self) + pub fn stet(&mut self) -> STET_W { + STET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sthr0.rs b/jh7110-vf2-12a-pac/src/uart1/sthr0.rs index bfd277a..764ff05 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sthr0.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sthr0.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sthr1.rs b/jh7110-vf2-12a-pac/src/uart1/sthr1.rs index cc79733..5d58855 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sthr1.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sthr1.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sthr10.rs b/jh7110-vf2-12a-pac/src/uart1/sthr10.rs index be2659d..ffc38ff 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sthr10.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sthr10.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sthr11.rs b/jh7110-vf2-12a-pac/src/uart1/sthr11.rs index 8613dd5..1f8147f 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sthr11.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sthr11.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sthr12.rs b/jh7110-vf2-12a-pac/src/uart1/sthr12.rs index b354b10..7d816f3 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sthr12.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sthr12.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sthr13.rs b/jh7110-vf2-12a-pac/src/uart1/sthr13.rs index 06df4bc..9283b6a 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sthr13.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sthr13.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sthr14.rs b/jh7110-vf2-12a-pac/src/uart1/sthr14.rs index e181dd0..2daf622 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sthr14.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sthr14.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sthr15.rs b/jh7110-vf2-12a-pac/src/uart1/sthr15.rs index 4825778..f70715e 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sthr15.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sthr15.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sthr2.rs b/jh7110-vf2-12a-pac/src/uart1/sthr2.rs index d390f10..f1a9c77 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sthr2.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sthr2.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sthr3.rs b/jh7110-vf2-12a-pac/src/uart1/sthr3.rs index a74fdf0..06aab9e 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sthr3.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sthr3.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sthr4.rs b/jh7110-vf2-12a-pac/src/uart1/sthr4.rs index 1ee6b87..f6e7944 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sthr4.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sthr4.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sthr5.rs b/jh7110-vf2-12a-pac/src/uart1/sthr5.rs index ca360fe..7873a53 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sthr5.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sthr5.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sthr6.rs b/jh7110-vf2-12a-pac/src/uart1/sthr6.rs index 18e6fac..87c81df 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sthr6.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sthr6.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sthr7.rs b/jh7110-vf2-12a-pac/src/uart1/sthr7.rs index 27072a3..9928b3d 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sthr7.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sthr7.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sthr8.rs b/jh7110-vf2-12a-pac/src/uart1/sthr8.rs index 15060b8..565cb1d 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sthr8.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sthr8.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/sthr9.rs b/jh7110-vf2-12a-pac/src/uart1/sthr9.rs index 58af642..e64fece 100644 --- a/jh7110-vf2-12a-pac/src/uart1/sthr9.rs +++ b/jh7110-vf2-12a-pac/src/uart1/sthr9.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/tfl.rs b/jh7110-vf2-12a-pac/src/uart1/tfl.rs index e1faba6..db09fe3 100644 --- a/jh7110-vf2-12a-pac/src/uart1/tfl.rs +++ b/jh7110-vf2-12a-pac/src/uart1/tfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/tfr.rs b/jh7110-vf2-12a-pac/src/uart1/tfr.rs index 8e9ad91..714deff 100644 --- a/jh7110-vf2-12a-pac/src/uart1/tfr.rs +++ b/jh7110-vf2-12a-pac/src/uart1/tfr.rs @@ -14,7 +14,11 @@ is set to one). When FIFOs are implemented and enabled, reading this register gi } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/thr.rs b/jh7110-vf2-12a-pac/src/uart1/thr.rs index f910bd8..7845232 100644 --- a/jh7110-vf2-12a-pac/src/uart1/thr.rs +++ b/jh7110-vf2-12a-pac/src/uart1/thr.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `thr` writer - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type THR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type THR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn thr(&mut self) -> THR_W { - THR_W::new(self) + pub fn thr(&mut self) -> THR_W { + THR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/ucv.rs b/jh7110-vf2-12a-pac/src/uart1/ucv.rs index 8a3be91..6497a08 100644 --- a/jh7110-vf2-12a-pac/src/uart1/ucv.rs +++ b/jh7110-vf2-12a-pac/src/uart1/ucv.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart1/usr.rs b/jh7110-vf2-12a-pac/src/uart1/usr.rs index 445a085..b96417d 100644 --- a/jh7110-vf2-12a-pac/src/uart1/usr.rs +++ b/jh7110-vf2-12a-pac/src/uart1/usr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2.rs b/jh7110-vf2-12a-pac/src/uart2.rs index c462fbf..8a5f089 100644 --- a/jh7110-vf2-12a-pac/src/uart2.rs +++ b/jh7110-vf2-12a-pac/src/uart2.rs @@ -4,20 +4,13 @@ pub struct RegisterBlock { _reserved_0_dll: [u8; 0x04], _reserved_1_dlh: [u8; 0x04], _reserved_2_fcr: [u8; 0x04], - #[doc = "0x0c - Line Control Register"] - pub lcr: LCR, - #[doc = "0x10 - Modem Control Register"] - pub mcr: MCR, - #[doc = "0x14 - Line Status Register"] - pub lsr: LSR, - #[doc = "0x18 - Line Status Register"] - pub msr: MSR, - #[doc = "0x1c - Scratch Pad Register"] - pub scr: SCR, - #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdll: LPDLL, - #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdlh: LPDLH, + lcr: LCR, + mcr: MCR, + lsr: LSR, + msr: MSR, + scr: SCR, + lpdll: LPDLL, + lpdlh: LPDLH, _reserved10: [u8; 0x08], _reserved_10_srbr0: [u8; 0x04], _reserved_11_srbr1: [u8; 0x04], @@ -35,564 +28,663 @@ pub struct RegisterBlock { _reserved_23_srbr13: [u8; 0x04], _reserved_24_srbr14: [u8; 0x04], _reserved_25_srbr15: [u8; 0x04], - #[doc = "0x70 - FIFO Access Register"] - pub far: FAR, - #[doc = "0x74 - Transmit FIFO Read"] - pub tfr: TFR, - #[doc = "0x78 - Receive FIFO Write"] - pub rfw: RFW, - #[doc = "0x7c - UART Status Register"] - pub usr: USR, - #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub tfl: TFL, - #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub rfl: RFL, - #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srr: SRR, - #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srts: SRTS, - #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sbcr: SBCR, - #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sdmam: SDMAM, - #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sfe: SFE, - #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srt: SRT, - #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub stet: STET, - #[doc = "0xa4 - Halt TX"] - pub htx: HTX, - #[doc = "0xa8 - DMA Software Acknowledge"] - pub dmasa: DMASA, + far: FAR, + tfr: TFR, + rfw: RFW, + usr: USR, + tfl: TFL, + rfl: RFL, + srr: SRR, + srts: SRTS, + sbcr: SBCR, + sdmam: SDMAM, + sfe: SFE, + srt: SRT, + stet: STET, + htx: HTX, + dmasa: DMASA, _reserved41: [u8; 0x48], - #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] - pub cpr: CPR, + cpr: CPR, _reserved_42_ctr: [u8; 0x04], } impl RegisterBlock { #[doc = "0x00 - Divisor Latch Low"] #[inline(always)] pub const fn dll(&self) -> &DLL { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Transmit Holding Register"] #[inline(always)] pub const fn thr(&self) -> &THR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Receive Buffer Register"] #[inline(always)] pub const fn rbr(&self) -> &RBR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x04 - Interrupt Enable Register"] #[inline(always)] pub const fn ier(&self) -> &IER { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x04 - Divisor Latch High"] #[inline(always)] pub const fn dlh(&self) -> &DLH { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x08 - FIFO Control Register"] #[inline(always)] pub const fn fcr(&self) -> &FCR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } } #[doc = "0x08 - Interrupt Identity Register"] #[inline(always)] pub const fn iir(&self) -> &IIR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } + } + #[doc = "0x0c - Line Control Register"] + #[inline(always)] + pub const fn lcr(&self) -> &LCR { + &self.lcr + } + #[doc = "0x10 - Modem Control Register"] + #[inline(always)] + pub const fn mcr(&self) -> &MCR { + &self.mcr + } + #[doc = "0x14 - Line Status Register"] + #[inline(always)] + pub const fn lsr(&self) -> &LSR { + &self.lsr + } + #[doc = "0x18 - Line Status Register"] + #[inline(always)] + pub const fn msr(&self) -> &MSR { + &self.msr + } + #[doc = "0x1c - Scratch Pad Register"] + #[inline(always)] + pub const fn scr(&self) -> &SCR { + &self.scr + } + #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdll(&self) -> &LPDLL { + &self.lpdll + } + #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdlh(&self) -> &LPDLH { + &self.lpdlh } #[doc = "0x30 - Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr0(&self) -> &STHR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x30 - Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr0(&self) -> &SRBR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x34 - Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr1(&self) -> &STHR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x34 - Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr1(&self) -> &SRBR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x38 - Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr2(&self) -> &STHR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x38 - Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr2(&self) -> &SRBR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x3c - Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr3(&self) -> &STHR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x3c - Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr3(&self) -> &SRBR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x40 - Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr4(&self) -> &STHR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x40 - Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr4(&self) -> &SRBR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x44 - Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr5(&self) -> &STHR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x44 - Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr5(&self) -> &SRBR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x48 - Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr6(&self) -> &STHR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x48 - Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr6(&self) -> &SRBR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x4c - Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr7(&self) -> &STHR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x4c - Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr7(&self) -> &SRBR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x50 - Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr8(&self) -> &STHR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x50 - Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr8(&self) -> &SRBR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x54 - Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr9(&self) -> &STHR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x54 - Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr9(&self) -> &SRBR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x58 - Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr10(&self) -> &STHR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x58 - Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr10(&self) -> &SRBR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x5c - Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr11(&self) -> &STHR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x5c - Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr11(&self) -> &SRBR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x60 - Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr12(&self) -> &STHR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x60 - Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr12(&self) -> &SRBR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x64 - Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr13(&self) -> &STHR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x64 - Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr13(&self) -> &SRBR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x68 - Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr14(&self) -> &STHR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x68 - Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr14(&self) -> &SRBR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x6c - Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr15(&self) -> &STHR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } } #[doc = "0x6c - Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr15(&self) -> &SRBR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } + } + #[doc = "0x70 - FIFO Access Register"] + #[inline(always)] + pub const fn far(&self) -> &FAR { + &self.far + } + #[doc = "0x74 - Transmit FIFO Read"] + #[inline(always)] + pub const fn tfr(&self) -> &TFR { + &self.tfr + } + #[doc = "0x78 - Receive FIFO Write"] + #[inline(always)] + pub const fn rfw(&self) -> &RFW { + &self.rfw + } + #[doc = "0x7c - UART Status Register"] + #[inline(always)] + pub const fn usr(&self) -> &USR { + &self.usr + } + #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn tfl(&self) -> &TFL { + &self.tfl + } + #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn rfl(&self) -> &RFL { + &self.rfl + } + #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srr(&self) -> &SRR { + &self.srr + } + #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srts(&self) -> &SRTS { + &self.srts + } + #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sbcr(&self) -> &SBCR { + &self.sbcr + } + #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sdmam(&self) -> &SDMAM { + &self.sdmam + } + #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sfe(&self) -> &SFE { + &self.sfe + } + #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srt(&self) -> &SRT { + &self.srt + } + #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn stet(&self) -> &STET { + &self.stet + } + #[doc = "0xa4 - Halt TX"] + #[inline(always)] + pub const fn htx(&self) -> &HTX { + &self.htx + } + #[doc = "0xa8 - DMA Software Acknowledge"] + #[inline(always)] + pub const fn dmasa(&self) -> &DMASA { + &self.dmasa + } + #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn cpr(&self) -> &CPR { + &self.cpr } #[doc = "0xf8 - Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ctr(&self) -> &CTR { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } #[doc = "0xf8 - UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ucv(&self) -> &UCV { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } } -#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rbr`] +#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbr`] module"] pub type RBR = crate::Reg; #[doc = "Receive Buffer Register"] pub mod rbr; -#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`thr`] +#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thr`] module"] pub type THR = crate::Reg; #[doc = "Transmit Holding Register"] pub mod thr; -#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dll`] +#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll`] module"] pub type DLL = crate::Reg; #[doc = "Divisor Latch Low"] pub mod dll; -#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dlh`] +#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlh`] module"] pub type DLH = crate::Reg; #[doc = "Divisor Latch High"] pub mod dlh; -#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`iir`] +#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] module"] pub type IIR = crate::Reg; #[doc = "Interrupt Identity Register"] pub mod iir; -#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fcr`] +#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"] pub type FCR = crate::Reg; #[doc = "FIFO Control Register"] pub mod fcr; -#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lcr`] +#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] module"] pub type LCR = crate::Reg; #[doc = "Line Control Register"] pub mod lcr; -#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mcr`] +#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] pub type MCR = crate::Reg; #[doc = "Modem Control Register"] pub mod mcr; -#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lsr`] +#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] module"] pub type LSR = crate::Reg; #[doc = "Line Status Register"] pub mod lsr; -#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msr`] +#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"] pub type MSR = crate::Reg; #[doc = "Line Status Register"] pub mod msr; -#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scr`] +#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`] module"] pub type SCR = crate::Reg; #[doc = "Scratch Pad Register"] pub mod scr; -#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdll`] +#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdll`] module"] pub type LPDLL = crate::Reg; #[doc = "Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdll; -#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdlh`] +#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdlh`] module"] pub type LPDLH = crate::Reg; #[doc = "Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdlh; -#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr0`] +#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr0`] module"] pub type SRBR0 = crate::Reg; #[doc = "Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr0; -#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr0`] +#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr0`] module"] pub type STHR0 = crate::Reg; #[doc = "Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr0; -#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr1`] +#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr1`] module"] pub type SRBR1 = crate::Reg; #[doc = "Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr1; -#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr1`] +#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr1`] module"] pub type STHR1 = crate::Reg; #[doc = "Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr1; -#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr2`] +#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr2`] module"] pub type SRBR2 = crate::Reg; #[doc = "Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr2; -#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr2`] +#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr2`] module"] pub type STHR2 = crate::Reg; #[doc = "Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr2; -#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr3`] +#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr3`] module"] pub type SRBR3 = crate::Reg; #[doc = "Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr3; -#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr3`] +#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr3`] module"] pub type STHR3 = crate::Reg; #[doc = "Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr3; -#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr4`] +#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr4`] module"] pub type SRBR4 = crate::Reg; #[doc = "Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr4; -#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr4`] +#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr4`] module"] pub type STHR4 = crate::Reg; #[doc = "Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr4; -#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr5`] +#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr5`] module"] pub type SRBR5 = crate::Reg; #[doc = "Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr5; -#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr5`] +#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr5`] module"] pub type STHR5 = crate::Reg; #[doc = "Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr5; -#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr6`] +#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr6`] module"] pub type SRBR6 = crate::Reg; #[doc = "Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr6; -#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr6`] +#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr6`] module"] pub type STHR6 = crate::Reg; #[doc = "Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr6; -#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr7`] +#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr7`] module"] pub type SRBR7 = crate::Reg; #[doc = "Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr7; -#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr7`] +#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr7`] module"] pub type STHR7 = crate::Reg; #[doc = "Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr7; -#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr8`] +#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr8`] module"] pub type SRBR8 = crate::Reg; #[doc = "Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr8; -#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr8`] +#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr8`] module"] pub type STHR8 = crate::Reg; #[doc = "Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr8; -#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr9`] +#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr9`] module"] pub type SRBR9 = crate::Reg; #[doc = "Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr9; -#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr9`] +#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr9`] module"] pub type STHR9 = crate::Reg; #[doc = "Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr9; -#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr10`] +#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr10`] module"] pub type SRBR10 = crate::Reg; #[doc = "Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr10; -#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr10`] +#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr10`] module"] pub type STHR10 = crate::Reg; #[doc = "Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr10; -#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr11`] +#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr11`] module"] pub type SRBR11 = crate::Reg; #[doc = "Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr11; -#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr11`] +#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr11`] module"] pub type STHR11 = crate::Reg; #[doc = "Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr11; -#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr12`] +#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr12`] module"] pub type SRBR12 = crate::Reg; #[doc = "Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr12; -#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr12`] +#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr12`] module"] pub type STHR12 = crate::Reg; #[doc = "Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr12; -#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr13`] +#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr13`] module"] pub type SRBR13 = crate::Reg; #[doc = "Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr13; -#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr13`] +#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr13`] module"] pub type STHR13 = crate::Reg; #[doc = "Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr13; -#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr14`] +#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr14`] module"] pub type SRBR14 = crate::Reg; #[doc = "Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr14; -#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr14`] +#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr14`] module"] pub type STHR14 = crate::Reg; #[doc = "Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr14; -#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr15`] +#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr15`] module"] pub type SRBR15 = crate::Reg; #[doc = "Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr15; -#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr15`] +#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr15`] module"] pub type STHR15 = crate::Reg; #[doc = "Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr15; -#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`far`] +#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@far`] module"] pub type FAR = crate::Reg; #[doc = "FIFO Access Register"] pub mod far; -#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfr`] +#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfr`] module"] pub type TFR = crate::Reg; #[doc = "Transmit FIFO Read"] pub mod tfr; -#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfw`] +#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfw`] module"] pub type RFW = crate::Reg; #[doc = "Receive FIFO Write"] pub mod rfw; -#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`usr`] +#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usr`] module"] pub type USR = crate::Reg; #[doc = "UART Status Register"] pub mod usr; -#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfl`] +#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfl`] module"] pub type TFL = crate::Reg; #[doc = "Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod tfl; -#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfl`] +#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfl`] module"] pub type RFL = crate::Reg; #[doc = "Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod rfl; -#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srr`] +#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srr`] module"] pub type SRR = crate::Reg; #[doc = "Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srr; -#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srts`] +#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srts`] module"] pub type SRTS = crate::Reg; #[doc = "Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srts; -#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sbcr`] +#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sbcr`] module"] pub type SBCR = crate::Reg; #[doc = "Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sbcr; -#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sdmam`] +#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdmam`] module"] pub type SDMAM = crate::Reg; #[doc = "Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sdmam; -#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sfe`] +#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfe`] module"] pub type SFE = crate::Reg; #[doc = "Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sfe; -#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srt`] +#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srt`] module"] pub type SRT = crate::Reg; #[doc = "Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srt; -#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stet`] +#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stet`] module"] pub type STET = crate::Reg; #[doc = "Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod stet; -#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`htx`] +#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@htx`] module"] pub type HTX = crate::Reg; #[doc = "Halt TX"] pub mod htx; -#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dmasa`] +#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasa`] module"] pub type DMASA = crate::Reg; #[doc = "DMA Software Acknowledge"] pub mod dmasa; -#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cpr`] +#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpr`] module"] pub type CPR = crate::Reg; #[doc = "Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] pub mod cpr; -#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ucv`] +#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucv`] module"] pub type UCV = crate::Reg; #[doc = "UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] pub mod ucv; -#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctr`] +#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"] pub type CTR = crate::Reg; #[doc = "Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] diff --git a/jh7110-vf2-12a-pac/src/uart2/cpr.rs b/jh7110-vf2-12a-pac/src/uart2/cpr.rs index 4807519..332b584 100644 --- a/jh7110-vf2-12a-pac/src/uart2/cpr.rs +++ b/jh7110-vf2-12a-pac/src/uart2/cpr.rs @@ -89,7 +89,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/ctr.rs b/jh7110-vf2-12a-pac/src/uart2/ctr.rs index c3760d5..ac70194 100644 --- a/jh7110-vf2-12a-pac/src/uart2/ctr.rs +++ b/jh7110-vf2-12a-pac/src/uart2/ctr.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/dlh.rs b/jh7110-vf2-12a-pac/src/uart2/dlh.rs index 3257a2d..2a788c1 100644 --- a/jh7110-vf2-12a-pac/src/uart2/dlh.rs +++ b/jh7110-vf2-12a-pac/src/uart2/dlh.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLH_R = crate::FieldReader; #[doc = "Field `dlh` writer - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dlh(&mut self) -> DLH_W { - DLH_W::new(self) + pub fn dlh(&mut self) -> DLH_W { + DLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/dll.rs b/jh7110-vf2-12a-pac/src/uart2/dll.rs index 9c9daff..1c9d765 100644 --- a/jh7110-vf2-12a-pac/src/uart2/dll.rs +++ b/jh7110-vf2-12a-pac/src/uart2/dll.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLL_R = crate::FieldReader; #[doc = "Field `dll` writer - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dll(&mut self) -> DLL_W { - DLL_W::new(self) + pub fn dll(&mut self) -> DLL_W { + DLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/dmasa.rs b/jh7110-vf2-12a-pac/src/uart2/dmasa.rs index 7bcfb26..2fc4e6d 100644 --- a/jh7110-vf2-12a-pac/src/uart2/dmasa.rs +++ b/jh7110-vf2-12a-pac/src/uart2/dmasa.rs @@ -3,15 +3,19 @@ pub type R = crate::R; #[doc = "Register `dmasa` writer"] pub type W = crate::W; #[doc = "Field `dmasa` writer - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type DMASA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMASA_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn dmasa(&mut self) -> DMASA_W { - DMASA_W::new(self) + pub fn dmasa(&mut self) -> DMASA_W { + DMASA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/far.rs b/jh7110-vf2-12a-pac/src/uart2/far.rs index 3b3bcb1..d52059a 100644 --- a/jh7110-vf2-12a-pac/src/uart2/far.rs +++ b/jh7110-vf2-12a-pac/src/uart2/far.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `far` reader - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] pub type FAR_R = crate::BitReader; #[doc = "Field `far` writer - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] -pub type FAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FAR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] #[must_use] - pub fn far(&mut self) -> FAR_W { - FAR_W::new(self) + pub fn far(&mut self) -> FAR_W { + FAR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/fcr.rs b/jh7110-vf2-12a-pac/src/uart2/fcr.rs index 4fbb499..a64a60b 100644 --- a/jh7110-vf2-12a-pac/src/uart2/fcr.rs +++ b/jh7110-vf2-12a-pac/src/uart2/fcr.rs @@ -3,55 +3,59 @@ pub type R = crate::R; #[doc = "Register `fcr` writer"] pub type W = crate::W; #[doc = "Field `fifoe` writer - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] -pub type FIFOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIFOE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfifor` writer - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfifor` writer - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dmam` writer - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] -pub type DMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMAM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tet` writer - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type TET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `rt` writer - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type RT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type RT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl W { #[doc = "Bit 0 - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] #[inline(always)] #[must_use] - pub fn fifoe(&mut self) -> FIFOE_W { - FIFOE_W::new(self) + pub fn fifoe(&mut self) -> FIFOE_W { + FIFOE_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfifor(&mut self) -> RFIFOR_W { - RFIFOR_W::new(self) + pub fn rfifor(&mut self) -> RFIFOR_W { + RFIFOR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfifor(&mut self) -> XFIFOR_W { - XFIFOR_W::new(self) + pub fn xfifor(&mut self) -> XFIFOR_W { + XFIFOR_W::new(self, 2) } #[doc = "Bit 3 - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn dmam(&mut self) -> DMAM_W { - DMAM_W::new(self) + pub fn dmam(&mut self) -> DMAM_W { + DMAM_W::new(self, 3) } #[doc = "Bits 4:5 - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn tet(&mut self) -> TET_W { - TET_W::new(self) + pub fn tet(&mut self) -> TET_W { + TET_W::new(self, 4) } #[doc = "Bits 6:7 - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn rt(&mut self) -> RT_W { - RT_W::new(self) + pub fn rt(&mut self) -> RT_W { + RT_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/htx.rs b/jh7110-vf2-12a-pac/src/uart2/htx.rs index ad027bd..fc82325 100644 --- a/jh7110-vf2-12a-pac/src/uart2/htx.rs +++ b/jh7110-vf2-12a-pac/src/uart2/htx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `htx` reader - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] pub type HTX_R = crate::BitReader; #[doc = "Field `htx` writer - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] -pub type HTX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HTX_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] #[must_use] - pub fn htx(&mut self) -> HTX_W { - HTX_W::new(self) + pub fn htx(&mut self) -> HTX_W { + HTX_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/ier.rs b/jh7110-vf2-12a-pac/src/uart2/ier.rs index 006fbea..3cf3d7f 100644 --- a/jh7110-vf2-12a-pac/src/uart2/ier.rs +++ b/jh7110-vf2-12a-pac/src/uart2/ier.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `erbfi` reader - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] pub type ERBFI_R = crate::BitReader; #[doc = "Field `erbfi` writer - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] -pub type ERBFI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ERBFI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `etbei` reader - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] pub type ETBEI_R = crate::BitReader; #[doc = "Field `etbei` writer - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ETBEI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ETBEI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `elsi` reader - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] pub type ELSI_R = crate::BitReader; #[doc = "Field `elsi` writer - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ELSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ELSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `edssi` reader - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] pub type EDSSI_R = crate::BitReader; #[doc = "Field `edssi` writer - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] -pub type EDSSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EDSSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ptime` reader - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] pub type PTIME_R = crate::BitReader; #[doc = "Field `ptime` writer - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] -pub type PTIME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PTIME_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn erbfi(&mut self) -> ERBFI_W { - ERBFI_W::new(self) + pub fn erbfi(&mut self) -> ERBFI_W { + ERBFI_W::new(self, 0) } #[doc = "Bit 1 - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn etbei(&mut self) -> ETBEI_W { - ETBEI_W::new(self) + pub fn etbei(&mut self) -> ETBEI_W { + ETBEI_W::new(self, 1) } #[doc = "Bit 2 - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn elsi(&mut self) -> ELSI_W { - ELSI_W::new(self) + pub fn elsi(&mut self) -> ELSI_W { + ELSI_W::new(self, 2) } #[doc = "Bit 3 - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn edssi(&mut self) -> EDSSI_W { - EDSSI_W::new(self) + pub fn edssi(&mut self) -> EDSSI_W { + EDSSI_W::new(self, 3) } #[doc = "Bit 7 - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn ptime(&mut self) -> PTIME_W { - PTIME_W::new(self) + pub fn ptime(&mut self) -> PTIME_W { + PTIME_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/iir.rs b/jh7110-vf2-12a-pac/src/uart2/iir.rs index c90daa5..c949f03 100644 --- a/jh7110-vf2-12a-pac/src/uart2/iir.rs +++ b/jh7110-vf2-12a-pac/src/uart2/iir.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/lcr.rs b/jh7110-vf2-12a-pac/src/uart2/lcr.rs index acd83ee..3bc10c2 100644 --- a/jh7110-vf2-12a-pac/src/uart2/lcr.rs +++ b/jh7110-vf2-12a-pac/src/uart2/lcr.rs @@ -7,7 +7,7 @@ is zero), always readable. This is used to select the number of data bits per ch pub type DLS_R = crate::FieldReader; #[doc = "Field `dls` writer - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] -pub type DLS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DLS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `stop` reader - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] @@ -15,31 +15,31 @@ pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pen` reader - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] pub type PEN_R = crate::BitReader; #[doc = "Field `pen` writer - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] -pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `eps` reader - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] pub type EPS_R = crate::BitReader; #[doc = "Field `eps` writer - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] -pub type EPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EPS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bc` reader - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] pub type BC_R = crate::BitReader; #[doc = "Field `bc` writer - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] -pub type BC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dlab` reader - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] pub type DLAB_R = crate::BitReader; #[doc = "Field `dlab` writer - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] -pub type DLAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DLAB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:1 - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] @@ -84,46 +84,50 @@ impl W { is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] #[inline(always)] #[must_use] - pub fn dls(&mut self) -> DLS_W { - DLS_W::new(self) + pub fn dls(&mut self) -> DLS_W { + DLS_W::new(self, 0) } #[doc = "Bit 2 - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 2) } #[doc = "Bit 3 - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W { - PEN_W::new(self) + pub fn pen(&mut self) -> PEN_W { + PEN_W::new(self, 3) } #[doc = "Bit 4 - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] #[inline(always)] #[must_use] - pub fn eps(&mut self) -> EPS_W { - EPS_W::new(self) + pub fn eps(&mut self) -> EPS_W { + EPS_W::new(self, 4) } #[doc = "Bit 6 - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] #[inline(always)] #[must_use] - pub fn bc(&mut self) -> BC_W { - BC_W::new(self) + pub fn bc(&mut self) -> BC_W { + BC_W::new(self, 6) } #[doc = "Bit 7 - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] #[inline(always)] #[must_use] - pub fn dlab(&mut self) -> DLAB_W { - DLAB_W::new(self) + pub fn dlab(&mut self) -> DLAB_W { + DLAB_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/lpdlh.rs b/jh7110-vf2-12a-pac/src/uart2/lpdlh.rs index 8a910c8..095afa9 100644 --- a/jh7110-vf2-12a-pac/src/uart2/lpdlh.rs +++ b/jh7110-vf2-12a-pac/src/uart2/lpdlh.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdlh` reader - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] pub type LPDLH_R = crate::FieldReader; #[doc = "Field `lpdlh` writer - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] -pub type LPDLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] #[must_use] - pub fn lpdlh(&mut self) -> LPDLH_W { - LPDLH_W::new(self) + pub fn lpdlh(&mut self) -> LPDLH_W { + LPDLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/lpdll.rs b/jh7110-vf2-12a-pac/src/uart2/lpdll.rs index 7780651..21d0018 100644 --- a/jh7110-vf2-12a-pac/src/uart2/lpdll.rs +++ b/jh7110-vf2-12a-pac/src/uart2/lpdll.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdll` reader - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] pub type LPDLL_R = crate::FieldReader; #[doc = "Field `lpdll` writer - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type LPDLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn lpdll(&mut self) -> LPDLL_W { - LPDLL_W::new(self) + pub fn lpdll(&mut self) -> LPDLL_W { + LPDLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/lsr.rs b/jh7110-vf2-12a-pac/src/uart2/lsr.rs index f576c10..ff2ab48 100644 --- a/jh7110-vf2-12a-pac/src/uart2/lsr.rs +++ b/jh7110-vf2-12a-pac/src/uart2/lsr.rs @@ -73,7 +73,11 @@ set to one). This is used to indicate if there is at least one parity error, fra } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/mcr.rs b/jh7110-vf2-12a-pac/src/uart2/mcr.rs index 6932ee7..9c93108 100644 --- a/jh7110-vf2-12a-pac/src/uart2/mcr.rs +++ b/jh7110-vf2-12a-pac/src/uart2/mcr.rs @@ -7,7 +7,7 @@ set to one), the dtr_n output is held inactive high while the value of this loca pub type DTR_R = crate::BitReader; #[doc = "Field `dtr` writer - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type DTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rts` reader - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR\\[5\\] @@ -23,19 +23,19 @@ set to one) and FIFOs enable (FCR\\[0\\] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR\\[1\\] is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out1` reader - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT1_R = crate::BitReader; #[doc = "Field `out1` writer - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out2` reader - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT2_R = crate::BitReader; #[doc = "Field `out2` writer - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `lb` reader - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] @@ -43,15 +43,15 @@ pub type LB_R = crate::BitReader; #[doc = "Field `lb` writer - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] -pub type LB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `afce` reader - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] pub type AFCE_R = crate::BitReader; #[doc = "Field `afce` writer - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] -pub type AFCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AFCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sire` reader - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] pub type SIRE_R = crate::BitReader; #[doc = "Field `sire` writer - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] -pub type SIRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SIRE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] @@ -105,8 +105,8 @@ impl W { set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn dtr(&mut self) -> DTR_W { - DTR_W::new(self) + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 0) } #[doc = "Bit 1 - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] @@ -117,44 +117,48 @@ is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W { - RTS_W::new(self) + pub fn rts(&mut self) -> RTS_W { + RTS_W::new(self, 1) } #[doc = "Bit 2 - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out1(&mut self) -> OUT1_W { - OUT1_W::new(self) + pub fn out1(&mut self) -> OUT1_W { + OUT1_W::new(self, 2) } #[doc = "Bit 3 - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out2(&mut self) -> OUT2_W { - OUT2_W::new(self) + pub fn out2(&mut self) -> OUT2_W { + OUT2_W::new(self, 3) } #[doc = "Bit 4 - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] #[inline(always)] #[must_use] - pub fn lb(&mut self) -> LB_W { - LB_W::new(self) + pub fn lb(&mut self) -> LB_W { + LB_W::new(self, 4) } #[doc = "Bit 5 - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] #[inline(always)] #[must_use] - pub fn afce(&mut self) -> AFCE_W { - AFCE_W::new(self) + pub fn afce(&mut self) -> AFCE_W { + AFCE_W::new(self, 5) } #[doc = "Bit 6 - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] #[inline(always)] #[must_use] - pub fn sire(&mut self) -> SIRE_W { - SIRE_W::new(self) + pub fn sire(&mut self) -> SIRE_W { + SIRE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/msr.rs b/jh7110-vf2-12a-pac/src/uart2/msr.rs index 65c526b..b54fc38 100644 --- a/jh7110-vf2-12a-pac/src/uart2/msr.rs +++ b/jh7110-vf2-12a-pac/src/uart2/msr.rs @@ -93,7 +93,11 @@ set to one), DCD is the same as MCR\\[3\\] } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/rbr.rs b/jh7110-vf2-12a-pac/src/uart2/rbr.rs index 03003ed..403adcf 100644 --- a/jh7110-vf2-12a-pac/src/uart2/rbr.rs +++ b/jh7110-vf2-12a-pac/src/uart2/rbr.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/rfl.rs b/jh7110-vf2-12a-pac/src/uart2/rfl.rs index 2aea928..59355cb 100644 --- a/jh7110-vf2-12a-pac/src/uart2/rfl.rs +++ b/jh7110-vf2-12a-pac/src/uart2/rfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/rfw.rs b/jh7110-vf2-12a-pac/src/uart2/rfw.rs index 7b917de..490472d 100644 --- a/jh7110-vf2-12a-pac/src/uart2/rfw.rs +++ b/jh7110-vf2-12a-pac/src/uart2/rfw.rs @@ -4,36 +4,40 @@ pub type R = crate::R; pub type W = crate::W; #[doc = "Field `rfwd` writer - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] -pub type RFWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type RFWD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `rfpe` writer - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] -pub type RFPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFPE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rffe` writer - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] -pub type RFFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bits 0:7 - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] #[inline(always)] #[must_use] - pub fn rfwd(&mut self) -> RFWD_W { - RFWD_W::new(self) + pub fn rfwd(&mut self) -> RFWD_W { + RFWD_W::new(self, 0) } #[doc = "Bit 8 - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rfpe(&mut self) -> RFPE_W { - RFPE_W::new(self) + pub fn rfpe(&mut self) -> RFPE_W { + RFPE_W::new(self, 8) } #[doc = "Bit 9 - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rffe(&mut self) -> RFFE_W { - RFFE_W::new(self) + pub fn rffe(&mut self) -> RFFE_W { + RFFE_W::new(self, 9) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sbcr.rs b/jh7110-vf2-12a-pac/src/uart2/sbcr.rs index 73914e9..5a120c0 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sbcr.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sbcr.rs @@ -7,7 +7,7 @@ pub type W = crate::W; pub type SBCR_R = crate::BitReader; #[doc = "Field `sbcr` writer - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] -pub type SBCR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SBCR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] @@ -21,10 +21,14 @@ impl W { = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] #[inline(always)] #[must_use] - pub fn sbcr(&mut self) -> SBCR_W { - SBCR_W::new(self) + pub fn sbcr(&mut self) -> SBCR_W { + SBCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/scr.rs b/jh7110-vf2-12a-pac/src/uart2/scr.rs index 744352e..f46ba21 100644 --- a/jh7110-vf2-12a-pac/src/uart2/scr.rs +++ b/jh7110-vf2-12a-pac/src/uart2/scr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `scr` reader - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sdmam.rs b/jh7110-vf2-12a-pac/src/uart2/sdmam.rs index 684377c..4be4fa2 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sdmam.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sdmam.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sdmam` reader - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] pub type SDMAM_R = crate::BitReader; #[doc = "Field `sdmam` writer - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] -pub type SDMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SDMAM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn sdmam(&mut self) -> SDMAM_W { - SDMAM_W::new(self) + pub fn sdmam(&mut self) -> SDMAM_W { + SDMAM_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sfe.rs b/jh7110-vf2-12a-pac/src/uart2/sfe.rs index e68b088..ed26fee 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sfe.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sfe.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sfe` reader - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] pub type SFE_R = crate::BitReader; #[doc = "Field `sfe` writer - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] -pub type SFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] #[must_use] - pub fn sfe(&mut self) -> SFE_W { - SFE_W::new(self) + pub fn sfe(&mut self) -> SFE_W { + SFE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srbr0.rs b/jh7110-vf2-12a-pac/src/uart2/srbr0.rs index 4076661..4e44d1a 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srbr0.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srbr0.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srbr1.rs b/jh7110-vf2-12a-pac/src/uart2/srbr1.rs index 2f31b75..46bc479 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srbr1.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srbr1.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srbr10.rs b/jh7110-vf2-12a-pac/src/uart2/srbr10.rs index 3639d65..70297bf 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srbr10.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srbr10.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srbr11.rs b/jh7110-vf2-12a-pac/src/uart2/srbr11.rs index 92d29b1..28d0277 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srbr11.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srbr11.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srbr12.rs b/jh7110-vf2-12a-pac/src/uart2/srbr12.rs index 52e795e..3eccd9a 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srbr12.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srbr12.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srbr13.rs b/jh7110-vf2-12a-pac/src/uart2/srbr13.rs index 50aae40..e47e4e4 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srbr13.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srbr13.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srbr14.rs b/jh7110-vf2-12a-pac/src/uart2/srbr14.rs index cb25819..8f23662 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srbr14.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srbr14.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srbr15.rs b/jh7110-vf2-12a-pac/src/uart2/srbr15.rs index b25ae46..1dac092 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srbr15.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srbr15.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srbr2.rs b/jh7110-vf2-12a-pac/src/uart2/srbr2.rs index 9f3236c..afb0617 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srbr2.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srbr2.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srbr3.rs b/jh7110-vf2-12a-pac/src/uart2/srbr3.rs index 5c1edda..0ff3650 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srbr3.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srbr3.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srbr4.rs b/jh7110-vf2-12a-pac/src/uart2/srbr4.rs index e6bee93..59560c4 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srbr4.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srbr4.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srbr5.rs b/jh7110-vf2-12a-pac/src/uart2/srbr5.rs index e599009..763e341 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srbr5.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srbr5.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srbr6.rs b/jh7110-vf2-12a-pac/src/uart2/srbr6.rs index b0155b3..78e2a40 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srbr6.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srbr6.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srbr7.rs b/jh7110-vf2-12a-pac/src/uart2/srbr7.rs index b8f9b88..0723ff0 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srbr7.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srbr7.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srbr8.rs b/jh7110-vf2-12a-pac/src/uart2/srbr8.rs index f57b044..4702cd9 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srbr8.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srbr8.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srbr9.rs b/jh7110-vf2-12a-pac/src/uart2/srbr9.rs index 3a160aa..e1a262e 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srbr9.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srbr9.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srr.rs b/jh7110-vf2-12a-pac/src/uart2/srr.rs index 6671199..fdb0c0a 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srr.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srr.rs @@ -3,31 +3,35 @@ pub type R = crate::R; #[doc = "Register `srr` writer"] pub type W = crate::W; #[doc = "Field `ur` writer - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] -pub type UR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type UR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfr` writer - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfr` writer - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFR_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] #[inline(always)] #[must_use] - pub fn ur(&mut self) -> UR_W { - UR_W::new(self) + pub fn ur(&mut self) -> UR_W { + UR_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfr(&mut self) -> RFR_W { - RFR_W::new(self) + pub fn rfr(&mut self) -> RFR_W { + RFR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfr(&mut self) -> XFR_W { - XFR_W::new(self) + pub fn xfr(&mut self) -> XFR_W { + XFR_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srt.rs b/jh7110-vf2-12a-pac/src/uart2/srt.rs index fed4f1f..da909fd 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srt.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `srt` reader - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] pub type SRT_R = crate::FieldReader; #[doc = "Field `srt` writer - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type SRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SRT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn srt(&mut self) -> SRT_W { - SRT_W::new(self) + pub fn srt(&mut self) -> SRT_W { + SRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/srts.rs b/jh7110-vf2-12a-pac/src/uart2/srts.rs index ceb0ee4..cf1e2a9 100644 --- a/jh7110-vf2-12a-pac/src/uart2/srts.rs +++ b/jh7110-vf2-12a-pac/src/uart2/srts.rs @@ -15,7 +15,7 @@ pub type SRTS_R = crate::BitReader; = 1) and FIFOs enable (FCR\\[0\\] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR\\[4\\] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] -pub type SRTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SRTS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Request to Send. This is a shadow register for the RTS bit (MCR\\[1\\]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] = 0), the rts_n signal is set low by programming MCR\\[1\\] @@ -37,10 +37,14 @@ impl W { = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn srts(&mut self) -> SRTS_W { - SRTS_W::new(self) + pub fn srts(&mut self) -> SRTS_W { + SRTS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/stet.rs b/jh7110-vf2-12a-pac/src/uart2/stet.rs index acb8ba1..503dc8a 100644 --- a/jh7110-vf2-12a-pac/src/uart2/stet.rs +++ b/jh7110-vf2-12a-pac/src/uart2/stet.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `stet` reader - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] pub type STET_R = crate::FieldReader; #[doc = "Field `stet` writer - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type STET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type STET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn stet(&mut self) -> STET_W { - STET_W::new(self) + pub fn stet(&mut self) -> STET_W { + STET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sthr0.rs b/jh7110-vf2-12a-pac/src/uart2/sthr0.rs index bfd277a..764ff05 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sthr0.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sthr0.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sthr1.rs b/jh7110-vf2-12a-pac/src/uart2/sthr1.rs index cc79733..5d58855 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sthr1.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sthr1.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sthr10.rs b/jh7110-vf2-12a-pac/src/uart2/sthr10.rs index be2659d..ffc38ff 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sthr10.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sthr10.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sthr11.rs b/jh7110-vf2-12a-pac/src/uart2/sthr11.rs index 8613dd5..1f8147f 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sthr11.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sthr11.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sthr12.rs b/jh7110-vf2-12a-pac/src/uart2/sthr12.rs index b354b10..7d816f3 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sthr12.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sthr12.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sthr13.rs b/jh7110-vf2-12a-pac/src/uart2/sthr13.rs index 06df4bc..9283b6a 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sthr13.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sthr13.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sthr14.rs b/jh7110-vf2-12a-pac/src/uart2/sthr14.rs index e181dd0..2daf622 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sthr14.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sthr14.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sthr15.rs b/jh7110-vf2-12a-pac/src/uart2/sthr15.rs index 4825778..f70715e 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sthr15.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sthr15.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sthr2.rs b/jh7110-vf2-12a-pac/src/uart2/sthr2.rs index d390f10..f1a9c77 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sthr2.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sthr2.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sthr3.rs b/jh7110-vf2-12a-pac/src/uart2/sthr3.rs index a74fdf0..06aab9e 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sthr3.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sthr3.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sthr4.rs b/jh7110-vf2-12a-pac/src/uart2/sthr4.rs index 1ee6b87..f6e7944 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sthr4.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sthr4.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sthr5.rs b/jh7110-vf2-12a-pac/src/uart2/sthr5.rs index ca360fe..7873a53 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sthr5.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sthr5.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sthr6.rs b/jh7110-vf2-12a-pac/src/uart2/sthr6.rs index 18e6fac..87c81df 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sthr6.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sthr6.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sthr7.rs b/jh7110-vf2-12a-pac/src/uart2/sthr7.rs index 27072a3..9928b3d 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sthr7.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sthr7.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sthr8.rs b/jh7110-vf2-12a-pac/src/uart2/sthr8.rs index 15060b8..565cb1d 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sthr8.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sthr8.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/sthr9.rs b/jh7110-vf2-12a-pac/src/uart2/sthr9.rs index 58af642..e64fece 100644 --- a/jh7110-vf2-12a-pac/src/uart2/sthr9.rs +++ b/jh7110-vf2-12a-pac/src/uart2/sthr9.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/tfl.rs b/jh7110-vf2-12a-pac/src/uart2/tfl.rs index e1faba6..db09fe3 100644 --- a/jh7110-vf2-12a-pac/src/uart2/tfl.rs +++ b/jh7110-vf2-12a-pac/src/uart2/tfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/tfr.rs b/jh7110-vf2-12a-pac/src/uart2/tfr.rs index 8e9ad91..714deff 100644 --- a/jh7110-vf2-12a-pac/src/uart2/tfr.rs +++ b/jh7110-vf2-12a-pac/src/uart2/tfr.rs @@ -14,7 +14,11 @@ is set to one). When FIFOs are implemented and enabled, reading this register gi } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/thr.rs b/jh7110-vf2-12a-pac/src/uart2/thr.rs index f910bd8..7845232 100644 --- a/jh7110-vf2-12a-pac/src/uart2/thr.rs +++ b/jh7110-vf2-12a-pac/src/uart2/thr.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `thr` writer - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type THR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type THR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn thr(&mut self) -> THR_W { - THR_W::new(self) + pub fn thr(&mut self) -> THR_W { + THR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/ucv.rs b/jh7110-vf2-12a-pac/src/uart2/ucv.rs index 8a3be91..6497a08 100644 --- a/jh7110-vf2-12a-pac/src/uart2/ucv.rs +++ b/jh7110-vf2-12a-pac/src/uart2/ucv.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart2/usr.rs b/jh7110-vf2-12a-pac/src/uart2/usr.rs index 445a085..b96417d 100644 --- a/jh7110-vf2-12a-pac/src/uart2/usr.rs +++ b/jh7110-vf2-12a-pac/src/uart2/usr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3.rs b/jh7110-vf2-12a-pac/src/uart3.rs index c462fbf..8a5f089 100644 --- a/jh7110-vf2-12a-pac/src/uart3.rs +++ b/jh7110-vf2-12a-pac/src/uart3.rs @@ -4,20 +4,13 @@ pub struct RegisterBlock { _reserved_0_dll: [u8; 0x04], _reserved_1_dlh: [u8; 0x04], _reserved_2_fcr: [u8; 0x04], - #[doc = "0x0c - Line Control Register"] - pub lcr: LCR, - #[doc = "0x10 - Modem Control Register"] - pub mcr: MCR, - #[doc = "0x14 - Line Status Register"] - pub lsr: LSR, - #[doc = "0x18 - Line Status Register"] - pub msr: MSR, - #[doc = "0x1c - Scratch Pad Register"] - pub scr: SCR, - #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdll: LPDLL, - #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdlh: LPDLH, + lcr: LCR, + mcr: MCR, + lsr: LSR, + msr: MSR, + scr: SCR, + lpdll: LPDLL, + lpdlh: LPDLH, _reserved10: [u8; 0x08], _reserved_10_srbr0: [u8; 0x04], _reserved_11_srbr1: [u8; 0x04], @@ -35,564 +28,663 @@ pub struct RegisterBlock { _reserved_23_srbr13: [u8; 0x04], _reserved_24_srbr14: [u8; 0x04], _reserved_25_srbr15: [u8; 0x04], - #[doc = "0x70 - FIFO Access Register"] - pub far: FAR, - #[doc = "0x74 - Transmit FIFO Read"] - pub tfr: TFR, - #[doc = "0x78 - Receive FIFO Write"] - pub rfw: RFW, - #[doc = "0x7c - UART Status Register"] - pub usr: USR, - #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub tfl: TFL, - #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub rfl: RFL, - #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srr: SRR, - #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srts: SRTS, - #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sbcr: SBCR, - #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sdmam: SDMAM, - #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sfe: SFE, - #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srt: SRT, - #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub stet: STET, - #[doc = "0xa4 - Halt TX"] - pub htx: HTX, - #[doc = "0xa8 - DMA Software Acknowledge"] - pub dmasa: DMASA, + far: FAR, + tfr: TFR, + rfw: RFW, + usr: USR, + tfl: TFL, + rfl: RFL, + srr: SRR, + srts: SRTS, + sbcr: SBCR, + sdmam: SDMAM, + sfe: SFE, + srt: SRT, + stet: STET, + htx: HTX, + dmasa: DMASA, _reserved41: [u8; 0x48], - #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] - pub cpr: CPR, + cpr: CPR, _reserved_42_ctr: [u8; 0x04], } impl RegisterBlock { #[doc = "0x00 - Divisor Latch Low"] #[inline(always)] pub const fn dll(&self) -> &DLL { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Transmit Holding Register"] #[inline(always)] pub const fn thr(&self) -> &THR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Receive Buffer Register"] #[inline(always)] pub const fn rbr(&self) -> &RBR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x04 - Interrupt Enable Register"] #[inline(always)] pub const fn ier(&self) -> &IER { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x04 - Divisor Latch High"] #[inline(always)] pub const fn dlh(&self) -> &DLH { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x08 - FIFO Control Register"] #[inline(always)] pub const fn fcr(&self) -> &FCR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } } #[doc = "0x08 - Interrupt Identity Register"] #[inline(always)] pub const fn iir(&self) -> &IIR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } + } + #[doc = "0x0c - Line Control Register"] + #[inline(always)] + pub const fn lcr(&self) -> &LCR { + &self.lcr + } + #[doc = "0x10 - Modem Control Register"] + #[inline(always)] + pub const fn mcr(&self) -> &MCR { + &self.mcr + } + #[doc = "0x14 - Line Status Register"] + #[inline(always)] + pub const fn lsr(&self) -> &LSR { + &self.lsr + } + #[doc = "0x18 - Line Status Register"] + #[inline(always)] + pub const fn msr(&self) -> &MSR { + &self.msr + } + #[doc = "0x1c - Scratch Pad Register"] + #[inline(always)] + pub const fn scr(&self) -> &SCR { + &self.scr + } + #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdll(&self) -> &LPDLL { + &self.lpdll + } + #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdlh(&self) -> &LPDLH { + &self.lpdlh } #[doc = "0x30 - Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr0(&self) -> &STHR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x30 - Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr0(&self) -> &SRBR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x34 - Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr1(&self) -> &STHR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x34 - Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr1(&self) -> &SRBR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x38 - Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr2(&self) -> &STHR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x38 - Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr2(&self) -> &SRBR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x3c - Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr3(&self) -> &STHR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x3c - Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr3(&self) -> &SRBR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x40 - Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr4(&self) -> &STHR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x40 - Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr4(&self) -> &SRBR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x44 - Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr5(&self) -> &STHR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x44 - Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr5(&self) -> &SRBR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x48 - Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr6(&self) -> &STHR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x48 - Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr6(&self) -> &SRBR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x4c - Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr7(&self) -> &STHR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x4c - Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr7(&self) -> &SRBR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x50 - Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr8(&self) -> &STHR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x50 - Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr8(&self) -> &SRBR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x54 - Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr9(&self) -> &STHR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x54 - Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr9(&self) -> &SRBR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x58 - Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr10(&self) -> &STHR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x58 - Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr10(&self) -> &SRBR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x5c - Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr11(&self) -> &STHR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x5c - Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr11(&self) -> &SRBR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x60 - Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr12(&self) -> &STHR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x60 - Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr12(&self) -> &SRBR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x64 - Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr13(&self) -> &STHR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x64 - Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr13(&self) -> &SRBR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x68 - Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr14(&self) -> &STHR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x68 - Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr14(&self) -> &SRBR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x6c - Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr15(&self) -> &STHR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } } #[doc = "0x6c - Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr15(&self) -> &SRBR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } + } + #[doc = "0x70 - FIFO Access Register"] + #[inline(always)] + pub const fn far(&self) -> &FAR { + &self.far + } + #[doc = "0x74 - Transmit FIFO Read"] + #[inline(always)] + pub const fn tfr(&self) -> &TFR { + &self.tfr + } + #[doc = "0x78 - Receive FIFO Write"] + #[inline(always)] + pub const fn rfw(&self) -> &RFW { + &self.rfw + } + #[doc = "0x7c - UART Status Register"] + #[inline(always)] + pub const fn usr(&self) -> &USR { + &self.usr + } + #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn tfl(&self) -> &TFL { + &self.tfl + } + #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn rfl(&self) -> &RFL { + &self.rfl + } + #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srr(&self) -> &SRR { + &self.srr + } + #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srts(&self) -> &SRTS { + &self.srts + } + #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sbcr(&self) -> &SBCR { + &self.sbcr + } + #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sdmam(&self) -> &SDMAM { + &self.sdmam + } + #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sfe(&self) -> &SFE { + &self.sfe + } + #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srt(&self) -> &SRT { + &self.srt + } + #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn stet(&self) -> &STET { + &self.stet + } + #[doc = "0xa4 - Halt TX"] + #[inline(always)] + pub const fn htx(&self) -> &HTX { + &self.htx + } + #[doc = "0xa8 - DMA Software Acknowledge"] + #[inline(always)] + pub const fn dmasa(&self) -> &DMASA { + &self.dmasa + } + #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn cpr(&self) -> &CPR { + &self.cpr } #[doc = "0xf8 - Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ctr(&self) -> &CTR { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } #[doc = "0xf8 - UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ucv(&self) -> &UCV { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } } -#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rbr`] +#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbr`] module"] pub type RBR = crate::Reg; #[doc = "Receive Buffer Register"] pub mod rbr; -#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`thr`] +#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thr`] module"] pub type THR = crate::Reg; #[doc = "Transmit Holding Register"] pub mod thr; -#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dll`] +#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll`] module"] pub type DLL = crate::Reg; #[doc = "Divisor Latch Low"] pub mod dll; -#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dlh`] +#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlh`] module"] pub type DLH = crate::Reg; #[doc = "Divisor Latch High"] pub mod dlh; -#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`iir`] +#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] module"] pub type IIR = crate::Reg; #[doc = "Interrupt Identity Register"] pub mod iir; -#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fcr`] +#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"] pub type FCR = crate::Reg; #[doc = "FIFO Control Register"] pub mod fcr; -#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lcr`] +#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] module"] pub type LCR = crate::Reg; #[doc = "Line Control Register"] pub mod lcr; -#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mcr`] +#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] pub type MCR = crate::Reg; #[doc = "Modem Control Register"] pub mod mcr; -#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lsr`] +#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] module"] pub type LSR = crate::Reg; #[doc = "Line Status Register"] pub mod lsr; -#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msr`] +#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"] pub type MSR = crate::Reg; #[doc = "Line Status Register"] pub mod msr; -#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scr`] +#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`] module"] pub type SCR = crate::Reg; #[doc = "Scratch Pad Register"] pub mod scr; -#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdll`] +#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdll`] module"] pub type LPDLL = crate::Reg; #[doc = "Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdll; -#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdlh`] +#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdlh`] module"] pub type LPDLH = crate::Reg; #[doc = "Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdlh; -#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr0`] +#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr0`] module"] pub type SRBR0 = crate::Reg; #[doc = "Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr0; -#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr0`] +#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr0`] module"] pub type STHR0 = crate::Reg; #[doc = "Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr0; -#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr1`] +#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr1`] module"] pub type SRBR1 = crate::Reg; #[doc = "Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr1; -#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr1`] +#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr1`] module"] pub type STHR1 = crate::Reg; #[doc = "Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr1; -#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr2`] +#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr2`] module"] pub type SRBR2 = crate::Reg; #[doc = "Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr2; -#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr2`] +#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr2`] module"] pub type STHR2 = crate::Reg; #[doc = "Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr2; -#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr3`] +#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr3`] module"] pub type SRBR3 = crate::Reg; #[doc = "Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr3; -#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr3`] +#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr3`] module"] pub type STHR3 = crate::Reg; #[doc = "Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr3; -#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr4`] +#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr4`] module"] pub type SRBR4 = crate::Reg; #[doc = "Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr4; -#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr4`] +#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr4`] module"] pub type STHR4 = crate::Reg; #[doc = "Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr4; -#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr5`] +#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr5`] module"] pub type SRBR5 = crate::Reg; #[doc = "Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr5; -#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr5`] +#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr5`] module"] pub type STHR5 = crate::Reg; #[doc = "Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr5; -#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr6`] +#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr6`] module"] pub type SRBR6 = crate::Reg; #[doc = "Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr6; -#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr6`] +#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr6`] module"] pub type STHR6 = crate::Reg; #[doc = "Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr6; -#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr7`] +#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr7`] module"] pub type SRBR7 = crate::Reg; #[doc = "Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr7; -#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr7`] +#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr7`] module"] pub type STHR7 = crate::Reg; #[doc = "Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr7; -#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr8`] +#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr8`] module"] pub type SRBR8 = crate::Reg; #[doc = "Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr8; -#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr8`] +#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr8`] module"] pub type STHR8 = crate::Reg; #[doc = "Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr8; -#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr9`] +#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr9`] module"] pub type SRBR9 = crate::Reg; #[doc = "Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr9; -#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr9`] +#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr9`] module"] pub type STHR9 = crate::Reg; #[doc = "Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr9; -#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr10`] +#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr10`] module"] pub type SRBR10 = crate::Reg; #[doc = "Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr10; -#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr10`] +#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr10`] module"] pub type STHR10 = crate::Reg; #[doc = "Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr10; -#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr11`] +#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr11`] module"] pub type SRBR11 = crate::Reg; #[doc = "Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr11; -#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr11`] +#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr11`] module"] pub type STHR11 = crate::Reg; #[doc = "Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr11; -#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr12`] +#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr12`] module"] pub type SRBR12 = crate::Reg; #[doc = "Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr12; -#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr12`] +#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr12`] module"] pub type STHR12 = crate::Reg; #[doc = "Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr12; -#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr13`] +#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr13`] module"] pub type SRBR13 = crate::Reg; #[doc = "Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr13; -#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr13`] +#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr13`] module"] pub type STHR13 = crate::Reg; #[doc = "Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr13; -#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr14`] +#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr14`] module"] pub type SRBR14 = crate::Reg; #[doc = "Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr14; -#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr14`] +#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr14`] module"] pub type STHR14 = crate::Reg; #[doc = "Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr14; -#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr15`] +#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr15`] module"] pub type SRBR15 = crate::Reg; #[doc = "Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr15; -#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr15`] +#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr15`] module"] pub type STHR15 = crate::Reg; #[doc = "Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr15; -#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`far`] +#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@far`] module"] pub type FAR = crate::Reg; #[doc = "FIFO Access Register"] pub mod far; -#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfr`] +#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfr`] module"] pub type TFR = crate::Reg; #[doc = "Transmit FIFO Read"] pub mod tfr; -#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfw`] +#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfw`] module"] pub type RFW = crate::Reg; #[doc = "Receive FIFO Write"] pub mod rfw; -#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`usr`] +#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usr`] module"] pub type USR = crate::Reg; #[doc = "UART Status Register"] pub mod usr; -#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfl`] +#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfl`] module"] pub type TFL = crate::Reg; #[doc = "Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod tfl; -#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfl`] +#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfl`] module"] pub type RFL = crate::Reg; #[doc = "Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod rfl; -#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srr`] +#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srr`] module"] pub type SRR = crate::Reg; #[doc = "Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srr; -#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srts`] +#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srts`] module"] pub type SRTS = crate::Reg; #[doc = "Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srts; -#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sbcr`] +#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sbcr`] module"] pub type SBCR = crate::Reg; #[doc = "Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sbcr; -#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sdmam`] +#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdmam`] module"] pub type SDMAM = crate::Reg; #[doc = "Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sdmam; -#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sfe`] +#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfe`] module"] pub type SFE = crate::Reg; #[doc = "Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sfe; -#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srt`] +#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srt`] module"] pub type SRT = crate::Reg; #[doc = "Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srt; -#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stet`] +#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stet`] module"] pub type STET = crate::Reg; #[doc = "Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod stet; -#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`htx`] +#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@htx`] module"] pub type HTX = crate::Reg; #[doc = "Halt TX"] pub mod htx; -#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dmasa`] +#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasa`] module"] pub type DMASA = crate::Reg; #[doc = "DMA Software Acknowledge"] pub mod dmasa; -#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cpr`] +#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpr`] module"] pub type CPR = crate::Reg; #[doc = "Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] pub mod cpr; -#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ucv`] +#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucv`] module"] pub type UCV = crate::Reg; #[doc = "UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] pub mod ucv; -#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctr`] +#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"] pub type CTR = crate::Reg; #[doc = "Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] diff --git a/jh7110-vf2-12a-pac/src/uart3/cpr.rs b/jh7110-vf2-12a-pac/src/uart3/cpr.rs index 4807519..332b584 100644 --- a/jh7110-vf2-12a-pac/src/uart3/cpr.rs +++ b/jh7110-vf2-12a-pac/src/uart3/cpr.rs @@ -89,7 +89,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/ctr.rs b/jh7110-vf2-12a-pac/src/uart3/ctr.rs index c3760d5..ac70194 100644 --- a/jh7110-vf2-12a-pac/src/uart3/ctr.rs +++ b/jh7110-vf2-12a-pac/src/uart3/ctr.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/dlh.rs b/jh7110-vf2-12a-pac/src/uart3/dlh.rs index 3257a2d..2a788c1 100644 --- a/jh7110-vf2-12a-pac/src/uart3/dlh.rs +++ b/jh7110-vf2-12a-pac/src/uart3/dlh.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLH_R = crate::FieldReader; #[doc = "Field `dlh` writer - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dlh(&mut self) -> DLH_W { - DLH_W::new(self) + pub fn dlh(&mut self) -> DLH_W { + DLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/dll.rs b/jh7110-vf2-12a-pac/src/uart3/dll.rs index 9c9daff..1c9d765 100644 --- a/jh7110-vf2-12a-pac/src/uart3/dll.rs +++ b/jh7110-vf2-12a-pac/src/uart3/dll.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLL_R = crate::FieldReader; #[doc = "Field `dll` writer - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dll(&mut self) -> DLL_W { - DLL_W::new(self) + pub fn dll(&mut self) -> DLL_W { + DLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/dmasa.rs b/jh7110-vf2-12a-pac/src/uart3/dmasa.rs index 7bcfb26..2fc4e6d 100644 --- a/jh7110-vf2-12a-pac/src/uart3/dmasa.rs +++ b/jh7110-vf2-12a-pac/src/uart3/dmasa.rs @@ -3,15 +3,19 @@ pub type R = crate::R; #[doc = "Register `dmasa` writer"] pub type W = crate::W; #[doc = "Field `dmasa` writer - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type DMASA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMASA_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn dmasa(&mut self) -> DMASA_W { - DMASA_W::new(self) + pub fn dmasa(&mut self) -> DMASA_W { + DMASA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/far.rs b/jh7110-vf2-12a-pac/src/uart3/far.rs index 3b3bcb1..d52059a 100644 --- a/jh7110-vf2-12a-pac/src/uart3/far.rs +++ b/jh7110-vf2-12a-pac/src/uart3/far.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `far` reader - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] pub type FAR_R = crate::BitReader; #[doc = "Field `far` writer - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] -pub type FAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FAR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] #[must_use] - pub fn far(&mut self) -> FAR_W { - FAR_W::new(self) + pub fn far(&mut self) -> FAR_W { + FAR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/fcr.rs b/jh7110-vf2-12a-pac/src/uart3/fcr.rs index 4fbb499..a64a60b 100644 --- a/jh7110-vf2-12a-pac/src/uart3/fcr.rs +++ b/jh7110-vf2-12a-pac/src/uart3/fcr.rs @@ -3,55 +3,59 @@ pub type R = crate::R; #[doc = "Register `fcr` writer"] pub type W = crate::W; #[doc = "Field `fifoe` writer - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] -pub type FIFOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIFOE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfifor` writer - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfifor` writer - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dmam` writer - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] -pub type DMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMAM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tet` writer - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type TET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `rt` writer - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type RT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type RT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl W { #[doc = "Bit 0 - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] #[inline(always)] #[must_use] - pub fn fifoe(&mut self) -> FIFOE_W { - FIFOE_W::new(self) + pub fn fifoe(&mut self) -> FIFOE_W { + FIFOE_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfifor(&mut self) -> RFIFOR_W { - RFIFOR_W::new(self) + pub fn rfifor(&mut self) -> RFIFOR_W { + RFIFOR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfifor(&mut self) -> XFIFOR_W { - XFIFOR_W::new(self) + pub fn xfifor(&mut self) -> XFIFOR_W { + XFIFOR_W::new(self, 2) } #[doc = "Bit 3 - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn dmam(&mut self) -> DMAM_W { - DMAM_W::new(self) + pub fn dmam(&mut self) -> DMAM_W { + DMAM_W::new(self, 3) } #[doc = "Bits 4:5 - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn tet(&mut self) -> TET_W { - TET_W::new(self) + pub fn tet(&mut self) -> TET_W { + TET_W::new(self, 4) } #[doc = "Bits 6:7 - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn rt(&mut self) -> RT_W { - RT_W::new(self) + pub fn rt(&mut self) -> RT_W { + RT_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/htx.rs b/jh7110-vf2-12a-pac/src/uart3/htx.rs index ad027bd..fc82325 100644 --- a/jh7110-vf2-12a-pac/src/uart3/htx.rs +++ b/jh7110-vf2-12a-pac/src/uart3/htx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `htx` reader - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] pub type HTX_R = crate::BitReader; #[doc = "Field `htx` writer - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] -pub type HTX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HTX_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] #[must_use] - pub fn htx(&mut self) -> HTX_W { - HTX_W::new(self) + pub fn htx(&mut self) -> HTX_W { + HTX_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/ier.rs b/jh7110-vf2-12a-pac/src/uart3/ier.rs index 006fbea..3cf3d7f 100644 --- a/jh7110-vf2-12a-pac/src/uart3/ier.rs +++ b/jh7110-vf2-12a-pac/src/uart3/ier.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `erbfi` reader - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] pub type ERBFI_R = crate::BitReader; #[doc = "Field `erbfi` writer - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] -pub type ERBFI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ERBFI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `etbei` reader - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] pub type ETBEI_R = crate::BitReader; #[doc = "Field `etbei` writer - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ETBEI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ETBEI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `elsi` reader - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] pub type ELSI_R = crate::BitReader; #[doc = "Field `elsi` writer - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ELSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ELSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `edssi` reader - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] pub type EDSSI_R = crate::BitReader; #[doc = "Field `edssi` writer - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] -pub type EDSSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EDSSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ptime` reader - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] pub type PTIME_R = crate::BitReader; #[doc = "Field `ptime` writer - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] -pub type PTIME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PTIME_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn erbfi(&mut self) -> ERBFI_W { - ERBFI_W::new(self) + pub fn erbfi(&mut self) -> ERBFI_W { + ERBFI_W::new(self, 0) } #[doc = "Bit 1 - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn etbei(&mut self) -> ETBEI_W { - ETBEI_W::new(self) + pub fn etbei(&mut self) -> ETBEI_W { + ETBEI_W::new(self, 1) } #[doc = "Bit 2 - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn elsi(&mut self) -> ELSI_W { - ELSI_W::new(self) + pub fn elsi(&mut self) -> ELSI_W { + ELSI_W::new(self, 2) } #[doc = "Bit 3 - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn edssi(&mut self) -> EDSSI_W { - EDSSI_W::new(self) + pub fn edssi(&mut self) -> EDSSI_W { + EDSSI_W::new(self, 3) } #[doc = "Bit 7 - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn ptime(&mut self) -> PTIME_W { - PTIME_W::new(self) + pub fn ptime(&mut self) -> PTIME_W { + PTIME_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/iir.rs b/jh7110-vf2-12a-pac/src/uart3/iir.rs index c90daa5..c949f03 100644 --- a/jh7110-vf2-12a-pac/src/uart3/iir.rs +++ b/jh7110-vf2-12a-pac/src/uart3/iir.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/lcr.rs b/jh7110-vf2-12a-pac/src/uart3/lcr.rs index acd83ee..3bc10c2 100644 --- a/jh7110-vf2-12a-pac/src/uart3/lcr.rs +++ b/jh7110-vf2-12a-pac/src/uart3/lcr.rs @@ -7,7 +7,7 @@ is zero), always readable. This is used to select the number of data bits per ch pub type DLS_R = crate::FieldReader; #[doc = "Field `dls` writer - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] -pub type DLS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DLS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `stop` reader - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] @@ -15,31 +15,31 @@ pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pen` reader - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] pub type PEN_R = crate::BitReader; #[doc = "Field `pen` writer - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] -pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `eps` reader - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] pub type EPS_R = crate::BitReader; #[doc = "Field `eps` writer - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] -pub type EPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EPS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bc` reader - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] pub type BC_R = crate::BitReader; #[doc = "Field `bc` writer - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] -pub type BC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dlab` reader - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] pub type DLAB_R = crate::BitReader; #[doc = "Field `dlab` writer - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] -pub type DLAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DLAB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:1 - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] @@ -84,46 +84,50 @@ impl W { is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] #[inline(always)] #[must_use] - pub fn dls(&mut self) -> DLS_W { - DLS_W::new(self) + pub fn dls(&mut self) -> DLS_W { + DLS_W::new(self, 0) } #[doc = "Bit 2 - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 2) } #[doc = "Bit 3 - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W { - PEN_W::new(self) + pub fn pen(&mut self) -> PEN_W { + PEN_W::new(self, 3) } #[doc = "Bit 4 - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] #[inline(always)] #[must_use] - pub fn eps(&mut self) -> EPS_W { - EPS_W::new(self) + pub fn eps(&mut self) -> EPS_W { + EPS_W::new(self, 4) } #[doc = "Bit 6 - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] #[inline(always)] #[must_use] - pub fn bc(&mut self) -> BC_W { - BC_W::new(self) + pub fn bc(&mut self) -> BC_W { + BC_W::new(self, 6) } #[doc = "Bit 7 - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] #[inline(always)] #[must_use] - pub fn dlab(&mut self) -> DLAB_W { - DLAB_W::new(self) + pub fn dlab(&mut self) -> DLAB_W { + DLAB_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/lpdlh.rs b/jh7110-vf2-12a-pac/src/uart3/lpdlh.rs index 8a910c8..095afa9 100644 --- a/jh7110-vf2-12a-pac/src/uart3/lpdlh.rs +++ b/jh7110-vf2-12a-pac/src/uart3/lpdlh.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdlh` reader - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] pub type LPDLH_R = crate::FieldReader; #[doc = "Field `lpdlh` writer - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] -pub type LPDLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] #[must_use] - pub fn lpdlh(&mut self) -> LPDLH_W { - LPDLH_W::new(self) + pub fn lpdlh(&mut self) -> LPDLH_W { + LPDLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/lpdll.rs b/jh7110-vf2-12a-pac/src/uart3/lpdll.rs index 7780651..21d0018 100644 --- a/jh7110-vf2-12a-pac/src/uart3/lpdll.rs +++ b/jh7110-vf2-12a-pac/src/uart3/lpdll.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdll` reader - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] pub type LPDLL_R = crate::FieldReader; #[doc = "Field `lpdll` writer - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type LPDLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn lpdll(&mut self) -> LPDLL_W { - LPDLL_W::new(self) + pub fn lpdll(&mut self) -> LPDLL_W { + LPDLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/lsr.rs b/jh7110-vf2-12a-pac/src/uart3/lsr.rs index f576c10..ff2ab48 100644 --- a/jh7110-vf2-12a-pac/src/uart3/lsr.rs +++ b/jh7110-vf2-12a-pac/src/uart3/lsr.rs @@ -73,7 +73,11 @@ set to one). This is used to indicate if there is at least one parity error, fra } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/mcr.rs b/jh7110-vf2-12a-pac/src/uart3/mcr.rs index 6932ee7..9c93108 100644 --- a/jh7110-vf2-12a-pac/src/uart3/mcr.rs +++ b/jh7110-vf2-12a-pac/src/uart3/mcr.rs @@ -7,7 +7,7 @@ set to one), the dtr_n output is held inactive high while the value of this loca pub type DTR_R = crate::BitReader; #[doc = "Field `dtr` writer - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type DTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rts` reader - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR\\[5\\] @@ -23,19 +23,19 @@ set to one) and FIFOs enable (FCR\\[0\\] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR\\[1\\] is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out1` reader - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT1_R = crate::BitReader; #[doc = "Field `out1` writer - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out2` reader - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT2_R = crate::BitReader; #[doc = "Field `out2` writer - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `lb` reader - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] @@ -43,15 +43,15 @@ pub type LB_R = crate::BitReader; #[doc = "Field `lb` writer - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] -pub type LB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `afce` reader - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] pub type AFCE_R = crate::BitReader; #[doc = "Field `afce` writer - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] -pub type AFCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AFCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sire` reader - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] pub type SIRE_R = crate::BitReader; #[doc = "Field `sire` writer - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] -pub type SIRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SIRE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] @@ -105,8 +105,8 @@ impl W { set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn dtr(&mut self) -> DTR_W { - DTR_W::new(self) + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 0) } #[doc = "Bit 1 - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] @@ -117,44 +117,48 @@ is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W { - RTS_W::new(self) + pub fn rts(&mut self) -> RTS_W { + RTS_W::new(self, 1) } #[doc = "Bit 2 - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out1(&mut self) -> OUT1_W { - OUT1_W::new(self) + pub fn out1(&mut self) -> OUT1_W { + OUT1_W::new(self, 2) } #[doc = "Bit 3 - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out2(&mut self) -> OUT2_W { - OUT2_W::new(self) + pub fn out2(&mut self) -> OUT2_W { + OUT2_W::new(self, 3) } #[doc = "Bit 4 - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] #[inline(always)] #[must_use] - pub fn lb(&mut self) -> LB_W { - LB_W::new(self) + pub fn lb(&mut self) -> LB_W { + LB_W::new(self, 4) } #[doc = "Bit 5 - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] #[inline(always)] #[must_use] - pub fn afce(&mut self) -> AFCE_W { - AFCE_W::new(self) + pub fn afce(&mut self) -> AFCE_W { + AFCE_W::new(self, 5) } #[doc = "Bit 6 - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] #[inline(always)] #[must_use] - pub fn sire(&mut self) -> SIRE_W { - SIRE_W::new(self) + pub fn sire(&mut self) -> SIRE_W { + SIRE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/msr.rs b/jh7110-vf2-12a-pac/src/uart3/msr.rs index 65c526b..b54fc38 100644 --- a/jh7110-vf2-12a-pac/src/uart3/msr.rs +++ b/jh7110-vf2-12a-pac/src/uart3/msr.rs @@ -93,7 +93,11 @@ set to one), DCD is the same as MCR\\[3\\] } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/rbr.rs b/jh7110-vf2-12a-pac/src/uart3/rbr.rs index 03003ed..403adcf 100644 --- a/jh7110-vf2-12a-pac/src/uart3/rbr.rs +++ b/jh7110-vf2-12a-pac/src/uart3/rbr.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/rfl.rs b/jh7110-vf2-12a-pac/src/uart3/rfl.rs index 2aea928..59355cb 100644 --- a/jh7110-vf2-12a-pac/src/uart3/rfl.rs +++ b/jh7110-vf2-12a-pac/src/uart3/rfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/rfw.rs b/jh7110-vf2-12a-pac/src/uart3/rfw.rs index 7b917de..490472d 100644 --- a/jh7110-vf2-12a-pac/src/uart3/rfw.rs +++ b/jh7110-vf2-12a-pac/src/uart3/rfw.rs @@ -4,36 +4,40 @@ pub type R = crate::R; pub type W = crate::W; #[doc = "Field `rfwd` writer - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] -pub type RFWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type RFWD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `rfpe` writer - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] -pub type RFPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFPE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rffe` writer - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] -pub type RFFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bits 0:7 - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] #[inline(always)] #[must_use] - pub fn rfwd(&mut self) -> RFWD_W { - RFWD_W::new(self) + pub fn rfwd(&mut self) -> RFWD_W { + RFWD_W::new(self, 0) } #[doc = "Bit 8 - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rfpe(&mut self) -> RFPE_W { - RFPE_W::new(self) + pub fn rfpe(&mut self) -> RFPE_W { + RFPE_W::new(self, 8) } #[doc = "Bit 9 - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rffe(&mut self) -> RFFE_W { - RFFE_W::new(self) + pub fn rffe(&mut self) -> RFFE_W { + RFFE_W::new(self, 9) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sbcr.rs b/jh7110-vf2-12a-pac/src/uart3/sbcr.rs index 73914e9..5a120c0 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sbcr.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sbcr.rs @@ -7,7 +7,7 @@ pub type W = crate::W; pub type SBCR_R = crate::BitReader; #[doc = "Field `sbcr` writer - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] -pub type SBCR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SBCR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] @@ -21,10 +21,14 @@ impl W { = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] #[inline(always)] #[must_use] - pub fn sbcr(&mut self) -> SBCR_W { - SBCR_W::new(self) + pub fn sbcr(&mut self) -> SBCR_W { + SBCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/scr.rs b/jh7110-vf2-12a-pac/src/uart3/scr.rs index 744352e..f46ba21 100644 --- a/jh7110-vf2-12a-pac/src/uart3/scr.rs +++ b/jh7110-vf2-12a-pac/src/uart3/scr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `scr` reader - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sdmam.rs b/jh7110-vf2-12a-pac/src/uart3/sdmam.rs index 684377c..4be4fa2 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sdmam.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sdmam.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sdmam` reader - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] pub type SDMAM_R = crate::BitReader; #[doc = "Field `sdmam` writer - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] -pub type SDMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SDMAM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn sdmam(&mut self) -> SDMAM_W { - SDMAM_W::new(self) + pub fn sdmam(&mut self) -> SDMAM_W { + SDMAM_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sfe.rs b/jh7110-vf2-12a-pac/src/uart3/sfe.rs index e68b088..ed26fee 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sfe.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sfe.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sfe` reader - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] pub type SFE_R = crate::BitReader; #[doc = "Field `sfe` writer - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] -pub type SFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] #[must_use] - pub fn sfe(&mut self) -> SFE_W { - SFE_W::new(self) + pub fn sfe(&mut self) -> SFE_W { + SFE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srbr0.rs b/jh7110-vf2-12a-pac/src/uart3/srbr0.rs index 4076661..4e44d1a 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srbr0.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srbr0.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srbr1.rs b/jh7110-vf2-12a-pac/src/uart3/srbr1.rs index 2f31b75..46bc479 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srbr1.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srbr1.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srbr10.rs b/jh7110-vf2-12a-pac/src/uart3/srbr10.rs index 3639d65..70297bf 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srbr10.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srbr10.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srbr11.rs b/jh7110-vf2-12a-pac/src/uart3/srbr11.rs index 92d29b1..28d0277 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srbr11.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srbr11.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srbr12.rs b/jh7110-vf2-12a-pac/src/uart3/srbr12.rs index 52e795e..3eccd9a 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srbr12.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srbr12.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srbr13.rs b/jh7110-vf2-12a-pac/src/uart3/srbr13.rs index 50aae40..e47e4e4 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srbr13.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srbr13.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srbr14.rs b/jh7110-vf2-12a-pac/src/uart3/srbr14.rs index cb25819..8f23662 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srbr14.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srbr14.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srbr15.rs b/jh7110-vf2-12a-pac/src/uart3/srbr15.rs index b25ae46..1dac092 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srbr15.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srbr15.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srbr2.rs b/jh7110-vf2-12a-pac/src/uart3/srbr2.rs index 9f3236c..afb0617 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srbr2.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srbr2.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srbr3.rs b/jh7110-vf2-12a-pac/src/uart3/srbr3.rs index 5c1edda..0ff3650 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srbr3.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srbr3.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srbr4.rs b/jh7110-vf2-12a-pac/src/uart3/srbr4.rs index e6bee93..59560c4 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srbr4.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srbr4.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srbr5.rs b/jh7110-vf2-12a-pac/src/uart3/srbr5.rs index e599009..763e341 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srbr5.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srbr5.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srbr6.rs b/jh7110-vf2-12a-pac/src/uart3/srbr6.rs index b0155b3..78e2a40 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srbr6.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srbr6.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srbr7.rs b/jh7110-vf2-12a-pac/src/uart3/srbr7.rs index b8f9b88..0723ff0 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srbr7.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srbr7.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srbr8.rs b/jh7110-vf2-12a-pac/src/uart3/srbr8.rs index f57b044..4702cd9 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srbr8.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srbr8.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srbr9.rs b/jh7110-vf2-12a-pac/src/uart3/srbr9.rs index 3a160aa..e1a262e 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srbr9.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srbr9.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srr.rs b/jh7110-vf2-12a-pac/src/uart3/srr.rs index 6671199..fdb0c0a 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srr.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srr.rs @@ -3,31 +3,35 @@ pub type R = crate::R; #[doc = "Register `srr` writer"] pub type W = crate::W; #[doc = "Field `ur` writer - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] -pub type UR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type UR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfr` writer - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfr` writer - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFR_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] #[inline(always)] #[must_use] - pub fn ur(&mut self) -> UR_W { - UR_W::new(self) + pub fn ur(&mut self) -> UR_W { + UR_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfr(&mut self) -> RFR_W { - RFR_W::new(self) + pub fn rfr(&mut self) -> RFR_W { + RFR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfr(&mut self) -> XFR_W { - XFR_W::new(self) + pub fn xfr(&mut self) -> XFR_W { + XFR_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srt.rs b/jh7110-vf2-12a-pac/src/uart3/srt.rs index fed4f1f..da909fd 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srt.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `srt` reader - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] pub type SRT_R = crate::FieldReader; #[doc = "Field `srt` writer - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type SRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SRT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn srt(&mut self) -> SRT_W { - SRT_W::new(self) + pub fn srt(&mut self) -> SRT_W { + SRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/srts.rs b/jh7110-vf2-12a-pac/src/uart3/srts.rs index ceb0ee4..cf1e2a9 100644 --- a/jh7110-vf2-12a-pac/src/uart3/srts.rs +++ b/jh7110-vf2-12a-pac/src/uart3/srts.rs @@ -15,7 +15,7 @@ pub type SRTS_R = crate::BitReader; = 1) and FIFOs enable (FCR\\[0\\] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR\\[4\\] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] -pub type SRTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SRTS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Request to Send. This is a shadow register for the RTS bit (MCR\\[1\\]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] = 0), the rts_n signal is set low by programming MCR\\[1\\] @@ -37,10 +37,14 @@ impl W { = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn srts(&mut self) -> SRTS_W { - SRTS_W::new(self) + pub fn srts(&mut self) -> SRTS_W { + SRTS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/stet.rs b/jh7110-vf2-12a-pac/src/uart3/stet.rs index acb8ba1..503dc8a 100644 --- a/jh7110-vf2-12a-pac/src/uart3/stet.rs +++ b/jh7110-vf2-12a-pac/src/uart3/stet.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `stet` reader - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] pub type STET_R = crate::FieldReader; #[doc = "Field `stet` writer - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type STET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type STET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn stet(&mut self) -> STET_W { - STET_W::new(self) + pub fn stet(&mut self) -> STET_W { + STET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sthr0.rs b/jh7110-vf2-12a-pac/src/uart3/sthr0.rs index bfd277a..764ff05 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sthr0.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sthr0.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sthr1.rs b/jh7110-vf2-12a-pac/src/uart3/sthr1.rs index cc79733..5d58855 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sthr1.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sthr1.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sthr10.rs b/jh7110-vf2-12a-pac/src/uart3/sthr10.rs index be2659d..ffc38ff 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sthr10.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sthr10.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sthr11.rs b/jh7110-vf2-12a-pac/src/uart3/sthr11.rs index 8613dd5..1f8147f 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sthr11.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sthr11.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sthr12.rs b/jh7110-vf2-12a-pac/src/uart3/sthr12.rs index b354b10..7d816f3 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sthr12.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sthr12.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sthr13.rs b/jh7110-vf2-12a-pac/src/uart3/sthr13.rs index 06df4bc..9283b6a 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sthr13.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sthr13.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sthr14.rs b/jh7110-vf2-12a-pac/src/uart3/sthr14.rs index e181dd0..2daf622 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sthr14.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sthr14.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sthr15.rs b/jh7110-vf2-12a-pac/src/uart3/sthr15.rs index 4825778..f70715e 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sthr15.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sthr15.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sthr2.rs b/jh7110-vf2-12a-pac/src/uart3/sthr2.rs index d390f10..f1a9c77 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sthr2.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sthr2.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sthr3.rs b/jh7110-vf2-12a-pac/src/uart3/sthr3.rs index a74fdf0..06aab9e 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sthr3.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sthr3.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sthr4.rs b/jh7110-vf2-12a-pac/src/uart3/sthr4.rs index 1ee6b87..f6e7944 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sthr4.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sthr4.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sthr5.rs b/jh7110-vf2-12a-pac/src/uart3/sthr5.rs index ca360fe..7873a53 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sthr5.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sthr5.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sthr6.rs b/jh7110-vf2-12a-pac/src/uart3/sthr6.rs index 18e6fac..87c81df 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sthr6.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sthr6.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sthr7.rs b/jh7110-vf2-12a-pac/src/uart3/sthr7.rs index 27072a3..9928b3d 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sthr7.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sthr7.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sthr8.rs b/jh7110-vf2-12a-pac/src/uart3/sthr8.rs index 15060b8..565cb1d 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sthr8.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sthr8.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/sthr9.rs b/jh7110-vf2-12a-pac/src/uart3/sthr9.rs index 58af642..e64fece 100644 --- a/jh7110-vf2-12a-pac/src/uart3/sthr9.rs +++ b/jh7110-vf2-12a-pac/src/uart3/sthr9.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/tfl.rs b/jh7110-vf2-12a-pac/src/uart3/tfl.rs index e1faba6..db09fe3 100644 --- a/jh7110-vf2-12a-pac/src/uart3/tfl.rs +++ b/jh7110-vf2-12a-pac/src/uart3/tfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/tfr.rs b/jh7110-vf2-12a-pac/src/uart3/tfr.rs index 8e9ad91..714deff 100644 --- a/jh7110-vf2-12a-pac/src/uart3/tfr.rs +++ b/jh7110-vf2-12a-pac/src/uart3/tfr.rs @@ -14,7 +14,11 @@ is set to one). When FIFOs are implemented and enabled, reading this register gi } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/thr.rs b/jh7110-vf2-12a-pac/src/uart3/thr.rs index f910bd8..7845232 100644 --- a/jh7110-vf2-12a-pac/src/uart3/thr.rs +++ b/jh7110-vf2-12a-pac/src/uart3/thr.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `thr` writer - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type THR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type THR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn thr(&mut self) -> THR_W { - THR_W::new(self) + pub fn thr(&mut self) -> THR_W { + THR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/ucv.rs b/jh7110-vf2-12a-pac/src/uart3/ucv.rs index 8a3be91..6497a08 100644 --- a/jh7110-vf2-12a-pac/src/uart3/ucv.rs +++ b/jh7110-vf2-12a-pac/src/uart3/ucv.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart3/usr.rs b/jh7110-vf2-12a-pac/src/uart3/usr.rs index 445a085..b96417d 100644 --- a/jh7110-vf2-12a-pac/src/uart3/usr.rs +++ b/jh7110-vf2-12a-pac/src/uart3/usr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4.rs b/jh7110-vf2-12a-pac/src/uart4.rs index c462fbf..8a5f089 100644 --- a/jh7110-vf2-12a-pac/src/uart4.rs +++ b/jh7110-vf2-12a-pac/src/uart4.rs @@ -4,20 +4,13 @@ pub struct RegisterBlock { _reserved_0_dll: [u8; 0x04], _reserved_1_dlh: [u8; 0x04], _reserved_2_fcr: [u8; 0x04], - #[doc = "0x0c - Line Control Register"] - pub lcr: LCR, - #[doc = "0x10 - Modem Control Register"] - pub mcr: MCR, - #[doc = "0x14 - Line Status Register"] - pub lsr: LSR, - #[doc = "0x18 - Line Status Register"] - pub msr: MSR, - #[doc = "0x1c - Scratch Pad Register"] - pub scr: SCR, - #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdll: LPDLL, - #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdlh: LPDLH, + lcr: LCR, + mcr: MCR, + lsr: LSR, + msr: MSR, + scr: SCR, + lpdll: LPDLL, + lpdlh: LPDLH, _reserved10: [u8; 0x08], _reserved_10_srbr0: [u8; 0x04], _reserved_11_srbr1: [u8; 0x04], @@ -35,564 +28,663 @@ pub struct RegisterBlock { _reserved_23_srbr13: [u8; 0x04], _reserved_24_srbr14: [u8; 0x04], _reserved_25_srbr15: [u8; 0x04], - #[doc = "0x70 - FIFO Access Register"] - pub far: FAR, - #[doc = "0x74 - Transmit FIFO Read"] - pub tfr: TFR, - #[doc = "0x78 - Receive FIFO Write"] - pub rfw: RFW, - #[doc = "0x7c - UART Status Register"] - pub usr: USR, - #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub tfl: TFL, - #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub rfl: RFL, - #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srr: SRR, - #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srts: SRTS, - #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sbcr: SBCR, - #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sdmam: SDMAM, - #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sfe: SFE, - #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srt: SRT, - #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub stet: STET, - #[doc = "0xa4 - Halt TX"] - pub htx: HTX, - #[doc = "0xa8 - DMA Software Acknowledge"] - pub dmasa: DMASA, + far: FAR, + tfr: TFR, + rfw: RFW, + usr: USR, + tfl: TFL, + rfl: RFL, + srr: SRR, + srts: SRTS, + sbcr: SBCR, + sdmam: SDMAM, + sfe: SFE, + srt: SRT, + stet: STET, + htx: HTX, + dmasa: DMASA, _reserved41: [u8; 0x48], - #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] - pub cpr: CPR, + cpr: CPR, _reserved_42_ctr: [u8; 0x04], } impl RegisterBlock { #[doc = "0x00 - Divisor Latch Low"] #[inline(always)] pub const fn dll(&self) -> &DLL { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Transmit Holding Register"] #[inline(always)] pub const fn thr(&self) -> &THR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Receive Buffer Register"] #[inline(always)] pub const fn rbr(&self) -> &RBR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x04 - Interrupt Enable Register"] #[inline(always)] pub const fn ier(&self) -> &IER { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x04 - Divisor Latch High"] #[inline(always)] pub const fn dlh(&self) -> &DLH { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x08 - FIFO Control Register"] #[inline(always)] pub const fn fcr(&self) -> &FCR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } } #[doc = "0x08 - Interrupt Identity Register"] #[inline(always)] pub const fn iir(&self) -> &IIR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } + } + #[doc = "0x0c - Line Control Register"] + #[inline(always)] + pub const fn lcr(&self) -> &LCR { + &self.lcr + } + #[doc = "0x10 - Modem Control Register"] + #[inline(always)] + pub const fn mcr(&self) -> &MCR { + &self.mcr + } + #[doc = "0x14 - Line Status Register"] + #[inline(always)] + pub const fn lsr(&self) -> &LSR { + &self.lsr + } + #[doc = "0x18 - Line Status Register"] + #[inline(always)] + pub const fn msr(&self) -> &MSR { + &self.msr + } + #[doc = "0x1c - Scratch Pad Register"] + #[inline(always)] + pub const fn scr(&self) -> &SCR { + &self.scr + } + #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdll(&self) -> &LPDLL { + &self.lpdll + } + #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdlh(&self) -> &LPDLH { + &self.lpdlh } #[doc = "0x30 - Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr0(&self) -> &STHR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x30 - Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr0(&self) -> &SRBR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x34 - Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr1(&self) -> &STHR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x34 - Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr1(&self) -> &SRBR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x38 - Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr2(&self) -> &STHR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x38 - Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr2(&self) -> &SRBR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x3c - Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr3(&self) -> &STHR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x3c - Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr3(&self) -> &SRBR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x40 - Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr4(&self) -> &STHR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x40 - Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr4(&self) -> &SRBR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x44 - Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr5(&self) -> &STHR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x44 - Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr5(&self) -> &SRBR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x48 - Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr6(&self) -> &STHR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x48 - Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr6(&self) -> &SRBR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x4c - Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr7(&self) -> &STHR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x4c - Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr7(&self) -> &SRBR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x50 - Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr8(&self) -> &STHR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x50 - Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr8(&self) -> &SRBR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x54 - Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr9(&self) -> &STHR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x54 - Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr9(&self) -> &SRBR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x58 - Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr10(&self) -> &STHR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x58 - Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr10(&self) -> &SRBR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x5c - Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr11(&self) -> &STHR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x5c - Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr11(&self) -> &SRBR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x60 - Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr12(&self) -> &STHR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x60 - Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr12(&self) -> &SRBR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x64 - Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr13(&self) -> &STHR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x64 - Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr13(&self) -> &SRBR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x68 - Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr14(&self) -> &STHR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x68 - Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr14(&self) -> &SRBR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x6c - Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr15(&self) -> &STHR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } } #[doc = "0x6c - Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr15(&self) -> &SRBR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } + } + #[doc = "0x70 - FIFO Access Register"] + #[inline(always)] + pub const fn far(&self) -> &FAR { + &self.far + } + #[doc = "0x74 - Transmit FIFO Read"] + #[inline(always)] + pub const fn tfr(&self) -> &TFR { + &self.tfr + } + #[doc = "0x78 - Receive FIFO Write"] + #[inline(always)] + pub const fn rfw(&self) -> &RFW { + &self.rfw + } + #[doc = "0x7c - UART Status Register"] + #[inline(always)] + pub const fn usr(&self) -> &USR { + &self.usr + } + #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn tfl(&self) -> &TFL { + &self.tfl + } + #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn rfl(&self) -> &RFL { + &self.rfl + } + #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srr(&self) -> &SRR { + &self.srr + } + #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srts(&self) -> &SRTS { + &self.srts + } + #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sbcr(&self) -> &SBCR { + &self.sbcr + } + #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sdmam(&self) -> &SDMAM { + &self.sdmam + } + #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sfe(&self) -> &SFE { + &self.sfe + } + #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srt(&self) -> &SRT { + &self.srt + } + #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn stet(&self) -> &STET { + &self.stet + } + #[doc = "0xa4 - Halt TX"] + #[inline(always)] + pub const fn htx(&self) -> &HTX { + &self.htx + } + #[doc = "0xa8 - DMA Software Acknowledge"] + #[inline(always)] + pub const fn dmasa(&self) -> &DMASA { + &self.dmasa + } + #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn cpr(&self) -> &CPR { + &self.cpr } #[doc = "0xf8 - Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ctr(&self) -> &CTR { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } #[doc = "0xf8 - UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ucv(&self) -> &UCV { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } } -#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rbr`] +#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbr`] module"] pub type RBR = crate::Reg; #[doc = "Receive Buffer Register"] pub mod rbr; -#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`thr`] +#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thr`] module"] pub type THR = crate::Reg; #[doc = "Transmit Holding Register"] pub mod thr; -#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dll`] +#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll`] module"] pub type DLL = crate::Reg; #[doc = "Divisor Latch Low"] pub mod dll; -#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dlh`] +#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlh`] module"] pub type DLH = crate::Reg; #[doc = "Divisor Latch High"] pub mod dlh; -#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`iir`] +#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] module"] pub type IIR = crate::Reg; #[doc = "Interrupt Identity Register"] pub mod iir; -#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fcr`] +#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"] pub type FCR = crate::Reg; #[doc = "FIFO Control Register"] pub mod fcr; -#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lcr`] +#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] module"] pub type LCR = crate::Reg; #[doc = "Line Control Register"] pub mod lcr; -#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mcr`] +#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] pub type MCR = crate::Reg; #[doc = "Modem Control Register"] pub mod mcr; -#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lsr`] +#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] module"] pub type LSR = crate::Reg; #[doc = "Line Status Register"] pub mod lsr; -#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msr`] +#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"] pub type MSR = crate::Reg; #[doc = "Line Status Register"] pub mod msr; -#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scr`] +#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`] module"] pub type SCR = crate::Reg; #[doc = "Scratch Pad Register"] pub mod scr; -#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdll`] +#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdll`] module"] pub type LPDLL = crate::Reg; #[doc = "Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdll; -#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdlh`] +#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdlh`] module"] pub type LPDLH = crate::Reg; #[doc = "Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdlh; -#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr0`] +#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr0`] module"] pub type SRBR0 = crate::Reg; #[doc = "Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr0; -#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr0`] +#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr0`] module"] pub type STHR0 = crate::Reg; #[doc = "Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr0; -#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr1`] +#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr1`] module"] pub type SRBR1 = crate::Reg; #[doc = "Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr1; -#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr1`] +#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr1`] module"] pub type STHR1 = crate::Reg; #[doc = "Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr1; -#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr2`] +#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr2`] module"] pub type SRBR2 = crate::Reg; #[doc = "Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr2; -#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr2`] +#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr2`] module"] pub type STHR2 = crate::Reg; #[doc = "Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr2; -#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr3`] +#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr3`] module"] pub type SRBR3 = crate::Reg; #[doc = "Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr3; -#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr3`] +#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr3`] module"] pub type STHR3 = crate::Reg; #[doc = "Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr3; -#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr4`] +#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr4`] module"] pub type SRBR4 = crate::Reg; #[doc = "Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr4; -#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr4`] +#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr4`] module"] pub type STHR4 = crate::Reg; #[doc = "Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr4; -#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr5`] +#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr5`] module"] pub type SRBR5 = crate::Reg; #[doc = "Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr5; -#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr5`] +#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr5`] module"] pub type STHR5 = crate::Reg; #[doc = "Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr5; -#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr6`] +#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr6`] module"] pub type SRBR6 = crate::Reg; #[doc = "Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr6; -#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr6`] +#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr6`] module"] pub type STHR6 = crate::Reg; #[doc = "Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr6; -#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr7`] +#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr7`] module"] pub type SRBR7 = crate::Reg; #[doc = "Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr7; -#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr7`] +#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr7`] module"] pub type STHR7 = crate::Reg; #[doc = "Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr7; -#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr8`] +#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr8`] module"] pub type SRBR8 = crate::Reg; #[doc = "Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr8; -#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr8`] +#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr8`] module"] pub type STHR8 = crate::Reg; #[doc = "Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr8; -#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr9`] +#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr9`] module"] pub type SRBR9 = crate::Reg; #[doc = "Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr9; -#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr9`] +#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr9`] module"] pub type STHR9 = crate::Reg; #[doc = "Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr9; -#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr10`] +#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr10`] module"] pub type SRBR10 = crate::Reg; #[doc = "Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr10; -#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr10`] +#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr10`] module"] pub type STHR10 = crate::Reg; #[doc = "Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr10; -#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr11`] +#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr11`] module"] pub type SRBR11 = crate::Reg; #[doc = "Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr11; -#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr11`] +#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr11`] module"] pub type STHR11 = crate::Reg; #[doc = "Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr11; -#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr12`] +#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr12`] module"] pub type SRBR12 = crate::Reg; #[doc = "Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr12; -#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr12`] +#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr12`] module"] pub type STHR12 = crate::Reg; #[doc = "Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr12; -#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr13`] +#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr13`] module"] pub type SRBR13 = crate::Reg; #[doc = "Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr13; -#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr13`] +#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr13`] module"] pub type STHR13 = crate::Reg; #[doc = "Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr13; -#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr14`] +#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr14`] module"] pub type SRBR14 = crate::Reg; #[doc = "Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr14; -#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr14`] +#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr14`] module"] pub type STHR14 = crate::Reg; #[doc = "Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr14; -#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr15`] +#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr15`] module"] pub type SRBR15 = crate::Reg; #[doc = "Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr15; -#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr15`] +#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr15`] module"] pub type STHR15 = crate::Reg; #[doc = "Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr15; -#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`far`] +#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@far`] module"] pub type FAR = crate::Reg; #[doc = "FIFO Access Register"] pub mod far; -#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfr`] +#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfr`] module"] pub type TFR = crate::Reg; #[doc = "Transmit FIFO Read"] pub mod tfr; -#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfw`] +#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfw`] module"] pub type RFW = crate::Reg; #[doc = "Receive FIFO Write"] pub mod rfw; -#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`usr`] +#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usr`] module"] pub type USR = crate::Reg; #[doc = "UART Status Register"] pub mod usr; -#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfl`] +#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfl`] module"] pub type TFL = crate::Reg; #[doc = "Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod tfl; -#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfl`] +#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfl`] module"] pub type RFL = crate::Reg; #[doc = "Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod rfl; -#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srr`] +#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srr`] module"] pub type SRR = crate::Reg; #[doc = "Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srr; -#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srts`] +#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srts`] module"] pub type SRTS = crate::Reg; #[doc = "Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srts; -#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sbcr`] +#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sbcr`] module"] pub type SBCR = crate::Reg; #[doc = "Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sbcr; -#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sdmam`] +#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdmam`] module"] pub type SDMAM = crate::Reg; #[doc = "Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sdmam; -#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sfe`] +#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfe`] module"] pub type SFE = crate::Reg; #[doc = "Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sfe; -#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srt`] +#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srt`] module"] pub type SRT = crate::Reg; #[doc = "Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srt; -#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stet`] +#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stet`] module"] pub type STET = crate::Reg; #[doc = "Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod stet; -#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`htx`] +#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@htx`] module"] pub type HTX = crate::Reg; #[doc = "Halt TX"] pub mod htx; -#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dmasa`] +#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasa`] module"] pub type DMASA = crate::Reg; #[doc = "DMA Software Acknowledge"] pub mod dmasa; -#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cpr`] +#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpr`] module"] pub type CPR = crate::Reg; #[doc = "Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] pub mod cpr; -#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ucv`] +#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucv`] module"] pub type UCV = crate::Reg; #[doc = "UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] pub mod ucv; -#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctr`] +#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"] pub type CTR = crate::Reg; #[doc = "Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] diff --git a/jh7110-vf2-12a-pac/src/uart4/cpr.rs b/jh7110-vf2-12a-pac/src/uart4/cpr.rs index 4807519..332b584 100644 --- a/jh7110-vf2-12a-pac/src/uart4/cpr.rs +++ b/jh7110-vf2-12a-pac/src/uart4/cpr.rs @@ -89,7 +89,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/ctr.rs b/jh7110-vf2-12a-pac/src/uart4/ctr.rs index c3760d5..ac70194 100644 --- a/jh7110-vf2-12a-pac/src/uart4/ctr.rs +++ b/jh7110-vf2-12a-pac/src/uart4/ctr.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/dlh.rs b/jh7110-vf2-12a-pac/src/uart4/dlh.rs index 3257a2d..2a788c1 100644 --- a/jh7110-vf2-12a-pac/src/uart4/dlh.rs +++ b/jh7110-vf2-12a-pac/src/uart4/dlh.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLH_R = crate::FieldReader; #[doc = "Field `dlh` writer - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dlh(&mut self) -> DLH_W { - DLH_W::new(self) + pub fn dlh(&mut self) -> DLH_W { + DLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/dll.rs b/jh7110-vf2-12a-pac/src/uart4/dll.rs index 9c9daff..1c9d765 100644 --- a/jh7110-vf2-12a-pac/src/uart4/dll.rs +++ b/jh7110-vf2-12a-pac/src/uart4/dll.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLL_R = crate::FieldReader; #[doc = "Field `dll` writer - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dll(&mut self) -> DLL_W { - DLL_W::new(self) + pub fn dll(&mut self) -> DLL_W { + DLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/dmasa.rs b/jh7110-vf2-12a-pac/src/uart4/dmasa.rs index 7bcfb26..2fc4e6d 100644 --- a/jh7110-vf2-12a-pac/src/uart4/dmasa.rs +++ b/jh7110-vf2-12a-pac/src/uart4/dmasa.rs @@ -3,15 +3,19 @@ pub type R = crate::R; #[doc = "Register `dmasa` writer"] pub type W = crate::W; #[doc = "Field `dmasa` writer - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type DMASA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMASA_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn dmasa(&mut self) -> DMASA_W { - DMASA_W::new(self) + pub fn dmasa(&mut self) -> DMASA_W { + DMASA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/far.rs b/jh7110-vf2-12a-pac/src/uart4/far.rs index 3b3bcb1..d52059a 100644 --- a/jh7110-vf2-12a-pac/src/uart4/far.rs +++ b/jh7110-vf2-12a-pac/src/uart4/far.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `far` reader - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] pub type FAR_R = crate::BitReader; #[doc = "Field `far` writer - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] -pub type FAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FAR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] #[must_use] - pub fn far(&mut self) -> FAR_W { - FAR_W::new(self) + pub fn far(&mut self) -> FAR_W { + FAR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/fcr.rs b/jh7110-vf2-12a-pac/src/uart4/fcr.rs index 4fbb499..a64a60b 100644 --- a/jh7110-vf2-12a-pac/src/uart4/fcr.rs +++ b/jh7110-vf2-12a-pac/src/uart4/fcr.rs @@ -3,55 +3,59 @@ pub type R = crate::R; #[doc = "Register `fcr` writer"] pub type W = crate::W; #[doc = "Field `fifoe` writer - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] -pub type FIFOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIFOE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfifor` writer - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfifor` writer - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dmam` writer - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] -pub type DMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMAM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tet` writer - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type TET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `rt` writer - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type RT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type RT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl W { #[doc = "Bit 0 - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] #[inline(always)] #[must_use] - pub fn fifoe(&mut self) -> FIFOE_W { - FIFOE_W::new(self) + pub fn fifoe(&mut self) -> FIFOE_W { + FIFOE_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfifor(&mut self) -> RFIFOR_W { - RFIFOR_W::new(self) + pub fn rfifor(&mut self) -> RFIFOR_W { + RFIFOR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfifor(&mut self) -> XFIFOR_W { - XFIFOR_W::new(self) + pub fn xfifor(&mut self) -> XFIFOR_W { + XFIFOR_W::new(self, 2) } #[doc = "Bit 3 - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn dmam(&mut self) -> DMAM_W { - DMAM_W::new(self) + pub fn dmam(&mut self) -> DMAM_W { + DMAM_W::new(self, 3) } #[doc = "Bits 4:5 - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn tet(&mut self) -> TET_W { - TET_W::new(self) + pub fn tet(&mut self) -> TET_W { + TET_W::new(self, 4) } #[doc = "Bits 6:7 - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn rt(&mut self) -> RT_W { - RT_W::new(self) + pub fn rt(&mut self) -> RT_W { + RT_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/htx.rs b/jh7110-vf2-12a-pac/src/uart4/htx.rs index ad027bd..fc82325 100644 --- a/jh7110-vf2-12a-pac/src/uart4/htx.rs +++ b/jh7110-vf2-12a-pac/src/uart4/htx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `htx` reader - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] pub type HTX_R = crate::BitReader; #[doc = "Field `htx` writer - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] -pub type HTX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HTX_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] #[must_use] - pub fn htx(&mut self) -> HTX_W { - HTX_W::new(self) + pub fn htx(&mut self) -> HTX_W { + HTX_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/ier.rs b/jh7110-vf2-12a-pac/src/uart4/ier.rs index 006fbea..3cf3d7f 100644 --- a/jh7110-vf2-12a-pac/src/uart4/ier.rs +++ b/jh7110-vf2-12a-pac/src/uart4/ier.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `erbfi` reader - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] pub type ERBFI_R = crate::BitReader; #[doc = "Field `erbfi` writer - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] -pub type ERBFI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ERBFI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `etbei` reader - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] pub type ETBEI_R = crate::BitReader; #[doc = "Field `etbei` writer - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ETBEI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ETBEI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `elsi` reader - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] pub type ELSI_R = crate::BitReader; #[doc = "Field `elsi` writer - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ELSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ELSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `edssi` reader - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] pub type EDSSI_R = crate::BitReader; #[doc = "Field `edssi` writer - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] -pub type EDSSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EDSSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ptime` reader - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] pub type PTIME_R = crate::BitReader; #[doc = "Field `ptime` writer - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] -pub type PTIME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PTIME_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn erbfi(&mut self) -> ERBFI_W { - ERBFI_W::new(self) + pub fn erbfi(&mut self) -> ERBFI_W { + ERBFI_W::new(self, 0) } #[doc = "Bit 1 - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn etbei(&mut self) -> ETBEI_W { - ETBEI_W::new(self) + pub fn etbei(&mut self) -> ETBEI_W { + ETBEI_W::new(self, 1) } #[doc = "Bit 2 - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn elsi(&mut self) -> ELSI_W { - ELSI_W::new(self) + pub fn elsi(&mut self) -> ELSI_W { + ELSI_W::new(self, 2) } #[doc = "Bit 3 - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn edssi(&mut self) -> EDSSI_W { - EDSSI_W::new(self) + pub fn edssi(&mut self) -> EDSSI_W { + EDSSI_W::new(self, 3) } #[doc = "Bit 7 - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn ptime(&mut self) -> PTIME_W { - PTIME_W::new(self) + pub fn ptime(&mut self) -> PTIME_W { + PTIME_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/iir.rs b/jh7110-vf2-12a-pac/src/uart4/iir.rs index c90daa5..c949f03 100644 --- a/jh7110-vf2-12a-pac/src/uart4/iir.rs +++ b/jh7110-vf2-12a-pac/src/uart4/iir.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/lcr.rs b/jh7110-vf2-12a-pac/src/uart4/lcr.rs index acd83ee..3bc10c2 100644 --- a/jh7110-vf2-12a-pac/src/uart4/lcr.rs +++ b/jh7110-vf2-12a-pac/src/uart4/lcr.rs @@ -7,7 +7,7 @@ is zero), always readable. This is used to select the number of data bits per ch pub type DLS_R = crate::FieldReader; #[doc = "Field `dls` writer - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] -pub type DLS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DLS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `stop` reader - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] @@ -15,31 +15,31 @@ pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pen` reader - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] pub type PEN_R = crate::BitReader; #[doc = "Field `pen` writer - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] -pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `eps` reader - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] pub type EPS_R = crate::BitReader; #[doc = "Field `eps` writer - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] -pub type EPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EPS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bc` reader - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] pub type BC_R = crate::BitReader; #[doc = "Field `bc` writer - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] -pub type BC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dlab` reader - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] pub type DLAB_R = crate::BitReader; #[doc = "Field `dlab` writer - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] -pub type DLAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DLAB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:1 - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] @@ -84,46 +84,50 @@ impl W { is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] #[inline(always)] #[must_use] - pub fn dls(&mut self) -> DLS_W { - DLS_W::new(self) + pub fn dls(&mut self) -> DLS_W { + DLS_W::new(self, 0) } #[doc = "Bit 2 - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 2) } #[doc = "Bit 3 - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W { - PEN_W::new(self) + pub fn pen(&mut self) -> PEN_W { + PEN_W::new(self, 3) } #[doc = "Bit 4 - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] #[inline(always)] #[must_use] - pub fn eps(&mut self) -> EPS_W { - EPS_W::new(self) + pub fn eps(&mut self) -> EPS_W { + EPS_W::new(self, 4) } #[doc = "Bit 6 - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] #[inline(always)] #[must_use] - pub fn bc(&mut self) -> BC_W { - BC_W::new(self) + pub fn bc(&mut self) -> BC_W { + BC_W::new(self, 6) } #[doc = "Bit 7 - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] #[inline(always)] #[must_use] - pub fn dlab(&mut self) -> DLAB_W { - DLAB_W::new(self) + pub fn dlab(&mut self) -> DLAB_W { + DLAB_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/lpdlh.rs b/jh7110-vf2-12a-pac/src/uart4/lpdlh.rs index 8a910c8..095afa9 100644 --- a/jh7110-vf2-12a-pac/src/uart4/lpdlh.rs +++ b/jh7110-vf2-12a-pac/src/uart4/lpdlh.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdlh` reader - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] pub type LPDLH_R = crate::FieldReader; #[doc = "Field `lpdlh` writer - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] -pub type LPDLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] #[must_use] - pub fn lpdlh(&mut self) -> LPDLH_W { - LPDLH_W::new(self) + pub fn lpdlh(&mut self) -> LPDLH_W { + LPDLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/lpdll.rs b/jh7110-vf2-12a-pac/src/uart4/lpdll.rs index 7780651..21d0018 100644 --- a/jh7110-vf2-12a-pac/src/uart4/lpdll.rs +++ b/jh7110-vf2-12a-pac/src/uart4/lpdll.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdll` reader - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] pub type LPDLL_R = crate::FieldReader; #[doc = "Field `lpdll` writer - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type LPDLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn lpdll(&mut self) -> LPDLL_W { - LPDLL_W::new(self) + pub fn lpdll(&mut self) -> LPDLL_W { + LPDLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/lsr.rs b/jh7110-vf2-12a-pac/src/uart4/lsr.rs index f576c10..ff2ab48 100644 --- a/jh7110-vf2-12a-pac/src/uart4/lsr.rs +++ b/jh7110-vf2-12a-pac/src/uart4/lsr.rs @@ -73,7 +73,11 @@ set to one). This is used to indicate if there is at least one parity error, fra } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/mcr.rs b/jh7110-vf2-12a-pac/src/uart4/mcr.rs index 6932ee7..9c93108 100644 --- a/jh7110-vf2-12a-pac/src/uart4/mcr.rs +++ b/jh7110-vf2-12a-pac/src/uart4/mcr.rs @@ -7,7 +7,7 @@ set to one), the dtr_n output is held inactive high while the value of this loca pub type DTR_R = crate::BitReader; #[doc = "Field `dtr` writer - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type DTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rts` reader - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR\\[5\\] @@ -23,19 +23,19 @@ set to one) and FIFOs enable (FCR\\[0\\] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR\\[1\\] is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out1` reader - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT1_R = crate::BitReader; #[doc = "Field `out1` writer - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out2` reader - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT2_R = crate::BitReader; #[doc = "Field `out2` writer - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `lb` reader - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] @@ -43,15 +43,15 @@ pub type LB_R = crate::BitReader; #[doc = "Field `lb` writer - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] -pub type LB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `afce` reader - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] pub type AFCE_R = crate::BitReader; #[doc = "Field `afce` writer - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] -pub type AFCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AFCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sire` reader - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] pub type SIRE_R = crate::BitReader; #[doc = "Field `sire` writer - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] -pub type SIRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SIRE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] @@ -105,8 +105,8 @@ impl W { set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn dtr(&mut self) -> DTR_W { - DTR_W::new(self) + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 0) } #[doc = "Bit 1 - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] @@ -117,44 +117,48 @@ is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W { - RTS_W::new(self) + pub fn rts(&mut self) -> RTS_W { + RTS_W::new(self, 1) } #[doc = "Bit 2 - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out1(&mut self) -> OUT1_W { - OUT1_W::new(self) + pub fn out1(&mut self) -> OUT1_W { + OUT1_W::new(self, 2) } #[doc = "Bit 3 - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out2(&mut self) -> OUT2_W { - OUT2_W::new(self) + pub fn out2(&mut self) -> OUT2_W { + OUT2_W::new(self, 3) } #[doc = "Bit 4 - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] #[inline(always)] #[must_use] - pub fn lb(&mut self) -> LB_W { - LB_W::new(self) + pub fn lb(&mut self) -> LB_W { + LB_W::new(self, 4) } #[doc = "Bit 5 - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] #[inline(always)] #[must_use] - pub fn afce(&mut self) -> AFCE_W { - AFCE_W::new(self) + pub fn afce(&mut self) -> AFCE_W { + AFCE_W::new(self, 5) } #[doc = "Bit 6 - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] #[inline(always)] #[must_use] - pub fn sire(&mut self) -> SIRE_W { - SIRE_W::new(self) + pub fn sire(&mut self) -> SIRE_W { + SIRE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/msr.rs b/jh7110-vf2-12a-pac/src/uart4/msr.rs index 65c526b..b54fc38 100644 --- a/jh7110-vf2-12a-pac/src/uart4/msr.rs +++ b/jh7110-vf2-12a-pac/src/uart4/msr.rs @@ -93,7 +93,11 @@ set to one), DCD is the same as MCR\\[3\\] } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/rbr.rs b/jh7110-vf2-12a-pac/src/uart4/rbr.rs index 03003ed..403adcf 100644 --- a/jh7110-vf2-12a-pac/src/uart4/rbr.rs +++ b/jh7110-vf2-12a-pac/src/uart4/rbr.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/rfl.rs b/jh7110-vf2-12a-pac/src/uart4/rfl.rs index 2aea928..59355cb 100644 --- a/jh7110-vf2-12a-pac/src/uart4/rfl.rs +++ b/jh7110-vf2-12a-pac/src/uart4/rfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/rfw.rs b/jh7110-vf2-12a-pac/src/uart4/rfw.rs index 7b917de..490472d 100644 --- a/jh7110-vf2-12a-pac/src/uart4/rfw.rs +++ b/jh7110-vf2-12a-pac/src/uart4/rfw.rs @@ -4,36 +4,40 @@ pub type R = crate::R; pub type W = crate::W; #[doc = "Field `rfwd` writer - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] -pub type RFWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type RFWD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `rfpe` writer - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] -pub type RFPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFPE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rffe` writer - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] -pub type RFFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bits 0:7 - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] #[inline(always)] #[must_use] - pub fn rfwd(&mut self) -> RFWD_W { - RFWD_W::new(self) + pub fn rfwd(&mut self) -> RFWD_W { + RFWD_W::new(self, 0) } #[doc = "Bit 8 - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rfpe(&mut self) -> RFPE_W { - RFPE_W::new(self) + pub fn rfpe(&mut self) -> RFPE_W { + RFPE_W::new(self, 8) } #[doc = "Bit 9 - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rffe(&mut self) -> RFFE_W { - RFFE_W::new(self) + pub fn rffe(&mut self) -> RFFE_W { + RFFE_W::new(self, 9) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sbcr.rs b/jh7110-vf2-12a-pac/src/uart4/sbcr.rs index 73914e9..5a120c0 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sbcr.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sbcr.rs @@ -7,7 +7,7 @@ pub type W = crate::W; pub type SBCR_R = crate::BitReader; #[doc = "Field `sbcr` writer - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] -pub type SBCR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SBCR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] @@ -21,10 +21,14 @@ impl W { = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] #[inline(always)] #[must_use] - pub fn sbcr(&mut self) -> SBCR_W { - SBCR_W::new(self) + pub fn sbcr(&mut self) -> SBCR_W { + SBCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/scr.rs b/jh7110-vf2-12a-pac/src/uart4/scr.rs index 744352e..f46ba21 100644 --- a/jh7110-vf2-12a-pac/src/uart4/scr.rs +++ b/jh7110-vf2-12a-pac/src/uart4/scr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `scr` reader - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sdmam.rs b/jh7110-vf2-12a-pac/src/uart4/sdmam.rs index 684377c..4be4fa2 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sdmam.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sdmam.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sdmam` reader - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] pub type SDMAM_R = crate::BitReader; #[doc = "Field `sdmam` writer - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] -pub type SDMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SDMAM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn sdmam(&mut self) -> SDMAM_W { - SDMAM_W::new(self) + pub fn sdmam(&mut self) -> SDMAM_W { + SDMAM_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sfe.rs b/jh7110-vf2-12a-pac/src/uart4/sfe.rs index e68b088..ed26fee 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sfe.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sfe.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sfe` reader - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] pub type SFE_R = crate::BitReader; #[doc = "Field `sfe` writer - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] -pub type SFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] #[must_use] - pub fn sfe(&mut self) -> SFE_W { - SFE_W::new(self) + pub fn sfe(&mut self) -> SFE_W { + SFE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srbr0.rs b/jh7110-vf2-12a-pac/src/uart4/srbr0.rs index 4076661..4e44d1a 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srbr0.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srbr0.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srbr1.rs b/jh7110-vf2-12a-pac/src/uart4/srbr1.rs index 2f31b75..46bc479 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srbr1.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srbr1.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srbr10.rs b/jh7110-vf2-12a-pac/src/uart4/srbr10.rs index 3639d65..70297bf 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srbr10.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srbr10.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srbr11.rs b/jh7110-vf2-12a-pac/src/uart4/srbr11.rs index 92d29b1..28d0277 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srbr11.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srbr11.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srbr12.rs b/jh7110-vf2-12a-pac/src/uart4/srbr12.rs index 52e795e..3eccd9a 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srbr12.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srbr12.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srbr13.rs b/jh7110-vf2-12a-pac/src/uart4/srbr13.rs index 50aae40..e47e4e4 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srbr13.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srbr13.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srbr14.rs b/jh7110-vf2-12a-pac/src/uart4/srbr14.rs index cb25819..8f23662 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srbr14.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srbr14.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srbr15.rs b/jh7110-vf2-12a-pac/src/uart4/srbr15.rs index b25ae46..1dac092 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srbr15.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srbr15.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srbr2.rs b/jh7110-vf2-12a-pac/src/uart4/srbr2.rs index 9f3236c..afb0617 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srbr2.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srbr2.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srbr3.rs b/jh7110-vf2-12a-pac/src/uart4/srbr3.rs index 5c1edda..0ff3650 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srbr3.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srbr3.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srbr4.rs b/jh7110-vf2-12a-pac/src/uart4/srbr4.rs index e6bee93..59560c4 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srbr4.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srbr4.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srbr5.rs b/jh7110-vf2-12a-pac/src/uart4/srbr5.rs index e599009..763e341 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srbr5.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srbr5.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srbr6.rs b/jh7110-vf2-12a-pac/src/uart4/srbr6.rs index b0155b3..78e2a40 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srbr6.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srbr6.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srbr7.rs b/jh7110-vf2-12a-pac/src/uart4/srbr7.rs index b8f9b88..0723ff0 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srbr7.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srbr7.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srbr8.rs b/jh7110-vf2-12a-pac/src/uart4/srbr8.rs index f57b044..4702cd9 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srbr8.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srbr8.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srbr9.rs b/jh7110-vf2-12a-pac/src/uart4/srbr9.rs index 3a160aa..e1a262e 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srbr9.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srbr9.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srr.rs b/jh7110-vf2-12a-pac/src/uart4/srr.rs index 6671199..fdb0c0a 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srr.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srr.rs @@ -3,31 +3,35 @@ pub type R = crate::R; #[doc = "Register `srr` writer"] pub type W = crate::W; #[doc = "Field `ur` writer - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] -pub type UR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type UR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfr` writer - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfr` writer - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFR_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] #[inline(always)] #[must_use] - pub fn ur(&mut self) -> UR_W { - UR_W::new(self) + pub fn ur(&mut self) -> UR_W { + UR_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfr(&mut self) -> RFR_W { - RFR_W::new(self) + pub fn rfr(&mut self) -> RFR_W { + RFR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfr(&mut self) -> XFR_W { - XFR_W::new(self) + pub fn xfr(&mut self) -> XFR_W { + XFR_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srt.rs b/jh7110-vf2-12a-pac/src/uart4/srt.rs index fed4f1f..da909fd 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srt.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `srt` reader - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] pub type SRT_R = crate::FieldReader; #[doc = "Field `srt` writer - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type SRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SRT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn srt(&mut self) -> SRT_W { - SRT_W::new(self) + pub fn srt(&mut self) -> SRT_W { + SRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/srts.rs b/jh7110-vf2-12a-pac/src/uart4/srts.rs index ceb0ee4..cf1e2a9 100644 --- a/jh7110-vf2-12a-pac/src/uart4/srts.rs +++ b/jh7110-vf2-12a-pac/src/uart4/srts.rs @@ -15,7 +15,7 @@ pub type SRTS_R = crate::BitReader; = 1) and FIFOs enable (FCR\\[0\\] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR\\[4\\] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] -pub type SRTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SRTS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Request to Send. This is a shadow register for the RTS bit (MCR\\[1\\]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] = 0), the rts_n signal is set low by programming MCR\\[1\\] @@ -37,10 +37,14 @@ impl W { = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn srts(&mut self) -> SRTS_W { - SRTS_W::new(self) + pub fn srts(&mut self) -> SRTS_W { + SRTS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/stet.rs b/jh7110-vf2-12a-pac/src/uart4/stet.rs index acb8ba1..503dc8a 100644 --- a/jh7110-vf2-12a-pac/src/uart4/stet.rs +++ b/jh7110-vf2-12a-pac/src/uart4/stet.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `stet` reader - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] pub type STET_R = crate::FieldReader; #[doc = "Field `stet` writer - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type STET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type STET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn stet(&mut self) -> STET_W { - STET_W::new(self) + pub fn stet(&mut self) -> STET_W { + STET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sthr0.rs b/jh7110-vf2-12a-pac/src/uart4/sthr0.rs index bfd277a..764ff05 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sthr0.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sthr0.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sthr1.rs b/jh7110-vf2-12a-pac/src/uart4/sthr1.rs index cc79733..5d58855 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sthr1.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sthr1.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sthr10.rs b/jh7110-vf2-12a-pac/src/uart4/sthr10.rs index be2659d..ffc38ff 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sthr10.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sthr10.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sthr11.rs b/jh7110-vf2-12a-pac/src/uart4/sthr11.rs index 8613dd5..1f8147f 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sthr11.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sthr11.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sthr12.rs b/jh7110-vf2-12a-pac/src/uart4/sthr12.rs index b354b10..7d816f3 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sthr12.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sthr12.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sthr13.rs b/jh7110-vf2-12a-pac/src/uart4/sthr13.rs index 06df4bc..9283b6a 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sthr13.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sthr13.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sthr14.rs b/jh7110-vf2-12a-pac/src/uart4/sthr14.rs index e181dd0..2daf622 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sthr14.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sthr14.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sthr15.rs b/jh7110-vf2-12a-pac/src/uart4/sthr15.rs index 4825778..f70715e 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sthr15.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sthr15.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sthr2.rs b/jh7110-vf2-12a-pac/src/uart4/sthr2.rs index d390f10..f1a9c77 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sthr2.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sthr2.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sthr3.rs b/jh7110-vf2-12a-pac/src/uart4/sthr3.rs index a74fdf0..06aab9e 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sthr3.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sthr3.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sthr4.rs b/jh7110-vf2-12a-pac/src/uart4/sthr4.rs index 1ee6b87..f6e7944 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sthr4.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sthr4.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sthr5.rs b/jh7110-vf2-12a-pac/src/uart4/sthr5.rs index ca360fe..7873a53 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sthr5.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sthr5.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sthr6.rs b/jh7110-vf2-12a-pac/src/uart4/sthr6.rs index 18e6fac..87c81df 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sthr6.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sthr6.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sthr7.rs b/jh7110-vf2-12a-pac/src/uart4/sthr7.rs index 27072a3..9928b3d 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sthr7.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sthr7.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sthr8.rs b/jh7110-vf2-12a-pac/src/uart4/sthr8.rs index 15060b8..565cb1d 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sthr8.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sthr8.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/sthr9.rs b/jh7110-vf2-12a-pac/src/uart4/sthr9.rs index 58af642..e64fece 100644 --- a/jh7110-vf2-12a-pac/src/uart4/sthr9.rs +++ b/jh7110-vf2-12a-pac/src/uart4/sthr9.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/tfl.rs b/jh7110-vf2-12a-pac/src/uart4/tfl.rs index e1faba6..db09fe3 100644 --- a/jh7110-vf2-12a-pac/src/uart4/tfl.rs +++ b/jh7110-vf2-12a-pac/src/uart4/tfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/tfr.rs b/jh7110-vf2-12a-pac/src/uart4/tfr.rs index 8e9ad91..714deff 100644 --- a/jh7110-vf2-12a-pac/src/uart4/tfr.rs +++ b/jh7110-vf2-12a-pac/src/uart4/tfr.rs @@ -14,7 +14,11 @@ is set to one). When FIFOs are implemented and enabled, reading this register gi } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/thr.rs b/jh7110-vf2-12a-pac/src/uart4/thr.rs index f910bd8..7845232 100644 --- a/jh7110-vf2-12a-pac/src/uart4/thr.rs +++ b/jh7110-vf2-12a-pac/src/uart4/thr.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `thr` writer - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type THR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type THR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn thr(&mut self) -> THR_W { - THR_W::new(self) + pub fn thr(&mut self) -> THR_W { + THR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/ucv.rs b/jh7110-vf2-12a-pac/src/uart4/ucv.rs index 8a3be91..6497a08 100644 --- a/jh7110-vf2-12a-pac/src/uart4/ucv.rs +++ b/jh7110-vf2-12a-pac/src/uart4/ucv.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart4/usr.rs b/jh7110-vf2-12a-pac/src/uart4/usr.rs index 445a085..b96417d 100644 --- a/jh7110-vf2-12a-pac/src/uart4/usr.rs +++ b/jh7110-vf2-12a-pac/src/uart4/usr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5.rs b/jh7110-vf2-12a-pac/src/uart5.rs index c462fbf..8a5f089 100644 --- a/jh7110-vf2-12a-pac/src/uart5.rs +++ b/jh7110-vf2-12a-pac/src/uart5.rs @@ -4,20 +4,13 @@ pub struct RegisterBlock { _reserved_0_dll: [u8; 0x04], _reserved_1_dlh: [u8; 0x04], _reserved_2_fcr: [u8; 0x04], - #[doc = "0x0c - Line Control Register"] - pub lcr: LCR, - #[doc = "0x10 - Modem Control Register"] - pub mcr: MCR, - #[doc = "0x14 - Line Status Register"] - pub lsr: LSR, - #[doc = "0x18 - Line Status Register"] - pub msr: MSR, - #[doc = "0x1c - Scratch Pad Register"] - pub scr: SCR, - #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdll: LPDLL, - #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdlh: LPDLH, + lcr: LCR, + mcr: MCR, + lsr: LSR, + msr: MSR, + scr: SCR, + lpdll: LPDLL, + lpdlh: LPDLH, _reserved10: [u8; 0x08], _reserved_10_srbr0: [u8; 0x04], _reserved_11_srbr1: [u8; 0x04], @@ -35,564 +28,663 @@ pub struct RegisterBlock { _reserved_23_srbr13: [u8; 0x04], _reserved_24_srbr14: [u8; 0x04], _reserved_25_srbr15: [u8; 0x04], - #[doc = "0x70 - FIFO Access Register"] - pub far: FAR, - #[doc = "0x74 - Transmit FIFO Read"] - pub tfr: TFR, - #[doc = "0x78 - Receive FIFO Write"] - pub rfw: RFW, - #[doc = "0x7c - UART Status Register"] - pub usr: USR, - #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub tfl: TFL, - #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub rfl: RFL, - #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srr: SRR, - #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srts: SRTS, - #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sbcr: SBCR, - #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sdmam: SDMAM, - #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sfe: SFE, - #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srt: SRT, - #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub stet: STET, - #[doc = "0xa4 - Halt TX"] - pub htx: HTX, - #[doc = "0xa8 - DMA Software Acknowledge"] - pub dmasa: DMASA, + far: FAR, + tfr: TFR, + rfw: RFW, + usr: USR, + tfl: TFL, + rfl: RFL, + srr: SRR, + srts: SRTS, + sbcr: SBCR, + sdmam: SDMAM, + sfe: SFE, + srt: SRT, + stet: STET, + htx: HTX, + dmasa: DMASA, _reserved41: [u8; 0x48], - #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] - pub cpr: CPR, + cpr: CPR, _reserved_42_ctr: [u8; 0x04], } impl RegisterBlock { #[doc = "0x00 - Divisor Latch Low"] #[inline(always)] pub const fn dll(&self) -> &DLL { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Transmit Holding Register"] #[inline(always)] pub const fn thr(&self) -> &THR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Receive Buffer Register"] #[inline(always)] pub const fn rbr(&self) -> &RBR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x04 - Interrupt Enable Register"] #[inline(always)] pub const fn ier(&self) -> &IER { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x04 - Divisor Latch High"] #[inline(always)] pub const fn dlh(&self) -> &DLH { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x08 - FIFO Control Register"] #[inline(always)] pub const fn fcr(&self) -> &FCR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } } #[doc = "0x08 - Interrupt Identity Register"] #[inline(always)] pub const fn iir(&self) -> &IIR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } + } + #[doc = "0x0c - Line Control Register"] + #[inline(always)] + pub const fn lcr(&self) -> &LCR { + &self.lcr + } + #[doc = "0x10 - Modem Control Register"] + #[inline(always)] + pub const fn mcr(&self) -> &MCR { + &self.mcr + } + #[doc = "0x14 - Line Status Register"] + #[inline(always)] + pub const fn lsr(&self) -> &LSR { + &self.lsr + } + #[doc = "0x18 - Line Status Register"] + #[inline(always)] + pub const fn msr(&self) -> &MSR { + &self.msr + } + #[doc = "0x1c - Scratch Pad Register"] + #[inline(always)] + pub const fn scr(&self) -> &SCR { + &self.scr + } + #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdll(&self) -> &LPDLL { + &self.lpdll + } + #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdlh(&self) -> &LPDLH { + &self.lpdlh } #[doc = "0x30 - Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr0(&self) -> &STHR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x30 - Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr0(&self) -> &SRBR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x34 - Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr1(&self) -> &STHR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x34 - Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr1(&self) -> &SRBR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x38 - Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr2(&self) -> &STHR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x38 - Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr2(&self) -> &SRBR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x3c - Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr3(&self) -> &STHR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x3c - Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr3(&self) -> &SRBR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x40 - Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr4(&self) -> &STHR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x40 - Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr4(&self) -> &SRBR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x44 - Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr5(&self) -> &STHR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x44 - Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr5(&self) -> &SRBR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x48 - Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr6(&self) -> &STHR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x48 - Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr6(&self) -> &SRBR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x4c - Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr7(&self) -> &STHR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x4c - Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr7(&self) -> &SRBR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x50 - Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr8(&self) -> &STHR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x50 - Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr8(&self) -> &SRBR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x54 - Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr9(&self) -> &STHR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x54 - Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr9(&self) -> &SRBR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x58 - Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr10(&self) -> &STHR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x58 - Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr10(&self) -> &SRBR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x5c - Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr11(&self) -> &STHR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x5c - Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr11(&self) -> &SRBR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x60 - Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr12(&self) -> &STHR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x60 - Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr12(&self) -> &SRBR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x64 - Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr13(&self) -> &STHR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x64 - Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr13(&self) -> &SRBR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x68 - Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr14(&self) -> &STHR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x68 - Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr14(&self) -> &SRBR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x6c - Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr15(&self) -> &STHR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } } #[doc = "0x6c - Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr15(&self) -> &SRBR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } + } + #[doc = "0x70 - FIFO Access Register"] + #[inline(always)] + pub const fn far(&self) -> &FAR { + &self.far + } + #[doc = "0x74 - Transmit FIFO Read"] + #[inline(always)] + pub const fn tfr(&self) -> &TFR { + &self.tfr + } + #[doc = "0x78 - Receive FIFO Write"] + #[inline(always)] + pub const fn rfw(&self) -> &RFW { + &self.rfw + } + #[doc = "0x7c - UART Status Register"] + #[inline(always)] + pub const fn usr(&self) -> &USR { + &self.usr + } + #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn tfl(&self) -> &TFL { + &self.tfl + } + #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn rfl(&self) -> &RFL { + &self.rfl + } + #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srr(&self) -> &SRR { + &self.srr + } + #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srts(&self) -> &SRTS { + &self.srts + } + #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sbcr(&self) -> &SBCR { + &self.sbcr + } + #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sdmam(&self) -> &SDMAM { + &self.sdmam + } + #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sfe(&self) -> &SFE { + &self.sfe + } + #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srt(&self) -> &SRT { + &self.srt + } + #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn stet(&self) -> &STET { + &self.stet + } + #[doc = "0xa4 - Halt TX"] + #[inline(always)] + pub const fn htx(&self) -> &HTX { + &self.htx + } + #[doc = "0xa8 - DMA Software Acknowledge"] + #[inline(always)] + pub const fn dmasa(&self) -> &DMASA { + &self.dmasa + } + #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn cpr(&self) -> &CPR { + &self.cpr } #[doc = "0xf8 - Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ctr(&self) -> &CTR { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } #[doc = "0xf8 - UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ucv(&self) -> &UCV { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } } -#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rbr`] +#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbr`] module"] pub type RBR = crate::Reg; #[doc = "Receive Buffer Register"] pub mod rbr; -#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`thr`] +#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thr`] module"] pub type THR = crate::Reg; #[doc = "Transmit Holding Register"] pub mod thr; -#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dll`] +#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll`] module"] pub type DLL = crate::Reg; #[doc = "Divisor Latch Low"] pub mod dll; -#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dlh`] +#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlh`] module"] pub type DLH = crate::Reg; #[doc = "Divisor Latch High"] pub mod dlh; -#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`iir`] +#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] module"] pub type IIR = crate::Reg; #[doc = "Interrupt Identity Register"] pub mod iir; -#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fcr`] +#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"] pub type FCR = crate::Reg; #[doc = "FIFO Control Register"] pub mod fcr; -#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lcr`] +#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] module"] pub type LCR = crate::Reg; #[doc = "Line Control Register"] pub mod lcr; -#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mcr`] +#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] pub type MCR = crate::Reg; #[doc = "Modem Control Register"] pub mod mcr; -#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lsr`] +#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] module"] pub type LSR = crate::Reg; #[doc = "Line Status Register"] pub mod lsr; -#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msr`] +#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"] pub type MSR = crate::Reg; #[doc = "Line Status Register"] pub mod msr; -#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scr`] +#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`] module"] pub type SCR = crate::Reg; #[doc = "Scratch Pad Register"] pub mod scr; -#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdll`] +#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdll`] module"] pub type LPDLL = crate::Reg; #[doc = "Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdll; -#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdlh`] +#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdlh`] module"] pub type LPDLH = crate::Reg; #[doc = "Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdlh; -#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr0`] +#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr0`] module"] pub type SRBR0 = crate::Reg; #[doc = "Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr0; -#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr0`] +#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr0`] module"] pub type STHR0 = crate::Reg; #[doc = "Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr0; -#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr1`] +#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr1`] module"] pub type SRBR1 = crate::Reg; #[doc = "Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr1; -#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr1`] +#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr1`] module"] pub type STHR1 = crate::Reg; #[doc = "Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr1; -#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr2`] +#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr2`] module"] pub type SRBR2 = crate::Reg; #[doc = "Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr2; -#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr2`] +#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr2`] module"] pub type STHR2 = crate::Reg; #[doc = "Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr2; -#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr3`] +#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr3`] module"] pub type SRBR3 = crate::Reg; #[doc = "Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr3; -#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr3`] +#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr3`] module"] pub type STHR3 = crate::Reg; #[doc = "Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr3; -#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr4`] +#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr4`] module"] pub type SRBR4 = crate::Reg; #[doc = "Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr4; -#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr4`] +#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr4`] module"] pub type STHR4 = crate::Reg; #[doc = "Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr4; -#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr5`] +#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr5`] module"] pub type SRBR5 = crate::Reg; #[doc = "Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr5; -#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr5`] +#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr5`] module"] pub type STHR5 = crate::Reg; #[doc = "Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr5; -#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr6`] +#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr6`] module"] pub type SRBR6 = crate::Reg; #[doc = "Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr6; -#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr6`] +#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr6`] module"] pub type STHR6 = crate::Reg; #[doc = "Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr6; -#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr7`] +#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr7`] module"] pub type SRBR7 = crate::Reg; #[doc = "Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr7; -#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr7`] +#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr7`] module"] pub type STHR7 = crate::Reg; #[doc = "Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr7; -#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr8`] +#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr8`] module"] pub type SRBR8 = crate::Reg; #[doc = "Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr8; -#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr8`] +#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr8`] module"] pub type STHR8 = crate::Reg; #[doc = "Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr8; -#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr9`] +#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr9`] module"] pub type SRBR9 = crate::Reg; #[doc = "Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr9; -#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr9`] +#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr9`] module"] pub type STHR9 = crate::Reg; #[doc = "Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr9; -#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr10`] +#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr10`] module"] pub type SRBR10 = crate::Reg; #[doc = "Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr10; -#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr10`] +#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr10`] module"] pub type STHR10 = crate::Reg; #[doc = "Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr10; -#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr11`] +#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr11`] module"] pub type SRBR11 = crate::Reg; #[doc = "Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr11; -#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr11`] +#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr11`] module"] pub type STHR11 = crate::Reg; #[doc = "Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr11; -#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr12`] +#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr12`] module"] pub type SRBR12 = crate::Reg; #[doc = "Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr12; -#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr12`] +#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr12`] module"] pub type STHR12 = crate::Reg; #[doc = "Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr12; -#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr13`] +#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr13`] module"] pub type SRBR13 = crate::Reg; #[doc = "Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr13; -#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr13`] +#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr13`] module"] pub type STHR13 = crate::Reg; #[doc = "Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr13; -#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr14`] +#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr14`] module"] pub type SRBR14 = crate::Reg; #[doc = "Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr14; -#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr14`] +#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr14`] module"] pub type STHR14 = crate::Reg; #[doc = "Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr14; -#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr15`] +#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr15`] module"] pub type SRBR15 = crate::Reg; #[doc = "Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr15; -#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr15`] +#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr15`] module"] pub type STHR15 = crate::Reg; #[doc = "Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr15; -#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`far`] +#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@far`] module"] pub type FAR = crate::Reg; #[doc = "FIFO Access Register"] pub mod far; -#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfr`] +#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfr`] module"] pub type TFR = crate::Reg; #[doc = "Transmit FIFO Read"] pub mod tfr; -#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfw`] +#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfw`] module"] pub type RFW = crate::Reg; #[doc = "Receive FIFO Write"] pub mod rfw; -#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`usr`] +#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usr`] module"] pub type USR = crate::Reg; #[doc = "UART Status Register"] pub mod usr; -#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfl`] +#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfl`] module"] pub type TFL = crate::Reg; #[doc = "Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod tfl; -#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfl`] +#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfl`] module"] pub type RFL = crate::Reg; #[doc = "Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod rfl; -#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srr`] +#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srr`] module"] pub type SRR = crate::Reg; #[doc = "Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srr; -#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srts`] +#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srts`] module"] pub type SRTS = crate::Reg; #[doc = "Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srts; -#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sbcr`] +#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sbcr`] module"] pub type SBCR = crate::Reg; #[doc = "Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sbcr; -#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sdmam`] +#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdmam`] module"] pub type SDMAM = crate::Reg; #[doc = "Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sdmam; -#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sfe`] +#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfe`] module"] pub type SFE = crate::Reg; #[doc = "Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sfe; -#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srt`] +#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srt`] module"] pub type SRT = crate::Reg; #[doc = "Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srt; -#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stet`] +#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stet`] module"] pub type STET = crate::Reg; #[doc = "Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod stet; -#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`htx`] +#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@htx`] module"] pub type HTX = crate::Reg; #[doc = "Halt TX"] pub mod htx; -#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dmasa`] +#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasa`] module"] pub type DMASA = crate::Reg; #[doc = "DMA Software Acknowledge"] pub mod dmasa; -#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cpr`] +#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpr`] module"] pub type CPR = crate::Reg; #[doc = "Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] pub mod cpr; -#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ucv`] +#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucv`] module"] pub type UCV = crate::Reg; #[doc = "UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] pub mod ucv; -#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctr`] +#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"] pub type CTR = crate::Reg; #[doc = "Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] diff --git a/jh7110-vf2-12a-pac/src/uart5/cpr.rs b/jh7110-vf2-12a-pac/src/uart5/cpr.rs index 4807519..332b584 100644 --- a/jh7110-vf2-12a-pac/src/uart5/cpr.rs +++ b/jh7110-vf2-12a-pac/src/uart5/cpr.rs @@ -89,7 +89,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/ctr.rs b/jh7110-vf2-12a-pac/src/uart5/ctr.rs index c3760d5..ac70194 100644 --- a/jh7110-vf2-12a-pac/src/uart5/ctr.rs +++ b/jh7110-vf2-12a-pac/src/uart5/ctr.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/dlh.rs b/jh7110-vf2-12a-pac/src/uart5/dlh.rs index 3257a2d..2a788c1 100644 --- a/jh7110-vf2-12a-pac/src/uart5/dlh.rs +++ b/jh7110-vf2-12a-pac/src/uart5/dlh.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLH_R = crate::FieldReader; #[doc = "Field `dlh` writer - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dlh(&mut self) -> DLH_W { - DLH_W::new(self) + pub fn dlh(&mut self) -> DLH_W { + DLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/dll.rs b/jh7110-vf2-12a-pac/src/uart5/dll.rs index 9c9daff..1c9d765 100644 --- a/jh7110-vf2-12a-pac/src/uart5/dll.rs +++ b/jh7110-vf2-12a-pac/src/uart5/dll.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLL_R = crate::FieldReader; #[doc = "Field `dll` writer - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dll(&mut self) -> DLL_W { - DLL_W::new(self) + pub fn dll(&mut self) -> DLL_W { + DLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/dmasa.rs b/jh7110-vf2-12a-pac/src/uart5/dmasa.rs index 7bcfb26..2fc4e6d 100644 --- a/jh7110-vf2-12a-pac/src/uart5/dmasa.rs +++ b/jh7110-vf2-12a-pac/src/uart5/dmasa.rs @@ -3,15 +3,19 @@ pub type R = crate::R; #[doc = "Register `dmasa` writer"] pub type W = crate::W; #[doc = "Field `dmasa` writer - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type DMASA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMASA_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn dmasa(&mut self) -> DMASA_W { - DMASA_W::new(self) + pub fn dmasa(&mut self) -> DMASA_W { + DMASA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/far.rs b/jh7110-vf2-12a-pac/src/uart5/far.rs index 3b3bcb1..d52059a 100644 --- a/jh7110-vf2-12a-pac/src/uart5/far.rs +++ b/jh7110-vf2-12a-pac/src/uart5/far.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `far` reader - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] pub type FAR_R = crate::BitReader; #[doc = "Field `far` writer - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] -pub type FAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FAR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] #[must_use] - pub fn far(&mut self) -> FAR_W { - FAR_W::new(self) + pub fn far(&mut self) -> FAR_W { + FAR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/fcr.rs b/jh7110-vf2-12a-pac/src/uart5/fcr.rs index 4fbb499..a64a60b 100644 --- a/jh7110-vf2-12a-pac/src/uart5/fcr.rs +++ b/jh7110-vf2-12a-pac/src/uart5/fcr.rs @@ -3,55 +3,59 @@ pub type R = crate::R; #[doc = "Register `fcr` writer"] pub type W = crate::W; #[doc = "Field `fifoe` writer - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] -pub type FIFOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIFOE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfifor` writer - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfifor` writer - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dmam` writer - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] -pub type DMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMAM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tet` writer - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type TET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `rt` writer - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type RT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type RT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl W { #[doc = "Bit 0 - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] #[inline(always)] #[must_use] - pub fn fifoe(&mut self) -> FIFOE_W { - FIFOE_W::new(self) + pub fn fifoe(&mut self) -> FIFOE_W { + FIFOE_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfifor(&mut self) -> RFIFOR_W { - RFIFOR_W::new(self) + pub fn rfifor(&mut self) -> RFIFOR_W { + RFIFOR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfifor(&mut self) -> XFIFOR_W { - XFIFOR_W::new(self) + pub fn xfifor(&mut self) -> XFIFOR_W { + XFIFOR_W::new(self, 2) } #[doc = "Bit 3 - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn dmam(&mut self) -> DMAM_W { - DMAM_W::new(self) + pub fn dmam(&mut self) -> DMAM_W { + DMAM_W::new(self, 3) } #[doc = "Bits 4:5 - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn tet(&mut self) -> TET_W { - TET_W::new(self) + pub fn tet(&mut self) -> TET_W { + TET_W::new(self, 4) } #[doc = "Bits 6:7 - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn rt(&mut self) -> RT_W { - RT_W::new(self) + pub fn rt(&mut self) -> RT_W { + RT_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/htx.rs b/jh7110-vf2-12a-pac/src/uart5/htx.rs index ad027bd..fc82325 100644 --- a/jh7110-vf2-12a-pac/src/uart5/htx.rs +++ b/jh7110-vf2-12a-pac/src/uart5/htx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `htx` reader - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] pub type HTX_R = crate::BitReader; #[doc = "Field `htx` writer - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] -pub type HTX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HTX_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] #[must_use] - pub fn htx(&mut self) -> HTX_W { - HTX_W::new(self) + pub fn htx(&mut self) -> HTX_W { + HTX_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/ier.rs b/jh7110-vf2-12a-pac/src/uart5/ier.rs index 006fbea..3cf3d7f 100644 --- a/jh7110-vf2-12a-pac/src/uart5/ier.rs +++ b/jh7110-vf2-12a-pac/src/uart5/ier.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `erbfi` reader - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] pub type ERBFI_R = crate::BitReader; #[doc = "Field `erbfi` writer - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] -pub type ERBFI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ERBFI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `etbei` reader - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] pub type ETBEI_R = crate::BitReader; #[doc = "Field `etbei` writer - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ETBEI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ETBEI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `elsi` reader - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] pub type ELSI_R = crate::BitReader; #[doc = "Field `elsi` writer - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ELSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ELSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `edssi` reader - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] pub type EDSSI_R = crate::BitReader; #[doc = "Field `edssi` writer - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] -pub type EDSSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EDSSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ptime` reader - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] pub type PTIME_R = crate::BitReader; #[doc = "Field `ptime` writer - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] -pub type PTIME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PTIME_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn erbfi(&mut self) -> ERBFI_W { - ERBFI_W::new(self) + pub fn erbfi(&mut self) -> ERBFI_W { + ERBFI_W::new(self, 0) } #[doc = "Bit 1 - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn etbei(&mut self) -> ETBEI_W { - ETBEI_W::new(self) + pub fn etbei(&mut self) -> ETBEI_W { + ETBEI_W::new(self, 1) } #[doc = "Bit 2 - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn elsi(&mut self) -> ELSI_W { - ELSI_W::new(self) + pub fn elsi(&mut self) -> ELSI_W { + ELSI_W::new(self, 2) } #[doc = "Bit 3 - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn edssi(&mut self) -> EDSSI_W { - EDSSI_W::new(self) + pub fn edssi(&mut self) -> EDSSI_W { + EDSSI_W::new(self, 3) } #[doc = "Bit 7 - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn ptime(&mut self) -> PTIME_W { - PTIME_W::new(self) + pub fn ptime(&mut self) -> PTIME_W { + PTIME_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/iir.rs b/jh7110-vf2-12a-pac/src/uart5/iir.rs index c90daa5..c949f03 100644 --- a/jh7110-vf2-12a-pac/src/uart5/iir.rs +++ b/jh7110-vf2-12a-pac/src/uart5/iir.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/lcr.rs b/jh7110-vf2-12a-pac/src/uart5/lcr.rs index acd83ee..3bc10c2 100644 --- a/jh7110-vf2-12a-pac/src/uart5/lcr.rs +++ b/jh7110-vf2-12a-pac/src/uart5/lcr.rs @@ -7,7 +7,7 @@ is zero), always readable. This is used to select the number of data bits per ch pub type DLS_R = crate::FieldReader; #[doc = "Field `dls` writer - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] -pub type DLS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DLS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `stop` reader - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] @@ -15,31 +15,31 @@ pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pen` reader - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] pub type PEN_R = crate::BitReader; #[doc = "Field `pen` writer - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] -pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `eps` reader - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] pub type EPS_R = crate::BitReader; #[doc = "Field `eps` writer - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] -pub type EPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EPS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bc` reader - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] pub type BC_R = crate::BitReader; #[doc = "Field `bc` writer - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] -pub type BC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dlab` reader - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] pub type DLAB_R = crate::BitReader; #[doc = "Field `dlab` writer - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] -pub type DLAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DLAB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:1 - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] @@ -84,46 +84,50 @@ impl W { is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] #[inline(always)] #[must_use] - pub fn dls(&mut self) -> DLS_W { - DLS_W::new(self) + pub fn dls(&mut self) -> DLS_W { + DLS_W::new(self, 0) } #[doc = "Bit 2 - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 2) } #[doc = "Bit 3 - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W { - PEN_W::new(self) + pub fn pen(&mut self) -> PEN_W { + PEN_W::new(self, 3) } #[doc = "Bit 4 - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] #[inline(always)] #[must_use] - pub fn eps(&mut self) -> EPS_W { - EPS_W::new(self) + pub fn eps(&mut self) -> EPS_W { + EPS_W::new(self, 4) } #[doc = "Bit 6 - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] #[inline(always)] #[must_use] - pub fn bc(&mut self) -> BC_W { - BC_W::new(self) + pub fn bc(&mut self) -> BC_W { + BC_W::new(self, 6) } #[doc = "Bit 7 - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] #[inline(always)] #[must_use] - pub fn dlab(&mut self) -> DLAB_W { - DLAB_W::new(self) + pub fn dlab(&mut self) -> DLAB_W { + DLAB_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/lpdlh.rs b/jh7110-vf2-12a-pac/src/uart5/lpdlh.rs index 8a910c8..095afa9 100644 --- a/jh7110-vf2-12a-pac/src/uart5/lpdlh.rs +++ b/jh7110-vf2-12a-pac/src/uart5/lpdlh.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdlh` reader - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] pub type LPDLH_R = crate::FieldReader; #[doc = "Field `lpdlh` writer - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] -pub type LPDLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] #[must_use] - pub fn lpdlh(&mut self) -> LPDLH_W { - LPDLH_W::new(self) + pub fn lpdlh(&mut self) -> LPDLH_W { + LPDLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/lpdll.rs b/jh7110-vf2-12a-pac/src/uart5/lpdll.rs index 7780651..21d0018 100644 --- a/jh7110-vf2-12a-pac/src/uart5/lpdll.rs +++ b/jh7110-vf2-12a-pac/src/uart5/lpdll.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdll` reader - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] pub type LPDLL_R = crate::FieldReader; #[doc = "Field `lpdll` writer - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type LPDLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn lpdll(&mut self) -> LPDLL_W { - LPDLL_W::new(self) + pub fn lpdll(&mut self) -> LPDLL_W { + LPDLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/lsr.rs b/jh7110-vf2-12a-pac/src/uart5/lsr.rs index f576c10..ff2ab48 100644 --- a/jh7110-vf2-12a-pac/src/uart5/lsr.rs +++ b/jh7110-vf2-12a-pac/src/uart5/lsr.rs @@ -73,7 +73,11 @@ set to one). This is used to indicate if there is at least one parity error, fra } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/mcr.rs b/jh7110-vf2-12a-pac/src/uart5/mcr.rs index 6932ee7..9c93108 100644 --- a/jh7110-vf2-12a-pac/src/uart5/mcr.rs +++ b/jh7110-vf2-12a-pac/src/uart5/mcr.rs @@ -7,7 +7,7 @@ set to one), the dtr_n output is held inactive high while the value of this loca pub type DTR_R = crate::BitReader; #[doc = "Field `dtr` writer - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type DTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rts` reader - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR\\[5\\] @@ -23,19 +23,19 @@ set to one) and FIFOs enable (FCR\\[0\\] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR\\[1\\] is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out1` reader - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT1_R = crate::BitReader; #[doc = "Field `out1` writer - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out2` reader - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT2_R = crate::BitReader; #[doc = "Field `out2` writer - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `lb` reader - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] @@ -43,15 +43,15 @@ pub type LB_R = crate::BitReader; #[doc = "Field `lb` writer - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] -pub type LB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `afce` reader - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] pub type AFCE_R = crate::BitReader; #[doc = "Field `afce` writer - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] -pub type AFCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AFCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sire` reader - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] pub type SIRE_R = crate::BitReader; #[doc = "Field `sire` writer - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] -pub type SIRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SIRE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] @@ -105,8 +105,8 @@ impl W { set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn dtr(&mut self) -> DTR_W { - DTR_W::new(self) + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 0) } #[doc = "Bit 1 - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] @@ -117,44 +117,48 @@ is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W { - RTS_W::new(self) + pub fn rts(&mut self) -> RTS_W { + RTS_W::new(self, 1) } #[doc = "Bit 2 - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out1(&mut self) -> OUT1_W { - OUT1_W::new(self) + pub fn out1(&mut self) -> OUT1_W { + OUT1_W::new(self, 2) } #[doc = "Bit 3 - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out2(&mut self) -> OUT2_W { - OUT2_W::new(self) + pub fn out2(&mut self) -> OUT2_W { + OUT2_W::new(self, 3) } #[doc = "Bit 4 - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] #[inline(always)] #[must_use] - pub fn lb(&mut self) -> LB_W { - LB_W::new(self) + pub fn lb(&mut self) -> LB_W { + LB_W::new(self, 4) } #[doc = "Bit 5 - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] #[inline(always)] #[must_use] - pub fn afce(&mut self) -> AFCE_W { - AFCE_W::new(self) + pub fn afce(&mut self) -> AFCE_W { + AFCE_W::new(self, 5) } #[doc = "Bit 6 - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] #[inline(always)] #[must_use] - pub fn sire(&mut self) -> SIRE_W { - SIRE_W::new(self) + pub fn sire(&mut self) -> SIRE_W { + SIRE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/msr.rs b/jh7110-vf2-12a-pac/src/uart5/msr.rs index 65c526b..b54fc38 100644 --- a/jh7110-vf2-12a-pac/src/uart5/msr.rs +++ b/jh7110-vf2-12a-pac/src/uart5/msr.rs @@ -93,7 +93,11 @@ set to one), DCD is the same as MCR\\[3\\] } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/rbr.rs b/jh7110-vf2-12a-pac/src/uart5/rbr.rs index 03003ed..403adcf 100644 --- a/jh7110-vf2-12a-pac/src/uart5/rbr.rs +++ b/jh7110-vf2-12a-pac/src/uart5/rbr.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/rfl.rs b/jh7110-vf2-12a-pac/src/uart5/rfl.rs index 2aea928..59355cb 100644 --- a/jh7110-vf2-12a-pac/src/uart5/rfl.rs +++ b/jh7110-vf2-12a-pac/src/uart5/rfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/rfw.rs b/jh7110-vf2-12a-pac/src/uart5/rfw.rs index 7b917de..490472d 100644 --- a/jh7110-vf2-12a-pac/src/uart5/rfw.rs +++ b/jh7110-vf2-12a-pac/src/uart5/rfw.rs @@ -4,36 +4,40 @@ pub type R = crate::R; pub type W = crate::W; #[doc = "Field `rfwd` writer - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] -pub type RFWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type RFWD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `rfpe` writer - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] -pub type RFPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFPE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rffe` writer - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] -pub type RFFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bits 0:7 - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] #[inline(always)] #[must_use] - pub fn rfwd(&mut self) -> RFWD_W { - RFWD_W::new(self) + pub fn rfwd(&mut self) -> RFWD_W { + RFWD_W::new(self, 0) } #[doc = "Bit 8 - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rfpe(&mut self) -> RFPE_W { - RFPE_W::new(self) + pub fn rfpe(&mut self) -> RFPE_W { + RFPE_W::new(self, 8) } #[doc = "Bit 9 - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rffe(&mut self) -> RFFE_W { - RFFE_W::new(self) + pub fn rffe(&mut self) -> RFFE_W { + RFFE_W::new(self, 9) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sbcr.rs b/jh7110-vf2-12a-pac/src/uart5/sbcr.rs index 73914e9..5a120c0 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sbcr.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sbcr.rs @@ -7,7 +7,7 @@ pub type W = crate::W; pub type SBCR_R = crate::BitReader; #[doc = "Field `sbcr` writer - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] -pub type SBCR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SBCR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] @@ -21,10 +21,14 @@ impl W { = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] #[inline(always)] #[must_use] - pub fn sbcr(&mut self) -> SBCR_W { - SBCR_W::new(self) + pub fn sbcr(&mut self) -> SBCR_W { + SBCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/scr.rs b/jh7110-vf2-12a-pac/src/uart5/scr.rs index 744352e..f46ba21 100644 --- a/jh7110-vf2-12a-pac/src/uart5/scr.rs +++ b/jh7110-vf2-12a-pac/src/uart5/scr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `scr` reader - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sdmam.rs b/jh7110-vf2-12a-pac/src/uart5/sdmam.rs index 684377c..4be4fa2 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sdmam.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sdmam.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sdmam` reader - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] pub type SDMAM_R = crate::BitReader; #[doc = "Field `sdmam` writer - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] -pub type SDMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SDMAM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn sdmam(&mut self) -> SDMAM_W { - SDMAM_W::new(self) + pub fn sdmam(&mut self) -> SDMAM_W { + SDMAM_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sfe.rs b/jh7110-vf2-12a-pac/src/uart5/sfe.rs index e68b088..ed26fee 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sfe.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sfe.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sfe` reader - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] pub type SFE_R = crate::BitReader; #[doc = "Field `sfe` writer - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] -pub type SFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] #[must_use] - pub fn sfe(&mut self) -> SFE_W { - SFE_W::new(self) + pub fn sfe(&mut self) -> SFE_W { + SFE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srbr0.rs b/jh7110-vf2-12a-pac/src/uart5/srbr0.rs index 4076661..4e44d1a 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srbr0.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srbr0.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srbr1.rs b/jh7110-vf2-12a-pac/src/uart5/srbr1.rs index 2f31b75..46bc479 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srbr1.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srbr1.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srbr10.rs b/jh7110-vf2-12a-pac/src/uart5/srbr10.rs index 3639d65..70297bf 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srbr10.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srbr10.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srbr11.rs b/jh7110-vf2-12a-pac/src/uart5/srbr11.rs index 92d29b1..28d0277 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srbr11.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srbr11.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srbr12.rs b/jh7110-vf2-12a-pac/src/uart5/srbr12.rs index 52e795e..3eccd9a 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srbr12.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srbr12.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srbr13.rs b/jh7110-vf2-12a-pac/src/uart5/srbr13.rs index 50aae40..e47e4e4 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srbr13.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srbr13.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srbr14.rs b/jh7110-vf2-12a-pac/src/uart5/srbr14.rs index cb25819..8f23662 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srbr14.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srbr14.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srbr15.rs b/jh7110-vf2-12a-pac/src/uart5/srbr15.rs index b25ae46..1dac092 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srbr15.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srbr15.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srbr2.rs b/jh7110-vf2-12a-pac/src/uart5/srbr2.rs index 9f3236c..afb0617 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srbr2.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srbr2.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srbr3.rs b/jh7110-vf2-12a-pac/src/uart5/srbr3.rs index 5c1edda..0ff3650 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srbr3.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srbr3.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srbr4.rs b/jh7110-vf2-12a-pac/src/uart5/srbr4.rs index e6bee93..59560c4 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srbr4.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srbr4.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srbr5.rs b/jh7110-vf2-12a-pac/src/uart5/srbr5.rs index e599009..763e341 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srbr5.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srbr5.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srbr6.rs b/jh7110-vf2-12a-pac/src/uart5/srbr6.rs index b0155b3..78e2a40 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srbr6.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srbr6.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srbr7.rs b/jh7110-vf2-12a-pac/src/uart5/srbr7.rs index b8f9b88..0723ff0 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srbr7.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srbr7.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srbr8.rs b/jh7110-vf2-12a-pac/src/uart5/srbr8.rs index f57b044..4702cd9 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srbr8.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srbr8.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srbr9.rs b/jh7110-vf2-12a-pac/src/uart5/srbr9.rs index 3a160aa..e1a262e 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srbr9.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srbr9.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srr.rs b/jh7110-vf2-12a-pac/src/uart5/srr.rs index 6671199..fdb0c0a 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srr.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srr.rs @@ -3,31 +3,35 @@ pub type R = crate::R; #[doc = "Register `srr` writer"] pub type W = crate::W; #[doc = "Field `ur` writer - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] -pub type UR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type UR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfr` writer - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfr` writer - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFR_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] #[inline(always)] #[must_use] - pub fn ur(&mut self) -> UR_W { - UR_W::new(self) + pub fn ur(&mut self) -> UR_W { + UR_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfr(&mut self) -> RFR_W { - RFR_W::new(self) + pub fn rfr(&mut self) -> RFR_W { + RFR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfr(&mut self) -> XFR_W { - XFR_W::new(self) + pub fn xfr(&mut self) -> XFR_W { + XFR_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srt.rs b/jh7110-vf2-12a-pac/src/uart5/srt.rs index fed4f1f..da909fd 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srt.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `srt` reader - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] pub type SRT_R = crate::FieldReader; #[doc = "Field `srt` writer - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type SRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SRT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn srt(&mut self) -> SRT_W { - SRT_W::new(self) + pub fn srt(&mut self) -> SRT_W { + SRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/srts.rs b/jh7110-vf2-12a-pac/src/uart5/srts.rs index ceb0ee4..cf1e2a9 100644 --- a/jh7110-vf2-12a-pac/src/uart5/srts.rs +++ b/jh7110-vf2-12a-pac/src/uart5/srts.rs @@ -15,7 +15,7 @@ pub type SRTS_R = crate::BitReader; = 1) and FIFOs enable (FCR\\[0\\] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR\\[4\\] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] -pub type SRTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SRTS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Request to Send. This is a shadow register for the RTS bit (MCR\\[1\\]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] = 0), the rts_n signal is set low by programming MCR\\[1\\] @@ -37,10 +37,14 @@ impl W { = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn srts(&mut self) -> SRTS_W { - SRTS_W::new(self) + pub fn srts(&mut self) -> SRTS_W { + SRTS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/stet.rs b/jh7110-vf2-12a-pac/src/uart5/stet.rs index acb8ba1..503dc8a 100644 --- a/jh7110-vf2-12a-pac/src/uart5/stet.rs +++ b/jh7110-vf2-12a-pac/src/uart5/stet.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `stet` reader - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] pub type STET_R = crate::FieldReader; #[doc = "Field `stet` writer - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type STET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type STET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn stet(&mut self) -> STET_W { - STET_W::new(self) + pub fn stet(&mut self) -> STET_W { + STET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sthr0.rs b/jh7110-vf2-12a-pac/src/uart5/sthr0.rs index bfd277a..764ff05 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sthr0.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sthr0.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sthr1.rs b/jh7110-vf2-12a-pac/src/uart5/sthr1.rs index cc79733..5d58855 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sthr1.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sthr1.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sthr10.rs b/jh7110-vf2-12a-pac/src/uart5/sthr10.rs index be2659d..ffc38ff 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sthr10.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sthr10.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sthr11.rs b/jh7110-vf2-12a-pac/src/uart5/sthr11.rs index 8613dd5..1f8147f 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sthr11.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sthr11.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sthr12.rs b/jh7110-vf2-12a-pac/src/uart5/sthr12.rs index b354b10..7d816f3 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sthr12.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sthr12.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sthr13.rs b/jh7110-vf2-12a-pac/src/uart5/sthr13.rs index 06df4bc..9283b6a 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sthr13.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sthr13.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sthr14.rs b/jh7110-vf2-12a-pac/src/uart5/sthr14.rs index e181dd0..2daf622 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sthr14.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sthr14.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sthr15.rs b/jh7110-vf2-12a-pac/src/uart5/sthr15.rs index 4825778..f70715e 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sthr15.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sthr15.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sthr2.rs b/jh7110-vf2-12a-pac/src/uart5/sthr2.rs index d390f10..f1a9c77 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sthr2.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sthr2.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sthr3.rs b/jh7110-vf2-12a-pac/src/uart5/sthr3.rs index a74fdf0..06aab9e 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sthr3.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sthr3.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sthr4.rs b/jh7110-vf2-12a-pac/src/uart5/sthr4.rs index 1ee6b87..f6e7944 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sthr4.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sthr4.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sthr5.rs b/jh7110-vf2-12a-pac/src/uart5/sthr5.rs index ca360fe..7873a53 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sthr5.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sthr5.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sthr6.rs b/jh7110-vf2-12a-pac/src/uart5/sthr6.rs index 18e6fac..87c81df 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sthr6.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sthr6.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sthr7.rs b/jh7110-vf2-12a-pac/src/uart5/sthr7.rs index 27072a3..9928b3d 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sthr7.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sthr7.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sthr8.rs b/jh7110-vf2-12a-pac/src/uart5/sthr8.rs index 15060b8..565cb1d 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sthr8.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sthr8.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/sthr9.rs b/jh7110-vf2-12a-pac/src/uart5/sthr9.rs index 58af642..e64fece 100644 --- a/jh7110-vf2-12a-pac/src/uart5/sthr9.rs +++ b/jh7110-vf2-12a-pac/src/uart5/sthr9.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/tfl.rs b/jh7110-vf2-12a-pac/src/uart5/tfl.rs index e1faba6..db09fe3 100644 --- a/jh7110-vf2-12a-pac/src/uart5/tfl.rs +++ b/jh7110-vf2-12a-pac/src/uart5/tfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/tfr.rs b/jh7110-vf2-12a-pac/src/uart5/tfr.rs index 8e9ad91..714deff 100644 --- a/jh7110-vf2-12a-pac/src/uart5/tfr.rs +++ b/jh7110-vf2-12a-pac/src/uart5/tfr.rs @@ -14,7 +14,11 @@ is set to one). When FIFOs are implemented and enabled, reading this register gi } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/thr.rs b/jh7110-vf2-12a-pac/src/uart5/thr.rs index f910bd8..7845232 100644 --- a/jh7110-vf2-12a-pac/src/uart5/thr.rs +++ b/jh7110-vf2-12a-pac/src/uart5/thr.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `thr` writer - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type THR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type THR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn thr(&mut self) -> THR_W { - THR_W::new(self) + pub fn thr(&mut self) -> THR_W { + THR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/ucv.rs b/jh7110-vf2-12a-pac/src/uart5/ucv.rs index 8a3be91..6497a08 100644 --- a/jh7110-vf2-12a-pac/src/uart5/ucv.rs +++ b/jh7110-vf2-12a-pac/src/uart5/ucv.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-12a-pac/src/uart5/usr.rs b/jh7110-vf2-12a-pac/src/uart5/usr.rs index 445a085..b96417d 100644 --- a/jh7110-vf2-12a-pac/src/uart5/usr.rs +++ b/jh7110-vf2-12a-pac/src/uart5/usr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl.rs index 705b41d..665a4ad 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl.rs @@ -1,284 +1,426 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + aon_iomux_cfgsaif_syscfg_fmux0: AON_IOMUX_CFGSAIF_SYSCFG_FMUX0, + aon_iomux_cfgsaif_syscfg_fmux1: AON_IOMUX_CFGSAIF_SYSCFG_FMUX1, + aon_iomux_cfgsaif_syscfg_fmux2: AON_IOMUX_CFGSAIF_SYSCFG_FMUX2, + aon_iomux_cfgsaif_syscfg_fmux3: AON_IOMUX_CFGSAIF_SYSCFG_FMUX3, + aon_iomux_cfgsaif_syscfg_ioirq4: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4, + aon_iomux_cfgsaif_syscfg_ioirq5: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5, + aon_iomux_cfgsaif_syscfg_ioirq6: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6, + aon_iomux_cfgsaif_syscfg_ioirq7: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7, + aon_iomux_cfgsaif_syscfg_ioirq8: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8, + aon_iomux_cfgsaif_syscfg_ioirq9: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9, + aon_iomux_cfgsaif_syscfg_ioirq10: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10, + aon_iomux_cfgsaif_syscfg_ioirq11: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11, + aon_iomux_cfgsaif_syscfg48: AON_IOMUX_CFGSAIF_SYSCFG48, + aon_iomux_cfgsaif_syscfg52: AON_IOMUX_CFGSAIF_SYSCFG52, + aon_iomux_cfgsaif_syscfg56: AON_IOMUX_CFGSAIF_SYSCFG56, + aon_iomux_cfgsaif_syscfg60: AON_IOMUX_CFGSAIF_SYSCFG60, + aon_iomux_cfgsaif_syscfg64: AON_IOMUX_CFGSAIF_SYSCFG64, + aon_iomux_cfgsaif_syscfg68: AON_IOMUX_CFGSAIF_SYSCFG68, + _reserved18: [u8; 0x04], + aon_iomux_cfgsaif_syscfg76: AON_IOMUX_CFGSAIF_SYSCFG76, + _reserved19: [u8; 0x04], + aon_iomux_cfgsaif_syscfg84: AON_IOMUX_CFGSAIF_SYSCFG84, + aon_iomux_cfgsaif_syscfg88: AON_IOMUX_CFGSAIF_SYSCFG88, + aon_iomux_cfgsaif_syscfg92: AON_IOMUX_CFGSAIF_SYSCFG92, + aon_iomux_cfgsaif_syscfg96: AON_IOMUX_CFGSAIF_SYSCFG96, + aon_iomux_cfgsaif_syscfg100: AON_IOMUX_CFGSAIF_SYSCFG100, + aon_iomux_cfgsaif_syscfg104: AON_IOMUX_CFGSAIF_SYSCFG104, + aon_iomux_cfgsaif_syscfg108: AON_IOMUX_CFGSAIF_SYSCFG108, + aon_iomux_cfgsaif_syscfg112: AON_IOMUX_CFGSAIF_SYSCFG112, + aon_iomux_cfgsaif_syscfg116: AON_IOMUX_CFGSAIF_SYSCFG116, + aon_iomux_cfgsaif_syscfg120: AON_IOMUX_CFGSAIF_SYSCFG120, + aon_iomux_cfgsaif_syscfg124: AON_IOMUX_CFGSAIF_SYSCFG124, + aon_iomux_cfgsaif_syscfg128: AON_IOMUX_CFGSAIF_SYSCFG128, + aon_iomux_cfgsaif_syscfg132: AON_IOMUX_CFGSAIF_SYSCFG132, + aon_iomux_cfgsaif_syscfg136: AON_IOMUX_CFGSAIF_SYSCFG136, + aon_iomux_cfgsaif_syscfg140: AON_IOMUX_CFGSAIF_SYSCFG140, + aon_iomux_cfgsaif_syscfg144: AON_IOMUX_CFGSAIF_SYSCFG144, +} +impl RegisterBlock { #[doc = "0x00 - AON IOMUX CFG SAIF SYSCFG FMUX 0"] - pub aon_iomux_cfgsaif_syscfg_fmux0: AON_IOMUX_CFGSAIF_SYSCFG_FMUX0, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_fmux0(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_FMUX0 { + &self.aon_iomux_cfgsaif_syscfg_fmux0 + } #[doc = "0x04 - AON IOMUX CFG SAIF SYSCFG FMUX 1"] - pub aon_iomux_cfgsaif_syscfg_fmux1: AON_IOMUX_CFGSAIF_SYSCFG_FMUX1, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_fmux1(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_FMUX1 { + &self.aon_iomux_cfgsaif_syscfg_fmux1 + } #[doc = "0x08 - AON IOMUX CFG SAIF SYSCFG FMUX 2"] - pub aon_iomux_cfgsaif_syscfg_fmux2: AON_IOMUX_CFGSAIF_SYSCFG_FMUX2, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_fmux2(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_FMUX2 { + &self.aon_iomux_cfgsaif_syscfg_fmux2 + } #[doc = "0x0c - AON IOMUX CFG SAIF SYSCFG FMUX 3"] - pub aon_iomux_cfgsaif_syscfg_fmux3: AON_IOMUX_CFGSAIF_SYSCFG_FMUX3, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_fmux3(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_FMUX3 { + &self.aon_iomux_cfgsaif_syscfg_fmux3 + } #[doc = "0x10 - AON IOMUX CFG SAIF SYSCFG IOIRQ 4"] - pub aon_iomux_cfgsaif_syscfg_ioirq4: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_ioirq4(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4 { + &self.aon_iomux_cfgsaif_syscfg_ioirq4 + } #[doc = "0x14 - AON IOMUX CFG SAIF SYSCFG IOIRQ 5"] - pub aon_iomux_cfgsaif_syscfg_ioirq5: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_ioirq5(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5 { + &self.aon_iomux_cfgsaif_syscfg_ioirq5 + } #[doc = "0x18 - AON IOMUX CFG SAIF SYSCFG IOIRQ 6"] - pub aon_iomux_cfgsaif_syscfg_ioirq6: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_ioirq6(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6 { + &self.aon_iomux_cfgsaif_syscfg_ioirq6 + } #[doc = "0x1c - AON IOMUX CFG SAIF SYSCFG IOIRQ 7"] - pub aon_iomux_cfgsaif_syscfg_ioirq7: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_ioirq7(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7 { + &self.aon_iomux_cfgsaif_syscfg_ioirq7 + } #[doc = "0x20 - AON IOMUX CFG SAIF SYSCFG IOIRQ 8"] - pub aon_iomux_cfgsaif_syscfg_ioirq8: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_ioirq8(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8 { + &self.aon_iomux_cfgsaif_syscfg_ioirq8 + } #[doc = "0x24 - AON IOMUX CFG SAIF SYSCFG IOIRQ 9"] - pub aon_iomux_cfgsaif_syscfg_ioirq9: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_ioirq9(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9 { + &self.aon_iomux_cfgsaif_syscfg_ioirq9 + } #[doc = "0x28 - AON IOMUX CFG SAIF SYSCFG IOIRQ 10"] - pub aon_iomux_cfgsaif_syscfg_ioirq10: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_ioirq10(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10 { + &self.aon_iomux_cfgsaif_syscfg_ioirq10 + } #[doc = "0x2c - AON IOMUX CFG SAIF SYSCFG IOIRQ 11"] - pub aon_iomux_cfgsaif_syscfg_ioirq11: AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg_ioirq11(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11 { + &self.aon_iomux_cfgsaif_syscfg_ioirq11 + } #[doc = "0x30 - AON IOMUX CFG SAIF SYSCFG 48"] - pub aon_iomux_cfgsaif_syscfg48: AON_IOMUX_CFGSAIF_SYSCFG48, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg48(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG48 { + &self.aon_iomux_cfgsaif_syscfg48 + } #[doc = "0x34 - AON IOMUX CFG SAIF SYSCFG 52"] - pub aon_iomux_cfgsaif_syscfg52: AON_IOMUX_CFGSAIF_SYSCFG52, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg52(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG52 { + &self.aon_iomux_cfgsaif_syscfg52 + } #[doc = "0x38 - AON IOMUX CFG SAIF SYSCFG 56"] - pub aon_iomux_cfgsaif_syscfg56: AON_IOMUX_CFGSAIF_SYSCFG56, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg56(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG56 { + &self.aon_iomux_cfgsaif_syscfg56 + } #[doc = "0x3c - AON IOMUX CFG SAIF SYSCFG 60"] - pub aon_iomux_cfgsaif_syscfg60: AON_IOMUX_CFGSAIF_SYSCFG60, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg60(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG60 { + &self.aon_iomux_cfgsaif_syscfg60 + } #[doc = "0x40 - AON IOMUX CFG SAIF SYSCFG 64"] - pub aon_iomux_cfgsaif_syscfg64: AON_IOMUX_CFGSAIF_SYSCFG64, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg64(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG64 { + &self.aon_iomux_cfgsaif_syscfg64 + } #[doc = "0x44 - AON IOMUX CFG SAIF SYSCFG 68"] - pub aon_iomux_cfgsaif_syscfg68: AON_IOMUX_CFGSAIF_SYSCFG68, - _reserved18: [u8; 0x04], + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg68(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG68 { + &self.aon_iomux_cfgsaif_syscfg68 + } #[doc = "0x4c - AON IOMUX CFG SAIF SYSCFG 76"] - pub aon_iomux_cfgsaif_syscfg76: AON_IOMUX_CFGSAIF_SYSCFG76, - _reserved19: [u8; 0x04], + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg76(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG76 { + &self.aon_iomux_cfgsaif_syscfg76 + } #[doc = "0x54 - AON IOMUX CFG SAIF SYSCFG 84"] - pub aon_iomux_cfgsaif_syscfg84: AON_IOMUX_CFGSAIF_SYSCFG84, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg84(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG84 { + &self.aon_iomux_cfgsaif_syscfg84 + } #[doc = "0x58 - AON IOMUX CFG SAIF SYSCFG 88"] - pub aon_iomux_cfgsaif_syscfg88: AON_IOMUX_CFGSAIF_SYSCFG88, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg88(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG88 { + &self.aon_iomux_cfgsaif_syscfg88 + } #[doc = "0x5c - AON IOMUX CFG SAIF SYSCFG 92"] - pub aon_iomux_cfgsaif_syscfg92: AON_IOMUX_CFGSAIF_SYSCFG92, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg92(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG92 { + &self.aon_iomux_cfgsaif_syscfg92 + } #[doc = "0x60 - AON IOMUX CFG SAIF SYSCFG 96"] - pub aon_iomux_cfgsaif_syscfg96: AON_IOMUX_CFGSAIF_SYSCFG96, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg96(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG96 { + &self.aon_iomux_cfgsaif_syscfg96 + } #[doc = "0x64 - AON IOMUX CFG SAIF SYSCFG 100"] - pub aon_iomux_cfgsaif_syscfg100: AON_IOMUX_CFGSAIF_SYSCFG100, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg100(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG100 { + &self.aon_iomux_cfgsaif_syscfg100 + } #[doc = "0x68 - AON IOMUX CFG SAIF SYSCFG 104"] - pub aon_iomux_cfgsaif_syscfg104: AON_IOMUX_CFGSAIF_SYSCFG104, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg104(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG104 { + &self.aon_iomux_cfgsaif_syscfg104 + } #[doc = "0x6c - AON IOMUX CFG SAIF SYSCFG 108"] - pub aon_iomux_cfgsaif_syscfg108: AON_IOMUX_CFGSAIF_SYSCFG108, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg108(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG108 { + &self.aon_iomux_cfgsaif_syscfg108 + } #[doc = "0x70 - AON IOMUX CFG SAIF SYSCFG 112"] - pub aon_iomux_cfgsaif_syscfg112: AON_IOMUX_CFGSAIF_SYSCFG112, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg112(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG112 { + &self.aon_iomux_cfgsaif_syscfg112 + } #[doc = "0x74 - AON IOMUX CFG SAIF SYSCFG 116"] - pub aon_iomux_cfgsaif_syscfg116: AON_IOMUX_CFGSAIF_SYSCFG116, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg116(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG116 { + &self.aon_iomux_cfgsaif_syscfg116 + } #[doc = "0x78 - AON IOMUX CFG SAIF SYSCFG 120"] - pub aon_iomux_cfgsaif_syscfg120: AON_IOMUX_CFGSAIF_SYSCFG120, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg120(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG120 { + &self.aon_iomux_cfgsaif_syscfg120 + } #[doc = "0x7c - AON IOMUX CFG SAIF SYSCFG 124"] - pub aon_iomux_cfgsaif_syscfg124: AON_IOMUX_CFGSAIF_SYSCFG124, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg124(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG124 { + &self.aon_iomux_cfgsaif_syscfg124 + } #[doc = "0x80 - AON IOMUX CFG SAIF SYSCFG 128"] - pub aon_iomux_cfgsaif_syscfg128: AON_IOMUX_CFGSAIF_SYSCFG128, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg128(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG128 { + &self.aon_iomux_cfgsaif_syscfg128 + } #[doc = "0x84 - AON IOMUX CFG SAIF SYSCFG 132"] - pub aon_iomux_cfgsaif_syscfg132: AON_IOMUX_CFGSAIF_SYSCFG132, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg132(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG132 { + &self.aon_iomux_cfgsaif_syscfg132 + } #[doc = "0x88 - AON IOMUX CFG SAIF SYSCFG 136"] - pub aon_iomux_cfgsaif_syscfg136: AON_IOMUX_CFGSAIF_SYSCFG136, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg136(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG136 { + &self.aon_iomux_cfgsaif_syscfg136 + } #[doc = "0x8c - AON IOMUX CFG SAIF SYSCFG 140"] - pub aon_iomux_cfgsaif_syscfg140: AON_IOMUX_CFGSAIF_SYSCFG140, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg140(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG140 { + &self.aon_iomux_cfgsaif_syscfg140 + } #[doc = "0x90 - AON IOMUX CFG SAIF SYSCFG 144"] - pub aon_iomux_cfgsaif_syscfg144: AON_IOMUX_CFGSAIF_SYSCFG144, + #[inline(always)] + pub const fn aon_iomux_cfgsaif_syscfg144(&self) -> &AON_IOMUX_CFGSAIF_SYSCFG144 { + &self.aon_iomux_cfgsaif_syscfg144 + } } -#[doc = "aon_iomux_cfgsaif_syscfg_fmux0 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_fmux0`] +#[doc = "aon_iomux_cfgsaif_syscfg_fmux0 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_fmux0`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_FMUX0 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 0"] pub mod aon_iomux_cfgsaif_syscfg_fmux0; -#[doc = "aon_iomux_cfgsaif_syscfg_fmux1 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_fmux1`] +#[doc = "aon_iomux_cfgsaif_syscfg_fmux1 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_fmux1`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_FMUX1 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 1"] pub mod aon_iomux_cfgsaif_syscfg_fmux1; -#[doc = "aon_iomux_cfgsaif_syscfg_fmux2 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_fmux2`] +#[doc = "aon_iomux_cfgsaif_syscfg_fmux2 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_fmux2`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_FMUX2 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 2"] pub mod aon_iomux_cfgsaif_syscfg_fmux2; -#[doc = "aon_iomux_cfgsaif_syscfg_fmux3 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_fmux3`] +#[doc = "aon_iomux_cfgsaif_syscfg_fmux3 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG FMUX 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_fmux3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_fmux3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_fmux3`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_FMUX3 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG FMUX 3"] pub mod aon_iomux_cfgsaif_syscfg_fmux3; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq4 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_ioirq4`] +#[doc = "aon_iomux_cfgsaif_syscfg_ioirq4 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq4`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ4 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 4"] pub mod aon_iomux_cfgsaif_syscfg_ioirq4; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq5 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_ioirq5`] +#[doc = "aon_iomux_cfgsaif_syscfg_ioirq5 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq5`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ5 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 5"] pub mod aon_iomux_cfgsaif_syscfg_ioirq5; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq6 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq6::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_ioirq6`] +#[doc = "aon_iomux_cfgsaif_syscfg_ioirq6 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq6::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq6`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ6 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 6"] pub mod aon_iomux_cfgsaif_syscfg_ioirq6; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq7 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq7::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_ioirq7`] +#[doc = "aon_iomux_cfgsaif_syscfg_ioirq7 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq7::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq7`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ7 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 7"] pub mod aon_iomux_cfgsaif_syscfg_ioirq7; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq8 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_ioirq8`] +#[doc = "aon_iomux_cfgsaif_syscfg_ioirq8 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq8`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ8 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 8"] pub mod aon_iomux_cfgsaif_syscfg_ioirq8; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq9 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq9::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_ioirq9`] +#[doc = "aon_iomux_cfgsaif_syscfg_ioirq9 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq9::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq9`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ9 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 9"] pub mod aon_iomux_cfgsaif_syscfg_ioirq9; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq10 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq10::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_ioirq10`] +#[doc = "aon_iomux_cfgsaif_syscfg_ioirq10 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq10::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq10`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ10 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 10"] pub mod aon_iomux_cfgsaif_syscfg_ioirq10; -#[doc = "aon_iomux_cfgsaif_syscfg_ioirq11 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq11::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg_ioirq11`] +#[doc = "aon_iomux_cfgsaif_syscfg_ioirq11 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG IOIRQ 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg_ioirq11::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg_ioirq11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg_ioirq11`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG_IOIRQ11 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG IOIRQ 11"] pub mod aon_iomux_cfgsaif_syscfg_ioirq11; -#[doc = "aon_iomux_cfgsaif_syscfg48 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg48`] +#[doc = "aon_iomux_cfgsaif_syscfg48 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg48`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG48 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 48"] pub mod aon_iomux_cfgsaif_syscfg48; -#[doc = "aon_iomux_cfgsaif_syscfg52 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg52`] +#[doc = "aon_iomux_cfgsaif_syscfg52 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg52`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG52 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 52"] pub mod aon_iomux_cfgsaif_syscfg52; -#[doc = "aon_iomux_cfgsaif_syscfg56 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg56`] +#[doc = "aon_iomux_cfgsaif_syscfg56 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg56`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG56 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 56"] pub mod aon_iomux_cfgsaif_syscfg56; -#[doc = "aon_iomux_cfgsaif_syscfg60 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg60`] +#[doc = "aon_iomux_cfgsaif_syscfg60 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg60`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG60 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 60"] pub mod aon_iomux_cfgsaif_syscfg60; -#[doc = "aon_iomux_cfgsaif_syscfg64 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg64`] +#[doc = "aon_iomux_cfgsaif_syscfg64 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg64`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG64 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 64"] pub mod aon_iomux_cfgsaif_syscfg64; -#[doc = "aon_iomux_cfgsaif_syscfg68 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg68`] +#[doc = "aon_iomux_cfgsaif_syscfg68 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg68`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG68 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 68"] pub mod aon_iomux_cfgsaif_syscfg68; -#[doc = "aon_iomux_cfgsaif_syscfg76 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg76`] +#[doc = "aon_iomux_cfgsaif_syscfg76 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg76`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG76 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 76"] pub mod aon_iomux_cfgsaif_syscfg76; -#[doc = "aon_iomux_cfgsaif_syscfg84 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg84`] +#[doc = "aon_iomux_cfgsaif_syscfg84 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg84`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG84 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 84"] pub mod aon_iomux_cfgsaif_syscfg84; -#[doc = "aon_iomux_cfgsaif_syscfg88 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg88`] +#[doc = "aon_iomux_cfgsaif_syscfg88 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg88`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG88 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 88"] pub mod aon_iomux_cfgsaif_syscfg88; -#[doc = "aon_iomux_cfgsaif_syscfg92 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg92`] +#[doc = "aon_iomux_cfgsaif_syscfg92 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg92`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG92 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 92"] pub mod aon_iomux_cfgsaif_syscfg92; -#[doc = "aon_iomux_cfgsaif_syscfg96 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg96`] +#[doc = "aon_iomux_cfgsaif_syscfg96 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg96`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG96 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 96"] pub mod aon_iomux_cfgsaif_syscfg96; -#[doc = "aon_iomux_cfgsaif_syscfg100 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg100`] +#[doc = "aon_iomux_cfgsaif_syscfg100 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg100`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG100 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 100"] pub mod aon_iomux_cfgsaif_syscfg100; -#[doc = "aon_iomux_cfgsaif_syscfg104 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg104`] +#[doc = "aon_iomux_cfgsaif_syscfg104 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg104`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG104 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 104"] pub mod aon_iomux_cfgsaif_syscfg104; -#[doc = "aon_iomux_cfgsaif_syscfg108 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg108`] +#[doc = "aon_iomux_cfgsaif_syscfg108 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg108`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG108 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 108"] pub mod aon_iomux_cfgsaif_syscfg108; -#[doc = "aon_iomux_cfgsaif_syscfg112 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg112`] +#[doc = "aon_iomux_cfgsaif_syscfg112 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg112`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG112 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 112"] pub mod aon_iomux_cfgsaif_syscfg112; -#[doc = "aon_iomux_cfgsaif_syscfg116 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg116`] +#[doc = "aon_iomux_cfgsaif_syscfg116 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg116`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG116 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 116"] pub mod aon_iomux_cfgsaif_syscfg116; -#[doc = "aon_iomux_cfgsaif_syscfg120 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg120`] +#[doc = "aon_iomux_cfgsaif_syscfg120 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg120`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG120 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 120"] pub mod aon_iomux_cfgsaif_syscfg120; -#[doc = "aon_iomux_cfgsaif_syscfg124 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg124`] +#[doc = "aon_iomux_cfgsaif_syscfg124 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg124`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG124 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 124"] pub mod aon_iomux_cfgsaif_syscfg124; -#[doc = "aon_iomux_cfgsaif_syscfg128 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg128`] +#[doc = "aon_iomux_cfgsaif_syscfg128 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg128`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG128 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 128"] pub mod aon_iomux_cfgsaif_syscfg128; -#[doc = "aon_iomux_cfgsaif_syscfg132 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg132::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg132::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg132`] +#[doc = "aon_iomux_cfgsaif_syscfg132 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg132::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg132::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg132`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG132 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 132"] pub mod aon_iomux_cfgsaif_syscfg132; -#[doc = "aon_iomux_cfgsaif_syscfg136 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg136`] +#[doc = "aon_iomux_cfgsaif_syscfg136 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg136`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG136 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 136"] pub mod aon_iomux_cfgsaif_syscfg136; -#[doc = "aon_iomux_cfgsaif_syscfg140 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg140::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg140::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg140`] +#[doc = "aon_iomux_cfgsaif_syscfg140 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg140::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg140::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg140`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG140 = crate::Reg; #[doc = "AON IOMUX CFG SAIF SYSCFG 140"] pub mod aon_iomux_cfgsaif_syscfg140; -#[doc = "aon_iomux_cfgsaif_syscfg144 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg144::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg144::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_iomux_cfgsaif_syscfg144`] +#[doc = "aon_iomux_cfgsaif_syscfg144 (rw) register accessor: AON IOMUX CFG SAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_iomux_cfgsaif_syscfg144::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_iomux_cfgsaif_syscfg144::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_iomux_cfgsaif_syscfg144`] module"] pub type AON_IOMUX_CFGSAIF_SYSCFG144 = crate::Reg; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg100.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg100.rs index cc40d71..7a6eb49 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg100.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg100.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_rxd1_syscon` reader - padcfg_pad_gmac0_rxd1_syscon"] pub type PADCFG_PAD_GMAC0_RXD1_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_rxd1_syscon` writer - padcfg_pad_gmac0_rxd1_syscon"] -pub type PADCFG_PAD_GMAC0_RXD1_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_RXD1_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd1_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_rxd1_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_RXD1_SYSCON_W { - PADCFG_PAD_GMAC0_RXD1_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_RXD1_SYSCON_W { + PADCFG_PAD_GMAC0_RXD1_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg104.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg104.rs index 708564a..c7f5618 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg104.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg104.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_rxd2_syscon` reader - padcfg_pad_gmac0_rxd2_syscon"] pub type PADCFG_PAD_GMAC0_RXD2_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_rxd2_syscon` writer - padcfg_pad_gmac0_rxd2_syscon"] -pub type PADCFG_PAD_GMAC0_RXD2_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_RXD2_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd2_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_rxd2_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_RXD2_SYSCON_W { - PADCFG_PAD_GMAC0_RXD2_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_RXD2_SYSCON_W { + PADCFG_PAD_GMAC0_RXD2_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg108.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg108.rs index 1498c6f..31aaf9e 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg108.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg108.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_rxd3_syscon` reader - padcfg_pad_gmac0_rxd3_syscon"] pub type PADCFG_PAD_GMAC0_RXD3_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_rxd3_syscon` writer - padcfg_pad_gmac0_rxd3_syscon"] -pub type PADCFG_PAD_GMAC0_RXD3_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_RXD3_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxd3_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_rxd3_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_RXD3_SYSCON_W { - PADCFG_PAD_GMAC0_RXD3_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_RXD3_SYSCON_W { + PADCFG_PAD_GMAC0_RXD3_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg112.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg112.rs index db26577..7b68d46 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg112.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg112.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_rxdv_syscon` reader - padcfg_pad_gmac0_rxdv_syscon"] pub type PADCFG_PAD_GMAC0_RXDV_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_rxdv_syscon` writer - padcfg_pad_gmac0_rxdv_syscon"] -pub type PADCFG_PAD_GMAC0_RXDV_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_RXDV_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxdv_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_rxdv_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_RXDV_SYSCON_W { - PADCFG_PAD_GMAC0_RXDV_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_RXDV_SYSCON_W { + PADCFG_PAD_GMAC0_RXDV_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg116.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg116.rs index 76cd0ed..5a9c872 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg116.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg116.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_rxc_syscon` reader - padcfg_pad_gmac0_rxc_syscon"] pub type PADCFG_PAD_GMAC0_RXC_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_rxc_syscon` writer - padcfg_pad_gmac0_rxc_syscon"] -pub type PADCFG_PAD_GMAC0_RXC_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_RXC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_rxc_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_rxc_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_RXC_SYSCON_W { - PADCFG_PAD_GMAC0_RXC_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_RXC_SYSCON_W { + PADCFG_PAD_GMAC0_RXC_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg120.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg120.rs index f0a90d5..71a2e97 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg120.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg120.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_txd0_syscon` reader - padcfg_pad_gmac0_txd0_syscon"] pub type PADCFG_PAD_GMAC0_TXD0_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_txd0_syscon` writer - padcfg_pad_gmac0_txd0_syscon"] -pub type PADCFG_PAD_GMAC0_TXD0_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_TXD0_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd0_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_txd0_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_TXD0_SYSCON_W { - PADCFG_PAD_GMAC0_TXD0_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_TXD0_SYSCON_W { + PADCFG_PAD_GMAC0_TXD0_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg124.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg124.rs index 475164a..dda00ba 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg124.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg124.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_txd1_syscon` reader - padcfg_pad_gmac0_txd1_syscon"] pub type PADCFG_PAD_GMAC0_TXD1_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_txd1_syscon` writer - padcfg_pad_gmac0_txd1_syscon"] -pub type PADCFG_PAD_GMAC0_TXD1_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_TXD1_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd1_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_txd1_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_TXD1_SYSCON_W { - PADCFG_PAD_GMAC0_TXD1_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_TXD1_SYSCON_W { + PADCFG_PAD_GMAC0_TXD1_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg128.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg128.rs index 4ae5c62..18bc4c0 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg128.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg128.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_txd2_syscon` reader - padcfg_pad_gmac0_txd2_syscon"] pub type PADCFG_PAD_GMAC0_TXD2_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_txd2_syscon` writer - padcfg_pad_gmac0_txd2_syscon"] -pub type PADCFG_PAD_GMAC0_TXD2_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_TXD2_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd2_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_txd2_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_TXD2_SYSCON_W { - PADCFG_PAD_GMAC0_TXD2_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_TXD2_SYSCON_W { + PADCFG_PAD_GMAC0_TXD2_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg132.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg132.rs index 403cd3e..b8888c2 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg132.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg132.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_txd3_syscon` reader - padcfg_pad_gmac0_txd3_syscon"] pub type PADCFG_PAD_GMAC0_TXD3_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_txd3_syscon` writer - padcfg_pad_gmac0_txd3_syscon"] -pub type PADCFG_PAD_GMAC0_TXD3_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_TXD3_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_txd3_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_txd3_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_TXD3_SYSCON_W { - PADCFG_PAD_GMAC0_TXD3_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_TXD3_SYSCON_W { + PADCFG_PAD_GMAC0_TXD3_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg136.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg136.rs index 157b06f..1423c0e 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg136.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg136.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_txen_syscon` reader - padcfg_pad_gmac0_txen_syscon"] pub type PADCFG_PAD_GMAC0_TXEN_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_txen_syscon` writer - padcfg_pad_gmac0_txen_syscon"] -pub type PADCFG_PAD_GMAC0_TXEN_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_TXEN_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_txen_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_txen_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_TXEN_SYSCON_W { - PADCFG_PAD_GMAC0_TXEN_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_TXEN_SYSCON_W { + PADCFG_PAD_GMAC0_TXEN_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg140.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg140.rs index 1986c87..3328694 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg140.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg140.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_txc_syscon` reader - padcfg_pad_gmac0_txc_syscon"] pub type PADCFG_PAD_GMAC0_TXC_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_txc_syscon` writer - padcfg_pad_gmac0_txc_syscon"] -pub type PADCFG_PAD_GMAC0_TXC_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_TXC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_txc_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_txc_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_TXC_SYSCON_W { - PADCFG_PAD_GMAC0_TXC_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_TXC_SYSCON_W { + PADCFG_PAD_GMAC0_TXC_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg144.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg144.rs index 6db0a97..4e9cfe6 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg144.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg144.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `pad_gmac0_rxc_func_sel` reader - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] pub type PAD_GMAC0_RXC_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gmac0_rxc_func_sel` writer - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] -pub type PAD_GMAC0_RXC_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PAD_GMAC0_RXC_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn pad_gmac0_rxc_func_sel( &mut self, - ) -> PAD_GMAC0_RXC_FUNC_SEL_W { - PAD_GMAC0_RXC_FUNC_SEL_W::new(self) + ) -> PAD_GMAC0_RXC_FUNC_SEL_W { + PAD_GMAC0_RXC_FUNC_SEL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs index b321542..6e37db2 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg48.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_testen_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type PADCFG_PAD_TESTEN_POS_R = crate::BitReader; #[doc = "Field `padcfg_pad_testen_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_TESTEN_POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_TESTEN_POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_testen_pos( &mut self, - ) -> PADCFG_PAD_TESTEN_POS_W { - PADCFG_PAD_TESTEN_POS_W::new(self) + ) -> PADCFG_PAD_TESTEN_POS_W { + PADCFG_PAD_TESTEN_POS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs index 8ef1a98..e6eee84 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg52.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_rgpio0_ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type PADCFG_PAD_RGPIO0_IE_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio0_ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO0_IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO0_IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio0_ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type PADCFG_PAD_RGPIO0_DS_R = crate::FieldReader; #[doc = "Field `padcfg_pad_rgpio0_ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO0_DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_RGPIO0_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `padcfg_pad_rgpio0_pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PADCFG_PAD_RGPIO0_PU_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio0_pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO0_PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO0_PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio0_pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PADCFG_PAD_RGPIO0_PD_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio0_pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO0_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO0_PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio0_slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type PADCFG_PAD_RGPIO0_SLEW_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio0_slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO0_SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO0_SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio0_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type PADCFG_PAD_RGPIO0_SMT_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio0_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO0_SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO0_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio0_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type PADCFG_PAD_RGPIO0_POS_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio0_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO0_POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO0_POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -73,58 +73,62 @@ impl W { #[must_use] pub fn padcfg_pad_rgpio0_ie( &mut self, - ) -> PADCFG_PAD_RGPIO0_IE_W { - PADCFG_PAD_RGPIO0_IE_W::new(self) + ) -> PADCFG_PAD_RGPIO0_IE_W { + PADCFG_PAD_RGPIO0_IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio0_ds( &mut self, - ) -> PADCFG_PAD_RGPIO0_DS_W { - PADCFG_PAD_RGPIO0_DS_W::new(self) + ) -> PADCFG_PAD_RGPIO0_DS_W { + PADCFG_PAD_RGPIO0_DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio0_pu( &mut self, - ) -> PADCFG_PAD_RGPIO0_PU_W { - PADCFG_PAD_RGPIO0_PU_W::new(self) + ) -> PADCFG_PAD_RGPIO0_PU_W { + PADCFG_PAD_RGPIO0_PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio0_pd( &mut self, - ) -> PADCFG_PAD_RGPIO0_PD_W { - PADCFG_PAD_RGPIO0_PD_W::new(self) + ) -> PADCFG_PAD_RGPIO0_PD_W { + PADCFG_PAD_RGPIO0_PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio0_slew( &mut self, - ) -> PADCFG_PAD_RGPIO0_SLEW_W { - PADCFG_PAD_RGPIO0_SLEW_W::new(self) + ) -> PADCFG_PAD_RGPIO0_SLEW_W { + PADCFG_PAD_RGPIO0_SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio0_smt( &mut self, - ) -> PADCFG_PAD_RGPIO0_SMT_W { - PADCFG_PAD_RGPIO0_SMT_W::new(self) + ) -> PADCFG_PAD_RGPIO0_SMT_W { + PADCFG_PAD_RGPIO0_SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio0_pos( &mut self, - ) -> PADCFG_PAD_RGPIO0_POS_W { - PADCFG_PAD_RGPIO0_POS_W::new(self) + ) -> PADCFG_PAD_RGPIO0_POS_W { + PADCFG_PAD_RGPIO0_POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs index 47270f1..e4df2d1 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg56.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_rgpio1_ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type PADCFG_PAD_RGPIO1_IE_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio1_ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO1_IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO1_IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio1_ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type PADCFG_PAD_RGPIO1_DS_R = crate::FieldReader; #[doc = "Field `padcfg_pad_rgpio1_ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO1_DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_RGPIO1_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `padcfg_pad_rgpio1_pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PADCFG_PAD_RGPIO1_PU_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio1_pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO1_PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO1_PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio1_pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PADCFG_PAD_RGPIO1_PD_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio1_pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO1_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO1_PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio1_slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type PADCFG_PAD_RGPIO1_SLEW_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio1_slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO1_SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO1_SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio1_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type PADCFG_PAD_RGPIO1_SMT_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio1_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO1_SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO1_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio1_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type PADCFG_PAD_RGPIO1_POS_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio1_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO1_POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO1_POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -73,58 +73,62 @@ impl W { #[must_use] pub fn padcfg_pad_rgpio1_ie( &mut self, - ) -> PADCFG_PAD_RGPIO1_IE_W { - PADCFG_PAD_RGPIO1_IE_W::new(self) + ) -> PADCFG_PAD_RGPIO1_IE_W { + PADCFG_PAD_RGPIO1_IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio1_ds( &mut self, - ) -> PADCFG_PAD_RGPIO1_DS_W { - PADCFG_PAD_RGPIO1_DS_W::new(self) + ) -> PADCFG_PAD_RGPIO1_DS_W { + PADCFG_PAD_RGPIO1_DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio1_pu( &mut self, - ) -> PADCFG_PAD_RGPIO1_PU_W { - PADCFG_PAD_RGPIO1_PU_W::new(self) + ) -> PADCFG_PAD_RGPIO1_PU_W { + PADCFG_PAD_RGPIO1_PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio1_pd( &mut self, - ) -> PADCFG_PAD_RGPIO1_PD_W { - PADCFG_PAD_RGPIO1_PD_W::new(self) + ) -> PADCFG_PAD_RGPIO1_PD_W { + PADCFG_PAD_RGPIO1_PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio1_slew( &mut self, - ) -> PADCFG_PAD_RGPIO1_SLEW_W { - PADCFG_PAD_RGPIO1_SLEW_W::new(self) + ) -> PADCFG_PAD_RGPIO1_SLEW_W { + PADCFG_PAD_RGPIO1_SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio1_smt( &mut self, - ) -> PADCFG_PAD_RGPIO1_SMT_W { - PADCFG_PAD_RGPIO1_SMT_W::new(self) + ) -> PADCFG_PAD_RGPIO1_SMT_W { + PADCFG_PAD_RGPIO1_SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio1_pos( &mut self, - ) -> PADCFG_PAD_RGPIO1_POS_W { - PADCFG_PAD_RGPIO1_POS_W::new(self) + ) -> PADCFG_PAD_RGPIO1_POS_W { + PADCFG_PAD_RGPIO1_POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs index 0017ce6..5a6586e 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg60.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_rgpio2_ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type PADCFG_PAD_RGPIO2_IE_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio2_ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO2_IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO2_IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio2_ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type PADCFG_PAD_RGPIO2_DS_R = crate::FieldReader; #[doc = "Field `padcfg_pad_rgpio2_ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO2_DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_RGPIO2_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `padcfg_pad_rgpio2_pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PADCFG_PAD_RGPIO2_PU_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio2_pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO2_PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO2_PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio2_pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PADCFG_PAD_RGPIO2_PD_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio2_pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO2_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO2_PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio2_slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type PADCFG_PAD_RGPIO2_SLEW_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio2_slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO2_SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO2_SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio2_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type PADCFG_PAD_RGPIO2_SMT_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio2_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO2_SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO2_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio2_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type PADCFG_PAD_RGPIO2_POS_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio2_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO2_POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO2_POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -73,58 +73,62 @@ impl W { #[must_use] pub fn padcfg_pad_rgpio2_ie( &mut self, - ) -> PADCFG_PAD_RGPIO2_IE_W { - PADCFG_PAD_RGPIO2_IE_W::new(self) + ) -> PADCFG_PAD_RGPIO2_IE_W { + PADCFG_PAD_RGPIO2_IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio2_ds( &mut self, - ) -> PADCFG_PAD_RGPIO2_DS_W { - PADCFG_PAD_RGPIO2_DS_W::new(self) + ) -> PADCFG_PAD_RGPIO2_DS_W { + PADCFG_PAD_RGPIO2_DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio2_pu( &mut self, - ) -> PADCFG_PAD_RGPIO2_PU_W { - PADCFG_PAD_RGPIO2_PU_W::new(self) + ) -> PADCFG_PAD_RGPIO2_PU_W { + PADCFG_PAD_RGPIO2_PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio2_pd( &mut self, - ) -> PADCFG_PAD_RGPIO2_PD_W { - PADCFG_PAD_RGPIO2_PD_W::new(self) + ) -> PADCFG_PAD_RGPIO2_PD_W { + PADCFG_PAD_RGPIO2_PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio2_slew( &mut self, - ) -> PADCFG_PAD_RGPIO2_SLEW_W { - PADCFG_PAD_RGPIO2_SLEW_W::new(self) + ) -> PADCFG_PAD_RGPIO2_SLEW_W { + PADCFG_PAD_RGPIO2_SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio2_smt( &mut self, - ) -> PADCFG_PAD_RGPIO2_SMT_W { - PADCFG_PAD_RGPIO2_SMT_W::new(self) + ) -> PADCFG_PAD_RGPIO2_SMT_W { + PADCFG_PAD_RGPIO2_SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio2_pos( &mut self, - ) -> PADCFG_PAD_RGPIO2_POS_W { - PADCFG_PAD_RGPIO2_POS_W::new(self) + ) -> PADCFG_PAD_RGPIO2_POS_W { + PADCFG_PAD_RGPIO2_POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs index 9c5e498..8dfbee5 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg64.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_rgpio3_ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type PADCFG_PAD_RGPIO3_IE_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio3_ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type PADCFG_PAD_RGPIO3_IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO3_IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio3_ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type PADCFG_PAD_RGPIO3_DS_R = crate::FieldReader; #[doc = "Field `padcfg_pad_rgpio3_ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type PADCFG_PAD_RGPIO3_DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_RGPIO3_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `padcfg_pad_rgpio3_pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PADCFG_PAD_RGPIO3_PU_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio3_pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO3_PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO3_PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio3_pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PADCFG_PAD_RGPIO3_PD_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio3_pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PADCFG_PAD_RGPIO3_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO3_PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio3_slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type PADCFG_PAD_RGPIO3_SLEW_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio3_slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type PADCFG_PAD_RGPIO3_SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO3_SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio3_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type PADCFG_PAD_RGPIO3_SMT_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio3_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type PADCFG_PAD_RGPIO3_SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO3_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rgpio3_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type PADCFG_PAD_RGPIO3_POS_R = crate::BitReader; #[doc = "Field `padcfg_pad_rgpio3_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RGPIO3_POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RGPIO3_POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -73,58 +73,62 @@ impl W { #[must_use] pub fn padcfg_pad_rgpio3_ie( &mut self, - ) -> PADCFG_PAD_RGPIO3_IE_W { - PADCFG_PAD_RGPIO3_IE_W::new(self) + ) -> PADCFG_PAD_RGPIO3_IE_W { + PADCFG_PAD_RGPIO3_IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio3_ds( &mut self, - ) -> PADCFG_PAD_RGPIO3_DS_W { - PADCFG_PAD_RGPIO3_DS_W::new(self) + ) -> PADCFG_PAD_RGPIO3_DS_W { + PADCFG_PAD_RGPIO3_DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio3_pu( &mut self, - ) -> PADCFG_PAD_RGPIO3_PU_W { - PADCFG_PAD_RGPIO3_PU_W::new(self) + ) -> PADCFG_PAD_RGPIO3_PU_W { + PADCFG_PAD_RGPIO3_PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio3_pd( &mut self, - ) -> PADCFG_PAD_RGPIO3_PD_W { - PADCFG_PAD_RGPIO3_PD_W::new(self) + ) -> PADCFG_PAD_RGPIO3_PD_W { + PADCFG_PAD_RGPIO3_PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio3_slew( &mut self, - ) -> PADCFG_PAD_RGPIO3_SLEW_W { - PADCFG_PAD_RGPIO3_SLEW_W::new(self) + ) -> PADCFG_PAD_RGPIO3_SLEW_W { + PADCFG_PAD_RGPIO3_SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio3_smt( &mut self, - ) -> PADCFG_PAD_RGPIO3_SMT_W { - PADCFG_PAD_RGPIO3_SMT_W::new(self) + ) -> PADCFG_PAD_RGPIO3_SMT_W { + PADCFG_PAD_RGPIO3_SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rgpio3_pos( &mut self, - ) -> PADCFG_PAD_RGPIO3_POS_W { - PADCFG_PAD_RGPIO3_POS_W::new(self) + ) -> PADCFG_PAD_RGPIO3_POS_W { + PADCFG_PAD_RGPIO3_POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs index aee1a8b..6c5a65b 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg68.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_rstn_smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] pub type PADCFG_PAD_RSTN_SMT_R = crate::BitReader; #[doc = "Field `padcfg_pad_rstn_smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] -pub type PADCFG_PAD_RSTN_SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RSTN_SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `padcfg_pad_rstn_pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] pub type PADCFG_PAD_RSTN_POS_R = crate::BitReader; #[doc = "Field `padcfg_pad_rstn_pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] -pub type PADCFG_PAD_RSTN_POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PADCFG_PAD_RSTN_POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled"] #[inline(always)] @@ -28,18 +28,22 @@ impl W { #[must_use] pub fn padcfg_pad_rstn_smt( &mut self, - ) -> PADCFG_PAD_RSTN_SMT_W { - PADCFG_PAD_RSTN_SMT_W::new(self) + ) -> PADCFG_PAD_RSTN_SMT_W { + PADCFG_PAD_RSTN_SMT_W::new(self, 0) } #[doc = "Bit 1 - Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] pub fn padcfg_pad_rstn_pos( &mut self, - ) -> PADCFG_PAD_RSTN_POS_W { - PADCFG_PAD_RSTN_POS_W::new(self) + ) -> PADCFG_PAD_RSTN_POS_W { + PADCFG_PAD_RSTN_POS_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs index b528e85..452613c 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg76.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_rtc_ds` reader - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] pub type PADCFG_PAD_RTC_DS_R = crate::FieldReader; #[doc = "Field `padcfg_pad_rtc_ds` writer - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] -pub type PADCFG_PAD_RTC_DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_RTC_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] #[inline(always)] #[must_use] - pub fn padcfg_pad_rtc_ds(&mut self) -> PADCFG_PAD_RTC_DS_W { - PADCFG_PAD_RTC_DS_W::new(self) + pub fn padcfg_pad_rtc_ds(&mut self) -> PADCFG_PAD_RTC_DS_W { + PADCFG_PAD_RTC_DS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs index 4a8e766..067aebb 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg84.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_osc_ds` reader - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] pub type PADCFG_PAD_OSC_DS_R = crate::FieldReader; #[doc = "Field `padcfg_pad_osc_ds` writer - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] -pub type PADCFG_PAD_OSC_DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_OSC_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA."] #[inline(always)] #[must_use] - pub fn padcfg_pad_osc_ds(&mut self) -> PADCFG_PAD_OSC_DS_W { - PADCFG_PAD_OSC_DS_W::new(self) + pub fn padcfg_pad_osc_ds(&mut self) -> PADCFG_PAD_OSC_DS_W { + PADCFG_PAD_OSC_DS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs index bf3a970..f744712 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg88.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_mdc_syscon` reader - padcfg_pad_gmac0_mdc_syscon"] pub type PADCFG_PAD_GMAC0_MDC_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_mdc_syscon` writer - padcfg_pad_gmac0_mdc_syscon"] -pub type PADCFG_PAD_GMAC0_MDC_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_MDC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_mdc_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_mdc_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_MDC_SYSCON_W { - PADCFG_PAD_GMAC0_MDC_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_MDC_SYSCON_W { + PADCFG_PAD_GMAC0_MDC_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs index 2e1d110..fd12b7e 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg92.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_mdio_syscon` reader - padcfg_pad_gmac0_mdio_syscon"] pub type PADCFG_PAD_GMAC0_MDIO_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_mdio_syscon` writer - padcfg_pad_gmac0_mdio_syscon"] -pub type PADCFG_PAD_GMAC0_MDIO_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_MDIO_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac0_mdio_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_mdio_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_MDIO_SYSCON_W { - PADCFG_PAD_GMAC0_MDIO_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_MDIO_SYSCON_W { + PADCFG_PAD_GMAC0_MDIO_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs index ba8ef45..3f8dabd 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg96.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac0_rxd0_syscon` reader - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] pub type PADCFG_PAD_GMAC0_RXD0_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac0_rxd0_syscon` writer - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] -pub type PADCFG_PAD_GMAC0_RXD0_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC0_RXD0_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac0_rxd0_syscon( &mut self, - ) -> PADCFG_PAD_GMAC0_RXD0_SYSCON_W { - PADCFG_PAD_GMAC0_RXD0_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC0_RXD0_SYSCON_W { + PADCFG_PAD_GMAC0_RXD0_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux0.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux0.rs index 731dd39..1bb9c0c 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux0.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux0.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `aon_iomux_gpo0_doen_cfg` reader - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] pub type AON_IOMUX_GPO0_DOEN_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpo0_doen_cfg` writer - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO0_DOEN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type AON_IOMUX_GPO0_DOEN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `aon_iomux_gpo1_doen_cfg` reader - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] pub type AON_IOMUX_GPO1_DOEN_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpo1_doen_cfg` writer - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO1_DOEN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type AON_IOMUX_GPO1_DOEN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `aon_iomux_gpo2_doen_cfg` reader - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] pub type AON_IOMUX_GPO2_DOEN_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpo2_doen_cfg` writer - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO2_DOEN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type AON_IOMUX_GPO2_DOEN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `aon_iomux_gpo3_doen_cfg` reader - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] pub type AON_IOMUX_GPO3_DOEN_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpo3_doen_cfg` writer - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO3_DOEN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type AON_IOMUX_GPO3_DOEN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:2 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] #[inline(always)] @@ -46,34 +46,38 @@ impl W { #[must_use] pub fn aon_iomux_gpo0_doen_cfg( &mut self, - ) -> AON_IOMUX_GPO0_DOEN_CFG_W { - AON_IOMUX_GPO0_DOEN_CFG_W::new(self) + ) -> AON_IOMUX_GPO0_DOEN_CFG_W { + AON_IOMUX_GPO0_DOEN_CFG_W::new(self, 0) } #[doc = "Bits 8:10 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] #[inline(always)] #[must_use] pub fn aon_iomux_gpo1_doen_cfg( &mut self, - ) -> AON_IOMUX_GPO1_DOEN_CFG_W { - AON_IOMUX_GPO1_DOEN_CFG_W::new(self) + ) -> AON_IOMUX_GPO1_DOEN_CFG_W { + AON_IOMUX_GPO1_DOEN_CFG_W::new(self, 8) } #[doc = "Bits 16:18 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] #[inline(always)] #[must_use] pub fn aon_iomux_gpo2_doen_cfg( &mut self, - ) -> AON_IOMUX_GPO2_DOEN_CFG_W { - AON_IOMUX_GPO2_DOEN_CFG_W::new(self) + ) -> AON_IOMUX_GPO2_DOEN_CFG_W { + AON_IOMUX_GPO2_DOEN_CFG_W::new(self, 16) } #[doc = "Bits 24:26 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] #[inline(always)] #[must_use] pub fn aon_iomux_gpo3_doen_cfg( &mut self, - ) -> AON_IOMUX_GPO3_DOEN_CFG_W { - AON_IOMUX_GPO3_DOEN_CFG_W::new(self) + ) -> AON_IOMUX_GPO3_DOEN_CFG_W { + AON_IOMUX_GPO3_DOEN_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux1.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux1.rs index 6b079d8..045b180 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux1.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `aon_iomux_gpo0_dout_cfg` reader - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] pub type AON_IOMUX_GPO0_DOUT_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpo0_dout_cfg` writer - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO0_DOUT_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_IOMUX_GPO0_DOUT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `aon_iomux_gpo1_dout_cfg` reader - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] pub type AON_IOMUX_GPO1_DOUT_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpo1_dout_cfg` writer - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO1_DOUT_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_IOMUX_GPO1_DOUT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `aon_iomux_gpo2_dout_cfg` reader - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] pub type AON_IOMUX_GPO2_DOUT_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpo2_dout_cfg` writer - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO2_DOUT_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_IOMUX_GPO2_DOUT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `aon_iomux_gpo3_dout_cfg` reader - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] pub type AON_IOMUX_GPO3_DOUT_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpo3_dout_cfg` writer - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] -pub type AON_IOMUX_GPO3_DOUT_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_IOMUX_GPO3_DOUT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] #[inline(always)] @@ -46,34 +46,38 @@ impl W { #[must_use] pub fn aon_iomux_gpo0_dout_cfg( &mut self, - ) -> AON_IOMUX_GPO0_DOUT_CFG_W { - AON_IOMUX_GPO0_DOUT_CFG_W::new(self) + ) -> AON_IOMUX_GPO0_DOUT_CFG_W { + AON_IOMUX_GPO0_DOUT_CFG_W::new(self, 0) } #[doc = "Bits 8:11 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] #[inline(always)] #[must_use] pub fn aon_iomux_gpo1_dout_cfg( &mut self, - ) -> AON_IOMUX_GPO1_DOUT_CFG_W { - AON_IOMUX_GPO1_DOUT_CFG_W::new(self) + ) -> AON_IOMUX_GPO1_DOUT_CFG_W { + AON_IOMUX_GPO1_DOUT_CFG_W::new(self, 8) } #[doc = "Bits 16:19 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] #[inline(always)] #[must_use] pub fn aon_iomux_gpo2_dout_cfg( &mut self, - ) -> AON_IOMUX_GPO2_DOUT_CFG_W { - AON_IOMUX_GPO2_DOUT_CFG_W::new(self) + ) -> AON_IOMUX_GPO2_DOUT_CFG_W { + AON_IOMUX_GPO2_DOUT_CFG_W::new(self, 16) } #[doc = "Bits 24:27 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information."] #[inline(always)] #[must_use] pub fn aon_iomux_gpo3_dout_cfg( &mut self, - ) -> AON_IOMUX_GPO3_DOUT_CFG_W { - AON_IOMUX_GPO3_DOUT_CFG_W::new(self) + ) -> AON_IOMUX_GPO3_DOUT_CFG_W { + AON_IOMUX_GPO3_DOUT_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux2.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux2.rs index efe3a61..a8f9ba4 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux2.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux2.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W<'a, REG> = + crate::FieldWriter<'a, REG, 3>; #[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W<'a, REG> = + crate::FieldWriter<'a, REG, 3>; #[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W<'a, REG> = + crate::FieldWriter<'a, REG, 3>; #[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_R = crate::FieldReader; #[doc = "Field `aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W<'a, REG> = + crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:2 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -58,46 +58,42 @@ impl W { #[must_use] pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_0_cfg( &mut self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W< - AON_IOMUX_CFGSAIF_SYSCFG_FMUX2_SPEC, - 0, - > { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W::new(self) + ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W + { + AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0_CFG_W::new(self, 0) } #[doc = "Bits 8:10 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_1_cfg( &mut self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W< - AON_IOMUX_CFGSAIF_SYSCFG_FMUX2_SPEC, - 8, - > { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W::new(self) + ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W + { + AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1_CFG_W::new(self, 8) } #[doc = "Bits 16:18 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_2_cfg( &mut self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W< - AON_IOMUX_CFGSAIF_SYSCFG_FMUX2_SPEC, - 16, - > { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W::new(self) + ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W + { + AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2_CFG_W::new(self, 16) } #[doc = "Bits 24:26 - The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn aon_iomux_gpi_u0_pmu_io_event_stub_gpio_wakeup_3_cfg( &mut self, - ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W< - AON_IOMUX_CFGSAIF_SYSCFG_FMUX2_SPEC, - 24, - > { - AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W::new(self) + ) -> AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W + { + AON_IOMUX_GPI_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux3.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux3.rs index 03bd0c4..94cc018 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux3.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_fmux3.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `aon_gpioen_0_reg` reader - Enable GPIO IRQ function."] pub type AON_GPIOEN_0_REG_R = crate::BitReader; #[doc = "Field `aon_gpioen_0_reg` writer - Enable GPIO IRQ function."] -pub type AON_GPIOEN_0_REG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AON_GPIOEN_0_REG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable GPIO IRQ function."] #[inline(always)] @@ -17,12 +17,14 @@ impl W { #[doc = "Bit 0 - Enable GPIO IRQ function."] #[inline(always)] #[must_use] - pub fn aon_gpioen_0_reg( - &mut self, - ) -> AON_GPIOEN_0_REG_W { - AON_GPIOEN_0_REG_W::new(self) + pub fn aon_gpioen_0_reg(&mut self) -> AON_GPIOEN_0_REG_W { + AON_GPIOEN_0_REG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq10.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq10.rs index 2b3b623..71d7011 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq10.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq10.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq11.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq11.rs index 2fb0443..6e7f217 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq11.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq11.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq4.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq4.rs index 8e55dcc..f984d07 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq4.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq4.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `aon_gpiois_0_reg` reader - 1: Edge trigger, 0: Level trigger"] pub type AON_GPIOIS_0_REG_R = crate::FieldReader; #[doc = "Field `aon_gpiois_0_reg` writer - 1: Edge trigger, 0: Level trigger"] -pub type AON_GPIOIS_0_REG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_GPIOIS_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - 1: Edge trigger, 0: Level trigger"] #[inline(always)] @@ -17,12 +17,14 @@ impl W { #[doc = "Bits 0:3 - 1: Edge trigger, 0: Level trigger"] #[inline(always)] #[must_use] - pub fn aon_gpiois_0_reg( - &mut self, - ) -> AON_GPIOIS_0_REG_W { - AON_GPIOIS_0_REG_W::new(self) + pub fn aon_gpiois_0_reg(&mut self) -> AON_GPIOIS_0_REG_W { + AON_GPIOIS_0_REG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq5.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq5.rs index 4fded86..91bc1c3 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq5.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq5.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `aon_gpioic_0_reg` reader - 1: Do not clear the register, 0: Clear the register"] pub type AON_GPIOIC_0_REG_R = crate::FieldReader; #[doc = "Field `aon_gpioic_0_reg` writer - 1: Do not clear the register, 0: Clear the register"] -pub type AON_GPIOIC_0_REG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_GPIOIC_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - 1: Do not clear the register, 0: Clear the register"] #[inline(always)] @@ -17,12 +17,14 @@ impl W { #[doc = "Bits 0:3 - 1: Do not clear the register, 0: Clear the register"] #[inline(always)] #[must_use] - pub fn aon_gpioic_0_reg( - &mut self, - ) -> AON_GPIOIC_0_REG_W { - AON_GPIOIC_0_REG_W::new(self) + pub fn aon_gpioic_0_reg(&mut self) -> AON_GPIOIC_0_REG_W { + AON_GPIOIC_0_REG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq6.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq6.rs index df0a298..925eb89 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq6.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq6.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `aon_gpioibe_0_reg` reader - 1: Trigger on both edges, 0: Trigger on a single edge"] pub type AON_GPIOIBE_0_REG_R = crate::FieldReader; #[doc = "Field `aon_gpioibe_0_reg` writer - 1: Trigger on both edges, 0: Trigger on a single edge"] -pub type AON_GPIOIBE_0_REG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_GPIOIBE_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - 1: Trigger on both edges, 0: Trigger on a single edge"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn aon_gpioibe_0_reg( &mut self, - ) -> AON_GPIOIBE_0_REG_W { - AON_GPIOIBE_0_REG_W::new(self) + ) -> AON_GPIOIBE_0_REG_W { + AON_GPIOIBE_0_REG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq7.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq7.rs index 51e5fde..353765a 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq7.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq7.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `aon_gpioiev_0_reg` reader - 1: Positive/Low, 0: Negative/High"] pub type AON_GPIOIEV_0_REG_R = crate::FieldReader; #[doc = "Field `aon_gpioiev_0_reg` writer - 1: Positive/Low, 0: Negative/High"] -pub type AON_GPIOIEV_0_REG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_GPIOIEV_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - 1: Positive/Low, 0: Negative/High"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn aon_gpioiev_0_reg( &mut self, - ) -> AON_GPIOIEV_0_REG_W { - AON_GPIOIEV_0_REG_W::new(self) + ) -> AON_GPIOIEV_0_REG_W { + AON_GPIOIEV_0_REG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq8.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq8.rs index b296bb3..cd46c19 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq8.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq8.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `aon_gpioie_0_reg` reader - 1: Unmask, 0: Mask"] pub type AON_GPIOIE_0_REG_R = crate::FieldReader; #[doc = "Field `aon_gpioie_0_reg` writer - 1: Unmask, 0: Mask"] -pub type AON_GPIOIE_0_REG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type AON_GPIOIE_0_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - 1: Unmask, 0: Mask"] #[inline(always)] @@ -17,12 +17,14 @@ impl W { #[doc = "Bits 0:3 - 1: Unmask, 0: Mask"] #[inline(always)] #[must_use] - pub fn aon_gpioie_0_reg( - &mut self, - ) -> AON_GPIOIE_0_REG_W { - AON_GPIOIE_0_REG_W::new(self) + pub fn aon_gpioie_0_reg(&mut self) -> AON_GPIOIE_0_REG_W { + AON_GPIOIE_0_REG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq9.rs b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq9.rs index e2b4528..72caae7 100644 --- a/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq9.rs +++ b/jh7110-vf2-13b-pac/src/aon_pinctrl/aon_iomux_cfgsaif_syscfg_ioirq9.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_syscon.rs b/jh7110-vf2-13b-pac/src/aon_syscon.rs index b79c8a8..6b80cee 100644 --- a/jh7110-vf2-13b-pac/src/aon_syscon.rs +++ b/jh7110-vf2-13b-pac/src/aon_syscon.rs @@ -1,87 +1,133 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + aon_sysconsaif_syscfg0: AON_SYSCONSAIF_SYSCFG0, + aon_sysconsaif_syscfg4: AON_SYSCONSAIF_SYSCFG4, + aon_sysconsaif_syscfg8: AON_SYSCONSAIF_SYSCFG8, + aon_sysconsaif_syscfg12: AON_SYSCONSAIF_SYSCFG12, + aon_sysconsaif_syscfg16: AON_SYSCONSAIF_SYSCFG16, + aon_sysconsaif_syscfg20: AON_SYSCONSAIF_SYSCFG20, + aon_sysconsaif_syscfg24: AON_SYSCONSAIF_SYSCFG24, + aon_sysconsaif_syscfg28: AON_SYSCONSAIF_SYSCFG28, + aon_sysconsaif_syscfg32: AON_SYSCONSAIF_SYSCFG32, + aon_sysconsaif_syscfg36: AON_SYSCONSAIF_SYSCFG36, + aon_sysconsaif_syscfg40: AON_SYSCONSAIF_SYSCFG40, +} +impl RegisterBlock { #[doc = "0x00 - AON SYSCONSAIF SYSCFG 0"] - pub aon_sysconsaif_syscfg0: AON_SYSCONSAIF_SYSCFG0, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg0(&self) -> &AON_SYSCONSAIF_SYSCFG0 { + &self.aon_sysconsaif_syscfg0 + } #[doc = "0x04 - AON SYSCONSAIF SYSCFG 4"] - pub aon_sysconsaif_syscfg4: AON_SYSCONSAIF_SYSCFG4, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg4(&self) -> &AON_SYSCONSAIF_SYSCFG4 { + &self.aon_sysconsaif_syscfg4 + } #[doc = "0x08 - AON SYSCONSAIF SYSCFG 8"] - pub aon_sysconsaif_syscfg8: AON_SYSCONSAIF_SYSCFG8, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg8(&self) -> &AON_SYSCONSAIF_SYSCFG8 { + &self.aon_sysconsaif_syscfg8 + } #[doc = "0x0c - AON SYSCONSAIF SYSCFG 12"] - pub aon_sysconsaif_syscfg12: AON_SYSCONSAIF_SYSCFG12, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg12(&self) -> &AON_SYSCONSAIF_SYSCFG12 { + &self.aon_sysconsaif_syscfg12 + } #[doc = "0x10 - AON SYSCONSAIF SYSCFG 16"] - pub aon_sysconsaif_syscfg16: AON_SYSCONSAIF_SYSCFG16, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg16(&self) -> &AON_SYSCONSAIF_SYSCFG16 { + &self.aon_sysconsaif_syscfg16 + } #[doc = "0x14 - AON SYSCONSAIF SYSCFG 20"] - pub aon_sysconsaif_syscfg20: AON_SYSCONSAIF_SYSCFG20, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg20(&self) -> &AON_SYSCONSAIF_SYSCFG20 { + &self.aon_sysconsaif_syscfg20 + } #[doc = "0x18 - AON SYSCONSAIF SYSCFG 24"] - pub aon_sysconsaif_syscfg24: AON_SYSCONSAIF_SYSCFG24, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg24(&self) -> &AON_SYSCONSAIF_SYSCFG24 { + &self.aon_sysconsaif_syscfg24 + } #[doc = "0x1c - AON SYSCONSAIF SYSCFG 28"] - pub aon_sysconsaif_syscfg28: AON_SYSCONSAIF_SYSCFG28, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg28(&self) -> &AON_SYSCONSAIF_SYSCFG28 { + &self.aon_sysconsaif_syscfg28 + } #[doc = "0x20 - AON SYSCONSAIF SYSCFG 32"] - pub aon_sysconsaif_syscfg32: AON_SYSCONSAIF_SYSCFG32, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg32(&self) -> &AON_SYSCONSAIF_SYSCFG32 { + &self.aon_sysconsaif_syscfg32 + } #[doc = "0x24 - AON SYSCONSAIF SYSCFG 36"] - pub aon_sysconsaif_syscfg36: AON_SYSCONSAIF_SYSCFG36, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg36(&self) -> &AON_SYSCONSAIF_SYSCFG36 { + &self.aon_sysconsaif_syscfg36 + } #[doc = "0x28 - AON SYSCONSAIF SYSCFG 40"] - pub aon_sysconsaif_syscfg40: AON_SYSCONSAIF_SYSCFG40, + #[inline(always)] + pub const fn aon_sysconsaif_syscfg40(&self) -> &AON_SYSCONSAIF_SYSCFG40 { + &self.aon_sysconsaif_syscfg40 + } } -#[doc = "aon_sysconsaif_syscfg0 (rw) register accessor: AON SYSCONSAIF SYSCFG 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg0`] +#[doc = "aon_sysconsaif_syscfg0 (rw) register accessor: AON SYSCONSAIF SYSCFG 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg0`] module"] pub type AON_SYSCONSAIF_SYSCFG0 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 0"] pub mod aon_sysconsaif_syscfg0; -#[doc = "aon_sysconsaif_syscfg4 (rw) register accessor: AON SYSCONSAIF SYSCFG 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg4`] +#[doc = "aon_sysconsaif_syscfg4 (rw) register accessor: AON SYSCONSAIF SYSCFG 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg4`] module"] pub type AON_SYSCONSAIF_SYSCFG4 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 4"] pub mod aon_sysconsaif_syscfg4; -#[doc = "aon_sysconsaif_syscfg8 (rw) register accessor: AON SYSCONSAIF SYSCFG 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg8`] +#[doc = "aon_sysconsaif_syscfg8 (rw) register accessor: AON SYSCONSAIF SYSCFG 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg8`] module"] pub type AON_SYSCONSAIF_SYSCFG8 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 8"] pub mod aon_sysconsaif_syscfg8; -#[doc = "aon_sysconsaif_syscfg12 (rw) register accessor: AON SYSCONSAIF SYSCFG 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg12::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg12`] +#[doc = "aon_sysconsaif_syscfg12 (rw) register accessor: AON SYSCONSAIF SYSCFG 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg12::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg12`] module"] pub type AON_SYSCONSAIF_SYSCFG12 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 12"] pub mod aon_sysconsaif_syscfg12; -#[doc = "aon_sysconsaif_syscfg16 (rw) register accessor: AON SYSCONSAIF SYSCFG 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg16::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg16`] +#[doc = "aon_sysconsaif_syscfg16 (rw) register accessor: AON SYSCONSAIF SYSCFG 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg16::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg16`] module"] pub type AON_SYSCONSAIF_SYSCFG16 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 16"] pub mod aon_sysconsaif_syscfg16; -#[doc = "aon_sysconsaif_syscfg20 (rw) register accessor: AON SYSCONSAIF SYSCFG 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg20::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg20`] +#[doc = "aon_sysconsaif_syscfg20 (rw) register accessor: AON SYSCONSAIF SYSCFG 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg20::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg20`] module"] pub type AON_SYSCONSAIF_SYSCFG20 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 20"] pub mod aon_sysconsaif_syscfg20; -#[doc = "aon_sysconsaif_syscfg24 (rw) register accessor: AON SYSCONSAIF SYSCFG 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg24::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg24`] +#[doc = "aon_sysconsaif_syscfg24 (rw) register accessor: AON SYSCONSAIF SYSCFG 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg24::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg24`] module"] pub type AON_SYSCONSAIF_SYSCFG24 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 24"] pub mod aon_sysconsaif_syscfg24; -#[doc = "aon_sysconsaif_syscfg28 (rw) register accessor: AON SYSCONSAIF SYSCFG 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg28::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg28`] +#[doc = "aon_sysconsaif_syscfg28 (rw) register accessor: AON SYSCONSAIF SYSCFG 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg28::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg28`] module"] pub type AON_SYSCONSAIF_SYSCFG28 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 28"] pub mod aon_sysconsaif_syscfg28; -#[doc = "aon_sysconsaif_syscfg32 (rw) register accessor: AON SYSCONSAIF SYSCFG 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg32::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg32`] +#[doc = "aon_sysconsaif_syscfg32 (rw) register accessor: AON SYSCONSAIF SYSCFG 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg32::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg32`] module"] pub type AON_SYSCONSAIF_SYSCFG32 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 32"] pub mod aon_sysconsaif_syscfg32; -#[doc = "aon_sysconsaif_syscfg36 (rw) register accessor: AON SYSCONSAIF SYSCFG 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg36::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg36`] +#[doc = "aon_sysconsaif_syscfg36 (rw) register accessor: AON SYSCONSAIF SYSCFG 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg36::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg36`] module"] pub type AON_SYSCONSAIF_SYSCFG36 = crate::Reg; #[doc = "AON SYSCONSAIF SYSCFG 36"] pub mod aon_sysconsaif_syscfg36; -#[doc = "aon_sysconsaif_syscfg40 (rw) register accessor: AON SYSCONSAIF SYSCFG 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg40::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aon_sysconsaif_syscfg40`] +#[doc = "aon_sysconsaif_syscfg40 (rw) register accessor: AON SYSCONSAIF SYSCFG 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aon_sysconsaif_syscfg40::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aon_sysconsaif_syscfg40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_sysconsaif_syscfg40`] module"] pub type AON_SYSCONSAIF_SYSCFG40 = crate::Reg; diff --git a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg0.rs b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg0.rs index 6f1c6ca..185bc30 100644 --- a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg0.rs +++ b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `aon_gp_reg` reader - aon_gp_reg"] pub type AON_GP_REG_R = crate::FieldReader; #[doc = "Field `aon_gp_reg` writer - aon_gp_reg"] -pub type AON_GP_REG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type AON_GP_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - aon_gp_reg"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - aon_gp_reg"] #[inline(always)] #[must_use] - pub fn aon_gp_reg(&mut self) -> AON_GP_REG_W { - AON_GP_REG_W::new(self) + pub fn aon_gp_reg(&mut self) -> AON_GP_REG_W { + AON_GP_REG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg12.rs b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg12.rs index b10ae91..3be4f38 100644 --- a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg12.rs +++ b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg12.rs @@ -7,42 +7,41 @@ pub type U0_BOOT_CTRL_BOOT_VECTOR_35_32_R = crate::FieldReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] pub type GMAC5_AXI64_SCFG_RAM_CFG_SLP_R = crate::BitReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] -pub type GMAC5_AXI64_SCFG_RAM_CFG_SLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GMAC5_AXI64_SCFG_RAM_CFG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] pub type GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_R = crate::BitReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] -pub type GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] pub type GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_R = crate::FieldReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] -pub type GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] pub type GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_R = crate::FieldReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] -pub type GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] pub type GMAC5_AXI64_SCFG_RAM_CFG_TRB_R = crate::FieldReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] -pub type GMAC5_AXI64_SCFG_RAM_CFG_TRB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type GMAC5_AXI64_SCFG_RAM_CFG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] pub type GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_R = crate::FieldReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] -pub type GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] pub type GMAC5_AXI64_SCFG_RAM_CFG_VS_R = crate::BitReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] -pub type GMAC5_AXI64_SCFG_RAM_CFG_VS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GMAC5_AXI64_SCFG_RAM_CFG_VS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] pub type GMAC5_AXI64_SCFG_RAM_CFG_VG_R = crate::BitReader; #[doc = "Field `gmac5_axi64_scfg_ram_cfg_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] -pub type GMAC5_AXI64_SCFG_RAM_CFG_VG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GMAC5_AXI64_SCFG_RAM_CFG_VG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gmac5_axi64_mac_speed_o` reader - gmac5_axi64_mac_speed_o"] pub type GMAC5_AXI64_MAC_SPEED_O_R = crate::FieldReader; #[doc = "Field `gmac5_axi64_phy_intf_sel_i` reader - Active PHY Selected. When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. Values: 0x0 - GMII or MII, 0x1 - RGMII, 0x2 - SGMII, 0x3 - TBI, 0x4 - RMII, 0x5 - RTBI, 0x6 - SMII, 0x7 - REVMII"] pub type GMAC5_AXI64_PHY_INTF_SEL_I_R = crate::FieldReader; #[doc = "Field `gmac5_axi64_phy_intf_sel_i` writer - Active PHY Selected. When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. Values: 0x0 - GMII or MII, 0x1 - RGMII, 0x2 - SGMII, 0x3 - TBI, 0x4 - RMII, 0x5 - RTBI, 0x6 - SMII, 0x7 - REVMII"] -pub type GMAC5_AXI64_PHY_INTF_SEL_I_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type GMAC5_AXI64_PHY_INTF_SEL_I_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:3 - u0_boot_ctrl_boot_vector_35_32"] #[inline(always)] @@ -108,74 +107,78 @@ impl W { #[must_use] pub fn gmac5_axi64_scfg_ram_cfg_slp( &mut self, - ) -> GMAC5_AXI64_SCFG_RAM_CFG_SLP_W { - GMAC5_AXI64_SCFG_RAM_CFG_SLP_W::new(self) + ) -> GMAC5_AXI64_SCFG_RAM_CFG_SLP_W { + GMAC5_AXI64_SCFG_RAM_CFG_SLP_W::new(self, 4) } #[doc = "Bit 5 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] #[inline(always)] #[must_use] pub fn gmac5_axi64_scfg_ram_cfg_sram_config_sd( &mut self, - ) -> GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W { - GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W::new(self) + ) -> GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W { + GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W::new(self, 5) } #[doc = "Bits 6:7 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn gmac5_axi64_scfg_ram_cfg_rtsel( &mut self, - ) -> GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W { - GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W::new(self) + ) -> GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W { + GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W::new(self, 6) } #[doc = "Bits 8:9 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn gmac5_axi64_scfg_ram_cfg_ptsel( &mut self, - ) -> GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W { - GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W::new(self) + ) -> GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W { + GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W::new(self, 8) } #[doc = "Bits 10:11 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn gmac5_axi64_scfg_ram_cfg_trb( &mut self, - ) -> GMAC5_AXI64_SCFG_RAM_CFG_TRB_W { - GMAC5_AXI64_SCFG_RAM_CFG_TRB_W::new(self) + ) -> GMAC5_AXI64_SCFG_RAM_CFG_TRB_W { + GMAC5_AXI64_SCFG_RAM_CFG_TRB_W::new(self, 10) } #[doc = "Bits 12:13 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn gmac5_axi64_scfg_ram_cfg_wtsel( &mut self, - ) -> GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W { - GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W::new(self) + ) -> GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W { + GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W::new(self, 12) } #[doc = "Bit 14 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn gmac5_axi64_scfg_ram_cfg_vs( &mut self, - ) -> GMAC5_AXI64_SCFG_RAM_CFG_VS_W { - GMAC5_AXI64_SCFG_RAM_CFG_VS_W::new(self) + ) -> GMAC5_AXI64_SCFG_RAM_CFG_VS_W { + GMAC5_AXI64_SCFG_RAM_CFG_VS_W::new(self, 14) } #[doc = "Bit 15 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn gmac5_axi64_scfg_ram_cfg_vg( &mut self, - ) -> GMAC5_AXI64_SCFG_RAM_CFG_VG_W { - GMAC5_AXI64_SCFG_RAM_CFG_VG_W::new(self) + ) -> GMAC5_AXI64_SCFG_RAM_CFG_VG_W { + GMAC5_AXI64_SCFG_RAM_CFG_VG_W::new(self, 15) } #[doc = "Bits 18:20 - Active PHY Selected. When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. Values: 0x0 - GMII or MII, 0x1 - RGMII, 0x2 - SGMII, 0x3 - TBI, 0x4 - RMII, 0x5 - RTBI, 0x6 - SMII, 0x7 - REVMII"] #[inline(always)] #[must_use] pub fn gmac5_axi64_phy_intf_sel_i( &mut self, - ) -> GMAC5_AXI64_PHY_INTF_SEL_I_W { - GMAC5_AXI64_PHY_INTF_SEL_I_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> GMAC5_AXI64_PHY_INTF_SEL_I_W { + GMAC5_AXI64_PHY_INTF_SEL_I_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg16.rs b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg16.rs index 03874e4..757d797 100644 --- a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg16.rs +++ b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg16.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg20.rs b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg20.rs index de6a843..51d904d 100644 --- a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg20.rs +++ b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg20.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg24.rs b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg24.rs index 2ff7519..b2d392d 100644 --- a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg24.rs +++ b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg24.rs @@ -26,7 +26,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg28.rs b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg28.rs index 0960490..bb8bbfd 100644 --- a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg28.rs +++ b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg28.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg32.rs b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg32.rs index f84ba2b..92cfdb9 100644 --- a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg32.rs +++ b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg32.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg36.rs b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg36.rs index ce2a854..6627170 100644 --- a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg36.rs +++ b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg36.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg4.rs b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg4.rs index e47a8e5..679a461 100644 --- a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg4.rs +++ b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg4.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg40.rs b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg40.rs index 801573e..0c34ef1 100644 --- a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg40.rs +++ b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg40.rs @@ -11,13 +11,13 @@ pub type U0_OTPC_LOAD_BUSY_R = crate::BitReader; #[doc = "Field `u0_reset_ctrl_clr_reset_status` reader - u0_reset_ctrl_clr_reset_status"] pub type U0_RESET_CTRL_CLR_RESET_STATUS_R = crate::BitReader; #[doc = "Field `u0_reset_ctrl_clr_reset_status` writer - u0_reset_ctrl_clr_reset_status"] -pub type U0_RESET_CTRL_CLR_RESET_STATUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_RESET_CTRL_CLR_RESET_STATUS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_reset_ctrl_pll_timecnt_finish` reader - u0_reset_ctrl_pll_timecnt_finish"] pub type U0_RESET_CTRL_PLL_TIMECNT_FINISH_R = crate::BitReader; #[doc = "Field `u0_reset_ctrl_rstn_sw` reader - u0_reset_ctrl_rstn_sw"] pub type U0_RESET_CTRL_RSTN_SW_R = crate::BitReader; #[doc = "Field `u0_reset_ctrl_rstn_sw` writer - u0_reset_ctrl_rstn_sw"] -pub type U0_RESET_CTRL_RSTN_SW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_RESET_CTRL_RSTN_SW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_reset_ctrl_sys_reset_status` reader - u0_reset_ctrl_sys_reset_status"] pub type U0_RESET_CTRL_SYS_RESET_STATUS_R = crate::FieldReader; impl R { @@ -63,18 +63,22 @@ impl W { #[must_use] pub fn u0_reset_ctrl_clr_reset_status( &mut self, - ) -> U0_RESET_CTRL_CLR_RESET_STATUS_W { - U0_RESET_CTRL_CLR_RESET_STATUS_W::new(self) + ) -> U0_RESET_CTRL_CLR_RESET_STATUS_W { + U0_RESET_CTRL_CLR_RESET_STATUS_W::new(self, 3) } #[doc = "Bit 5 - u0_reset_ctrl_rstn_sw"] #[inline(always)] #[must_use] pub fn u0_reset_ctrl_rstn_sw( &mut self, - ) -> U0_RESET_CTRL_RSTN_SW_W { - U0_RESET_CTRL_RSTN_SW_W::new(self) + ) -> U0_RESET_CTRL_RSTN_SW_W { + U0_RESET_CTRL_RSTN_SW_W::new(self, 5) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg8.rs b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg8.rs index 526e1ae..cbffe58 100644 --- a/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg8.rs +++ b/jh7110-vf2-13b-pac/src/aon_syscon/aon_sysconsaif_syscfg8.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aoncrg.rs b/jh7110-vf2-13b-pac/src/aoncrg.rs index cf238c3..96a0761 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg.rs @@ -1,115 +1,181 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + clk_osc: CLK_OSC, + clk_aon_apb: CLK_AON_APB, + clk_ahb_gmac5: CLK_AHB_GMAC5, + clk_axi_gmac5: CLK_AXI_GMAC5, + clk_gmac0_rmii_rtx: CLK_GMAC0_RMII_RTX, + clk_gmac5_axi64_tx: CLK_GMAC5_AXI64_TX, + clk_gmac5_axi64_txi: CLK_GMAC5_AXI64_TXI, + clk_gmac5_axi64_rx: CLK_GMAC5_AXI64_RX, + clk_gmac5_axi64_rxi: CLK_GMAC5_AXI64_RXI, + clk_optc_apb: CLK_OPTC_APB, + clk_rtc_hms_apb: CLK_RTC_HMS_APB, + clk_rtc_internal: CLK_RTC_INTERNAL, + clk_rtc_hms_osc32k: CLK_RTC_HMS_OSC32K, + clk_rtc_hms_cal: CLK_RTC_HMS_CAL, + soft_rst_addr_sel: SOFT_RST_ADDR_SEL, + aoncrg_rst_status: AONCRG_RST_STATUS, +} +impl RegisterBlock { #[doc = "0x00 - Oscillator Clock"] - pub clk_osc: CLK_OSC, + #[inline(always)] + pub const fn clk_osc(&self) -> &CLK_OSC { + &self.clk_osc + } #[doc = "0x04 - AON APB Function Clock"] - pub clk_aon_apb: CLK_AON_APB, + #[inline(always)] + pub const fn clk_aon_apb(&self) -> &CLK_AON_APB { + &self.clk_aon_apb + } #[doc = "0x08 - AHB GMAC5 Clock"] - pub clk_ahb_gmac5: CLK_AHB_GMAC5, + #[inline(always)] + pub const fn clk_ahb_gmac5(&self) -> &CLK_AHB_GMAC5 { + &self.clk_ahb_gmac5 + } #[doc = "0x0c - AXI GMAC5 Clock"] - pub clk_axi_gmac5: CLK_AXI_GMAC5, + #[inline(always)] + pub const fn clk_axi_gmac5(&self) -> &CLK_AXI_GMAC5 { + &self.clk_axi_gmac5 + } #[doc = "0x10 - GMAC0 RMII RTX Clock"] - pub clk_gmac0_rmii_rtx: CLK_GMAC0_RMII_RTX, + #[inline(always)] + pub const fn clk_gmac0_rmii_rtx(&self) -> &CLK_GMAC0_RMII_RTX { + &self.clk_gmac0_rmii_rtx + } #[doc = "0x14 - GMAC5 AXI64 Clock Transmitter"] - pub clk_gmac5_axi64_tx: CLK_GMAC5_AXI64_TX, + #[inline(always)] + pub const fn clk_gmac5_axi64_tx(&self) -> &CLK_GMAC5_AXI64_TX { + &self.clk_gmac5_axi64_tx + } #[doc = "0x18 - GMAC5 AXI64 Clock Transmission Inverter"] - pub clk_gmac5_axi64_txi: CLK_GMAC5_AXI64_TXI, + #[inline(always)] + pub const fn clk_gmac5_axi64_txi(&self) -> &CLK_GMAC5_AXI64_TXI { + &self.clk_gmac5_axi64_txi + } #[doc = "0x1c - GMAC5 AXI64 Clock Receiver"] - pub clk_gmac5_axi64_rx: CLK_GMAC5_AXI64_RX, + #[inline(always)] + pub const fn clk_gmac5_axi64_rx(&self) -> &CLK_GMAC5_AXI64_RX { + &self.clk_gmac5_axi64_rx + } #[doc = "0x20 - GMAC5 AXI64 Clock Receiving Inverter"] - pub clk_gmac5_axi64_rxi: CLK_GMAC5_AXI64_RXI, + #[inline(always)] + pub const fn clk_gmac5_axi64_rxi(&self) -> &CLK_GMAC5_AXI64_RXI { + &self.clk_gmac5_axi64_rxi + } #[doc = "0x24 - OPTC APB Clock"] - pub clk_optc_apb: CLK_OPTC_APB, + #[inline(always)] + pub const fn clk_optc_apb(&self) -> &CLK_OPTC_APB { + &self.clk_optc_apb + } #[doc = "0x28 - RTC HMS APB Clock"] - pub clk_rtc_hms_apb: CLK_RTC_HMS_APB, + #[inline(always)] + pub const fn clk_rtc_hms_apb(&self) -> &CLK_RTC_HMS_APB { + &self.clk_rtc_hms_apb + } #[doc = "0x2c - RTC Internal Clock"] - pub clk_rtc_internal: CLK_RTC_INTERNAL, + #[inline(always)] + pub const fn clk_rtc_internal(&self) -> &CLK_RTC_INTERNAL { + &self.clk_rtc_internal + } #[doc = "0x30 - RTC HMS Clock Oscillator 32K"] - pub clk_rtc_hms_osc32k: CLK_RTC_HMS_OSC32K, + #[inline(always)] + pub const fn clk_rtc_hms_osc32k(&self) -> &CLK_RTC_HMS_OSC32K { + &self.clk_rtc_hms_osc32k + } #[doc = "0x34 - RTC HMS Clock Calculator"] - pub clk_rtc_hms_cal: CLK_RTC_HMS_CAL, + #[inline(always)] + pub const fn clk_rtc_hms_cal(&self) -> &CLK_RTC_HMS_CAL { + &self.clk_rtc_hms_cal + } #[doc = "0x38 - Software RESET Address Selector"] - pub soft_rst_addr_sel: SOFT_RST_ADDR_SEL, + #[inline(always)] + pub const fn soft_rst_addr_sel(&self) -> &SOFT_RST_ADDR_SEL { + &self.soft_rst_addr_sel + } #[doc = "0x3c - AONCRG RESET Status"] - pub aoncrg_rst_status: AONCRG_RST_STATUS, + #[inline(always)] + pub const fn aoncrg_rst_status(&self) -> &AONCRG_RST_STATUS { + &self.aoncrg_rst_status + } } -#[doc = "clk_osc (rw) register accessor: Oscillator Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_osc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_osc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_osc`] +#[doc = "clk_osc (rw) register accessor: Oscillator Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_osc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_osc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_osc`] module"] pub type CLK_OSC = crate::Reg; #[doc = "Oscillator Clock"] pub mod clk_osc; -#[doc = "clk_aon_apb (rw) register accessor: AON APB Function Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_aon_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_aon_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_aon_apb`] +#[doc = "clk_aon_apb (rw) register accessor: AON APB Function Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_aon_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_aon_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_aon_apb`] module"] pub type CLK_AON_APB = crate::Reg; #[doc = "AON APB Function Clock"] pub mod clk_aon_apb; -#[doc = "clk_ahb_gmac5 (rw) register accessor: AHB GMAC5 Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ahb_gmac5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ahb_gmac5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_ahb_gmac5`] +#[doc = "clk_ahb_gmac5 (rw) register accessor: AHB GMAC5 Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ahb_gmac5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ahb_gmac5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_ahb_gmac5`] module"] pub type CLK_AHB_GMAC5 = crate::Reg; #[doc = "AHB GMAC5 Clock"] pub mod clk_ahb_gmac5; -#[doc = "clk_axi_gmac5 (rw) register accessor: AXI GMAC5 Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_gmac5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_gmac5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_axi_gmac5`] +#[doc = "clk_axi_gmac5 (rw) register accessor: AXI GMAC5 Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_gmac5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_gmac5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_axi_gmac5`] module"] pub type CLK_AXI_GMAC5 = crate::Reg; #[doc = "AXI GMAC5 Clock"] pub mod clk_axi_gmac5; -#[doc = "clk_gmac0_rmii_rtx (rw) register accessor: GMAC0 RMII RTX Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac0_rmii_rtx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac0_rmii_rtx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac0_rmii_rtx`] +#[doc = "clk_gmac0_rmii_rtx (rw) register accessor: GMAC0 RMII RTX Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac0_rmii_rtx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac0_rmii_rtx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac0_rmii_rtx`] module"] pub type CLK_GMAC0_RMII_RTX = crate::Reg; #[doc = "GMAC0 RMII RTX Clock"] pub mod clk_gmac0_rmii_rtx; -#[doc = "clk_gmac5_axi64_tx (rw) register accessor: GMAC5 AXI64 Clock Transmitter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_tx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_tx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_tx`] +#[doc = "clk_gmac5_axi64_tx (rw) register accessor: GMAC5 AXI64 Clock Transmitter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_tx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_tx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_tx`] module"] pub type CLK_GMAC5_AXI64_TX = crate::Reg; #[doc = "GMAC5 AXI64 Clock Transmitter"] pub mod clk_gmac5_axi64_tx; -#[doc = "clk_gmac5_axi64_txi (rw) register accessor: GMAC5 AXI64 Clock Transmission Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_txi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_txi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_txi`] +#[doc = "clk_gmac5_axi64_txi (rw) register accessor: GMAC5 AXI64 Clock Transmission Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_txi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_txi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_txi`] module"] pub type CLK_GMAC5_AXI64_TXI = crate::Reg; #[doc = "GMAC5 AXI64 Clock Transmission Inverter"] pub mod clk_gmac5_axi64_txi; -#[doc = "clk_gmac5_axi64_rx (rw) register accessor: GMAC5 AXI64 Clock Receiver\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_rx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_rx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_rx`] +#[doc = "clk_gmac5_axi64_rx (rw) register accessor: GMAC5 AXI64 Clock Receiver\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_rx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_rx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_rx`] module"] pub type CLK_GMAC5_AXI64_RX = crate::Reg; #[doc = "GMAC5 AXI64 Clock Receiver"] pub mod clk_gmac5_axi64_rx; -#[doc = "clk_gmac5_axi64_rxi (rw) register accessor: GMAC5 AXI64 Clock Receiving Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_rxi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_rxi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_rxi`] +#[doc = "clk_gmac5_axi64_rxi (rw) register accessor: GMAC5 AXI64 Clock Receiving Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_rxi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_rxi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_rxi`] module"] pub type CLK_GMAC5_AXI64_RXI = crate::Reg; #[doc = "GMAC5 AXI64 Clock Receiving Inverter"] pub mod clk_gmac5_axi64_rxi; -#[doc = "clk_optc_apb (rw) register accessor: OPTC APB Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_optc_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_optc_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_optc_apb`] +#[doc = "clk_optc_apb (rw) register accessor: OPTC APB Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_optc_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_optc_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_optc_apb`] module"] pub type CLK_OPTC_APB = crate::Reg; #[doc = "OPTC APB Clock"] pub mod clk_optc_apb; -#[doc = "clk_rtc_hms_apb (rw) register accessor: RTC HMS APB Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_hms_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_hms_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_rtc_hms_apb`] +#[doc = "clk_rtc_hms_apb (rw) register accessor: RTC HMS APB Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_hms_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_hms_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_rtc_hms_apb`] module"] pub type CLK_RTC_HMS_APB = crate::Reg; #[doc = "RTC HMS APB Clock"] pub mod clk_rtc_hms_apb; -#[doc = "clk_rtc_internal (rw) register accessor: RTC Internal Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_internal::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_internal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_rtc_internal`] +#[doc = "clk_rtc_internal (rw) register accessor: RTC Internal Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_internal::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_internal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_rtc_internal`] module"] pub type CLK_RTC_INTERNAL = crate::Reg; #[doc = "RTC Internal Clock"] pub mod clk_rtc_internal; -#[doc = "clk_rtc_hms_osc32k (rw) register accessor: RTC HMS Clock Oscillator 32K\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_hms_osc32k::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_hms_osc32k::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_rtc_hms_osc32k`] +#[doc = "clk_rtc_hms_osc32k (rw) register accessor: RTC HMS Clock Oscillator 32K\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_hms_osc32k::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_hms_osc32k::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_rtc_hms_osc32k`] module"] pub type CLK_RTC_HMS_OSC32K = crate::Reg; #[doc = "RTC HMS Clock Oscillator 32K"] pub mod clk_rtc_hms_osc32k; -#[doc = "clk_rtc_hms_cal (rw) register accessor: RTC HMS Clock Calculator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_hms_cal::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_hms_cal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_rtc_hms_cal`] +#[doc = "clk_rtc_hms_cal (rw) register accessor: RTC HMS Clock Calculator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_hms_cal::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_hms_cal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_rtc_hms_cal`] module"] pub type CLK_RTC_HMS_CAL = crate::Reg; #[doc = "RTC HMS Clock Calculator"] pub mod clk_rtc_hms_cal; -#[doc = "soft_rst_addr_sel (rw) register accessor: Software RESET Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_rst_addr_sel`] +#[doc = "soft_rst_addr_sel (rw) register accessor: Software RESET Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_rst_addr_sel`] module"] pub type SOFT_RST_ADDR_SEL = crate::Reg; #[doc = "Software RESET Address Selector"] pub mod soft_rst_addr_sel; -#[doc = "aoncrg_rst_status (rw) register accessor: AONCRG RESET Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aoncrg_rst_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aoncrg_rst_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aoncrg_rst_status`] +#[doc = "aoncrg_rst_status (rw) register accessor: AONCRG RESET Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aoncrg_rst_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aoncrg_rst_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aoncrg_rst_status`] module"] pub type AONCRG_RST_STATUS = crate::Reg; #[doc = "AONCRG RESET Status"] diff --git a/jh7110-vf2-13b-pac/src/aoncrg/aoncrg_rst_status.rs b/jh7110-vf2-13b-pac/src/aoncrg/aoncrg_rst_status.rs index 073f3fb..83ffda5 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg/aoncrg_rst_status.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg/aoncrg_rst_status.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `gmac5_axi64_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type GMAC5_AXI64_RSTN_AXI_R = crate::BitReader; #[doc = "Field `gmac5_axi64_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type GMAC5_AXI64_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GMAC5_AXI64_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gmac5_axi64_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type GMAC5_AXI64_RSTN_AHB_R = crate::BitReader; #[doc = "Field `gmac5_axi64_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type GMAC5_AXI64_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GMAC5_AXI64_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `aon_iomux_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type AON_IOMUX_PRESETN_R = crate::BitReader; #[doc = "Field `aon_iomux_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type AON_IOMUX_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AON_IOMUX_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pmu_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type PMU_RSTN_APB_R = crate::BitReader; #[doc = "Field `pmu_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type PMU_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PMU_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pmu_rstn_wkup` reader - 1: Assert reset, 0: De-assert reset"] pub type PMU_RSTN_WKUP_R = crate::BitReader; #[doc = "Field `pmu_rstn_wkup` writer - 1: Assert reset, 0: De-assert reset"] -pub type PMU_RSTN_WKUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PMU_RSTN_WKUP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtc_hms_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RTC_HMS_RSTN_APB_R = crate::BitReader; #[doc = "Field `rtc_hms_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RTC_HMS_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTC_HMS_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtc_hms_rstn_cal` reader - 1: Assert reset, 0: De-assert reset"] pub type RTC_HMS_RSTN_CAL_R = crate::BitReader; #[doc = "Field `rtc_hms_rstn_cal` writer - 1: Assert reset, 0: De-assert reset"] -pub type RTC_HMS_RSTN_CAL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTC_HMS_RSTN_CAL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtc_hms_rstn_osc32k` reader - 1: Assert reset, 0: De-assert reset"] pub type RTC_HMS_RSTN_OSC32K_R = crate::BitReader; #[doc = "Field `rtc_hms_rstn_osc32k` writer - 1: Assert reset, 0: De-assert reset"] -pub type RTC_HMS_RSTN_OSC32K_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTC_HMS_RSTN_OSC32K_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -80,52 +80,56 @@ impl W { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn gmac5_axi64_rstn_axi(&mut self) -> GMAC5_AXI64_RSTN_AXI_W { - GMAC5_AXI64_RSTN_AXI_W::new(self) + pub fn gmac5_axi64_rstn_axi(&mut self) -> GMAC5_AXI64_RSTN_AXI_W { + GMAC5_AXI64_RSTN_AXI_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn gmac5_axi64_rstn_ahb(&mut self) -> GMAC5_AXI64_RSTN_AHB_W { - GMAC5_AXI64_RSTN_AHB_W::new(self) + pub fn gmac5_axi64_rstn_ahb(&mut self) -> GMAC5_AXI64_RSTN_AHB_W { + GMAC5_AXI64_RSTN_AHB_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn aon_iomux_presetn(&mut self) -> AON_IOMUX_PRESETN_W { - AON_IOMUX_PRESETN_W::new(self) + pub fn aon_iomux_presetn(&mut self) -> AON_IOMUX_PRESETN_W { + AON_IOMUX_PRESETN_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn pmu_rstn_apb(&mut self) -> PMU_RSTN_APB_W { - PMU_RSTN_APB_W::new(self) + pub fn pmu_rstn_apb(&mut self) -> PMU_RSTN_APB_W { + PMU_RSTN_APB_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn pmu_rstn_wkup(&mut self) -> PMU_RSTN_WKUP_W { - PMU_RSTN_WKUP_W::new(self) + pub fn pmu_rstn_wkup(&mut self) -> PMU_RSTN_WKUP_W { + PMU_RSTN_WKUP_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rtc_hms_rstn_apb(&mut self) -> RTC_HMS_RSTN_APB_W { - RTC_HMS_RSTN_APB_W::new(self) + pub fn rtc_hms_rstn_apb(&mut self) -> RTC_HMS_RSTN_APB_W { + RTC_HMS_RSTN_APB_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rtc_hms_rstn_cal(&mut self) -> RTC_HMS_RSTN_CAL_W { - RTC_HMS_RSTN_CAL_W::new(self) + pub fn rtc_hms_rstn_cal(&mut self) -> RTC_HMS_RSTN_CAL_W { + RTC_HMS_RSTN_CAL_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rtc_hms_rstn_osc32k(&mut self) -> RTC_HMS_RSTN_OSC32K_W { - RTC_HMS_RSTN_OSC32K_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn rtc_hms_rstn_osc32k(&mut self) -> RTC_HMS_RSTN_OSC32K_W { + RTC_HMS_RSTN_OSC32K_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aoncrg/clk_ahb_gmac5.rs b/jh7110-vf2-13b-pac/src/aoncrg/clk_ahb_gmac5.rs index b031301..1a81926 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg/clk_ahb_gmac5.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg/clk_ahb_gmac5.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aoncrg/clk_aon_apb.rs b/jh7110-vf2-13b-pac/src/aoncrg/clk_aon_apb.rs index bbd5215..95bf754 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg/clk_aon_apb.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg/clk_aon_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_osc_div4, clk_osc"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_osc_div4, clk_osc"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc_div4, clk_osc"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc_div4, clk_osc"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aoncrg/clk_axi_gmac5.rs b/jh7110-vf2-13b-pac/src/aoncrg/clk_axi_gmac5.rs index 00d7b78..beff06a 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg/clk_axi_gmac5.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg/clk_axi_gmac5.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac0_rmii_rtx.rs b/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac0_rmii_rtx.rs index 310e0da..17a7a00 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac0_rmii_rtx.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac0_rmii_rtx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac5_axi64_rx.rs b/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac5_axi64_rx.rs index df8a3f3..287e146 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac5_axi64_rx.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac5_axi64_rx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `dly_chain_sel` reader - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] pub type DLY_CHAIN_SEL_R = crate::FieldReader; #[doc = "Field `dly_chain_sel` writer - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] -pub type DLY_CHAIN_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type DLY_CHAIN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] #[inline(always)] #[must_use] - pub fn dly_chain_sel(&mut self) -> DLY_CHAIN_SEL_W { - DLY_CHAIN_SEL_W::new(self) + pub fn dly_chain_sel(&mut self) -> DLY_CHAIN_SEL_W { + DLY_CHAIN_SEL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac5_axi64_rxi.rs b/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac5_axi64_rxi.rs index 67e5cc8..d1370fb 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac5_axi64_rxi.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac5_axi64_rxi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac5_axi64_tx.rs b/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac5_axi64_tx.rs index ebe5f21..c148a40 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac5_axi64_tx.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac5_axi64_tx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: u0_sys_crg_clk_gmac0_gtxclk, clk_gmac0_rmii_rtx"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: u0_sys_crg_clk_gmac0_gtxclk, clk_gmac0_rmii_rtx"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: u0_sys_crg_clk_gmac0_gtxclk, clk_gmac0_rmii_rtx"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: u0_sys_crg_clk_gmac0_gtxclk, clk_gmac0_rmii_rtx"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac5_axi64_txi.rs b/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac5_axi64_txi.rs index 9bb5777..ee093f4 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac5_axi64_txi.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg/clk_gmac5_axi64_txi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aoncrg/clk_optc_apb.rs b/jh7110-vf2-13b-pac/src/aoncrg/clk_optc_apb.rs index aae9f3b..95f2d7d 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg/clk_optc_apb.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg/clk_optc_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aoncrg/clk_osc.rs b/jh7110-vf2-13b-pac/src/aoncrg/clk_osc.rs index 97a9a1e..c1533ef 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg/clk_osc.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg/clk_osc.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aoncrg/clk_rtc_hms_apb.rs b/jh7110-vf2-13b-pac/src/aoncrg/clk_rtc_hms_apb.rs index 8d5536a..963f47b 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg/clk_rtc_hms_apb.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg/clk_rtc_hms_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aoncrg/clk_rtc_hms_cal.rs b/jh7110-vf2-13b-pac/src/aoncrg/clk_rtc_hms_cal.rs index ceca8e2..e759a1f 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg/clk_rtc_hms_cal.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg/clk_rtc_hms_cal.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aoncrg/clk_rtc_hms_osc32k.rs b/jh7110-vf2-13b-pac/src/aoncrg/clk_rtc_hms_osc32k.rs index b45692e..324c4f2 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg/clk_rtc_hms_osc32k.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg/clk_rtc_hms_osc32k.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_rtc, clk_rtc_internal"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_rtc, clk_rtc_internal"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_rtc, clk_rtc_internal"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_rtc, clk_rtc_internal"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aoncrg/clk_rtc_internal.rs b/jh7110-vf2-13b-pac/src/aoncrg/clk_rtc_internal.rs index 7b7e065..f537c6b 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg/clk_rtc_internal.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg/clk_rtc_internal.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=1022, Default=750, Min=750, Typical=750"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=1022, Default=750, Min=750, Typical=750"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=1022, Default=750, Min=750, Typical=750"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=1022, Default=750, Min=750, Typical=750"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/aoncrg/soft_rst_addr_sel.rs b/jh7110-vf2-13b-pac/src/aoncrg/soft_rst_addr_sel.rs index ac4416a..78952e8 100644 --- a/jh7110-vf2-13b-pac/src/aoncrg/soft_rst_addr_sel.rs +++ b/jh7110-vf2-13b-pac/src/aoncrg/soft_rst_addr_sel.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `gmac5_axi64_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type GMAC5_AXI64_RSTN_AXI_R = crate::BitReader; #[doc = "Field `gmac5_axi64_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type GMAC5_AXI64_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GMAC5_AXI64_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gmac5_axi64_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type GMAC5_AXI64_RSTN_AHB_R = crate::BitReader; #[doc = "Field `gmac5_axi64_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type GMAC5_AXI64_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GMAC5_AXI64_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `aon_iomux_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type AON_IOMUX_PRESETN_R = crate::BitReader; #[doc = "Field `aon_iomux_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type AON_IOMUX_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AON_IOMUX_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pmu_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type PMU_RSTN_APB_R = crate::BitReader; #[doc = "Field `pmu_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type PMU_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PMU_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pmu_rstn_wkup` reader - 1: Assert reset, 0: De-assert reset"] pub type PMU_RSTN_WKUP_R = crate::BitReader; #[doc = "Field `pmu_rstn_wkup` writer - 1: Assert reset, 0: De-assert reset"] -pub type PMU_RSTN_WKUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PMU_RSTN_WKUP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtc_hms_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RTC_HMS_RSTN_APB_R = crate::BitReader; #[doc = "Field `rtc_hms_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RTC_HMS_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTC_HMS_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtc_hms_rstn_cal` reader - 1: Assert reset, 0: De-assert reset"] pub type RTC_HMS_RSTN_CAL_R = crate::BitReader; #[doc = "Field `rtc_hms_rstn_cal` writer - 1: Assert reset, 0: De-assert reset"] -pub type RTC_HMS_RSTN_CAL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTC_HMS_RSTN_CAL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtc_hms_rstn_osc32k` reader - 1: Assert reset, 0: De-assert reset"] pub type RTC_HMS_RSTN_OSC32K_R = crate::BitReader; #[doc = "Field `rtc_hms_rstn_osc32k` writer - 1: Assert reset, 0: De-assert reset"] -pub type RTC_HMS_RSTN_OSC32K_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTC_HMS_RSTN_OSC32K_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -80,52 +80,56 @@ impl W { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn gmac5_axi64_rstn_axi(&mut self) -> GMAC5_AXI64_RSTN_AXI_W { - GMAC5_AXI64_RSTN_AXI_W::new(self) + pub fn gmac5_axi64_rstn_axi(&mut self) -> GMAC5_AXI64_RSTN_AXI_W { + GMAC5_AXI64_RSTN_AXI_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn gmac5_axi64_rstn_ahb(&mut self) -> GMAC5_AXI64_RSTN_AHB_W { - GMAC5_AXI64_RSTN_AHB_W::new(self) + pub fn gmac5_axi64_rstn_ahb(&mut self) -> GMAC5_AXI64_RSTN_AHB_W { + GMAC5_AXI64_RSTN_AHB_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn aon_iomux_presetn(&mut self) -> AON_IOMUX_PRESETN_W { - AON_IOMUX_PRESETN_W::new(self) + pub fn aon_iomux_presetn(&mut self) -> AON_IOMUX_PRESETN_W { + AON_IOMUX_PRESETN_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn pmu_rstn_apb(&mut self) -> PMU_RSTN_APB_W { - PMU_RSTN_APB_W::new(self) + pub fn pmu_rstn_apb(&mut self) -> PMU_RSTN_APB_W { + PMU_RSTN_APB_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn pmu_rstn_wkup(&mut self) -> PMU_RSTN_WKUP_W { - PMU_RSTN_WKUP_W::new(self) + pub fn pmu_rstn_wkup(&mut self) -> PMU_RSTN_WKUP_W { + PMU_RSTN_WKUP_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rtc_hms_rstn_apb(&mut self) -> RTC_HMS_RSTN_APB_W { - RTC_HMS_RSTN_APB_W::new(self) + pub fn rtc_hms_rstn_apb(&mut self) -> RTC_HMS_RSTN_APB_W { + RTC_HMS_RSTN_APB_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rtc_hms_rstn_cal(&mut self) -> RTC_HMS_RSTN_CAL_W { - RTC_HMS_RSTN_CAL_W::new(self) + pub fn rtc_hms_rstn_cal(&mut self) -> RTC_HMS_RSTN_CAL_W { + RTC_HMS_RSTN_CAL_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rtc_hms_rstn_osc32k(&mut self) -> RTC_HMS_RSTN_OSC32K_W { - RTC_HMS_RSTN_OSC32K_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn rtc_hms_rstn_osc32k(&mut self) -> RTC_HMS_RSTN_OSC32K_W { + RTC_HMS_RSTN_OSC32K_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/clint.rs b/jh7110-vf2-13b-pac/src/clint.rs index 42c26c7..f3f4b70 100644 --- a/jh7110-vf2-13b-pac/src/clint.rs +++ b/jh7110-vf2-13b-pac/src/clint.rs @@ -1,82 +1,128 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + msip_0: MSIP_0, + msip_1: MSIP_1, + msip_2: MSIP_2, + msip_3: MSIP_3, + msip_4: MSIP_4, + _reserved5: [u8; 0x3fec], + mtimecmp_0: MTIMECMP_0, + mtimecmp_1: MTIMECMP_1, + mtimecmp_2: MTIMECMP_2, + mtimecmp_3: MTIMECMP_3, + mtimecmp_4: MTIMECMP_4, + _reserved10: [u8; 0x7fd0], + mtime: MTIME, +} +impl RegisterBlock { #[doc = "0x00 - MSIP Register for hart 0"] - pub msip_0: MSIP_0, + #[inline(always)] + pub const fn msip_0(&self) -> &MSIP_0 { + &self.msip_0 + } #[doc = "0x04 - MSIP Register for hart 1"] - pub msip_1: MSIP_1, + #[inline(always)] + pub const fn msip_1(&self) -> &MSIP_1 { + &self.msip_1 + } #[doc = "0x08 - MSIP Register for hart 2"] - pub msip_2: MSIP_2, + #[inline(always)] + pub const fn msip_2(&self) -> &MSIP_2 { + &self.msip_2 + } #[doc = "0x0c - MSIP Register for hart 3"] - pub msip_3: MSIP_3, + #[inline(always)] + pub const fn msip_3(&self) -> &MSIP_3 { + &self.msip_3 + } #[doc = "0x10 - MSIP Register for hart 4"] - pub msip_4: MSIP_4, - _reserved5: [u8; 0x3fec], + #[inline(always)] + pub const fn msip_4(&self) -> &MSIP_4 { + &self.msip_4 + } #[doc = "0x4000..0x4008 - MTIMECMP Register for hart 0"] - pub mtimecmp_0: MTIMECMP_0, + #[inline(always)] + pub const fn mtimecmp_0(&self) -> &MTIMECMP_0 { + &self.mtimecmp_0 + } #[doc = "0x4008..0x4010 - MTIMECMP Register for hart 1"] - pub mtimecmp_1: MTIMECMP_1, + #[inline(always)] + pub const fn mtimecmp_1(&self) -> &MTIMECMP_1 { + &self.mtimecmp_1 + } #[doc = "0x4010..0x4018 - MTIMECMP Register for hart 2"] - pub mtimecmp_2: MTIMECMP_2, + #[inline(always)] + pub const fn mtimecmp_2(&self) -> &MTIMECMP_2 { + &self.mtimecmp_2 + } #[doc = "0x4018..0x4020 - MTIMECMP Register for hart 3"] - pub mtimecmp_3: MTIMECMP_3, + #[inline(always)] + pub const fn mtimecmp_3(&self) -> &MTIMECMP_3 { + &self.mtimecmp_3 + } #[doc = "0x4020..0x4028 - MTIMECMP Register for hart 4"] - pub mtimecmp_4: MTIMECMP_4, - _reserved10: [u8; 0x7fd0], + #[inline(always)] + pub const fn mtimecmp_4(&self) -> &MTIMECMP_4 { + &self.mtimecmp_4 + } #[doc = "0xbff8..0xc000 - MTIME Register"] - pub mtime: MTIME, + #[inline(always)] + pub const fn mtime(&self) -> &MTIME { + &self.mtime + } } -#[doc = "msip_0 (rw) register accessor: MSIP Register for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msip_0`] +#[doc = "msip_0 (rw) register accessor: MSIP Register for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msip_0`] module"] pub type MSIP_0 = crate::Reg; #[doc = "MSIP Register for hart 0"] pub mod msip_0; -#[doc = "msip_1 (rw) register accessor: MSIP Register for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msip_1`] +#[doc = "msip_1 (rw) register accessor: MSIP Register for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msip_1`] module"] pub type MSIP_1 = crate::Reg; #[doc = "MSIP Register for hart 1"] pub mod msip_1; -#[doc = "msip_2 (rw) register accessor: MSIP Register for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msip_2`] +#[doc = "msip_2 (rw) register accessor: MSIP Register for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msip_2`] module"] pub type MSIP_2 = crate::Reg; #[doc = "MSIP Register for hart 2"] pub mod msip_2; -#[doc = "msip_3 (rw) register accessor: MSIP Register for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msip_3`] +#[doc = "msip_3 (rw) register accessor: MSIP Register for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msip_3`] module"] pub type MSIP_3 = crate::Reg; #[doc = "MSIP Register for hart 3"] pub mod msip_3; -#[doc = "msip_4 (rw) register accessor: MSIP Register for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msip_4`] +#[doc = "msip_4 (rw) register accessor: MSIP Register for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msip_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msip_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msip_4`] module"] pub type MSIP_4 = crate::Reg; #[doc = "MSIP Register for hart 4"] pub mod msip_4; -#[doc = "mtimecmp_0 (rw) register accessor: MTIMECMP Register for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mtimecmp_0`] +#[doc = "mtimecmp_0 (rw) register accessor: MTIMECMP Register for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimecmp_0`] module"] pub type MTIMECMP_0 = crate::Reg; #[doc = "MTIMECMP Register for hart 0"] pub mod mtimecmp_0; -#[doc = "mtimecmp_1 (rw) register accessor: MTIMECMP Register for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mtimecmp_1`] +#[doc = "mtimecmp_1 (rw) register accessor: MTIMECMP Register for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimecmp_1`] module"] pub type MTIMECMP_1 = crate::Reg; #[doc = "MTIMECMP Register for hart 1"] pub mod mtimecmp_1; -#[doc = "mtimecmp_2 (rw) register accessor: MTIMECMP Register for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mtimecmp_2`] +#[doc = "mtimecmp_2 (rw) register accessor: MTIMECMP Register for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimecmp_2`] module"] pub type MTIMECMP_2 = crate::Reg; #[doc = "MTIMECMP Register for hart 2"] pub mod mtimecmp_2; -#[doc = "mtimecmp_3 (rw) register accessor: MTIMECMP Register for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mtimecmp_3`] +#[doc = "mtimecmp_3 (rw) register accessor: MTIMECMP Register for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimecmp_3`] module"] pub type MTIMECMP_3 = crate::Reg; #[doc = "MTIMECMP Register for hart 3"] pub mod mtimecmp_3; -#[doc = "mtimecmp_4 (rw) register accessor: MTIMECMP Register for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mtimecmp_4`] +#[doc = "mtimecmp_4 (rw) register accessor: MTIMECMP Register for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimecmp_4`] module"] pub type MTIMECMP_4 = crate::Reg; #[doc = "MTIMECMP Register for hart 4"] pub mod mtimecmp_4; -#[doc = "mtime (rw) register accessor: MTIME Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtime::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtime::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mtime`] +#[doc = "mtime (rw) register accessor: MTIME Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtime::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtime::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtime`] module"] pub type MTIME = crate::Reg; #[doc = "MTIME Register"] diff --git a/jh7110-vf2-13b-pac/src/clint/msip_0.rs b/jh7110-vf2-13b-pac/src/clint/msip_0.rs index 0b60c42..a61378a 100644 --- a/jh7110-vf2-13b-pac/src/clint/msip_0.rs +++ b/jh7110-vf2-13b-pac/src/clint/msip_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/clint/msip_1.rs b/jh7110-vf2-13b-pac/src/clint/msip_1.rs index 66fc898..6fa7e52 100644 --- a/jh7110-vf2-13b-pac/src/clint/msip_1.rs +++ b/jh7110-vf2-13b-pac/src/clint/msip_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/clint/msip_2.rs b/jh7110-vf2-13b-pac/src/clint/msip_2.rs index 51fa11e..a089709 100644 --- a/jh7110-vf2-13b-pac/src/clint/msip_2.rs +++ b/jh7110-vf2-13b-pac/src/clint/msip_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/clint/msip_3.rs b/jh7110-vf2-13b-pac/src/clint/msip_3.rs index f1a6a08..3a389fe 100644 --- a/jh7110-vf2-13b-pac/src/clint/msip_3.rs +++ b/jh7110-vf2-13b-pac/src/clint/msip_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/clint/msip_4.rs b/jh7110-vf2-13b-pac/src/clint/msip_4.rs index 23015f8..7ec7c2c 100644 --- a/jh7110-vf2-13b-pac/src/clint/msip_4.rs +++ b/jh7110-vf2-13b-pac/src/clint/msip_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/clint/mtime.rs b/jh7110-vf2-13b-pac/src/clint/mtime.rs index c5a3aa2..3e976b3 100644 --- a/jh7110-vf2-13b-pac/src/clint/mtime.rs +++ b/jh7110-vf2-13b-pac/src/clint/mtime.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u64) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/clint/mtimecmp_0.rs b/jh7110-vf2-13b-pac/src/clint/mtimecmp_0.rs index 611f411..9a1b9eb 100644 --- a/jh7110-vf2-13b-pac/src/clint/mtimecmp_0.rs +++ b/jh7110-vf2-13b-pac/src/clint/mtimecmp_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u64) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/clint/mtimecmp_1.rs b/jh7110-vf2-13b-pac/src/clint/mtimecmp_1.rs index 176bbf9..c12b004 100644 --- a/jh7110-vf2-13b-pac/src/clint/mtimecmp_1.rs +++ b/jh7110-vf2-13b-pac/src/clint/mtimecmp_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u64) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/clint/mtimecmp_2.rs b/jh7110-vf2-13b-pac/src/clint/mtimecmp_2.rs index bbb635b..5595999 100644 --- a/jh7110-vf2-13b-pac/src/clint/mtimecmp_2.rs +++ b/jh7110-vf2-13b-pac/src/clint/mtimecmp_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u64) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/clint/mtimecmp_3.rs b/jh7110-vf2-13b-pac/src/clint/mtimecmp_3.rs index 4fac76a..e646879 100644 --- a/jh7110-vf2-13b-pac/src/clint/mtimecmp_3.rs +++ b/jh7110-vf2-13b-pac/src/clint/mtimecmp_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u64) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/clint/mtimecmp_4.rs b/jh7110-vf2-13b-pac/src/clint/mtimecmp_4.rs index 5db21c3..483d6bf 100644 --- a/jh7110-vf2-13b-pac/src/clint/mtimecmp_4.rs +++ b/jh7110-vf2-13b-pac/src/clint/mtimecmp_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u64) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/generic.rs b/jh7110-vf2-13b-pac/src/generic.rs index 551a0ae..59c8e74 100644 --- a/jh7110-vf2-13b-pac/src/generic.rs +++ b/jh7110-vf2-13b-pac/src/generic.rs @@ -243,7 +243,7 @@ pub type R = raw::R; impl R { #[doc = " Reads raw bits from register."] #[inline(always)] - pub fn bits(&self) -> REG::Ux { + pub const fn bits(&self) -> REG::Ux { self.bits } } @@ -271,7 +271,7 @@ pub type BitReader = raw::BitReader; impl FieldReader { #[doc = " Reads raw bits from field."] #[inline(always)] - pub fn bits(&self) -> FI::Ux { + pub const fn bits(&self) -> FI::Ux { self.bits } } @@ -297,17 +297,17 @@ where impl BitReader { #[doc = " Value of the field as raw bits."] #[inline(always)] - pub fn bit(&self) -> bool { + pub const fn bit(&self) -> bool { self.bits } #[doc = " Returns `true` if the bit is clear (0)."] #[inline(always)] - pub fn bit_is_clear(&self) -> bool { + pub const fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = " Returns `true` if the bit is set (1)."] #[inline(always)] - pub fn bit_is_set(&self) -> bool { + pub const fn bit_is_set(&self) -> bool { self.bit() } } @@ -316,55 +316,103 @@ pub struct Safe; #[doc(hidden)] pub struct Unsafe; #[doc = " Write field Proxy with unsafe `bits`"] -pub type FieldWriter<'a, REG, const WI: u8, const O: u8, FI = u8> = - raw::FieldWriter<'a, REG, WI, O, FI, Unsafe>; +pub type FieldWriter<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Unsafe>; #[doc = " Write field Proxy with safe `bits`"] -pub type FieldWriterSafe<'a, REG, const WI: u8, const O: u8, FI = u8> = - raw::FieldWriter<'a, REG, WI, O, FI, Safe>; -impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriter<'a, REG, WI, OF, FI> +pub type FieldWriterSafe<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Safe>; +impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI> where REG: Writable + RegisterSpec, FI: FieldSpec, + REG::Ux: From, { #[doc = " Field width"] pub const WIDTH: u8 = WI; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + WI + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + unsafe { self.bits(FI::Ux::from(variant)) } + } } -impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriterSafe<'a, REG, WI, OF, FI> +impl<'a, REG, const WI: u8, FI> FieldWriterSafe<'a, REG, WI, FI> where REG: Writable + RegisterSpec, FI: FieldSpec, + REG::Ux: From, { #[doc = " Field width"] pub const WIDTH: u8 = WI; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + WI + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + self.bits(FI::Ux::from(variant)) + } } macro_rules! bit_proxy { ($ writer : ident , $ mwv : ident) => { #[doc(hidden)] pub struct $mwv; #[doc = " Bit-wise write field proxy"] - pub type $writer<'a, REG, const O: u8, FI = bool> = raw::BitWriter<'a, REG, O, FI, $mwv>; - impl<'a, REG, const OF: u8, FI> $writer<'a, REG, OF, FI> + pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>; + impl<'a, REG, FI> $writer<'a, REG, FI> where REG: Writable + RegisterSpec, bool: From, { #[doc = " Field width"] pub const WIDTH: u8 = 1; - } - }; -} -macro_rules! impl_bit_proxy { - ($ writer : ident) => { - impl<'a, REG, const OF: u8, FI> $writer<'a, REG, OF, FI> - where - REG: Writable + RegisterSpec, - bool: From, - { + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + Self::WIDTH + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } #[doc = " Writes bit to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << OF); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << OF; + self.w.bits &= !(REG::Ux::one() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o; self.w } #[doc = " Writes `variant` to the field"] @@ -382,56 +430,7 @@ bit_proxy!(BitWriter1C, Bit1C); bit_proxy!(BitWriter0S, Bit0S); bit_proxy!(BitWriter1T, Bit1T); bit_proxy!(BitWriter0T, Bit0T); -impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriter<'a, REG, WI, OF, FI> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, -{ - #[doc = " Writes raw bits to the field"] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { - self.w.bits &= !(REG::Ux::mask::() << OF); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut W { - unsafe { self.bits(FI::Ux::from(variant)) } - } -} -impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriterSafe<'a, REG, WI, OF, FI> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, -{ - #[doc = " Writes raw bits to the field"] - #[inline(always)] - pub fn bits(self, value: FI::Ux) -> &'a mut W { - self.w.bits &= !(REG::Ux::mask::() << OF); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut W { - self.bits(FI::Ux::from(variant)) - } -} -impl_bit_proxy!(BitWriter); -impl_bit_proxy!(BitWriter1S); -impl_bit_proxy!(BitWriter0C); -impl_bit_proxy!(BitWriter1C); -impl_bit_proxy!(BitWriter0S); -impl_bit_proxy!(BitWriter1T); -impl_bit_proxy!(BitWriter0T); -impl<'a, REG, const OF: u8, FI> BitWriter<'a, REG, OF, FI> +impl<'a, REG, FI> BitWriter<'a, REG, FI> where REG: Writable + RegisterSpec, bool: From, @@ -439,17 +438,17 @@ where #[doc = " Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { - self.w.bits |= REG::Ux::one() << OF; + self.w.bits |= REG::Ux::one() << self.o; self.w } #[doc = " Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << OF); + self.w.bits &= !(REG::Ux::one() << self.o); self.w } } -impl<'a, REG, const OF: u8, FI> BitWriter1S<'a, REG, OF, FI> +impl<'a, REG, FI> BitWriter1S<'a, REG, FI> where REG: Writable + RegisterSpec, bool: From, @@ -457,11 +456,11 @@ where #[doc = " Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { - self.w.bits |= REG::Ux::one() << OF; + self.w.bits |= REG::Ux::one() << self.o; self.w } } -impl<'a, REG, const OF: u8, FI> BitWriter0C<'a, REG, OF, FI> +impl<'a, REG, FI> BitWriter0C<'a, REG, FI> where REG: Writable + RegisterSpec, bool: From, @@ -469,11 +468,11 @@ where #[doc = " Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << OF); + self.w.bits &= !(REG::Ux::one() << self.o); self.w } } -impl<'a, REG, const OF: u8, FI> BitWriter1C<'a, REG, OF, FI> +impl<'a, REG, FI> BitWriter1C<'a, REG, FI> where REG: Writable + RegisterSpec, bool: From, @@ -481,11 +480,11 @@ where #[doc = "Clears the field bit by passing one"] #[inline(always)] pub fn clear_bit_by_one(self) -> &'a mut W { - self.w.bits |= REG::Ux::one() << OF; + self.w.bits |= REG::Ux::one() << self.o; self.w } } -impl<'a, REG, const OF: u8, FI> BitWriter0S<'a, REG, OF, FI> +impl<'a, REG, FI> BitWriter0S<'a, REG, FI> where REG: Writable + RegisterSpec, bool: From, @@ -493,11 +492,11 @@ where #[doc = "Sets the field bit by passing zero"] #[inline(always)] pub fn set_bit_by_zero(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << OF); + self.w.bits &= !(REG::Ux::one() << self.o); self.w } } -impl<'a, REG, const OF: u8, FI> BitWriter1T<'a, REG, OF, FI> +impl<'a, REG, FI> BitWriter1T<'a, REG, FI> where REG: Writable + RegisterSpec, bool: From, @@ -505,11 +504,11 @@ where #[doc = "Toggle the field bit by passing one"] #[inline(always)] pub fn toggle_bit(self) -> &'a mut W { - self.w.bits |= REG::Ux::one() << OF; + self.w.bits |= REG::Ux::one() << self.o; self.w } } -impl<'a, REG, const OF: u8, FI> BitWriter0T<'a, REG, OF, FI> +impl<'a, REG, FI> BitWriter0T<'a, REG, FI> where REG: Writable + RegisterSpec, bool: From, @@ -517,7 +516,7 @@ where #[doc = "Toggle the field bit by passing zero"] #[inline(always)] pub fn toggle_bit(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << OF); + self.w.bits &= !(REG::Ux::one() << self.o); self.w } } diff --git a/jh7110-vf2-13b-pac/src/generic/raw.rs b/jh7110-vf2-13b-pac/src/generic/raw.rs index 74e7752..81f5779 100644 --- a/jh7110-vf2-13b-pac/src/generic/raw.rs +++ b/jh7110-vf2-13b-pac/src/generic/raw.rs @@ -19,7 +19,7 @@ impl FieldReader { #[doc = " Creates a new instance of the reader."] #[allow(unused)] #[inline(always)] - pub(crate) fn new(bits: FI::Ux) -> Self { + pub(crate) const fn new(bits: FI::Ux) -> Self { Self { bits, _reg: marker::PhantomData, @@ -34,22 +34,23 @@ impl BitReader { #[doc = " Creates a new instance of the reader."] #[allow(unused)] #[inline(always)] - pub(crate) fn new(bits: bool) -> Self { + pub(crate) const fn new(bits: bool) -> Self { Self { bits, _reg: marker::PhantomData, } } } -pub struct FieldWriter<'a, REG, const WI: u8, const O: u8, FI = u8, Safety = Unsafe> +pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> where REG: Writable + RegisterSpec, FI: FieldSpec, { pub(crate) w: &'a mut W, + pub(crate) o: u8, _field: marker::PhantomData<(FI, Safety)>, } -impl<'a, REG, const WI: u8, const O: u8, FI, Safety> FieldWriter<'a, REG, WI, O, FI, Safety> +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> where REG: Writable + RegisterSpec, FI: FieldSpec, @@ -57,22 +58,24 @@ where #[doc = " Creates a new instance of the writer"] #[allow(unused)] #[inline(always)] - pub(crate) fn new(w: &'a mut W) -> Self { + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { Self { w, + o, _field: marker::PhantomData, } } } -pub struct BitWriter<'a, REG, const O: u8, FI = bool, M = BitM> +pub struct BitWriter<'a, REG, FI = bool, M = BitM> where REG: Writable + RegisterSpec, bool: From, { pub(crate) w: &'a mut W, + pub(crate) o: u8, _field: marker::PhantomData<(FI, M)>, } -impl<'a, REG, const O: u8, FI, M> BitWriter<'a, REG, O, FI, M> +impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M> where REG: Writable + RegisterSpec, bool: From, @@ -80,9 +83,10 @@ where #[doc = " Creates a new instance of the writer"] #[allow(unused)] #[inline(always)] - pub(crate) fn new(w: &'a mut W) -> Self { + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { Self { w, + o, _field: marker::PhantomData, } } diff --git a/jh7110-vf2-13b-pac/src/i2c0.rs b/jh7110-vf2-13b-pac/src/i2c0.rs index d0fe76a..fdffe28 100644 --- a/jh7110-vf2-13b-pac/src/i2c0.rs +++ b/jh7110-vf2-13b-pac/src/i2c0.rs @@ -1,266 +1,416 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + con: CON, + tar: TAR, + sar: SAR, + _reserved3: [u8; 0x04], + data_cmd: DATA_CMD, + ss_scl_hcnt: SS_SCL_HCNT, + ss_scl_lcnt: SS_SCL_LCNT, + fs_scl_hcnt: FS_SCL_HCNT, + fs_scl_lcnt: FS_SCL_LCNT, + hs_scl_hcnt: HS_SCL_HCNT, + hs_scl_lcnt: HS_SCL_LCNT, + intr_stat: INTR_STAT, + intr_mask: INTR_MASK, + raw_intr_stat: RAW_INTR_STAT, + rx_tl: RX_TL, + tx_tl: TX_TL, + clr_intr: CLR_INTR, + clr_rx_under: CLR_RX_UNDER, + clr_rx_over: CLR_RX_OVER, + clr_tx_over: CLR_TX_OVER, + clr_rd_req: CLR_RD_REQ, + clr_tx_abrt: CLR_TX_ABRT, + clr_rx_done: CLR_RX_DONE, + clr_activity: CLR_ACTIVITY, + clr_stop_det: CLR_STOP_DET, + clr_start_det: CLR_START_DET, + clr_gen_call: CLR_GEN_CALL, + enable: ENABLE, + status: STATUS, + txflr: TXFLR, + rxflr: RXFLR, + sda_hold: SDA_HOLD, + tx_abrt_source: TX_ABRT_SOURCE, + _reserved32: [u8; 0x18], + enable_status: ENABLE_STATUS, + _reserved33: [u8; 0x08], + clr_restart_det: CLR_RESTART_DET, + _reserved34: [u8; 0x48], + comp_param_1: COMP_PARAM_1, + comp_version: COMP_VERSION, + comp_type: COMP_TYPE, +} +impl RegisterBlock { #[doc = "0x00 - DesignWare I2C CON"] - pub con: CON, + #[inline(always)] + pub const fn con(&self) -> &CON { + &self.con + } #[doc = "0x04 - DesignWare I2C TAR"] - pub tar: TAR, + #[inline(always)] + pub const fn tar(&self) -> &TAR { + &self.tar + } #[doc = "0x08 - DesignWare I2C SAR"] - pub sar: SAR, - _reserved3: [u8; 0x04], + #[inline(always)] + pub const fn sar(&self) -> &SAR { + &self.sar + } #[doc = "0x10 - DesignWare I2C Data Command"] - pub data_cmd: DATA_CMD, + #[inline(always)] + pub const fn data_cmd(&self) -> &DATA_CMD { + &self.data_cmd + } #[doc = "0x14 - DesignWare I2C SS SCL HCNT"] - pub ss_scl_hcnt: SS_SCL_HCNT, + #[inline(always)] + pub const fn ss_scl_hcnt(&self) -> &SS_SCL_HCNT { + &self.ss_scl_hcnt + } #[doc = "0x18 - DesignWare I2C SS SCL LCNT"] - pub ss_scl_lcnt: SS_SCL_LCNT, + #[inline(always)] + pub const fn ss_scl_lcnt(&self) -> &SS_SCL_LCNT { + &self.ss_scl_lcnt + } #[doc = "0x1c - DesignWare I2C FS SCL HCNT"] - pub fs_scl_hcnt: FS_SCL_HCNT, + #[inline(always)] + pub const fn fs_scl_hcnt(&self) -> &FS_SCL_HCNT { + &self.fs_scl_hcnt + } #[doc = "0x20 - DesignWare I2C FS SCL LCNT"] - pub fs_scl_lcnt: FS_SCL_LCNT, + #[inline(always)] + pub const fn fs_scl_lcnt(&self) -> &FS_SCL_LCNT { + &self.fs_scl_lcnt + } #[doc = "0x24 - DesignWare I2C HS SCL HCNT"] - pub hs_scl_hcnt: HS_SCL_HCNT, + #[inline(always)] + pub const fn hs_scl_hcnt(&self) -> &HS_SCL_HCNT { + &self.hs_scl_hcnt + } #[doc = "0x28 - DesignWare I2C HS SCL LCNT"] - pub hs_scl_lcnt: HS_SCL_LCNT, + #[inline(always)] + pub const fn hs_scl_lcnt(&self) -> &HS_SCL_LCNT { + &self.hs_scl_lcnt + } #[doc = "0x2c - DesignWare I2C Interrupt Status"] - pub intr_stat: INTR_STAT, + #[inline(always)] + pub const fn intr_stat(&self) -> &INTR_STAT { + &self.intr_stat + } #[doc = "0x30 - DesignWare I2C Interrupt Mask"] - pub intr_mask: INTR_MASK, + #[inline(always)] + pub const fn intr_mask(&self) -> &INTR_MASK { + &self.intr_mask + } #[doc = "0x34 - DesignWare I2C Raw Interrupt Status"] - pub raw_intr_stat: RAW_INTR_STAT, + #[inline(always)] + pub const fn raw_intr_stat(&self) -> &RAW_INTR_STAT { + &self.raw_intr_stat + } #[doc = "0x38 - DesignWare I2C RX TL"] - pub rx_tl: RX_TL, + #[inline(always)] + pub const fn rx_tl(&self) -> &RX_TL { + &self.rx_tl + } #[doc = "0x3c - DesignWare I2C TX TL"] - pub tx_tl: TX_TL, + #[inline(always)] + pub const fn tx_tl(&self) -> &TX_TL { + &self.tx_tl + } #[doc = "0x40 - DesignWare I2C Clear Interrrupt"] - pub clr_intr: CLR_INTR, + #[inline(always)] + pub const fn clr_intr(&self) -> &CLR_INTR { + &self.clr_intr + } #[doc = "0x44 - DesignWare I2C Clear RX Underrun"] - pub clr_rx_under: CLR_RX_UNDER, + #[inline(always)] + pub const fn clr_rx_under(&self) -> &CLR_RX_UNDER { + &self.clr_rx_under + } #[doc = "0x48 - DesignWare I2C Clear RX Overrun"] - pub clr_rx_over: CLR_RX_OVER, + #[inline(always)] + pub const fn clr_rx_over(&self) -> &CLR_RX_OVER { + &self.clr_rx_over + } #[doc = "0x4c - DesignWare I2C Clear TX Overrun"] - pub clr_tx_over: CLR_TX_OVER, + #[inline(always)] + pub const fn clr_tx_over(&self) -> &CLR_TX_OVER { + &self.clr_tx_over + } #[doc = "0x50 - DesignWare I2C Clear Read Request"] - pub clr_rd_req: CLR_RD_REQ, + #[inline(always)] + pub const fn clr_rd_req(&self) -> &CLR_RD_REQ { + &self.clr_rd_req + } #[doc = "0x54 - DesignWare I2C Clear TX Abort"] - pub clr_tx_abrt: CLR_TX_ABRT, + #[inline(always)] + pub const fn clr_tx_abrt(&self) -> &CLR_TX_ABRT { + &self.clr_tx_abrt + } #[doc = "0x58 - DesignWare I2C Clear RX Done"] - pub clr_rx_done: CLR_RX_DONE, + #[inline(always)] + pub const fn clr_rx_done(&self) -> &CLR_RX_DONE { + &self.clr_rx_done + } #[doc = "0x5c - DesignWare I2C Clear Activity"] - pub clr_activity: CLR_ACTIVITY, + #[inline(always)] + pub const fn clr_activity(&self) -> &CLR_ACTIVITY { + &self.clr_activity + } #[doc = "0x60 - DesignWare I2C Clear Stop DET"] - pub clr_stop_det: CLR_STOP_DET, + #[inline(always)] + pub const fn clr_stop_det(&self) -> &CLR_STOP_DET { + &self.clr_stop_det + } #[doc = "0x64 - DesignWare I2C Clear Start DET"] - pub clr_start_det: CLR_START_DET, + #[inline(always)] + pub const fn clr_start_det(&self) -> &CLR_START_DET { + &self.clr_start_det + } #[doc = "0x68 - DesignWare I2C Clear General Call"] - pub clr_gen_call: CLR_GEN_CALL, + #[inline(always)] + pub const fn clr_gen_call(&self) -> &CLR_GEN_CALL { + &self.clr_gen_call + } #[doc = "0x6c - DesignWare I2C Enable"] - pub enable: ENABLE, + #[inline(always)] + pub const fn enable(&self) -> &ENABLE { + &self.enable + } #[doc = "0x70 - DesignWare I2C Status"] - pub status: STATUS, + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } #[doc = "0x74 - DesignWare I2C TX Failure"] - pub txflr: TXFLR, + #[inline(always)] + pub const fn txflr(&self) -> &TXFLR { + &self.txflr + } #[doc = "0x78 - DesignWare I2C RX Failure"] - pub rxflr: RXFLR, + #[inline(always)] + pub const fn rxflr(&self) -> &RXFLR { + &self.rxflr + } #[doc = "0x7c - DesignWare I2C SDA Hold"] - pub sda_hold: SDA_HOLD, + #[inline(always)] + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold + } #[doc = "0x80 - DesignWare I2C TX Abort Source"] - pub tx_abrt_source: TX_ABRT_SOURCE, - _reserved32: [u8; 0x18], + #[inline(always)] + pub const fn tx_abrt_source(&self) -> &TX_ABRT_SOURCE { + &self.tx_abrt_source + } #[doc = "0x9c - DesignWare I2C Enable Status"] - pub enable_status: ENABLE_STATUS, - _reserved33: [u8; 0x08], + #[inline(always)] + pub const fn enable_status(&self) -> &ENABLE_STATUS { + &self.enable_status + } #[doc = "0xa8 - DesignWare I2C Clear Restart DET"] - pub clr_restart_det: CLR_RESTART_DET, - _reserved34: [u8; 0x48], + #[inline(always)] + pub const fn clr_restart_det(&self) -> &CLR_RESTART_DET { + &self.clr_restart_det + } #[doc = "0xf4 - DesignWare I2C Compatibility Parameter 1"] - pub comp_param_1: COMP_PARAM_1, + #[inline(always)] + pub const fn comp_param_1(&self) -> &COMP_PARAM_1 { + &self.comp_param_1 + } #[doc = "0xf8 - DesignWare I2C Compatibility Version"] - pub comp_version: COMP_VERSION, + #[inline(always)] + pub const fn comp_version(&self) -> &COMP_VERSION { + &self.comp_version + } #[doc = "0xfc - DesignWare I2C Compatibility Type"] - pub comp_type: COMP_TYPE, + #[inline(always)] + pub const fn comp_type(&self) -> &COMP_TYPE { + &self.comp_type + } } -#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`con`] +#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@con`] module"] pub type CON = crate::Reg; #[doc = "DesignWare I2C CON"] pub mod con; -#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tar`] +#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar`] module"] pub type TAR = crate::Reg; #[doc = "DesignWare I2C TAR"] pub mod tar; -#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sar`] +#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`] module"] pub type SAR = crate::Reg; #[doc = "DesignWare I2C SAR"] pub mod sar; -#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`data_cmd`] +#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_cmd`] module"] pub type DATA_CMD = crate::Reg; #[doc = "DesignWare I2C Data Command"] pub mod data_cmd; -#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_hcnt`] +#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_hcnt`] module"] pub type SS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL HCNT"] pub mod ss_scl_hcnt; -#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_lcnt`] +#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_lcnt`] module"] pub type SS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL LCNT"] pub mod ss_scl_lcnt; -#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_hcnt`] +#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_hcnt`] module"] pub type FS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL HCNT"] pub mod fs_scl_hcnt; -#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_lcnt`] +#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_lcnt`] module"] pub type FS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL LCNT"] pub mod fs_scl_lcnt; -#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_hcnt`] +#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_hcnt`] module"] pub type HS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL HCNT"] pub mod hs_scl_hcnt; -#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_lcnt`] +#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_lcnt`] module"] pub type HS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL LCNT"] pub mod hs_scl_lcnt; -#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_stat`] +#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"] pub type INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Interrupt Status"] pub mod intr_stat; -#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_mask`] +#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mask`] module"] pub type INTR_MASK = crate::Reg; #[doc = "DesignWare I2C Interrupt Mask"] pub mod intr_mask; -#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`raw_intr_stat`] +#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"] pub type RAW_INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Raw Interrupt Status"] pub mod raw_intr_stat; -#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rx_tl`] +#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tl`] module"] pub type RX_TL = crate::Reg; #[doc = "DesignWare I2C RX TL"] pub mod rx_tl; -#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_tl`] +#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_tl`] module"] pub type TX_TL = crate::Reg; #[doc = "DesignWare I2C TX TL"] pub mod tx_tl; -#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_intr`] +#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_intr`] module"] pub type CLR_INTR = crate::Reg; #[doc = "DesignWare I2C Clear Interrrupt"] pub mod clr_intr; -#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_under`] +#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_under`] module"] pub type CLR_RX_UNDER = crate::Reg; #[doc = "DesignWare I2C Clear RX Underrun"] pub mod clr_rx_under; -#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_over`] +#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_over`] module"] pub type CLR_RX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear RX Overrun"] pub mod clr_rx_over; -#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_over`] +#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_over`] module"] pub type CLR_TX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear TX Overrun"] pub mod clr_tx_over; -#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rd_req`] +#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rd_req`] module"] pub type CLR_RD_REQ = crate::Reg; #[doc = "DesignWare I2C Clear Read Request"] pub mod clr_rd_req; -#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_abrt`] +#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_abrt`] module"] pub type CLR_TX_ABRT = crate::Reg; #[doc = "DesignWare I2C Clear TX Abort"] pub mod clr_tx_abrt; -#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_done`] +#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_done`] module"] pub type CLR_RX_DONE = crate::Reg; #[doc = "DesignWare I2C Clear RX Done"] pub mod clr_rx_done; -#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_activity`] +#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_activity`] module"] pub type CLR_ACTIVITY = crate::Reg; #[doc = "DesignWare I2C Clear Activity"] pub mod clr_activity; -#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_stop_det`] +#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_stop_det`] module"] pub type CLR_STOP_DET = crate::Reg; #[doc = "DesignWare I2C Clear Stop DET"] pub mod clr_stop_det; -#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_start_det`] +#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_start_det`] module"] pub type CLR_START_DET = crate::Reg; #[doc = "DesignWare I2C Clear Start DET"] pub mod clr_start_det; -#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_gen_call`] +#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_gen_call`] module"] pub type CLR_GEN_CALL = crate::Reg; #[doc = "DesignWare I2C Clear General Call"] pub mod clr_gen_call; -#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable`] +#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] pub type ENABLE = crate::Reg; #[doc = "DesignWare I2C Enable"] pub mod enable; -#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`status`] +#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] pub type STATUS = crate::Reg; #[doc = "DesignWare I2C Status"] pub mod status; -#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txflr`] +#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txflr`] module"] pub type TXFLR = crate::Reg; #[doc = "DesignWare I2C TX Failure"] pub mod txflr; -#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxflr`] +#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxflr`] module"] pub type RXFLR = crate::Reg; #[doc = "DesignWare I2C RX Failure"] pub mod rxflr; -#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sda_hold`] +#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] pub type SDA_HOLD = crate::Reg; #[doc = "DesignWare I2C SDA Hold"] pub mod sda_hold; -#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_abrt_source`] +#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_abrt_source`] module"] pub type TX_ABRT_SOURCE = crate::Reg; #[doc = "DesignWare I2C TX Abort Source"] pub mod tx_abrt_source; -#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_status`] +#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_status`] module"] pub type ENABLE_STATUS = crate::Reg; #[doc = "DesignWare I2C Enable Status"] pub mod enable_status; -#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_restart_det`] +#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_restart_det`] module"] pub type CLR_RESTART_DET = crate::Reg; #[doc = "DesignWare I2C Clear Restart DET"] pub mod clr_restart_det; -#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_param_1`] +#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_param_1`] module"] pub type COMP_PARAM_1 = crate::Reg; #[doc = "DesignWare I2C Compatibility Parameter 1"] pub mod comp_param_1; -#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_version`] +#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_version`] module"] pub type COMP_VERSION = crate::Reg; #[doc = "DesignWare I2C Compatibility Version"] pub mod comp_version; -#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_type`] +#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_type`] module"] pub type COMP_TYPE = crate::Reg; #[doc = "DesignWare I2C Compatibility Type"] diff --git a/jh7110-vf2-13b-pac/src/i2c0/clr_activity.rs b/jh7110-vf2-13b-pac/src/i2c0/clr_activity.rs index d26bb80..1ee2297 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/clr_activity.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/clr_activity.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_activity` reader - clr_activity"] pub type CLR_ACTIVITY_R = crate::FieldReader; #[doc = "Field `clr_activity` writer - clr_activity"] -pub type CLR_ACTIVITY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_ACTIVITY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] #[must_use] - pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { - CLR_ACTIVITY_W::new(self) + pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { + CLR_ACTIVITY_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/clr_gen_call.rs b/jh7110-vf2-13b-pac/src/i2c0/clr_gen_call.rs index a9ea5af..4a7c5ba 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/clr_gen_call.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/clr_gen_call.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_gen_call` reader - clr_gen_call"] pub type CLR_GEN_CALL_R = crate::FieldReader; #[doc = "Field `clr_gen_call` writer - clr_gen_call"] -pub type CLR_GEN_CALL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_GEN_CALL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] #[must_use] - pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { - CLR_GEN_CALL_W::new(self) + pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { + CLR_GEN_CALL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/clr_intr.rs b/jh7110-vf2-13b-pac/src/i2c0/clr_intr.rs index a7daf57..cf57b09 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/clr_intr.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/clr_intr.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/clr_rd_req.rs b/jh7110-vf2-13b-pac/src/i2c0/clr_rd_req.rs index e275da1..4beae9d 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/clr_rd_req.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/clr_rd_req.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rd_req` reader - clr_rd_req"] pub type CLR_RD_REQ_R = crate::FieldReader; #[doc = "Field `clr_rd_req` writer - clr_rd_req"] -pub type CLR_RD_REQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RD_REQ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] #[must_use] - pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { - CLR_RD_REQ_W::new(self) + pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { + CLR_RD_REQ_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/clr_restart_det.rs b/jh7110-vf2-13b-pac/src/i2c0/clr_restart_det.rs index 5be7f5d..88d193c 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/clr_restart_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/clr_restart_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_restart_det` reader - clr_restart_det"] pub type CLR_RESTART_DET_R = crate::FieldReader; #[doc = "Field `clr_restart_det` writer - clr_restart_det"] -pub type CLR_RESTART_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RESTART_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] #[must_use] - pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { - CLR_RESTART_DET_W::new(self) + pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { + CLR_RESTART_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/clr_rx_done.rs b/jh7110-vf2-13b-pac/src/i2c0/clr_rx_done.rs index 02d83c5..7e14a3f 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/clr_rx_done.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/clr_rx_done.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_done` reader - clr_rx_done"] pub type CLR_RX_DONE_R = crate::FieldReader; #[doc = "Field `clr_rx_done` writer - clr_rx_done"] -pub type CLR_RX_DONE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_DONE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] #[must_use] - pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { - CLR_RX_DONE_W::new(self) + pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { + CLR_RX_DONE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/clr_rx_over.rs b/jh7110-vf2-13b-pac/src/i2c0/clr_rx_over.rs index 6d7ff4e..2302921 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/clr_rx_over.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/clr_rx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_over` reader - clr_rx_over"] pub type CLR_RX_OVER_R = crate::FieldReader; #[doc = "Field `clr_rx_over` writer - clr_rx_over"] -pub type CLR_RX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] #[must_use] - pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { - CLR_RX_OVER_W::new(self) + pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { + CLR_RX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/clr_rx_under.rs b/jh7110-vf2-13b-pac/src/i2c0/clr_rx_under.rs index 4a24f7c..35e15bd 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/clr_rx_under.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/clr_rx_under.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_under` reader - clr_rx_under"] pub type CLR_RX_UNDER_R = crate::FieldReader; #[doc = "Field `clr_rx_under` writer - clr_rx_under"] -pub type CLR_RX_UNDER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_UNDER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] #[must_use] - pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { - CLR_RX_UNDER_W::new(self) + pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { + CLR_RX_UNDER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/clr_start_det.rs b/jh7110-vf2-13b-pac/src/i2c0/clr_start_det.rs index cebc4bc..2314f65 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/clr_start_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/clr_start_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_start_det` reader - clr_start_det"] pub type CLR_START_DET_R = crate::FieldReader; #[doc = "Field `clr_start_det` writer - clr_start_det"] -pub type CLR_START_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_START_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] #[must_use] - pub fn clr_start_det(&mut self) -> CLR_START_DET_W { - CLR_START_DET_W::new(self) + pub fn clr_start_det(&mut self) -> CLR_START_DET_W { + CLR_START_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/clr_stop_det.rs b/jh7110-vf2-13b-pac/src/i2c0/clr_stop_det.rs index 44f39f3..49abcac 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/clr_stop_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/clr_stop_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_stop_det` reader - clr_stop_det"] pub type CLR_STOP_DET_R = crate::FieldReader; #[doc = "Field `clr_stop_det` writer - clr_stop_det"] -pub type CLR_STOP_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_STOP_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] #[must_use] - pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { - CLR_STOP_DET_W::new(self) + pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { + CLR_STOP_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/clr_tx_abrt.rs b/jh7110-vf2-13b-pac/src/i2c0/clr_tx_abrt.rs index 6ac441c..3bc0f6f 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/clr_tx_abrt.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/clr_tx_abrt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_abrt` reader - clr_tx_abrt"] pub type CLR_TX_ABRT_R = crate::FieldReader; #[doc = "Field `clr_tx_abrt` writer - clr_tx_abrt"] -pub type CLR_TX_ABRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_ABRT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] #[must_use] - pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { - CLR_TX_ABRT_W::new(self) + pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { + CLR_TX_ABRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/clr_tx_over.rs b/jh7110-vf2-13b-pac/src/i2c0/clr_tx_over.rs index 2b32b52..a5b6933 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/clr_tx_over.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/clr_tx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_over` reader - clr_tx_over"] pub type CLR_TX_OVER_R = crate::FieldReader; #[doc = "Field `clr_tx_over` writer - clr_tx_over"] -pub type CLR_TX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] #[must_use] - pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { - CLR_TX_OVER_W::new(self) + pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { + CLR_TX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/comp_param_1.rs b/jh7110-vf2-13b-pac/src/i2c0/comp_param_1.rs index 24a22e1..95c5002 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/comp_param_1.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/comp_param_1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/comp_type.rs b/jh7110-vf2-13b-pac/src/i2c0/comp_type.rs index ac916b5..1336c43 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/comp_type.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/comp_type.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/comp_version.rs b/jh7110-vf2-13b-pac/src/i2c0/comp_version.rs index 4be31fa..e8309c8 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/comp_version.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/comp_version.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/con.rs b/jh7110-vf2-13b-pac/src/i2c0/con.rs index 873c534..28aa865 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/con.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/con.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `master` reader - I2C Master Connection - 0: Slave, 1: Master"] pub type MASTER_R = crate::BitReader; #[doc = "Field `master` writer - I2C Master Connection - 0: Slave, 1: Master"] -pub type MASTER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `speed` reader - I2C Speed - 01: Standard, 10: Fast, 11: High"] pub type SPEED_R = crate::FieldReader; #[doc = "Field `speed` writer - I2C Speed - 01: Standard, 10: Fast, 11: High"] -pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `slave_10bitaddr` reader - I2C Slave 10-bit Address - 0: False, 1: True"] pub type SLAVE_10BITADDR_R = crate::BitReader; #[doc = "Field `slave_10bitaddr` writer - I2C Slave 10-bit Address - 0: False, 1: True"] -pub type SLAVE_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_10bitaddr` reader - I2C Master 10-bit Address - 0: False, 1: True"] pub type MASTER_10BITADDR_R = crate::BitReader; #[doc = "Field `master_10bitaddr` writer - I2C Master 10-bit Address - 0: False, 1: True"] -pub type MASTER_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_en` reader - I2C Restart Enable - 0: False, 1: True"] pub type RESTART_EN_R = crate::BitReader; #[doc = "Field `restart_en` writer - I2C Restart Enable - 0: False, 1: True"] -pub type RESTART_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_disable` reader - I2C Slave Disable - 0: False, 1: True"] pub type SLAVE_DISABLE_R = crate::BitReader; #[doc = "Field `slave_disable` writer - I2C Slave Disable - 0: False, 1: True"] -pub type SLAVE_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det_ifaddressed` reader - I2C Stop DET If Addressed - 0: False, 1: True"] pub type STOP_DET_IFADDRESSED_R = crate::BitReader; #[doc = "Field `stop_det_ifaddressed` writer - I2C Stop DET If Addressed - 0: False, 1: True"] -pub type STOP_DET_IFADDRESSED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty_ctrl` reader - I2C TX Empty Control - 0: False, 1: True"] pub type TX_EMPTY_CTRL_R = crate::BitReader; #[doc = "Field `tx_empty_ctrl` writer - I2C TX Empty Control - 0: False, 1: True"] -pub type TX_EMPTY_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_fifo_full_hld_ctrl` reader - I2C RX FIFO Full Hold Control - 0: False, 1: True"] pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; #[doc = "Field `rx_fifo_full_hld_ctrl` writer - I2C RX FIFO Full Hold Control - 0: False, 1: True"] -pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bus_clear_ctrl` reader - I2C Bus Clear Control - 0: False, 1: True"] pub type BUS_CLEAR_CTRL_R = crate::BitReader; #[doc = "Field `bus_clear_ctrl` writer - I2C Bus Clear Control - 0: False, 1: True"] -pub type BUS_CLEAR_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BUS_CLEAR_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] #[must_use] - pub fn master(&mut self) -> MASTER_W { - MASTER_W::new(self) + pub fn master(&mut self) -> MASTER_W { + MASTER_W::new(self, 0) } #[doc = "Bits 1:2 - I2C Speed - 01: Standard, 10: Fast, 11: High"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W { - SPEED_W::new(self) + pub fn speed(&mut self) -> SPEED_W { + SPEED_W::new(self, 1) } #[doc = "Bit 3 - I2C Slave 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { - SLAVE_10BITADDR_W::new(self) + pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { + SLAVE_10BITADDR_W::new(self, 3) } #[doc = "Bit 4 - I2C Master 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { - MASTER_10BITADDR_W::new(self) + pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { + MASTER_10BITADDR_W::new(self, 4) } #[doc = "Bit 5 - I2C Restart Enable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn restart_en(&mut self) -> RESTART_EN_W { - RESTART_EN_W::new(self) + pub fn restart_en(&mut self) -> RESTART_EN_W { + RESTART_EN_W::new(self, 5) } #[doc = "Bit 6 - I2C Slave Disable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { - SLAVE_DISABLE_W::new(self) + pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { + SLAVE_DISABLE_W::new(self, 6) } #[doc = "Bit 7 - I2C Stop DET If Addressed - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { - STOP_DET_IFADDRESSED_W::new(self) + pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { + STOP_DET_IFADDRESSED_W::new(self, 7) } #[doc = "Bit 8 - I2C TX Empty Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { - TX_EMPTY_CTRL_W::new(self) + pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { + TX_EMPTY_CTRL_W::new(self, 8) } #[doc = "Bit 9 - I2C RX FIFO Full Hold Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { - RX_FIFO_FULL_HLD_CTRL_W::new(self) + pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { + RX_FIFO_FULL_HLD_CTRL_W::new(self, 9) } #[doc = "Bit 11 - I2C Bus Clear Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { - BUS_CLEAR_CTRL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { + BUS_CLEAR_CTRL_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/data_cmd.rs b/jh7110-vf2-13b-pac/src/i2c0/data_cmd.rs index cf36408..2b320d4 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/data_cmd.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/data_cmd.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `dat` reader - Data Command Data Byte"] pub type DAT_R = crate::FieldReader; #[doc = "Field `dat` writer - Data Command Data Byte"] -pub type DAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `read` reader - Data Command READ Bit - 0: Write, 1: Read"] pub type READ_R = crate::BitReader; #[doc = "Field `read` writer - Data Command READ Bit - 0: Write, 1: Read"] -pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop` reader - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart` reader - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] pub type RESTART_R = crate::BitReader; #[doc = "Field `restart` writer - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] -pub type RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `first_data_byte` reader - Data Command First Data Byte - 0: False, 1: True"] pub type FIRST_DATA_BYTE_R = crate::BitReader; #[doc = "Field `first_data_byte` writer - Data Command First Data Byte - 0: False, 1: True"] -pub type FIRST_DATA_BYTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIRST_DATA_BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] #[must_use] - pub fn dat(&mut self) -> DAT_W { - DAT_W::new(self) + pub fn dat(&mut self) -> DAT_W { + DAT_W::new(self, 0) } #[doc = "Bit 8 - Data Command READ Bit - 0: Write, 1: Read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W { - READ_W::new(self) + pub fn read(&mut self) -> READ_W { + READ_W::new(self, 8) } #[doc = "Bit 9 - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 9) } #[doc = "Bit 10 - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] #[inline(always)] #[must_use] - pub fn restart(&mut self) -> RESTART_W { - RESTART_W::new(self) + pub fn restart(&mut self) -> RESTART_W { + RESTART_W::new(self, 10) } #[doc = "Bit 11 - Data Command First Data Byte - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { - FIRST_DATA_BYTE_W::new(self) + pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { + FIRST_DATA_BYTE_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/enable.rs b/jh7110-vf2-13b-pac/src/i2c0/enable.rs index c5ca9d7..3629f6b 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/enable.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/enable.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `abort` reader - abort"] pub type ABORT_R = crate::BitReader; #[doc = "Field `abort` writer - abort"] -pub type ABORT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 1 - abort"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 1 - abort"] #[inline(always)] #[must_use] - pub fn abort(&mut self) -> ABORT_W { - ABORT_W::new(self) + pub fn abort(&mut self) -> ABORT_W { + ABORT_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/enable_status.rs b/jh7110-vf2-13b-pac/src/i2c0/enable_status.rs index 2c102a6..8b9b7d3 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/enable_status.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/enable_status.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `activity` reader - activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tfe` reader - tfe"] pub type TFE_R = crate::BitReader; #[doc = "Field `tfe` writer - tfe"] -pub type TFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TFE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfne` reader - rfne"] pub type RFNE_R = crate::BitReader; #[doc = "Field `rfne` writer - rfne"] -pub type RFNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFNE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_activity` reader - master_activity"] pub type MASTER_ACTIVITY_R = crate::BitReader; #[doc = "Field `master_activity` writer - master_activity"] -pub type MASTER_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_activity` reader - slave_activity"] pub type SLAVE_ACTIVITY_R = crate::BitReader; #[doc = "Field `slave_activity` writer - slave_activity"] -pub type SLAVE_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - activity"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 0) } #[doc = "Bit 2 - tfe"] #[inline(always)] #[must_use] - pub fn tfe(&mut self) -> TFE_W { - TFE_W::new(self) + pub fn tfe(&mut self) -> TFE_W { + TFE_W::new(self, 2) } #[doc = "Bit 3 - rfne"] #[inline(always)] #[must_use] - pub fn rfne(&mut self) -> RFNE_W { - RFNE_W::new(self) + pub fn rfne(&mut self) -> RFNE_W { + RFNE_W::new(self, 3) } #[doc = "Bit 5 - master_activity"] #[inline(always)] #[must_use] - pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { - MASTER_ACTIVITY_W::new(self) + pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { + MASTER_ACTIVITY_W::new(self, 5) } #[doc = "Bit 6 - slave_activity"] #[inline(always)] #[must_use] - pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { - SLAVE_ACTIVITY_W::new(self) + pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { + SLAVE_ACTIVITY_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/fs_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c0/fs_scl_hcnt.rs index 9a9fd72..8a4f6d1 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/fs_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/fs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_hcnt` reader - fs_scl_hcnt"] pub type FS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_hcnt` writer - fs_scl_hcnt"] -pub type FS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { - FS_SCL_HCNT_W::new(self) + pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { + FS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/fs_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c0/fs_scl_lcnt.rs index 5e41cd1..4b4dd6b 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/fs_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/fs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_lcnt` reader - fs_scl_lcnt"] pub type FS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_lcnt` writer - fs_scl_lcnt"] -pub type FS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { - FS_SCL_LCNT_W::new(self) + pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { + FS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/hs_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c0/hs_scl_hcnt.rs index fba7f13..9b0a71c 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/hs_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/hs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_hcnt` reader - hs_scl_hcnt"] pub type HS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_hcnt` writer - hs_scl_hcnt"] -pub type HS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { - HS_SCL_HCNT_W::new(self) + pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { + HS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/hs_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c0/hs_scl_lcnt.rs index 9fca7a5..a715282 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/hs_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/hs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_lcnt` reader - hs_scl_lcnt"] pub type HS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_lcnt` writer - hs_scl_lcnt"] -pub type HS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { - HS_SCL_LCNT_W::new(self) + pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { + HS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/intr_mask.rs b/jh7110-vf2-13b-pac/src/i2c0/intr_mask.rs index 20a334f..769b629 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/intr_mask.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/intr_mask.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/intr_stat.rs b/jh7110-vf2-13b-pac/src/i2c0/intr_stat.rs index 2c2ba34..f376c26 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/intr_stat.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/raw_intr_stat.rs b/jh7110-vf2-13b-pac/src/i2c0/raw_intr_stat.rs index af97981..dd5e8e0 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/raw_intr_stat.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/raw_intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/rx_tl.rs b/jh7110-vf2-13b-pac/src/i2c0/rx_tl.rs index 1455a10..f3f39f4 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/rx_tl.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/rx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rx_tl` reader - rx_tl"] pub type RX_TL_R = crate::FieldReader; #[doc = "Field `rx_tl` writer - rx_tl"] -pub type RX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] #[must_use] - pub fn rx_tl(&mut self) -> RX_TL_W { - RX_TL_W::new(self) + pub fn rx_tl(&mut self) -> RX_TL_W { + RX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/rxflr.rs b/jh7110-vf2-13b-pac/src/i2c0/rxflr.rs index 910e254..4dccf5e 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/rxflr.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/rxflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rxflr` reader - rxflr"] pub type RXFLR_R = crate::FieldReader; #[doc = "Field `rxflr` writer - rxflr"] -pub type RXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] #[must_use] - pub fn rxflr(&mut self) -> RXFLR_W { - RXFLR_W::new(self) + pub fn rxflr(&mut self) -> RXFLR_W { + RXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/sar.rs b/jh7110-vf2-13b-pac/src/i2c0/sar.rs index d272e7a..1af6273 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/sar.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/sar.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Slave address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Slave address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Slave address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Slave address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; impl R { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Slave address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/sda_hold.rs b/jh7110-vf2-13b-pac/src/i2c0/sda_hold.rs index 82ceac5..d5d7512 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/sda_hold.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/sda_hold.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sda_hold` reader - sda_hold"] pub type SDA_HOLD_R = crate::FieldReader; #[doc = "Field `sda_hold` writer - sda_hold"] -pub type SDA_HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SDA_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] #[must_use] - pub fn sda_hold(&mut self) -> SDA_HOLD_W { - SDA_HOLD_W::new(self) + pub fn sda_hold(&mut self) -> SDA_HOLD_W { + SDA_HOLD_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/ss_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c0/ss_scl_hcnt.rs index 33736c7..77d7ea0 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/ss_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/ss_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_hcnt` reader - ss_scl_hcnt"] pub type SS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_hcnt` writer - ss_scl_hcnt"] -pub type SS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { - SS_SCL_HCNT_W::new(self) + pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { + SS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/ss_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c0/ss_scl_lcnt.rs index ce22b5d..8208747 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/ss_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/ss_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_lcnt` reader - ss_scl_lcnt"] pub type SS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_lcnt` writer - ss_scl_lcnt"] -pub type SS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { - SS_SCL_LCNT_W::new(self) + pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { + SS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/status.rs b/jh7110-vf2-13b-pac/src/i2c0/status.rs index 9489e49..1b7ab67 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/status.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/tar.rs b/jh7110-vf2-13b-pac/src/i2c0/tar.rs index 9fedc71..3044a8c 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/tar.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/tar.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Target address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Target address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Target address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Target address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; #[doc = "Field `mode` reader - Target addressing mode - 0: 7-bit, 1: 10-bit"] pub type MODE_R = crate::BitReader; #[doc = "Field `mode` writer - Target addressing mode - 0: 7-bit, 1: 10-bit"] -pub type MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Target address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } #[doc = "Bit 12 - Target addressing mode - 0: 7-bit, 1: 10-bit"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W { - MODE_W::new(self) + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 12) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/tx_abrt_source.rs b/jh7110-vf2-13b-pac/src/i2c0/tx_abrt_source.rs index 6f31813..c4fdf1a 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/tx_abrt_source.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/tx_abrt_source.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/tx_tl.rs b/jh7110-vf2-13b-pac/src/i2c0/tx_tl.rs index 84a1734..b0e6c64 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/tx_tl.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/tx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `tx_tl` reader - tx_tl"] pub type TX_TL_R = crate::FieldReader; #[doc = "Field `tx_tl` writer - tx_tl"] -pub type TX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] #[must_use] - pub fn tx_tl(&mut self) -> TX_TL_W { - TX_TL_W::new(self) + pub fn tx_tl(&mut self) -> TX_TL_W { + TX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c0/txflr.rs b/jh7110-vf2-13b-pac/src/i2c0/txflr.rs index b8e5fdd..5ca351d 100644 --- a/jh7110-vf2-13b-pac/src/i2c0/txflr.rs +++ b/jh7110-vf2-13b-pac/src/i2c0/txflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `txflr` reader - txflr"] pub type TXFLR_R = crate::FieldReader; #[doc = "Field `txflr` writer - txflr"] -pub type TXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - txflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - txflr"] #[inline(always)] #[must_use] - pub fn txflr(&mut self) -> TXFLR_W { - TXFLR_W::new(self) + pub fn txflr(&mut self) -> TXFLR_W { + TXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1.rs b/jh7110-vf2-13b-pac/src/i2c1.rs index d0fe76a..fdffe28 100644 --- a/jh7110-vf2-13b-pac/src/i2c1.rs +++ b/jh7110-vf2-13b-pac/src/i2c1.rs @@ -1,266 +1,416 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + con: CON, + tar: TAR, + sar: SAR, + _reserved3: [u8; 0x04], + data_cmd: DATA_CMD, + ss_scl_hcnt: SS_SCL_HCNT, + ss_scl_lcnt: SS_SCL_LCNT, + fs_scl_hcnt: FS_SCL_HCNT, + fs_scl_lcnt: FS_SCL_LCNT, + hs_scl_hcnt: HS_SCL_HCNT, + hs_scl_lcnt: HS_SCL_LCNT, + intr_stat: INTR_STAT, + intr_mask: INTR_MASK, + raw_intr_stat: RAW_INTR_STAT, + rx_tl: RX_TL, + tx_tl: TX_TL, + clr_intr: CLR_INTR, + clr_rx_under: CLR_RX_UNDER, + clr_rx_over: CLR_RX_OVER, + clr_tx_over: CLR_TX_OVER, + clr_rd_req: CLR_RD_REQ, + clr_tx_abrt: CLR_TX_ABRT, + clr_rx_done: CLR_RX_DONE, + clr_activity: CLR_ACTIVITY, + clr_stop_det: CLR_STOP_DET, + clr_start_det: CLR_START_DET, + clr_gen_call: CLR_GEN_CALL, + enable: ENABLE, + status: STATUS, + txflr: TXFLR, + rxflr: RXFLR, + sda_hold: SDA_HOLD, + tx_abrt_source: TX_ABRT_SOURCE, + _reserved32: [u8; 0x18], + enable_status: ENABLE_STATUS, + _reserved33: [u8; 0x08], + clr_restart_det: CLR_RESTART_DET, + _reserved34: [u8; 0x48], + comp_param_1: COMP_PARAM_1, + comp_version: COMP_VERSION, + comp_type: COMP_TYPE, +} +impl RegisterBlock { #[doc = "0x00 - DesignWare I2C CON"] - pub con: CON, + #[inline(always)] + pub const fn con(&self) -> &CON { + &self.con + } #[doc = "0x04 - DesignWare I2C TAR"] - pub tar: TAR, + #[inline(always)] + pub const fn tar(&self) -> &TAR { + &self.tar + } #[doc = "0x08 - DesignWare I2C SAR"] - pub sar: SAR, - _reserved3: [u8; 0x04], + #[inline(always)] + pub const fn sar(&self) -> &SAR { + &self.sar + } #[doc = "0x10 - DesignWare I2C Data Command"] - pub data_cmd: DATA_CMD, + #[inline(always)] + pub const fn data_cmd(&self) -> &DATA_CMD { + &self.data_cmd + } #[doc = "0x14 - DesignWare I2C SS SCL HCNT"] - pub ss_scl_hcnt: SS_SCL_HCNT, + #[inline(always)] + pub const fn ss_scl_hcnt(&self) -> &SS_SCL_HCNT { + &self.ss_scl_hcnt + } #[doc = "0x18 - DesignWare I2C SS SCL LCNT"] - pub ss_scl_lcnt: SS_SCL_LCNT, + #[inline(always)] + pub const fn ss_scl_lcnt(&self) -> &SS_SCL_LCNT { + &self.ss_scl_lcnt + } #[doc = "0x1c - DesignWare I2C FS SCL HCNT"] - pub fs_scl_hcnt: FS_SCL_HCNT, + #[inline(always)] + pub const fn fs_scl_hcnt(&self) -> &FS_SCL_HCNT { + &self.fs_scl_hcnt + } #[doc = "0x20 - DesignWare I2C FS SCL LCNT"] - pub fs_scl_lcnt: FS_SCL_LCNT, + #[inline(always)] + pub const fn fs_scl_lcnt(&self) -> &FS_SCL_LCNT { + &self.fs_scl_lcnt + } #[doc = "0x24 - DesignWare I2C HS SCL HCNT"] - pub hs_scl_hcnt: HS_SCL_HCNT, + #[inline(always)] + pub const fn hs_scl_hcnt(&self) -> &HS_SCL_HCNT { + &self.hs_scl_hcnt + } #[doc = "0x28 - DesignWare I2C HS SCL LCNT"] - pub hs_scl_lcnt: HS_SCL_LCNT, + #[inline(always)] + pub const fn hs_scl_lcnt(&self) -> &HS_SCL_LCNT { + &self.hs_scl_lcnt + } #[doc = "0x2c - DesignWare I2C Interrupt Status"] - pub intr_stat: INTR_STAT, + #[inline(always)] + pub const fn intr_stat(&self) -> &INTR_STAT { + &self.intr_stat + } #[doc = "0x30 - DesignWare I2C Interrupt Mask"] - pub intr_mask: INTR_MASK, + #[inline(always)] + pub const fn intr_mask(&self) -> &INTR_MASK { + &self.intr_mask + } #[doc = "0x34 - DesignWare I2C Raw Interrupt Status"] - pub raw_intr_stat: RAW_INTR_STAT, + #[inline(always)] + pub const fn raw_intr_stat(&self) -> &RAW_INTR_STAT { + &self.raw_intr_stat + } #[doc = "0x38 - DesignWare I2C RX TL"] - pub rx_tl: RX_TL, + #[inline(always)] + pub const fn rx_tl(&self) -> &RX_TL { + &self.rx_tl + } #[doc = "0x3c - DesignWare I2C TX TL"] - pub tx_tl: TX_TL, + #[inline(always)] + pub const fn tx_tl(&self) -> &TX_TL { + &self.tx_tl + } #[doc = "0x40 - DesignWare I2C Clear Interrrupt"] - pub clr_intr: CLR_INTR, + #[inline(always)] + pub const fn clr_intr(&self) -> &CLR_INTR { + &self.clr_intr + } #[doc = "0x44 - DesignWare I2C Clear RX Underrun"] - pub clr_rx_under: CLR_RX_UNDER, + #[inline(always)] + pub const fn clr_rx_under(&self) -> &CLR_RX_UNDER { + &self.clr_rx_under + } #[doc = "0x48 - DesignWare I2C Clear RX Overrun"] - pub clr_rx_over: CLR_RX_OVER, + #[inline(always)] + pub const fn clr_rx_over(&self) -> &CLR_RX_OVER { + &self.clr_rx_over + } #[doc = "0x4c - DesignWare I2C Clear TX Overrun"] - pub clr_tx_over: CLR_TX_OVER, + #[inline(always)] + pub const fn clr_tx_over(&self) -> &CLR_TX_OVER { + &self.clr_tx_over + } #[doc = "0x50 - DesignWare I2C Clear Read Request"] - pub clr_rd_req: CLR_RD_REQ, + #[inline(always)] + pub const fn clr_rd_req(&self) -> &CLR_RD_REQ { + &self.clr_rd_req + } #[doc = "0x54 - DesignWare I2C Clear TX Abort"] - pub clr_tx_abrt: CLR_TX_ABRT, + #[inline(always)] + pub const fn clr_tx_abrt(&self) -> &CLR_TX_ABRT { + &self.clr_tx_abrt + } #[doc = "0x58 - DesignWare I2C Clear RX Done"] - pub clr_rx_done: CLR_RX_DONE, + #[inline(always)] + pub const fn clr_rx_done(&self) -> &CLR_RX_DONE { + &self.clr_rx_done + } #[doc = "0x5c - DesignWare I2C Clear Activity"] - pub clr_activity: CLR_ACTIVITY, + #[inline(always)] + pub const fn clr_activity(&self) -> &CLR_ACTIVITY { + &self.clr_activity + } #[doc = "0x60 - DesignWare I2C Clear Stop DET"] - pub clr_stop_det: CLR_STOP_DET, + #[inline(always)] + pub const fn clr_stop_det(&self) -> &CLR_STOP_DET { + &self.clr_stop_det + } #[doc = "0x64 - DesignWare I2C Clear Start DET"] - pub clr_start_det: CLR_START_DET, + #[inline(always)] + pub const fn clr_start_det(&self) -> &CLR_START_DET { + &self.clr_start_det + } #[doc = "0x68 - DesignWare I2C Clear General Call"] - pub clr_gen_call: CLR_GEN_CALL, + #[inline(always)] + pub const fn clr_gen_call(&self) -> &CLR_GEN_CALL { + &self.clr_gen_call + } #[doc = "0x6c - DesignWare I2C Enable"] - pub enable: ENABLE, + #[inline(always)] + pub const fn enable(&self) -> &ENABLE { + &self.enable + } #[doc = "0x70 - DesignWare I2C Status"] - pub status: STATUS, + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } #[doc = "0x74 - DesignWare I2C TX Failure"] - pub txflr: TXFLR, + #[inline(always)] + pub const fn txflr(&self) -> &TXFLR { + &self.txflr + } #[doc = "0x78 - DesignWare I2C RX Failure"] - pub rxflr: RXFLR, + #[inline(always)] + pub const fn rxflr(&self) -> &RXFLR { + &self.rxflr + } #[doc = "0x7c - DesignWare I2C SDA Hold"] - pub sda_hold: SDA_HOLD, + #[inline(always)] + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold + } #[doc = "0x80 - DesignWare I2C TX Abort Source"] - pub tx_abrt_source: TX_ABRT_SOURCE, - _reserved32: [u8; 0x18], + #[inline(always)] + pub const fn tx_abrt_source(&self) -> &TX_ABRT_SOURCE { + &self.tx_abrt_source + } #[doc = "0x9c - DesignWare I2C Enable Status"] - pub enable_status: ENABLE_STATUS, - _reserved33: [u8; 0x08], + #[inline(always)] + pub const fn enable_status(&self) -> &ENABLE_STATUS { + &self.enable_status + } #[doc = "0xa8 - DesignWare I2C Clear Restart DET"] - pub clr_restart_det: CLR_RESTART_DET, - _reserved34: [u8; 0x48], + #[inline(always)] + pub const fn clr_restart_det(&self) -> &CLR_RESTART_DET { + &self.clr_restart_det + } #[doc = "0xf4 - DesignWare I2C Compatibility Parameter 1"] - pub comp_param_1: COMP_PARAM_1, + #[inline(always)] + pub const fn comp_param_1(&self) -> &COMP_PARAM_1 { + &self.comp_param_1 + } #[doc = "0xf8 - DesignWare I2C Compatibility Version"] - pub comp_version: COMP_VERSION, + #[inline(always)] + pub const fn comp_version(&self) -> &COMP_VERSION { + &self.comp_version + } #[doc = "0xfc - DesignWare I2C Compatibility Type"] - pub comp_type: COMP_TYPE, + #[inline(always)] + pub const fn comp_type(&self) -> &COMP_TYPE { + &self.comp_type + } } -#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`con`] +#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@con`] module"] pub type CON = crate::Reg; #[doc = "DesignWare I2C CON"] pub mod con; -#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tar`] +#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar`] module"] pub type TAR = crate::Reg; #[doc = "DesignWare I2C TAR"] pub mod tar; -#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sar`] +#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`] module"] pub type SAR = crate::Reg; #[doc = "DesignWare I2C SAR"] pub mod sar; -#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`data_cmd`] +#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_cmd`] module"] pub type DATA_CMD = crate::Reg; #[doc = "DesignWare I2C Data Command"] pub mod data_cmd; -#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_hcnt`] +#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_hcnt`] module"] pub type SS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL HCNT"] pub mod ss_scl_hcnt; -#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_lcnt`] +#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_lcnt`] module"] pub type SS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL LCNT"] pub mod ss_scl_lcnt; -#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_hcnt`] +#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_hcnt`] module"] pub type FS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL HCNT"] pub mod fs_scl_hcnt; -#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_lcnt`] +#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_lcnt`] module"] pub type FS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL LCNT"] pub mod fs_scl_lcnt; -#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_hcnt`] +#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_hcnt`] module"] pub type HS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL HCNT"] pub mod hs_scl_hcnt; -#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_lcnt`] +#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_lcnt`] module"] pub type HS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL LCNT"] pub mod hs_scl_lcnt; -#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_stat`] +#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"] pub type INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Interrupt Status"] pub mod intr_stat; -#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_mask`] +#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mask`] module"] pub type INTR_MASK = crate::Reg; #[doc = "DesignWare I2C Interrupt Mask"] pub mod intr_mask; -#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`raw_intr_stat`] +#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"] pub type RAW_INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Raw Interrupt Status"] pub mod raw_intr_stat; -#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rx_tl`] +#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tl`] module"] pub type RX_TL = crate::Reg; #[doc = "DesignWare I2C RX TL"] pub mod rx_tl; -#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_tl`] +#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_tl`] module"] pub type TX_TL = crate::Reg; #[doc = "DesignWare I2C TX TL"] pub mod tx_tl; -#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_intr`] +#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_intr`] module"] pub type CLR_INTR = crate::Reg; #[doc = "DesignWare I2C Clear Interrrupt"] pub mod clr_intr; -#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_under`] +#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_under`] module"] pub type CLR_RX_UNDER = crate::Reg; #[doc = "DesignWare I2C Clear RX Underrun"] pub mod clr_rx_under; -#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_over`] +#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_over`] module"] pub type CLR_RX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear RX Overrun"] pub mod clr_rx_over; -#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_over`] +#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_over`] module"] pub type CLR_TX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear TX Overrun"] pub mod clr_tx_over; -#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rd_req`] +#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rd_req`] module"] pub type CLR_RD_REQ = crate::Reg; #[doc = "DesignWare I2C Clear Read Request"] pub mod clr_rd_req; -#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_abrt`] +#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_abrt`] module"] pub type CLR_TX_ABRT = crate::Reg; #[doc = "DesignWare I2C Clear TX Abort"] pub mod clr_tx_abrt; -#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_done`] +#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_done`] module"] pub type CLR_RX_DONE = crate::Reg; #[doc = "DesignWare I2C Clear RX Done"] pub mod clr_rx_done; -#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_activity`] +#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_activity`] module"] pub type CLR_ACTIVITY = crate::Reg; #[doc = "DesignWare I2C Clear Activity"] pub mod clr_activity; -#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_stop_det`] +#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_stop_det`] module"] pub type CLR_STOP_DET = crate::Reg; #[doc = "DesignWare I2C Clear Stop DET"] pub mod clr_stop_det; -#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_start_det`] +#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_start_det`] module"] pub type CLR_START_DET = crate::Reg; #[doc = "DesignWare I2C Clear Start DET"] pub mod clr_start_det; -#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_gen_call`] +#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_gen_call`] module"] pub type CLR_GEN_CALL = crate::Reg; #[doc = "DesignWare I2C Clear General Call"] pub mod clr_gen_call; -#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable`] +#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] pub type ENABLE = crate::Reg; #[doc = "DesignWare I2C Enable"] pub mod enable; -#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`status`] +#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] pub type STATUS = crate::Reg; #[doc = "DesignWare I2C Status"] pub mod status; -#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txflr`] +#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txflr`] module"] pub type TXFLR = crate::Reg; #[doc = "DesignWare I2C TX Failure"] pub mod txflr; -#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxflr`] +#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxflr`] module"] pub type RXFLR = crate::Reg; #[doc = "DesignWare I2C RX Failure"] pub mod rxflr; -#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sda_hold`] +#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] pub type SDA_HOLD = crate::Reg; #[doc = "DesignWare I2C SDA Hold"] pub mod sda_hold; -#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_abrt_source`] +#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_abrt_source`] module"] pub type TX_ABRT_SOURCE = crate::Reg; #[doc = "DesignWare I2C TX Abort Source"] pub mod tx_abrt_source; -#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_status`] +#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_status`] module"] pub type ENABLE_STATUS = crate::Reg; #[doc = "DesignWare I2C Enable Status"] pub mod enable_status; -#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_restart_det`] +#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_restart_det`] module"] pub type CLR_RESTART_DET = crate::Reg; #[doc = "DesignWare I2C Clear Restart DET"] pub mod clr_restart_det; -#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_param_1`] +#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_param_1`] module"] pub type COMP_PARAM_1 = crate::Reg; #[doc = "DesignWare I2C Compatibility Parameter 1"] pub mod comp_param_1; -#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_version`] +#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_version`] module"] pub type COMP_VERSION = crate::Reg; #[doc = "DesignWare I2C Compatibility Version"] pub mod comp_version; -#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_type`] +#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_type`] module"] pub type COMP_TYPE = crate::Reg; #[doc = "DesignWare I2C Compatibility Type"] diff --git a/jh7110-vf2-13b-pac/src/i2c1/clr_activity.rs b/jh7110-vf2-13b-pac/src/i2c1/clr_activity.rs index d26bb80..1ee2297 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/clr_activity.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/clr_activity.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_activity` reader - clr_activity"] pub type CLR_ACTIVITY_R = crate::FieldReader; #[doc = "Field `clr_activity` writer - clr_activity"] -pub type CLR_ACTIVITY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_ACTIVITY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] #[must_use] - pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { - CLR_ACTIVITY_W::new(self) + pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { + CLR_ACTIVITY_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/clr_gen_call.rs b/jh7110-vf2-13b-pac/src/i2c1/clr_gen_call.rs index a9ea5af..4a7c5ba 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/clr_gen_call.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/clr_gen_call.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_gen_call` reader - clr_gen_call"] pub type CLR_GEN_CALL_R = crate::FieldReader; #[doc = "Field `clr_gen_call` writer - clr_gen_call"] -pub type CLR_GEN_CALL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_GEN_CALL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] #[must_use] - pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { - CLR_GEN_CALL_W::new(self) + pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { + CLR_GEN_CALL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/clr_intr.rs b/jh7110-vf2-13b-pac/src/i2c1/clr_intr.rs index a7daf57..cf57b09 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/clr_intr.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/clr_intr.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/clr_rd_req.rs b/jh7110-vf2-13b-pac/src/i2c1/clr_rd_req.rs index e275da1..4beae9d 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/clr_rd_req.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/clr_rd_req.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rd_req` reader - clr_rd_req"] pub type CLR_RD_REQ_R = crate::FieldReader; #[doc = "Field `clr_rd_req` writer - clr_rd_req"] -pub type CLR_RD_REQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RD_REQ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] #[must_use] - pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { - CLR_RD_REQ_W::new(self) + pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { + CLR_RD_REQ_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/clr_restart_det.rs b/jh7110-vf2-13b-pac/src/i2c1/clr_restart_det.rs index 5be7f5d..88d193c 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/clr_restart_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/clr_restart_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_restart_det` reader - clr_restart_det"] pub type CLR_RESTART_DET_R = crate::FieldReader; #[doc = "Field `clr_restart_det` writer - clr_restart_det"] -pub type CLR_RESTART_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RESTART_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] #[must_use] - pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { - CLR_RESTART_DET_W::new(self) + pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { + CLR_RESTART_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/clr_rx_done.rs b/jh7110-vf2-13b-pac/src/i2c1/clr_rx_done.rs index 02d83c5..7e14a3f 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/clr_rx_done.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/clr_rx_done.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_done` reader - clr_rx_done"] pub type CLR_RX_DONE_R = crate::FieldReader; #[doc = "Field `clr_rx_done` writer - clr_rx_done"] -pub type CLR_RX_DONE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_DONE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] #[must_use] - pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { - CLR_RX_DONE_W::new(self) + pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { + CLR_RX_DONE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/clr_rx_over.rs b/jh7110-vf2-13b-pac/src/i2c1/clr_rx_over.rs index 6d7ff4e..2302921 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/clr_rx_over.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/clr_rx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_over` reader - clr_rx_over"] pub type CLR_RX_OVER_R = crate::FieldReader; #[doc = "Field `clr_rx_over` writer - clr_rx_over"] -pub type CLR_RX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] #[must_use] - pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { - CLR_RX_OVER_W::new(self) + pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { + CLR_RX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/clr_rx_under.rs b/jh7110-vf2-13b-pac/src/i2c1/clr_rx_under.rs index 4a24f7c..35e15bd 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/clr_rx_under.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/clr_rx_under.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_under` reader - clr_rx_under"] pub type CLR_RX_UNDER_R = crate::FieldReader; #[doc = "Field `clr_rx_under` writer - clr_rx_under"] -pub type CLR_RX_UNDER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_UNDER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] #[must_use] - pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { - CLR_RX_UNDER_W::new(self) + pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { + CLR_RX_UNDER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/clr_start_det.rs b/jh7110-vf2-13b-pac/src/i2c1/clr_start_det.rs index cebc4bc..2314f65 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/clr_start_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/clr_start_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_start_det` reader - clr_start_det"] pub type CLR_START_DET_R = crate::FieldReader; #[doc = "Field `clr_start_det` writer - clr_start_det"] -pub type CLR_START_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_START_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] #[must_use] - pub fn clr_start_det(&mut self) -> CLR_START_DET_W { - CLR_START_DET_W::new(self) + pub fn clr_start_det(&mut self) -> CLR_START_DET_W { + CLR_START_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/clr_stop_det.rs b/jh7110-vf2-13b-pac/src/i2c1/clr_stop_det.rs index 44f39f3..49abcac 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/clr_stop_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/clr_stop_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_stop_det` reader - clr_stop_det"] pub type CLR_STOP_DET_R = crate::FieldReader; #[doc = "Field `clr_stop_det` writer - clr_stop_det"] -pub type CLR_STOP_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_STOP_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] #[must_use] - pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { - CLR_STOP_DET_W::new(self) + pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { + CLR_STOP_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/clr_tx_abrt.rs b/jh7110-vf2-13b-pac/src/i2c1/clr_tx_abrt.rs index 6ac441c..3bc0f6f 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/clr_tx_abrt.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/clr_tx_abrt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_abrt` reader - clr_tx_abrt"] pub type CLR_TX_ABRT_R = crate::FieldReader; #[doc = "Field `clr_tx_abrt` writer - clr_tx_abrt"] -pub type CLR_TX_ABRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_ABRT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] #[must_use] - pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { - CLR_TX_ABRT_W::new(self) + pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { + CLR_TX_ABRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/clr_tx_over.rs b/jh7110-vf2-13b-pac/src/i2c1/clr_tx_over.rs index 2b32b52..a5b6933 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/clr_tx_over.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/clr_tx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_over` reader - clr_tx_over"] pub type CLR_TX_OVER_R = crate::FieldReader; #[doc = "Field `clr_tx_over` writer - clr_tx_over"] -pub type CLR_TX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] #[must_use] - pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { - CLR_TX_OVER_W::new(self) + pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { + CLR_TX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/comp_param_1.rs b/jh7110-vf2-13b-pac/src/i2c1/comp_param_1.rs index 24a22e1..95c5002 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/comp_param_1.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/comp_param_1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/comp_type.rs b/jh7110-vf2-13b-pac/src/i2c1/comp_type.rs index ac916b5..1336c43 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/comp_type.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/comp_type.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/comp_version.rs b/jh7110-vf2-13b-pac/src/i2c1/comp_version.rs index 4be31fa..e8309c8 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/comp_version.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/comp_version.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/con.rs b/jh7110-vf2-13b-pac/src/i2c1/con.rs index 873c534..28aa865 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/con.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/con.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `master` reader - I2C Master Connection - 0: Slave, 1: Master"] pub type MASTER_R = crate::BitReader; #[doc = "Field `master` writer - I2C Master Connection - 0: Slave, 1: Master"] -pub type MASTER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `speed` reader - I2C Speed - 01: Standard, 10: Fast, 11: High"] pub type SPEED_R = crate::FieldReader; #[doc = "Field `speed` writer - I2C Speed - 01: Standard, 10: Fast, 11: High"] -pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `slave_10bitaddr` reader - I2C Slave 10-bit Address - 0: False, 1: True"] pub type SLAVE_10BITADDR_R = crate::BitReader; #[doc = "Field `slave_10bitaddr` writer - I2C Slave 10-bit Address - 0: False, 1: True"] -pub type SLAVE_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_10bitaddr` reader - I2C Master 10-bit Address - 0: False, 1: True"] pub type MASTER_10BITADDR_R = crate::BitReader; #[doc = "Field `master_10bitaddr` writer - I2C Master 10-bit Address - 0: False, 1: True"] -pub type MASTER_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_en` reader - I2C Restart Enable - 0: False, 1: True"] pub type RESTART_EN_R = crate::BitReader; #[doc = "Field `restart_en` writer - I2C Restart Enable - 0: False, 1: True"] -pub type RESTART_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_disable` reader - I2C Slave Disable - 0: False, 1: True"] pub type SLAVE_DISABLE_R = crate::BitReader; #[doc = "Field `slave_disable` writer - I2C Slave Disable - 0: False, 1: True"] -pub type SLAVE_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det_ifaddressed` reader - I2C Stop DET If Addressed - 0: False, 1: True"] pub type STOP_DET_IFADDRESSED_R = crate::BitReader; #[doc = "Field `stop_det_ifaddressed` writer - I2C Stop DET If Addressed - 0: False, 1: True"] -pub type STOP_DET_IFADDRESSED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty_ctrl` reader - I2C TX Empty Control - 0: False, 1: True"] pub type TX_EMPTY_CTRL_R = crate::BitReader; #[doc = "Field `tx_empty_ctrl` writer - I2C TX Empty Control - 0: False, 1: True"] -pub type TX_EMPTY_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_fifo_full_hld_ctrl` reader - I2C RX FIFO Full Hold Control - 0: False, 1: True"] pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; #[doc = "Field `rx_fifo_full_hld_ctrl` writer - I2C RX FIFO Full Hold Control - 0: False, 1: True"] -pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bus_clear_ctrl` reader - I2C Bus Clear Control - 0: False, 1: True"] pub type BUS_CLEAR_CTRL_R = crate::BitReader; #[doc = "Field `bus_clear_ctrl` writer - I2C Bus Clear Control - 0: False, 1: True"] -pub type BUS_CLEAR_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BUS_CLEAR_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] #[must_use] - pub fn master(&mut self) -> MASTER_W { - MASTER_W::new(self) + pub fn master(&mut self) -> MASTER_W { + MASTER_W::new(self, 0) } #[doc = "Bits 1:2 - I2C Speed - 01: Standard, 10: Fast, 11: High"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W { - SPEED_W::new(self) + pub fn speed(&mut self) -> SPEED_W { + SPEED_W::new(self, 1) } #[doc = "Bit 3 - I2C Slave 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { - SLAVE_10BITADDR_W::new(self) + pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { + SLAVE_10BITADDR_W::new(self, 3) } #[doc = "Bit 4 - I2C Master 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { - MASTER_10BITADDR_W::new(self) + pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { + MASTER_10BITADDR_W::new(self, 4) } #[doc = "Bit 5 - I2C Restart Enable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn restart_en(&mut self) -> RESTART_EN_W { - RESTART_EN_W::new(self) + pub fn restart_en(&mut self) -> RESTART_EN_W { + RESTART_EN_W::new(self, 5) } #[doc = "Bit 6 - I2C Slave Disable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { - SLAVE_DISABLE_W::new(self) + pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { + SLAVE_DISABLE_W::new(self, 6) } #[doc = "Bit 7 - I2C Stop DET If Addressed - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { - STOP_DET_IFADDRESSED_W::new(self) + pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { + STOP_DET_IFADDRESSED_W::new(self, 7) } #[doc = "Bit 8 - I2C TX Empty Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { - TX_EMPTY_CTRL_W::new(self) + pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { + TX_EMPTY_CTRL_W::new(self, 8) } #[doc = "Bit 9 - I2C RX FIFO Full Hold Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { - RX_FIFO_FULL_HLD_CTRL_W::new(self) + pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { + RX_FIFO_FULL_HLD_CTRL_W::new(self, 9) } #[doc = "Bit 11 - I2C Bus Clear Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { - BUS_CLEAR_CTRL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { + BUS_CLEAR_CTRL_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/data_cmd.rs b/jh7110-vf2-13b-pac/src/i2c1/data_cmd.rs index cf36408..2b320d4 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/data_cmd.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/data_cmd.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `dat` reader - Data Command Data Byte"] pub type DAT_R = crate::FieldReader; #[doc = "Field `dat` writer - Data Command Data Byte"] -pub type DAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `read` reader - Data Command READ Bit - 0: Write, 1: Read"] pub type READ_R = crate::BitReader; #[doc = "Field `read` writer - Data Command READ Bit - 0: Write, 1: Read"] -pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop` reader - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart` reader - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] pub type RESTART_R = crate::BitReader; #[doc = "Field `restart` writer - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] -pub type RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `first_data_byte` reader - Data Command First Data Byte - 0: False, 1: True"] pub type FIRST_DATA_BYTE_R = crate::BitReader; #[doc = "Field `first_data_byte` writer - Data Command First Data Byte - 0: False, 1: True"] -pub type FIRST_DATA_BYTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIRST_DATA_BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] #[must_use] - pub fn dat(&mut self) -> DAT_W { - DAT_W::new(self) + pub fn dat(&mut self) -> DAT_W { + DAT_W::new(self, 0) } #[doc = "Bit 8 - Data Command READ Bit - 0: Write, 1: Read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W { - READ_W::new(self) + pub fn read(&mut self) -> READ_W { + READ_W::new(self, 8) } #[doc = "Bit 9 - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 9) } #[doc = "Bit 10 - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] #[inline(always)] #[must_use] - pub fn restart(&mut self) -> RESTART_W { - RESTART_W::new(self) + pub fn restart(&mut self) -> RESTART_W { + RESTART_W::new(self, 10) } #[doc = "Bit 11 - Data Command First Data Byte - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { - FIRST_DATA_BYTE_W::new(self) + pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { + FIRST_DATA_BYTE_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/enable.rs b/jh7110-vf2-13b-pac/src/i2c1/enable.rs index c5ca9d7..3629f6b 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/enable.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/enable.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `abort` reader - abort"] pub type ABORT_R = crate::BitReader; #[doc = "Field `abort` writer - abort"] -pub type ABORT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 1 - abort"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 1 - abort"] #[inline(always)] #[must_use] - pub fn abort(&mut self) -> ABORT_W { - ABORT_W::new(self) + pub fn abort(&mut self) -> ABORT_W { + ABORT_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/enable_status.rs b/jh7110-vf2-13b-pac/src/i2c1/enable_status.rs index 2c102a6..8b9b7d3 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/enable_status.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/enable_status.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `activity` reader - activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tfe` reader - tfe"] pub type TFE_R = crate::BitReader; #[doc = "Field `tfe` writer - tfe"] -pub type TFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TFE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfne` reader - rfne"] pub type RFNE_R = crate::BitReader; #[doc = "Field `rfne` writer - rfne"] -pub type RFNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFNE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_activity` reader - master_activity"] pub type MASTER_ACTIVITY_R = crate::BitReader; #[doc = "Field `master_activity` writer - master_activity"] -pub type MASTER_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_activity` reader - slave_activity"] pub type SLAVE_ACTIVITY_R = crate::BitReader; #[doc = "Field `slave_activity` writer - slave_activity"] -pub type SLAVE_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - activity"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 0) } #[doc = "Bit 2 - tfe"] #[inline(always)] #[must_use] - pub fn tfe(&mut self) -> TFE_W { - TFE_W::new(self) + pub fn tfe(&mut self) -> TFE_W { + TFE_W::new(self, 2) } #[doc = "Bit 3 - rfne"] #[inline(always)] #[must_use] - pub fn rfne(&mut self) -> RFNE_W { - RFNE_W::new(self) + pub fn rfne(&mut self) -> RFNE_W { + RFNE_W::new(self, 3) } #[doc = "Bit 5 - master_activity"] #[inline(always)] #[must_use] - pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { - MASTER_ACTIVITY_W::new(self) + pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { + MASTER_ACTIVITY_W::new(self, 5) } #[doc = "Bit 6 - slave_activity"] #[inline(always)] #[must_use] - pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { - SLAVE_ACTIVITY_W::new(self) + pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { + SLAVE_ACTIVITY_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/fs_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c1/fs_scl_hcnt.rs index 9a9fd72..8a4f6d1 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/fs_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/fs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_hcnt` reader - fs_scl_hcnt"] pub type FS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_hcnt` writer - fs_scl_hcnt"] -pub type FS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { - FS_SCL_HCNT_W::new(self) + pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { + FS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/fs_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c1/fs_scl_lcnt.rs index 5e41cd1..4b4dd6b 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/fs_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/fs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_lcnt` reader - fs_scl_lcnt"] pub type FS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_lcnt` writer - fs_scl_lcnt"] -pub type FS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { - FS_SCL_LCNT_W::new(self) + pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { + FS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/hs_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c1/hs_scl_hcnt.rs index fba7f13..9b0a71c 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/hs_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/hs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_hcnt` reader - hs_scl_hcnt"] pub type HS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_hcnt` writer - hs_scl_hcnt"] -pub type HS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { - HS_SCL_HCNT_W::new(self) + pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { + HS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/hs_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c1/hs_scl_lcnt.rs index 9fca7a5..a715282 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/hs_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/hs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_lcnt` reader - hs_scl_lcnt"] pub type HS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_lcnt` writer - hs_scl_lcnt"] -pub type HS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { - HS_SCL_LCNT_W::new(self) + pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { + HS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/intr_mask.rs b/jh7110-vf2-13b-pac/src/i2c1/intr_mask.rs index 20a334f..769b629 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/intr_mask.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/intr_mask.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/intr_stat.rs b/jh7110-vf2-13b-pac/src/i2c1/intr_stat.rs index 2c2ba34..f376c26 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/intr_stat.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/raw_intr_stat.rs b/jh7110-vf2-13b-pac/src/i2c1/raw_intr_stat.rs index af97981..dd5e8e0 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/raw_intr_stat.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/raw_intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/rx_tl.rs b/jh7110-vf2-13b-pac/src/i2c1/rx_tl.rs index 1455a10..f3f39f4 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/rx_tl.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/rx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rx_tl` reader - rx_tl"] pub type RX_TL_R = crate::FieldReader; #[doc = "Field `rx_tl` writer - rx_tl"] -pub type RX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] #[must_use] - pub fn rx_tl(&mut self) -> RX_TL_W { - RX_TL_W::new(self) + pub fn rx_tl(&mut self) -> RX_TL_W { + RX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/rxflr.rs b/jh7110-vf2-13b-pac/src/i2c1/rxflr.rs index 910e254..4dccf5e 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/rxflr.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/rxflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rxflr` reader - rxflr"] pub type RXFLR_R = crate::FieldReader; #[doc = "Field `rxflr` writer - rxflr"] -pub type RXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] #[must_use] - pub fn rxflr(&mut self) -> RXFLR_W { - RXFLR_W::new(self) + pub fn rxflr(&mut self) -> RXFLR_W { + RXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/sar.rs b/jh7110-vf2-13b-pac/src/i2c1/sar.rs index d272e7a..1af6273 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/sar.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/sar.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Slave address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Slave address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Slave address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Slave address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; impl R { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Slave address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/sda_hold.rs b/jh7110-vf2-13b-pac/src/i2c1/sda_hold.rs index 82ceac5..d5d7512 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/sda_hold.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/sda_hold.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sda_hold` reader - sda_hold"] pub type SDA_HOLD_R = crate::FieldReader; #[doc = "Field `sda_hold` writer - sda_hold"] -pub type SDA_HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SDA_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] #[must_use] - pub fn sda_hold(&mut self) -> SDA_HOLD_W { - SDA_HOLD_W::new(self) + pub fn sda_hold(&mut self) -> SDA_HOLD_W { + SDA_HOLD_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/ss_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c1/ss_scl_hcnt.rs index 33736c7..77d7ea0 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/ss_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/ss_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_hcnt` reader - ss_scl_hcnt"] pub type SS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_hcnt` writer - ss_scl_hcnt"] -pub type SS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { - SS_SCL_HCNT_W::new(self) + pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { + SS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/ss_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c1/ss_scl_lcnt.rs index ce22b5d..8208747 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/ss_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/ss_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_lcnt` reader - ss_scl_lcnt"] pub type SS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_lcnt` writer - ss_scl_lcnt"] -pub type SS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { - SS_SCL_LCNT_W::new(self) + pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { + SS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/status.rs b/jh7110-vf2-13b-pac/src/i2c1/status.rs index 9489e49..1b7ab67 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/status.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/tar.rs b/jh7110-vf2-13b-pac/src/i2c1/tar.rs index 9fedc71..3044a8c 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/tar.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/tar.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Target address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Target address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Target address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Target address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; #[doc = "Field `mode` reader - Target addressing mode - 0: 7-bit, 1: 10-bit"] pub type MODE_R = crate::BitReader; #[doc = "Field `mode` writer - Target addressing mode - 0: 7-bit, 1: 10-bit"] -pub type MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Target address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } #[doc = "Bit 12 - Target addressing mode - 0: 7-bit, 1: 10-bit"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W { - MODE_W::new(self) + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 12) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/tx_abrt_source.rs b/jh7110-vf2-13b-pac/src/i2c1/tx_abrt_source.rs index 6f31813..c4fdf1a 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/tx_abrt_source.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/tx_abrt_source.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/tx_tl.rs b/jh7110-vf2-13b-pac/src/i2c1/tx_tl.rs index 84a1734..b0e6c64 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/tx_tl.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/tx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `tx_tl` reader - tx_tl"] pub type TX_TL_R = crate::FieldReader; #[doc = "Field `tx_tl` writer - tx_tl"] -pub type TX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] #[must_use] - pub fn tx_tl(&mut self) -> TX_TL_W { - TX_TL_W::new(self) + pub fn tx_tl(&mut self) -> TX_TL_W { + TX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c1/txflr.rs b/jh7110-vf2-13b-pac/src/i2c1/txflr.rs index b8e5fdd..5ca351d 100644 --- a/jh7110-vf2-13b-pac/src/i2c1/txflr.rs +++ b/jh7110-vf2-13b-pac/src/i2c1/txflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `txflr` reader - txflr"] pub type TXFLR_R = crate::FieldReader; #[doc = "Field `txflr` writer - txflr"] -pub type TXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - txflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - txflr"] #[inline(always)] #[must_use] - pub fn txflr(&mut self) -> TXFLR_W { - TXFLR_W::new(self) + pub fn txflr(&mut self) -> TXFLR_W { + TXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2.rs b/jh7110-vf2-13b-pac/src/i2c2.rs index d0fe76a..fdffe28 100644 --- a/jh7110-vf2-13b-pac/src/i2c2.rs +++ b/jh7110-vf2-13b-pac/src/i2c2.rs @@ -1,266 +1,416 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + con: CON, + tar: TAR, + sar: SAR, + _reserved3: [u8; 0x04], + data_cmd: DATA_CMD, + ss_scl_hcnt: SS_SCL_HCNT, + ss_scl_lcnt: SS_SCL_LCNT, + fs_scl_hcnt: FS_SCL_HCNT, + fs_scl_lcnt: FS_SCL_LCNT, + hs_scl_hcnt: HS_SCL_HCNT, + hs_scl_lcnt: HS_SCL_LCNT, + intr_stat: INTR_STAT, + intr_mask: INTR_MASK, + raw_intr_stat: RAW_INTR_STAT, + rx_tl: RX_TL, + tx_tl: TX_TL, + clr_intr: CLR_INTR, + clr_rx_under: CLR_RX_UNDER, + clr_rx_over: CLR_RX_OVER, + clr_tx_over: CLR_TX_OVER, + clr_rd_req: CLR_RD_REQ, + clr_tx_abrt: CLR_TX_ABRT, + clr_rx_done: CLR_RX_DONE, + clr_activity: CLR_ACTIVITY, + clr_stop_det: CLR_STOP_DET, + clr_start_det: CLR_START_DET, + clr_gen_call: CLR_GEN_CALL, + enable: ENABLE, + status: STATUS, + txflr: TXFLR, + rxflr: RXFLR, + sda_hold: SDA_HOLD, + tx_abrt_source: TX_ABRT_SOURCE, + _reserved32: [u8; 0x18], + enable_status: ENABLE_STATUS, + _reserved33: [u8; 0x08], + clr_restart_det: CLR_RESTART_DET, + _reserved34: [u8; 0x48], + comp_param_1: COMP_PARAM_1, + comp_version: COMP_VERSION, + comp_type: COMP_TYPE, +} +impl RegisterBlock { #[doc = "0x00 - DesignWare I2C CON"] - pub con: CON, + #[inline(always)] + pub const fn con(&self) -> &CON { + &self.con + } #[doc = "0x04 - DesignWare I2C TAR"] - pub tar: TAR, + #[inline(always)] + pub const fn tar(&self) -> &TAR { + &self.tar + } #[doc = "0x08 - DesignWare I2C SAR"] - pub sar: SAR, - _reserved3: [u8; 0x04], + #[inline(always)] + pub const fn sar(&self) -> &SAR { + &self.sar + } #[doc = "0x10 - DesignWare I2C Data Command"] - pub data_cmd: DATA_CMD, + #[inline(always)] + pub const fn data_cmd(&self) -> &DATA_CMD { + &self.data_cmd + } #[doc = "0x14 - DesignWare I2C SS SCL HCNT"] - pub ss_scl_hcnt: SS_SCL_HCNT, + #[inline(always)] + pub const fn ss_scl_hcnt(&self) -> &SS_SCL_HCNT { + &self.ss_scl_hcnt + } #[doc = "0x18 - DesignWare I2C SS SCL LCNT"] - pub ss_scl_lcnt: SS_SCL_LCNT, + #[inline(always)] + pub const fn ss_scl_lcnt(&self) -> &SS_SCL_LCNT { + &self.ss_scl_lcnt + } #[doc = "0x1c - DesignWare I2C FS SCL HCNT"] - pub fs_scl_hcnt: FS_SCL_HCNT, + #[inline(always)] + pub const fn fs_scl_hcnt(&self) -> &FS_SCL_HCNT { + &self.fs_scl_hcnt + } #[doc = "0x20 - DesignWare I2C FS SCL LCNT"] - pub fs_scl_lcnt: FS_SCL_LCNT, + #[inline(always)] + pub const fn fs_scl_lcnt(&self) -> &FS_SCL_LCNT { + &self.fs_scl_lcnt + } #[doc = "0x24 - DesignWare I2C HS SCL HCNT"] - pub hs_scl_hcnt: HS_SCL_HCNT, + #[inline(always)] + pub const fn hs_scl_hcnt(&self) -> &HS_SCL_HCNT { + &self.hs_scl_hcnt + } #[doc = "0x28 - DesignWare I2C HS SCL LCNT"] - pub hs_scl_lcnt: HS_SCL_LCNT, + #[inline(always)] + pub const fn hs_scl_lcnt(&self) -> &HS_SCL_LCNT { + &self.hs_scl_lcnt + } #[doc = "0x2c - DesignWare I2C Interrupt Status"] - pub intr_stat: INTR_STAT, + #[inline(always)] + pub const fn intr_stat(&self) -> &INTR_STAT { + &self.intr_stat + } #[doc = "0x30 - DesignWare I2C Interrupt Mask"] - pub intr_mask: INTR_MASK, + #[inline(always)] + pub const fn intr_mask(&self) -> &INTR_MASK { + &self.intr_mask + } #[doc = "0x34 - DesignWare I2C Raw Interrupt Status"] - pub raw_intr_stat: RAW_INTR_STAT, + #[inline(always)] + pub const fn raw_intr_stat(&self) -> &RAW_INTR_STAT { + &self.raw_intr_stat + } #[doc = "0x38 - DesignWare I2C RX TL"] - pub rx_tl: RX_TL, + #[inline(always)] + pub const fn rx_tl(&self) -> &RX_TL { + &self.rx_tl + } #[doc = "0x3c - DesignWare I2C TX TL"] - pub tx_tl: TX_TL, + #[inline(always)] + pub const fn tx_tl(&self) -> &TX_TL { + &self.tx_tl + } #[doc = "0x40 - DesignWare I2C Clear Interrrupt"] - pub clr_intr: CLR_INTR, + #[inline(always)] + pub const fn clr_intr(&self) -> &CLR_INTR { + &self.clr_intr + } #[doc = "0x44 - DesignWare I2C Clear RX Underrun"] - pub clr_rx_under: CLR_RX_UNDER, + #[inline(always)] + pub const fn clr_rx_under(&self) -> &CLR_RX_UNDER { + &self.clr_rx_under + } #[doc = "0x48 - DesignWare I2C Clear RX Overrun"] - pub clr_rx_over: CLR_RX_OVER, + #[inline(always)] + pub const fn clr_rx_over(&self) -> &CLR_RX_OVER { + &self.clr_rx_over + } #[doc = "0x4c - DesignWare I2C Clear TX Overrun"] - pub clr_tx_over: CLR_TX_OVER, + #[inline(always)] + pub const fn clr_tx_over(&self) -> &CLR_TX_OVER { + &self.clr_tx_over + } #[doc = "0x50 - DesignWare I2C Clear Read Request"] - pub clr_rd_req: CLR_RD_REQ, + #[inline(always)] + pub const fn clr_rd_req(&self) -> &CLR_RD_REQ { + &self.clr_rd_req + } #[doc = "0x54 - DesignWare I2C Clear TX Abort"] - pub clr_tx_abrt: CLR_TX_ABRT, + #[inline(always)] + pub const fn clr_tx_abrt(&self) -> &CLR_TX_ABRT { + &self.clr_tx_abrt + } #[doc = "0x58 - DesignWare I2C Clear RX Done"] - pub clr_rx_done: CLR_RX_DONE, + #[inline(always)] + pub const fn clr_rx_done(&self) -> &CLR_RX_DONE { + &self.clr_rx_done + } #[doc = "0x5c - DesignWare I2C Clear Activity"] - pub clr_activity: CLR_ACTIVITY, + #[inline(always)] + pub const fn clr_activity(&self) -> &CLR_ACTIVITY { + &self.clr_activity + } #[doc = "0x60 - DesignWare I2C Clear Stop DET"] - pub clr_stop_det: CLR_STOP_DET, + #[inline(always)] + pub const fn clr_stop_det(&self) -> &CLR_STOP_DET { + &self.clr_stop_det + } #[doc = "0x64 - DesignWare I2C Clear Start DET"] - pub clr_start_det: CLR_START_DET, + #[inline(always)] + pub const fn clr_start_det(&self) -> &CLR_START_DET { + &self.clr_start_det + } #[doc = "0x68 - DesignWare I2C Clear General Call"] - pub clr_gen_call: CLR_GEN_CALL, + #[inline(always)] + pub const fn clr_gen_call(&self) -> &CLR_GEN_CALL { + &self.clr_gen_call + } #[doc = "0x6c - DesignWare I2C Enable"] - pub enable: ENABLE, + #[inline(always)] + pub const fn enable(&self) -> &ENABLE { + &self.enable + } #[doc = "0x70 - DesignWare I2C Status"] - pub status: STATUS, + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } #[doc = "0x74 - DesignWare I2C TX Failure"] - pub txflr: TXFLR, + #[inline(always)] + pub const fn txflr(&self) -> &TXFLR { + &self.txflr + } #[doc = "0x78 - DesignWare I2C RX Failure"] - pub rxflr: RXFLR, + #[inline(always)] + pub const fn rxflr(&self) -> &RXFLR { + &self.rxflr + } #[doc = "0x7c - DesignWare I2C SDA Hold"] - pub sda_hold: SDA_HOLD, + #[inline(always)] + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold + } #[doc = "0x80 - DesignWare I2C TX Abort Source"] - pub tx_abrt_source: TX_ABRT_SOURCE, - _reserved32: [u8; 0x18], + #[inline(always)] + pub const fn tx_abrt_source(&self) -> &TX_ABRT_SOURCE { + &self.tx_abrt_source + } #[doc = "0x9c - DesignWare I2C Enable Status"] - pub enable_status: ENABLE_STATUS, - _reserved33: [u8; 0x08], + #[inline(always)] + pub const fn enable_status(&self) -> &ENABLE_STATUS { + &self.enable_status + } #[doc = "0xa8 - DesignWare I2C Clear Restart DET"] - pub clr_restart_det: CLR_RESTART_DET, - _reserved34: [u8; 0x48], + #[inline(always)] + pub const fn clr_restart_det(&self) -> &CLR_RESTART_DET { + &self.clr_restart_det + } #[doc = "0xf4 - DesignWare I2C Compatibility Parameter 1"] - pub comp_param_1: COMP_PARAM_1, + #[inline(always)] + pub const fn comp_param_1(&self) -> &COMP_PARAM_1 { + &self.comp_param_1 + } #[doc = "0xf8 - DesignWare I2C Compatibility Version"] - pub comp_version: COMP_VERSION, + #[inline(always)] + pub const fn comp_version(&self) -> &COMP_VERSION { + &self.comp_version + } #[doc = "0xfc - DesignWare I2C Compatibility Type"] - pub comp_type: COMP_TYPE, + #[inline(always)] + pub const fn comp_type(&self) -> &COMP_TYPE { + &self.comp_type + } } -#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`con`] +#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@con`] module"] pub type CON = crate::Reg; #[doc = "DesignWare I2C CON"] pub mod con; -#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tar`] +#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar`] module"] pub type TAR = crate::Reg; #[doc = "DesignWare I2C TAR"] pub mod tar; -#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sar`] +#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`] module"] pub type SAR = crate::Reg; #[doc = "DesignWare I2C SAR"] pub mod sar; -#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`data_cmd`] +#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_cmd`] module"] pub type DATA_CMD = crate::Reg; #[doc = "DesignWare I2C Data Command"] pub mod data_cmd; -#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_hcnt`] +#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_hcnt`] module"] pub type SS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL HCNT"] pub mod ss_scl_hcnt; -#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_lcnt`] +#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_lcnt`] module"] pub type SS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL LCNT"] pub mod ss_scl_lcnt; -#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_hcnt`] +#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_hcnt`] module"] pub type FS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL HCNT"] pub mod fs_scl_hcnt; -#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_lcnt`] +#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_lcnt`] module"] pub type FS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL LCNT"] pub mod fs_scl_lcnt; -#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_hcnt`] +#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_hcnt`] module"] pub type HS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL HCNT"] pub mod hs_scl_hcnt; -#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_lcnt`] +#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_lcnt`] module"] pub type HS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL LCNT"] pub mod hs_scl_lcnt; -#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_stat`] +#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"] pub type INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Interrupt Status"] pub mod intr_stat; -#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_mask`] +#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mask`] module"] pub type INTR_MASK = crate::Reg; #[doc = "DesignWare I2C Interrupt Mask"] pub mod intr_mask; -#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`raw_intr_stat`] +#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"] pub type RAW_INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Raw Interrupt Status"] pub mod raw_intr_stat; -#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rx_tl`] +#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tl`] module"] pub type RX_TL = crate::Reg; #[doc = "DesignWare I2C RX TL"] pub mod rx_tl; -#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_tl`] +#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_tl`] module"] pub type TX_TL = crate::Reg; #[doc = "DesignWare I2C TX TL"] pub mod tx_tl; -#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_intr`] +#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_intr`] module"] pub type CLR_INTR = crate::Reg; #[doc = "DesignWare I2C Clear Interrrupt"] pub mod clr_intr; -#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_under`] +#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_under`] module"] pub type CLR_RX_UNDER = crate::Reg; #[doc = "DesignWare I2C Clear RX Underrun"] pub mod clr_rx_under; -#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_over`] +#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_over`] module"] pub type CLR_RX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear RX Overrun"] pub mod clr_rx_over; -#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_over`] +#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_over`] module"] pub type CLR_TX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear TX Overrun"] pub mod clr_tx_over; -#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rd_req`] +#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rd_req`] module"] pub type CLR_RD_REQ = crate::Reg; #[doc = "DesignWare I2C Clear Read Request"] pub mod clr_rd_req; -#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_abrt`] +#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_abrt`] module"] pub type CLR_TX_ABRT = crate::Reg; #[doc = "DesignWare I2C Clear TX Abort"] pub mod clr_tx_abrt; -#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_done`] +#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_done`] module"] pub type CLR_RX_DONE = crate::Reg; #[doc = "DesignWare I2C Clear RX Done"] pub mod clr_rx_done; -#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_activity`] +#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_activity`] module"] pub type CLR_ACTIVITY = crate::Reg; #[doc = "DesignWare I2C Clear Activity"] pub mod clr_activity; -#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_stop_det`] +#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_stop_det`] module"] pub type CLR_STOP_DET = crate::Reg; #[doc = "DesignWare I2C Clear Stop DET"] pub mod clr_stop_det; -#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_start_det`] +#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_start_det`] module"] pub type CLR_START_DET = crate::Reg; #[doc = "DesignWare I2C Clear Start DET"] pub mod clr_start_det; -#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_gen_call`] +#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_gen_call`] module"] pub type CLR_GEN_CALL = crate::Reg; #[doc = "DesignWare I2C Clear General Call"] pub mod clr_gen_call; -#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable`] +#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] pub type ENABLE = crate::Reg; #[doc = "DesignWare I2C Enable"] pub mod enable; -#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`status`] +#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] pub type STATUS = crate::Reg; #[doc = "DesignWare I2C Status"] pub mod status; -#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txflr`] +#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txflr`] module"] pub type TXFLR = crate::Reg; #[doc = "DesignWare I2C TX Failure"] pub mod txflr; -#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxflr`] +#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxflr`] module"] pub type RXFLR = crate::Reg; #[doc = "DesignWare I2C RX Failure"] pub mod rxflr; -#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sda_hold`] +#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] pub type SDA_HOLD = crate::Reg; #[doc = "DesignWare I2C SDA Hold"] pub mod sda_hold; -#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_abrt_source`] +#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_abrt_source`] module"] pub type TX_ABRT_SOURCE = crate::Reg; #[doc = "DesignWare I2C TX Abort Source"] pub mod tx_abrt_source; -#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_status`] +#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_status`] module"] pub type ENABLE_STATUS = crate::Reg; #[doc = "DesignWare I2C Enable Status"] pub mod enable_status; -#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_restart_det`] +#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_restart_det`] module"] pub type CLR_RESTART_DET = crate::Reg; #[doc = "DesignWare I2C Clear Restart DET"] pub mod clr_restart_det; -#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_param_1`] +#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_param_1`] module"] pub type COMP_PARAM_1 = crate::Reg; #[doc = "DesignWare I2C Compatibility Parameter 1"] pub mod comp_param_1; -#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_version`] +#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_version`] module"] pub type COMP_VERSION = crate::Reg; #[doc = "DesignWare I2C Compatibility Version"] pub mod comp_version; -#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_type`] +#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_type`] module"] pub type COMP_TYPE = crate::Reg; #[doc = "DesignWare I2C Compatibility Type"] diff --git a/jh7110-vf2-13b-pac/src/i2c2/clr_activity.rs b/jh7110-vf2-13b-pac/src/i2c2/clr_activity.rs index d26bb80..1ee2297 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/clr_activity.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/clr_activity.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_activity` reader - clr_activity"] pub type CLR_ACTIVITY_R = crate::FieldReader; #[doc = "Field `clr_activity` writer - clr_activity"] -pub type CLR_ACTIVITY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_ACTIVITY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] #[must_use] - pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { - CLR_ACTIVITY_W::new(self) + pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { + CLR_ACTIVITY_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/clr_gen_call.rs b/jh7110-vf2-13b-pac/src/i2c2/clr_gen_call.rs index a9ea5af..4a7c5ba 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/clr_gen_call.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/clr_gen_call.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_gen_call` reader - clr_gen_call"] pub type CLR_GEN_CALL_R = crate::FieldReader; #[doc = "Field `clr_gen_call` writer - clr_gen_call"] -pub type CLR_GEN_CALL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_GEN_CALL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] #[must_use] - pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { - CLR_GEN_CALL_W::new(self) + pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { + CLR_GEN_CALL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/clr_intr.rs b/jh7110-vf2-13b-pac/src/i2c2/clr_intr.rs index a7daf57..cf57b09 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/clr_intr.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/clr_intr.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/clr_rd_req.rs b/jh7110-vf2-13b-pac/src/i2c2/clr_rd_req.rs index e275da1..4beae9d 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/clr_rd_req.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/clr_rd_req.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rd_req` reader - clr_rd_req"] pub type CLR_RD_REQ_R = crate::FieldReader; #[doc = "Field `clr_rd_req` writer - clr_rd_req"] -pub type CLR_RD_REQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RD_REQ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] #[must_use] - pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { - CLR_RD_REQ_W::new(self) + pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { + CLR_RD_REQ_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/clr_restart_det.rs b/jh7110-vf2-13b-pac/src/i2c2/clr_restart_det.rs index 5be7f5d..88d193c 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/clr_restart_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/clr_restart_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_restart_det` reader - clr_restart_det"] pub type CLR_RESTART_DET_R = crate::FieldReader; #[doc = "Field `clr_restart_det` writer - clr_restart_det"] -pub type CLR_RESTART_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RESTART_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] #[must_use] - pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { - CLR_RESTART_DET_W::new(self) + pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { + CLR_RESTART_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/clr_rx_done.rs b/jh7110-vf2-13b-pac/src/i2c2/clr_rx_done.rs index 02d83c5..7e14a3f 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/clr_rx_done.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/clr_rx_done.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_done` reader - clr_rx_done"] pub type CLR_RX_DONE_R = crate::FieldReader; #[doc = "Field `clr_rx_done` writer - clr_rx_done"] -pub type CLR_RX_DONE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_DONE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] #[must_use] - pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { - CLR_RX_DONE_W::new(self) + pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { + CLR_RX_DONE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/clr_rx_over.rs b/jh7110-vf2-13b-pac/src/i2c2/clr_rx_over.rs index 6d7ff4e..2302921 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/clr_rx_over.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/clr_rx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_over` reader - clr_rx_over"] pub type CLR_RX_OVER_R = crate::FieldReader; #[doc = "Field `clr_rx_over` writer - clr_rx_over"] -pub type CLR_RX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] #[must_use] - pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { - CLR_RX_OVER_W::new(self) + pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { + CLR_RX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/clr_rx_under.rs b/jh7110-vf2-13b-pac/src/i2c2/clr_rx_under.rs index 4a24f7c..35e15bd 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/clr_rx_under.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/clr_rx_under.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_under` reader - clr_rx_under"] pub type CLR_RX_UNDER_R = crate::FieldReader; #[doc = "Field `clr_rx_under` writer - clr_rx_under"] -pub type CLR_RX_UNDER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_UNDER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] #[must_use] - pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { - CLR_RX_UNDER_W::new(self) + pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { + CLR_RX_UNDER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/clr_start_det.rs b/jh7110-vf2-13b-pac/src/i2c2/clr_start_det.rs index cebc4bc..2314f65 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/clr_start_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/clr_start_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_start_det` reader - clr_start_det"] pub type CLR_START_DET_R = crate::FieldReader; #[doc = "Field `clr_start_det` writer - clr_start_det"] -pub type CLR_START_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_START_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] #[must_use] - pub fn clr_start_det(&mut self) -> CLR_START_DET_W { - CLR_START_DET_W::new(self) + pub fn clr_start_det(&mut self) -> CLR_START_DET_W { + CLR_START_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/clr_stop_det.rs b/jh7110-vf2-13b-pac/src/i2c2/clr_stop_det.rs index 44f39f3..49abcac 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/clr_stop_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/clr_stop_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_stop_det` reader - clr_stop_det"] pub type CLR_STOP_DET_R = crate::FieldReader; #[doc = "Field `clr_stop_det` writer - clr_stop_det"] -pub type CLR_STOP_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_STOP_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] #[must_use] - pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { - CLR_STOP_DET_W::new(self) + pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { + CLR_STOP_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/clr_tx_abrt.rs b/jh7110-vf2-13b-pac/src/i2c2/clr_tx_abrt.rs index 6ac441c..3bc0f6f 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/clr_tx_abrt.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/clr_tx_abrt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_abrt` reader - clr_tx_abrt"] pub type CLR_TX_ABRT_R = crate::FieldReader; #[doc = "Field `clr_tx_abrt` writer - clr_tx_abrt"] -pub type CLR_TX_ABRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_ABRT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] #[must_use] - pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { - CLR_TX_ABRT_W::new(self) + pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { + CLR_TX_ABRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/clr_tx_over.rs b/jh7110-vf2-13b-pac/src/i2c2/clr_tx_over.rs index 2b32b52..a5b6933 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/clr_tx_over.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/clr_tx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_over` reader - clr_tx_over"] pub type CLR_TX_OVER_R = crate::FieldReader; #[doc = "Field `clr_tx_over` writer - clr_tx_over"] -pub type CLR_TX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] #[must_use] - pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { - CLR_TX_OVER_W::new(self) + pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { + CLR_TX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/comp_param_1.rs b/jh7110-vf2-13b-pac/src/i2c2/comp_param_1.rs index 24a22e1..95c5002 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/comp_param_1.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/comp_param_1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/comp_type.rs b/jh7110-vf2-13b-pac/src/i2c2/comp_type.rs index ac916b5..1336c43 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/comp_type.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/comp_type.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/comp_version.rs b/jh7110-vf2-13b-pac/src/i2c2/comp_version.rs index 4be31fa..e8309c8 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/comp_version.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/comp_version.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/con.rs b/jh7110-vf2-13b-pac/src/i2c2/con.rs index 873c534..28aa865 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/con.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/con.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `master` reader - I2C Master Connection - 0: Slave, 1: Master"] pub type MASTER_R = crate::BitReader; #[doc = "Field `master` writer - I2C Master Connection - 0: Slave, 1: Master"] -pub type MASTER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `speed` reader - I2C Speed - 01: Standard, 10: Fast, 11: High"] pub type SPEED_R = crate::FieldReader; #[doc = "Field `speed` writer - I2C Speed - 01: Standard, 10: Fast, 11: High"] -pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `slave_10bitaddr` reader - I2C Slave 10-bit Address - 0: False, 1: True"] pub type SLAVE_10BITADDR_R = crate::BitReader; #[doc = "Field `slave_10bitaddr` writer - I2C Slave 10-bit Address - 0: False, 1: True"] -pub type SLAVE_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_10bitaddr` reader - I2C Master 10-bit Address - 0: False, 1: True"] pub type MASTER_10BITADDR_R = crate::BitReader; #[doc = "Field `master_10bitaddr` writer - I2C Master 10-bit Address - 0: False, 1: True"] -pub type MASTER_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_en` reader - I2C Restart Enable - 0: False, 1: True"] pub type RESTART_EN_R = crate::BitReader; #[doc = "Field `restart_en` writer - I2C Restart Enable - 0: False, 1: True"] -pub type RESTART_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_disable` reader - I2C Slave Disable - 0: False, 1: True"] pub type SLAVE_DISABLE_R = crate::BitReader; #[doc = "Field `slave_disable` writer - I2C Slave Disable - 0: False, 1: True"] -pub type SLAVE_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det_ifaddressed` reader - I2C Stop DET If Addressed - 0: False, 1: True"] pub type STOP_DET_IFADDRESSED_R = crate::BitReader; #[doc = "Field `stop_det_ifaddressed` writer - I2C Stop DET If Addressed - 0: False, 1: True"] -pub type STOP_DET_IFADDRESSED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty_ctrl` reader - I2C TX Empty Control - 0: False, 1: True"] pub type TX_EMPTY_CTRL_R = crate::BitReader; #[doc = "Field `tx_empty_ctrl` writer - I2C TX Empty Control - 0: False, 1: True"] -pub type TX_EMPTY_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_fifo_full_hld_ctrl` reader - I2C RX FIFO Full Hold Control - 0: False, 1: True"] pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; #[doc = "Field `rx_fifo_full_hld_ctrl` writer - I2C RX FIFO Full Hold Control - 0: False, 1: True"] -pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bus_clear_ctrl` reader - I2C Bus Clear Control - 0: False, 1: True"] pub type BUS_CLEAR_CTRL_R = crate::BitReader; #[doc = "Field `bus_clear_ctrl` writer - I2C Bus Clear Control - 0: False, 1: True"] -pub type BUS_CLEAR_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BUS_CLEAR_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] #[must_use] - pub fn master(&mut self) -> MASTER_W { - MASTER_W::new(self) + pub fn master(&mut self) -> MASTER_W { + MASTER_W::new(self, 0) } #[doc = "Bits 1:2 - I2C Speed - 01: Standard, 10: Fast, 11: High"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W { - SPEED_W::new(self) + pub fn speed(&mut self) -> SPEED_W { + SPEED_W::new(self, 1) } #[doc = "Bit 3 - I2C Slave 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { - SLAVE_10BITADDR_W::new(self) + pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { + SLAVE_10BITADDR_W::new(self, 3) } #[doc = "Bit 4 - I2C Master 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { - MASTER_10BITADDR_W::new(self) + pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { + MASTER_10BITADDR_W::new(self, 4) } #[doc = "Bit 5 - I2C Restart Enable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn restart_en(&mut self) -> RESTART_EN_W { - RESTART_EN_W::new(self) + pub fn restart_en(&mut self) -> RESTART_EN_W { + RESTART_EN_W::new(self, 5) } #[doc = "Bit 6 - I2C Slave Disable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { - SLAVE_DISABLE_W::new(self) + pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { + SLAVE_DISABLE_W::new(self, 6) } #[doc = "Bit 7 - I2C Stop DET If Addressed - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { - STOP_DET_IFADDRESSED_W::new(self) + pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { + STOP_DET_IFADDRESSED_W::new(self, 7) } #[doc = "Bit 8 - I2C TX Empty Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { - TX_EMPTY_CTRL_W::new(self) + pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { + TX_EMPTY_CTRL_W::new(self, 8) } #[doc = "Bit 9 - I2C RX FIFO Full Hold Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { - RX_FIFO_FULL_HLD_CTRL_W::new(self) + pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { + RX_FIFO_FULL_HLD_CTRL_W::new(self, 9) } #[doc = "Bit 11 - I2C Bus Clear Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { - BUS_CLEAR_CTRL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { + BUS_CLEAR_CTRL_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/data_cmd.rs b/jh7110-vf2-13b-pac/src/i2c2/data_cmd.rs index cf36408..2b320d4 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/data_cmd.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/data_cmd.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `dat` reader - Data Command Data Byte"] pub type DAT_R = crate::FieldReader; #[doc = "Field `dat` writer - Data Command Data Byte"] -pub type DAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `read` reader - Data Command READ Bit - 0: Write, 1: Read"] pub type READ_R = crate::BitReader; #[doc = "Field `read` writer - Data Command READ Bit - 0: Write, 1: Read"] -pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop` reader - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart` reader - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] pub type RESTART_R = crate::BitReader; #[doc = "Field `restart` writer - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] -pub type RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `first_data_byte` reader - Data Command First Data Byte - 0: False, 1: True"] pub type FIRST_DATA_BYTE_R = crate::BitReader; #[doc = "Field `first_data_byte` writer - Data Command First Data Byte - 0: False, 1: True"] -pub type FIRST_DATA_BYTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIRST_DATA_BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] #[must_use] - pub fn dat(&mut self) -> DAT_W { - DAT_W::new(self) + pub fn dat(&mut self) -> DAT_W { + DAT_W::new(self, 0) } #[doc = "Bit 8 - Data Command READ Bit - 0: Write, 1: Read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W { - READ_W::new(self) + pub fn read(&mut self) -> READ_W { + READ_W::new(self, 8) } #[doc = "Bit 9 - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 9) } #[doc = "Bit 10 - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] #[inline(always)] #[must_use] - pub fn restart(&mut self) -> RESTART_W { - RESTART_W::new(self) + pub fn restart(&mut self) -> RESTART_W { + RESTART_W::new(self, 10) } #[doc = "Bit 11 - Data Command First Data Byte - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { - FIRST_DATA_BYTE_W::new(self) + pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { + FIRST_DATA_BYTE_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/enable.rs b/jh7110-vf2-13b-pac/src/i2c2/enable.rs index c5ca9d7..3629f6b 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/enable.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/enable.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `abort` reader - abort"] pub type ABORT_R = crate::BitReader; #[doc = "Field `abort` writer - abort"] -pub type ABORT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 1 - abort"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 1 - abort"] #[inline(always)] #[must_use] - pub fn abort(&mut self) -> ABORT_W { - ABORT_W::new(self) + pub fn abort(&mut self) -> ABORT_W { + ABORT_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/enable_status.rs b/jh7110-vf2-13b-pac/src/i2c2/enable_status.rs index 2c102a6..8b9b7d3 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/enable_status.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/enable_status.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `activity` reader - activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tfe` reader - tfe"] pub type TFE_R = crate::BitReader; #[doc = "Field `tfe` writer - tfe"] -pub type TFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TFE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfne` reader - rfne"] pub type RFNE_R = crate::BitReader; #[doc = "Field `rfne` writer - rfne"] -pub type RFNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFNE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_activity` reader - master_activity"] pub type MASTER_ACTIVITY_R = crate::BitReader; #[doc = "Field `master_activity` writer - master_activity"] -pub type MASTER_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_activity` reader - slave_activity"] pub type SLAVE_ACTIVITY_R = crate::BitReader; #[doc = "Field `slave_activity` writer - slave_activity"] -pub type SLAVE_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - activity"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 0) } #[doc = "Bit 2 - tfe"] #[inline(always)] #[must_use] - pub fn tfe(&mut self) -> TFE_W { - TFE_W::new(self) + pub fn tfe(&mut self) -> TFE_W { + TFE_W::new(self, 2) } #[doc = "Bit 3 - rfne"] #[inline(always)] #[must_use] - pub fn rfne(&mut self) -> RFNE_W { - RFNE_W::new(self) + pub fn rfne(&mut self) -> RFNE_W { + RFNE_W::new(self, 3) } #[doc = "Bit 5 - master_activity"] #[inline(always)] #[must_use] - pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { - MASTER_ACTIVITY_W::new(self) + pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { + MASTER_ACTIVITY_W::new(self, 5) } #[doc = "Bit 6 - slave_activity"] #[inline(always)] #[must_use] - pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { - SLAVE_ACTIVITY_W::new(self) + pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { + SLAVE_ACTIVITY_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/fs_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c2/fs_scl_hcnt.rs index 9a9fd72..8a4f6d1 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/fs_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/fs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_hcnt` reader - fs_scl_hcnt"] pub type FS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_hcnt` writer - fs_scl_hcnt"] -pub type FS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { - FS_SCL_HCNT_W::new(self) + pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { + FS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/fs_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c2/fs_scl_lcnt.rs index 5e41cd1..4b4dd6b 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/fs_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/fs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_lcnt` reader - fs_scl_lcnt"] pub type FS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_lcnt` writer - fs_scl_lcnt"] -pub type FS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { - FS_SCL_LCNT_W::new(self) + pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { + FS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/hs_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c2/hs_scl_hcnt.rs index fba7f13..9b0a71c 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/hs_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/hs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_hcnt` reader - hs_scl_hcnt"] pub type HS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_hcnt` writer - hs_scl_hcnt"] -pub type HS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { - HS_SCL_HCNT_W::new(self) + pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { + HS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/hs_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c2/hs_scl_lcnt.rs index 9fca7a5..a715282 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/hs_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/hs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_lcnt` reader - hs_scl_lcnt"] pub type HS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_lcnt` writer - hs_scl_lcnt"] -pub type HS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { - HS_SCL_LCNT_W::new(self) + pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { + HS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/intr_mask.rs b/jh7110-vf2-13b-pac/src/i2c2/intr_mask.rs index 20a334f..769b629 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/intr_mask.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/intr_mask.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/intr_stat.rs b/jh7110-vf2-13b-pac/src/i2c2/intr_stat.rs index 2c2ba34..f376c26 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/intr_stat.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/raw_intr_stat.rs b/jh7110-vf2-13b-pac/src/i2c2/raw_intr_stat.rs index af97981..dd5e8e0 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/raw_intr_stat.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/raw_intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/rx_tl.rs b/jh7110-vf2-13b-pac/src/i2c2/rx_tl.rs index 1455a10..f3f39f4 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/rx_tl.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/rx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rx_tl` reader - rx_tl"] pub type RX_TL_R = crate::FieldReader; #[doc = "Field `rx_tl` writer - rx_tl"] -pub type RX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] #[must_use] - pub fn rx_tl(&mut self) -> RX_TL_W { - RX_TL_W::new(self) + pub fn rx_tl(&mut self) -> RX_TL_W { + RX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/rxflr.rs b/jh7110-vf2-13b-pac/src/i2c2/rxflr.rs index 910e254..4dccf5e 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/rxflr.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/rxflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rxflr` reader - rxflr"] pub type RXFLR_R = crate::FieldReader; #[doc = "Field `rxflr` writer - rxflr"] -pub type RXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] #[must_use] - pub fn rxflr(&mut self) -> RXFLR_W { - RXFLR_W::new(self) + pub fn rxflr(&mut self) -> RXFLR_W { + RXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/sar.rs b/jh7110-vf2-13b-pac/src/i2c2/sar.rs index d272e7a..1af6273 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/sar.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/sar.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Slave address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Slave address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Slave address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Slave address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; impl R { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Slave address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/sda_hold.rs b/jh7110-vf2-13b-pac/src/i2c2/sda_hold.rs index 82ceac5..d5d7512 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/sda_hold.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/sda_hold.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sda_hold` reader - sda_hold"] pub type SDA_HOLD_R = crate::FieldReader; #[doc = "Field `sda_hold` writer - sda_hold"] -pub type SDA_HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SDA_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] #[must_use] - pub fn sda_hold(&mut self) -> SDA_HOLD_W { - SDA_HOLD_W::new(self) + pub fn sda_hold(&mut self) -> SDA_HOLD_W { + SDA_HOLD_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/ss_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c2/ss_scl_hcnt.rs index 33736c7..77d7ea0 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/ss_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/ss_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_hcnt` reader - ss_scl_hcnt"] pub type SS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_hcnt` writer - ss_scl_hcnt"] -pub type SS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { - SS_SCL_HCNT_W::new(self) + pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { + SS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/ss_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c2/ss_scl_lcnt.rs index ce22b5d..8208747 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/ss_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/ss_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_lcnt` reader - ss_scl_lcnt"] pub type SS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_lcnt` writer - ss_scl_lcnt"] -pub type SS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { - SS_SCL_LCNT_W::new(self) + pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { + SS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/status.rs b/jh7110-vf2-13b-pac/src/i2c2/status.rs index 9489e49..1b7ab67 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/status.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/tar.rs b/jh7110-vf2-13b-pac/src/i2c2/tar.rs index 9fedc71..3044a8c 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/tar.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/tar.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Target address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Target address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Target address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Target address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; #[doc = "Field `mode` reader - Target addressing mode - 0: 7-bit, 1: 10-bit"] pub type MODE_R = crate::BitReader; #[doc = "Field `mode` writer - Target addressing mode - 0: 7-bit, 1: 10-bit"] -pub type MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Target address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } #[doc = "Bit 12 - Target addressing mode - 0: 7-bit, 1: 10-bit"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W { - MODE_W::new(self) + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 12) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/tx_abrt_source.rs b/jh7110-vf2-13b-pac/src/i2c2/tx_abrt_source.rs index 6f31813..c4fdf1a 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/tx_abrt_source.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/tx_abrt_source.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/tx_tl.rs b/jh7110-vf2-13b-pac/src/i2c2/tx_tl.rs index 84a1734..b0e6c64 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/tx_tl.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/tx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `tx_tl` reader - tx_tl"] pub type TX_TL_R = crate::FieldReader; #[doc = "Field `tx_tl` writer - tx_tl"] -pub type TX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] #[must_use] - pub fn tx_tl(&mut self) -> TX_TL_W { - TX_TL_W::new(self) + pub fn tx_tl(&mut self) -> TX_TL_W { + TX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c2/txflr.rs b/jh7110-vf2-13b-pac/src/i2c2/txflr.rs index b8e5fdd..5ca351d 100644 --- a/jh7110-vf2-13b-pac/src/i2c2/txflr.rs +++ b/jh7110-vf2-13b-pac/src/i2c2/txflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `txflr` reader - txflr"] pub type TXFLR_R = crate::FieldReader; #[doc = "Field `txflr` writer - txflr"] -pub type TXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - txflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - txflr"] #[inline(always)] #[must_use] - pub fn txflr(&mut self) -> TXFLR_W { - TXFLR_W::new(self) + pub fn txflr(&mut self) -> TXFLR_W { + TXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3.rs b/jh7110-vf2-13b-pac/src/i2c3.rs index d0fe76a..fdffe28 100644 --- a/jh7110-vf2-13b-pac/src/i2c3.rs +++ b/jh7110-vf2-13b-pac/src/i2c3.rs @@ -1,266 +1,416 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + con: CON, + tar: TAR, + sar: SAR, + _reserved3: [u8; 0x04], + data_cmd: DATA_CMD, + ss_scl_hcnt: SS_SCL_HCNT, + ss_scl_lcnt: SS_SCL_LCNT, + fs_scl_hcnt: FS_SCL_HCNT, + fs_scl_lcnt: FS_SCL_LCNT, + hs_scl_hcnt: HS_SCL_HCNT, + hs_scl_lcnt: HS_SCL_LCNT, + intr_stat: INTR_STAT, + intr_mask: INTR_MASK, + raw_intr_stat: RAW_INTR_STAT, + rx_tl: RX_TL, + tx_tl: TX_TL, + clr_intr: CLR_INTR, + clr_rx_under: CLR_RX_UNDER, + clr_rx_over: CLR_RX_OVER, + clr_tx_over: CLR_TX_OVER, + clr_rd_req: CLR_RD_REQ, + clr_tx_abrt: CLR_TX_ABRT, + clr_rx_done: CLR_RX_DONE, + clr_activity: CLR_ACTIVITY, + clr_stop_det: CLR_STOP_DET, + clr_start_det: CLR_START_DET, + clr_gen_call: CLR_GEN_CALL, + enable: ENABLE, + status: STATUS, + txflr: TXFLR, + rxflr: RXFLR, + sda_hold: SDA_HOLD, + tx_abrt_source: TX_ABRT_SOURCE, + _reserved32: [u8; 0x18], + enable_status: ENABLE_STATUS, + _reserved33: [u8; 0x08], + clr_restart_det: CLR_RESTART_DET, + _reserved34: [u8; 0x48], + comp_param_1: COMP_PARAM_1, + comp_version: COMP_VERSION, + comp_type: COMP_TYPE, +} +impl RegisterBlock { #[doc = "0x00 - DesignWare I2C CON"] - pub con: CON, + #[inline(always)] + pub const fn con(&self) -> &CON { + &self.con + } #[doc = "0x04 - DesignWare I2C TAR"] - pub tar: TAR, + #[inline(always)] + pub const fn tar(&self) -> &TAR { + &self.tar + } #[doc = "0x08 - DesignWare I2C SAR"] - pub sar: SAR, - _reserved3: [u8; 0x04], + #[inline(always)] + pub const fn sar(&self) -> &SAR { + &self.sar + } #[doc = "0x10 - DesignWare I2C Data Command"] - pub data_cmd: DATA_CMD, + #[inline(always)] + pub const fn data_cmd(&self) -> &DATA_CMD { + &self.data_cmd + } #[doc = "0x14 - DesignWare I2C SS SCL HCNT"] - pub ss_scl_hcnt: SS_SCL_HCNT, + #[inline(always)] + pub const fn ss_scl_hcnt(&self) -> &SS_SCL_HCNT { + &self.ss_scl_hcnt + } #[doc = "0x18 - DesignWare I2C SS SCL LCNT"] - pub ss_scl_lcnt: SS_SCL_LCNT, + #[inline(always)] + pub const fn ss_scl_lcnt(&self) -> &SS_SCL_LCNT { + &self.ss_scl_lcnt + } #[doc = "0x1c - DesignWare I2C FS SCL HCNT"] - pub fs_scl_hcnt: FS_SCL_HCNT, + #[inline(always)] + pub const fn fs_scl_hcnt(&self) -> &FS_SCL_HCNT { + &self.fs_scl_hcnt + } #[doc = "0x20 - DesignWare I2C FS SCL LCNT"] - pub fs_scl_lcnt: FS_SCL_LCNT, + #[inline(always)] + pub const fn fs_scl_lcnt(&self) -> &FS_SCL_LCNT { + &self.fs_scl_lcnt + } #[doc = "0x24 - DesignWare I2C HS SCL HCNT"] - pub hs_scl_hcnt: HS_SCL_HCNT, + #[inline(always)] + pub const fn hs_scl_hcnt(&self) -> &HS_SCL_HCNT { + &self.hs_scl_hcnt + } #[doc = "0x28 - DesignWare I2C HS SCL LCNT"] - pub hs_scl_lcnt: HS_SCL_LCNT, + #[inline(always)] + pub const fn hs_scl_lcnt(&self) -> &HS_SCL_LCNT { + &self.hs_scl_lcnt + } #[doc = "0x2c - DesignWare I2C Interrupt Status"] - pub intr_stat: INTR_STAT, + #[inline(always)] + pub const fn intr_stat(&self) -> &INTR_STAT { + &self.intr_stat + } #[doc = "0x30 - DesignWare I2C Interrupt Mask"] - pub intr_mask: INTR_MASK, + #[inline(always)] + pub const fn intr_mask(&self) -> &INTR_MASK { + &self.intr_mask + } #[doc = "0x34 - DesignWare I2C Raw Interrupt Status"] - pub raw_intr_stat: RAW_INTR_STAT, + #[inline(always)] + pub const fn raw_intr_stat(&self) -> &RAW_INTR_STAT { + &self.raw_intr_stat + } #[doc = "0x38 - DesignWare I2C RX TL"] - pub rx_tl: RX_TL, + #[inline(always)] + pub const fn rx_tl(&self) -> &RX_TL { + &self.rx_tl + } #[doc = "0x3c - DesignWare I2C TX TL"] - pub tx_tl: TX_TL, + #[inline(always)] + pub const fn tx_tl(&self) -> &TX_TL { + &self.tx_tl + } #[doc = "0x40 - DesignWare I2C Clear Interrrupt"] - pub clr_intr: CLR_INTR, + #[inline(always)] + pub const fn clr_intr(&self) -> &CLR_INTR { + &self.clr_intr + } #[doc = "0x44 - DesignWare I2C Clear RX Underrun"] - pub clr_rx_under: CLR_RX_UNDER, + #[inline(always)] + pub const fn clr_rx_under(&self) -> &CLR_RX_UNDER { + &self.clr_rx_under + } #[doc = "0x48 - DesignWare I2C Clear RX Overrun"] - pub clr_rx_over: CLR_RX_OVER, + #[inline(always)] + pub const fn clr_rx_over(&self) -> &CLR_RX_OVER { + &self.clr_rx_over + } #[doc = "0x4c - DesignWare I2C Clear TX Overrun"] - pub clr_tx_over: CLR_TX_OVER, + #[inline(always)] + pub const fn clr_tx_over(&self) -> &CLR_TX_OVER { + &self.clr_tx_over + } #[doc = "0x50 - DesignWare I2C Clear Read Request"] - pub clr_rd_req: CLR_RD_REQ, + #[inline(always)] + pub const fn clr_rd_req(&self) -> &CLR_RD_REQ { + &self.clr_rd_req + } #[doc = "0x54 - DesignWare I2C Clear TX Abort"] - pub clr_tx_abrt: CLR_TX_ABRT, + #[inline(always)] + pub const fn clr_tx_abrt(&self) -> &CLR_TX_ABRT { + &self.clr_tx_abrt + } #[doc = "0x58 - DesignWare I2C Clear RX Done"] - pub clr_rx_done: CLR_RX_DONE, + #[inline(always)] + pub const fn clr_rx_done(&self) -> &CLR_RX_DONE { + &self.clr_rx_done + } #[doc = "0x5c - DesignWare I2C Clear Activity"] - pub clr_activity: CLR_ACTIVITY, + #[inline(always)] + pub const fn clr_activity(&self) -> &CLR_ACTIVITY { + &self.clr_activity + } #[doc = "0x60 - DesignWare I2C Clear Stop DET"] - pub clr_stop_det: CLR_STOP_DET, + #[inline(always)] + pub const fn clr_stop_det(&self) -> &CLR_STOP_DET { + &self.clr_stop_det + } #[doc = "0x64 - DesignWare I2C Clear Start DET"] - pub clr_start_det: CLR_START_DET, + #[inline(always)] + pub const fn clr_start_det(&self) -> &CLR_START_DET { + &self.clr_start_det + } #[doc = "0x68 - DesignWare I2C Clear General Call"] - pub clr_gen_call: CLR_GEN_CALL, + #[inline(always)] + pub const fn clr_gen_call(&self) -> &CLR_GEN_CALL { + &self.clr_gen_call + } #[doc = "0x6c - DesignWare I2C Enable"] - pub enable: ENABLE, + #[inline(always)] + pub const fn enable(&self) -> &ENABLE { + &self.enable + } #[doc = "0x70 - DesignWare I2C Status"] - pub status: STATUS, + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } #[doc = "0x74 - DesignWare I2C TX Failure"] - pub txflr: TXFLR, + #[inline(always)] + pub const fn txflr(&self) -> &TXFLR { + &self.txflr + } #[doc = "0x78 - DesignWare I2C RX Failure"] - pub rxflr: RXFLR, + #[inline(always)] + pub const fn rxflr(&self) -> &RXFLR { + &self.rxflr + } #[doc = "0x7c - DesignWare I2C SDA Hold"] - pub sda_hold: SDA_HOLD, + #[inline(always)] + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold + } #[doc = "0x80 - DesignWare I2C TX Abort Source"] - pub tx_abrt_source: TX_ABRT_SOURCE, - _reserved32: [u8; 0x18], + #[inline(always)] + pub const fn tx_abrt_source(&self) -> &TX_ABRT_SOURCE { + &self.tx_abrt_source + } #[doc = "0x9c - DesignWare I2C Enable Status"] - pub enable_status: ENABLE_STATUS, - _reserved33: [u8; 0x08], + #[inline(always)] + pub const fn enable_status(&self) -> &ENABLE_STATUS { + &self.enable_status + } #[doc = "0xa8 - DesignWare I2C Clear Restart DET"] - pub clr_restart_det: CLR_RESTART_DET, - _reserved34: [u8; 0x48], + #[inline(always)] + pub const fn clr_restart_det(&self) -> &CLR_RESTART_DET { + &self.clr_restart_det + } #[doc = "0xf4 - DesignWare I2C Compatibility Parameter 1"] - pub comp_param_1: COMP_PARAM_1, + #[inline(always)] + pub const fn comp_param_1(&self) -> &COMP_PARAM_1 { + &self.comp_param_1 + } #[doc = "0xf8 - DesignWare I2C Compatibility Version"] - pub comp_version: COMP_VERSION, + #[inline(always)] + pub const fn comp_version(&self) -> &COMP_VERSION { + &self.comp_version + } #[doc = "0xfc - DesignWare I2C Compatibility Type"] - pub comp_type: COMP_TYPE, + #[inline(always)] + pub const fn comp_type(&self) -> &COMP_TYPE { + &self.comp_type + } } -#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`con`] +#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@con`] module"] pub type CON = crate::Reg; #[doc = "DesignWare I2C CON"] pub mod con; -#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tar`] +#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar`] module"] pub type TAR = crate::Reg; #[doc = "DesignWare I2C TAR"] pub mod tar; -#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sar`] +#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`] module"] pub type SAR = crate::Reg; #[doc = "DesignWare I2C SAR"] pub mod sar; -#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`data_cmd`] +#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_cmd`] module"] pub type DATA_CMD = crate::Reg; #[doc = "DesignWare I2C Data Command"] pub mod data_cmd; -#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_hcnt`] +#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_hcnt`] module"] pub type SS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL HCNT"] pub mod ss_scl_hcnt; -#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_lcnt`] +#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_lcnt`] module"] pub type SS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL LCNT"] pub mod ss_scl_lcnt; -#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_hcnt`] +#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_hcnt`] module"] pub type FS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL HCNT"] pub mod fs_scl_hcnt; -#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_lcnt`] +#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_lcnt`] module"] pub type FS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL LCNT"] pub mod fs_scl_lcnt; -#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_hcnt`] +#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_hcnt`] module"] pub type HS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL HCNT"] pub mod hs_scl_hcnt; -#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_lcnt`] +#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_lcnt`] module"] pub type HS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL LCNT"] pub mod hs_scl_lcnt; -#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_stat`] +#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"] pub type INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Interrupt Status"] pub mod intr_stat; -#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_mask`] +#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mask`] module"] pub type INTR_MASK = crate::Reg; #[doc = "DesignWare I2C Interrupt Mask"] pub mod intr_mask; -#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`raw_intr_stat`] +#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"] pub type RAW_INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Raw Interrupt Status"] pub mod raw_intr_stat; -#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rx_tl`] +#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tl`] module"] pub type RX_TL = crate::Reg; #[doc = "DesignWare I2C RX TL"] pub mod rx_tl; -#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_tl`] +#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_tl`] module"] pub type TX_TL = crate::Reg; #[doc = "DesignWare I2C TX TL"] pub mod tx_tl; -#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_intr`] +#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_intr`] module"] pub type CLR_INTR = crate::Reg; #[doc = "DesignWare I2C Clear Interrrupt"] pub mod clr_intr; -#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_under`] +#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_under`] module"] pub type CLR_RX_UNDER = crate::Reg; #[doc = "DesignWare I2C Clear RX Underrun"] pub mod clr_rx_under; -#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_over`] +#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_over`] module"] pub type CLR_RX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear RX Overrun"] pub mod clr_rx_over; -#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_over`] +#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_over`] module"] pub type CLR_TX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear TX Overrun"] pub mod clr_tx_over; -#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rd_req`] +#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rd_req`] module"] pub type CLR_RD_REQ = crate::Reg; #[doc = "DesignWare I2C Clear Read Request"] pub mod clr_rd_req; -#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_abrt`] +#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_abrt`] module"] pub type CLR_TX_ABRT = crate::Reg; #[doc = "DesignWare I2C Clear TX Abort"] pub mod clr_tx_abrt; -#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_done`] +#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_done`] module"] pub type CLR_RX_DONE = crate::Reg; #[doc = "DesignWare I2C Clear RX Done"] pub mod clr_rx_done; -#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_activity`] +#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_activity`] module"] pub type CLR_ACTIVITY = crate::Reg; #[doc = "DesignWare I2C Clear Activity"] pub mod clr_activity; -#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_stop_det`] +#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_stop_det`] module"] pub type CLR_STOP_DET = crate::Reg; #[doc = "DesignWare I2C Clear Stop DET"] pub mod clr_stop_det; -#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_start_det`] +#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_start_det`] module"] pub type CLR_START_DET = crate::Reg; #[doc = "DesignWare I2C Clear Start DET"] pub mod clr_start_det; -#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_gen_call`] +#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_gen_call`] module"] pub type CLR_GEN_CALL = crate::Reg; #[doc = "DesignWare I2C Clear General Call"] pub mod clr_gen_call; -#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable`] +#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] pub type ENABLE = crate::Reg; #[doc = "DesignWare I2C Enable"] pub mod enable; -#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`status`] +#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] pub type STATUS = crate::Reg; #[doc = "DesignWare I2C Status"] pub mod status; -#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txflr`] +#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txflr`] module"] pub type TXFLR = crate::Reg; #[doc = "DesignWare I2C TX Failure"] pub mod txflr; -#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxflr`] +#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxflr`] module"] pub type RXFLR = crate::Reg; #[doc = "DesignWare I2C RX Failure"] pub mod rxflr; -#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sda_hold`] +#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] pub type SDA_HOLD = crate::Reg; #[doc = "DesignWare I2C SDA Hold"] pub mod sda_hold; -#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_abrt_source`] +#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_abrt_source`] module"] pub type TX_ABRT_SOURCE = crate::Reg; #[doc = "DesignWare I2C TX Abort Source"] pub mod tx_abrt_source; -#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_status`] +#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_status`] module"] pub type ENABLE_STATUS = crate::Reg; #[doc = "DesignWare I2C Enable Status"] pub mod enable_status; -#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_restart_det`] +#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_restart_det`] module"] pub type CLR_RESTART_DET = crate::Reg; #[doc = "DesignWare I2C Clear Restart DET"] pub mod clr_restart_det; -#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_param_1`] +#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_param_1`] module"] pub type COMP_PARAM_1 = crate::Reg; #[doc = "DesignWare I2C Compatibility Parameter 1"] pub mod comp_param_1; -#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_version`] +#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_version`] module"] pub type COMP_VERSION = crate::Reg; #[doc = "DesignWare I2C Compatibility Version"] pub mod comp_version; -#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_type`] +#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_type`] module"] pub type COMP_TYPE = crate::Reg; #[doc = "DesignWare I2C Compatibility Type"] diff --git a/jh7110-vf2-13b-pac/src/i2c3/clr_activity.rs b/jh7110-vf2-13b-pac/src/i2c3/clr_activity.rs index d26bb80..1ee2297 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/clr_activity.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/clr_activity.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_activity` reader - clr_activity"] pub type CLR_ACTIVITY_R = crate::FieldReader; #[doc = "Field `clr_activity` writer - clr_activity"] -pub type CLR_ACTIVITY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_ACTIVITY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] #[must_use] - pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { - CLR_ACTIVITY_W::new(self) + pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { + CLR_ACTIVITY_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/clr_gen_call.rs b/jh7110-vf2-13b-pac/src/i2c3/clr_gen_call.rs index a9ea5af..4a7c5ba 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/clr_gen_call.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/clr_gen_call.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_gen_call` reader - clr_gen_call"] pub type CLR_GEN_CALL_R = crate::FieldReader; #[doc = "Field `clr_gen_call` writer - clr_gen_call"] -pub type CLR_GEN_CALL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_GEN_CALL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] #[must_use] - pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { - CLR_GEN_CALL_W::new(self) + pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { + CLR_GEN_CALL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/clr_intr.rs b/jh7110-vf2-13b-pac/src/i2c3/clr_intr.rs index a7daf57..cf57b09 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/clr_intr.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/clr_intr.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/clr_rd_req.rs b/jh7110-vf2-13b-pac/src/i2c3/clr_rd_req.rs index e275da1..4beae9d 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/clr_rd_req.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/clr_rd_req.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rd_req` reader - clr_rd_req"] pub type CLR_RD_REQ_R = crate::FieldReader; #[doc = "Field `clr_rd_req` writer - clr_rd_req"] -pub type CLR_RD_REQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RD_REQ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] #[must_use] - pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { - CLR_RD_REQ_W::new(self) + pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { + CLR_RD_REQ_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/clr_restart_det.rs b/jh7110-vf2-13b-pac/src/i2c3/clr_restart_det.rs index 5be7f5d..88d193c 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/clr_restart_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/clr_restart_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_restart_det` reader - clr_restart_det"] pub type CLR_RESTART_DET_R = crate::FieldReader; #[doc = "Field `clr_restart_det` writer - clr_restart_det"] -pub type CLR_RESTART_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RESTART_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] #[must_use] - pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { - CLR_RESTART_DET_W::new(self) + pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { + CLR_RESTART_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/clr_rx_done.rs b/jh7110-vf2-13b-pac/src/i2c3/clr_rx_done.rs index 02d83c5..7e14a3f 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/clr_rx_done.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/clr_rx_done.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_done` reader - clr_rx_done"] pub type CLR_RX_DONE_R = crate::FieldReader; #[doc = "Field `clr_rx_done` writer - clr_rx_done"] -pub type CLR_RX_DONE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_DONE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] #[must_use] - pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { - CLR_RX_DONE_W::new(self) + pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { + CLR_RX_DONE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/clr_rx_over.rs b/jh7110-vf2-13b-pac/src/i2c3/clr_rx_over.rs index 6d7ff4e..2302921 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/clr_rx_over.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/clr_rx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_over` reader - clr_rx_over"] pub type CLR_RX_OVER_R = crate::FieldReader; #[doc = "Field `clr_rx_over` writer - clr_rx_over"] -pub type CLR_RX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] #[must_use] - pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { - CLR_RX_OVER_W::new(self) + pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { + CLR_RX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/clr_rx_under.rs b/jh7110-vf2-13b-pac/src/i2c3/clr_rx_under.rs index 4a24f7c..35e15bd 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/clr_rx_under.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/clr_rx_under.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_under` reader - clr_rx_under"] pub type CLR_RX_UNDER_R = crate::FieldReader; #[doc = "Field `clr_rx_under` writer - clr_rx_under"] -pub type CLR_RX_UNDER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_UNDER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] #[must_use] - pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { - CLR_RX_UNDER_W::new(self) + pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { + CLR_RX_UNDER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/clr_start_det.rs b/jh7110-vf2-13b-pac/src/i2c3/clr_start_det.rs index cebc4bc..2314f65 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/clr_start_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/clr_start_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_start_det` reader - clr_start_det"] pub type CLR_START_DET_R = crate::FieldReader; #[doc = "Field `clr_start_det` writer - clr_start_det"] -pub type CLR_START_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_START_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] #[must_use] - pub fn clr_start_det(&mut self) -> CLR_START_DET_W { - CLR_START_DET_W::new(self) + pub fn clr_start_det(&mut self) -> CLR_START_DET_W { + CLR_START_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/clr_stop_det.rs b/jh7110-vf2-13b-pac/src/i2c3/clr_stop_det.rs index 44f39f3..49abcac 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/clr_stop_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/clr_stop_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_stop_det` reader - clr_stop_det"] pub type CLR_STOP_DET_R = crate::FieldReader; #[doc = "Field `clr_stop_det` writer - clr_stop_det"] -pub type CLR_STOP_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_STOP_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] #[must_use] - pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { - CLR_STOP_DET_W::new(self) + pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { + CLR_STOP_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/clr_tx_abrt.rs b/jh7110-vf2-13b-pac/src/i2c3/clr_tx_abrt.rs index 6ac441c..3bc0f6f 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/clr_tx_abrt.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/clr_tx_abrt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_abrt` reader - clr_tx_abrt"] pub type CLR_TX_ABRT_R = crate::FieldReader; #[doc = "Field `clr_tx_abrt` writer - clr_tx_abrt"] -pub type CLR_TX_ABRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_ABRT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] #[must_use] - pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { - CLR_TX_ABRT_W::new(self) + pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { + CLR_TX_ABRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/clr_tx_over.rs b/jh7110-vf2-13b-pac/src/i2c3/clr_tx_over.rs index 2b32b52..a5b6933 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/clr_tx_over.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/clr_tx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_over` reader - clr_tx_over"] pub type CLR_TX_OVER_R = crate::FieldReader; #[doc = "Field `clr_tx_over` writer - clr_tx_over"] -pub type CLR_TX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] #[must_use] - pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { - CLR_TX_OVER_W::new(self) + pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { + CLR_TX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/comp_param_1.rs b/jh7110-vf2-13b-pac/src/i2c3/comp_param_1.rs index 24a22e1..95c5002 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/comp_param_1.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/comp_param_1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/comp_type.rs b/jh7110-vf2-13b-pac/src/i2c3/comp_type.rs index ac916b5..1336c43 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/comp_type.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/comp_type.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/comp_version.rs b/jh7110-vf2-13b-pac/src/i2c3/comp_version.rs index 4be31fa..e8309c8 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/comp_version.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/comp_version.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/con.rs b/jh7110-vf2-13b-pac/src/i2c3/con.rs index 873c534..28aa865 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/con.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/con.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `master` reader - I2C Master Connection - 0: Slave, 1: Master"] pub type MASTER_R = crate::BitReader; #[doc = "Field `master` writer - I2C Master Connection - 0: Slave, 1: Master"] -pub type MASTER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `speed` reader - I2C Speed - 01: Standard, 10: Fast, 11: High"] pub type SPEED_R = crate::FieldReader; #[doc = "Field `speed` writer - I2C Speed - 01: Standard, 10: Fast, 11: High"] -pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `slave_10bitaddr` reader - I2C Slave 10-bit Address - 0: False, 1: True"] pub type SLAVE_10BITADDR_R = crate::BitReader; #[doc = "Field `slave_10bitaddr` writer - I2C Slave 10-bit Address - 0: False, 1: True"] -pub type SLAVE_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_10bitaddr` reader - I2C Master 10-bit Address - 0: False, 1: True"] pub type MASTER_10BITADDR_R = crate::BitReader; #[doc = "Field `master_10bitaddr` writer - I2C Master 10-bit Address - 0: False, 1: True"] -pub type MASTER_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_en` reader - I2C Restart Enable - 0: False, 1: True"] pub type RESTART_EN_R = crate::BitReader; #[doc = "Field `restart_en` writer - I2C Restart Enable - 0: False, 1: True"] -pub type RESTART_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_disable` reader - I2C Slave Disable - 0: False, 1: True"] pub type SLAVE_DISABLE_R = crate::BitReader; #[doc = "Field `slave_disable` writer - I2C Slave Disable - 0: False, 1: True"] -pub type SLAVE_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det_ifaddressed` reader - I2C Stop DET If Addressed - 0: False, 1: True"] pub type STOP_DET_IFADDRESSED_R = crate::BitReader; #[doc = "Field `stop_det_ifaddressed` writer - I2C Stop DET If Addressed - 0: False, 1: True"] -pub type STOP_DET_IFADDRESSED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty_ctrl` reader - I2C TX Empty Control - 0: False, 1: True"] pub type TX_EMPTY_CTRL_R = crate::BitReader; #[doc = "Field `tx_empty_ctrl` writer - I2C TX Empty Control - 0: False, 1: True"] -pub type TX_EMPTY_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_fifo_full_hld_ctrl` reader - I2C RX FIFO Full Hold Control - 0: False, 1: True"] pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; #[doc = "Field `rx_fifo_full_hld_ctrl` writer - I2C RX FIFO Full Hold Control - 0: False, 1: True"] -pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bus_clear_ctrl` reader - I2C Bus Clear Control - 0: False, 1: True"] pub type BUS_CLEAR_CTRL_R = crate::BitReader; #[doc = "Field `bus_clear_ctrl` writer - I2C Bus Clear Control - 0: False, 1: True"] -pub type BUS_CLEAR_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BUS_CLEAR_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] #[must_use] - pub fn master(&mut self) -> MASTER_W { - MASTER_W::new(self) + pub fn master(&mut self) -> MASTER_W { + MASTER_W::new(self, 0) } #[doc = "Bits 1:2 - I2C Speed - 01: Standard, 10: Fast, 11: High"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W { - SPEED_W::new(self) + pub fn speed(&mut self) -> SPEED_W { + SPEED_W::new(self, 1) } #[doc = "Bit 3 - I2C Slave 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { - SLAVE_10BITADDR_W::new(self) + pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { + SLAVE_10BITADDR_W::new(self, 3) } #[doc = "Bit 4 - I2C Master 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { - MASTER_10BITADDR_W::new(self) + pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { + MASTER_10BITADDR_W::new(self, 4) } #[doc = "Bit 5 - I2C Restart Enable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn restart_en(&mut self) -> RESTART_EN_W { - RESTART_EN_W::new(self) + pub fn restart_en(&mut self) -> RESTART_EN_W { + RESTART_EN_W::new(self, 5) } #[doc = "Bit 6 - I2C Slave Disable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { - SLAVE_DISABLE_W::new(self) + pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { + SLAVE_DISABLE_W::new(self, 6) } #[doc = "Bit 7 - I2C Stop DET If Addressed - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { - STOP_DET_IFADDRESSED_W::new(self) + pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { + STOP_DET_IFADDRESSED_W::new(self, 7) } #[doc = "Bit 8 - I2C TX Empty Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { - TX_EMPTY_CTRL_W::new(self) + pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { + TX_EMPTY_CTRL_W::new(self, 8) } #[doc = "Bit 9 - I2C RX FIFO Full Hold Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { - RX_FIFO_FULL_HLD_CTRL_W::new(self) + pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { + RX_FIFO_FULL_HLD_CTRL_W::new(self, 9) } #[doc = "Bit 11 - I2C Bus Clear Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { - BUS_CLEAR_CTRL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { + BUS_CLEAR_CTRL_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/data_cmd.rs b/jh7110-vf2-13b-pac/src/i2c3/data_cmd.rs index cf36408..2b320d4 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/data_cmd.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/data_cmd.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `dat` reader - Data Command Data Byte"] pub type DAT_R = crate::FieldReader; #[doc = "Field `dat` writer - Data Command Data Byte"] -pub type DAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `read` reader - Data Command READ Bit - 0: Write, 1: Read"] pub type READ_R = crate::BitReader; #[doc = "Field `read` writer - Data Command READ Bit - 0: Write, 1: Read"] -pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop` reader - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart` reader - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] pub type RESTART_R = crate::BitReader; #[doc = "Field `restart` writer - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] -pub type RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `first_data_byte` reader - Data Command First Data Byte - 0: False, 1: True"] pub type FIRST_DATA_BYTE_R = crate::BitReader; #[doc = "Field `first_data_byte` writer - Data Command First Data Byte - 0: False, 1: True"] -pub type FIRST_DATA_BYTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIRST_DATA_BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] #[must_use] - pub fn dat(&mut self) -> DAT_W { - DAT_W::new(self) + pub fn dat(&mut self) -> DAT_W { + DAT_W::new(self, 0) } #[doc = "Bit 8 - Data Command READ Bit - 0: Write, 1: Read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W { - READ_W::new(self) + pub fn read(&mut self) -> READ_W { + READ_W::new(self, 8) } #[doc = "Bit 9 - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 9) } #[doc = "Bit 10 - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] #[inline(always)] #[must_use] - pub fn restart(&mut self) -> RESTART_W { - RESTART_W::new(self) + pub fn restart(&mut self) -> RESTART_W { + RESTART_W::new(self, 10) } #[doc = "Bit 11 - Data Command First Data Byte - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { - FIRST_DATA_BYTE_W::new(self) + pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { + FIRST_DATA_BYTE_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/enable.rs b/jh7110-vf2-13b-pac/src/i2c3/enable.rs index c5ca9d7..3629f6b 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/enable.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/enable.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `abort` reader - abort"] pub type ABORT_R = crate::BitReader; #[doc = "Field `abort` writer - abort"] -pub type ABORT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 1 - abort"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 1 - abort"] #[inline(always)] #[must_use] - pub fn abort(&mut self) -> ABORT_W { - ABORT_W::new(self) + pub fn abort(&mut self) -> ABORT_W { + ABORT_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/enable_status.rs b/jh7110-vf2-13b-pac/src/i2c3/enable_status.rs index 2c102a6..8b9b7d3 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/enable_status.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/enable_status.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `activity` reader - activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tfe` reader - tfe"] pub type TFE_R = crate::BitReader; #[doc = "Field `tfe` writer - tfe"] -pub type TFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TFE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfne` reader - rfne"] pub type RFNE_R = crate::BitReader; #[doc = "Field `rfne` writer - rfne"] -pub type RFNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFNE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_activity` reader - master_activity"] pub type MASTER_ACTIVITY_R = crate::BitReader; #[doc = "Field `master_activity` writer - master_activity"] -pub type MASTER_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_activity` reader - slave_activity"] pub type SLAVE_ACTIVITY_R = crate::BitReader; #[doc = "Field `slave_activity` writer - slave_activity"] -pub type SLAVE_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - activity"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 0) } #[doc = "Bit 2 - tfe"] #[inline(always)] #[must_use] - pub fn tfe(&mut self) -> TFE_W { - TFE_W::new(self) + pub fn tfe(&mut self) -> TFE_W { + TFE_W::new(self, 2) } #[doc = "Bit 3 - rfne"] #[inline(always)] #[must_use] - pub fn rfne(&mut self) -> RFNE_W { - RFNE_W::new(self) + pub fn rfne(&mut self) -> RFNE_W { + RFNE_W::new(self, 3) } #[doc = "Bit 5 - master_activity"] #[inline(always)] #[must_use] - pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { - MASTER_ACTIVITY_W::new(self) + pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { + MASTER_ACTIVITY_W::new(self, 5) } #[doc = "Bit 6 - slave_activity"] #[inline(always)] #[must_use] - pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { - SLAVE_ACTIVITY_W::new(self) + pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { + SLAVE_ACTIVITY_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/fs_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c3/fs_scl_hcnt.rs index 9a9fd72..8a4f6d1 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/fs_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/fs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_hcnt` reader - fs_scl_hcnt"] pub type FS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_hcnt` writer - fs_scl_hcnt"] -pub type FS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { - FS_SCL_HCNT_W::new(self) + pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { + FS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/fs_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c3/fs_scl_lcnt.rs index 5e41cd1..4b4dd6b 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/fs_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/fs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_lcnt` reader - fs_scl_lcnt"] pub type FS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_lcnt` writer - fs_scl_lcnt"] -pub type FS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { - FS_SCL_LCNT_W::new(self) + pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { + FS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/hs_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c3/hs_scl_hcnt.rs index fba7f13..9b0a71c 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/hs_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/hs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_hcnt` reader - hs_scl_hcnt"] pub type HS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_hcnt` writer - hs_scl_hcnt"] -pub type HS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { - HS_SCL_HCNT_W::new(self) + pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { + HS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/hs_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c3/hs_scl_lcnt.rs index 9fca7a5..a715282 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/hs_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/hs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_lcnt` reader - hs_scl_lcnt"] pub type HS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_lcnt` writer - hs_scl_lcnt"] -pub type HS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { - HS_SCL_LCNT_W::new(self) + pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { + HS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/intr_mask.rs b/jh7110-vf2-13b-pac/src/i2c3/intr_mask.rs index 20a334f..769b629 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/intr_mask.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/intr_mask.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/intr_stat.rs b/jh7110-vf2-13b-pac/src/i2c3/intr_stat.rs index 2c2ba34..f376c26 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/intr_stat.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/raw_intr_stat.rs b/jh7110-vf2-13b-pac/src/i2c3/raw_intr_stat.rs index af97981..dd5e8e0 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/raw_intr_stat.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/raw_intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/rx_tl.rs b/jh7110-vf2-13b-pac/src/i2c3/rx_tl.rs index 1455a10..f3f39f4 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/rx_tl.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/rx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rx_tl` reader - rx_tl"] pub type RX_TL_R = crate::FieldReader; #[doc = "Field `rx_tl` writer - rx_tl"] -pub type RX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] #[must_use] - pub fn rx_tl(&mut self) -> RX_TL_W { - RX_TL_W::new(self) + pub fn rx_tl(&mut self) -> RX_TL_W { + RX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/rxflr.rs b/jh7110-vf2-13b-pac/src/i2c3/rxflr.rs index 910e254..4dccf5e 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/rxflr.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/rxflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rxflr` reader - rxflr"] pub type RXFLR_R = crate::FieldReader; #[doc = "Field `rxflr` writer - rxflr"] -pub type RXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] #[must_use] - pub fn rxflr(&mut self) -> RXFLR_W { - RXFLR_W::new(self) + pub fn rxflr(&mut self) -> RXFLR_W { + RXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/sar.rs b/jh7110-vf2-13b-pac/src/i2c3/sar.rs index d272e7a..1af6273 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/sar.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/sar.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Slave address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Slave address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Slave address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Slave address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; impl R { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Slave address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/sda_hold.rs b/jh7110-vf2-13b-pac/src/i2c3/sda_hold.rs index 82ceac5..d5d7512 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/sda_hold.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/sda_hold.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sda_hold` reader - sda_hold"] pub type SDA_HOLD_R = crate::FieldReader; #[doc = "Field `sda_hold` writer - sda_hold"] -pub type SDA_HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SDA_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] #[must_use] - pub fn sda_hold(&mut self) -> SDA_HOLD_W { - SDA_HOLD_W::new(self) + pub fn sda_hold(&mut self) -> SDA_HOLD_W { + SDA_HOLD_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/ss_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c3/ss_scl_hcnt.rs index 33736c7..77d7ea0 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/ss_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/ss_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_hcnt` reader - ss_scl_hcnt"] pub type SS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_hcnt` writer - ss_scl_hcnt"] -pub type SS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { - SS_SCL_HCNT_W::new(self) + pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { + SS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/ss_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c3/ss_scl_lcnt.rs index ce22b5d..8208747 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/ss_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/ss_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_lcnt` reader - ss_scl_lcnt"] pub type SS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_lcnt` writer - ss_scl_lcnt"] -pub type SS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { - SS_SCL_LCNT_W::new(self) + pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { + SS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/status.rs b/jh7110-vf2-13b-pac/src/i2c3/status.rs index 9489e49..1b7ab67 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/status.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/tar.rs b/jh7110-vf2-13b-pac/src/i2c3/tar.rs index 9fedc71..3044a8c 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/tar.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/tar.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Target address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Target address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Target address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Target address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; #[doc = "Field `mode` reader - Target addressing mode - 0: 7-bit, 1: 10-bit"] pub type MODE_R = crate::BitReader; #[doc = "Field `mode` writer - Target addressing mode - 0: 7-bit, 1: 10-bit"] -pub type MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Target address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } #[doc = "Bit 12 - Target addressing mode - 0: 7-bit, 1: 10-bit"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W { - MODE_W::new(self) + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 12) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/tx_abrt_source.rs b/jh7110-vf2-13b-pac/src/i2c3/tx_abrt_source.rs index 6f31813..c4fdf1a 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/tx_abrt_source.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/tx_abrt_source.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/tx_tl.rs b/jh7110-vf2-13b-pac/src/i2c3/tx_tl.rs index 84a1734..b0e6c64 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/tx_tl.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/tx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `tx_tl` reader - tx_tl"] pub type TX_TL_R = crate::FieldReader; #[doc = "Field `tx_tl` writer - tx_tl"] -pub type TX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] #[must_use] - pub fn tx_tl(&mut self) -> TX_TL_W { - TX_TL_W::new(self) + pub fn tx_tl(&mut self) -> TX_TL_W { + TX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c3/txflr.rs b/jh7110-vf2-13b-pac/src/i2c3/txflr.rs index b8e5fdd..5ca351d 100644 --- a/jh7110-vf2-13b-pac/src/i2c3/txflr.rs +++ b/jh7110-vf2-13b-pac/src/i2c3/txflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `txflr` reader - txflr"] pub type TXFLR_R = crate::FieldReader; #[doc = "Field `txflr` writer - txflr"] -pub type TXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - txflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - txflr"] #[inline(always)] #[must_use] - pub fn txflr(&mut self) -> TXFLR_W { - TXFLR_W::new(self) + pub fn txflr(&mut self) -> TXFLR_W { + TXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4.rs b/jh7110-vf2-13b-pac/src/i2c4.rs index d0fe76a..fdffe28 100644 --- a/jh7110-vf2-13b-pac/src/i2c4.rs +++ b/jh7110-vf2-13b-pac/src/i2c4.rs @@ -1,266 +1,416 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + con: CON, + tar: TAR, + sar: SAR, + _reserved3: [u8; 0x04], + data_cmd: DATA_CMD, + ss_scl_hcnt: SS_SCL_HCNT, + ss_scl_lcnt: SS_SCL_LCNT, + fs_scl_hcnt: FS_SCL_HCNT, + fs_scl_lcnt: FS_SCL_LCNT, + hs_scl_hcnt: HS_SCL_HCNT, + hs_scl_lcnt: HS_SCL_LCNT, + intr_stat: INTR_STAT, + intr_mask: INTR_MASK, + raw_intr_stat: RAW_INTR_STAT, + rx_tl: RX_TL, + tx_tl: TX_TL, + clr_intr: CLR_INTR, + clr_rx_under: CLR_RX_UNDER, + clr_rx_over: CLR_RX_OVER, + clr_tx_over: CLR_TX_OVER, + clr_rd_req: CLR_RD_REQ, + clr_tx_abrt: CLR_TX_ABRT, + clr_rx_done: CLR_RX_DONE, + clr_activity: CLR_ACTIVITY, + clr_stop_det: CLR_STOP_DET, + clr_start_det: CLR_START_DET, + clr_gen_call: CLR_GEN_CALL, + enable: ENABLE, + status: STATUS, + txflr: TXFLR, + rxflr: RXFLR, + sda_hold: SDA_HOLD, + tx_abrt_source: TX_ABRT_SOURCE, + _reserved32: [u8; 0x18], + enable_status: ENABLE_STATUS, + _reserved33: [u8; 0x08], + clr_restart_det: CLR_RESTART_DET, + _reserved34: [u8; 0x48], + comp_param_1: COMP_PARAM_1, + comp_version: COMP_VERSION, + comp_type: COMP_TYPE, +} +impl RegisterBlock { #[doc = "0x00 - DesignWare I2C CON"] - pub con: CON, + #[inline(always)] + pub const fn con(&self) -> &CON { + &self.con + } #[doc = "0x04 - DesignWare I2C TAR"] - pub tar: TAR, + #[inline(always)] + pub const fn tar(&self) -> &TAR { + &self.tar + } #[doc = "0x08 - DesignWare I2C SAR"] - pub sar: SAR, - _reserved3: [u8; 0x04], + #[inline(always)] + pub const fn sar(&self) -> &SAR { + &self.sar + } #[doc = "0x10 - DesignWare I2C Data Command"] - pub data_cmd: DATA_CMD, + #[inline(always)] + pub const fn data_cmd(&self) -> &DATA_CMD { + &self.data_cmd + } #[doc = "0x14 - DesignWare I2C SS SCL HCNT"] - pub ss_scl_hcnt: SS_SCL_HCNT, + #[inline(always)] + pub const fn ss_scl_hcnt(&self) -> &SS_SCL_HCNT { + &self.ss_scl_hcnt + } #[doc = "0x18 - DesignWare I2C SS SCL LCNT"] - pub ss_scl_lcnt: SS_SCL_LCNT, + #[inline(always)] + pub const fn ss_scl_lcnt(&self) -> &SS_SCL_LCNT { + &self.ss_scl_lcnt + } #[doc = "0x1c - DesignWare I2C FS SCL HCNT"] - pub fs_scl_hcnt: FS_SCL_HCNT, + #[inline(always)] + pub const fn fs_scl_hcnt(&self) -> &FS_SCL_HCNT { + &self.fs_scl_hcnt + } #[doc = "0x20 - DesignWare I2C FS SCL LCNT"] - pub fs_scl_lcnt: FS_SCL_LCNT, + #[inline(always)] + pub const fn fs_scl_lcnt(&self) -> &FS_SCL_LCNT { + &self.fs_scl_lcnt + } #[doc = "0x24 - DesignWare I2C HS SCL HCNT"] - pub hs_scl_hcnt: HS_SCL_HCNT, + #[inline(always)] + pub const fn hs_scl_hcnt(&self) -> &HS_SCL_HCNT { + &self.hs_scl_hcnt + } #[doc = "0x28 - DesignWare I2C HS SCL LCNT"] - pub hs_scl_lcnt: HS_SCL_LCNT, + #[inline(always)] + pub const fn hs_scl_lcnt(&self) -> &HS_SCL_LCNT { + &self.hs_scl_lcnt + } #[doc = "0x2c - DesignWare I2C Interrupt Status"] - pub intr_stat: INTR_STAT, + #[inline(always)] + pub const fn intr_stat(&self) -> &INTR_STAT { + &self.intr_stat + } #[doc = "0x30 - DesignWare I2C Interrupt Mask"] - pub intr_mask: INTR_MASK, + #[inline(always)] + pub const fn intr_mask(&self) -> &INTR_MASK { + &self.intr_mask + } #[doc = "0x34 - DesignWare I2C Raw Interrupt Status"] - pub raw_intr_stat: RAW_INTR_STAT, + #[inline(always)] + pub const fn raw_intr_stat(&self) -> &RAW_INTR_STAT { + &self.raw_intr_stat + } #[doc = "0x38 - DesignWare I2C RX TL"] - pub rx_tl: RX_TL, + #[inline(always)] + pub const fn rx_tl(&self) -> &RX_TL { + &self.rx_tl + } #[doc = "0x3c - DesignWare I2C TX TL"] - pub tx_tl: TX_TL, + #[inline(always)] + pub const fn tx_tl(&self) -> &TX_TL { + &self.tx_tl + } #[doc = "0x40 - DesignWare I2C Clear Interrrupt"] - pub clr_intr: CLR_INTR, + #[inline(always)] + pub const fn clr_intr(&self) -> &CLR_INTR { + &self.clr_intr + } #[doc = "0x44 - DesignWare I2C Clear RX Underrun"] - pub clr_rx_under: CLR_RX_UNDER, + #[inline(always)] + pub const fn clr_rx_under(&self) -> &CLR_RX_UNDER { + &self.clr_rx_under + } #[doc = "0x48 - DesignWare I2C Clear RX Overrun"] - pub clr_rx_over: CLR_RX_OVER, + #[inline(always)] + pub const fn clr_rx_over(&self) -> &CLR_RX_OVER { + &self.clr_rx_over + } #[doc = "0x4c - DesignWare I2C Clear TX Overrun"] - pub clr_tx_over: CLR_TX_OVER, + #[inline(always)] + pub const fn clr_tx_over(&self) -> &CLR_TX_OVER { + &self.clr_tx_over + } #[doc = "0x50 - DesignWare I2C Clear Read Request"] - pub clr_rd_req: CLR_RD_REQ, + #[inline(always)] + pub const fn clr_rd_req(&self) -> &CLR_RD_REQ { + &self.clr_rd_req + } #[doc = "0x54 - DesignWare I2C Clear TX Abort"] - pub clr_tx_abrt: CLR_TX_ABRT, + #[inline(always)] + pub const fn clr_tx_abrt(&self) -> &CLR_TX_ABRT { + &self.clr_tx_abrt + } #[doc = "0x58 - DesignWare I2C Clear RX Done"] - pub clr_rx_done: CLR_RX_DONE, + #[inline(always)] + pub const fn clr_rx_done(&self) -> &CLR_RX_DONE { + &self.clr_rx_done + } #[doc = "0x5c - DesignWare I2C Clear Activity"] - pub clr_activity: CLR_ACTIVITY, + #[inline(always)] + pub const fn clr_activity(&self) -> &CLR_ACTIVITY { + &self.clr_activity + } #[doc = "0x60 - DesignWare I2C Clear Stop DET"] - pub clr_stop_det: CLR_STOP_DET, + #[inline(always)] + pub const fn clr_stop_det(&self) -> &CLR_STOP_DET { + &self.clr_stop_det + } #[doc = "0x64 - DesignWare I2C Clear Start DET"] - pub clr_start_det: CLR_START_DET, + #[inline(always)] + pub const fn clr_start_det(&self) -> &CLR_START_DET { + &self.clr_start_det + } #[doc = "0x68 - DesignWare I2C Clear General Call"] - pub clr_gen_call: CLR_GEN_CALL, + #[inline(always)] + pub const fn clr_gen_call(&self) -> &CLR_GEN_CALL { + &self.clr_gen_call + } #[doc = "0x6c - DesignWare I2C Enable"] - pub enable: ENABLE, + #[inline(always)] + pub const fn enable(&self) -> &ENABLE { + &self.enable + } #[doc = "0x70 - DesignWare I2C Status"] - pub status: STATUS, + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } #[doc = "0x74 - DesignWare I2C TX Failure"] - pub txflr: TXFLR, + #[inline(always)] + pub const fn txflr(&self) -> &TXFLR { + &self.txflr + } #[doc = "0x78 - DesignWare I2C RX Failure"] - pub rxflr: RXFLR, + #[inline(always)] + pub const fn rxflr(&self) -> &RXFLR { + &self.rxflr + } #[doc = "0x7c - DesignWare I2C SDA Hold"] - pub sda_hold: SDA_HOLD, + #[inline(always)] + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold + } #[doc = "0x80 - DesignWare I2C TX Abort Source"] - pub tx_abrt_source: TX_ABRT_SOURCE, - _reserved32: [u8; 0x18], + #[inline(always)] + pub const fn tx_abrt_source(&self) -> &TX_ABRT_SOURCE { + &self.tx_abrt_source + } #[doc = "0x9c - DesignWare I2C Enable Status"] - pub enable_status: ENABLE_STATUS, - _reserved33: [u8; 0x08], + #[inline(always)] + pub const fn enable_status(&self) -> &ENABLE_STATUS { + &self.enable_status + } #[doc = "0xa8 - DesignWare I2C Clear Restart DET"] - pub clr_restart_det: CLR_RESTART_DET, - _reserved34: [u8; 0x48], + #[inline(always)] + pub const fn clr_restart_det(&self) -> &CLR_RESTART_DET { + &self.clr_restart_det + } #[doc = "0xf4 - DesignWare I2C Compatibility Parameter 1"] - pub comp_param_1: COMP_PARAM_1, + #[inline(always)] + pub const fn comp_param_1(&self) -> &COMP_PARAM_1 { + &self.comp_param_1 + } #[doc = "0xf8 - DesignWare I2C Compatibility Version"] - pub comp_version: COMP_VERSION, + #[inline(always)] + pub const fn comp_version(&self) -> &COMP_VERSION { + &self.comp_version + } #[doc = "0xfc - DesignWare I2C Compatibility Type"] - pub comp_type: COMP_TYPE, + #[inline(always)] + pub const fn comp_type(&self) -> &COMP_TYPE { + &self.comp_type + } } -#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`con`] +#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@con`] module"] pub type CON = crate::Reg; #[doc = "DesignWare I2C CON"] pub mod con; -#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tar`] +#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar`] module"] pub type TAR = crate::Reg; #[doc = "DesignWare I2C TAR"] pub mod tar; -#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sar`] +#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`] module"] pub type SAR = crate::Reg; #[doc = "DesignWare I2C SAR"] pub mod sar; -#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`data_cmd`] +#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_cmd`] module"] pub type DATA_CMD = crate::Reg; #[doc = "DesignWare I2C Data Command"] pub mod data_cmd; -#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_hcnt`] +#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_hcnt`] module"] pub type SS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL HCNT"] pub mod ss_scl_hcnt; -#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_lcnt`] +#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_lcnt`] module"] pub type SS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL LCNT"] pub mod ss_scl_lcnt; -#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_hcnt`] +#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_hcnt`] module"] pub type FS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL HCNT"] pub mod fs_scl_hcnt; -#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_lcnt`] +#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_lcnt`] module"] pub type FS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL LCNT"] pub mod fs_scl_lcnt; -#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_hcnt`] +#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_hcnt`] module"] pub type HS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL HCNT"] pub mod hs_scl_hcnt; -#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_lcnt`] +#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_lcnt`] module"] pub type HS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL LCNT"] pub mod hs_scl_lcnt; -#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_stat`] +#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"] pub type INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Interrupt Status"] pub mod intr_stat; -#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_mask`] +#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mask`] module"] pub type INTR_MASK = crate::Reg; #[doc = "DesignWare I2C Interrupt Mask"] pub mod intr_mask; -#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`raw_intr_stat`] +#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"] pub type RAW_INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Raw Interrupt Status"] pub mod raw_intr_stat; -#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rx_tl`] +#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tl`] module"] pub type RX_TL = crate::Reg; #[doc = "DesignWare I2C RX TL"] pub mod rx_tl; -#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_tl`] +#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_tl`] module"] pub type TX_TL = crate::Reg; #[doc = "DesignWare I2C TX TL"] pub mod tx_tl; -#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_intr`] +#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_intr`] module"] pub type CLR_INTR = crate::Reg; #[doc = "DesignWare I2C Clear Interrrupt"] pub mod clr_intr; -#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_under`] +#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_under`] module"] pub type CLR_RX_UNDER = crate::Reg; #[doc = "DesignWare I2C Clear RX Underrun"] pub mod clr_rx_under; -#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_over`] +#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_over`] module"] pub type CLR_RX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear RX Overrun"] pub mod clr_rx_over; -#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_over`] +#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_over`] module"] pub type CLR_TX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear TX Overrun"] pub mod clr_tx_over; -#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rd_req`] +#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rd_req`] module"] pub type CLR_RD_REQ = crate::Reg; #[doc = "DesignWare I2C Clear Read Request"] pub mod clr_rd_req; -#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_abrt`] +#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_abrt`] module"] pub type CLR_TX_ABRT = crate::Reg; #[doc = "DesignWare I2C Clear TX Abort"] pub mod clr_tx_abrt; -#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_done`] +#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_done`] module"] pub type CLR_RX_DONE = crate::Reg; #[doc = "DesignWare I2C Clear RX Done"] pub mod clr_rx_done; -#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_activity`] +#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_activity`] module"] pub type CLR_ACTIVITY = crate::Reg; #[doc = "DesignWare I2C Clear Activity"] pub mod clr_activity; -#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_stop_det`] +#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_stop_det`] module"] pub type CLR_STOP_DET = crate::Reg; #[doc = "DesignWare I2C Clear Stop DET"] pub mod clr_stop_det; -#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_start_det`] +#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_start_det`] module"] pub type CLR_START_DET = crate::Reg; #[doc = "DesignWare I2C Clear Start DET"] pub mod clr_start_det; -#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_gen_call`] +#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_gen_call`] module"] pub type CLR_GEN_CALL = crate::Reg; #[doc = "DesignWare I2C Clear General Call"] pub mod clr_gen_call; -#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable`] +#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] pub type ENABLE = crate::Reg; #[doc = "DesignWare I2C Enable"] pub mod enable; -#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`status`] +#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] pub type STATUS = crate::Reg; #[doc = "DesignWare I2C Status"] pub mod status; -#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txflr`] +#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txflr`] module"] pub type TXFLR = crate::Reg; #[doc = "DesignWare I2C TX Failure"] pub mod txflr; -#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxflr`] +#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxflr`] module"] pub type RXFLR = crate::Reg; #[doc = "DesignWare I2C RX Failure"] pub mod rxflr; -#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sda_hold`] +#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] pub type SDA_HOLD = crate::Reg; #[doc = "DesignWare I2C SDA Hold"] pub mod sda_hold; -#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_abrt_source`] +#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_abrt_source`] module"] pub type TX_ABRT_SOURCE = crate::Reg; #[doc = "DesignWare I2C TX Abort Source"] pub mod tx_abrt_source; -#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_status`] +#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_status`] module"] pub type ENABLE_STATUS = crate::Reg; #[doc = "DesignWare I2C Enable Status"] pub mod enable_status; -#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_restart_det`] +#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_restart_det`] module"] pub type CLR_RESTART_DET = crate::Reg; #[doc = "DesignWare I2C Clear Restart DET"] pub mod clr_restart_det; -#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_param_1`] +#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_param_1`] module"] pub type COMP_PARAM_1 = crate::Reg; #[doc = "DesignWare I2C Compatibility Parameter 1"] pub mod comp_param_1; -#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_version`] +#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_version`] module"] pub type COMP_VERSION = crate::Reg; #[doc = "DesignWare I2C Compatibility Version"] pub mod comp_version; -#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_type`] +#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_type`] module"] pub type COMP_TYPE = crate::Reg; #[doc = "DesignWare I2C Compatibility Type"] diff --git a/jh7110-vf2-13b-pac/src/i2c4/clr_activity.rs b/jh7110-vf2-13b-pac/src/i2c4/clr_activity.rs index d26bb80..1ee2297 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/clr_activity.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/clr_activity.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_activity` reader - clr_activity"] pub type CLR_ACTIVITY_R = crate::FieldReader; #[doc = "Field `clr_activity` writer - clr_activity"] -pub type CLR_ACTIVITY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_ACTIVITY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] #[must_use] - pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { - CLR_ACTIVITY_W::new(self) + pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { + CLR_ACTIVITY_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/clr_gen_call.rs b/jh7110-vf2-13b-pac/src/i2c4/clr_gen_call.rs index a9ea5af..4a7c5ba 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/clr_gen_call.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/clr_gen_call.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_gen_call` reader - clr_gen_call"] pub type CLR_GEN_CALL_R = crate::FieldReader; #[doc = "Field `clr_gen_call` writer - clr_gen_call"] -pub type CLR_GEN_CALL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_GEN_CALL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] #[must_use] - pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { - CLR_GEN_CALL_W::new(self) + pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { + CLR_GEN_CALL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/clr_intr.rs b/jh7110-vf2-13b-pac/src/i2c4/clr_intr.rs index a7daf57..cf57b09 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/clr_intr.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/clr_intr.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/clr_rd_req.rs b/jh7110-vf2-13b-pac/src/i2c4/clr_rd_req.rs index e275da1..4beae9d 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/clr_rd_req.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/clr_rd_req.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rd_req` reader - clr_rd_req"] pub type CLR_RD_REQ_R = crate::FieldReader; #[doc = "Field `clr_rd_req` writer - clr_rd_req"] -pub type CLR_RD_REQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RD_REQ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] #[must_use] - pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { - CLR_RD_REQ_W::new(self) + pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { + CLR_RD_REQ_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/clr_restart_det.rs b/jh7110-vf2-13b-pac/src/i2c4/clr_restart_det.rs index 5be7f5d..88d193c 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/clr_restart_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/clr_restart_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_restart_det` reader - clr_restart_det"] pub type CLR_RESTART_DET_R = crate::FieldReader; #[doc = "Field `clr_restart_det` writer - clr_restart_det"] -pub type CLR_RESTART_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RESTART_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] #[must_use] - pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { - CLR_RESTART_DET_W::new(self) + pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { + CLR_RESTART_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/clr_rx_done.rs b/jh7110-vf2-13b-pac/src/i2c4/clr_rx_done.rs index 02d83c5..7e14a3f 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/clr_rx_done.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/clr_rx_done.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_done` reader - clr_rx_done"] pub type CLR_RX_DONE_R = crate::FieldReader; #[doc = "Field `clr_rx_done` writer - clr_rx_done"] -pub type CLR_RX_DONE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_DONE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] #[must_use] - pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { - CLR_RX_DONE_W::new(self) + pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { + CLR_RX_DONE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/clr_rx_over.rs b/jh7110-vf2-13b-pac/src/i2c4/clr_rx_over.rs index 6d7ff4e..2302921 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/clr_rx_over.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/clr_rx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_over` reader - clr_rx_over"] pub type CLR_RX_OVER_R = crate::FieldReader; #[doc = "Field `clr_rx_over` writer - clr_rx_over"] -pub type CLR_RX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] #[must_use] - pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { - CLR_RX_OVER_W::new(self) + pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { + CLR_RX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/clr_rx_under.rs b/jh7110-vf2-13b-pac/src/i2c4/clr_rx_under.rs index 4a24f7c..35e15bd 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/clr_rx_under.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/clr_rx_under.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_under` reader - clr_rx_under"] pub type CLR_RX_UNDER_R = crate::FieldReader; #[doc = "Field `clr_rx_under` writer - clr_rx_under"] -pub type CLR_RX_UNDER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_UNDER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] #[must_use] - pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { - CLR_RX_UNDER_W::new(self) + pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { + CLR_RX_UNDER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/clr_start_det.rs b/jh7110-vf2-13b-pac/src/i2c4/clr_start_det.rs index cebc4bc..2314f65 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/clr_start_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/clr_start_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_start_det` reader - clr_start_det"] pub type CLR_START_DET_R = crate::FieldReader; #[doc = "Field `clr_start_det` writer - clr_start_det"] -pub type CLR_START_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_START_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] #[must_use] - pub fn clr_start_det(&mut self) -> CLR_START_DET_W { - CLR_START_DET_W::new(self) + pub fn clr_start_det(&mut self) -> CLR_START_DET_W { + CLR_START_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/clr_stop_det.rs b/jh7110-vf2-13b-pac/src/i2c4/clr_stop_det.rs index 44f39f3..49abcac 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/clr_stop_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/clr_stop_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_stop_det` reader - clr_stop_det"] pub type CLR_STOP_DET_R = crate::FieldReader; #[doc = "Field `clr_stop_det` writer - clr_stop_det"] -pub type CLR_STOP_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_STOP_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] #[must_use] - pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { - CLR_STOP_DET_W::new(self) + pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { + CLR_STOP_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/clr_tx_abrt.rs b/jh7110-vf2-13b-pac/src/i2c4/clr_tx_abrt.rs index 6ac441c..3bc0f6f 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/clr_tx_abrt.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/clr_tx_abrt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_abrt` reader - clr_tx_abrt"] pub type CLR_TX_ABRT_R = crate::FieldReader; #[doc = "Field `clr_tx_abrt` writer - clr_tx_abrt"] -pub type CLR_TX_ABRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_ABRT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] #[must_use] - pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { - CLR_TX_ABRT_W::new(self) + pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { + CLR_TX_ABRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/clr_tx_over.rs b/jh7110-vf2-13b-pac/src/i2c4/clr_tx_over.rs index 2b32b52..a5b6933 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/clr_tx_over.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/clr_tx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_over` reader - clr_tx_over"] pub type CLR_TX_OVER_R = crate::FieldReader; #[doc = "Field `clr_tx_over` writer - clr_tx_over"] -pub type CLR_TX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] #[must_use] - pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { - CLR_TX_OVER_W::new(self) + pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { + CLR_TX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/comp_param_1.rs b/jh7110-vf2-13b-pac/src/i2c4/comp_param_1.rs index 24a22e1..95c5002 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/comp_param_1.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/comp_param_1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/comp_type.rs b/jh7110-vf2-13b-pac/src/i2c4/comp_type.rs index ac916b5..1336c43 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/comp_type.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/comp_type.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/comp_version.rs b/jh7110-vf2-13b-pac/src/i2c4/comp_version.rs index 4be31fa..e8309c8 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/comp_version.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/comp_version.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/con.rs b/jh7110-vf2-13b-pac/src/i2c4/con.rs index 873c534..28aa865 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/con.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/con.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `master` reader - I2C Master Connection - 0: Slave, 1: Master"] pub type MASTER_R = crate::BitReader; #[doc = "Field `master` writer - I2C Master Connection - 0: Slave, 1: Master"] -pub type MASTER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `speed` reader - I2C Speed - 01: Standard, 10: Fast, 11: High"] pub type SPEED_R = crate::FieldReader; #[doc = "Field `speed` writer - I2C Speed - 01: Standard, 10: Fast, 11: High"] -pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `slave_10bitaddr` reader - I2C Slave 10-bit Address - 0: False, 1: True"] pub type SLAVE_10BITADDR_R = crate::BitReader; #[doc = "Field `slave_10bitaddr` writer - I2C Slave 10-bit Address - 0: False, 1: True"] -pub type SLAVE_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_10bitaddr` reader - I2C Master 10-bit Address - 0: False, 1: True"] pub type MASTER_10BITADDR_R = crate::BitReader; #[doc = "Field `master_10bitaddr` writer - I2C Master 10-bit Address - 0: False, 1: True"] -pub type MASTER_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_en` reader - I2C Restart Enable - 0: False, 1: True"] pub type RESTART_EN_R = crate::BitReader; #[doc = "Field `restart_en` writer - I2C Restart Enable - 0: False, 1: True"] -pub type RESTART_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_disable` reader - I2C Slave Disable - 0: False, 1: True"] pub type SLAVE_DISABLE_R = crate::BitReader; #[doc = "Field `slave_disable` writer - I2C Slave Disable - 0: False, 1: True"] -pub type SLAVE_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det_ifaddressed` reader - I2C Stop DET If Addressed - 0: False, 1: True"] pub type STOP_DET_IFADDRESSED_R = crate::BitReader; #[doc = "Field `stop_det_ifaddressed` writer - I2C Stop DET If Addressed - 0: False, 1: True"] -pub type STOP_DET_IFADDRESSED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty_ctrl` reader - I2C TX Empty Control - 0: False, 1: True"] pub type TX_EMPTY_CTRL_R = crate::BitReader; #[doc = "Field `tx_empty_ctrl` writer - I2C TX Empty Control - 0: False, 1: True"] -pub type TX_EMPTY_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_fifo_full_hld_ctrl` reader - I2C RX FIFO Full Hold Control - 0: False, 1: True"] pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; #[doc = "Field `rx_fifo_full_hld_ctrl` writer - I2C RX FIFO Full Hold Control - 0: False, 1: True"] -pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bus_clear_ctrl` reader - I2C Bus Clear Control - 0: False, 1: True"] pub type BUS_CLEAR_CTRL_R = crate::BitReader; #[doc = "Field `bus_clear_ctrl` writer - I2C Bus Clear Control - 0: False, 1: True"] -pub type BUS_CLEAR_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BUS_CLEAR_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] #[must_use] - pub fn master(&mut self) -> MASTER_W { - MASTER_W::new(self) + pub fn master(&mut self) -> MASTER_W { + MASTER_W::new(self, 0) } #[doc = "Bits 1:2 - I2C Speed - 01: Standard, 10: Fast, 11: High"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W { - SPEED_W::new(self) + pub fn speed(&mut self) -> SPEED_W { + SPEED_W::new(self, 1) } #[doc = "Bit 3 - I2C Slave 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { - SLAVE_10BITADDR_W::new(self) + pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { + SLAVE_10BITADDR_W::new(self, 3) } #[doc = "Bit 4 - I2C Master 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { - MASTER_10BITADDR_W::new(self) + pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { + MASTER_10BITADDR_W::new(self, 4) } #[doc = "Bit 5 - I2C Restart Enable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn restart_en(&mut self) -> RESTART_EN_W { - RESTART_EN_W::new(self) + pub fn restart_en(&mut self) -> RESTART_EN_W { + RESTART_EN_W::new(self, 5) } #[doc = "Bit 6 - I2C Slave Disable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { - SLAVE_DISABLE_W::new(self) + pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { + SLAVE_DISABLE_W::new(self, 6) } #[doc = "Bit 7 - I2C Stop DET If Addressed - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { - STOP_DET_IFADDRESSED_W::new(self) + pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { + STOP_DET_IFADDRESSED_W::new(self, 7) } #[doc = "Bit 8 - I2C TX Empty Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { - TX_EMPTY_CTRL_W::new(self) + pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { + TX_EMPTY_CTRL_W::new(self, 8) } #[doc = "Bit 9 - I2C RX FIFO Full Hold Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { - RX_FIFO_FULL_HLD_CTRL_W::new(self) + pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { + RX_FIFO_FULL_HLD_CTRL_W::new(self, 9) } #[doc = "Bit 11 - I2C Bus Clear Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { - BUS_CLEAR_CTRL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { + BUS_CLEAR_CTRL_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/data_cmd.rs b/jh7110-vf2-13b-pac/src/i2c4/data_cmd.rs index cf36408..2b320d4 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/data_cmd.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/data_cmd.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `dat` reader - Data Command Data Byte"] pub type DAT_R = crate::FieldReader; #[doc = "Field `dat` writer - Data Command Data Byte"] -pub type DAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `read` reader - Data Command READ Bit - 0: Write, 1: Read"] pub type READ_R = crate::BitReader; #[doc = "Field `read` writer - Data Command READ Bit - 0: Write, 1: Read"] -pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop` reader - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart` reader - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] pub type RESTART_R = crate::BitReader; #[doc = "Field `restart` writer - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] -pub type RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `first_data_byte` reader - Data Command First Data Byte - 0: False, 1: True"] pub type FIRST_DATA_BYTE_R = crate::BitReader; #[doc = "Field `first_data_byte` writer - Data Command First Data Byte - 0: False, 1: True"] -pub type FIRST_DATA_BYTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIRST_DATA_BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] #[must_use] - pub fn dat(&mut self) -> DAT_W { - DAT_W::new(self) + pub fn dat(&mut self) -> DAT_W { + DAT_W::new(self, 0) } #[doc = "Bit 8 - Data Command READ Bit - 0: Write, 1: Read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W { - READ_W::new(self) + pub fn read(&mut self) -> READ_W { + READ_W::new(self, 8) } #[doc = "Bit 9 - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 9) } #[doc = "Bit 10 - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] #[inline(always)] #[must_use] - pub fn restart(&mut self) -> RESTART_W { - RESTART_W::new(self) + pub fn restart(&mut self) -> RESTART_W { + RESTART_W::new(self, 10) } #[doc = "Bit 11 - Data Command First Data Byte - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { - FIRST_DATA_BYTE_W::new(self) + pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { + FIRST_DATA_BYTE_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/enable.rs b/jh7110-vf2-13b-pac/src/i2c4/enable.rs index c5ca9d7..3629f6b 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/enable.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/enable.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `abort` reader - abort"] pub type ABORT_R = crate::BitReader; #[doc = "Field `abort` writer - abort"] -pub type ABORT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 1 - abort"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 1 - abort"] #[inline(always)] #[must_use] - pub fn abort(&mut self) -> ABORT_W { - ABORT_W::new(self) + pub fn abort(&mut self) -> ABORT_W { + ABORT_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/enable_status.rs b/jh7110-vf2-13b-pac/src/i2c4/enable_status.rs index 2c102a6..8b9b7d3 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/enable_status.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/enable_status.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `activity` reader - activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tfe` reader - tfe"] pub type TFE_R = crate::BitReader; #[doc = "Field `tfe` writer - tfe"] -pub type TFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TFE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfne` reader - rfne"] pub type RFNE_R = crate::BitReader; #[doc = "Field `rfne` writer - rfne"] -pub type RFNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFNE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_activity` reader - master_activity"] pub type MASTER_ACTIVITY_R = crate::BitReader; #[doc = "Field `master_activity` writer - master_activity"] -pub type MASTER_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_activity` reader - slave_activity"] pub type SLAVE_ACTIVITY_R = crate::BitReader; #[doc = "Field `slave_activity` writer - slave_activity"] -pub type SLAVE_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - activity"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 0) } #[doc = "Bit 2 - tfe"] #[inline(always)] #[must_use] - pub fn tfe(&mut self) -> TFE_W { - TFE_W::new(self) + pub fn tfe(&mut self) -> TFE_W { + TFE_W::new(self, 2) } #[doc = "Bit 3 - rfne"] #[inline(always)] #[must_use] - pub fn rfne(&mut self) -> RFNE_W { - RFNE_W::new(self) + pub fn rfne(&mut self) -> RFNE_W { + RFNE_W::new(self, 3) } #[doc = "Bit 5 - master_activity"] #[inline(always)] #[must_use] - pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { - MASTER_ACTIVITY_W::new(self) + pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { + MASTER_ACTIVITY_W::new(self, 5) } #[doc = "Bit 6 - slave_activity"] #[inline(always)] #[must_use] - pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { - SLAVE_ACTIVITY_W::new(self) + pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { + SLAVE_ACTIVITY_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/fs_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c4/fs_scl_hcnt.rs index 9a9fd72..8a4f6d1 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/fs_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/fs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_hcnt` reader - fs_scl_hcnt"] pub type FS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_hcnt` writer - fs_scl_hcnt"] -pub type FS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { - FS_SCL_HCNT_W::new(self) + pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { + FS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/fs_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c4/fs_scl_lcnt.rs index 5e41cd1..4b4dd6b 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/fs_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/fs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_lcnt` reader - fs_scl_lcnt"] pub type FS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_lcnt` writer - fs_scl_lcnt"] -pub type FS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { - FS_SCL_LCNT_W::new(self) + pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { + FS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/hs_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c4/hs_scl_hcnt.rs index fba7f13..9b0a71c 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/hs_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/hs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_hcnt` reader - hs_scl_hcnt"] pub type HS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_hcnt` writer - hs_scl_hcnt"] -pub type HS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { - HS_SCL_HCNT_W::new(self) + pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { + HS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/hs_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c4/hs_scl_lcnt.rs index 9fca7a5..a715282 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/hs_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/hs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_lcnt` reader - hs_scl_lcnt"] pub type HS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_lcnt` writer - hs_scl_lcnt"] -pub type HS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { - HS_SCL_LCNT_W::new(self) + pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { + HS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/intr_mask.rs b/jh7110-vf2-13b-pac/src/i2c4/intr_mask.rs index 20a334f..769b629 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/intr_mask.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/intr_mask.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/intr_stat.rs b/jh7110-vf2-13b-pac/src/i2c4/intr_stat.rs index 2c2ba34..f376c26 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/intr_stat.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/raw_intr_stat.rs b/jh7110-vf2-13b-pac/src/i2c4/raw_intr_stat.rs index af97981..dd5e8e0 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/raw_intr_stat.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/raw_intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/rx_tl.rs b/jh7110-vf2-13b-pac/src/i2c4/rx_tl.rs index 1455a10..f3f39f4 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/rx_tl.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/rx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rx_tl` reader - rx_tl"] pub type RX_TL_R = crate::FieldReader; #[doc = "Field `rx_tl` writer - rx_tl"] -pub type RX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] #[must_use] - pub fn rx_tl(&mut self) -> RX_TL_W { - RX_TL_W::new(self) + pub fn rx_tl(&mut self) -> RX_TL_W { + RX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/rxflr.rs b/jh7110-vf2-13b-pac/src/i2c4/rxflr.rs index 910e254..4dccf5e 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/rxflr.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/rxflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rxflr` reader - rxflr"] pub type RXFLR_R = crate::FieldReader; #[doc = "Field `rxflr` writer - rxflr"] -pub type RXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] #[must_use] - pub fn rxflr(&mut self) -> RXFLR_W { - RXFLR_W::new(self) + pub fn rxflr(&mut self) -> RXFLR_W { + RXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/sar.rs b/jh7110-vf2-13b-pac/src/i2c4/sar.rs index d272e7a..1af6273 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/sar.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/sar.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Slave address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Slave address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Slave address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Slave address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; impl R { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Slave address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/sda_hold.rs b/jh7110-vf2-13b-pac/src/i2c4/sda_hold.rs index 82ceac5..d5d7512 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/sda_hold.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/sda_hold.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sda_hold` reader - sda_hold"] pub type SDA_HOLD_R = crate::FieldReader; #[doc = "Field `sda_hold` writer - sda_hold"] -pub type SDA_HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SDA_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] #[must_use] - pub fn sda_hold(&mut self) -> SDA_HOLD_W { - SDA_HOLD_W::new(self) + pub fn sda_hold(&mut self) -> SDA_HOLD_W { + SDA_HOLD_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/ss_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c4/ss_scl_hcnt.rs index 33736c7..77d7ea0 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/ss_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/ss_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_hcnt` reader - ss_scl_hcnt"] pub type SS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_hcnt` writer - ss_scl_hcnt"] -pub type SS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { - SS_SCL_HCNT_W::new(self) + pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { + SS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/ss_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c4/ss_scl_lcnt.rs index ce22b5d..8208747 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/ss_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/ss_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_lcnt` reader - ss_scl_lcnt"] pub type SS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_lcnt` writer - ss_scl_lcnt"] -pub type SS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { - SS_SCL_LCNT_W::new(self) + pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { + SS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/status.rs b/jh7110-vf2-13b-pac/src/i2c4/status.rs index 9489e49..1b7ab67 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/status.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/tar.rs b/jh7110-vf2-13b-pac/src/i2c4/tar.rs index 9fedc71..3044a8c 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/tar.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/tar.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Target address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Target address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Target address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Target address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; #[doc = "Field `mode` reader - Target addressing mode - 0: 7-bit, 1: 10-bit"] pub type MODE_R = crate::BitReader; #[doc = "Field `mode` writer - Target addressing mode - 0: 7-bit, 1: 10-bit"] -pub type MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Target address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } #[doc = "Bit 12 - Target addressing mode - 0: 7-bit, 1: 10-bit"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W { - MODE_W::new(self) + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 12) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/tx_abrt_source.rs b/jh7110-vf2-13b-pac/src/i2c4/tx_abrt_source.rs index 6f31813..c4fdf1a 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/tx_abrt_source.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/tx_abrt_source.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/tx_tl.rs b/jh7110-vf2-13b-pac/src/i2c4/tx_tl.rs index 84a1734..b0e6c64 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/tx_tl.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/tx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `tx_tl` reader - tx_tl"] pub type TX_TL_R = crate::FieldReader; #[doc = "Field `tx_tl` writer - tx_tl"] -pub type TX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] #[must_use] - pub fn tx_tl(&mut self) -> TX_TL_W { - TX_TL_W::new(self) + pub fn tx_tl(&mut self) -> TX_TL_W { + TX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c4/txflr.rs b/jh7110-vf2-13b-pac/src/i2c4/txflr.rs index b8e5fdd..5ca351d 100644 --- a/jh7110-vf2-13b-pac/src/i2c4/txflr.rs +++ b/jh7110-vf2-13b-pac/src/i2c4/txflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `txflr` reader - txflr"] pub type TXFLR_R = crate::FieldReader; #[doc = "Field `txflr` writer - txflr"] -pub type TXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - txflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - txflr"] #[inline(always)] #[must_use] - pub fn txflr(&mut self) -> TXFLR_W { - TXFLR_W::new(self) + pub fn txflr(&mut self) -> TXFLR_W { + TXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5.rs b/jh7110-vf2-13b-pac/src/i2c5.rs index d0fe76a..fdffe28 100644 --- a/jh7110-vf2-13b-pac/src/i2c5.rs +++ b/jh7110-vf2-13b-pac/src/i2c5.rs @@ -1,266 +1,416 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + con: CON, + tar: TAR, + sar: SAR, + _reserved3: [u8; 0x04], + data_cmd: DATA_CMD, + ss_scl_hcnt: SS_SCL_HCNT, + ss_scl_lcnt: SS_SCL_LCNT, + fs_scl_hcnt: FS_SCL_HCNT, + fs_scl_lcnt: FS_SCL_LCNT, + hs_scl_hcnt: HS_SCL_HCNT, + hs_scl_lcnt: HS_SCL_LCNT, + intr_stat: INTR_STAT, + intr_mask: INTR_MASK, + raw_intr_stat: RAW_INTR_STAT, + rx_tl: RX_TL, + tx_tl: TX_TL, + clr_intr: CLR_INTR, + clr_rx_under: CLR_RX_UNDER, + clr_rx_over: CLR_RX_OVER, + clr_tx_over: CLR_TX_OVER, + clr_rd_req: CLR_RD_REQ, + clr_tx_abrt: CLR_TX_ABRT, + clr_rx_done: CLR_RX_DONE, + clr_activity: CLR_ACTIVITY, + clr_stop_det: CLR_STOP_DET, + clr_start_det: CLR_START_DET, + clr_gen_call: CLR_GEN_CALL, + enable: ENABLE, + status: STATUS, + txflr: TXFLR, + rxflr: RXFLR, + sda_hold: SDA_HOLD, + tx_abrt_source: TX_ABRT_SOURCE, + _reserved32: [u8; 0x18], + enable_status: ENABLE_STATUS, + _reserved33: [u8; 0x08], + clr_restart_det: CLR_RESTART_DET, + _reserved34: [u8; 0x48], + comp_param_1: COMP_PARAM_1, + comp_version: COMP_VERSION, + comp_type: COMP_TYPE, +} +impl RegisterBlock { #[doc = "0x00 - DesignWare I2C CON"] - pub con: CON, + #[inline(always)] + pub const fn con(&self) -> &CON { + &self.con + } #[doc = "0x04 - DesignWare I2C TAR"] - pub tar: TAR, + #[inline(always)] + pub const fn tar(&self) -> &TAR { + &self.tar + } #[doc = "0x08 - DesignWare I2C SAR"] - pub sar: SAR, - _reserved3: [u8; 0x04], + #[inline(always)] + pub const fn sar(&self) -> &SAR { + &self.sar + } #[doc = "0x10 - DesignWare I2C Data Command"] - pub data_cmd: DATA_CMD, + #[inline(always)] + pub const fn data_cmd(&self) -> &DATA_CMD { + &self.data_cmd + } #[doc = "0x14 - DesignWare I2C SS SCL HCNT"] - pub ss_scl_hcnt: SS_SCL_HCNT, + #[inline(always)] + pub const fn ss_scl_hcnt(&self) -> &SS_SCL_HCNT { + &self.ss_scl_hcnt + } #[doc = "0x18 - DesignWare I2C SS SCL LCNT"] - pub ss_scl_lcnt: SS_SCL_LCNT, + #[inline(always)] + pub const fn ss_scl_lcnt(&self) -> &SS_SCL_LCNT { + &self.ss_scl_lcnt + } #[doc = "0x1c - DesignWare I2C FS SCL HCNT"] - pub fs_scl_hcnt: FS_SCL_HCNT, + #[inline(always)] + pub const fn fs_scl_hcnt(&self) -> &FS_SCL_HCNT { + &self.fs_scl_hcnt + } #[doc = "0x20 - DesignWare I2C FS SCL LCNT"] - pub fs_scl_lcnt: FS_SCL_LCNT, + #[inline(always)] + pub const fn fs_scl_lcnt(&self) -> &FS_SCL_LCNT { + &self.fs_scl_lcnt + } #[doc = "0x24 - DesignWare I2C HS SCL HCNT"] - pub hs_scl_hcnt: HS_SCL_HCNT, + #[inline(always)] + pub const fn hs_scl_hcnt(&self) -> &HS_SCL_HCNT { + &self.hs_scl_hcnt + } #[doc = "0x28 - DesignWare I2C HS SCL LCNT"] - pub hs_scl_lcnt: HS_SCL_LCNT, + #[inline(always)] + pub const fn hs_scl_lcnt(&self) -> &HS_SCL_LCNT { + &self.hs_scl_lcnt + } #[doc = "0x2c - DesignWare I2C Interrupt Status"] - pub intr_stat: INTR_STAT, + #[inline(always)] + pub const fn intr_stat(&self) -> &INTR_STAT { + &self.intr_stat + } #[doc = "0x30 - DesignWare I2C Interrupt Mask"] - pub intr_mask: INTR_MASK, + #[inline(always)] + pub const fn intr_mask(&self) -> &INTR_MASK { + &self.intr_mask + } #[doc = "0x34 - DesignWare I2C Raw Interrupt Status"] - pub raw_intr_stat: RAW_INTR_STAT, + #[inline(always)] + pub const fn raw_intr_stat(&self) -> &RAW_INTR_STAT { + &self.raw_intr_stat + } #[doc = "0x38 - DesignWare I2C RX TL"] - pub rx_tl: RX_TL, + #[inline(always)] + pub const fn rx_tl(&self) -> &RX_TL { + &self.rx_tl + } #[doc = "0x3c - DesignWare I2C TX TL"] - pub tx_tl: TX_TL, + #[inline(always)] + pub const fn tx_tl(&self) -> &TX_TL { + &self.tx_tl + } #[doc = "0x40 - DesignWare I2C Clear Interrrupt"] - pub clr_intr: CLR_INTR, + #[inline(always)] + pub const fn clr_intr(&self) -> &CLR_INTR { + &self.clr_intr + } #[doc = "0x44 - DesignWare I2C Clear RX Underrun"] - pub clr_rx_under: CLR_RX_UNDER, + #[inline(always)] + pub const fn clr_rx_under(&self) -> &CLR_RX_UNDER { + &self.clr_rx_under + } #[doc = "0x48 - DesignWare I2C Clear RX Overrun"] - pub clr_rx_over: CLR_RX_OVER, + #[inline(always)] + pub const fn clr_rx_over(&self) -> &CLR_RX_OVER { + &self.clr_rx_over + } #[doc = "0x4c - DesignWare I2C Clear TX Overrun"] - pub clr_tx_over: CLR_TX_OVER, + #[inline(always)] + pub const fn clr_tx_over(&self) -> &CLR_TX_OVER { + &self.clr_tx_over + } #[doc = "0x50 - DesignWare I2C Clear Read Request"] - pub clr_rd_req: CLR_RD_REQ, + #[inline(always)] + pub const fn clr_rd_req(&self) -> &CLR_RD_REQ { + &self.clr_rd_req + } #[doc = "0x54 - DesignWare I2C Clear TX Abort"] - pub clr_tx_abrt: CLR_TX_ABRT, + #[inline(always)] + pub const fn clr_tx_abrt(&self) -> &CLR_TX_ABRT { + &self.clr_tx_abrt + } #[doc = "0x58 - DesignWare I2C Clear RX Done"] - pub clr_rx_done: CLR_RX_DONE, + #[inline(always)] + pub const fn clr_rx_done(&self) -> &CLR_RX_DONE { + &self.clr_rx_done + } #[doc = "0x5c - DesignWare I2C Clear Activity"] - pub clr_activity: CLR_ACTIVITY, + #[inline(always)] + pub const fn clr_activity(&self) -> &CLR_ACTIVITY { + &self.clr_activity + } #[doc = "0x60 - DesignWare I2C Clear Stop DET"] - pub clr_stop_det: CLR_STOP_DET, + #[inline(always)] + pub const fn clr_stop_det(&self) -> &CLR_STOP_DET { + &self.clr_stop_det + } #[doc = "0x64 - DesignWare I2C Clear Start DET"] - pub clr_start_det: CLR_START_DET, + #[inline(always)] + pub const fn clr_start_det(&self) -> &CLR_START_DET { + &self.clr_start_det + } #[doc = "0x68 - DesignWare I2C Clear General Call"] - pub clr_gen_call: CLR_GEN_CALL, + #[inline(always)] + pub const fn clr_gen_call(&self) -> &CLR_GEN_CALL { + &self.clr_gen_call + } #[doc = "0x6c - DesignWare I2C Enable"] - pub enable: ENABLE, + #[inline(always)] + pub const fn enable(&self) -> &ENABLE { + &self.enable + } #[doc = "0x70 - DesignWare I2C Status"] - pub status: STATUS, + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } #[doc = "0x74 - DesignWare I2C TX Failure"] - pub txflr: TXFLR, + #[inline(always)] + pub const fn txflr(&self) -> &TXFLR { + &self.txflr + } #[doc = "0x78 - DesignWare I2C RX Failure"] - pub rxflr: RXFLR, + #[inline(always)] + pub const fn rxflr(&self) -> &RXFLR { + &self.rxflr + } #[doc = "0x7c - DesignWare I2C SDA Hold"] - pub sda_hold: SDA_HOLD, + #[inline(always)] + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold + } #[doc = "0x80 - DesignWare I2C TX Abort Source"] - pub tx_abrt_source: TX_ABRT_SOURCE, - _reserved32: [u8; 0x18], + #[inline(always)] + pub const fn tx_abrt_source(&self) -> &TX_ABRT_SOURCE { + &self.tx_abrt_source + } #[doc = "0x9c - DesignWare I2C Enable Status"] - pub enable_status: ENABLE_STATUS, - _reserved33: [u8; 0x08], + #[inline(always)] + pub const fn enable_status(&self) -> &ENABLE_STATUS { + &self.enable_status + } #[doc = "0xa8 - DesignWare I2C Clear Restart DET"] - pub clr_restart_det: CLR_RESTART_DET, - _reserved34: [u8; 0x48], + #[inline(always)] + pub const fn clr_restart_det(&self) -> &CLR_RESTART_DET { + &self.clr_restart_det + } #[doc = "0xf4 - DesignWare I2C Compatibility Parameter 1"] - pub comp_param_1: COMP_PARAM_1, + #[inline(always)] + pub const fn comp_param_1(&self) -> &COMP_PARAM_1 { + &self.comp_param_1 + } #[doc = "0xf8 - DesignWare I2C Compatibility Version"] - pub comp_version: COMP_VERSION, + #[inline(always)] + pub const fn comp_version(&self) -> &COMP_VERSION { + &self.comp_version + } #[doc = "0xfc - DesignWare I2C Compatibility Type"] - pub comp_type: COMP_TYPE, + #[inline(always)] + pub const fn comp_type(&self) -> &COMP_TYPE { + &self.comp_type + } } -#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`con`] +#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@con`] module"] pub type CON = crate::Reg; #[doc = "DesignWare I2C CON"] pub mod con; -#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tar`] +#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar`] module"] pub type TAR = crate::Reg; #[doc = "DesignWare I2C TAR"] pub mod tar; -#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sar`] +#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`] module"] pub type SAR = crate::Reg; #[doc = "DesignWare I2C SAR"] pub mod sar; -#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`data_cmd`] +#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_cmd`] module"] pub type DATA_CMD = crate::Reg; #[doc = "DesignWare I2C Data Command"] pub mod data_cmd; -#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_hcnt`] +#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_hcnt`] module"] pub type SS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL HCNT"] pub mod ss_scl_hcnt; -#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_lcnt`] +#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_lcnt`] module"] pub type SS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL LCNT"] pub mod ss_scl_lcnt; -#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_hcnt`] +#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_hcnt`] module"] pub type FS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL HCNT"] pub mod fs_scl_hcnt; -#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_lcnt`] +#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_lcnt`] module"] pub type FS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL LCNT"] pub mod fs_scl_lcnt; -#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_hcnt`] +#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_hcnt`] module"] pub type HS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL HCNT"] pub mod hs_scl_hcnt; -#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_lcnt`] +#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_lcnt`] module"] pub type HS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL LCNT"] pub mod hs_scl_lcnt; -#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_stat`] +#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"] pub type INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Interrupt Status"] pub mod intr_stat; -#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_mask`] +#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mask`] module"] pub type INTR_MASK = crate::Reg; #[doc = "DesignWare I2C Interrupt Mask"] pub mod intr_mask; -#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`raw_intr_stat`] +#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"] pub type RAW_INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Raw Interrupt Status"] pub mod raw_intr_stat; -#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rx_tl`] +#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tl`] module"] pub type RX_TL = crate::Reg; #[doc = "DesignWare I2C RX TL"] pub mod rx_tl; -#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_tl`] +#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_tl`] module"] pub type TX_TL = crate::Reg; #[doc = "DesignWare I2C TX TL"] pub mod tx_tl; -#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_intr`] +#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_intr`] module"] pub type CLR_INTR = crate::Reg; #[doc = "DesignWare I2C Clear Interrrupt"] pub mod clr_intr; -#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_under`] +#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_under`] module"] pub type CLR_RX_UNDER = crate::Reg; #[doc = "DesignWare I2C Clear RX Underrun"] pub mod clr_rx_under; -#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_over`] +#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_over`] module"] pub type CLR_RX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear RX Overrun"] pub mod clr_rx_over; -#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_over`] +#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_over`] module"] pub type CLR_TX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear TX Overrun"] pub mod clr_tx_over; -#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rd_req`] +#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rd_req`] module"] pub type CLR_RD_REQ = crate::Reg; #[doc = "DesignWare I2C Clear Read Request"] pub mod clr_rd_req; -#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_abrt`] +#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_abrt`] module"] pub type CLR_TX_ABRT = crate::Reg; #[doc = "DesignWare I2C Clear TX Abort"] pub mod clr_tx_abrt; -#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_done`] +#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_done`] module"] pub type CLR_RX_DONE = crate::Reg; #[doc = "DesignWare I2C Clear RX Done"] pub mod clr_rx_done; -#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_activity`] +#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_activity`] module"] pub type CLR_ACTIVITY = crate::Reg; #[doc = "DesignWare I2C Clear Activity"] pub mod clr_activity; -#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_stop_det`] +#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_stop_det`] module"] pub type CLR_STOP_DET = crate::Reg; #[doc = "DesignWare I2C Clear Stop DET"] pub mod clr_stop_det; -#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_start_det`] +#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_start_det`] module"] pub type CLR_START_DET = crate::Reg; #[doc = "DesignWare I2C Clear Start DET"] pub mod clr_start_det; -#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_gen_call`] +#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_gen_call`] module"] pub type CLR_GEN_CALL = crate::Reg; #[doc = "DesignWare I2C Clear General Call"] pub mod clr_gen_call; -#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable`] +#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] pub type ENABLE = crate::Reg; #[doc = "DesignWare I2C Enable"] pub mod enable; -#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`status`] +#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] pub type STATUS = crate::Reg; #[doc = "DesignWare I2C Status"] pub mod status; -#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txflr`] +#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txflr`] module"] pub type TXFLR = crate::Reg; #[doc = "DesignWare I2C TX Failure"] pub mod txflr; -#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxflr`] +#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxflr`] module"] pub type RXFLR = crate::Reg; #[doc = "DesignWare I2C RX Failure"] pub mod rxflr; -#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sda_hold`] +#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] pub type SDA_HOLD = crate::Reg; #[doc = "DesignWare I2C SDA Hold"] pub mod sda_hold; -#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_abrt_source`] +#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_abrt_source`] module"] pub type TX_ABRT_SOURCE = crate::Reg; #[doc = "DesignWare I2C TX Abort Source"] pub mod tx_abrt_source; -#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_status`] +#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_status`] module"] pub type ENABLE_STATUS = crate::Reg; #[doc = "DesignWare I2C Enable Status"] pub mod enable_status; -#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_restart_det`] +#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_restart_det`] module"] pub type CLR_RESTART_DET = crate::Reg; #[doc = "DesignWare I2C Clear Restart DET"] pub mod clr_restart_det; -#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_param_1`] +#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_param_1`] module"] pub type COMP_PARAM_1 = crate::Reg; #[doc = "DesignWare I2C Compatibility Parameter 1"] pub mod comp_param_1; -#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_version`] +#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_version`] module"] pub type COMP_VERSION = crate::Reg; #[doc = "DesignWare I2C Compatibility Version"] pub mod comp_version; -#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_type`] +#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_type`] module"] pub type COMP_TYPE = crate::Reg; #[doc = "DesignWare I2C Compatibility Type"] diff --git a/jh7110-vf2-13b-pac/src/i2c5/clr_activity.rs b/jh7110-vf2-13b-pac/src/i2c5/clr_activity.rs index d26bb80..1ee2297 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/clr_activity.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/clr_activity.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_activity` reader - clr_activity"] pub type CLR_ACTIVITY_R = crate::FieldReader; #[doc = "Field `clr_activity` writer - clr_activity"] -pub type CLR_ACTIVITY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_ACTIVITY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] #[must_use] - pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { - CLR_ACTIVITY_W::new(self) + pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { + CLR_ACTIVITY_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/clr_gen_call.rs b/jh7110-vf2-13b-pac/src/i2c5/clr_gen_call.rs index a9ea5af..4a7c5ba 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/clr_gen_call.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/clr_gen_call.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_gen_call` reader - clr_gen_call"] pub type CLR_GEN_CALL_R = crate::FieldReader; #[doc = "Field `clr_gen_call` writer - clr_gen_call"] -pub type CLR_GEN_CALL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_GEN_CALL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] #[must_use] - pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { - CLR_GEN_CALL_W::new(self) + pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { + CLR_GEN_CALL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/clr_intr.rs b/jh7110-vf2-13b-pac/src/i2c5/clr_intr.rs index a7daf57..cf57b09 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/clr_intr.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/clr_intr.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/clr_rd_req.rs b/jh7110-vf2-13b-pac/src/i2c5/clr_rd_req.rs index e275da1..4beae9d 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/clr_rd_req.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/clr_rd_req.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rd_req` reader - clr_rd_req"] pub type CLR_RD_REQ_R = crate::FieldReader; #[doc = "Field `clr_rd_req` writer - clr_rd_req"] -pub type CLR_RD_REQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RD_REQ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] #[must_use] - pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { - CLR_RD_REQ_W::new(self) + pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { + CLR_RD_REQ_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/clr_restart_det.rs b/jh7110-vf2-13b-pac/src/i2c5/clr_restart_det.rs index 5be7f5d..88d193c 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/clr_restart_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/clr_restart_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_restart_det` reader - clr_restart_det"] pub type CLR_RESTART_DET_R = crate::FieldReader; #[doc = "Field `clr_restart_det` writer - clr_restart_det"] -pub type CLR_RESTART_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RESTART_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] #[must_use] - pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { - CLR_RESTART_DET_W::new(self) + pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { + CLR_RESTART_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/clr_rx_done.rs b/jh7110-vf2-13b-pac/src/i2c5/clr_rx_done.rs index 02d83c5..7e14a3f 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/clr_rx_done.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/clr_rx_done.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_done` reader - clr_rx_done"] pub type CLR_RX_DONE_R = crate::FieldReader; #[doc = "Field `clr_rx_done` writer - clr_rx_done"] -pub type CLR_RX_DONE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_DONE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] #[must_use] - pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { - CLR_RX_DONE_W::new(self) + pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { + CLR_RX_DONE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/clr_rx_over.rs b/jh7110-vf2-13b-pac/src/i2c5/clr_rx_over.rs index 6d7ff4e..2302921 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/clr_rx_over.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/clr_rx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_over` reader - clr_rx_over"] pub type CLR_RX_OVER_R = crate::FieldReader; #[doc = "Field `clr_rx_over` writer - clr_rx_over"] -pub type CLR_RX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] #[must_use] - pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { - CLR_RX_OVER_W::new(self) + pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { + CLR_RX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/clr_rx_under.rs b/jh7110-vf2-13b-pac/src/i2c5/clr_rx_under.rs index 4a24f7c..35e15bd 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/clr_rx_under.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/clr_rx_under.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_under` reader - clr_rx_under"] pub type CLR_RX_UNDER_R = crate::FieldReader; #[doc = "Field `clr_rx_under` writer - clr_rx_under"] -pub type CLR_RX_UNDER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_UNDER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] #[must_use] - pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { - CLR_RX_UNDER_W::new(self) + pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { + CLR_RX_UNDER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/clr_start_det.rs b/jh7110-vf2-13b-pac/src/i2c5/clr_start_det.rs index cebc4bc..2314f65 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/clr_start_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/clr_start_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_start_det` reader - clr_start_det"] pub type CLR_START_DET_R = crate::FieldReader; #[doc = "Field `clr_start_det` writer - clr_start_det"] -pub type CLR_START_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_START_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] #[must_use] - pub fn clr_start_det(&mut self) -> CLR_START_DET_W { - CLR_START_DET_W::new(self) + pub fn clr_start_det(&mut self) -> CLR_START_DET_W { + CLR_START_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/clr_stop_det.rs b/jh7110-vf2-13b-pac/src/i2c5/clr_stop_det.rs index 44f39f3..49abcac 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/clr_stop_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/clr_stop_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_stop_det` reader - clr_stop_det"] pub type CLR_STOP_DET_R = crate::FieldReader; #[doc = "Field `clr_stop_det` writer - clr_stop_det"] -pub type CLR_STOP_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_STOP_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] #[must_use] - pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { - CLR_STOP_DET_W::new(self) + pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { + CLR_STOP_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/clr_tx_abrt.rs b/jh7110-vf2-13b-pac/src/i2c5/clr_tx_abrt.rs index 6ac441c..3bc0f6f 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/clr_tx_abrt.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/clr_tx_abrt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_abrt` reader - clr_tx_abrt"] pub type CLR_TX_ABRT_R = crate::FieldReader; #[doc = "Field `clr_tx_abrt` writer - clr_tx_abrt"] -pub type CLR_TX_ABRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_ABRT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] #[must_use] - pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { - CLR_TX_ABRT_W::new(self) + pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { + CLR_TX_ABRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/clr_tx_over.rs b/jh7110-vf2-13b-pac/src/i2c5/clr_tx_over.rs index 2b32b52..a5b6933 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/clr_tx_over.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/clr_tx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_over` reader - clr_tx_over"] pub type CLR_TX_OVER_R = crate::FieldReader; #[doc = "Field `clr_tx_over` writer - clr_tx_over"] -pub type CLR_TX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] #[must_use] - pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { - CLR_TX_OVER_W::new(self) + pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { + CLR_TX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/comp_param_1.rs b/jh7110-vf2-13b-pac/src/i2c5/comp_param_1.rs index 24a22e1..95c5002 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/comp_param_1.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/comp_param_1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/comp_type.rs b/jh7110-vf2-13b-pac/src/i2c5/comp_type.rs index ac916b5..1336c43 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/comp_type.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/comp_type.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/comp_version.rs b/jh7110-vf2-13b-pac/src/i2c5/comp_version.rs index 4be31fa..e8309c8 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/comp_version.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/comp_version.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/con.rs b/jh7110-vf2-13b-pac/src/i2c5/con.rs index 873c534..28aa865 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/con.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/con.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `master` reader - I2C Master Connection - 0: Slave, 1: Master"] pub type MASTER_R = crate::BitReader; #[doc = "Field `master` writer - I2C Master Connection - 0: Slave, 1: Master"] -pub type MASTER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `speed` reader - I2C Speed - 01: Standard, 10: Fast, 11: High"] pub type SPEED_R = crate::FieldReader; #[doc = "Field `speed` writer - I2C Speed - 01: Standard, 10: Fast, 11: High"] -pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `slave_10bitaddr` reader - I2C Slave 10-bit Address - 0: False, 1: True"] pub type SLAVE_10BITADDR_R = crate::BitReader; #[doc = "Field `slave_10bitaddr` writer - I2C Slave 10-bit Address - 0: False, 1: True"] -pub type SLAVE_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_10bitaddr` reader - I2C Master 10-bit Address - 0: False, 1: True"] pub type MASTER_10BITADDR_R = crate::BitReader; #[doc = "Field `master_10bitaddr` writer - I2C Master 10-bit Address - 0: False, 1: True"] -pub type MASTER_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_en` reader - I2C Restart Enable - 0: False, 1: True"] pub type RESTART_EN_R = crate::BitReader; #[doc = "Field `restart_en` writer - I2C Restart Enable - 0: False, 1: True"] -pub type RESTART_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_disable` reader - I2C Slave Disable - 0: False, 1: True"] pub type SLAVE_DISABLE_R = crate::BitReader; #[doc = "Field `slave_disable` writer - I2C Slave Disable - 0: False, 1: True"] -pub type SLAVE_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det_ifaddressed` reader - I2C Stop DET If Addressed - 0: False, 1: True"] pub type STOP_DET_IFADDRESSED_R = crate::BitReader; #[doc = "Field `stop_det_ifaddressed` writer - I2C Stop DET If Addressed - 0: False, 1: True"] -pub type STOP_DET_IFADDRESSED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty_ctrl` reader - I2C TX Empty Control - 0: False, 1: True"] pub type TX_EMPTY_CTRL_R = crate::BitReader; #[doc = "Field `tx_empty_ctrl` writer - I2C TX Empty Control - 0: False, 1: True"] -pub type TX_EMPTY_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_fifo_full_hld_ctrl` reader - I2C RX FIFO Full Hold Control - 0: False, 1: True"] pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; #[doc = "Field `rx_fifo_full_hld_ctrl` writer - I2C RX FIFO Full Hold Control - 0: False, 1: True"] -pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bus_clear_ctrl` reader - I2C Bus Clear Control - 0: False, 1: True"] pub type BUS_CLEAR_CTRL_R = crate::BitReader; #[doc = "Field `bus_clear_ctrl` writer - I2C Bus Clear Control - 0: False, 1: True"] -pub type BUS_CLEAR_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BUS_CLEAR_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] #[must_use] - pub fn master(&mut self) -> MASTER_W { - MASTER_W::new(self) + pub fn master(&mut self) -> MASTER_W { + MASTER_W::new(self, 0) } #[doc = "Bits 1:2 - I2C Speed - 01: Standard, 10: Fast, 11: High"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W { - SPEED_W::new(self) + pub fn speed(&mut self) -> SPEED_W { + SPEED_W::new(self, 1) } #[doc = "Bit 3 - I2C Slave 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { - SLAVE_10BITADDR_W::new(self) + pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { + SLAVE_10BITADDR_W::new(self, 3) } #[doc = "Bit 4 - I2C Master 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { - MASTER_10BITADDR_W::new(self) + pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { + MASTER_10BITADDR_W::new(self, 4) } #[doc = "Bit 5 - I2C Restart Enable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn restart_en(&mut self) -> RESTART_EN_W { - RESTART_EN_W::new(self) + pub fn restart_en(&mut self) -> RESTART_EN_W { + RESTART_EN_W::new(self, 5) } #[doc = "Bit 6 - I2C Slave Disable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { - SLAVE_DISABLE_W::new(self) + pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { + SLAVE_DISABLE_W::new(self, 6) } #[doc = "Bit 7 - I2C Stop DET If Addressed - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { - STOP_DET_IFADDRESSED_W::new(self) + pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { + STOP_DET_IFADDRESSED_W::new(self, 7) } #[doc = "Bit 8 - I2C TX Empty Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { - TX_EMPTY_CTRL_W::new(self) + pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { + TX_EMPTY_CTRL_W::new(self, 8) } #[doc = "Bit 9 - I2C RX FIFO Full Hold Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { - RX_FIFO_FULL_HLD_CTRL_W::new(self) + pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { + RX_FIFO_FULL_HLD_CTRL_W::new(self, 9) } #[doc = "Bit 11 - I2C Bus Clear Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { - BUS_CLEAR_CTRL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { + BUS_CLEAR_CTRL_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/data_cmd.rs b/jh7110-vf2-13b-pac/src/i2c5/data_cmd.rs index cf36408..2b320d4 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/data_cmd.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/data_cmd.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `dat` reader - Data Command Data Byte"] pub type DAT_R = crate::FieldReader; #[doc = "Field `dat` writer - Data Command Data Byte"] -pub type DAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `read` reader - Data Command READ Bit - 0: Write, 1: Read"] pub type READ_R = crate::BitReader; #[doc = "Field `read` writer - Data Command READ Bit - 0: Write, 1: Read"] -pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop` reader - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart` reader - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] pub type RESTART_R = crate::BitReader; #[doc = "Field `restart` writer - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] -pub type RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `first_data_byte` reader - Data Command First Data Byte - 0: False, 1: True"] pub type FIRST_DATA_BYTE_R = crate::BitReader; #[doc = "Field `first_data_byte` writer - Data Command First Data Byte - 0: False, 1: True"] -pub type FIRST_DATA_BYTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIRST_DATA_BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] #[must_use] - pub fn dat(&mut self) -> DAT_W { - DAT_W::new(self) + pub fn dat(&mut self) -> DAT_W { + DAT_W::new(self, 0) } #[doc = "Bit 8 - Data Command READ Bit - 0: Write, 1: Read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W { - READ_W::new(self) + pub fn read(&mut self) -> READ_W { + READ_W::new(self, 8) } #[doc = "Bit 9 - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 9) } #[doc = "Bit 10 - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] #[inline(always)] #[must_use] - pub fn restart(&mut self) -> RESTART_W { - RESTART_W::new(self) + pub fn restart(&mut self) -> RESTART_W { + RESTART_W::new(self, 10) } #[doc = "Bit 11 - Data Command First Data Byte - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { - FIRST_DATA_BYTE_W::new(self) + pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { + FIRST_DATA_BYTE_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/enable.rs b/jh7110-vf2-13b-pac/src/i2c5/enable.rs index c5ca9d7..3629f6b 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/enable.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/enable.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `abort` reader - abort"] pub type ABORT_R = crate::BitReader; #[doc = "Field `abort` writer - abort"] -pub type ABORT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 1 - abort"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 1 - abort"] #[inline(always)] #[must_use] - pub fn abort(&mut self) -> ABORT_W { - ABORT_W::new(self) + pub fn abort(&mut self) -> ABORT_W { + ABORT_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/enable_status.rs b/jh7110-vf2-13b-pac/src/i2c5/enable_status.rs index 2c102a6..8b9b7d3 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/enable_status.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/enable_status.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `activity` reader - activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tfe` reader - tfe"] pub type TFE_R = crate::BitReader; #[doc = "Field `tfe` writer - tfe"] -pub type TFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TFE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfne` reader - rfne"] pub type RFNE_R = crate::BitReader; #[doc = "Field `rfne` writer - rfne"] -pub type RFNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFNE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_activity` reader - master_activity"] pub type MASTER_ACTIVITY_R = crate::BitReader; #[doc = "Field `master_activity` writer - master_activity"] -pub type MASTER_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_activity` reader - slave_activity"] pub type SLAVE_ACTIVITY_R = crate::BitReader; #[doc = "Field `slave_activity` writer - slave_activity"] -pub type SLAVE_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - activity"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 0) } #[doc = "Bit 2 - tfe"] #[inline(always)] #[must_use] - pub fn tfe(&mut self) -> TFE_W { - TFE_W::new(self) + pub fn tfe(&mut self) -> TFE_W { + TFE_W::new(self, 2) } #[doc = "Bit 3 - rfne"] #[inline(always)] #[must_use] - pub fn rfne(&mut self) -> RFNE_W { - RFNE_W::new(self) + pub fn rfne(&mut self) -> RFNE_W { + RFNE_W::new(self, 3) } #[doc = "Bit 5 - master_activity"] #[inline(always)] #[must_use] - pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { - MASTER_ACTIVITY_W::new(self) + pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { + MASTER_ACTIVITY_W::new(self, 5) } #[doc = "Bit 6 - slave_activity"] #[inline(always)] #[must_use] - pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { - SLAVE_ACTIVITY_W::new(self) + pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { + SLAVE_ACTIVITY_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/fs_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c5/fs_scl_hcnt.rs index 9a9fd72..8a4f6d1 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/fs_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/fs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_hcnt` reader - fs_scl_hcnt"] pub type FS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_hcnt` writer - fs_scl_hcnt"] -pub type FS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { - FS_SCL_HCNT_W::new(self) + pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { + FS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/fs_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c5/fs_scl_lcnt.rs index 5e41cd1..4b4dd6b 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/fs_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/fs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_lcnt` reader - fs_scl_lcnt"] pub type FS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_lcnt` writer - fs_scl_lcnt"] -pub type FS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { - FS_SCL_LCNT_W::new(self) + pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { + FS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/hs_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c5/hs_scl_hcnt.rs index fba7f13..9b0a71c 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/hs_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/hs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_hcnt` reader - hs_scl_hcnt"] pub type HS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_hcnt` writer - hs_scl_hcnt"] -pub type HS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { - HS_SCL_HCNT_W::new(self) + pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { + HS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/hs_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c5/hs_scl_lcnt.rs index 9fca7a5..a715282 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/hs_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/hs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_lcnt` reader - hs_scl_lcnt"] pub type HS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_lcnt` writer - hs_scl_lcnt"] -pub type HS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { - HS_SCL_LCNT_W::new(self) + pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { + HS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/intr_mask.rs b/jh7110-vf2-13b-pac/src/i2c5/intr_mask.rs index 20a334f..769b629 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/intr_mask.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/intr_mask.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/intr_stat.rs b/jh7110-vf2-13b-pac/src/i2c5/intr_stat.rs index 2c2ba34..f376c26 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/intr_stat.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/raw_intr_stat.rs b/jh7110-vf2-13b-pac/src/i2c5/raw_intr_stat.rs index af97981..dd5e8e0 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/raw_intr_stat.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/raw_intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/rx_tl.rs b/jh7110-vf2-13b-pac/src/i2c5/rx_tl.rs index 1455a10..f3f39f4 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/rx_tl.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/rx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rx_tl` reader - rx_tl"] pub type RX_TL_R = crate::FieldReader; #[doc = "Field `rx_tl` writer - rx_tl"] -pub type RX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] #[must_use] - pub fn rx_tl(&mut self) -> RX_TL_W { - RX_TL_W::new(self) + pub fn rx_tl(&mut self) -> RX_TL_W { + RX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/rxflr.rs b/jh7110-vf2-13b-pac/src/i2c5/rxflr.rs index 910e254..4dccf5e 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/rxflr.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/rxflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rxflr` reader - rxflr"] pub type RXFLR_R = crate::FieldReader; #[doc = "Field `rxflr` writer - rxflr"] -pub type RXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] #[must_use] - pub fn rxflr(&mut self) -> RXFLR_W { - RXFLR_W::new(self) + pub fn rxflr(&mut self) -> RXFLR_W { + RXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/sar.rs b/jh7110-vf2-13b-pac/src/i2c5/sar.rs index d272e7a..1af6273 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/sar.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/sar.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Slave address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Slave address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Slave address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Slave address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; impl R { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Slave address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/sda_hold.rs b/jh7110-vf2-13b-pac/src/i2c5/sda_hold.rs index 82ceac5..d5d7512 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/sda_hold.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/sda_hold.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sda_hold` reader - sda_hold"] pub type SDA_HOLD_R = crate::FieldReader; #[doc = "Field `sda_hold` writer - sda_hold"] -pub type SDA_HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SDA_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] #[must_use] - pub fn sda_hold(&mut self) -> SDA_HOLD_W { - SDA_HOLD_W::new(self) + pub fn sda_hold(&mut self) -> SDA_HOLD_W { + SDA_HOLD_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/ss_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c5/ss_scl_hcnt.rs index 33736c7..77d7ea0 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/ss_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/ss_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_hcnt` reader - ss_scl_hcnt"] pub type SS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_hcnt` writer - ss_scl_hcnt"] -pub type SS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { - SS_SCL_HCNT_W::new(self) + pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { + SS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/ss_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c5/ss_scl_lcnt.rs index ce22b5d..8208747 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/ss_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/ss_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_lcnt` reader - ss_scl_lcnt"] pub type SS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_lcnt` writer - ss_scl_lcnt"] -pub type SS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { - SS_SCL_LCNT_W::new(self) + pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { + SS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/status.rs b/jh7110-vf2-13b-pac/src/i2c5/status.rs index 9489e49..1b7ab67 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/status.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/tar.rs b/jh7110-vf2-13b-pac/src/i2c5/tar.rs index 9fedc71..3044a8c 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/tar.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/tar.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Target address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Target address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Target address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Target address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; #[doc = "Field `mode` reader - Target addressing mode - 0: 7-bit, 1: 10-bit"] pub type MODE_R = crate::BitReader; #[doc = "Field `mode` writer - Target addressing mode - 0: 7-bit, 1: 10-bit"] -pub type MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Target address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } #[doc = "Bit 12 - Target addressing mode - 0: 7-bit, 1: 10-bit"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W { - MODE_W::new(self) + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 12) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/tx_abrt_source.rs b/jh7110-vf2-13b-pac/src/i2c5/tx_abrt_source.rs index 6f31813..c4fdf1a 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/tx_abrt_source.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/tx_abrt_source.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/tx_tl.rs b/jh7110-vf2-13b-pac/src/i2c5/tx_tl.rs index 84a1734..b0e6c64 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/tx_tl.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/tx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `tx_tl` reader - tx_tl"] pub type TX_TL_R = crate::FieldReader; #[doc = "Field `tx_tl` writer - tx_tl"] -pub type TX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] #[must_use] - pub fn tx_tl(&mut self) -> TX_TL_W { - TX_TL_W::new(self) + pub fn tx_tl(&mut self) -> TX_TL_W { + TX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c5/txflr.rs b/jh7110-vf2-13b-pac/src/i2c5/txflr.rs index b8e5fdd..5ca351d 100644 --- a/jh7110-vf2-13b-pac/src/i2c5/txflr.rs +++ b/jh7110-vf2-13b-pac/src/i2c5/txflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `txflr` reader - txflr"] pub type TXFLR_R = crate::FieldReader; #[doc = "Field `txflr` writer - txflr"] -pub type TXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - txflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - txflr"] #[inline(always)] #[must_use] - pub fn txflr(&mut self) -> TXFLR_W { - TXFLR_W::new(self) + pub fn txflr(&mut self) -> TXFLR_W { + TXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6.rs b/jh7110-vf2-13b-pac/src/i2c6.rs index d0fe76a..fdffe28 100644 --- a/jh7110-vf2-13b-pac/src/i2c6.rs +++ b/jh7110-vf2-13b-pac/src/i2c6.rs @@ -1,266 +1,416 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + con: CON, + tar: TAR, + sar: SAR, + _reserved3: [u8; 0x04], + data_cmd: DATA_CMD, + ss_scl_hcnt: SS_SCL_HCNT, + ss_scl_lcnt: SS_SCL_LCNT, + fs_scl_hcnt: FS_SCL_HCNT, + fs_scl_lcnt: FS_SCL_LCNT, + hs_scl_hcnt: HS_SCL_HCNT, + hs_scl_lcnt: HS_SCL_LCNT, + intr_stat: INTR_STAT, + intr_mask: INTR_MASK, + raw_intr_stat: RAW_INTR_STAT, + rx_tl: RX_TL, + tx_tl: TX_TL, + clr_intr: CLR_INTR, + clr_rx_under: CLR_RX_UNDER, + clr_rx_over: CLR_RX_OVER, + clr_tx_over: CLR_TX_OVER, + clr_rd_req: CLR_RD_REQ, + clr_tx_abrt: CLR_TX_ABRT, + clr_rx_done: CLR_RX_DONE, + clr_activity: CLR_ACTIVITY, + clr_stop_det: CLR_STOP_DET, + clr_start_det: CLR_START_DET, + clr_gen_call: CLR_GEN_CALL, + enable: ENABLE, + status: STATUS, + txflr: TXFLR, + rxflr: RXFLR, + sda_hold: SDA_HOLD, + tx_abrt_source: TX_ABRT_SOURCE, + _reserved32: [u8; 0x18], + enable_status: ENABLE_STATUS, + _reserved33: [u8; 0x08], + clr_restart_det: CLR_RESTART_DET, + _reserved34: [u8; 0x48], + comp_param_1: COMP_PARAM_1, + comp_version: COMP_VERSION, + comp_type: COMP_TYPE, +} +impl RegisterBlock { #[doc = "0x00 - DesignWare I2C CON"] - pub con: CON, + #[inline(always)] + pub const fn con(&self) -> &CON { + &self.con + } #[doc = "0x04 - DesignWare I2C TAR"] - pub tar: TAR, + #[inline(always)] + pub const fn tar(&self) -> &TAR { + &self.tar + } #[doc = "0x08 - DesignWare I2C SAR"] - pub sar: SAR, - _reserved3: [u8; 0x04], + #[inline(always)] + pub const fn sar(&self) -> &SAR { + &self.sar + } #[doc = "0x10 - DesignWare I2C Data Command"] - pub data_cmd: DATA_CMD, + #[inline(always)] + pub const fn data_cmd(&self) -> &DATA_CMD { + &self.data_cmd + } #[doc = "0x14 - DesignWare I2C SS SCL HCNT"] - pub ss_scl_hcnt: SS_SCL_HCNT, + #[inline(always)] + pub const fn ss_scl_hcnt(&self) -> &SS_SCL_HCNT { + &self.ss_scl_hcnt + } #[doc = "0x18 - DesignWare I2C SS SCL LCNT"] - pub ss_scl_lcnt: SS_SCL_LCNT, + #[inline(always)] + pub const fn ss_scl_lcnt(&self) -> &SS_SCL_LCNT { + &self.ss_scl_lcnt + } #[doc = "0x1c - DesignWare I2C FS SCL HCNT"] - pub fs_scl_hcnt: FS_SCL_HCNT, + #[inline(always)] + pub const fn fs_scl_hcnt(&self) -> &FS_SCL_HCNT { + &self.fs_scl_hcnt + } #[doc = "0x20 - DesignWare I2C FS SCL LCNT"] - pub fs_scl_lcnt: FS_SCL_LCNT, + #[inline(always)] + pub const fn fs_scl_lcnt(&self) -> &FS_SCL_LCNT { + &self.fs_scl_lcnt + } #[doc = "0x24 - DesignWare I2C HS SCL HCNT"] - pub hs_scl_hcnt: HS_SCL_HCNT, + #[inline(always)] + pub const fn hs_scl_hcnt(&self) -> &HS_SCL_HCNT { + &self.hs_scl_hcnt + } #[doc = "0x28 - DesignWare I2C HS SCL LCNT"] - pub hs_scl_lcnt: HS_SCL_LCNT, + #[inline(always)] + pub const fn hs_scl_lcnt(&self) -> &HS_SCL_LCNT { + &self.hs_scl_lcnt + } #[doc = "0x2c - DesignWare I2C Interrupt Status"] - pub intr_stat: INTR_STAT, + #[inline(always)] + pub const fn intr_stat(&self) -> &INTR_STAT { + &self.intr_stat + } #[doc = "0x30 - DesignWare I2C Interrupt Mask"] - pub intr_mask: INTR_MASK, + #[inline(always)] + pub const fn intr_mask(&self) -> &INTR_MASK { + &self.intr_mask + } #[doc = "0x34 - DesignWare I2C Raw Interrupt Status"] - pub raw_intr_stat: RAW_INTR_STAT, + #[inline(always)] + pub const fn raw_intr_stat(&self) -> &RAW_INTR_STAT { + &self.raw_intr_stat + } #[doc = "0x38 - DesignWare I2C RX TL"] - pub rx_tl: RX_TL, + #[inline(always)] + pub const fn rx_tl(&self) -> &RX_TL { + &self.rx_tl + } #[doc = "0x3c - DesignWare I2C TX TL"] - pub tx_tl: TX_TL, + #[inline(always)] + pub const fn tx_tl(&self) -> &TX_TL { + &self.tx_tl + } #[doc = "0x40 - DesignWare I2C Clear Interrrupt"] - pub clr_intr: CLR_INTR, + #[inline(always)] + pub const fn clr_intr(&self) -> &CLR_INTR { + &self.clr_intr + } #[doc = "0x44 - DesignWare I2C Clear RX Underrun"] - pub clr_rx_under: CLR_RX_UNDER, + #[inline(always)] + pub const fn clr_rx_under(&self) -> &CLR_RX_UNDER { + &self.clr_rx_under + } #[doc = "0x48 - DesignWare I2C Clear RX Overrun"] - pub clr_rx_over: CLR_RX_OVER, + #[inline(always)] + pub const fn clr_rx_over(&self) -> &CLR_RX_OVER { + &self.clr_rx_over + } #[doc = "0x4c - DesignWare I2C Clear TX Overrun"] - pub clr_tx_over: CLR_TX_OVER, + #[inline(always)] + pub const fn clr_tx_over(&self) -> &CLR_TX_OVER { + &self.clr_tx_over + } #[doc = "0x50 - DesignWare I2C Clear Read Request"] - pub clr_rd_req: CLR_RD_REQ, + #[inline(always)] + pub const fn clr_rd_req(&self) -> &CLR_RD_REQ { + &self.clr_rd_req + } #[doc = "0x54 - DesignWare I2C Clear TX Abort"] - pub clr_tx_abrt: CLR_TX_ABRT, + #[inline(always)] + pub const fn clr_tx_abrt(&self) -> &CLR_TX_ABRT { + &self.clr_tx_abrt + } #[doc = "0x58 - DesignWare I2C Clear RX Done"] - pub clr_rx_done: CLR_RX_DONE, + #[inline(always)] + pub const fn clr_rx_done(&self) -> &CLR_RX_DONE { + &self.clr_rx_done + } #[doc = "0x5c - DesignWare I2C Clear Activity"] - pub clr_activity: CLR_ACTIVITY, + #[inline(always)] + pub const fn clr_activity(&self) -> &CLR_ACTIVITY { + &self.clr_activity + } #[doc = "0x60 - DesignWare I2C Clear Stop DET"] - pub clr_stop_det: CLR_STOP_DET, + #[inline(always)] + pub const fn clr_stop_det(&self) -> &CLR_STOP_DET { + &self.clr_stop_det + } #[doc = "0x64 - DesignWare I2C Clear Start DET"] - pub clr_start_det: CLR_START_DET, + #[inline(always)] + pub const fn clr_start_det(&self) -> &CLR_START_DET { + &self.clr_start_det + } #[doc = "0x68 - DesignWare I2C Clear General Call"] - pub clr_gen_call: CLR_GEN_CALL, + #[inline(always)] + pub const fn clr_gen_call(&self) -> &CLR_GEN_CALL { + &self.clr_gen_call + } #[doc = "0x6c - DesignWare I2C Enable"] - pub enable: ENABLE, + #[inline(always)] + pub const fn enable(&self) -> &ENABLE { + &self.enable + } #[doc = "0x70 - DesignWare I2C Status"] - pub status: STATUS, + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } #[doc = "0x74 - DesignWare I2C TX Failure"] - pub txflr: TXFLR, + #[inline(always)] + pub const fn txflr(&self) -> &TXFLR { + &self.txflr + } #[doc = "0x78 - DesignWare I2C RX Failure"] - pub rxflr: RXFLR, + #[inline(always)] + pub const fn rxflr(&self) -> &RXFLR { + &self.rxflr + } #[doc = "0x7c - DesignWare I2C SDA Hold"] - pub sda_hold: SDA_HOLD, + #[inline(always)] + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold + } #[doc = "0x80 - DesignWare I2C TX Abort Source"] - pub tx_abrt_source: TX_ABRT_SOURCE, - _reserved32: [u8; 0x18], + #[inline(always)] + pub const fn tx_abrt_source(&self) -> &TX_ABRT_SOURCE { + &self.tx_abrt_source + } #[doc = "0x9c - DesignWare I2C Enable Status"] - pub enable_status: ENABLE_STATUS, - _reserved33: [u8; 0x08], + #[inline(always)] + pub const fn enable_status(&self) -> &ENABLE_STATUS { + &self.enable_status + } #[doc = "0xa8 - DesignWare I2C Clear Restart DET"] - pub clr_restart_det: CLR_RESTART_DET, - _reserved34: [u8; 0x48], + #[inline(always)] + pub const fn clr_restart_det(&self) -> &CLR_RESTART_DET { + &self.clr_restart_det + } #[doc = "0xf4 - DesignWare I2C Compatibility Parameter 1"] - pub comp_param_1: COMP_PARAM_1, + #[inline(always)] + pub const fn comp_param_1(&self) -> &COMP_PARAM_1 { + &self.comp_param_1 + } #[doc = "0xf8 - DesignWare I2C Compatibility Version"] - pub comp_version: COMP_VERSION, + #[inline(always)] + pub const fn comp_version(&self) -> &COMP_VERSION { + &self.comp_version + } #[doc = "0xfc - DesignWare I2C Compatibility Type"] - pub comp_type: COMP_TYPE, + #[inline(always)] + pub const fn comp_type(&self) -> &COMP_TYPE { + &self.comp_type + } } -#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`con`] +#[doc = "con (rw) register accessor: DesignWare I2C CON\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@con`] module"] pub type CON = crate::Reg; #[doc = "DesignWare I2C CON"] pub mod con; -#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tar`] +#[doc = "tar (rw) register accessor: DesignWare I2C TAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar`] module"] pub type TAR = crate::Reg; #[doc = "DesignWare I2C TAR"] pub mod tar; -#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sar`] +#[doc = "sar (rw) register accessor: DesignWare I2C SAR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`] module"] pub type SAR = crate::Reg; #[doc = "DesignWare I2C SAR"] pub mod sar; -#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`data_cmd`] +#[doc = "data_cmd (rw) register accessor: DesignWare I2C Data Command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_cmd`] module"] pub type DATA_CMD = crate::Reg; #[doc = "DesignWare I2C Data Command"] pub mod data_cmd; -#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_hcnt`] +#[doc = "ss_scl_hcnt (rw) register accessor: DesignWare I2C SS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_hcnt`] module"] pub type SS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL HCNT"] pub mod ss_scl_hcnt; -#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ss_scl_lcnt`] +#[doc = "ss_scl_lcnt (rw) register accessor: DesignWare I2C SS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_scl_lcnt`] module"] pub type SS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C SS SCL LCNT"] pub mod ss_scl_lcnt; -#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_hcnt`] +#[doc = "fs_scl_hcnt (rw) register accessor: DesignWare I2C FS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_hcnt`] module"] pub type FS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL HCNT"] pub mod fs_scl_hcnt; -#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fs_scl_lcnt`] +#[doc = "fs_scl_lcnt (rw) register accessor: DesignWare I2C FS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fs_scl_lcnt`] module"] pub type FS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C FS SCL LCNT"] pub mod fs_scl_lcnt; -#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_hcnt`] +#[doc = "hs_scl_hcnt (rw) register accessor: DesignWare I2C HS SCL HCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_hcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_hcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_hcnt`] module"] pub type HS_SCL_HCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL HCNT"] pub mod hs_scl_hcnt; -#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hs_scl_lcnt`] +#[doc = "hs_scl_lcnt (rw) register accessor: DesignWare I2C HS SCL LCNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_scl_lcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_scl_lcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_scl_lcnt`] module"] pub type HS_SCL_LCNT = crate::Reg; #[doc = "DesignWare I2C HS SCL LCNT"] pub mod hs_scl_lcnt; -#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_stat`] +#[doc = "intr_stat (rw) register accessor: DesignWare I2C Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"] pub type INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Interrupt Status"] pub mod intr_stat; -#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`intr_mask`] +#[doc = "intr_mask (rw) register accessor: DesignWare I2C Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mask`] module"] pub type INTR_MASK = crate::Reg; #[doc = "DesignWare I2C Interrupt Mask"] pub mod intr_mask; -#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`raw_intr_stat`] +#[doc = "raw_intr_stat (rw) register accessor: DesignWare I2C Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"] pub type RAW_INTR_STAT = crate::Reg; #[doc = "DesignWare I2C Raw Interrupt Status"] pub mod raw_intr_stat; -#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rx_tl`] +#[doc = "rx_tl (rw) register accessor: DesignWare I2C RX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tl`] module"] pub type RX_TL = crate::Reg; #[doc = "DesignWare I2C RX TL"] pub mod rx_tl; -#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_tl`] +#[doc = "tx_tl (rw) register accessor: DesignWare I2C TX TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_tl`] module"] pub type TX_TL = crate::Reg; #[doc = "DesignWare I2C TX TL"] pub mod tx_tl; -#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_intr`] +#[doc = "clr_intr (rw) register accessor: DesignWare I2C Clear Interrrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_intr`] module"] pub type CLR_INTR = crate::Reg; #[doc = "DesignWare I2C Clear Interrrupt"] pub mod clr_intr; -#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_under`] +#[doc = "clr_rx_under (rw) register accessor: DesignWare I2C Clear RX Underrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_under`] module"] pub type CLR_RX_UNDER = crate::Reg; #[doc = "DesignWare I2C Clear RX Underrun"] pub mod clr_rx_under; -#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_over`] +#[doc = "clr_rx_over (rw) register accessor: DesignWare I2C Clear RX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_over`] module"] pub type CLR_RX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear RX Overrun"] pub mod clr_rx_over; -#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_over`] +#[doc = "clr_tx_over (rw) register accessor: DesignWare I2C Clear TX Overrun\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_over`] module"] pub type CLR_TX_OVER = crate::Reg; #[doc = "DesignWare I2C Clear TX Overrun"] pub mod clr_tx_over; -#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rd_req`] +#[doc = "clr_rd_req (rw) register accessor: DesignWare I2C Clear Read Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rd_req`] module"] pub type CLR_RD_REQ = crate::Reg; #[doc = "DesignWare I2C Clear Read Request"] pub mod clr_rd_req; -#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_tx_abrt`] +#[doc = "clr_tx_abrt (rw) register accessor: DesignWare I2C Clear TX Abort\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_tx_abrt`] module"] pub type CLR_TX_ABRT = crate::Reg; #[doc = "DesignWare I2C Clear TX Abort"] pub mod clr_tx_abrt; -#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_rx_done`] +#[doc = "clr_rx_done (rw) register accessor: DesignWare I2C Clear RX Done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_rx_done`] module"] pub type CLR_RX_DONE = crate::Reg; #[doc = "DesignWare I2C Clear RX Done"] pub mod clr_rx_done; -#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_activity`] +#[doc = "clr_activity (rw) register accessor: DesignWare I2C Clear Activity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_activity`] module"] pub type CLR_ACTIVITY = crate::Reg; #[doc = "DesignWare I2C Clear Activity"] pub mod clr_activity; -#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_stop_det`] +#[doc = "clr_stop_det (rw) register accessor: DesignWare I2C Clear Stop DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_stop_det`] module"] pub type CLR_STOP_DET = crate::Reg; #[doc = "DesignWare I2C Clear Stop DET"] pub mod clr_stop_det; -#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_start_det`] +#[doc = "clr_start_det (rw) register accessor: DesignWare I2C Clear Start DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_start_det`] module"] pub type CLR_START_DET = crate::Reg; #[doc = "DesignWare I2C Clear Start DET"] pub mod clr_start_det; -#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_gen_call`] +#[doc = "clr_gen_call (rw) register accessor: DesignWare I2C Clear General Call\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_gen_call`] module"] pub type CLR_GEN_CALL = crate::Reg; #[doc = "DesignWare I2C Clear General Call"] pub mod clr_gen_call; -#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable`] +#[doc = "enable (rw) register accessor: DesignWare I2C Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] pub type ENABLE = crate::Reg; #[doc = "DesignWare I2C Enable"] pub mod enable; -#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`status`] +#[doc = "status (rw) register accessor: DesignWare I2C Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] pub type STATUS = crate::Reg; #[doc = "DesignWare I2C Status"] pub mod status; -#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txflr`] +#[doc = "txflr (rw) register accessor: DesignWare I2C TX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txflr`] module"] pub type TXFLR = crate::Reg; #[doc = "DesignWare I2C TX Failure"] pub mod txflr; -#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxflr`] +#[doc = "rxflr (rw) register accessor: DesignWare I2C RX Failure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxflr`] module"] pub type RXFLR = crate::Reg; #[doc = "DesignWare I2C RX Failure"] pub mod rxflr; -#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sda_hold`] +#[doc = "sda_hold (rw) register accessor: DesignWare I2C SDA Hold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] pub type SDA_HOLD = crate::Reg; #[doc = "DesignWare I2C SDA Hold"] pub mod sda_hold; -#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tx_abrt_source`] +#[doc = "tx_abrt_source (rw) register accessor: DesignWare I2C TX Abort Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_abrt_source`] module"] pub type TX_ABRT_SOURCE = crate::Reg; #[doc = "DesignWare I2C TX Abort Source"] pub mod tx_abrt_source; -#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_status`] +#[doc = "enable_status (rw) register accessor: DesignWare I2C Enable Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_status`] module"] pub type ENABLE_STATUS = crate::Reg; #[doc = "DesignWare I2C Enable Status"] pub mod enable_status; -#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clr_restart_det`] +#[doc = "clr_restart_det (rw) register accessor: DesignWare I2C Clear Restart DET\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr_restart_det`] module"] pub type CLR_RESTART_DET = crate::Reg; #[doc = "DesignWare I2C Clear Restart DET"] pub mod clr_restart_det; -#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_param_1`] +#[doc = "comp_param_1 (rw) register accessor: DesignWare I2C Compatibility Parameter 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_param_1`] module"] pub type COMP_PARAM_1 = crate::Reg; #[doc = "DesignWare I2C Compatibility Parameter 1"] pub mod comp_param_1; -#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_version`] +#[doc = "comp_version (rw) register accessor: DesignWare I2C Compatibility Version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_version`] module"] pub type COMP_VERSION = crate::Reg; #[doc = "DesignWare I2C Compatibility Version"] pub mod comp_version; -#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`comp_type`] +#[doc = "comp_type (rw) register accessor: DesignWare I2C Compatibility Type\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp_type`] module"] pub type COMP_TYPE = crate::Reg; #[doc = "DesignWare I2C Compatibility Type"] diff --git a/jh7110-vf2-13b-pac/src/i2c6/clr_activity.rs b/jh7110-vf2-13b-pac/src/i2c6/clr_activity.rs index d26bb80..1ee2297 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/clr_activity.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/clr_activity.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_activity` reader - clr_activity"] pub type CLR_ACTIVITY_R = crate::FieldReader; #[doc = "Field `clr_activity` writer - clr_activity"] -pub type CLR_ACTIVITY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_ACTIVITY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_activity"] #[inline(always)] #[must_use] - pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { - CLR_ACTIVITY_W::new(self) + pub fn clr_activity(&mut self) -> CLR_ACTIVITY_W { + CLR_ACTIVITY_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/clr_gen_call.rs b/jh7110-vf2-13b-pac/src/i2c6/clr_gen_call.rs index a9ea5af..4a7c5ba 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/clr_gen_call.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/clr_gen_call.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_gen_call` reader - clr_gen_call"] pub type CLR_GEN_CALL_R = crate::FieldReader; #[doc = "Field `clr_gen_call` writer - clr_gen_call"] -pub type CLR_GEN_CALL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_GEN_CALL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_gen_call"] #[inline(always)] #[must_use] - pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { - CLR_GEN_CALL_W::new(self) + pub fn clr_gen_call(&mut self) -> CLR_GEN_CALL_W { + CLR_GEN_CALL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/clr_intr.rs b/jh7110-vf2-13b-pac/src/i2c6/clr_intr.rs index a7daf57..cf57b09 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/clr_intr.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/clr_intr.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/clr_rd_req.rs b/jh7110-vf2-13b-pac/src/i2c6/clr_rd_req.rs index e275da1..4beae9d 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/clr_rd_req.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/clr_rd_req.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rd_req` reader - clr_rd_req"] pub type CLR_RD_REQ_R = crate::FieldReader; #[doc = "Field `clr_rd_req` writer - clr_rd_req"] -pub type CLR_RD_REQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RD_REQ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rd_req"] #[inline(always)] #[must_use] - pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { - CLR_RD_REQ_W::new(self) + pub fn clr_rd_req(&mut self) -> CLR_RD_REQ_W { + CLR_RD_REQ_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/clr_restart_det.rs b/jh7110-vf2-13b-pac/src/i2c6/clr_restart_det.rs index 5be7f5d..88d193c 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/clr_restart_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/clr_restart_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_restart_det` reader - clr_restart_det"] pub type CLR_RESTART_DET_R = crate::FieldReader; #[doc = "Field `clr_restart_det` writer - clr_restart_det"] -pub type CLR_RESTART_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RESTART_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_restart_det"] #[inline(always)] #[must_use] - pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { - CLR_RESTART_DET_W::new(self) + pub fn clr_restart_det(&mut self) -> CLR_RESTART_DET_W { + CLR_RESTART_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/clr_rx_done.rs b/jh7110-vf2-13b-pac/src/i2c6/clr_rx_done.rs index 02d83c5..7e14a3f 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/clr_rx_done.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/clr_rx_done.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_done` reader - clr_rx_done"] pub type CLR_RX_DONE_R = crate::FieldReader; #[doc = "Field `clr_rx_done` writer - clr_rx_done"] -pub type CLR_RX_DONE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_DONE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_done"] #[inline(always)] #[must_use] - pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { - CLR_RX_DONE_W::new(self) + pub fn clr_rx_done(&mut self) -> CLR_RX_DONE_W { + CLR_RX_DONE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/clr_rx_over.rs b/jh7110-vf2-13b-pac/src/i2c6/clr_rx_over.rs index 6d7ff4e..2302921 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/clr_rx_over.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/clr_rx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_over` reader - clr_rx_over"] pub type CLR_RX_OVER_R = crate::FieldReader; #[doc = "Field `clr_rx_over` writer - clr_rx_over"] -pub type CLR_RX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_over"] #[inline(always)] #[must_use] - pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { - CLR_RX_OVER_W::new(self) + pub fn clr_rx_over(&mut self) -> CLR_RX_OVER_W { + CLR_RX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/clr_rx_under.rs b/jh7110-vf2-13b-pac/src/i2c6/clr_rx_under.rs index 4a24f7c..35e15bd 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/clr_rx_under.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/clr_rx_under.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_rx_under` reader - clr_rx_under"] pub type CLR_RX_UNDER_R = crate::FieldReader; #[doc = "Field `clr_rx_under` writer - clr_rx_under"] -pub type CLR_RX_UNDER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_RX_UNDER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_rx_under"] #[inline(always)] #[must_use] - pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { - CLR_RX_UNDER_W::new(self) + pub fn clr_rx_under(&mut self) -> CLR_RX_UNDER_W { + CLR_RX_UNDER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/clr_start_det.rs b/jh7110-vf2-13b-pac/src/i2c6/clr_start_det.rs index cebc4bc..2314f65 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/clr_start_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/clr_start_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_start_det` reader - clr_start_det"] pub type CLR_START_DET_R = crate::FieldReader; #[doc = "Field `clr_start_det` writer - clr_start_det"] -pub type CLR_START_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_START_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_start_det"] #[inline(always)] #[must_use] - pub fn clr_start_det(&mut self) -> CLR_START_DET_W { - CLR_START_DET_W::new(self) + pub fn clr_start_det(&mut self) -> CLR_START_DET_W { + CLR_START_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/clr_stop_det.rs b/jh7110-vf2-13b-pac/src/i2c6/clr_stop_det.rs index 44f39f3..49abcac 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/clr_stop_det.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/clr_stop_det.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_stop_det` reader - clr_stop_det"] pub type CLR_STOP_DET_R = crate::FieldReader; #[doc = "Field `clr_stop_det` writer - clr_stop_det"] -pub type CLR_STOP_DET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_STOP_DET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_stop_det"] #[inline(always)] #[must_use] - pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { - CLR_STOP_DET_W::new(self) + pub fn clr_stop_det(&mut self) -> CLR_STOP_DET_W { + CLR_STOP_DET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/clr_tx_abrt.rs b/jh7110-vf2-13b-pac/src/i2c6/clr_tx_abrt.rs index 6ac441c..3bc0f6f 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/clr_tx_abrt.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/clr_tx_abrt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_abrt` reader - clr_tx_abrt"] pub type CLR_TX_ABRT_R = crate::FieldReader; #[doc = "Field `clr_tx_abrt` writer - clr_tx_abrt"] -pub type CLR_TX_ABRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_ABRT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_abrt"] #[inline(always)] #[must_use] - pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { - CLR_TX_ABRT_W::new(self) + pub fn clr_tx_abrt(&mut self) -> CLR_TX_ABRT_W { + CLR_TX_ABRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/clr_tx_over.rs b/jh7110-vf2-13b-pac/src/i2c6/clr_tx_over.rs index 2b32b52..a5b6933 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/clr_tx_over.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/clr_tx_over.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clr_tx_over` reader - clr_tx_over"] pub type CLR_TX_OVER_R = crate::FieldReader; #[doc = "Field `clr_tx_over` writer - clr_tx_over"] -pub type CLR_TX_OVER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type CLR_TX_OVER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - clr_tx_over"] #[inline(always)] #[must_use] - pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { - CLR_TX_OVER_W::new(self) + pub fn clr_tx_over(&mut self) -> CLR_TX_OVER_W { + CLR_TX_OVER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/comp_param_1.rs b/jh7110-vf2-13b-pac/src/i2c6/comp_param_1.rs index 24a22e1..95c5002 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/comp_param_1.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/comp_param_1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/comp_type.rs b/jh7110-vf2-13b-pac/src/i2c6/comp_type.rs index ac916b5..1336c43 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/comp_type.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/comp_type.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/comp_version.rs b/jh7110-vf2-13b-pac/src/i2c6/comp_version.rs index 4be31fa..e8309c8 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/comp_version.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/comp_version.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/con.rs b/jh7110-vf2-13b-pac/src/i2c6/con.rs index 873c534..28aa865 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/con.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/con.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `master` reader - I2C Master Connection - 0: Slave, 1: Master"] pub type MASTER_R = crate::BitReader; #[doc = "Field `master` writer - I2C Master Connection - 0: Slave, 1: Master"] -pub type MASTER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `speed` reader - I2C Speed - 01: Standard, 10: Fast, 11: High"] pub type SPEED_R = crate::FieldReader; #[doc = "Field `speed` writer - I2C Speed - 01: Standard, 10: Fast, 11: High"] -pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `slave_10bitaddr` reader - I2C Slave 10-bit Address - 0: False, 1: True"] pub type SLAVE_10BITADDR_R = crate::BitReader; #[doc = "Field `slave_10bitaddr` writer - I2C Slave 10-bit Address - 0: False, 1: True"] -pub type SLAVE_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_10bitaddr` reader - I2C Master 10-bit Address - 0: False, 1: True"] pub type MASTER_10BITADDR_R = crate::BitReader; #[doc = "Field `master_10bitaddr` writer - I2C Master 10-bit Address - 0: False, 1: True"] -pub type MASTER_10BITADDR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_10BITADDR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_en` reader - I2C Restart Enable - 0: False, 1: True"] pub type RESTART_EN_R = crate::BitReader; #[doc = "Field `restart_en` writer - I2C Restart Enable - 0: False, 1: True"] -pub type RESTART_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_disable` reader - I2C Slave Disable - 0: False, 1: True"] pub type SLAVE_DISABLE_R = crate::BitReader; #[doc = "Field `slave_disable` writer - I2C Slave Disable - 0: False, 1: True"] -pub type SLAVE_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det_ifaddressed` reader - I2C Stop DET If Addressed - 0: False, 1: True"] pub type STOP_DET_IFADDRESSED_R = crate::BitReader; #[doc = "Field `stop_det_ifaddressed` writer - I2C Stop DET If Addressed - 0: False, 1: True"] -pub type STOP_DET_IFADDRESSED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty_ctrl` reader - I2C TX Empty Control - 0: False, 1: True"] pub type TX_EMPTY_CTRL_R = crate::BitReader; #[doc = "Field `tx_empty_ctrl` writer - I2C TX Empty Control - 0: False, 1: True"] -pub type TX_EMPTY_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_fifo_full_hld_ctrl` reader - I2C RX FIFO Full Hold Control - 0: False, 1: True"] pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; #[doc = "Field `rx_fifo_full_hld_ctrl` writer - I2C RX FIFO Full Hold Control - 0: False, 1: True"] -pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bus_clear_ctrl` reader - I2C Bus Clear Control - 0: False, 1: True"] pub type BUS_CLEAR_CTRL_R = crate::BitReader; #[doc = "Field `bus_clear_ctrl` writer - I2C Bus Clear Control - 0: False, 1: True"] -pub type BUS_CLEAR_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BUS_CLEAR_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bit 0 - I2C Master Connection - 0: Slave, 1: Master"] #[inline(always)] #[must_use] - pub fn master(&mut self) -> MASTER_W { - MASTER_W::new(self) + pub fn master(&mut self) -> MASTER_W { + MASTER_W::new(self, 0) } #[doc = "Bits 1:2 - I2C Speed - 01: Standard, 10: Fast, 11: High"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W { - SPEED_W::new(self) + pub fn speed(&mut self) -> SPEED_W { + SPEED_W::new(self, 1) } #[doc = "Bit 3 - I2C Slave 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { - SLAVE_10BITADDR_W::new(self) + pub fn slave_10bitaddr(&mut self) -> SLAVE_10BITADDR_W { + SLAVE_10BITADDR_W::new(self, 3) } #[doc = "Bit 4 - I2C Master 10-bit Address - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { - MASTER_10BITADDR_W::new(self) + pub fn master_10bitaddr(&mut self) -> MASTER_10BITADDR_W { + MASTER_10BITADDR_W::new(self, 4) } #[doc = "Bit 5 - I2C Restart Enable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn restart_en(&mut self) -> RESTART_EN_W { - RESTART_EN_W::new(self) + pub fn restart_en(&mut self) -> RESTART_EN_W { + RESTART_EN_W::new(self, 5) } #[doc = "Bit 6 - I2C Slave Disable - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { - SLAVE_DISABLE_W::new(self) + pub fn slave_disable(&mut self) -> SLAVE_DISABLE_W { + SLAVE_DISABLE_W::new(self, 6) } #[doc = "Bit 7 - I2C Stop DET If Addressed - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { - STOP_DET_IFADDRESSED_W::new(self) + pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { + STOP_DET_IFADDRESSED_W::new(self, 7) } #[doc = "Bit 8 - I2C TX Empty Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { - TX_EMPTY_CTRL_W::new(self) + pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { + TX_EMPTY_CTRL_W::new(self, 8) } #[doc = "Bit 9 - I2C RX FIFO Full Hold Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { - RX_FIFO_FULL_HLD_CTRL_W::new(self) + pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { + RX_FIFO_FULL_HLD_CTRL_W::new(self, 9) } #[doc = "Bit 11 - I2C Bus Clear Control - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { - BUS_CLEAR_CTRL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn bus_clear_ctrl(&mut self) -> BUS_CLEAR_CTRL_W { + BUS_CLEAR_CTRL_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/data_cmd.rs b/jh7110-vf2-13b-pac/src/i2c6/data_cmd.rs index cf36408..2b320d4 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/data_cmd.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/data_cmd.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `dat` reader - Data Command Data Byte"] pub type DAT_R = crate::FieldReader; #[doc = "Field `dat` writer - Data Command Data Byte"] -pub type DAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `read` reader - Data Command READ Bit - 0: Write, 1: Read"] pub type READ_R = crate::BitReader; #[doc = "Field `read` writer - Data Command READ Bit - 0: Write, 1: Read"] -pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop` reader - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart` reader - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] pub type RESTART_R = crate::BitReader; #[doc = "Field `restart` writer - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] -pub type RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `first_data_byte` reader - Data Command First Data Byte - 0: False, 1: True"] pub type FIRST_DATA_BYTE_R = crate::BitReader; #[doc = "Field `first_data_byte` writer - Data Command First Data Byte - 0: False, 1: True"] -pub type FIRST_DATA_BYTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIRST_DATA_BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bits 0:7 - Data Command Data Byte"] #[inline(always)] #[must_use] - pub fn dat(&mut self) -> DAT_W { - DAT_W::new(self) + pub fn dat(&mut self) -> DAT_W { + DAT_W::new(self, 0) } #[doc = "Bit 8 - Data Command READ Bit - 0: Write, 1: Read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W { - READ_W::new(self) + pub fn read(&mut self) -> READ_W { + READ_W::new(self, 8) } #[doc = "Bit 9 - Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 9) } #[doc = "Bit 10 - Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer"] #[inline(always)] #[must_use] - pub fn restart(&mut self) -> RESTART_W { - RESTART_W::new(self) + pub fn restart(&mut self) -> RESTART_W { + RESTART_W::new(self, 10) } #[doc = "Bit 11 - Data Command First Data Byte - 0: False, 1: True"] #[inline(always)] #[must_use] - pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { - FIRST_DATA_BYTE_W::new(self) + pub fn first_data_byte(&mut self) -> FIRST_DATA_BYTE_W { + FIRST_DATA_BYTE_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/enable.rs b/jh7110-vf2-13b-pac/src/i2c6/enable.rs index c5ca9d7..3629f6b 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/enable.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/enable.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `abort` reader - abort"] pub type ABORT_R = crate::BitReader; #[doc = "Field `abort` writer - abort"] -pub type ABORT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 1 - abort"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 1 - abort"] #[inline(always)] #[must_use] - pub fn abort(&mut self) -> ABORT_W { - ABORT_W::new(self) + pub fn abort(&mut self) -> ABORT_W { + ABORT_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/enable_status.rs b/jh7110-vf2-13b-pac/src/i2c6/enable_status.rs index 2c102a6..8b9b7d3 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/enable_status.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/enable_status.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `activity` reader - activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tfe` reader - tfe"] pub type TFE_R = crate::BitReader; #[doc = "Field `tfe` writer - tfe"] -pub type TFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TFE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfne` reader - rfne"] pub type RFNE_R = crate::BitReader; #[doc = "Field `rfne` writer - rfne"] -pub type RFNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFNE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `master_activity` reader - master_activity"] pub type MASTER_ACTIVITY_R = crate::BitReader; #[doc = "Field `master_activity` writer - master_activity"] -pub type MASTER_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MASTER_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slave_activity` reader - slave_activity"] pub type SLAVE_ACTIVITY_R = crate::BitReader; #[doc = "Field `slave_activity` writer - slave_activity"] -pub type SLAVE_ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLAVE_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - activity"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 0) } #[doc = "Bit 2 - tfe"] #[inline(always)] #[must_use] - pub fn tfe(&mut self) -> TFE_W { - TFE_W::new(self) + pub fn tfe(&mut self) -> TFE_W { + TFE_W::new(self, 2) } #[doc = "Bit 3 - rfne"] #[inline(always)] #[must_use] - pub fn rfne(&mut self) -> RFNE_W { - RFNE_W::new(self) + pub fn rfne(&mut self) -> RFNE_W { + RFNE_W::new(self, 3) } #[doc = "Bit 5 - master_activity"] #[inline(always)] #[must_use] - pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { - MASTER_ACTIVITY_W::new(self) + pub fn master_activity(&mut self) -> MASTER_ACTIVITY_W { + MASTER_ACTIVITY_W::new(self, 5) } #[doc = "Bit 6 - slave_activity"] #[inline(always)] #[must_use] - pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { - SLAVE_ACTIVITY_W::new(self) + pub fn slave_activity(&mut self) -> SLAVE_ACTIVITY_W { + SLAVE_ACTIVITY_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/fs_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c6/fs_scl_hcnt.rs index 9a9fd72..8a4f6d1 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/fs_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/fs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_hcnt` reader - fs_scl_hcnt"] pub type FS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_hcnt` writer - fs_scl_hcnt"] -pub type FS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { - FS_SCL_HCNT_W::new(self) + pub fn fs_scl_hcnt(&mut self) -> FS_SCL_HCNT_W { + FS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/fs_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c6/fs_scl_lcnt.rs index 5e41cd1..4b4dd6b 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/fs_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/fs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `fs_scl_lcnt` reader - fs_scl_lcnt"] pub type FS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `fs_scl_lcnt` writer - fs_scl_lcnt"] -pub type FS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - fs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { - FS_SCL_LCNT_W::new(self) + pub fn fs_scl_lcnt(&mut self) -> FS_SCL_LCNT_W { + FS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/hs_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c6/hs_scl_hcnt.rs index fba7f13..9b0a71c 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/hs_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/hs_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_hcnt` reader - hs_scl_hcnt"] pub type HS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_hcnt` writer - hs_scl_hcnt"] -pub type HS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_hcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { - HS_SCL_HCNT_W::new(self) + pub fn hs_scl_hcnt(&mut self) -> HS_SCL_HCNT_W { + HS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/hs_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c6/hs_scl_lcnt.rs index 9fca7a5..a715282 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/hs_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/hs_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `hs_scl_lcnt` reader - hs_scl_lcnt"] pub type HS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `hs_scl_lcnt` writer - hs_scl_lcnt"] -pub type HS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type HS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - hs_scl_lcnt"] #[inline(always)] #[must_use] - pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { - HS_SCL_LCNT_W::new(self) + pub fn hs_scl_lcnt(&mut self) -> HS_SCL_LCNT_W { + HS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/intr_mask.rs b/jh7110-vf2-13b-pac/src/i2c6/intr_mask.rs index 20a334f..769b629 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/intr_mask.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/intr_mask.rs @@ -5,59 +5,59 @@ pub type W = crate::W; #[doc = "Field `rx_under` reader - RX FIFO Underrun"] pub type RX_UNDER_R = crate::BitReader; #[doc = "Field `rx_under` writer - RX FIFO Underrun"] -pub type RX_UNDER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_over` reader - RX FIFO Overrun"] pub type RX_OVER_R = crate::BitReader; #[doc = "Field `rx_over` writer - RX FIFO Overrun"] -pub type RX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_full` reader - RX FIFO Full"] pub type RX_FULL_R = crate::BitReader; #[doc = "Field `rx_full` writer - RX FIFO Full"] -pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_over` reader - TX FIFO Overrun"] pub type TX_OVER_R = crate::BitReader; #[doc = "Field `tx_over` writer - TX FIFO Overrun"] -pub type TX_OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_empty` reader - TX FIFO Empty"] pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `tx_empty` writer - TX FIFO Empty"] -pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_req` reader - Read Request"] pub type RD_REQ_R = crate::BitReader; #[doc = "Field `rd_req` writer - Read Request"] -pub type RD_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tx_abrt` reader - TX Abort"] pub type TX_ABRT_R = crate::BitReader; #[doc = "Field `tx_abrt` writer - TX Abort"] -pub type TX_ABRT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rx_done` reader - RX Done"] pub type RX_DONE_R = crate::BitReader; #[doc = "Field `rx_done` writer - RX Done"] -pub type RX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `activity` reader - Activity"] pub type ACTIVITY_R = crate::BitReader; #[doc = "Field `activity` writer - Activity"] -pub type ACTIVITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `stop_det` reader - Stop DET"] pub type STOP_DET_R = crate::BitReader; #[doc = "Field `stop_det` writer - Stop DET"] -pub type STOP_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `start_det` reader - Start DET"] pub type START_DET_R = crate::BitReader; #[doc = "Field `start_det` writer - Start DET"] -pub type START_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gen_call` reader - General Call"] pub type GEN_CALL_R = crate::BitReader; #[doc = "Field `gen_call` writer - General Call"] -pub type GEN_CALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `restart_det` reader - Restart DET"] pub type RESTART_DET_R = crate::BitReader; #[doc = "Field `restart_det` writer - Restart DET"] -pub type RESTART_DET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mst_on_hold` reader - Master on Hold"] pub type MST_ON_HOLD_R = crate::BitReader; #[doc = "Field `mst_on_hold` writer - Master on Hold"] -pub type MST_ON_HOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MST_ON_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] @@ -134,88 +134,92 @@ impl W { #[doc = "Bit 0 - RX FIFO Underrun"] #[inline(always)] #[must_use] - pub fn rx_under(&mut self) -> RX_UNDER_W { - RX_UNDER_W::new(self) + pub fn rx_under(&mut self) -> RX_UNDER_W { + RX_UNDER_W::new(self, 0) } #[doc = "Bit 1 - RX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn rx_over(&mut self) -> RX_OVER_W { - RX_OVER_W::new(self) + pub fn rx_over(&mut self) -> RX_OVER_W { + RX_OVER_W::new(self, 1) } #[doc = "Bit 2 - RX FIFO Full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W { - RX_FULL_W::new(self) + pub fn rx_full(&mut self) -> RX_FULL_W { + RX_FULL_W::new(self, 2) } #[doc = "Bit 3 - TX FIFO Overrun"] #[inline(always)] #[must_use] - pub fn tx_over(&mut self) -> TX_OVER_W { - TX_OVER_W::new(self) + pub fn tx_over(&mut self) -> TX_OVER_W { + TX_OVER_W::new(self, 3) } #[doc = "Bit 4 - TX FIFO Empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W { - TX_EMPTY_W::new(self) + pub fn tx_empty(&mut self) -> TX_EMPTY_W { + TX_EMPTY_W::new(self, 4) } #[doc = "Bit 5 - Read Request"] #[inline(always)] #[must_use] - pub fn rd_req(&mut self) -> RD_REQ_W { - RD_REQ_W::new(self) + pub fn rd_req(&mut self) -> RD_REQ_W { + RD_REQ_W::new(self, 5) } #[doc = "Bit 6 - TX Abort"] #[inline(always)] #[must_use] - pub fn tx_abrt(&mut self) -> TX_ABRT_W { - TX_ABRT_W::new(self) + pub fn tx_abrt(&mut self) -> TX_ABRT_W { + TX_ABRT_W::new(self, 6) } #[doc = "Bit 7 - RX Done"] #[inline(always)] #[must_use] - pub fn rx_done(&mut self) -> RX_DONE_W { - RX_DONE_W::new(self) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 7) } #[doc = "Bit 8 - Activity"] #[inline(always)] #[must_use] - pub fn activity(&mut self) -> ACTIVITY_W { - ACTIVITY_W::new(self) + pub fn activity(&mut self) -> ACTIVITY_W { + ACTIVITY_W::new(self, 8) } #[doc = "Bit 9 - Stop DET"] #[inline(always)] #[must_use] - pub fn stop_det(&mut self) -> STOP_DET_W { - STOP_DET_W::new(self) + pub fn stop_det(&mut self) -> STOP_DET_W { + STOP_DET_W::new(self, 9) } #[doc = "Bit 10 - Start DET"] #[inline(always)] #[must_use] - pub fn start_det(&mut self) -> START_DET_W { - START_DET_W::new(self) + pub fn start_det(&mut self) -> START_DET_W { + START_DET_W::new(self, 10) } #[doc = "Bit 11 - General Call"] #[inline(always)] #[must_use] - pub fn gen_call(&mut self) -> GEN_CALL_W { - GEN_CALL_W::new(self) + pub fn gen_call(&mut self) -> GEN_CALL_W { + GEN_CALL_W::new(self, 11) } #[doc = "Bit 12 - Restart DET"] #[inline(always)] #[must_use] - pub fn restart_det(&mut self) -> RESTART_DET_W { - RESTART_DET_W::new(self) + pub fn restart_det(&mut self) -> RESTART_DET_W { + RESTART_DET_W::new(self, 12) } #[doc = "Bit 13 - Master on Hold"] #[inline(always)] #[must_use] - pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { - MST_ON_HOLD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn mst_on_hold(&mut self) -> MST_ON_HOLD_W { + MST_ON_HOLD_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/intr_stat.rs b/jh7110-vf2-13b-pac/src/i2c6/intr_stat.rs index 2c2ba34..f376c26 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/intr_stat.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/raw_intr_stat.rs b/jh7110-vf2-13b-pac/src/i2c6/raw_intr_stat.rs index af97981..dd5e8e0 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/raw_intr_stat.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/raw_intr_stat.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/rx_tl.rs b/jh7110-vf2-13b-pac/src/i2c6/rx_tl.rs index 1455a10..f3f39f4 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/rx_tl.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/rx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rx_tl` reader - rx_tl"] pub type RX_TL_R = crate::FieldReader; #[doc = "Field `rx_tl` writer - rx_tl"] -pub type RX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rx_tl"] #[inline(always)] #[must_use] - pub fn rx_tl(&mut self) -> RX_TL_W { - RX_TL_W::new(self) + pub fn rx_tl(&mut self) -> RX_TL_W { + RX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/rxflr.rs b/jh7110-vf2-13b-pac/src/i2c6/rxflr.rs index 910e254..4dccf5e 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/rxflr.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/rxflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rxflr` reader - rxflr"] pub type RXFLR_R = crate::FieldReader; #[doc = "Field `rxflr` writer - rxflr"] -pub type RXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - rxflr"] #[inline(always)] #[must_use] - pub fn rxflr(&mut self) -> RXFLR_W { - RXFLR_W::new(self) + pub fn rxflr(&mut self) -> RXFLR_W { + RXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/sar.rs b/jh7110-vf2-13b-pac/src/i2c6/sar.rs index d272e7a..1af6273 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/sar.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/sar.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Slave address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Slave address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Slave address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Slave address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; impl R { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:6 - Slave address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Slave address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/sda_hold.rs b/jh7110-vf2-13b-pac/src/i2c6/sda_hold.rs index 82ceac5..d5d7512 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/sda_hold.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/sda_hold.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sda_hold` reader - sda_hold"] pub type SDA_HOLD_R = crate::FieldReader; #[doc = "Field `sda_hold` writer - sda_hold"] -pub type SDA_HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SDA_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - sda_hold"] #[inline(always)] #[must_use] - pub fn sda_hold(&mut self) -> SDA_HOLD_W { - SDA_HOLD_W::new(self) + pub fn sda_hold(&mut self) -> SDA_HOLD_W { + SDA_HOLD_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/ss_scl_hcnt.rs b/jh7110-vf2-13b-pac/src/i2c6/ss_scl_hcnt.rs index 33736c7..77d7ea0 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/ss_scl_hcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/ss_scl_hcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_hcnt` reader - ss_scl_hcnt"] pub type SS_SCL_HCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_hcnt` writer - ss_scl_hcnt"] -pub type SS_SCL_HCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_hcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { - SS_SCL_HCNT_W::new(self) + pub fn ss_scl_hcnt(&mut self) -> SS_SCL_HCNT_W { + SS_SCL_HCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/ss_scl_lcnt.rs b/jh7110-vf2-13b-pac/src/i2c6/ss_scl_lcnt.rs index ce22b5d..8208747 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/ss_scl_lcnt.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/ss_scl_lcnt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `ss_scl_lcnt` reader - ss_scl_lcnt"] pub type SS_SCL_LCNT_R = crate::FieldReader; #[doc = "Field `ss_scl_lcnt` writer - ss_scl_lcnt"] -pub type SS_SCL_LCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - ss_scl_lcnt"] #[inline(always)] #[must_use] - pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { - SS_SCL_LCNT_W::new(self) + pub fn ss_scl_lcnt(&mut self) -> SS_SCL_LCNT_W { + SS_SCL_LCNT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/status.rs b/jh7110-vf2-13b-pac/src/i2c6/status.rs index 9489e49..1b7ab67 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/status.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/tar.rs b/jh7110-vf2-13b-pac/src/i2c6/tar.rs index 9fedc71..3044a8c 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/tar.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/tar.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `address_7bit` reader - Target address, 7-bit mode"] pub type ADDRESS_7BIT_R = crate::FieldReader; #[doc = "Field `address_7bit` writer - Target address, 7-bit mode"] -pub type ADDRESS_7BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type ADDRESS_7BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `address_10bit` reader - Target address, 10-bit mode"] pub type ADDRESS_10BIT_R = crate::FieldReader; #[doc = "Field `address_10bit` writer - Target address, 10-bit mode"] -pub type ADDRESS_10BIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; +pub type ADDRESS_10BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; #[doc = "Field `mode` reader - Target addressing mode - 0: 7-bit, 1: 10-bit"] pub type MODE_R = crate::BitReader; #[doc = "Field `mode` writer - Target addressing mode - 0: 7-bit, 1: 10-bit"] -pub type MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:6 - Target address, 7-bit mode"] #[inline(always)] #[must_use] - pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { - ADDRESS_7BIT_W::new(self) + pub fn address_7bit(&mut self) -> ADDRESS_7BIT_W { + ADDRESS_7BIT_W::new(self, 0) } #[doc = "Bits 0:9 - Target address, 10-bit mode"] #[inline(always)] #[must_use] - pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { - ADDRESS_10BIT_W::new(self) + pub fn address_10bit(&mut self) -> ADDRESS_10BIT_W { + ADDRESS_10BIT_W::new(self, 0) } #[doc = "Bit 12 - Target addressing mode - 0: 7-bit, 1: 10-bit"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W { - MODE_W::new(self) + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 12) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/tx_abrt_source.rs b/jh7110-vf2-13b-pac/src/i2c6/tx_abrt_source.rs index 6f31813..c4fdf1a 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/tx_abrt_source.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/tx_abrt_source.rs @@ -103,7 +103,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/tx_tl.rs b/jh7110-vf2-13b-pac/src/i2c6/tx_tl.rs index 84a1734..b0e6c64 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/tx_tl.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/tx_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `tx_tl` reader - tx_tl"] pub type TX_TL_R = crate::FieldReader; #[doc = "Field `tx_tl` writer - tx_tl"] -pub type TX_TL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - tx_tl"] #[inline(always)] #[must_use] - pub fn tx_tl(&mut self) -> TX_TL_W { - TX_TL_W::new(self) + pub fn tx_tl(&mut self) -> TX_TL_W { + TX_TL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/i2c6/txflr.rs b/jh7110-vf2-13b-pac/src/i2c6/txflr.rs index b8e5fdd..5ca351d 100644 --- a/jh7110-vf2-13b-pac/src/i2c6/txflr.rs +++ b/jh7110-vf2-13b-pac/src/i2c6/txflr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `txflr` reader - txflr"] pub type TXFLR_R = crate::FieldReader; #[doc = "Field `txflr` writer - txflr"] -pub type TXFLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type TXFLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - txflr"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - txflr"] #[inline(always)] #[must_use] - pub fn txflr(&mut self) -> TXFLR_W { - TXFLR_W::new(self) + pub fn txflr(&mut self) -> TXFLR_W { + TXFLR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/lib.rs b/jh7110-vf2-13b-pac/src/lib.rs index 161e5b5..f318481 100644 --- a/jh7110-vf2-13b-pac/src/lib.rs +++ b/jh7110-vf2-13b-pac/src/lib.rs @@ -1,19 +1,5 @@ -#![doc = "Peripheral access API for STARFIVE VISIONFIVE 2 V1.3B microcontrollers (generated using svd2rust v0.30.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] -svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.30.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] -#![deny(dead_code)] -#![deny(improper_ctypes)] -#![deny(missing_docs)] -#![deny(no_mangle_generic_items)] -#![deny(non_shorthand_field_patterns)] -#![deny(overflowing_literals)] -#![deny(path_statements)] -#![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] -#![deny(unconditional_recursion)] -#![deny(unused_allocation)] -#![deny(unused_comparisons)] -#![deny(unused_parens)] -#![deny(while_true)] +#![doc = "Peripheral access API for STARFIVE VISIONFIVE 2 V1.3B microcontrollers (generated using svd2rust v0.31.2 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.31.2/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] #![allow(non_camel_case_types)] #![allow(non_snake_case)] #![no_std] @@ -26,6 +12,7 @@ pub mod generic; #[cfg(feature = "rt")] extern "C" {} #[doc(hidden)] +#[repr(C)] pub union Vector { pub _handler: unsafe extern "C" fn(), pub _reserved: usize, diff --git a/jh7110-vf2-13b-pac/src/plic.rs b/jh7110-vf2-13b-pac/src/plic.rs index f319cf6..ee9067d 100644 --- a/jh7110-vf2-13b-pac/src/plic.rs +++ b/jh7110-vf2-13b-pac/src/plic.rs @@ -2,1246 +2,1952 @@ #[repr(C)] pub struct RegisterBlock { _reserved0: [u8; 0x04], + priority_1: PRIORITY_1, + priority_2: PRIORITY_2, + priority_3: PRIORITY_3, + priority_4: PRIORITY_4, + priority_5: PRIORITY_5, + priority_6: PRIORITY_6, + priority_7: PRIORITY_7, + priority_8: PRIORITY_8, + priority_9: PRIORITY_9, + priority_10: PRIORITY_10, + priority_11: PRIORITY_11, + priority_12: PRIORITY_12, + priority_13: PRIORITY_13, + priority_14: PRIORITY_14, + priority_15: PRIORITY_15, + priority_16: PRIORITY_16, + priority_17: PRIORITY_17, + priority_18: PRIORITY_18, + priority_19: PRIORITY_19, + priority_20: PRIORITY_20, + priority_21: PRIORITY_21, + priority_22: PRIORITY_22, + priority_23: PRIORITY_23, + priority_24: PRIORITY_24, + priority_25: PRIORITY_25, + priority_26: PRIORITY_26, + priority_27: PRIORITY_27, + priority_28: PRIORITY_28, + priority_29: PRIORITY_29, + priority_30: PRIORITY_30, + priority_31: PRIORITY_31, + priority_32: PRIORITY_32, + priority_33: PRIORITY_33, + priority_34: PRIORITY_34, + priority_35: PRIORITY_35, + priority_36: PRIORITY_36, + priority_37: PRIORITY_37, + priority_38: PRIORITY_38, + priority_39: PRIORITY_39, + priority_40: PRIORITY_40, + priority_41: PRIORITY_41, + priority_42: PRIORITY_42, + priority_43: PRIORITY_43, + priority_44: PRIORITY_44, + priority_45: PRIORITY_45, + priority_46: PRIORITY_46, + priority_47: PRIORITY_47, + priority_48: PRIORITY_48, + priority_49: PRIORITY_49, + priority_50: PRIORITY_50, + priority_51: PRIORITY_51, + priority_52: PRIORITY_52, + priority_53: PRIORITY_53, + priority_54: PRIORITY_54, + priority_55: PRIORITY_55, + priority_56: PRIORITY_56, + priority_57: PRIORITY_57, + priority_58: PRIORITY_58, + priority_59: PRIORITY_59, + priority_60: PRIORITY_60, + priority_61: PRIORITY_61, + priority_62: PRIORITY_62, + priority_63: PRIORITY_63, + priority_64: PRIORITY_64, + priority_65: PRIORITY_65, + priority_66: PRIORITY_66, + priority_67: PRIORITY_67, + priority_68: PRIORITY_68, + priority_69: PRIORITY_69, + priority_70: PRIORITY_70, + priority_71: PRIORITY_71, + priority_72: PRIORITY_72, + priority_73: PRIORITY_73, + priority_74: PRIORITY_74, + priority_75: PRIORITY_75, + priority_76: PRIORITY_76, + priority_77: PRIORITY_77, + priority_78: PRIORITY_78, + priority_79: PRIORITY_79, + priority_80: PRIORITY_80, + priority_81: PRIORITY_81, + priority_82: PRIORITY_82, + priority_83: PRIORITY_83, + priority_84: PRIORITY_84, + priority_85: PRIORITY_85, + priority_86: PRIORITY_86, + priority_87: PRIORITY_87, + priority_88: PRIORITY_88, + priority_89: PRIORITY_89, + priority_90: PRIORITY_90, + priority_91: PRIORITY_91, + priority_92: PRIORITY_92, + priority_93: PRIORITY_93, + priority_94: PRIORITY_94, + priority_95: PRIORITY_95, + priority_96: PRIORITY_96, + priority_97: PRIORITY_97, + priority_98: PRIORITY_98, + priority_99: PRIORITY_99, + priority_100: PRIORITY_100, + priority_101: PRIORITY_101, + priority_102: PRIORITY_102, + priority_103: PRIORITY_103, + priority_104: PRIORITY_104, + priority_105: PRIORITY_105, + priority_106: PRIORITY_106, + priority_107: PRIORITY_107, + priority_108: PRIORITY_108, + priority_109: PRIORITY_109, + priority_110: PRIORITY_110, + priority_111: PRIORITY_111, + priority_112: PRIORITY_112, + priority_113: PRIORITY_113, + priority_114: PRIORITY_114, + priority_115: PRIORITY_115, + priority_116: PRIORITY_116, + priority_117: PRIORITY_117, + priority_118: PRIORITY_118, + priority_119: PRIORITY_119, + priority_120: PRIORITY_120, + priority_121: PRIORITY_121, + priority_122: PRIORITY_122, + priority_123: PRIORITY_123, + priority_124: PRIORITY_124, + priority_125: PRIORITY_125, + priority_126: PRIORITY_126, + priority_127: PRIORITY_127, + priority_128: PRIORITY_128, + priority_129: PRIORITY_129, + priority_130: PRIORITY_130, + priority_131: PRIORITY_131, + priority_132: PRIORITY_132, + priority_133: PRIORITY_133, + priority_134: PRIORITY_134, + priority_135: PRIORITY_135, + priority_136: PRIORITY_136, + _reserved136: [u8; 0x0ddc], + pending_0: PENDING_0, + pending_1: PENDING_1, + pending_2: PENDING_2, + pending_3: PENDING_3, + pending_4: PENDING_4, + _reserved141: [u8; 0x0fec], + enable_0_0: ENABLE_0_0, + enable_1_0: ENABLE_1_0, + enable_2_0: ENABLE_2_0, + enable_3_0: ENABLE_3_0, + enable_4_0: ENABLE_4_0, + _reserved146: [u8; 0x6c], + enable_0_1: ENABLE_0_1, + enable_1_1: ENABLE_1_1, + enable_2_1: ENABLE_2_1, + enable_3_1: ENABLE_3_1, + enable_4_1: ENABLE_4_1, + _reserved151: [u8; 0x6c], + enable_0_2: ENABLE_0_2, + enable_1_2: ENABLE_1_2, + enable_2_2: ENABLE_2_2, + enable_3_2: ENABLE_3_2, + enable_4_2: ENABLE_4_2, + _reserved156: [u8; 0x6c], + enable_0_3: ENABLE_0_3, + enable_1_3: ENABLE_1_3, + enable_2_3: ENABLE_2_3, + enable_3_3: ENABLE_3_3, + enable_4_3: ENABLE_4_3, + _reserved161: [u8; 0x6c], + enable_0_4: ENABLE_0_4, + enable_1_4: ENABLE_1_4, + enable_2_4: ENABLE_2_4, + enable_3_4: ENABLE_3_4, + enable_4_4: ENABLE_4_4, + _reserved166: [u8; 0x001f_ddec], + threshold_0: THRESHOLD_0, + claimplete_0: CLAIMPLETE_0, + _reserved168: [u8; 0x0ff8], + threshold_1: THRESHOLD_1, + claimplete_1: CLAIMPLETE_1, + _reserved170: [u8; 0x0ff8], + threshold_2: THRESHOLD_2, + claimplete_2: CLAIMPLETE_2, + _reserved172: [u8; 0x0ff8], + threshold_3: THRESHOLD_3, + claimplete_3: CLAIMPLETE_3, + _reserved174: [u8; 0x0ff8], + threshold_4: THRESHOLD_4, + claimplete_4: CLAIMPLETE_4, +} +impl RegisterBlock { #[doc = "0x04 - PRIORITY Register for interrupt id 1"] - pub priority_1: PRIORITY_1, + #[inline(always)] + pub const fn priority_1(&self) -> &PRIORITY_1 { + &self.priority_1 + } #[doc = "0x08 - PRIORITY Register for interrupt id 2"] - pub priority_2: PRIORITY_2, + #[inline(always)] + pub const fn priority_2(&self) -> &PRIORITY_2 { + &self.priority_2 + } #[doc = "0x0c - PRIORITY Register for interrupt id 3"] - pub priority_3: PRIORITY_3, + #[inline(always)] + pub const fn priority_3(&self) -> &PRIORITY_3 { + &self.priority_3 + } #[doc = "0x10 - PRIORITY Register for interrupt id 4"] - pub priority_4: PRIORITY_4, + #[inline(always)] + pub const fn priority_4(&self) -> &PRIORITY_4 { + &self.priority_4 + } #[doc = "0x14 - PRIORITY Register for interrupt id 5"] - pub priority_5: PRIORITY_5, + #[inline(always)] + pub const fn priority_5(&self) -> &PRIORITY_5 { + &self.priority_5 + } #[doc = "0x18 - PRIORITY Register for interrupt id 6"] - pub priority_6: PRIORITY_6, + #[inline(always)] + pub const fn priority_6(&self) -> &PRIORITY_6 { + &self.priority_6 + } #[doc = "0x1c - PRIORITY Register for interrupt id 7"] - pub priority_7: PRIORITY_7, + #[inline(always)] + pub const fn priority_7(&self) -> &PRIORITY_7 { + &self.priority_7 + } #[doc = "0x20 - PRIORITY Register for interrupt id 8"] - pub priority_8: PRIORITY_8, + #[inline(always)] + pub const fn priority_8(&self) -> &PRIORITY_8 { + &self.priority_8 + } #[doc = "0x24 - PRIORITY Register for interrupt id 9"] - pub priority_9: PRIORITY_9, + #[inline(always)] + pub const fn priority_9(&self) -> &PRIORITY_9 { + &self.priority_9 + } #[doc = "0x28 - PRIORITY Register for interrupt id 10"] - pub priority_10: PRIORITY_10, + #[inline(always)] + pub const fn priority_10(&self) -> &PRIORITY_10 { + &self.priority_10 + } #[doc = "0x2c - PRIORITY Register for interrupt id 11"] - pub priority_11: PRIORITY_11, + #[inline(always)] + pub const fn priority_11(&self) -> &PRIORITY_11 { + &self.priority_11 + } #[doc = "0x30 - PRIORITY Register for interrupt id 12"] - pub priority_12: PRIORITY_12, + #[inline(always)] + pub const fn priority_12(&self) -> &PRIORITY_12 { + &self.priority_12 + } #[doc = "0x34 - PRIORITY Register for interrupt id 13"] - pub priority_13: PRIORITY_13, + #[inline(always)] + pub const fn priority_13(&self) -> &PRIORITY_13 { + &self.priority_13 + } #[doc = "0x38 - PRIORITY Register for interrupt id 14"] - pub priority_14: PRIORITY_14, + #[inline(always)] + pub const fn priority_14(&self) -> &PRIORITY_14 { + &self.priority_14 + } #[doc = "0x3c - PRIORITY Register for interrupt id 15"] - pub priority_15: PRIORITY_15, + #[inline(always)] + pub const fn priority_15(&self) -> &PRIORITY_15 { + &self.priority_15 + } #[doc = "0x40 - PRIORITY Register for interrupt id 16"] - pub priority_16: PRIORITY_16, + #[inline(always)] + pub const fn priority_16(&self) -> &PRIORITY_16 { + &self.priority_16 + } #[doc = "0x44 - PRIORITY Register for interrupt id 17"] - pub priority_17: PRIORITY_17, + #[inline(always)] + pub const fn priority_17(&self) -> &PRIORITY_17 { + &self.priority_17 + } #[doc = "0x48 - PRIORITY Register for interrupt id 18"] - pub priority_18: PRIORITY_18, + #[inline(always)] + pub const fn priority_18(&self) -> &PRIORITY_18 { + &self.priority_18 + } #[doc = "0x4c - PRIORITY Register for interrupt id 19"] - pub priority_19: PRIORITY_19, + #[inline(always)] + pub const fn priority_19(&self) -> &PRIORITY_19 { + &self.priority_19 + } #[doc = "0x50 - PRIORITY Register for interrupt id 20"] - pub priority_20: PRIORITY_20, + #[inline(always)] + pub const fn priority_20(&self) -> &PRIORITY_20 { + &self.priority_20 + } #[doc = "0x54 - PRIORITY Register for interrupt id 21"] - pub priority_21: PRIORITY_21, + #[inline(always)] + pub const fn priority_21(&self) -> &PRIORITY_21 { + &self.priority_21 + } #[doc = "0x58 - PRIORITY Register for interrupt id 22"] - pub priority_22: PRIORITY_22, + #[inline(always)] + pub const fn priority_22(&self) -> &PRIORITY_22 { + &self.priority_22 + } #[doc = "0x5c - PRIORITY Register for interrupt id 23"] - pub priority_23: PRIORITY_23, + #[inline(always)] + pub const fn priority_23(&self) -> &PRIORITY_23 { + &self.priority_23 + } #[doc = "0x60 - PRIORITY Register for interrupt id 24"] - pub priority_24: PRIORITY_24, + #[inline(always)] + pub const fn priority_24(&self) -> &PRIORITY_24 { + &self.priority_24 + } #[doc = "0x64 - PRIORITY Register for interrupt id 25"] - pub priority_25: PRIORITY_25, + #[inline(always)] + pub const fn priority_25(&self) -> &PRIORITY_25 { + &self.priority_25 + } #[doc = "0x68 - PRIORITY Register for interrupt id 26"] - pub priority_26: PRIORITY_26, + #[inline(always)] + pub const fn priority_26(&self) -> &PRIORITY_26 { + &self.priority_26 + } #[doc = "0x6c - PRIORITY Register for interrupt id 27"] - pub priority_27: PRIORITY_27, + #[inline(always)] + pub const fn priority_27(&self) -> &PRIORITY_27 { + &self.priority_27 + } #[doc = "0x70 - PRIORITY Register for interrupt id 28"] - pub priority_28: PRIORITY_28, + #[inline(always)] + pub const fn priority_28(&self) -> &PRIORITY_28 { + &self.priority_28 + } #[doc = "0x74 - PRIORITY Register for interrupt id 29"] - pub priority_29: PRIORITY_29, + #[inline(always)] + pub const fn priority_29(&self) -> &PRIORITY_29 { + &self.priority_29 + } #[doc = "0x78 - PRIORITY Register for interrupt id 30"] - pub priority_30: PRIORITY_30, + #[inline(always)] + pub const fn priority_30(&self) -> &PRIORITY_30 { + &self.priority_30 + } #[doc = "0x7c - PRIORITY Register for interrupt id 31"] - pub priority_31: PRIORITY_31, + #[inline(always)] + pub const fn priority_31(&self) -> &PRIORITY_31 { + &self.priority_31 + } #[doc = "0x80 - PRIORITY Register for interrupt id 32"] - pub priority_32: PRIORITY_32, + #[inline(always)] + pub const fn priority_32(&self) -> &PRIORITY_32 { + &self.priority_32 + } #[doc = "0x84 - PRIORITY Register for interrupt id 33"] - pub priority_33: PRIORITY_33, + #[inline(always)] + pub const fn priority_33(&self) -> &PRIORITY_33 { + &self.priority_33 + } #[doc = "0x88 - PRIORITY Register for interrupt id 34"] - pub priority_34: PRIORITY_34, + #[inline(always)] + pub const fn priority_34(&self) -> &PRIORITY_34 { + &self.priority_34 + } #[doc = "0x8c - PRIORITY Register for interrupt id 35"] - pub priority_35: PRIORITY_35, + #[inline(always)] + pub const fn priority_35(&self) -> &PRIORITY_35 { + &self.priority_35 + } #[doc = "0x90 - PRIORITY Register for interrupt id 36"] - pub priority_36: PRIORITY_36, + #[inline(always)] + pub const fn priority_36(&self) -> &PRIORITY_36 { + &self.priority_36 + } #[doc = "0x94 - PRIORITY Register for interrupt id 37"] - pub priority_37: PRIORITY_37, + #[inline(always)] + pub const fn priority_37(&self) -> &PRIORITY_37 { + &self.priority_37 + } #[doc = "0x98 - PRIORITY Register for interrupt id 38"] - pub priority_38: PRIORITY_38, + #[inline(always)] + pub const fn priority_38(&self) -> &PRIORITY_38 { + &self.priority_38 + } #[doc = "0x9c - PRIORITY Register for interrupt id 39"] - pub priority_39: PRIORITY_39, + #[inline(always)] + pub const fn priority_39(&self) -> &PRIORITY_39 { + &self.priority_39 + } #[doc = "0xa0 - PRIORITY Register for interrupt id 40"] - pub priority_40: PRIORITY_40, + #[inline(always)] + pub const fn priority_40(&self) -> &PRIORITY_40 { + &self.priority_40 + } #[doc = "0xa4 - PRIORITY Register for interrupt id 41"] - pub priority_41: PRIORITY_41, + #[inline(always)] + pub const fn priority_41(&self) -> &PRIORITY_41 { + &self.priority_41 + } #[doc = "0xa8 - PRIORITY Register for interrupt id 42"] - pub priority_42: PRIORITY_42, + #[inline(always)] + pub const fn priority_42(&self) -> &PRIORITY_42 { + &self.priority_42 + } #[doc = "0xac - PRIORITY Register for interrupt id 43"] - pub priority_43: PRIORITY_43, + #[inline(always)] + pub const fn priority_43(&self) -> &PRIORITY_43 { + &self.priority_43 + } #[doc = "0xb0 - PRIORITY Register for interrupt id 44"] - pub priority_44: PRIORITY_44, + #[inline(always)] + pub const fn priority_44(&self) -> &PRIORITY_44 { + &self.priority_44 + } #[doc = "0xb4 - PRIORITY Register for interrupt id 45"] - pub priority_45: PRIORITY_45, + #[inline(always)] + pub const fn priority_45(&self) -> &PRIORITY_45 { + &self.priority_45 + } #[doc = "0xb8 - PRIORITY Register for interrupt id 46"] - pub priority_46: PRIORITY_46, + #[inline(always)] + pub const fn priority_46(&self) -> &PRIORITY_46 { + &self.priority_46 + } #[doc = "0xbc - PRIORITY Register for interrupt id 47"] - pub priority_47: PRIORITY_47, + #[inline(always)] + pub const fn priority_47(&self) -> &PRIORITY_47 { + &self.priority_47 + } #[doc = "0xc0 - PRIORITY Register for interrupt id 48"] - pub priority_48: PRIORITY_48, + #[inline(always)] + pub const fn priority_48(&self) -> &PRIORITY_48 { + &self.priority_48 + } #[doc = "0xc4 - PRIORITY Register for interrupt id 49"] - pub priority_49: PRIORITY_49, + #[inline(always)] + pub const fn priority_49(&self) -> &PRIORITY_49 { + &self.priority_49 + } #[doc = "0xc8 - PRIORITY Register for interrupt id 50"] - pub priority_50: PRIORITY_50, + #[inline(always)] + pub const fn priority_50(&self) -> &PRIORITY_50 { + &self.priority_50 + } #[doc = "0xcc - PRIORITY Register for interrupt id 51"] - pub priority_51: PRIORITY_51, + #[inline(always)] + pub const fn priority_51(&self) -> &PRIORITY_51 { + &self.priority_51 + } #[doc = "0xd0 - PRIORITY Register for interrupt id 52"] - pub priority_52: PRIORITY_52, + #[inline(always)] + pub const fn priority_52(&self) -> &PRIORITY_52 { + &self.priority_52 + } #[doc = "0xd4 - PRIORITY Register for interrupt id 53"] - pub priority_53: PRIORITY_53, + #[inline(always)] + pub const fn priority_53(&self) -> &PRIORITY_53 { + &self.priority_53 + } #[doc = "0xd8 - PRIORITY Register for interrupt id 54"] - pub priority_54: PRIORITY_54, + #[inline(always)] + pub const fn priority_54(&self) -> &PRIORITY_54 { + &self.priority_54 + } #[doc = "0xdc - PRIORITY Register for interrupt id 55"] - pub priority_55: PRIORITY_55, + #[inline(always)] + pub const fn priority_55(&self) -> &PRIORITY_55 { + &self.priority_55 + } #[doc = "0xe0 - PRIORITY Register for interrupt id 56"] - pub priority_56: PRIORITY_56, + #[inline(always)] + pub const fn priority_56(&self) -> &PRIORITY_56 { + &self.priority_56 + } #[doc = "0xe4 - PRIORITY Register for interrupt id 57"] - pub priority_57: PRIORITY_57, + #[inline(always)] + pub const fn priority_57(&self) -> &PRIORITY_57 { + &self.priority_57 + } #[doc = "0xe8 - PRIORITY Register for interrupt id 58"] - pub priority_58: PRIORITY_58, + #[inline(always)] + pub const fn priority_58(&self) -> &PRIORITY_58 { + &self.priority_58 + } #[doc = "0xec - PRIORITY Register for interrupt id 59"] - pub priority_59: PRIORITY_59, + #[inline(always)] + pub const fn priority_59(&self) -> &PRIORITY_59 { + &self.priority_59 + } #[doc = "0xf0 - PRIORITY Register for interrupt id 60"] - pub priority_60: PRIORITY_60, + #[inline(always)] + pub const fn priority_60(&self) -> &PRIORITY_60 { + &self.priority_60 + } #[doc = "0xf4 - PRIORITY Register for interrupt id 61"] - pub priority_61: PRIORITY_61, + #[inline(always)] + pub const fn priority_61(&self) -> &PRIORITY_61 { + &self.priority_61 + } #[doc = "0xf8 - PRIORITY Register for interrupt id 62"] - pub priority_62: PRIORITY_62, + #[inline(always)] + pub const fn priority_62(&self) -> &PRIORITY_62 { + &self.priority_62 + } #[doc = "0xfc - PRIORITY Register for interrupt id 63"] - pub priority_63: PRIORITY_63, + #[inline(always)] + pub const fn priority_63(&self) -> &PRIORITY_63 { + &self.priority_63 + } #[doc = "0x100 - PRIORITY Register for interrupt id 64"] - pub priority_64: PRIORITY_64, + #[inline(always)] + pub const fn priority_64(&self) -> &PRIORITY_64 { + &self.priority_64 + } #[doc = "0x104 - PRIORITY Register for interrupt id 65"] - pub priority_65: PRIORITY_65, + #[inline(always)] + pub const fn priority_65(&self) -> &PRIORITY_65 { + &self.priority_65 + } #[doc = "0x108 - PRIORITY Register for interrupt id 66"] - pub priority_66: PRIORITY_66, + #[inline(always)] + pub const fn priority_66(&self) -> &PRIORITY_66 { + &self.priority_66 + } #[doc = "0x10c - PRIORITY Register for interrupt id 67"] - pub priority_67: PRIORITY_67, + #[inline(always)] + pub const fn priority_67(&self) -> &PRIORITY_67 { + &self.priority_67 + } #[doc = "0x110 - PRIORITY Register for interrupt id 68"] - pub priority_68: PRIORITY_68, + #[inline(always)] + pub const fn priority_68(&self) -> &PRIORITY_68 { + &self.priority_68 + } #[doc = "0x114 - PRIORITY Register for interrupt id 69"] - pub priority_69: PRIORITY_69, + #[inline(always)] + pub const fn priority_69(&self) -> &PRIORITY_69 { + &self.priority_69 + } #[doc = "0x118 - PRIORITY Register for interrupt id 70"] - pub priority_70: PRIORITY_70, + #[inline(always)] + pub const fn priority_70(&self) -> &PRIORITY_70 { + &self.priority_70 + } #[doc = "0x11c - PRIORITY Register for interrupt id 71"] - pub priority_71: PRIORITY_71, + #[inline(always)] + pub const fn priority_71(&self) -> &PRIORITY_71 { + &self.priority_71 + } #[doc = "0x120 - PRIORITY Register for interrupt id 72"] - pub priority_72: PRIORITY_72, + #[inline(always)] + pub const fn priority_72(&self) -> &PRIORITY_72 { + &self.priority_72 + } #[doc = "0x124 - PRIORITY Register for interrupt id 73"] - pub priority_73: PRIORITY_73, + #[inline(always)] + pub const fn priority_73(&self) -> &PRIORITY_73 { + &self.priority_73 + } #[doc = "0x128 - PRIORITY Register for interrupt id 74"] - pub priority_74: PRIORITY_74, + #[inline(always)] + pub const fn priority_74(&self) -> &PRIORITY_74 { + &self.priority_74 + } #[doc = "0x12c - PRIORITY Register for interrupt id 75"] - pub priority_75: PRIORITY_75, + #[inline(always)] + pub const fn priority_75(&self) -> &PRIORITY_75 { + &self.priority_75 + } #[doc = "0x130 - PRIORITY Register for interrupt id 76"] - pub priority_76: PRIORITY_76, + #[inline(always)] + pub const fn priority_76(&self) -> &PRIORITY_76 { + &self.priority_76 + } #[doc = "0x134 - PRIORITY Register for interrupt id 77"] - pub priority_77: PRIORITY_77, + #[inline(always)] + pub const fn priority_77(&self) -> &PRIORITY_77 { + &self.priority_77 + } #[doc = "0x138 - PRIORITY Register for interrupt id 78"] - pub priority_78: PRIORITY_78, + #[inline(always)] + pub const fn priority_78(&self) -> &PRIORITY_78 { + &self.priority_78 + } #[doc = "0x13c - PRIORITY Register for interrupt id 79"] - pub priority_79: PRIORITY_79, + #[inline(always)] + pub const fn priority_79(&self) -> &PRIORITY_79 { + &self.priority_79 + } #[doc = "0x140 - PRIORITY Register for interrupt id 80"] - pub priority_80: PRIORITY_80, + #[inline(always)] + pub const fn priority_80(&self) -> &PRIORITY_80 { + &self.priority_80 + } #[doc = "0x144 - PRIORITY Register for interrupt id 81"] - pub priority_81: PRIORITY_81, + #[inline(always)] + pub const fn priority_81(&self) -> &PRIORITY_81 { + &self.priority_81 + } #[doc = "0x148 - PRIORITY Register for interrupt id 82"] - pub priority_82: PRIORITY_82, + #[inline(always)] + pub const fn priority_82(&self) -> &PRIORITY_82 { + &self.priority_82 + } #[doc = "0x14c - PRIORITY Register for interrupt id 83"] - pub priority_83: PRIORITY_83, + #[inline(always)] + pub const fn priority_83(&self) -> &PRIORITY_83 { + &self.priority_83 + } #[doc = "0x150 - PRIORITY Register for interrupt id 84"] - pub priority_84: PRIORITY_84, + #[inline(always)] + pub const fn priority_84(&self) -> &PRIORITY_84 { + &self.priority_84 + } #[doc = "0x154 - PRIORITY Register for interrupt id 85"] - pub priority_85: PRIORITY_85, + #[inline(always)] + pub const fn priority_85(&self) -> &PRIORITY_85 { + &self.priority_85 + } #[doc = "0x158 - PRIORITY Register for interrupt id 86"] - pub priority_86: PRIORITY_86, + #[inline(always)] + pub const fn priority_86(&self) -> &PRIORITY_86 { + &self.priority_86 + } #[doc = "0x15c - PRIORITY Register for interrupt id 87"] - pub priority_87: PRIORITY_87, + #[inline(always)] + pub const fn priority_87(&self) -> &PRIORITY_87 { + &self.priority_87 + } #[doc = "0x160 - PRIORITY Register for interrupt id 88"] - pub priority_88: PRIORITY_88, + #[inline(always)] + pub const fn priority_88(&self) -> &PRIORITY_88 { + &self.priority_88 + } #[doc = "0x164 - PRIORITY Register for interrupt id 89"] - pub priority_89: PRIORITY_89, + #[inline(always)] + pub const fn priority_89(&self) -> &PRIORITY_89 { + &self.priority_89 + } #[doc = "0x168 - PRIORITY Register for interrupt id 90"] - pub priority_90: PRIORITY_90, + #[inline(always)] + pub const fn priority_90(&self) -> &PRIORITY_90 { + &self.priority_90 + } #[doc = "0x16c - PRIORITY Register for interrupt id 91"] - pub priority_91: PRIORITY_91, + #[inline(always)] + pub const fn priority_91(&self) -> &PRIORITY_91 { + &self.priority_91 + } #[doc = "0x170 - PRIORITY Register for interrupt id 92"] - pub priority_92: PRIORITY_92, + #[inline(always)] + pub const fn priority_92(&self) -> &PRIORITY_92 { + &self.priority_92 + } #[doc = "0x174 - PRIORITY Register for interrupt id 93"] - pub priority_93: PRIORITY_93, + #[inline(always)] + pub const fn priority_93(&self) -> &PRIORITY_93 { + &self.priority_93 + } #[doc = "0x178 - PRIORITY Register for interrupt id 94"] - pub priority_94: PRIORITY_94, + #[inline(always)] + pub const fn priority_94(&self) -> &PRIORITY_94 { + &self.priority_94 + } #[doc = "0x17c - PRIORITY Register for interrupt id 95"] - pub priority_95: PRIORITY_95, + #[inline(always)] + pub const fn priority_95(&self) -> &PRIORITY_95 { + &self.priority_95 + } #[doc = "0x180 - PRIORITY Register for interrupt id 96"] - pub priority_96: PRIORITY_96, + #[inline(always)] + pub const fn priority_96(&self) -> &PRIORITY_96 { + &self.priority_96 + } #[doc = "0x184 - PRIORITY Register for interrupt id 97"] - pub priority_97: PRIORITY_97, + #[inline(always)] + pub const fn priority_97(&self) -> &PRIORITY_97 { + &self.priority_97 + } #[doc = "0x188 - PRIORITY Register for interrupt id 98"] - pub priority_98: PRIORITY_98, + #[inline(always)] + pub const fn priority_98(&self) -> &PRIORITY_98 { + &self.priority_98 + } #[doc = "0x18c - PRIORITY Register for interrupt id 99"] - pub priority_99: PRIORITY_99, + #[inline(always)] + pub const fn priority_99(&self) -> &PRIORITY_99 { + &self.priority_99 + } #[doc = "0x190 - PRIORITY Register for interrupt id 100"] - pub priority_100: PRIORITY_100, + #[inline(always)] + pub const fn priority_100(&self) -> &PRIORITY_100 { + &self.priority_100 + } #[doc = "0x194 - PRIORITY Register for interrupt id 101"] - pub priority_101: PRIORITY_101, + #[inline(always)] + pub const fn priority_101(&self) -> &PRIORITY_101 { + &self.priority_101 + } #[doc = "0x198 - PRIORITY Register for interrupt id 102"] - pub priority_102: PRIORITY_102, + #[inline(always)] + pub const fn priority_102(&self) -> &PRIORITY_102 { + &self.priority_102 + } #[doc = "0x19c - PRIORITY Register for interrupt id 103"] - pub priority_103: PRIORITY_103, + #[inline(always)] + pub const fn priority_103(&self) -> &PRIORITY_103 { + &self.priority_103 + } #[doc = "0x1a0 - PRIORITY Register for interrupt id 104"] - pub priority_104: PRIORITY_104, + #[inline(always)] + pub const fn priority_104(&self) -> &PRIORITY_104 { + &self.priority_104 + } #[doc = "0x1a4 - PRIORITY Register for interrupt id 105"] - pub priority_105: PRIORITY_105, + #[inline(always)] + pub const fn priority_105(&self) -> &PRIORITY_105 { + &self.priority_105 + } #[doc = "0x1a8 - PRIORITY Register for interrupt id 106"] - pub priority_106: PRIORITY_106, + #[inline(always)] + pub const fn priority_106(&self) -> &PRIORITY_106 { + &self.priority_106 + } #[doc = "0x1ac - PRIORITY Register for interrupt id 107"] - pub priority_107: PRIORITY_107, + #[inline(always)] + pub const fn priority_107(&self) -> &PRIORITY_107 { + &self.priority_107 + } #[doc = "0x1b0 - PRIORITY Register for interrupt id 108"] - pub priority_108: PRIORITY_108, + #[inline(always)] + pub const fn priority_108(&self) -> &PRIORITY_108 { + &self.priority_108 + } #[doc = "0x1b4 - PRIORITY Register for interrupt id 109"] - pub priority_109: PRIORITY_109, + #[inline(always)] + pub const fn priority_109(&self) -> &PRIORITY_109 { + &self.priority_109 + } #[doc = "0x1b8 - PRIORITY Register for interrupt id 110"] - pub priority_110: PRIORITY_110, + #[inline(always)] + pub const fn priority_110(&self) -> &PRIORITY_110 { + &self.priority_110 + } #[doc = "0x1bc - PRIORITY Register for interrupt id 111"] - pub priority_111: PRIORITY_111, + #[inline(always)] + pub const fn priority_111(&self) -> &PRIORITY_111 { + &self.priority_111 + } #[doc = "0x1c0 - PRIORITY Register for interrupt id 112"] - pub priority_112: PRIORITY_112, + #[inline(always)] + pub const fn priority_112(&self) -> &PRIORITY_112 { + &self.priority_112 + } #[doc = "0x1c4 - PRIORITY Register for interrupt id 113"] - pub priority_113: PRIORITY_113, + #[inline(always)] + pub const fn priority_113(&self) -> &PRIORITY_113 { + &self.priority_113 + } #[doc = "0x1c8 - PRIORITY Register for interrupt id 114"] - pub priority_114: PRIORITY_114, + #[inline(always)] + pub const fn priority_114(&self) -> &PRIORITY_114 { + &self.priority_114 + } #[doc = "0x1cc - PRIORITY Register for interrupt id 115"] - pub priority_115: PRIORITY_115, + #[inline(always)] + pub const fn priority_115(&self) -> &PRIORITY_115 { + &self.priority_115 + } #[doc = "0x1d0 - PRIORITY Register for interrupt id 116"] - pub priority_116: PRIORITY_116, + #[inline(always)] + pub const fn priority_116(&self) -> &PRIORITY_116 { + &self.priority_116 + } #[doc = "0x1d4 - PRIORITY Register for interrupt id 117"] - pub priority_117: PRIORITY_117, + #[inline(always)] + pub const fn priority_117(&self) -> &PRIORITY_117 { + &self.priority_117 + } #[doc = "0x1d8 - PRIORITY Register for interrupt id 118"] - pub priority_118: PRIORITY_118, + #[inline(always)] + pub const fn priority_118(&self) -> &PRIORITY_118 { + &self.priority_118 + } #[doc = "0x1dc - PRIORITY Register for interrupt id 119"] - pub priority_119: PRIORITY_119, + #[inline(always)] + pub const fn priority_119(&self) -> &PRIORITY_119 { + &self.priority_119 + } #[doc = "0x1e0 - PRIORITY Register for interrupt id 120"] - pub priority_120: PRIORITY_120, + #[inline(always)] + pub const fn priority_120(&self) -> &PRIORITY_120 { + &self.priority_120 + } #[doc = "0x1e4 - PRIORITY Register for interrupt id 121"] - pub priority_121: PRIORITY_121, + #[inline(always)] + pub const fn priority_121(&self) -> &PRIORITY_121 { + &self.priority_121 + } #[doc = "0x1e8 - PRIORITY Register for interrupt id 122"] - pub priority_122: PRIORITY_122, + #[inline(always)] + pub const fn priority_122(&self) -> &PRIORITY_122 { + &self.priority_122 + } #[doc = "0x1ec - PRIORITY Register for interrupt id 123"] - pub priority_123: PRIORITY_123, + #[inline(always)] + pub const fn priority_123(&self) -> &PRIORITY_123 { + &self.priority_123 + } #[doc = "0x1f0 - PRIORITY Register for interrupt id 124"] - pub priority_124: PRIORITY_124, + #[inline(always)] + pub const fn priority_124(&self) -> &PRIORITY_124 { + &self.priority_124 + } #[doc = "0x1f4 - PRIORITY Register for interrupt id 125"] - pub priority_125: PRIORITY_125, + #[inline(always)] + pub const fn priority_125(&self) -> &PRIORITY_125 { + &self.priority_125 + } #[doc = "0x1f8 - PRIORITY Register for interrupt id 126"] - pub priority_126: PRIORITY_126, + #[inline(always)] + pub const fn priority_126(&self) -> &PRIORITY_126 { + &self.priority_126 + } #[doc = "0x1fc - PRIORITY Register for interrupt id 127"] - pub priority_127: PRIORITY_127, + #[inline(always)] + pub const fn priority_127(&self) -> &PRIORITY_127 { + &self.priority_127 + } #[doc = "0x200 - PRIORITY Register for interrupt id 128"] - pub priority_128: PRIORITY_128, + #[inline(always)] + pub const fn priority_128(&self) -> &PRIORITY_128 { + &self.priority_128 + } #[doc = "0x204 - PRIORITY Register for interrupt id 129"] - pub priority_129: PRIORITY_129, + #[inline(always)] + pub const fn priority_129(&self) -> &PRIORITY_129 { + &self.priority_129 + } #[doc = "0x208 - PRIORITY Register for interrupt id 130"] - pub priority_130: PRIORITY_130, + #[inline(always)] + pub const fn priority_130(&self) -> &PRIORITY_130 { + &self.priority_130 + } #[doc = "0x20c - PRIORITY Register for interrupt id 131"] - pub priority_131: PRIORITY_131, + #[inline(always)] + pub const fn priority_131(&self) -> &PRIORITY_131 { + &self.priority_131 + } #[doc = "0x210 - PRIORITY Register for interrupt id 132"] - pub priority_132: PRIORITY_132, + #[inline(always)] + pub const fn priority_132(&self) -> &PRIORITY_132 { + &self.priority_132 + } #[doc = "0x214 - PRIORITY Register for interrupt id 133"] - pub priority_133: PRIORITY_133, + #[inline(always)] + pub const fn priority_133(&self) -> &PRIORITY_133 { + &self.priority_133 + } #[doc = "0x218 - PRIORITY Register for interrupt id 134"] - pub priority_134: PRIORITY_134, + #[inline(always)] + pub const fn priority_134(&self) -> &PRIORITY_134 { + &self.priority_134 + } #[doc = "0x21c - PRIORITY Register for interrupt id 135"] - pub priority_135: PRIORITY_135, + #[inline(always)] + pub const fn priority_135(&self) -> &PRIORITY_135 { + &self.priority_135 + } #[doc = "0x220 - PRIORITY Register for interrupt id 136"] - pub priority_136: PRIORITY_136, - _reserved136: [u8; 0x0ddc], + #[inline(always)] + pub const fn priority_136(&self) -> &PRIORITY_136 { + &self.priority_136 + } #[doc = "0x1000 - PENDING Register for interrupt ids 31 to 0"] - pub pending_0: PENDING_0, + #[inline(always)] + pub const fn pending_0(&self) -> &PENDING_0 { + &self.pending_0 + } #[doc = "0x1004 - PENDING Register for interrupt ids 63 to 32"] - pub pending_1: PENDING_1, + #[inline(always)] + pub const fn pending_1(&self) -> &PENDING_1 { + &self.pending_1 + } #[doc = "0x1008 - PENDING Register for interrupt ids 95 to 64"] - pub pending_2: PENDING_2, + #[inline(always)] + pub const fn pending_2(&self) -> &PENDING_2 { + &self.pending_2 + } #[doc = "0x100c - PENDING Register for interrupt ids 127 to 96"] - pub pending_3: PENDING_3, + #[inline(always)] + pub const fn pending_3(&self) -> &PENDING_3 { + &self.pending_3 + } #[doc = "0x1010 - PENDING Register for interrupt ids 136 to 128"] - pub pending_4: PENDING_4, - _reserved141: [u8; 0x0fec], + #[inline(always)] + pub const fn pending_4(&self) -> &PENDING_4 { + &self.pending_4 + } #[doc = "0x2000 - ENABLE Register for interrupt ids 31 to 0 for hart 0"] - pub enable_0_0: ENABLE_0_0, + #[inline(always)] + pub const fn enable_0_0(&self) -> &ENABLE_0_0 { + &self.enable_0_0 + } #[doc = "0x2004 - ENABLE Register for interrupt ids 63 to 32 for hart 0"] - pub enable_1_0: ENABLE_1_0, + #[inline(always)] + pub const fn enable_1_0(&self) -> &ENABLE_1_0 { + &self.enable_1_0 + } #[doc = "0x2008 - ENABLE Register for interrupt ids 95 to 64 for hart 0"] - pub enable_2_0: ENABLE_2_0, + #[inline(always)] + pub const fn enable_2_0(&self) -> &ENABLE_2_0 { + &self.enable_2_0 + } #[doc = "0x200c - ENABLE Register for interrupt ids 127 to 96 for hart 0"] - pub enable_3_0: ENABLE_3_0, + #[inline(always)] + pub const fn enable_3_0(&self) -> &ENABLE_3_0 { + &self.enable_3_0 + } #[doc = "0x2010 - ENABLE Register for interrupt ids 136 to 128 for hart 0"] - pub enable_4_0: ENABLE_4_0, - _reserved146: [u8; 0x6c], + #[inline(always)] + pub const fn enable_4_0(&self) -> &ENABLE_4_0 { + &self.enable_4_0 + } #[doc = "0x2080 - ENABLE Register for interrupt ids 31 to 0 for hart 1"] - pub enable_0_1: ENABLE_0_1, + #[inline(always)] + pub const fn enable_0_1(&self) -> &ENABLE_0_1 { + &self.enable_0_1 + } #[doc = "0x2084 - ENABLE Register for interrupt ids 63 to 32 for hart 1"] - pub enable_1_1: ENABLE_1_1, + #[inline(always)] + pub const fn enable_1_1(&self) -> &ENABLE_1_1 { + &self.enable_1_1 + } #[doc = "0x2088 - ENABLE Register for interrupt ids 95 to 64 for hart 1"] - pub enable_2_1: ENABLE_2_1, + #[inline(always)] + pub const fn enable_2_1(&self) -> &ENABLE_2_1 { + &self.enable_2_1 + } #[doc = "0x208c - ENABLE Register for interrupt ids 127 to 96 for hart 1"] - pub enable_3_1: ENABLE_3_1, + #[inline(always)] + pub const fn enable_3_1(&self) -> &ENABLE_3_1 { + &self.enable_3_1 + } #[doc = "0x2090 - ENABLE Register for interrupt ids 136 to 128 for hart 1"] - pub enable_4_1: ENABLE_4_1, - _reserved151: [u8; 0x6c], + #[inline(always)] + pub const fn enable_4_1(&self) -> &ENABLE_4_1 { + &self.enable_4_1 + } #[doc = "0x2100 - ENABLE Register for interrupt ids 31 to 0 for hart 2"] - pub enable_0_2: ENABLE_0_2, + #[inline(always)] + pub const fn enable_0_2(&self) -> &ENABLE_0_2 { + &self.enable_0_2 + } #[doc = "0x2104 - ENABLE Register for interrupt ids 63 to 32 for hart 2"] - pub enable_1_2: ENABLE_1_2, + #[inline(always)] + pub const fn enable_1_2(&self) -> &ENABLE_1_2 { + &self.enable_1_2 + } #[doc = "0x2108 - ENABLE Register for interrupt ids 95 to 64 for hart 2"] - pub enable_2_2: ENABLE_2_2, + #[inline(always)] + pub const fn enable_2_2(&self) -> &ENABLE_2_2 { + &self.enable_2_2 + } #[doc = "0x210c - ENABLE Register for interrupt ids 127 to 96 for hart 2"] - pub enable_3_2: ENABLE_3_2, + #[inline(always)] + pub const fn enable_3_2(&self) -> &ENABLE_3_2 { + &self.enable_3_2 + } #[doc = "0x2110 - ENABLE Register for interrupt ids 136 to 128 for hart 2"] - pub enable_4_2: ENABLE_4_2, - _reserved156: [u8; 0x6c], + #[inline(always)] + pub const fn enable_4_2(&self) -> &ENABLE_4_2 { + &self.enable_4_2 + } #[doc = "0x2180 - ENABLE Register for interrupt ids 31 to 0 for hart 3"] - pub enable_0_3: ENABLE_0_3, + #[inline(always)] + pub const fn enable_0_3(&self) -> &ENABLE_0_3 { + &self.enable_0_3 + } #[doc = "0x2184 - ENABLE Register for interrupt ids 63 to 32 for hart 3"] - pub enable_1_3: ENABLE_1_3, + #[inline(always)] + pub const fn enable_1_3(&self) -> &ENABLE_1_3 { + &self.enable_1_3 + } #[doc = "0x2188 - ENABLE Register for interrupt ids 95 to 64 for hart 3"] - pub enable_2_3: ENABLE_2_3, + #[inline(always)] + pub const fn enable_2_3(&self) -> &ENABLE_2_3 { + &self.enable_2_3 + } #[doc = "0x218c - ENABLE Register for interrupt ids 127 to 96 for hart 3"] - pub enable_3_3: ENABLE_3_3, + #[inline(always)] + pub const fn enable_3_3(&self) -> &ENABLE_3_3 { + &self.enable_3_3 + } #[doc = "0x2190 - ENABLE Register for interrupt ids 136 to 128 for hart 3"] - pub enable_4_3: ENABLE_4_3, - _reserved161: [u8; 0x6c], + #[inline(always)] + pub const fn enable_4_3(&self) -> &ENABLE_4_3 { + &self.enable_4_3 + } #[doc = "0x2200 - ENABLE Register for interrupt ids 31 to 0 for hart 4"] - pub enable_0_4: ENABLE_0_4, + #[inline(always)] + pub const fn enable_0_4(&self) -> &ENABLE_0_4 { + &self.enable_0_4 + } #[doc = "0x2204 - ENABLE Register for interrupt ids 63 to 32 for hart 4"] - pub enable_1_4: ENABLE_1_4, + #[inline(always)] + pub const fn enable_1_4(&self) -> &ENABLE_1_4 { + &self.enable_1_4 + } #[doc = "0x2208 - ENABLE Register for interrupt ids 95 to 64 for hart 4"] - pub enable_2_4: ENABLE_2_4, + #[inline(always)] + pub const fn enable_2_4(&self) -> &ENABLE_2_4 { + &self.enable_2_4 + } #[doc = "0x220c - ENABLE Register for interrupt ids 127 to 96 for hart 4"] - pub enable_3_4: ENABLE_3_4, + #[inline(always)] + pub const fn enable_3_4(&self) -> &ENABLE_3_4 { + &self.enable_3_4 + } #[doc = "0x2210 - ENABLE Register for interrupt ids 136 to 128 for hart 4"] - pub enable_4_4: ENABLE_4_4, - _reserved166: [u8; 0x001f_ddec], + #[inline(always)] + pub const fn enable_4_4(&self) -> &ENABLE_4_4 { + &self.enable_4_4 + } #[doc = "0x200000 - PRIORITY THRESHOLD Register for hart 0"] - pub threshold_0: THRESHOLD_0, + #[inline(always)] + pub const fn threshold_0(&self) -> &THRESHOLD_0 { + &self.threshold_0 + } #[doc = "0x200004 - CLAIM and COMPLETE Register for hart 0"] - pub claimplete_0: CLAIMPLETE_0, - _reserved168: [u8; 0x0ff8], + #[inline(always)] + pub const fn claimplete_0(&self) -> &CLAIMPLETE_0 { + &self.claimplete_0 + } #[doc = "0x201000 - PRIORITY THRESHOLD Register for hart 1"] - pub threshold_1: THRESHOLD_1, + #[inline(always)] + pub const fn threshold_1(&self) -> &THRESHOLD_1 { + &self.threshold_1 + } #[doc = "0x201004 - CLAIM and COMPLETE Register for hart 1"] - pub claimplete_1: CLAIMPLETE_1, - _reserved170: [u8; 0x0ff8], + #[inline(always)] + pub const fn claimplete_1(&self) -> &CLAIMPLETE_1 { + &self.claimplete_1 + } #[doc = "0x202000 - PRIORITY THRESHOLD Register for hart 2"] - pub threshold_2: THRESHOLD_2, + #[inline(always)] + pub const fn threshold_2(&self) -> &THRESHOLD_2 { + &self.threshold_2 + } #[doc = "0x202004 - CLAIM and COMPLETE Register for hart 2"] - pub claimplete_2: CLAIMPLETE_2, - _reserved172: [u8; 0x0ff8], + #[inline(always)] + pub const fn claimplete_2(&self) -> &CLAIMPLETE_2 { + &self.claimplete_2 + } #[doc = "0x203000 - PRIORITY THRESHOLD Register for hart 3"] - pub threshold_3: THRESHOLD_3, + #[inline(always)] + pub const fn threshold_3(&self) -> &THRESHOLD_3 { + &self.threshold_3 + } #[doc = "0x203004 - CLAIM and COMPLETE Register for hart 3"] - pub claimplete_3: CLAIMPLETE_3, - _reserved174: [u8; 0x0ff8], + #[inline(always)] + pub const fn claimplete_3(&self) -> &CLAIMPLETE_3 { + &self.claimplete_3 + } #[doc = "0x204000 - PRIORITY THRESHOLD Register for hart 4"] - pub threshold_4: THRESHOLD_4, + #[inline(always)] + pub const fn threshold_4(&self) -> &THRESHOLD_4 { + &self.threshold_4 + } #[doc = "0x204004 - CLAIM and COMPLETE Register for hart 4"] - pub claimplete_4: CLAIMPLETE_4, + #[inline(always)] + pub const fn claimplete_4(&self) -> &CLAIMPLETE_4 { + &self.claimplete_4 + } } -#[doc = "priority_1 (rw) register accessor: PRIORITY Register for interrupt id 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_1`] +#[doc = "priority_1 (rw) register accessor: PRIORITY Register for interrupt id 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_1`] module"] pub type PRIORITY_1 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 1"] pub mod priority_1; -#[doc = "priority_2 (rw) register accessor: PRIORITY Register for interrupt id 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_2`] +#[doc = "priority_2 (rw) register accessor: PRIORITY Register for interrupt id 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_2`] module"] pub type PRIORITY_2 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 2"] pub mod priority_2; -#[doc = "priority_3 (rw) register accessor: PRIORITY Register for interrupt id 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_3`] +#[doc = "priority_3 (rw) register accessor: PRIORITY Register for interrupt id 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_3`] module"] pub type PRIORITY_3 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 3"] pub mod priority_3; -#[doc = "priority_4 (rw) register accessor: PRIORITY Register for interrupt id 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_4`] +#[doc = "priority_4 (rw) register accessor: PRIORITY Register for interrupt id 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_4`] module"] pub type PRIORITY_4 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 4"] pub mod priority_4; -#[doc = "priority_5 (rw) register accessor: PRIORITY Register for interrupt id 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_5`] +#[doc = "priority_5 (rw) register accessor: PRIORITY Register for interrupt id 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_5`] module"] pub type PRIORITY_5 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 5"] pub mod priority_5; -#[doc = "priority_6 (rw) register accessor: PRIORITY Register for interrupt id 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_6::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_6`] +#[doc = "priority_6 (rw) register accessor: PRIORITY Register for interrupt id 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_6::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_6`] module"] pub type PRIORITY_6 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 6"] pub mod priority_6; -#[doc = "priority_7 (rw) register accessor: PRIORITY Register for interrupt id 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_7::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_7`] +#[doc = "priority_7 (rw) register accessor: PRIORITY Register for interrupt id 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_7::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_7`] module"] pub type PRIORITY_7 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 7"] pub mod priority_7; -#[doc = "priority_8 (rw) register accessor: PRIORITY Register for interrupt id 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_8`] +#[doc = "priority_8 (rw) register accessor: PRIORITY Register for interrupt id 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_8`] module"] pub type PRIORITY_8 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 8"] pub mod priority_8; -#[doc = "priority_9 (rw) register accessor: PRIORITY Register for interrupt id 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_9::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_9`] +#[doc = "priority_9 (rw) register accessor: PRIORITY Register for interrupt id 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_9::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_9`] module"] pub type PRIORITY_9 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 9"] pub mod priority_9; -#[doc = "priority_10 (rw) register accessor: PRIORITY Register for interrupt id 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_10::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_10`] +#[doc = "priority_10 (rw) register accessor: PRIORITY Register for interrupt id 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_10::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_10`] module"] pub type PRIORITY_10 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 10"] pub mod priority_10; -#[doc = "priority_11 (rw) register accessor: PRIORITY Register for interrupt id 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_11::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_11`] +#[doc = "priority_11 (rw) register accessor: PRIORITY Register for interrupt id 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_11::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_11`] module"] pub type PRIORITY_11 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 11"] pub mod priority_11; -#[doc = "priority_12 (rw) register accessor: PRIORITY Register for interrupt id 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_12::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_12`] +#[doc = "priority_12 (rw) register accessor: PRIORITY Register for interrupt id 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_12::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_12`] module"] pub type PRIORITY_12 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 12"] pub mod priority_12; -#[doc = "priority_13 (rw) register accessor: PRIORITY Register for interrupt id 13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_13::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_13`] +#[doc = "priority_13 (rw) register accessor: PRIORITY Register for interrupt id 13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_13::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_13`] module"] pub type PRIORITY_13 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 13"] pub mod priority_13; -#[doc = "priority_14 (rw) register accessor: PRIORITY Register for interrupt id 14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_14::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_14`] +#[doc = "priority_14 (rw) register accessor: PRIORITY Register for interrupt id 14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_14::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_14`] module"] pub type PRIORITY_14 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 14"] pub mod priority_14; -#[doc = "priority_15 (rw) register accessor: PRIORITY Register for interrupt id 15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_15::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_15`] +#[doc = "priority_15 (rw) register accessor: PRIORITY Register for interrupt id 15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_15::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_15`] module"] pub type PRIORITY_15 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 15"] pub mod priority_15; -#[doc = "priority_16 (rw) register accessor: PRIORITY Register for interrupt id 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_16::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_16`] +#[doc = "priority_16 (rw) register accessor: PRIORITY Register for interrupt id 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_16::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_16`] module"] pub type PRIORITY_16 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 16"] pub mod priority_16; -#[doc = "priority_17 (rw) register accessor: PRIORITY Register for interrupt id 17\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_17::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_17::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_17`] +#[doc = "priority_17 (rw) register accessor: PRIORITY Register for interrupt id 17\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_17::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_17::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_17`] module"] pub type PRIORITY_17 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 17"] pub mod priority_17; -#[doc = "priority_18 (rw) register accessor: PRIORITY Register for interrupt id 18\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_18::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_18::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_18`] +#[doc = "priority_18 (rw) register accessor: PRIORITY Register for interrupt id 18\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_18::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_18::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_18`] module"] pub type PRIORITY_18 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 18"] pub mod priority_18; -#[doc = "priority_19 (rw) register accessor: PRIORITY Register for interrupt id 19\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_19::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_19`] +#[doc = "priority_19 (rw) register accessor: PRIORITY Register for interrupt id 19\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_19::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_19`] module"] pub type PRIORITY_19 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 19"] pub mod priority_19; -#[doc = "priority_20 (rw) register accessor: PRIORITY Register for interrupt id 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_20::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_20`] +#[doc = "priority_20 (rw) register accessor: PRIORITY Register for interrupt id 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_20::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_20`] module"] pub type PRIORITY_20 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 20"] pub mod priority_20; -#[doc = "priority_21 (rw) register accessor: PRIORITY Register for interrupt id 21\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_21::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_21::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_21`] +#[doc = "priority_21 (rw) register accessor: PRIORITY Register for interrupt id 21\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_21::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_21::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_21`] module"] pub type PRIORITY_21 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 21"] pub mod priority_21; -#[doc = "priority_22 (rw) register accessor: PRIORITY Register for interrupt id 22\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_22::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_22::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_22`] +#[doc = "priority_22 (rw) register accessor: PRIORITY Register for interrupt id 22\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_22::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_22::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_22`] module"] pub type PRIORITY_22 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 22"] pub mod priority_22; -#[doc = "priority_23 (rw) register accessor: PRIORITY Register for interrupt id 23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_23::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_23`] +#[doc = "priority_23 (rw) register accessor: PRIORITY Register for interrupt id 23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_23::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_23`] module"] pub type PRIORITY_23 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 23"] pub mod priority_23; -#[doc = "priority_24 (rw) register accessor: PRIORITY Register for interrupt id 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_24::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_24`] +#[doc = "priority_24 (rw) register accessor: PRIORITY Register for interrupt id 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_24::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_24`] module"] pub type PRIORITY_24 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 24"] pub mod priority_24; -#[doc = "priority_25 (rw) register accessor: PRIORITY Register for interrupt id 25\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_25::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_25::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_25`] +#[doc = "priority_25 (rw) register accessor: PRIORITY Register for interrupt id 25\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_25::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_25::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_25`] module"] pub type PRIORITY_25 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 25"] pub mod priority_25; -#[doc = "priority_26 (rw) register accessor: PRIORITY Register for interrupt id 26\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_26::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_26::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_26`] +#[doc = "priority_26 (rw) register accessor: PRIORITY Register for interrupt id 26\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_26::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_26::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_26`] module"] pub type PRIORITY_26 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 26"] pub mod priority_26; -#[doc = "priority_27 (rw) register accessor: PRIORITY Register for interrupt id 27\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_27::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_27`] +#[doc = "priority_27 (rw) register accessor: PRIORITY Register for interrupt id 27\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_27::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_27`] module"] pub type PRIORITY_27 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 27"] pub mod priority_27; -#[doc = "priority_28 (rw) register accessor: PRIORITY Register for interrupt id 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_28::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_28`] +#[doc = "priority_28 (rw) register accessor: PRIORITY Register for interrupt id 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_28::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_28`] module"] pub type PRIORITY_28 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 28"] pub mod priority_28; -#[doc = "priority_29 (rw) register accessor: PRIORITY Register for interrupt id 29\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_29::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_29::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_29`] +#[doc = "priority_29 (rw) register accessor: PRIORITY Register for interrupt id 29\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_29::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_29::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_29`] module"] pub type PRIORITY_29 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 29"] pub mod priority_29; -#[doc = "priority_30 (rw) register accessor: PRIORITY Register for interrupt id 30\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_30::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_30::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_30`] +#[doc = "priority_30 (rw) register accessor: PRIORITY Register for interrupt id 30\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_30::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_30::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_30`] module"] pub type PRIORITY_30 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 30"] pub mod priority_30; -#[doc = "priority_31 (rw) register accessor: PRIORITY Register for interrupt id 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_31::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_31::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_31`] +#[doc = "priority_31 (rw) register accessor: PRIORITY Register for interrupt id 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_31::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_31::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_31`] module"] pub type PRIORITY_31 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 31"] pub mod priority_31; -#[doc = "priority_32 (rw) register accessor: PRIORITY Register for interrupt id 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_32::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_32`] +#[doc = "priority_32 (rw) register accessor: PRIORITY Register for interrupt id 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_32::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_32`] module"] pub type PRIORITY_32 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 32"] pub mod priority_32; -#[doc = "priority_33 (rw) register accessor: PRIORITY Register for interrupt id 33\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_33::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_33::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_33`] +#[doc = "priority_33 (rw) register accessor: PRIORITY Register for interrupt id 33\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_33::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_33::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_33`] module"] pub type PRIORITY_33 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 33"] pub mod priority_33; -#[doc = "priority_34 (rw) register accessor: PRIORITY Register for interrupt id 34\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_34::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_34::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_34`] +#[doc = "priority_34 (rw) register accessor: PRIORITY Register for interrupt id 34\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_34::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_34::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_34`] module"] pub type PRIORITY_34 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 34"] pub mod priority_34; -#[doc = "priority_35 (rw) register accessor: PRIORITY Register for interrupt id 35\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_35::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_35::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_35`] +#[doc = "priority_35 (rw) register accessor: PRIORITY Register for interrupt id 35\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_35::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_35::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_35`] module"] pub type PRIORITY_35 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 35"] pub mod priority_35; -#[doc = "priority_36 (rw) register accessor: PRIORITY Register for interrupt id 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_36::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_36`] +#[doc = "priority_36 (rw) register accessor: PRIORITY Register for interrupt id 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_36::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_36`] module"] pub type PRIORITY_36 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 36"] pub mod priority_36; -#[doc = "priority_37 (rw) register accessor: PRIORITY Register for interrupt id 37\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_37::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_37::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_37`] +#[doc = "priority_37 (rw) register accessor: PRIORITY Register for interrupt id 37\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_37::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_37::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_37`] module"] pub type PRIORITY_37 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 37"] pub mod priority_37; -#[doc = "priority_38 (rw) register accessor: PRIORITY Register for interrupt id 38\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_38::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_38::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_38`] +#[doc = "priority_38 (rw) register accessor: PRIORITY Register for interrupt id 38\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_38::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_38::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_38`] module"] pub type PRIORITY_38 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 38"] pub mod priority_38; -#[doc = "priority_39 (rw) register accessor: PRIORITY Register for interrupt id 39\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_39::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_39::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_39`] +#[doc = "priority_39 (rw) register accessor: PRIORITY Register for interrupt id 39\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_39::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_39::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_39`] module"] pub type PRIORITY_39 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 39"] pub mod priority_39; -#[doc = "priority_40 (rw) register accessor: PRIORITY Register for interrupt id 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_40::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_40`] +#[doc = "priority_40 (rw) register accessor: PRIORITY Register for interrupt id 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_40::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_40`] module"] pub type PRIORITY_40 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 40"] pub mod priority_40; -#[doc = "priority_41 (rw) register accessor: PRIORITY Register for interrupt id 41\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_41::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_41::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_41`] +#[doc = "priority_41 (rw) register accessor: PRIORITY Register for interrupt id 41\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_41::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_41::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_41`] module"] pub type PRIORITY_41 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 41"] pub mod priority_41; -#[doc = "priority_42 (rw) register accessor: PRIORITY Register for interrupt id 42\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_42::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_42::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_42`] +#[doc = "priority_42 (rw) register accessor: PRIORITY Register for interrupt id 42\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_42::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_42::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_42`] module"] pub type PRIORITY_42 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 42"] pub mod priority_42; -#[doc = "priority_43 (rw) register accessor: PRIORITY Register for interrupt id 43\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_43::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_43::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_43`] +#[doc = "priority_43 (rw) register accessor: PRIORITY Register for interrupt id 43\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_43::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_43::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_43`] module"] pub type PRIORITY_43 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 43"] pub mod priority_43; -#[doc = "priority_44 (rw) register accessor: PRIORITY Register for interrupt id 44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_44::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_44`] +#[doc = "priority_44 (rw) register accessor: PRIORITY Register for interrupt id 44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_44::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_44`] module"] pub type PRIORITY_44 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 44"] pub mod priority_44; -#[doc = "priority_45 (rw) register accessor: PRIORITY Register for interrupt id 45\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_45::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_45::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_45`] +#[doc = "priority_45 (rw) register accessor: PRIORITY Register for interrupt id 45\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_45::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_45::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_45`] module"] pub type PRIORITY_45 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 45"] pub mod priority_45; -#[doc = "priority_46 (rw) register accessor: PRIORITY Register for interrupt id 46\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_46::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_46::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_46`] +#[doc = "priority_46 (rw) register accessor: PRIORITY Register for interrupt id 46\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_46::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_46::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_46`] module"] pub type PRIORITY_46 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 46"] pub mod priority_46; -#[doc = "priority_47 (rw) register accessor: PRIORITY Register for interrupt id 47\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_47::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_47::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_47`] +#[doc = "priority_47 (rw) register accessor: PRIORITY Register for interrupt id 47\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_47::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_47::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_47`] module"] pub type PRIORITY_47 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 47"] pub mod priority_47; -#[doc = "priority_48 (rw) register accessor: PRIORITY Register for interrupt id 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_48`] +#[doc = "priority_48 (rw) register accessor: PRIORITY Register for interrupt id 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_48`] module"] pub type PRIORITY_48 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 48"] pub mod priority_48; -#[doc = "priority_49 (rw) register accessor: PRIORITY Register for interrupt id 49\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_49::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_49::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_49`] +#[doc = "priority_49 (rw) register accessor: PRIORITY Register for interrupt id 49\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_49::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_49::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_49`] module"] pub type PRIORITY_49 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 49"] pub mod priority_49; -#[doc = "priority_50 (rw) register accessor: PRIORITY Register for interrupt id 50\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_50::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_50::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_50`] +#[doc = "priority_50 (rw) register accessor: PRIORITY Register for interrupt id 50\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_50::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_50::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_50`] module"] pub type PRIORITY_50 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 50"] pub mod priority_50; -#[doc = "priority_51 (rw) register accessor: PRIORITY Register for interrupt id 51\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_51::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_51::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_51`] +#[doc = "priority_51 (rw) register accessor: PRIORITY Register for interrupt id 51\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_51::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_51::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_51`] module"] pub type PRIORITY_51 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 51"] pub mod priority_51; -#[doc = "priority_52 (rw) register accessor: PRIORITY Register for interrupt id 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_52`] +#[doc = "priority_52 (rw) register accessor: PRIORITY Register for interrupt id 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_52`] module"] pub type PRIORITY_52 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 52"] pub mod priority_52; -#[doc = "priority_53 (rw) register accessor: PRIORITY Register for interrupt id 53\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_53::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_53::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_53`] +#[doc = "priority_53 (rw) register accessor: PRIORITY Register for interrupt id 53\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_53::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_53::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_53`] module"] pub type PRIORITY_53 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 53"] pub mod priority_53; -#[doc = "priority_54 (rw) register accessor: PRIORITY Register for interrupt id 54\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_54::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_54::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_54`] +#[doc = "priority_54 (rw) register accessor: PRIORITY Register for interrupt id 54\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_54::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_54::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_54`] module"] pub type PRIORITY_54 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 54"] pub mod priority_54; -#[doc = "priority_55 (rw) register accessor: PRIORITY Register for interrupt id 55\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_55::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_55::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_55`] +#[doc = "priority_55 (rw) register accessor: PRIORITY Register for interrupt id 55\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_55::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_55::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_55`] module"] pub type PRIORITY_55 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 55"] pub mod priority_55; -#[doc = "priority_56 (rw) register accessor: PRIORITY Register for interrupt id 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_56`] +#[doc = "priority_56 (rw) register accessor: PRIORITY Register for interrupt id 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_56`] module"] pub type PRIORITY_56 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 56"] pub mod priority_56; -#[doc = "priority_57 (rw) register accessor: PRIORITY Register for interrupt id 57\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_57::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_57::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_57`] +#[doc = "priority_57 (rw) register accessor: PRIORITY Register for interrupt id 57\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_57::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_57::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_57`] module"] pub type PRIORITY_57 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 57"] pub mod priority_57; -#[doc = "priority_58 (rw) register accessor: PRIORITY Register for interrupt id 58\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_58::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_58::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_58`] +#[doc = "priority_58 (rw) register accessor: PRIORITY Register for interrupt id 58\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_58::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_58::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_58`] module"] pub type PRIORITY_58 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 58"] pub mod priority_58; -#[doc = "priority_59 (rw) register accessor: PRIORITY Register for interrupt id 59\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_59::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_59::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_59`] +#[doc = "priority_59 (rw) register accessor: PRIORITY Register for interrupt id 59\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_59::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_59::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_59`] module"] pub type PRIORITY_59 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 59"] pub mod priority_59; -#[doc = "priority_60 (rw) register accessor: PRIORITY Register for interrupt id 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_60`] +#[doc = "priority_60 (rw) register accessor: PRIORITY Register for interrupt id 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_60`] module"] pub type PRIORITY_60 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 60"] pub mod priority_60; -#[doc = "priority_61 (rw) register accessor: PRIORITY Register for interrupt id 61\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_61::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_61::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_61`] +#[doc = "priority_61 (rw) register accessor: PRIORITY Register for interrupt id 61\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_61::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_61::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_61`] module"] pub type PRIORITY_61 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 61"] pub mod priority_61; -#[doc = "priority_62 (rw) register accessor: PRIORITY Register for interrupt id 62\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_62::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_62::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_62`] +#[doc = "priority_62 (rw) register accessor: PRIORITY Register for interrupt id 62\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_62::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_62::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_62`] module"] pub type PRIORITY_62 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 62"] pub mod priority_62; -#[doc = "priority_63 (rw) register accessor: PRIORITY Register for interrupt id 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_63::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_63::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_63`] +#[doc = "priority_63 (rw) register accessor: PRIORITY Register for interrupt id 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_63::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_63::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_63`] module"] pub type PRIORITY_63 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 63"] pub mod priority_63; -#[doc = "priority_64 (rw) register accessor: PRIORITY Register for interrupt id 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_64`] +#[doc = "priority_64 (rw) register accessor: PRIORITY Register for interrupt id 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_64`] module"] pub type PRIORITY_64 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 64"] pub mod priority_64; -#[doc = "priority_65 (rw) register accessor: PRIORITY Register for interrupt id 65\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_65::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_65::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_65`] +#[doc = "priority_65 (rw) register accessor: PRIORITY Register for interrupt id 65\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_65::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_65::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_65`] module"] pub type PRIORITY_65 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 65"] pub mod priority_65; -#[doc = "priority_66 (rw) register accessor: PRIORITY Register for interrupt id 66\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_66::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_66::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_66`] +#[doc = "priority_66 (rw) register accessor: PRIORITY Register for interrupt id 66\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_66::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_66::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_66`] module"] pub type PRIORITY_66 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 66"] pub mod priority_66; -#[doc = "priority_67 (rw) register accessor: PRIORITY Register for interrupt id 67\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_67::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_67::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_67`] +#[doc = "priority_67 (rw) register accessor: PRIORITY Register for interrupt id 67\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_67::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_67::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_67`] module"] pub type PRIORITY_67 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 67"] pub mod priority_67; -#[doc = "priority_68 (rw) register accessor: PRIORITY Register for interrupt id 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_68`] +#[doc = "priority_68 (rw) register accessor: PRIORITY Register for interrupt id 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_68`] module"] pub type PRIORITY_68 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 68"] pub mod priority_68; -#[doc = "priority_69 (rw) register accessor: PRIORITY Register for interrupt id 69\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_69::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_69::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_69`] +#[doc = "priority_69 (rw) register accessor: PRIORITY Register for interrupt id 69\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_69::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_69::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_69`] module"] pub type PRIORITY_69 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 69"] pub mod priority_69; -#[doc = "priority_70 (rw) register accessor: PRIORITY Register for interrupt id 70\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_70::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_70::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_70`] +#[doc = "priority_70 (rw) register accessor: PRIORITY Register for interrupt id 70\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_70::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_70::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_70`] module"] pub type PRIORITY_70 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 70"] pub mod priority_70; -#[doc = "priority_71 (rw) register accessor: PRIORITY Register for interrupt id 71\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_71::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_71::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_71`] +#[doc = "priority_71 (rw) register accessor: PRIORITY Register for interrupt id 71\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_71::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_71::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_71`] module"] pub type PRIORITY_71 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 71"] pub mod priority_71; -#[doc = "priority_72 (rw) register accessor: PRIORITY Register for interrupt id 72\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_72::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_72::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_72`] +#[doc = "priority_72 (rw) register accessor: PRIORITY Register for interrupt id 72\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_72::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_72::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_72`] module"] pub type PRIORITY_72 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 72"] pub mod priority_72; -#[doc = "priority_73 (rw) register accessor: PRIORITY Register for interrupt id 73\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_73::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_73::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_73`] +#[doc = "priority_73 (rw) register accessor: PRIORITY Register for interrupt id 73\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_73::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_73::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_73`] module"] pub type PRIORITY_73 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 73"] pub mod priority_73; -#[doc = "priority_74 (rw) register accessor: PRIORITY Register for interrupt id 74\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_74::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_74::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_74`] +#[doc = "priority_74 (rw) register accessor: PRIORITY Register for interrupt id 74\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_74::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_74::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_74`] module"] pub type PRIORITY_74 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 74"] pub mod priority_74; -#[doc = "priority_75 (rw) register accessor: PRIORITY Register for interrupt id 75\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_75::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_75::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_75`] +#[doc = "priority_75 (rw) register accessor: PRIORITY Register for interrupt id 75\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_75::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_75::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_75`] module"] pub type PRIORITY_75 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 75"] pub mod priority_75; -#[doc = "priority_76 (rw) register accessor: PRIORITY Register for interrupt id 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_76`] +#[doc = "priority_76 (rw) register accessor: PRIORITY Register for interrupt id 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_76`] module"] pub type PRIORITY_76 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 76"] pub mod priority_76; -#[doc = "priority_77 (rw) register accessor: PRIORITY Register for interrupt id 77\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_77::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_77::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_77`] +#[doc = "priority_77 (rw) register accessor: PRIORITY Register for interrupt id 77\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_77::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_77::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_77`] module"] pub type PRIORITY_77 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 77"] pub mod priority_77; -#[doc = "priority_78 (rw) register accessor: PRIORITY Register for interrupt id 78\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_78::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_78::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_78`] +#[doc = "priority_78 (rw) register accessor: PRIORITY Register for interrupt id 78\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_78::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_78::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_78`] module"] pub type PRIORITY_78 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 78"] pub mod priority_78; -#[doc = "priority_79 (rw) register accessor: PRIORITY Register for interrupt id 79\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_79::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_79::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_79`] +#[doc = "priority_79 (rw) register accessor: PRIORITY Register for interrupt id 79\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_79::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_79::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_79`] module"] pub type PRIORITY_79 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 79"] pub mod priority_79; -#[doc = "priority_80 (rw) register accessor: PRIORITY Register for interrupt id 80\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_80::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_80::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_80`] +#[doc = "priority_80 (rw) register accessor: PRIORITY Register for interrupt id 80\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_80::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_80::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_80`] module"] pub type PRIORITY_80 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 80"] pub mod priority_80; -#[doc = "priority_81 (rw) register accessor: PRIORITY Register for interrupt id 81\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_81::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_81::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_81`] +#[doc = "priority_81 (rw) register accessor: PRIORITY Register for interrupt id 81\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_81::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_81::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_81`] module"] pub type PRIORITY_81 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 81"] pub mod priority_81; -#[doc = "priority_82 (rw) register accessor: PRIORITY Register for interrupt id 82\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_82::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_82::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_82`] +#[doc = "priority_82 (rw) register accessor: PRIORITY Register for interrupt id 82\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_82::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_82::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_82`] module"] pub type PRIORITY_82 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 82"] pub mod priority_82; -#[doc = "priority_83 (rw) register accessor: PRIORITY Register for interrupt id 83\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_83::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_83::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_83`] +#[doc = "priority_83 (rw) register accessor: PRIORITY Register for interrupt id 83\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_83::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_83::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_83`] module"] pub type PRIORITY_83 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 83"] pub mod priority_83; -#[doc = "priority_84 (rw) register accessor: PRIORITY Register for interrupt id 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_84`] +#[doc = "priority_84 (rw) register accessor: PRIORITY Register for interrupt id 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_84`] module"] pub type PRIORITY_84 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 84"] pub mod priority_84; -#[doc = "priority_85 (rw) register accessor: PRIORITY Register for interrupt id 85\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_85::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_85::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_85`] +#[doc = "priority_85 (rw) register accessor: PRIORITY Register for interrupt id 85\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_85::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_85::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_85`] module"] pub type PRIORITY_85 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 85"] pub mod priority_85; -#[doc = "priority_86 (rw) register accessor: PRIORITY Register for interrupt id 86\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_86::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_86::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_86`] +#[doc = "priority_86 (rw) register accessor: PRIORITY Register for interrupt id 86\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_86::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_86::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_86`] module"] pub type PRIORITY_86 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 86"] pub mod priority_86; -#[doc = "priority_87 (rw) register accessor: PRIORITY Register for interrupt id 87\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_87::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_87::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_87`] +#[doc = "priority_87 (rw) register accessor: PRIORITY Register for interrupt id 87\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_87::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_87::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_87`] module"] pub type PRIORITY_87 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 87"] pub mod priority_87; -#[doc = "priority_88 (rw) register accessor: PRIORITY Register for interrupt id 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_88`] +#[doc = "priority_88 (rw) register accessor: PRIORITY Register for interrupt id 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_88`] module"] pub type PRIORITY_88 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 88"] pub mod priority_88; -#[doc = "priority_89 (rw) register accessor: PRIORITY Register for interrupt id 89\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_89::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_89::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_89`] +#[doc = "priority_89 (rw) register accessor: PRIORITY Register for interrupt id 89\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_89::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_89::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_89`] module"] pub type PRIORITY_89 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 89"] pub mod priority_89; -#[doc = "priority_90 (rw) register accessor: PRIORITY Register for interrupt id 90\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_90::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_90::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_90`] +#[doc = "priority_90 (rw) register accessor: PRIORITY Register for interrupt id 90\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_90::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_90::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_90`] module"] pub type PRIORITY_90 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 90"] pub mod priority_90; -#[doc = "priority_91 (rw) register accessor: PRIORITY Register for interrupt id 91\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_91::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_91::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_91`] +#[doc = "priority_91 (rw) register accessor: PRIORITY Register for interrupt id 91\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_91::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_91::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_91`] module"] pub type PRIORITY_91 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 91"] pub mod priority_91; -#[doc = "priority_92 (rw) register accessor: PRIORITY Register for interrupt id 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_92`] +#[doc = "priority_92 (rw) register accessor: PRIORITY Register for interrupt id 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_92`] module"] pub type PRIORITY_92 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 92"] pub mod priority_92; -#[doc = "priority_93 (rw) register accessor: PRIORITY Register for interrupt id 93\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_93::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_93::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_93`] +#[doc = "priority_93 (rw) register accessor: PRIORITY Register for interrupt id 93\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_93::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_93::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_93`] module"] pub type PRIORITY_93 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 93"] pub mod priority_93; -#[doc = "priority_94 (rw) register accessor: PRIORITY Register for interrupt id 94\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_94::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_94::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_94`] +#[doc = "priority_94 (rw) register accessor: PRIORITY Register for interrupt id 94\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_94::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_94::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_94`] module"] pub type PRIORITY_94 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 94"] pub mod priority_94; -#[doc = "priority_95 (rw) register accessor: PRIORITY Register for interrupt id 95\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_95::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_95::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_95`] +#[doc = "priority_95 (rw) register accessor: PRIORITY Register for interrupt id 95\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_95::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_95::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_95`] module"] pub type PRIORITY_95 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 95"] pub mod priority_95; -#[doc = "priority_96 (rw) register accessor: PRIORITY Register for interrupt id 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_96`] +#[doc = "priority_96 (rw) register accessor: PRIORITY Register for interrupt id 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_96`] module"] pub type PRIORITY_96 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 96"] pub mod priority_96; -#[doc = "priority_97 (rw) register accessor: PRIORITY Register for interrupt id 97\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_97::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_97::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_97`] +#[doc = "priority_97 (rw) register accessor: PRIORITY Register for interrupt id 97\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_97::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_97::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_97`] module"] pub type PRIORITY_97 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 97"] pub mod priority_97; -#[doc = "priority_98 (rw) register accessor: PRIORITY Register for interrupt id 98\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_98::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_98::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_98`] +#[doc = "priority_98 (rw) register accessor: PRIORITY Register for interrupt id 98\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_98::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_98::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_98`] module"] pub type PRIORITY_98 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 98"] pub mod priority_98; -#[doc = "priority_99 (rw) register accessor: PRIORITY Register for interrupt id 99\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_99::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_99::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_99`] +#[doc = "priority_99 (rw) register accessor: PRIORITY Register for interrupt id 99\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_99::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_99::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_99`] module"] pub type PRIORITY_99 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 99"] pub mod priority_99; -#[doc = "priority_100 (rw) register accessor: PRIORITY Register for interrupt id 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_100`] +#[doc = "priority_100 (rw) register accessor: PRIORITY Register for interrupt id 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_100`] module"] pub type PRIORITY_100 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 100"] pub mod priority_100; -#[doc = "priority_101 (rw) register accessor: PRIORITY Register for interrupt id 101\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_101::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_101::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_101`] +#[doc = "priority_101 (rw) register accessor: PRIORITY Register for interrupt id 101\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_101::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_101::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_101`] module"] pub type PRIORITY_101 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 101"] pub mod priority_101; -#[doc = "priority_102 (rw) register accessor: PRIORITY Register for interrupt id 102\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_102::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_102::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_102`] +#[doc = "priority_102 (rw) register accessor: PRIORITY Register for interrupt id 102\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_102::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_102::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_102`] module"] pub type PRIORITY_102 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 102"] pub mod priority_102; -#[doc = "priority_103 (rw) register accessor: PRIORITY Register for interrupt id 103\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_103::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_103::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_103`] +#[doc = "priority_103 (rw) register accessor: PRIORITY Register for interrupt id 103\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_103::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_103::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_103`] module"] pub type PRIORITY_103 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 103"] pub mod priority_103; -#[doc = "priority_104 (rw) register accessor: PRIORITY Register for interrupt id 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_104`] +#[doc = "priority_104 (rw) register accessor: PRIORITY Register for interrupt id 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_104`] module"] pub type PRIORITY_104 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 104"] pub mod priority_104; -#[doc = "priority_105 (rw) register accessor: PRIORITY Register for interrupt id 105\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_105::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_105::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_105`] +#[doc = "priority_105 (rw) register accessor: PRIORITY Register for interrupt id 105\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_105::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_105::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_105`] module"] pub type PRIORITY_105 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 105"] pub mod priority_105; -#[doc = "priority_106 (rw) register accessor: PRIORITY Register for interrupt id 106\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_106::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_106::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_106`] +#[doc = "priority_106 (rw) register accessor: PRIORITY Register for interrupt id 106\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_106::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_106::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_106`] module"] pub type PRIORITY_106 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 106"] pub mod priority_106; -#[doc = "priority_107 (rw) register accessor: PRIORITY Register for interrupt id 107\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_107::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_107::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_107`] +#[doc = "priority_107 (rw) register accessor: PRIORITY Register for interrupt id 107\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_107::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_107::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_107`] module"] pub type PRIORITY_107 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 107"] pub mod priority_107; -#[doc = "priority_108 (rw) register accessor: PRIORITY Register for interrupt id 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_108`] +#[doc = "priority_108 (rw) register accessor: PRIORITY Register for interrupt id 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_108`] module"] pub type PRIORITY_108 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 108"] pub mod priority_108; -#[doc = "priority_109 (rw) register accessor: PRIORITY Register for interrupt id 109\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_109::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_109::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_109`] +#[doc = "priority_109 (rw) register accessor: PRIORITY Register for interrupt id 109\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_109::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_109::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_109`] module"] pub type PRIORITY_109 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 109"] pub mod priority_109; -#[doc = "priority_110 (rw) register accessor: PRIORITY Register for interrupt id 110\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_110::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_110::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_110`] +#[doc = "priority_110 (rw) register accessor: PRIORITY Register for interrupt id 110\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_110::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_110::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_110`] module"] pub type PRIORITY_110 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 110"] pub mod priority_110; -#[doc = "priority_111 (rw) register accessor: PRIORITY Register for interrupt id 111\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_111::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_111::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_111`] +#[doc = "priority_111 (rw) register accessor: PRIORITY Register for interrupt id 111\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_111::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_111::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_111`] module"] pub type PRIORITY_111 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 111"] pub mod priority_111; -#[doc = "priority_112 (rw) register accessor: PRIORITY Register for interrupt id 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_112`] +#[doc = "priority_112 (rw) register accessor: PRIORITY Register for interrupt id 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_112`] module"] pub type PRIORITY_112 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 112"] pub mod priority_112; -#[doc = "priority_113 (rw) register accessor: PRIORITY Register for interrupt id 113\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_113::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_113::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_113`] +#[doc = "priority_113 (rw) register accessor: PRIORITY Register for interrupt id 113\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_113::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_113::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_113`] module"] pub type PRIORITY_113 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 113"] pub mod priority_113; -#[doc = "priority_114 (rw) register accessor: PRIORITY Register for interrupt id 114\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_114::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_114::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_114`] +#[doc = "priority_114 (rw) register accessor: PRIORITY Register for interrupt id 114\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_114::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_114::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_114`] module"] pub type PRIORITY_114 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 114"] pub mod priority_114; -#[doc = "priority_115 (rw) register accessor: PRIORITY Register for interrupt id 115\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_115::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_115::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_115`] +#[doc = "priority_115 (rw) register accessor: PRIORITY Register for interrupt id 115\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_115::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_115::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_115`] module"] pub type PRIORITY_115 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 115"] pub mod priority_115; -#[doc = "priority_116 (rw) register accessor: PRIORITY Register for interrupt id 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_116`] +#[doc = "priority_116 (rw) register accessor: PRIORITY Register for interrupt id 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_116`] module"] pub type PRIORITY_116 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 116"] pub mod priority_116; -#[doc = "priority_117 (rw) register accessor: PRIORITY Register for interrupt id 117\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_117::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_117::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_117`] +#[doc = "priority_117 (rw) register accessor: PRIORITY Register for interrupt id 117\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_117::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_117::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_117`] module"] pub type PRIORITY_117 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 117"] pub mod priority_117; -#[doc = "priority_118 (rw) register accessor: PRIORITY Register for interrupt id 118\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_118::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_118::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_118`] +#[doc = "priority_118 (rw) register accessor: PRIORITY Register for interrupt id 118\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_118::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_118::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_118`] module"] pub type PRIORITY_118 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 118"] pub mod priority_118; -#[doc = "priority_119 (rw) register accessor: PRIORITY Register for interrupt id 119\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_119::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_119::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_119`] +#[doc = "priority_119 (rw) register accessor: PRIORITY Register for interrupt id 119\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_119::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_119::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_119`] module"] pub type PRIORITY_119 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 119"] pub mod priority_119; -#[doc = "priority_120 (rw) register accessor: PRIORITY Register for interrupt id 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_120`] +#[doc = "priority_120 (rw) register accessor: PRIORITY Register for interrupt id 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_120`] module"] pub type PRIORITY_120 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 120"] pub mod priority_120; -#[doc = "priority_121 (rw) register accessor: PRIORITY Register for interrupt id 121\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_121::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_121::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_121`] +#[doc = "priority_121 (rw) register accessor: PRIORITY Register for interrupt id 121\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_121::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_121::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_121`] module"] pub type PRIORITY_121 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 121"] pub mod priority_121; -#[doc = "priority_122 (rw) register accessor: PRIORITY Register for interrupt id 122\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_122::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_122::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_122`] +#[doc = "priority_122 (rw) register accessor: PRIORITY Register for interrupt id 122\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_122::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_122::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_122`] module"] pub type PRIORITY_122 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 122"] pub mod priority_122; -#[doc = "priority_123 (rw) register accessor: PRIORITY Register for interrupt id 123\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_123::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_123::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_123`] +#[doc = "priority_123 (rw) register accessor: PRIORITY Register for interrupt id 123\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_123::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_123::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_123`] module"] pub type PRIORITY_123 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 123"] pub mod priority_123; -#[doc = "priority_124 (rw) register accessor: PRIORITY Register for interrupt id 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_124`] +#[doc = "priority_124 (rw) register accessor: PRIORITY Register for interrupt id 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_124`] module"] pub type PRIORITY_124 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 124"] pub mod priority_124; -#[doc = "priority_125 (rw) register accessor: PRIORITY Register for interrupt id 125\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_125::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_125::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_125`] +#[doc = "priority_125 (rw) register accessor: PRIORITY Register for interrupt id 125\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_125::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_125::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_125`] module"] pub type PRIORITY_125 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 125"] pub mod priority_125; -#[doc = "priority_126 (rw) register accessor: PRIORITY Register for interrupt id 126\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_126::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_126::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_126`] +#[doc = "priority_126 (rw) register accessor: PRIORITY Register for interrupt id 126\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_126::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_126::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_126`] module"] pub type PRIORITY_126 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 126"] pub mod priority_126; -#[doc = "priority_127 (rw) register accessor: PRIORITY Register for interrupt id 127\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_127::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_127::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_127`] +#[doc = "priority_127 (rw) register accessor: PRIORITY Register for interrupt id 127\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_127::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_127::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_127`] module"] pub type PRIORITY_127 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 127"] pub mod priority_127; -#[doc = "priority_128 (rw) register accessor: PRIORITY Register for interrupt id 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_128`] +#[doc = "priority_128 (rw) register accessor: PRIORITY Register for interrupt id 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_128`] module"] pub type PRIORITY_128 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 128"] pub mod priority_128; -#[doc = "priority_129 (rw) register accessor: PRIORITY Register for interrupt id 129\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_129::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_129::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_129`] +#[doc = "priority_129 (rw) register accessor: PRIORITY Register for interrupt id 129\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_129::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_129::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_129`] module"] pub type PRIORITY_129 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 129"] pub mod priority_129; -#[doc = "priority_130 (rw) register accessor: PRIORITY Register for interrupt id 130\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_130::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_130::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_130`] +#[doc = "priority_130 (rw) register accessor: PRIORITY Register for interrupt id 130\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_130::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_130::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_130`] module"] pub type PRIORITY_130 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 130"] pub mod priority_130; -#[doc = "priority_131 (rw) register accessor: PRIORITY Register for interrupt id 131\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_131::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_131::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_131`] +#[doc = "priority_131 (rw) register accessor: PRIORITY Register for interrupt id 131\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_131::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_131::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_131`] module"] pub type PRIORITY_131 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 131"] pub mod priority_131; -#[doc = "priority_132 (rw) register accessor: PRIORITY Register for interrupt id 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_132::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_132::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_132`] +#[doc = "priority_132 (rw) register accessor: PRIORITY Register for interrupt id 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_132::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_132::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_132`] module"] pub type PRIORITY_132 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 132"] pub mod priority_132; -#[doc = "priority_133 (rw) register accessor: PRIORITY Register for interrupt id 133\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_133::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_133::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_133`] +#[doc = "priority_133 (rw) register accessor: PRIORITY Register for interrupt id 133\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_133::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_133::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_133`] module"] pub type PRIORITY_133 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 133"] pub mod priority_133; -#[doc = "priority_134 (rw) register accessor: PRIORITY Register for interrupt id 134\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_134::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_134::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_134`] +#[doc = "priority_134 (rw) register accessor: PRIORITY Register for interrupt id 134\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_134::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_134::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_134`] module"] pub type PRIORITY_134 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 134"] pub mod priority_134; -#[doc = "priority_135 (rw) register accessor: PRIORITY Register for interrupt id 135\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_135::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_135::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_135`] +#[doc = "priority_135 (rw) register accessor: PRIORITY Register for interrupt id 135\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_135::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_135::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_135`] module"] pub type PRIORITY_135 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 135"] pub mod priority_135; -#[doc = "priority_136 (rw) register accessor: PRIORITY Register for interrupt id 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`priority_136`] +#[doc = "priority_136 (rw) register accessor: PRIORITY Register for interrupt id 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority_136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority_136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority_136`] module"] pub type PRIORITY_136 = crate::Reg; #[doc = "PRIORITY Register for interrupt id 136"] pub mod priority_136; -#[doc = "pending_0 (rw) register accessor: PENDING Register for interrupt ids 31 to 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pending_0`] +#[doc = "pending_0 (rw) register accessor: PENDING Register for interrupt ids 31 to 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_0`] module"] pub type PENDING_0 = crate::Reg; #[doc = "PENDING Register for interrupt ids 31 to 0"] pub mod pending_0; -#[doc = "pending_1 (rw) register accessor: PENDING Register for interrupt ids 63 to 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pending_1`] +#[doc = "pending_1 (rw) register accessor: PENDING Register for interrupt ids 63 to 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_1`] module"] pub type PENDING_1 = crate::Reg; #[doc = "PENDING Register for interrupt ids 63 to 32"] pub mod pending_1; -#[doc = "pending_2 (rw) register accessor: PENDING Register for interrupt ids 95 to 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pending_2`] +#[doc = "pending_2 (rw) register accessor: PENDING Register for interrupt ids 95 to 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_2`] module"] pub type PENDING_2 = crate::Reg; #[doc = "PENDING Register for interrupt ids 95 to 64"] pub mod pending_2; -#[doc = "pending_3 (rw) register accessor: PENDING Register for interrupt ids 127 to 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pending_3`] +#[doc = "pending_3 (rw) register accessor: PENDING Register for interrupt ids 127 to 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_3`] module"] pub type PENDING_3 = crate::Reg; #[doc = "PENDING Register for interrupt ids 127 to 96"] pub mod pending_3; -#[doc = "pending_4 (rw) register accessor: PENDING Register for interrupt ids 136 to 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pending_4`] +#[doc = "pending_4 (rw) register accessor: PENDING Register for interrupt ids 136 to 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_4`] module"] pub type PENDING_4 = crate::Reg; #[doc = "PENDING Register for interrupt ids 136 to 128"] pub mod pending_4; -#[doc = "enable_0_0 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_0_0`] +#[doc = "enable_0_0 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_0_0`] module"] pub type ENABLE_0_0 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 31 to 0 for hart 0"] pub mod enable_0_0; -#[doc = "enable_1_0 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_1_0`] +#[doc = "enable_1_0 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_1_0`] module"] pub type ENABLE_1_0 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 63 to 32 for hart 0"] pub mod enable_1_0; -#[doc = "enable_2_0 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_2_0`] +#[doc = "enable_2_0 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_2_0`] module"] pub type ENABLE_2_0 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 95 to 64 for hart 0"] pub mod enable_2_0; -#[doc = "enable_3_0 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_3_0`] +#[doc = "enable_3_0 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_3_0`] module"] pub type ENABLE_3_0 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 127 to 96 for hart 0"] pub mod enable_3_0; -#[doc = "enable_4_0 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_4_0`] +#[doc = "enable_4_0 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_4_0`] module"] pub type ENABLE_4_0 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 136 to 128 for hart 0"] pub mod enable_4_0; -#[doc = "enable_0_1 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_0_1`] +#[doc = "enable_0_1 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_0_1`] module"] pub type ENABLE_0_1 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 31 to 0 for hart 1"] pub mod enable_0_1; -#[doc = "enable_1_1 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_1_1`] +#[doc = "enable_1_1 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_1_1`] module"] pub type ENABLE_1_1 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 63 to 32 for hart 1"] pub mod enable_1_1; -#[doc = "enable_2_1 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_2_1`] +#[doc = "enable_2_1 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_2_1`] module"] pub type ENABLE_2_1 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 95 to 64 for hart 1"] pub mod enable_2_1; -#[doc = "enable_3_1 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_3_1`] +#[doc = "enable_3_1 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_3_1`] module"] pub type ENABLE_3_1 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 127 to 96 for hart 1"] pub mod enable_3_1; -#[doc = "enable_4_1 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_4_1`] +#[doc = "enable_4_1 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_4_1`] module"] pub type ENABLE_4_1 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 136 to 128 for hart 1"] pub mod enable_4_1; -#[doc = "enable_0_2 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_0_2`] +#[doc = "enable_0_2 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_0_2`] module"] pub type ENABLE_0_2 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 31 to 0 for hart 2"] pub mod enable_0_2; -#[doc = "enable_1_2 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_1_2`] +#[doc = "enable_1_2 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_1_2`] module"] pub type ENABLE_1_2 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 63 to 32 for hart 2"] pub mod enable_1_2; -#[doc = "enable_2_2 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_2_2`] +#[doc = "enable_2_2 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_2_2`] module"] pub type ENABLE_2_2 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 95 to 64 for hart 2"] pub mod enable_2_2; -#[doc = "enable_3_2 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_3_2`] +#[doc = "enable_3_2 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_3_2`] module"] pub type ENABLE_3_2 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 127 to 96 for hart 2"] pub mod enable_3_2; -#[doc = "enable_4_2 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_4_2`] +#[doc = "enable_4_2 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_4_2`] module"] pub type ENABLE_4_2 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 136 to 128 for hart 2"] pub mod enable_4_2; -#[doc = "enable_0_3 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_0_3`] +#[doc = "enable_0_3 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_0_3`] module"] pub type ENABLE_0_3 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 31 to 0 for hart 3"] pub mod enable_0_3; -#[doc = "enable_1_3 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_1_3`] +#[doc = "enable_1_3 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_1_3`] module"] pub type ENABLE_1_3 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 63 to 32 for hart 3"] pub mod enable_1_3; -#[doc = "enable_2_3 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_2_3`] +#[doc = "enable_2_3 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_2_3`] module"] pub type ENABLE_2_3 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 95 to 64 for hart 3"] pub mod enable_2_3; -#[doc = "enable_3_3 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_3_3`] +#[doc = "enable_3_3 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_3_3`] module"] pub type ENABLE_3_3 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 127 to 96 for hart 3"] pub mod enable_3_3; -#[doc = "enable_4_3 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_4_3`] +#[doc = "enable_4_3 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_4_3`] module"] pub type ENABLE_4_3 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 136 to 128 for hart 3"] pub mod enable_4_3; -#[doc = "enable_0_4 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_0_4`] +#[doc = "enable_0_4 (rw) register accessor: ENABLE Register for interrupt ids 31 to 0 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_0_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_0_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_0_4`] module"] pub type ENABLE_0_4 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 31 to 0 for hart 4"] pub mod enable_0_4; -#[doc = "enable_1_4 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_1_4`] +#[doc = "enable_1_4 (rw) register accessor: ENABLE Register for interrupt ids 63 to 32 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_1_4`] module"] pub type ENABLE_1_4 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 63 to 32 for hart 4"] pub mod enable_1_4; -#[doc = "enable_2_4 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_2_4`] +#[doc = "enable_2_4 (rw) register accessor: ENABLE Register for interrupt ids 95 to 64 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_2_4`] module"] pub type ENABLE_2_4 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 95 to 64 for hart 4"] pub mod enable_2_4; -#[doc = "enable_3_4 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_3_4`] +#[doc = "enable_3_4 (rw) register accessor: ENABLE Register for interrupt ids 127 to 96 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_3_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_3_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_3_4`] module"] pub type ENABLE_3_4 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 127 to 96 for hart 4"] pub mod enable_3_4; -#[doc = "enable_4_4 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`enable_4_4`] +#[doc = "enable_4_4 (rw) register accessor: ENABLE Register for interrupt ids 136 to 128 for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_4_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_4_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_4_4`] module"] pub type ENABLE_4_4 = crate::Reg; #[doc = "ENABLE Register for interrupt ids 136 to 128 for hart 4"] pub mod enable_4_4; -#[doc = "threshold_0 (rw) register accessor: PRIORITY THRESHOLD Register for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`threshold_0`] +#[doc = "threshold_0 (rw) register accessor: PRIORITY THRESHOLD Register for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@threshold_0`] module"] pub type THRESHOLD_0 = crate::Reg; #[doc = "PRIORITY THRESHOLD Register for hart 0"] pub mod threshold_0; -#[doc = "claimplete_0 (rw) register accessor: CLAIM and COMPLETE Register for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`claimplete_0`] +#[doc = "claimplete_0 (rw) register accessor: CLAIM and COMPLETE Register for hart 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@claimplete_0`] module"] pub type CLAIMPLETE_0 = crate::Reg; #[doc = "CLAIM and COMPLETE Register for hart 0"] pub mod claimplete_0; -#[doc = "threshold_1 (rw) register accessor: PRIORITY THRESHOLD Register for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`threshold_1`] +#[doc = "threshold_1 (rw) register accessor: PRIORITY THRESHOLD Register for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@threshold_1`] module"] pub type THRESHOLD_1 = crate::Reg; #[doc = "PRIORITY THRESHOLD Register for hart 1"] pub mod threshold_1; -#[doc = "claimplete_1 (rw) register accessor: CLAIM and COMPLETE Register for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`claimplete_1`] +#[doc = "claimplete_1 (rw) register accessor: CLAIM and COMPLETE Register for hart 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@claimplete_1`] module"] pub type CLAIMPLETE_1 = crate::Reg; #[doc = "CLAIM and COMPLETE Register for hart 1"] pub mod claimplete_1; -#[doc = "threshold_2 (rw) register accessor: PRIORITY THRESHOLD Register for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`threshold_2`] +#[doc = "threshold_2 (rw) register accessor: PRIORITY THRESHOLD Register for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@threshold_2`] module"] pub type THRESHOLD_2 = crate::Reg; #[doc = "PRIORITY THRESHOLD Register for hart 2"] pub mod threshold_2; -#[doc = "claimplete_2 (rw) register accessor: CLAIM and COMPLETE Register for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`claimplete_2`] +#[doc = "claimplete_2 (rw) register accessor: CLAIM and COMPLETE Register for hart 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@claimplete_2`] module"] pub type CLAIMPLETE_2 = crate::Reg; #[doc = "CLAIM and COMPLETE Register for hart 2"] pub mod claimplete_2; -#[doc = "threshold_3 (rw) register accessor: PRIORITY THRESHOLD Register for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`threshold_3`] +#[doc = "threshold_3 (rw) register accessor: PRIORITY THRESHOLD Register for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@threshold_3`] module"] pub type THRESHOLD_3 = crate::Reg; #[doc = "PRIORITY THRESHOLD Register for hart 3"] pub mod threshold_3; -#[doc = "claimplete_3 (rw) register accessor: CLAIM and COMPLETE Register for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`claimplete_3`] +#[doc = "claimplete_3 (rw) register accessor: CLAIM and COMPLETE Register for hart 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@claimplete_3`] module"] pub type CLAIMPLETE_3 = crate::Reg; #[doc = "CLAIM and COMPLETE Register for hart 3"] pub mod claimplete_3; -#[doc = "threshold_4 (rw) register accessor: PRIORITY THRESHOLD Register for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`threshold_4`] +#[doc = "threshold_4 (rw) register accessor: PRIORITY THRESHOLD Register for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@threshold_4`] module"] pub type THRESHOLD_4 = crate::Reg; #[doc = "PRIORITY THRESHOLD Register for hart 4"] pub mod threshold_4; -#[doc = "claimplete_4 (rw) register accessor: CLAIM and COMPLETE Register for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`claimplete_4`] +#[doc = "claimplete_4 (rw) register accessor: CLAIM and COMPLETE Register for hart 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimplete_4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimplete_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@claimplete_4`] module"] pub type CLAIMPLETE_4 = crate::Reg; #[doc = "CLAIM and COMPLETE Register for hart 4"] diff --git a/jh7110-vf2-13b-pac/src/plic/claimplete_0.rs b/jh7110-vf2-13b-pac/src/plic/claimplete_0.rs index 8c7b2a1..309a345 100644 --- a/jh7110-vf2-13b-pac/src/plic/claimplete_0.rs +++ b/jh7110-vf2-13b-pac/src/plic/claimplete_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/claimplete_1.rs b/jh7110-vf2-13b-pac/src/plic/claimplete_1.rs index d25d107..71b03ed 100644 --- a/jh7110-vf2-13b-pac/src/plic/claimplete_1.rs +++ b/jh7110-vf2-13b-pac/src/plic/claimplete_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/claimplete_2.rs b/jh7110-vf2-13b-pac/src/plic/claimplete_2.rs index df5f3c6..b8c77a7 100644 --- a/jh7110-vf2-13b-pac/src/plic/claimplete_2.rs +++ b/jh7110-vf2-13b-pac/src/plic/claimplete_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/claimplete_3.rs b/jh7110-vf2-13b-pac/src/plic/claimplete_3.rs index 9980c87..77ba974 100644 --- a/jh7110-vf2-13b-pac/src/plic/claimplete_3.rs +++ b/jh7110-vf2-13b-pac/src/plic/claimplete_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/claimplete_4.rs b/jh7110-vf2-13b-pac/src/plic/claimplete_4.rs index 43b2a4a..5ee1c30 100644 --- a/jh7110-vf2-13b-pac/src/plic/claimplete_4.rs +++ b/jh7110-vf2-13b-pac/src/plic/claimplete_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_0_0.rs b/jh7110-vf2-13b-pac/src/plic/enable_0_0.rs index 9133aae..4a37545 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_0_0.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_0_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_0_1.rs b/jh7110-vf2-13b-pac/src/plic/enable_0_1.rs index 4f9e123..f8c0460 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_0_1.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_0_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_0_2.rs b/jh7110-vf2-13b-pac/src/plic/enable_0_2.rs index 5244d6d..bc1016b 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_0_2.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_0_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_0_3.rs b/jh7110-vf2-13b-pac/src/plic/enable_0_3.rs index 9368da5..6918758 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_0_3.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_0_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_0_4.rs b/jh7110-vf2-13b-pac/src/plic/enable_0_4.rs index 65619b0..d1825e0 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_0_4.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_0_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_1_0.rs b/jh7110-vf2-13b-pac/src/plic/enable_1_0.rs index 56ce5ec..d091de1 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_1_0.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_1_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_1_1.rs b/jh7110-vf2-13b-pac/src/plic/enable_1_1.rs index 5e51188..a03d978 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_1_1.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_1_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_1_2.rs b/jh7110-vf2-13b-pac/src/plic/enable_1_2.rs index 7a53a26..2c1899e 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_1_2.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_1_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_1_3.rs b/jh7110-vf2-13b-pac/src/plic/enable_1_3.rs index faedbfd..e962578 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_1_3.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_1_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_1_4.rs b/jh7110-vf2-13b-pac/src/plic/enable_1_4.rs index 70387de..57ad871 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_1_4.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_1_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_2_0.rs b/jh7110-vf2-13b-pac/src/plic/enable_2_0.rs index 6020e35..1691b10 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_2_0.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_2_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_2_1.rs b/jh7110-vf2-13b-pac/src/plic/enable_2_1.rs index 61e1ddf..c909155 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_2_1.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_2_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_2_2.rs b/jh7110-vf2-13b-pac/src/plic/enable_2_2.rs index 32c1275..9983cf7 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_2_2.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_2_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_2_3.rs b/jh7110-vf2-13b-pac/src/plic/enable_2_3.rs index 117eb71..6c59c83 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_2_3.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_2_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_2_4.rs b/jh7110-vf2-13b-pac/src/plic/enable_2_4.rs index 7e696c5..90b0170 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_2_4.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_2_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_3_0.rs b/jh7110-vf2-13b-pac/src/plic/enable_3_0.rs index 9c95f64..6788c15 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_3_0.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_3_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_3_1.rs b/jh7110-vf2-13b-pac/src/plic/enable_3_1.rs index 275fea8..441f1fe 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_3_1.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_3_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_3_2.rs b/jh7110-vf2-13b-pac/src/plic/enable_3_2.rs index eca95ad..7a3eff1 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_3_2.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_3_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_3_3.rs b/jh7110-vf2-13b-pac/src/plic/enable_3_3.rs index 1a0c02a..29f11f6 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_3_3.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_3_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_3_4.rs b/jh7110-vf2-13b-pac/src/plic/enable_3_4.rs index a787567..cf5a3b6 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_3_4.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_3_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_4_0.rs b/jh7110-vf2-13b-pac/src/plic/enable_4_0.rs index d53199e..f225813 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_4_0.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_4_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_4_1.rs b/jh7110-vf2-13b-pac/src/plic/enable_4_1.rs index d7e9c36..c75a645 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_4_1.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_4_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_4_2.rs b/jh7110-vf2-13b-pac/src/plic/enable_4_2.rs index c5826fb..616309f 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_4_2.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_4_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_4_3.rs b/jh7110-vf2-13b-pac/src/plic/enable_4_3.rs index 3d7f221..88e2dc2 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_4_3.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_4_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/enable_4_4.rs b/jh7110-vf2-13b-pac/src/plic/enable_4_4.rs index d7f4788..18bd59b 100644 --- a/jh7110-vf2-13b-pac/src/plic/enable_4_4.rs +++ b/jh7110-vf2-13b-pac/src/plic/enable_4_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/pending_0.rs b/jh7110-vf2-13b-pac/src/plic/pending_0.rs index d727a23..e716f6e 100644 --- a/jh7110-vf2-13b-pac/src/plic/pending_0.rs +++ b/jh7110-vf2-13b-pac/src/plic/pending_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/pending_1.rs b/jh7110-vf2-13b-pac/src/plic/pending_1.rs index 1ab928f..36eb516 100644 --- a/jh7110-vf2-13b-pac/src/plic/pending_1.rs +++ b/jh7110-vf2-13b-pac/src/plic/pending_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/pending_2.rs b/jh7110-vf2-13b-pac/src/plic/pending_2.rs index 16dc73b..c198eeb 100644 --- a/jh7110-vf2-13b-pac/src/plic/pending_2.rs +++ b/jh7110-vf2-13b-pac/src/plic/pending_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/pending_3.rs b/jh7110-vf2-13b-pac/src/plic/pending_3.rs index 01eca65..031b4d4 100644 --- a/jh7110-vf2-13b-pac/src/plic/pending_3.rs +++ b/jh7110-vf2-13b-pac/src/plic/pending_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/pending_4.rs b/jh7110-vf2-13b-pac/src/plic/pending_4.rs index 89e175d..8398e03 100644 --- a/jh7110-vf2-13b-pac/src/plic/pending_4.rs +++ b/jh7110-vf2-13b-pac/src/plic/pending_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_1.rs b/jh7110-vf2-13b-pac/src/plic/priority_1.rs index 89a2c4c..14af182 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_1.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_10.rs b/jh7110-vf2-13b-pac/src/plic/priority_10.rs index da4d61a..ae62e7f 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_10.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_10.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_100.rs b/jh7110-vf2-13b-pac/src/plic/priority_100.rs index 59cb32e..092d916 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_100.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_100.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_101.rs b/jh7110-vf2-13b-pac/src/plic/priority_101.rs index 6baf61e..5f3d5d8 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_101.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_101.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_102.rs b/jh7110-vf2-13b-pac/src/plic/priority_102.rs index c042534..87e17ba 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_102.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_102.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_103.rs b/jh7110-vf2-13b-pac/src/plic/priority_103.rs index 2c9f028..c03dede 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_103.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_103.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_104.rs b/jh7110-vf2-13b-pac/src/plic/priority_104.rs index 2230d10..deb4152 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_104.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_104.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_105.rs b/jh7110-vf2-13b-pac/src/plic/priority_105.rs index 26c4e2c..08f405c 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_105.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_105.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_106.rs b/jh7110-vf2-13b-pac/src/plic/priority_106.rs index 822f269..3a3be00 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_106.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_106.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_107.rs b/jh7110-vf2-13b-pac/src/plic/priority_107.rs index 6445925..89dbc01 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_107.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_107.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_108.rs b/jh7110-vf2-13b-pac/src/plic/priority_108.rs index 1686dc6..79c2d77 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_108.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_108.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_109.rs b/jh7110-vf2-13b-pac/src/plic/priority_109.rs index dc5e268..c8f90eb 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_109.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_109.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_11.rs b/jh7110-vf2-13b-pac/src/plic/priority_11.rs index 67ed54c..898a24a 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_11.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_11.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_110.rs b/jh7110-vf2-13b-pac/src/plic/priority_110.rs index f2aaaea..daf1b9a 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_110.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_110.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_111.rs b/jh7110-vf2-13b-pac/src/plic/priority_111.rs index 1388d35..1b19243 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_111.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_111.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_112.rs b/jh7110-vf2-13b-pac/src/plic/priority_112.rs index d290c0f..b5fa4ac 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_112.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_112.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_113.rs b/jh7110-vf2-13b-pac/src/plic/priority_113.rs index 10969f5..52df03e 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_113.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_113.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_114.rs b/jh7110-vf2-13b-pac/src/plic/priority_114.rs index eb98b42..7d4fa73 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_114.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_114.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_115.rs b/jh7110-vf2-13b-pac/src/plic/priority_115.rs index 2e7df6f..160973c 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_115.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_115.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_116.rs b/jh7110-vf2-13b-pac/src/plic/priority_116.rs index 45067de..6a44fb4 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_116.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_116.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_117.rs b/jh7110-vf2-13b-pac/src/plic/priority_117.rs index 0d80317..1fcd72e 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_117.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_117.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_118.rs b/jh7110-vf2-13b-pac/src/plic/priority_118.rs index f73de88..0a16f24 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_118.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_118.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_119.rs b/jh7110-vf2-13b-pac/src/plic/priority_119.rs index 4beda48..a27fd7d 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_119.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_119.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_12.rs b/jh7110-vf2-13b-pac/src/plic/priority_12.rs index 15817eb..14597b2 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_12.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_12.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_120.rs b/jh7110-vf2-13b-pac/src/plic/priority_120.rs index 21249b1..071cd28 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_120.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_120.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_121.rs b/jh7110-vf2-13b-pac/src/plic/priority_121.rs index d24778d..aabcf64 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_121.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_121.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_122.rs b/jh7110-vf2-13b-pac/src/plic/priority_122.rs index 463a95f..1f5aee5 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_122.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_122.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_123.rs b/jh7110-vf2-13b-pac/src/plic/priority_123.rs index 46f5339..4a9a3d1 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_123.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_123.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_124.rs b/jh7110-vf2-13b-pac/src/plic/priority_124.rs index 87d348d..6cf6ce0 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_124.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_124.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_125.rs b/jh7110-vf2-13b-pac/src/plic/priority_125.rs index 837d895..902c421 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_125.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_125.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_126.rs b/jh7110-vf2-13b-pac/src/plic/priority_126.rs index 902fc89..7c8c322 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_126.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_126.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_127.rs b/jh7110-vf2-13b-pac/src/plic/priority_127.rs index b0fe334..051179d 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_127.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_127.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_128.rs b/jh7110-vf2-13b-pac/src/plic/priority_128.rs index 6e888f7..4937dfe 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_128.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_128.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_129.rs b/jh7110-vf2-13b-pac/src/plic/priority_129.rs index 5602dad..3a22cda 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_129.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_129.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_13.rs b/jh7110-vf2-13b-pac/src/plic/priority_13.rs index f77071e..1e717fb 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_13.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_13.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_130.rs b/jh7110-vf2-13b-pac/src/plic/priority_130.rs index 72ec4cb..154fb8c 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_130.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_130.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_131.rs b/jh7110-vf2-13b-pac/src/plic/priority_131.rs index 02600ae..3ef39ed 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_131.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_131.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_132.rs b/jh7110-vf2-13b-pac/src/plic/priority_132.rs index cd0928b..e88db40 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_132.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_132.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_133.rs b/jh7110-vf2-13b-pac/src/plic/priority_133.rs index 615c9b9..1f2b499 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_133.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_133.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_134.rs b/jh7110-vf2-13b-pac/src/plic/priority_134.rs index 2514c00..af67dfd 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_134.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_134.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_135.rs b/jh7110-vf2-13b-pac/src/plic/priority_135.rs index a7a3a19..aceba08 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_135.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_135.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_136.rs b/jh7110-vf2-13b-pac/src/plic/priority_136.rs index be5df2a..f135836 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_136.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_136.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_14.rs b/jh7110-vf2-13b-pac/src/plic/priority_14.rs index e7f630a..f36f0e7 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_14.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_14.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_15.rs b/jh7110-vf2-13b-pac/src/plic/priority_15.rs index 6f39ea8..c560a75 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_15.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_15.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_16.rs b/jh7110-vf2-13b-pac/src/plic/priority_16.rs index 016251b..ccbb07f 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_16.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_16.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_17.rs b/jh7110-vf2-13b-pac/src/plic/priority_17.rs index 15c9e24..6d68631 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_17.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_17.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_18.rs b/jh7110-vf2-13b-pac/src/plic/priority_18.rs index d9e70c8..7b68752 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_18.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_18.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_19.rs b/jh7110-vf2-13b-pac/src/plic/priority_19.rs index e1cbce8..00ed894 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_19.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_19.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_2.rs b/jh7110-vf2-13b-pac/src/plic/priority_2.rs index 1561743..d0dfb0c 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_2.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_20.rs b/jh7110-vf2-13b-pac/src/plic/priority_20.rs index 4e14bf5..d5b049a 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_20.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_20.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_21.rs b/jh7110-vf2-13b-pac/src/plic/priority_21.rs index b4f712a..fbd03e0 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_21.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_21.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_22.rs b/jh7110-vf2-13b-pac/src/plic/priority_22.rs index adc7327..1a0ef02 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_22.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_22.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_23.rs b/jh7110-vf2-13b-pac/src/plic/priority_23.rs index dee61df..313f17f 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_23.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_23.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_24.rs b/jh7110-vf2-13b-pac/src/plic/priority_24.rs index 2b1d82b..413a617 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_24.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_24.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_25.rs b/jh7110-vf2-13b-pac/src/plic/priority_25.rs index a8f2863..b89a622 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_25.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_25.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_26.rs b/jh7110-vf2-13b-pac/src/plic/priority_26.rs index b67a6fd..98933ba 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_26.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_26.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_27.rs b/jh7110-vf2-13b-pac/src/plic/priority_27.rs index 4c20368..611e611 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_27.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_27.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_28.rs b/jh7110-vf2-13b-pac/src/plic/priority_28.rs index df68c98..e3be6ec 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_28.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_28.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_29.rs b/jh7110-vf2-13b-pac/src/plic/priority_29.rs index a524f03..941b4df 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_29.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_29.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_3.rs b/jh7110-vf2-13b-pac/src/plic/priority_3.rs index 682d6ca..9cf51b3 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_3.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_30.rs b/jh7110-vf2-13b-pac/src/plic/priority_30.rs index b3250f5..3a94aeb 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_30.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_30.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_31.rs b/jh7110-vf2-13b-pac/src/plic/priority_31.rs index c11c081..da4c621 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_31.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_31.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_32.rs b/jh7110-vf2-13b-pac/src/plic/priority_32.rs index 66db062..23c9cc6 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_32.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_32.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_33.rs b/jh7110-vf2-13b-pac/src/plic/priority_33.rs index c2d33cf..68f75fe 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_33.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_33.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_34.rs b/jh7110-vf2-13b-pac/src/plic/priority_34.rs index 7c6575c..16ec987 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_34.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_34.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_35.rs b/jh7110-vf2-13b-pac/src/plic/priority_35.rs index ebc3d7e..bb78a11 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_35.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_35.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_36.rs b/jh7110-vf2-13b-pac/src/plic/priority_36.rs index d45bc5c..934a266 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_36.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_36.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_37.rs b/jh7110-vf2-13b-pac/src/plic/priority_37.rs index 59ad4b9..684e44b 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_37.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_37.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_38.rs b/jh7110-vf2-13b-pac/src/plic/priority_38.rs index 40d64cc..d80810f 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_38.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_38.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_39.rs b/jh7110-vf2-13b-pac/src/plic/priority_39.rs index 3270b4f..4a6ecb7 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_39.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_39.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_4.rs b/jh7110-vf2-13b-pac/src/plic/priority_4.rs index ce93212..f251a12 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_4.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_40.rs b/jh7110-vf2-13b-pac/src/plic/priority_40.rs index 8eb085d..2792352 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_40.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_40.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_41.rs b/jh7110-vf2-13b-pac/src/plic/priority_41.rs index 7e150ae..7c66f0f 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_41.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_41.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_42.rs b/jh7110-vf2-13b-pac/src/plic/priority_42.rs index 7e69daa..a429467 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_42.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_42.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_43.rs b/jh7110-vf2-13b-pac/src/plic/priority_43.rs index 412e4f5..40be5d5 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_43.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_43.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_44.rs b/jh7110-vf2-13b-pac/src/plic/priority_44.rs index 9c412f5..ed41ba6 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_44.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_44.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_45.rs b/jh7110-vf2-13b-pac/src/plic/priority_45.rs index 7638a0a..4596730 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_45.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_45.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_46.rs b/jh7110-vf2-13b-pac/src/plic/priority_46.rs index 251dd67..66c6b21 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_46.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_46.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_47.rs b/jh7110-vf2-13b-pac/src/plic/priority_47.rs index f5f4cfa..7f969c0 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_47.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_47.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_48.rs b/jh7110-vf2-13b-pac/src/plic/priority_48.rs index b1ec29c..cc848bc 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_48.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_48.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_49.rs b/jh7110-vf2-13b-pac/src/plic/priority_49.rs index f37ecf9..962a102 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_49.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_49.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_5.rs b/jh7110-vf2-13b-pac/src/plic/priority_5.rs index ab2392d..066b5be 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_5.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_5.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_50.rs b/jh7110-vf2-13b-pac/src/plic/priority_50.rs index b58ca84..8202647 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_50.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_50.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_51.rs b/jh7110-vf2-13b-pac/src/plic/priority_51.rs index efe3297..e990197 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_51.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_51.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_52.rs b/jh7110-vf2-13b-pac/src/plic/priority_52.rs index 3a59d4d..6de4a93 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_52.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_52.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_53.rs b/jh7110-vf2-13b-pac/src/plic/priority_53.rs index 33065b1..ee1c587 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_53.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_53.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_54.rs b/jh7110-vf2-13b-pac/src/plic/priority_54.rs index b2140fc..ea867e3 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_54.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_54.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_55.rs b/jh7110-vf2-13b-pac/src/plic/priority_55.rs index 8958031..caf4382 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_55.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_55.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_56.rs b/jh7110-vf2-13b-pac/src/plic/priority_56.rs index 574abb0..09057d8 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_56.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_56.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_57.rs b/jh7110-vf2-13b-pac/src/plic/priority_57.rs index 2faa376..dd2d40d 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_57.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_57.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_58.rs b/jh7110-vf2-13b-pac/src/plic/priority_58.rs index a57dbb4..6858abf 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_58.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_58.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_59.rs b/jh7110-vf2-13b-pac/src/plic/priority_59.rs index 1528850..11a98bb 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_59.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_59.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_6.rs b/jh7110-vf2-13b-pac/src/plic/priority_6.rs index ab5418b..89ae6ae 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_6.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_6.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_60.rs b/jh7110-vf2-13b-pac/src/plic/priority_60.rs index d8e5b6d..1f72fc3 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_60.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_60.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_61.rs b/jh7110-vf2-13b-pac/src/plic/priority_61.rs index 9b538df..2050250 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_61.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_61.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_62.rs b/jh7110-vf2-13b-pac/src/plic/priority_62.rs index b104138..565e1be 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_62.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_62.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_63.rs b/jh7110-vf2-13b-pac/src/plic/priority_63.rs index ed1a48e..5a1854f 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_63.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_63.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_64.rs b/jh7110-vf2-13b-pac/src/plic/priority_64.rs index 327d342..a18646a 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_64.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_64.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_65.rs b/jh7110-vf2-13b-pac/src/plic/priority_65.rs index 3dbdc1f..c7ce4a8 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_65.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_65.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_66.rs b/jh7110-vf2-13b-pac/src/plic/priority_66.rs index 7a5cc54..a8b9b96 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_66.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_66.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_67.rs b/jh7110-vf2-13b-pac/src/plic/priority_67.rs index 1d91f1a..503c6fc 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_67.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_67.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_68.rs b/jh7110-vf2-13b-pac/src/plic/priority_68.rs index e538789..bcae2d2 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_68.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_68.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_69.rs b/jh7110-vf2-13b-pac/src/plic/priority_69.rs index 33c3036..c6727bd 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_69.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_69.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_7.rs b/jh7110-vf2-13b-pac/src/plic/priority_7.rs index 59313df..4f781bd 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_7.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_7.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_70.rs b/jh7110-vf2-13b-pac/src/plic/priority_70.rs index bbde1c5..57f263d 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_70.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_70.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_71.rs b/jh7110-vf2-13b-pac/src/plic/priority_71.rs index 510c12d..8b907db 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_71.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_71.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_72.rs b/jh7110-vf2-13b-pac/src/plic/priority_72.rs index d9e146b..df9d8b9 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_72.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_72.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_73.rs b/jh7110-vf2-13b-pac/src/plic/priority_73.rs index 99d2fdf..06b91f1 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_73.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_73.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_74.rs b/jh7110-vf2-13b-pac/src/plic/priority_74.rs index d1fa3dc..14fdec1 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_74.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_74.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_75.rs b/jh7110-vf2-13b-pac/src/plic/priority_75.rs index 7c618ad..3743a49 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_75.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_75.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_76.rs b/jh7110-vf2-13b-pac/src/plic/priority_76.rs index 0a6ee28..5ca57d9 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_76.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_76.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_77.rs b/jh7110-vf2-13b-pac/src/plic/priority_77.rs index 25e404a..c61835d 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_77.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_77.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_78.rs b/jh7110-vf2-13b-pac/src/plic/priority_78.rs index 8fca3e5..c9c7802 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_78.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_78.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_79.rs b/jh7110-vf2-13b-pac/src/plic/priority_79.rs index 2a3dc4f..e55c5bd 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_79.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_79.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_8.rs b/jh7110-vf2-13b-pac/src/plic/priority_8.rs index 5a0bc51..28aabc8 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_8.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_8.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_80.rs b/jh7110-vf2-13b-pac/src/plic/priority_80.rs index 052fb8f..2cfbe0c 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_80.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_80.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_81.rs b/jh7110-vf2-13b-pac/src/plic/priority_81.rs index 894c968..ddc872f 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_81.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_81.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_82.rs b/jh7110-vf2-13b-pac/src/plic/priority_82.rs index 6a6f7cb..554c940 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_82.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_82.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_83.rs b/jh7110-vf2-13b-pac/src/plic/priority_83.rs index 8d1851f..d1e9bbe 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_83.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_83.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_84.rs b/jh7110-vf2-13b-pac/src/plic/priority_84.rs index 09df181..cf97ab5 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_84.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_84.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_85.rs b/jh7110-vf2-13b-pac/src/plic/priority_85.rs index f3231d8..4ad3a05 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_85.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_85.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_86.rs b/jh7110-vf2-13b-pac/src/plic/priority_86.rs index ea7d42c..4dc1ae5 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_86.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_86.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_87.rs b/jh7110-vf2-13b-pac/src/plic/priority_87.rs index f8a4257..88a3b6b 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_87.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_87.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_88.rs b/jh7110-vf2-13b-pac/src/plic/priority_88.rs index 65e64e4..f97b14a 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_88.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_88.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_89.rs b/jh7110-vf2-13b-pac/src/plic/priority_89.rs index 7d49585..0ca387d 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_89.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_89.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_9.rs b/jh7110-vf2-13b-pac/src/plic/priority_9.rs index 24e030b..5704dfa 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_9.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_9.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_90.rs b/jh7110-vf2-13b-pac/src/plic/priority_90.rs index 5e86147..2697019 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_90.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_90.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_91.rs b/jh7110-vf2-13b-pac/src/plic/priority_91.rs index 69ace79..bf640c8 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_91.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_91.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_92.rs b/jh7110-vf2-13b-pac/src/plic/priority_92.rs index d00bb9a..6ea53de 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_92.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_92.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_93.rs b/jh7110-vf2-13b-pac/src/plic/priority_93.rs index 202b810..b6b5394 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_93.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_93.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_94.rs b/jh7110-vf2-13b-pac/src/plic/priority_94.rs index b6149e3..e5af85c 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_94.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_94.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_95.rs b/jh7110-vf2-13b-pac/src/plic/priority_95.rs index aa9eedf..94326ee 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_95.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_95.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_96.rs b/jh7110-vf2-13b-pac/src/plic/priority_96.rs index 68a103a..cdc85e0 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_96.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_96.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_97.rs b/jh7110-vf2-13b-pac/src/plic/priority_97.rs index 25e467e..7595282 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_97.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_97.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_98.rs b/jh7110-vf2-13b-pac/src/plic/priority_98.rs index 491167a..f9bff80 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_98.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_98.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/priority_99.rs b/jh7110-vf2-13b-pac/src/plic/priority_99.rs index 3db062c..66302fe 100644 --- a/jh7110-vf2-13b-pac/src/plic/priority_99.rs +++ b/jh7110-vf2-13b-pac/src/plic/priority_99.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/threshold_0.rs b/jh7110-vf2-13b-pac/src/plic/threshold_0.rs index 72e255d..67e7685 100644 --- a/jh7110-vf2-13b-pac/src/plic/threshold_0.rs +++ b/jh7110-vf2-13b-pac/src/plic/threshold_0.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/threshold_1.rs b/jh7110-vf2-13b-pac/src/plic/threshold_1.rs index b026258..4ee93ce 100644 --- a/jh7110-vf2-13b-pac/src/plic/threshold_1.rs +++ b/jh7110-vf2-13b-pac/src/plic/threshold_1.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/threshold_2.rs b/jh7110-vf2-13b-pac/src/plic/threshold_2.rs index 46a0d5e..cb915f7 100644 --- a/jh7110-vf2-13b-pac/src/plic/threshold_2.rs +++ b/jh7110-vf2-13b-pac/src/plic/threshold_2.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/threshold_3.rs b/jh7110-vf2-13b-pac/src/plic/threshold_3.rs index 04d7d53..96e5722 100644 --- a/jh7110-vf2-13b-pac/src/plic/threshold_3.rs +++ b/jh7110-vf2-13b-pac/src/plic/threshold_3.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/plic/threshold_4.rs b/jh7110-vf2-13b-pac/src/plic/threshold_4.rs index d85ce7b..933ec87 100644 --- a/jh7110-vf2-13b-pac/src/plic/threshold_4.rs +++ b/jh7110-vf2-13b-pac/src/plic/threshold_4.rs @@ -9,11 +9,15 @@ impl core::fmt::Debug for R { } impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - self.read().fmt(f) + core::fmt::Debug::fmt(&self.read(), f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu.rs b/jh7110-vf2-13b-pac/src/pmu.rs index 26e11b8..2a44091 100644 --- a/jh7110-vf2-13b-pac/src/pmu.rs +++ b/jh7110-vf2-13b-pac/src/pmu.rs @@ -2,157 +2,243 @@ #[repr(C)] pub struct RegisterBlock { _reserved0: [u8; 0x04], - #[doc = "0x04 - Hardware Event Turn-On Mask"] - pub hard_event_turn_on_mask: HARD_EVENT_TURN_ON_MASK, + hard_event_turn_on_mask: HARD_EVENT_TURN_ON_MASK, _reserved1: [u8; 0x04], + soft_turn_on_power_mode: SOFT_TURN_ON_POWER_MODE, + soft_turn_off_power_mode: SOFT_TURN_OFF_POWER_MODE, + timeout_seq_thd: TIMEOUT_SEQ_THD, + pdc0: PDC0, + pdc1: PDC1, + pdc2: PDC2, + _reserved7: [u8; 0x20], + sw_encourage: SW_ENCOURAGE, + tim: TIM, + pch_bypass: PCH_BYPASS, + pch_pstate: PCH_PSTATE, + pch_timeout: PCH_TIMEOUT, + lp_timeout: LP_TIMEOUT, + hard_turn_on_power_mode: HARD_TURN_ON_POWER_MODE, + _reserved14: [u8; 0x20], + current_power_mode: CURRENT_POWER_MODE, + current_seq_state: CURRENT_SEQ_STATE, + event_status: EVENT_STATUS, + int_status: INT_STATUS, + hw_event_crd: HW_EVENT_CRD, + encourage_type_crd: ENCOURAGE_TYPE_CRD, + pch_active: PCH_ACTIVE, +} +impl RegisterBlock { + #[doc = "0x04 - Hardware Event Turn-On Mask"] + #[inline(always)] + pub const fn hard_event_turn_on_mask(&self) -> &HARD_EVENT_TURN_ON_MASK { + &self.hard_event_turn_on_mask + } #[doc = "0x0c - Software Turn-On Power Mode"] - pub soft_turn_on_power_mode: SOFT_TURN_ON_POWER_MODE, + #[inline(always)] + pub const fn soft_turn_on_power_mode(&self) -> &SOFT_TURN_ON_POWER_MODE { + &self.soft_turn_on_power_mode + } #[doc = "0x10 - Software Turn-Off Power Mode"] - pub soft_turn_off_power_mode: SOFT_TURN_OFF_POWER_MODE, + #[inline(always)] + pub const fn soft_turn_off_power_mode(&self) -> &SOFT_TURN_OFF_POWER_MODE { + &self.soft_turn_off_power_mode + } #[doc = "0x14 - Threshold Sequence Timeout"] - pub timeout_seq_thd: TIMEOUT_SEQ_THD, + #[inline(always)] + pub const fn timeout_seq_thd(&self) -> &TIMEOUT_SEQ_THD { + &self.timeout_seq_thd + } #[doc = "0x18 - Powerdomain Cascade 0"] - pub pdc0: PDC0, + #[inline(always)] + pub const fn pdc0(&self) -> &PDC0 { + &self.pdc0 + } #[doc = "0x1c - Powerdomain Cascade 1"] - pub pdc1: PDC1, + #[inline(always)] + pub const fn pdc1(&self) -> &PDC1 { + &self.pdc1 + } #[doc = "0x20 - Powerdomain Cascade 2"] - pub pdc2: PDC2, - _reserved7: [u8; 0x20], + #[inline(always)] + pub const fn pdc2(&self) -> &PDC2 { + &self.pdc2 + } #[doc = "0x44 - Software Encouragement"] - pub sw_encourage: SW_ENCOURAGE, + #[inline(always)] + pub const fn sw_encourage(&self) -> &SW_ENCOURAGE { + &self.sw_encourage + } #[doc = "0x48 - TIMER Interrupt Mask"] - pub tim: TIM, + #[inline(always)] + pub const fn tim(&self) -> &TIM { + &self.tim + } #[doc = "0x4c - P-channel Bypass"] - pub pch_bypass: PCH_BYPASS, + #[inline(always)] + pub const fn pch_bypass(&self) -> &PCH_BYPASS { + &self.pch_bypass + } #[doc = "0x50 - P-channel PSTATE"] - pub pch_pstate: PCH_PSTATE, + #[inline(always)] + pub const fn pch_pstate(&self) -> &PCH_PSTATE { + &self.pch_pstate + } #[doc = "0x54 - P-channel Timeout Threshold"] - pub pch_timeout: PCH_TIMEOUT, + #[inline(always)] + pub const fn pch_timeout(&self) -> &PCH_TIMEOUT { + &self.pch_timeout + } #[doc = "0x58 - LP Cell Control Timeout Threshold"] - pub lp_timeout: LP_TIMEOUT, + #[inline(always)] + pub const fn lp_timeout(&self) -> &LP_TIMEOUT { + &self.lp_timeout + } #[doc = "0x5c - Hardware Turn-On Power Mode"] - pub hard_turn_on_power_mode: HARD_TURN_ON_POWER_MODE, - _reserved14: [u8; 0x20], + #[inline(always)] + pub const fn hard_turn_on_power_mode(&self) -> &HARD_TURN_ON_POWER_MODE { + &self.hard_turn_on_power_mode + } #[doc = "0x80 - Current Power Mode"] - pub current_power_mode: CURRENT_POWER_MODE, + #[inline(always)] + pub const fn current_power_mode(&self) -> &CURRENT_POWER_MODE { + &self.current_power_mode + } #[doc = "0x84 - Current Sequence State"] - pub current_seq_state: CURRENT_SEQ_STATE, + #[inline(always)] + pub const fn current_seq_state(&self) -> &CURRENT_SEQ_STATE { + &self.current_seq_state + } #[doc = "0x88 - PMU Event Status"] - pub event_status: EVENT_STATUS, + #[inline(always)] + pub const fn event_status(&self) -> &EVENT_STATUS { + &self.event_status + } #[doc = "0x8c - PMU Interrupt Status"] - pub int_status: INT_STATUS, + #[inline(always)] + pub const fn int_status(&self) -> &INT_STATUS { + &self.int_status + } #[doc = "0x90 - Hardware Event Record"] - pub hw_event_crd: HW_EVENT_CRD, + #[inline(always)] + pub const fn hw_event_crd(&self) -> &HW_EVENT_CRD { + &self.hw_event_crd + } #[doc = "0x94 - Hardware Event Type Record"] - pub encourage_type_crd: ENCOURAGE_TYPE_CRD, + #[inline(always)] + pub const fn encourage_type_crd(&self) -> &ENCOURAGE_TYPE_CRD { + &self.encourage_type_crd + } #[doc = "0x98 - P-channel PACTIVE Status"] - pub pch_active: PCH_ACTIVE, + #[inline(always)] + pub const fn pch_active(&self) -> &PCH_ACTIVE { + &self.pch_active + } } -#[doc = "hard_event_turn_on_mask (rw) register accessor: Hardware Event Turn-On Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hard_event_turn_on_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hard_event_turn_on_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hard_event_turn_on_mask`] +#[doc = "hard_event_turn_on_mask (rw) register accessor: Hardware Event Turn-On Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hard_event_turn_on_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hard_event_turn_on_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hard_event_turn_on_mask`] module"] pub type HARD_EVENT_TURN_ON_MASK = crate::Reg; #[doc = "Hardware Event Turn-On Mask"] pub mod hard_event_turn_on_mask; -#[doc = "soft_turn_on_power_mode (rw) register accessor: Software Turn-On Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_turn_on_power_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_turn_on_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_turn_on_power_mode`] +#[doc = "soft_turn_on_power_mode (rw) register accessor: Software Turn-On Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_turn_on_power_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_turn_on_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_turn_on_power_mode`] module"] pub type SOFT_TURN_ON_POWER_MODE = crate::Reg; #[doc = "Software Turn-On Power Mode"] pub mod soft_turn_on_power_mode; -#[doc = "soft_turn_off_power_mode (rw) register accessor: Software Turn-Off Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_turn_off_power_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_turn_off_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_turn_off_power_mode`] +#[doc = "soft_turn_off_power_mode (rw) register accessor: Software Turn-Off Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_turn_off_power_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_turn_off_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_turn_off_power_mode`] module"] pub type SOFT_TURN_OFF_POWER_MODE = crate::Reg; #[doc = "Software Turn-Off Power Mode"] pub mod soft_turn_off_power_mode; -#[doc = "timeout_seq_thd (rw) register accessor: Threshold Sequence Timeout\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_seq_thd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timeout_seq_thd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`timeout_seq_thd`] +#[doc = "timeout_seq_thd (rw) register accessor: Threshold Sequence Timeout\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_seq_thd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timeout_seq_thd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timeout_seq_thd`] module"] pub type TIMEOUT_SEQ_THD = crate::Reg; #[doc = "Threshold Sequence Timeout"] pub mod timeout_seq_thd; -#[doc = "pdc0 (rw) register accessor: Powerdomain Cascade 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pdc0`] +#[doc = "pdc0 (rw) register accessor: Powerdomain Cascade 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdc0`] module"] pub type PDC0 = crate::Reg; #[doc = "Powerdomain Cascade 0"] pub mod pdc0; -#[doc = "pdc1 (rw) register accessor: Powerdomain Cascade 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pdc1`] +#[doc = "pdc1 (rw) register accessor: Powerdomain Cascade 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdc1`] module"] pub type PDC1 = crate::Reg; #[doc = "Powerdomain Cascade 1"] pub mod pdc1; -#[doc = "pdc2 (rw) register accessor: Powerdomain Cascade 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pdc2`] +#[doc = "pdc2 (rw) register accessor: Powerdomain Cascade 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdc2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdc2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdc2`] module"] pub type PDC2 = crate::Reg; #[doc = "Powerdomain Cascade 2"] pub mod pdc2; -#[doc = "sw_encourage (rw) register accessor: Software Encouragement\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_encourage::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_encourage::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sw_encourage`] +#[doc = "sw_encourage (rw) register accessor: Software Encouragement\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_encourage::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_encourage::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sw_encourage`] module"] pub type SW_ENCOURAGE = crate::Reg; #[doc = "Software Encouragement"] pub mod sw_encourage; -#[doc = "tim (rw) register accessor: TIMER Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tim`] +#[doc = "tim (rw) register accessor: TIMER Interrupt Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim`] module"] pub type TIM = crate::Reg; #[doc = "TIMER Interrupt Mask"] pub mod tim; -#[doc = "pch_bypass (rw) register accessor: P-channel Bypass\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_bypass::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pch_bypass`] +#[doc = "pch_bypass (rw) register accessor: P-channel Bypass\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_bypass::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pch_bypass`] module"] pub type PCH_BYPASS = crate::Reg; #[doc = "P-channel Bypass"] pub mod pch_bypass; -#[doc = "pch_pstate (rw) register accessor: P-channel PSTATE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_pstate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_pstate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pch_pstate`] +#[doc = "pch_pstate (rw) register accessor: P-channel PSTATE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_pstate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_pstate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pch_pstate`] module"] pub type PCH_PSTATE = crate::Reg; #[doc = "P-channel PSTATE"] pub mod pch_pstate; -#[doc = "pch_timeout (rw) register accessor: P-channel Timeout Threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pch_timeout`] +#[doc = "pch_timeout (rw) register accessor: P-channel Timeout Threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pch_timeout`] module"] pub type PCH_TIMEOUT = crate::Reg; #[doc = "P-channel Timeout Threshold"] pub mod pch_timeout; -#[doc = "lp_timeout (rw) register accessor: LP Cell Control Timeout Threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lp_timeout`] +#[doc = "lp_timeout (rw) register accessor: LP Cell Control Timeout Threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_timeout`] module"] pub type LP_TIMEOUT = crate::Reg; #[doc = "LP Cell Control Timeout Threshold"] pub mod lp_timeout; -#[doc = "hard_turn_on_power_mode (rw) register accessor: Hardware Turn-On Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hard_turn_on_power_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hard_turn_on_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hard_turn_on_power_mode`] +#[doc = "hard_turn_on_power_mode (rw) register accessor: Hardware Turn-On Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hard_turn_on_power_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hard_turn_on_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hard_turn_on_power_mode`] module"] pub type HARD_TURN_ON_POWER_MODE = crate::Reg; #[doc = "Hardware Turn-On Power Mode"] pub mod hard_turn_on_power_mode; -#[doc = "current_power_mode (rw) register accessor: Current Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`current_power_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`current_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`current_power_mode`] +#[doc = "current_power_mode (rw) register accessor: Current Power Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`current_power_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`current_power_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@current_power_mode`] module"] pub type CURRENT_POWER_MODE = crate::Reg; #[doc = "Current Power Mode"] pub mod current_power_mode; -#[doc = "current_seq_state (rw) register accessor: Current Sequence State\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`current_seq_state::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`current_seq_state::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`current_seq_state`] +#[doc = "current_seq_state (rw) register accessor: Current Sequence State\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`current_seq_state::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`current_seq_state::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@current_seq_state`] module"] pub type CURRENT_SEQ_STATE = crate::Reg; #[doc = "Current Sequence State"] pub mod current_seq_state; -#[doc = "event_status (rw) register accessor: PMU Event Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`event_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`event_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`event_status`] +#[doc = "event_status (rw) register accessor: PMU Event Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`event_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`event_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@event_status`] module"] pub type EVENT_STATUS = crate::Reg; #[doc = "PMU Event Status"] pub mod event_status; -#[doc = "int_status (rw) register accessor: PMU Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`int_status`] +#[doc = "int_status (rw) register accessor: PMU Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_status`] module"] pub type INT_STATUS = crate::Reg; #[doc = "PMU Interrupt Status"] pub mod int_status; -#[doc = "hw_event_crd (rw) register accessor: Hardware Event Record\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_event_crd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hw_event_crd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hw_event_crd`] +#[doc = "hw_event_crd (rw) register accessor: Hardware Event Record\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_event_crd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hw_event_crd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_event_crd`] module"] pub type HW_EVENT_CRD = crate::Reg; #[doc = "Hardware Event Record"] pub mod hw_event_crd; -#[doc = "encourage_type_crd (rw) register accessor: Hardware Event Type Record\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`encourage_type_crd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`encourage_type_crd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`encourage_type_crd`] +#[doc = "encourage_type_crd (rw) register accessor: Hardware Event Type Record\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`encourage_type_crd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`encourage_type_crd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@encourage_type_crd`] module"] pub type ENCOURAGE_TYPE_CRD = crate::Reg; #[doc = "Hardware Event Type Record"] pub mod encourage_type_crd; -#[doc = "pch_active (rw) register accessor: P-channel PACTIVE Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_active::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_active::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pch_active`] +#[doc = "pch_active (rw) register accessor: P-channel PACTIVE Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pch_active::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pch_active::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pch_active`] module"] pub type PCH_ACTIVE = crate::Reg; #[doc = "P-channel PACTIVE Status"] diff --git a/jh7110-vf2-13b-pac/src/pmu/current_power_mode.rs b/jh7110-vf2-13b-pac/src/pmu/current_power_mode.rs index 7d70502..fa5dad7 100644 --- a/jh7110-vf2-13b-pac/src/pmu/current_power_mode.rs +++ b/jh7110-vf2-13b-pac/src/pmu/current_power_mode.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `systop_power_mode` reader - SYSTOP turn-on power mode."] pub type SYSTOP_POWER_MODE_R = crate::BitReader; #[doc = "Field `systop_power_mode` writer - SYSTOP turn-on power mode."] -pub type SYSTOP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SYSTOP_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `cpu_power_mode` reader - CPU turn-on power mode."] pub type CPU_POWER_MODE_R = crate::BitReader; #[doc = "Field `cpu_power_mode` writer - CPU turn-on power mode."] -pub type CPU_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CPU_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gpua_power_mode` reader - GPUA turn-on power mode."] pub type GPUA_POWER_MODE_R = crate::BitReader; #[doc = "Field `gpua_power_mode` writer - GPUA turn-on power mode."] -pub type GPUA_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GPUA_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `vdec_power_mode` reader - VDEC turn-on power mode."] pub type VDEC_POWER_MODE_R = crate::BitReader; #[doc = "Field `vdec_power_mode` writer - VDEC turn-on power mode."] -pub type VDEC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VDEC_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `vout_power_mode` reader - VOUT turn-on power mode."] pub type VOUT_POWER_MODE_R = crate::BitReader; #[doc = "Field `vout_power_mode` writer - VOUT turn-on power mode."] -pub type VOUT_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VOUT_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `isp_power_mode` reader - ISP turn-on power mode."] pub type ISP_POWER_MODE_R = crate::BitReader; #[doc = "Field `isp_power_mode` writer - ISP turn-on power mode."] -pub type ISP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ISP_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `venc_power_mode` reader - VENC turn-on power mode."] pub type VENC_POWER_MODE_R = crate::BitReader; #[doc = "Field `venc_power_mode` writer - VENC turn-on power mode."] -pub type VENC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VENC_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - SYSTOP turn-on power mode."] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - SYSTOP turn-on power mode."] #[inline(always)] #[must_use] - pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { - SYSTOP_POWER_MODE_W::new(self) + pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { + SYSTOP_POWER_MODE_W::new(self, 0) } #[doc = "Bit 1 - CPU turn-on power mode."] #[inline(always)] #[must_use] - pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { - CPU_POWER_MODE_W::new(self) + pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { + CPU_POWER_MODE_W::new(self, 1) } #[doc = "Bit 2 - GPUA turn-on power mode."] #[inline(always)] #[must_use] - pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { - GPUA_POWER_MODE_W::new(self) + pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { + GPUA_POWER_MODE_W::new(self, 2) } #[doc = "Bit 3 - VDEC turn-on power mode."] #[inline(always)] #[must_use] - pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { - VDEC_POWER_MODE_W::new(self) + pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { + VDEC_POWER_MODE_W::new(self, 3) } #[doc = "Bit 4 - VOUT turn-on power mode."] #[inline(always)] #[must_use] - pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { - VOUT_POWER_MODE_W::new(self) + pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { + VOUT_POWER_MODE_W::new(self, 4) } #[doc = "Bit 5 - ISP turn-on power mode."] #[inline(always)] #[must_use] - pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { - ISP_POWER_MODE_W::new(self) + pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { + ISP_POWER_MODE_W::new(self, 5) } #[doc = "Bit 6 - VENC turn-on power mode."] #[inline(always)] #[must_use] - pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { - VENC_POWER_MODE_W::new(self) + pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { + VENC_POWER_MODE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/current_seq_state.rs b/jh7110-vf2-13b-pac/src/pmu/current_seq_state.rs index de5ac6c..4534c7b 100644 --- a/jh7110-vf2-13b-pac/src/pmu/current_seq_state.rs +++ b/jh7110-vf2-13b-pac/src/pmu/current_seq_state.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/encourage_type_crd.rs b/jh7110-vf2-13b-pac/src/pmu/encourage_type_crd.rs index 1aff2c2..d32a1c9 100644 --- a/jh7110-vf2-13b-pac/src/pmu/encourage_type_crd.rs +++ b/jh7110-vf2-13b-pac/src/pmu/encourage_type_crd.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/event_status.rs b/jh7110-vf2-13b-pac/src/pmu/event_status.rs index 8fdbd4c..c34a9b6 100644 --- a/jh7110-vf2-13b-pac/src/pmu/event_status.rs +++ b/jh7110-vf2-13b-pac/src/pmu/event_status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/hard_event_turn_on_mask.rs b/jh7110-vf2-13b-pac/src/pmu/hard_event_turn_on_mask.rs index 1ddfc49..21850d6 100644 --- a/jh7110-vf2-13b-pac/src/pmu/hard_event_turn_on_mask.rs +++ b/jh7110-vf2-13b-pac/src/pmu/hard_event_turn_on_mask.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `hard_event_0_on_mask` reader - RTC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] pub type HARD_EVENT_0_ON_MASK_R = crate::BitReader; #[doc = "Field `hard_event_0_on_mask` writer - RTC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] -pub type HARD_EVENT_0_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HARD_EVENT_0_ON_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `hard_event_1_on_mask` reader - GMAC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] pub type HARD_EVENT_1_ON_MASK_R = crate::BitReader; #[doc = "Field `hard_event_1_on_mask` writer - GMAC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] -pub type HARD_EVENT_1_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HARD_EVENT_1_ON_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `hard_event_2_on_mask` reader - RFU, 1: mask hardware event, 0: enable hardware event"] pub type HARD_EVENT_2_ON_MASK_R = crate::BitReader; #[doc = "Field `hard_event_2_on_mask` writer - RFU, 1: mask hardware event, 0: enable hardware event"] -pub type HARD_EVENT_2_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HARD_EVENT_2_ON_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `hard_event_3_on_mask` reader - RGPIO0 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] pub type HARD_EVENT_3_ON_MASK_R = crate::BitReader; #[doc = "Field `hard_event_3_on_mask` writer - RGPIO0 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] -pub type HARD_EVENT_3_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HARD_EVENT_3_ON_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `hard_event_4_on_mask` reader - RGPIO1 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] pub type HARD_EVENT_4_ON_MASK_R = crate::BitReader; #[doc = "Field `hard_event_4_on_mask` writer - RGPIO1 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] -pub type HARD_EVENT_4_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HARD_EVENT_4_ON_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `hard_event_5_on_mask` reader - RGPIO2 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] pub type HARD_EVENT_5_ON_MASK_R = crate::BitReader; #[doc = "Field `hard_event_5_on_mask` writer - RGPIO2 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] -pub type HARD_EVENT_5_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HARD_EVENT_5_ON_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `hard_event_6_on_mask` reader - RGPIO3 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] pub type HARD_EVENT_6_ON_MASK_R = crate::BitReader; #[doc = "Field `hard_event_6_on_mask` writer - RGPIO3 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] -pub type HARD_EVENT_6_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HARD_EVENT_6_ON_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `hard_event_7_on_mask` reader - GPU event, 1: mask hardware event, 0: enable hardware event"] pub type HARD_EVENT_7_ON_MASK_R = crate::BitReader; #[doc = "Field `hard_event_7_on_mask` writer - GPU event, 1: mask hardware event, 0: enable hardware event"] -pub type HARD_EVENT_7_ON_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HARD_EVENT_7_ON_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RTC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] @@ -80,68 +80,56 @@ impl W { #[doc = "Bit 0 - RTC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] #[must_use] - pub fn hard_event_0_on_mask( - &mut self, - ) -> HARD_EVENT_0_ON_MASK_W { - HARD_EVENT_0_ON_MASK_W::new(self) + pub fn hard_event_0_on_mask(&mut self) -> HARD_EVENT_0_ON_MASK_W { + HARD_EVENT_0_ON_MASK_W::new(self, 0) } #[doc = "Bit 1 - GMAC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] #[must_use] - pub fn hard_event_1_on_mask( - &mut self, - ) -> HARD_EVENT_1_ON_MASK_W { - HARD_EVENT_1_ON_MASK_W::new(self) + pub fn hard_event_1_on_mask(&mut self) -> HARD_EVENT_1_ON_MASK_W { + HARD_EVENT_1_ON_MASK_W::new(self, 1) } #[doc = "Bit 2 - RFU, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] #[must_use] - pub fn hard_event_2_on_mask( - &mut self, - ) -> HARD_EVENT_2_ON_MASK_W { - HARD_EVENT_2_ON_MASK_W::new(self) + pub fn hard_event_2_on_mask(&mut self) -> HARD_EVENT_2_ON_MASK_W { + HARD_EVENT_2_ON_MASK_W::new(self, 2) } #[doc = "Bit 3 - RGPIO0 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] #[must_use] - pub fn hard_event_3_on_mask( - &mut self, - ) -> HARD_EVENT_3_ON_MASK_W { - HARD_EVENT_3_ON_MASK_W::new(self) + pub fn hard_event_3_on_mask(&mut self) -> HARD_EVENT_3_ON_MASK_W { + HARD_EVENT_3_ON_MASK_W::new(self, 3) } #[doc = "Bit 4 - RGPIO1 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] #[must_use] - pub fn hard_event_4_on_mask( - &mut self, - ) -> HARD_EVENT_4_ON_MASK_W { - HARD_EVENT_4_ON_MASK_W::new(self) + pub fn hard_event_4_on_mask(&mut self) -> HARD_EVENT_4_ON_MASK_W { + HARD_EVENT_4_ON_MASK_W::new(self, 4) } #[doc = "Bit 5 - RGPIO2 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] #[must_use] - pub fn hard_event_5_on_mask( - &mut self, - ) -> HARD_EVENT_5_ON_MASK_W { - HARD_EVENT_5_ON_MASK_W::new(self) + pub fn hard_event_5_on_mask(&mut self) -> HARD_EVENT_5_ON_MASK_W { + HARD_EVENT_5_ON_MASK_W::new(self, 5) } #[doc = "Bit 6 - RGPIO3 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] #[must_use] - pub fn hard_event_6_on_mask( - &mut self, - ) -> HARD_EVENT_6_ON_MASK_W { - HARD_EVENT_6_ON_MASK_W::new(self) + pub fn hard_event_6_on_mask(&mut self) -> HARD_EVENT_6_ON_MASK_W { + HARD_EVENT_6_ON_MASK_W::new(self, 6) } #[doc = "Bit 7 - GPU event, 1: mask hardware event, 0: enable hardware event"] #[inline(always)] #[must_use] - pub fn hard_event_7_on_mask( - &mut self, - ) -> HARD_EVENT_7_ON_MASK_W { - HARD_EVENT_7_ON_MASK_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn hard_event_7_on_mask(&mut self) -> HARD_EVENT_7_ON_MASK_W { + HARD_EVENT_7_ON_MASK_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/hard_turn_on_power_mode.rs b/jh7110-vf2-13b-pac/src/pmu/hard_turn_on_power_mode.rs index e0b0efb..a13aa48 100644 --- a/jh7110-vf2-13b-pac/src/pmu/hard_turn_on_power_mode.rs +++ b/jh7110-vf2-13b-pac/src/pmu/hard_turn_on_power_mode.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `systop_power_mode` reader - SYSTOP turn-on power mode."] pub type SYSTOP_POWER_MODE_R = crate::BitReader; #[doc = "Field `systop_power_mode` writer - SYSTOP turn-on power mode."] -pub type SYSTOP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SYSTOP_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `cpu_power_mode` reader - CPU turn-on power mode."] pub type CPU_POWER_MODE_R = crate::BitReader; #[doc = "Field `cpu_power_mode` writer - CPU turn-on power mode."] -pub type CPU_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CPU_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gpua_power_mode` reader - GPUA turn-on power mode."] pub type GPUA_POWER_MODE_R = crate::BitReader; #[doc = "Field `gpua_power_mode` writer - GPUA turn-on power mode."] -pub type GPUA_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GPUA_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `vdec_power_mode` reader - VDEC turn-on power mode."] pub type VDEC_POWER_MODE_R = crate::BitReader; #[doc = "Field `vdec_power_mode` writer - VDEC turn-on power mode."] -pub type VDEC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VDEC_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `vout_power_mode` reader - VOUT turn-on power mode."] pub type VOUT_POWER_MODE_R = crate::BitReader; #[doc = "Field `vout_power_mode` writer - VOUT turn-on power mode."] -pub type VOUT_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VOUT_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `isp_power_mode` reader - ISP turn-on power mode."] pub type ISP_POWER_MODE_R = crate::BitReader; #[doc = "Field `isp_power_mode` writer - ISP turn-on power mode."] -pub type ISP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ISP_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `venc_power_mode` reader - VENC turn-on power mode."] pub type VENC_POWER_MODE_R = crate::BitReader; #[doc = "Field `venc_power_mode` writer - VENC turn-on power mode."] -pub type VENC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VENC_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - SYSTOP turn-on power mode."] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - SYSTOP turn-on power mode."] #[inline(always)] #[must_use] - pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { - SYSTOP_POWER_MODE_W::new(self) + pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { + SYSTOP_POWER_MODE_W::new(self, 0) } #[doc = "Bit 1 - CPU turn-on power mode."] #[inline(always)] #[must_use] - pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { - CPU_POWER_MODE_W::new(self) + pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { + CPU_POWER_MODE_W::new(self, 1) } #[doc = "Bit 2 - GPUA turn-on power mode."] #[inline(always)] #[must_use] - pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { - GPUA_POWER_MODE_W::new(self) + pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { + GPUA_POWER_MODE_W::new(self, 2) } #[doc = "Bit 3 - VDEC turn-on power mode."] #[inline(always)] #[must_use] - pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { - VDEC_POWER_MODE_W::new(self) + pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { + VDEC_POWER_MODE_W::new(self, 3) } #[doc = "Bit 4 - VOUT turn-on power mode."] #[inline(always)] #[must_use] - pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { - VOUT_POWER_MODE_W::new(self) + pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { + VOUT_POWER_MODE_W::new(self, 4) } #[doc = "Bit 5 - ISP turn-on power mode."] #[inline(always)] #[must_use] - pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { - ISP_POWER_MODE_W::new(self) + pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { + ISP_POWER_MODE_W::new(self, 5) } #[doc = "Bit 6 - VENC turn-on power mode."] #[inline(always)] #[must_use] - pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { - VENC_POWER_MODE_W::new(self) + pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { + VENC_POWER_MODE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/hw_event_crd.rs b/jh7110-vf2-13b-pac/src/pmu/hw_event_crd.rs index bdd1461..c2905d2 100644 --- a/jh7110-vf2-13b-pac/src/pmu/hw_event_crd.rs +++ b/jh7110-vf2-13b-pac/src/pmu/hw_event_crd.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/int_status.rs b/jh7110-vf2-13b-pac/src/pmu/int_status.rs index 841a9e8..4e918b9 100644 --- a/jh7110-vf2-13b-pac/src/pmu/int_status.rs +++ b/jh7110-vf2-13b-pac/src/pmu/int_status.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/lp_timeout.rs b/jh7110-vf2-13b-pac/src/pmu/lp_timeout.rs index 8fdf4f0..57a8810 100644 --- a/jh7110-vf2-13b-pac/src/pmu/lp_timeout.rs +++ b/jh7110-vf2-13b-pac/src/pmu/lp_timeout.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lp_timeout` reader - LP Cell Control signal waiting carries acknowledge timeout."] pub type LP_TIMEOUT_R = crate::FieldReader; #[doc = "Field `lp_timeout` writer - LP Cell Control signal waiting carries acknowledge timeout."] -pub type LP_TIMEOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LP_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - LP Cell Control signal waiting carries acknowledge timeout."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - LP Cell Control signal waiting carries acknowledge timeout."] #[inline(always)] #[must_use] - pub fn lp_timeout(&mut self) -> LP_TIMEOUT_W { - LP_TIMEOUT_W::new(self) + pub fn lp_timeout(&mut self) -> LP_TIMEOUT_W { + LP_TIMEOUT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/pch_active.rs b/jh7110-vf2-13b-pac/src/pmu/pch_active.rs index c0d4dc2..1ca0ff9 100644 --- a/jh7110-vf2-13b-pac/src/pmu/pch_active.rs +++ b/jh7110-vf2-13b-pac/src/pmu/pch_active.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/pch_bypass.rs b/jh7110-vf2-13b-pac/src/pmu/pch_bypass.rs index e07a79f..7978dba 100644 --- a/jh7110-vf2-13b-pac/src/pmu/pch_bypass.rs +++ b/jh7110-vf2-13b-pac/src/pmu/pch_bypass.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `pch_bypass` reader - Bypass P-channel. 0: enable p-channel, 1: bypass p-channel"] pub type PCH_BYPASS_R = crate::BitReader; #[doc = "Field `pch_bypass` writer - Bypass P-channel. 0: enable p-channel, 1: bypass p-channel"] -pub type PCH_BYPASS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PCH_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Bypass P-channel. 0: enable p-channel, 1: bypass p-channel"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Bypass P-channel. 0: enable p-channel, 1: bypass p-channel"] #[inline(always)] #[must_use] - pub fn pch_bypass(&mut self) -> PCH_BYPASS_W { - PCH_BYPASS_W::new(self) + pub fn pch_bypass(&mut self) -> PCH_BYPASS_W { + PCH_BYPASS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/pch_pstate.rs b/jh7110-vf2-13b-pac/src/pmu/pch_pstate.rs index 2b2f0a9..e311176 100644 --- a/jh7110-vf2-13b-pac/src/pmu/pch_pstate.rs +++ b/jh7110-vf2-13b-pac/src/pmu/pch_pstate.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `pch_pstate` reader - P-channel state set"] pub type PCH_PSTATE_R = crate::FieldReader; #[doc = "Field `pch_pstate` writer - P-channel state set"] -pub type PCH_PSTATE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PCH_PSTATE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; impl R { #[doc = "Bits 0:4 - P-channel state set"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:4 - P-channel state set"] #[inline(always)] #[must_use] - pub fn pch_pstate(&mut self) -> PCH_PSTATE_W { - PCH_PSTATE_W::new(self) + pub fn pch_pstate(&mut self) -> PCH_PSTATE_W { + PCH_PSTATE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/pch_timeout.rs b/jh7110-vf2-13b-pac/src/pmu/pch_timeout.rs index 4ae8e16..54098c5 100644 --- a/jh7110-vf2-13b-pac/src/pmu/pch_timeout.rs +++ b/jh7110-vf2-13b-pac/src/pmu/pch_timeout.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `pch_timeout` reader - P-channel waiting device acknowledge timeout."] pub type PCH_TIMEOUT_R = crate::FieldReader; #[doc = "Field `pch_timeout` writer - P-channel waiting device acknowledge timeout."] -pub type PCH_TIMEOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type PCH_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - P-channel waiting device acknowledge timeout."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - P-channel waiting device acknowledge timeout."] #[inline(always)] #[must_use] - pub fn pch_timeout(&mut self) -> PCH_TIMEOUT_W { - PCH_TIMEOUT_W::new(self) + pub fn pch_timeout(&mut self) -> PCH_TIMEOUT_W { + PCH_TIMEOUT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/pdc0.rs b/jh7110-vf2-13b-pac/src/pmu/pdc0.rs index 49fa8c4..dfdf300 100644 --- a/jh7110-vf2-13b-pac/src/pmu/pdc0.rs +++ b/jh7110-vf2-13b-pac/src/pmu/pdc0.rs @@ -5,27 +5,27 @@ pub type W = crate::W; #[doc = "Field `pd0_off_cas` reader - Power domain 0 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD0_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd0_off_cas` writer - Power domain 0 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD0_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD0_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd0_on_cas` reader - Power domain 0 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD0_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd0_on_cas` writer - Power domain 0 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD0_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD0_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd1_off_cas` reader - Power domain 1 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD1_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd1_off_cas` writer - Power domain 1 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD1_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD1_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd1_on_cas` reader - Power domain 1 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD1_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd1_on_cas` writer - Power domain 1 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD1_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD1_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd2_off_cas` reader - Power domain 2 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD2_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd2_off_cas` writer - Power domain 2 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD2_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD2_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd2_on_cas` reader - Power domain 2 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD2_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd2_on_cas` writer - Power domain 2 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD2_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD2_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; impl R { #[doc = "Bits 0:4 - Power domain 0 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] @@ -62,40 +62,44 @@ impl W { #[doc = "Bits 0:4 - Power domain 0 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd0_off_cas(&mut self) -> PD0_OFF_CAS_W { - PD0_OFF_CAS_W::new(self) + pub fn pd0_off_cas(&mut self) -> PD0_OFF_CAS_W { + PD0_OFF_CAS_W::new(self, 0) } #[doc = "Bits 5:9 - Power domain 0 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd0_on_cas(&mut self) -> PD0_ON_CAS_W { - PD0_ON_CAS_W::new(self) + pub fn pd0_on_cas(&mut self) -> PD0_ON_CAS_W { + PD0_ON_CAS_W::new(self, 5) } #[doc = "Bits 10:14 - Power domain 1 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd1_off_cas(&mut self) -> PD1_OFF_CAS_W { - PD1_OFF_CAS_W::new(self) + pub fn pd1_off_cas(&mut self) -> PD1_OFF_CAS_W { + PD1_OFF_CAS_W::new(self, 10) } #[doc = "Bits 15:19 - Power domain 1 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd1_on_cas(&mut self) -> PD1_ON_CAS_W { - PD1_ON_CAS_W::new(self) + pub fn pd1_on_cas(&mut self) -> PD1_ON_CAS_W { + PD1_ON_CAS_W::new(self, 15) } #[doc = "Bits 20:24 - Power domain 2 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd2_off_cas(&mut self) -> PD2_OFF_CAS_W { - PD2_OFF_CAS_W::new(self) + pub fn pd2_off_cas(&mut self) -> PD2_OFF_CAS_W { + PD2_OFF_CAS_W::new(self, 20) } #[doc = "Bits 25:29 - Power domain 2 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd2_on_cas(&mut self) -> PD2_ON_CAS_W { - PD2_ON_CAS_W::new(self) + pub fn pd2_on_cas(&mut self) -> PD2_ON_CAS_W { + PD2_ON_CAS_W::new(self, 25) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/pdc1.rs b/jh7110-vf2-13b-pac/src/pmu/pdc1.rs index 5d0521e..ed69421 100644 --- a/jh7110-vf2-13b-pac/src/pmu/pdc1.rs +++ b/jh7110-vf2-13b-pac/src/pmu/pdc1.rs @@ -5,27 +5,27 @@ pub type W = crate::W; #[doc = "Field `pd3_off_cas` reader - Power domain 3 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD3_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd3_off_cas` writer - Power domain 3 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD3_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD3_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd3_on_cas` reader - Power domain 3 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD3_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd3_on_cas` writer - Power domain 3 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD3_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD3_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd4_off_cas` reader - Power domain 4 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD4_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd4_off_cas` writer - Power domain 4 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD4_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD4_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd4_on_cas` reader - Power domain 4 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD4_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd4_on_cas` writer - Power domain 4 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD4_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD4_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd5_off_cas` reader - Power domain 5 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD5_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd5_off_cas` writer - Power domain 5 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD5_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD5_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd5_on_cas` reader - Power domain 5 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD5_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd5_on_cas` writer - Power domain 5 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD5_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD5_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; impl R { #[doc = "Bits 0:4 - Power domain 3 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] @@ -62,40 +62,44 @@ impl W { #[doc = "Bits 0:4 - Power domain 3 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd3_off_cas(&mut self) -> PD3_OFF_CAS_W { - PD3_OFF_CAS_W::new(self) + pub fn pd3_off_cas(&mut self) -> PD3_OFF_CAS_W { + PD3_OFF_CAS_W::new(self, 0) } #[doc = "Bits 5:9 - Power domain 3 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd3_on_cas(&mut self) -> PD3_ON_CAS_W { - PD3_ON_CAS_W::new(self) + pub fn pd3_on_cas(&mut self) -> PD3_ON_CAS_W { + PD3_ON_CAS_W::new(self, 5) } #[doc = "Bits 10:14 - Power domain 4 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd4_off_cas(&mut self) -> PD4_OFF_CAS_W { - PD4_OFF_CAS_W::new(self) + pub fn pd4_off_cas(&mut self) -> PD4_OFF_CAS_W { + PD4_OFF_CAS_W::new(self, 10) } #[doc = "Bits 15:19 - Power domain 4 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd4_on_cas(&mut self) -> PD4_ON_CAS_W { - PD4_ON_CAS_W::new(self) + pub fn pd4_on_cas(&mut self) -> PD4_ON_CAS_W { + PD4_ON_CAS_W::new(self, 15) } #[doc = "Bits 20:24 - Power domain 5 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd5_off_cas(&mut self) -> PD5_OFF_CAS_W { - PD5_OFF_CAS_W::new(self) + pub fn pd5_off_cas(&mut self) -> PD5_OFF_CAS_W { + PD5_OFF_CAS_W::new(self, 20) } #[doc = "Bits 25:29 - Power domain 5 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd5_on_cas(&mut self) -> PD5_ON_CAS_W { - PD5_ON_CAS_W::new(self) + pub fn pd5_on_cas(&mut self) -> PD5_ON_CAS_W { + PD5_ON_CAS_W::new(self, 25) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/pdc2.rs b/jh7110-vf2-13b-pac/src/pmu/pdc2.rs index 7624c7d..956c250 100644 --- a/jh7110-vf2-13b-pac/src/pmu/pdc2.rs +++ b/jh7110-vf2-13b-pac/src/pmu/pdc2.rs @@ -5,27 +5,27 @@ pub type W = crate::W; #[doc = "Field `pd6_off_cas` reader - Power domain 6 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD6_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd6_off_cas` writer - Power domain 6 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD6_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD6_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd6_on_cas` reader - Power domain 6 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD6_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd6_on_cas` writer - Power domain 6 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD6_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD6_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd7_off_cas` reader - Power domain 7 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD7_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd7_off_cas` writer - Power domain 7 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD7_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD7_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd7_on_cas` reader - Power domain 7 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD7_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd7_on_cas` writer - Power domain 7 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD7_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD7_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd8_off_cas` reader - Power domain 8 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD8_OFF_CAS_R = crate::FieldReader; #[doc = "Field `pd8_off_cas` writer - Power domain 8 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD8_OFF_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD8_OFF_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `pd8_on_cas` reader - Power domain 8 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] pub type PD8_ON_CAS_R = crate::FieldReader; #[doc = "Field `pd8_on_cas` writer - Power domain 8 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] -pub type PD8_ON_CAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type PD8_ON_CAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; impl R { #[doc = "Bits 0:4 - Power domain 6 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] @@ -62,40 +62,44 @@ impl W { #[doc = "Bits 0:4 - Power domain 6 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd6_off_cas(&mut self) -> PD6_OFF_CAS_W { - PD6_OFF_CAS_W::new(self) + pub fn pd6_off_cas(&mut self) -> PD6_OFF_CAS_W { + PD6_OFF_CAS_W::new(self, 0) } #[doc = "Bits 5:9 - Power domain 6 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd6_on_cas(&mut self) -> PD6_ON_CAS_W { - PD6_ON_CAS_W::new(self) + pub fn pd6_on_cas(&mut self) -> PD6_ON_CAS_W { + PD6_ON_CAS_W::new(self, 5) } #[doc = "Bits 10:14 - Power domain 7 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd7_off_cas(&mut self) -> PD7_OFF_CAS_W { - PD7_OFF_CAS_W::new(self) + pub fn pd7_off_cas(&mut self) -> PD7_OFF_CAS_W { + PD7_OFF_CAS_W::new(self, 10) } #[doc = "Bits 15:19 - Power domain 7 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd7_on_cas(&mut self) -> PD7_ON_CAS_W { - PD7_ON_CAS_W::new(self) + pub fn pd7_on_cas(&mut self) -> PD7_ON_CAS_W { + PD7_ON_CAS_W::new(self, 15) } #[doc = "Bits 20:24 - Power domain 8 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd8_off_cas(&mut self) -> PD8_OFF_CAS_W { - PD8_OFF_CAS_W::new(self) + pub fn pd8_off_cas(&mut self) -> PD8_OFF_CAS_W { + PD8_OFF_CAS_W::new(self, 20) } #[doc = "Bits 25:29 - Power domain 8 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid."] #[inline(always)] #[must_use] - pub fn pd8_on_cas(&mut self) -> PD8_ON_CAS_W { - PD8_ON_CAS_W::new(self) + pub fn pd8_on_cas(&mut self) -> PD8_ON_CAS_W { + PD8_ON_CAS_W::new(self, 25) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/soft_turn_off_power_mode.rs b/jh7110-vf2-13b-pac/src/pmu/soft_turn_off_power_mode.rs index 6c09db0..4954cfe 100644 --- a/jh7110-vf2-13b-pac/src/pmu/soft_turn_off_power_mode.rs +++ b/jh7110-vf2-13b-pac/src/pmu/soft_turn_off_power_mode.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `systop_power_mode` reader - SYSTOP turn-off power mode."] pub type SYSTOP_POWER_MODE_R = crate::BitReader; #[doc = "Field `systop_power_mode` writer - SYSTOP turn-off power mode."] -pub type SYSTOP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SYSTOP_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `cpu_power_mode` reader - CPU turn-off power mode."] pub type CPU_POWER_MODE_R = crate::BitReader; #[doc = "Field `cpu_power_mode` writer - CPU turn-off power mode."] -pub type CPU_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CPU_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gpua_power_mode` reader - GPUA turn-off power mode."] pub type GPUA_POWER_MODE_R = crate::BitReader; #[doc = "Field `gpua_power_mode` writer - GPUA turn-off power mode."] -pub type GPUA_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GPUA_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `vdec_power_mode` reader - VDEC turn-off power mode."] pub type VDEC_POWER_MODE_R = crate::BitReader; #[doc = "Field `vdec_power_mode` writer - VDEC turn-off power mode."] -pub type VDEC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VDEC_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `vout_power_mode` reader - VOUT turn-off power mode."] pub type VOUT_POWER_MODE_R = crate::BitReader; #[doc = "Field `vout_power_mode` writer - VOUT turn-off power mode."] -pub type VOUT_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VOUT_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `isp_power_mode` reader - ISP turn-off power mode."] pub type ISP_POWER_MODE_R = crate::BitReader; #[doc = "Field `isp_power_mode` writer - ISP turn-off power mode."] -pub type ISP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ISP_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `venc_power_mode` reader - VENC turn-off power mode."] pub type VENC_POWER_MODE_R = crate::BitReader; #[doc = "Field `venc_power_mode` writer - VENC turn-off power mode."] -pub type VENC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VENC_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - SYSTOP turn-off power mode."] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - SYSTOP turn-off power mode."] #[inline(always)] #[must_use] - pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { - SYSTOP_POWER_MODE_W::new(self) + pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { + SYSTOP_POWER_MODE_W::new(self, 0) } #[doc = "Bit 1 - CPU turn-off power mode."] #[inline(always)] #[must_use] - pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { - CPU_POWER_MODE_W::new(self) + pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { + CPU_POWER_MODE_W::new(self, 1) } #[doc = "Bit 2 - GPUA turn-off power mode."] #[inline(always)] #[must_use] - pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { - GPUA_POWER_MODE_W::new(self) + pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { + GPUA_POWER_MODE_W::new(self, 2) } #[doc = "Bit 3 - VDEC turn-off power mode."] #[inline(always)] #[must_use] - pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { - VDEC_POWER_MODE_W::new(self) + pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { + VDEC_POWER_MODE_W::new(self, 3) } #[doc = "Bit 4 - VOUT turn-off power mode."] #[inline(always)] #[must_use] - pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { - VOUT_POWER_MODE_W::new(self) + pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { + VOUT_POWER_MODE_W::new(self, 4) } #[doc = "Bit 5 - ISP turn-off power mode."] #[inline(always)] #[must_use] - pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { - ISP_POWER_MODE_W::new(self) + pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { + ISP_POWER_MODE_W::new(self, 5) } #[doc = "Bit 6 - VENC turn-off power mode."] #[inline(always)] #[must_use] - pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { - VENC_POWER_MODE_W::new(self) + pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { + VENC_POWER_MODE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/soft_turn_on_power_mode.rs b/jh7110-vf2-13b-pac/src/pmu/soft_turn_on_power_mode.rs index d587985..1a9ffe2 100644 --- a/jh7110-vf2-13b-pac/src/pmu/soft_turn_on_power_mode.rs +++ b/jh7110-vf2-13b-pac/src/pmu/soft_turn_on_power_mode.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `systop_power_mode` reader - SYSTOP turn-on power mode."] pub type SYSTOP_POWER_MODE_R = crate::BitReader; #[doc = "Field `systop_power_mode` writer - SYSTOP turn-on power mode."] -pub type SYSTOP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SYSTOP_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `cpu_power_mode` reader - CPU turn-on power mode."] pub type CPU_POWER_MODE_R = crate::BitReader; #[doc = "Field `cpu_power_mode` writer - CPU turn-on power mode."] -pub type CPU_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CPU_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gpua_power_mode` reader - GPUA turn-on power mode."] pub type GPUA_POWER_MODE_R = crate::BitReader; #[doc = "Field `gpua_power_mode` writer - GPUA turn-on power mode."] -pub type GPUA_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GPUA_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `vdec_power_mode` reader - VDEC turn-on power mode."] pub type VDEC_POWER_MODE_R = crate::BitReader; #[doc = "Field `vdec_power_mode` writer - VDEC turn-on power mode."] -pub type VDEC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VDEC_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `vout_power_mode` reader - VOUT turn-on power mode."] pub type VOUT_POWER_MODE_R = crate::BitReader; #[doc = "Field `vout_power_mode` writer - VOUT turn-on power mode."] -pub type VOUT_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VOUT_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `isp_power_mode` reader - ISP turn-on power mode."] pub type ISP_POWER_MODE_R = crate::BitReader; #[doc = "Field `isp_power_mode` writer - ISP turn-on power mode."] -pub type ISP_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ISP_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `venc_power_mode` reader - VENC turn-on power mode."] pub type VENC_POWER_MODE_R = crate::BitReader; #[doc = "Field `venc_power_mode` writer - VENC turn-on power mode."] -pub type VENC_POWER_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type VENC_POWER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - SYSTOP turn-on power mode."] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - SYSTOP turn-on power mode."] #[inline(always)] #[must_use] - pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { - SYSTOP_POWER_MODE_W::new(self) + pub fn systop_power_mode(&mut self) -> SYSTOP_POWER_MODE_W { + SYSTOP_POWER_MODE_W::new(self, 0) } #[doc = "Bit 1 - CPU turn-on power mode."] #[inline(always)] #[must_use] - pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { - CPU_POWER_MODE_W::new(self) + pub fn cpu_power_mode(&mut self) -> CPU_POWER_MODE_W { + CPU_POWER_MODE_W::new(self, 1) } #[doc = "Bit 2 - GPUA turn-on power mode."] #[inline(always)] #[must_use] - pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { - GPUA_POWER_MODE_W::new(self) + pub fn gpua_power_mode(&mut self) -> GPUA_POWER_MODE_W { + GPUA_POWER_MODE_W::new(self, 2) } #[doc = "Bit 3 - VDEC turn-on power mode."] #[inline(always)] #[must_use] - pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { - VDEC_POWER_MODE_W::new(self) + pub fn vdec_power_mode(&mut self) -> VDEC_POWER_MODE_W { + VDEC_POWER_MODE_W::new(self, 3) } #[doc = "Bit 4 - VOUT turn-on power mode."] #[inline(always)] #[must_use] - pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { - VOUT_POWER_MODE_W::new(self) + pub fn vout_power_mode(&mut self) -> VOUT_POWER_MODE_W { + VOUT_POWER_MODE_W::new(self, 4) } #[doc = "Bit 5 - ISP turn-on power mode."] #[inline(always)] #[must_use] - pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { - ISP_POWER_MODE_W::new(self) + pub fn isp_power_mode(&mut self) -> ISP_POWER_MODE_W { + ISP_POWER_MODE_W::new(self, 5) } #[doc = "Bit 6 - VENC turn-on power mode."] #[inline(always)] #[must_use] - pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { - VENC_POWER_MODE_W::new(self) + pub fn venc_power_mode(&mut self) -> VENC_POWER_MODE_W { + VENC_POWER_MODE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/sw_encourage.rs b/jh7110-vf2-13b-pac/src/pmu/sw_encourage.rs index d8b550e..3fceb35 100644 --- a/jh7110-vf2-13b-pac/src/pmu/sw_encourage.rs +++ b/jh7110-vf2-13b-pac/src/pmu/sw_encourage.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sw_encourage` reader - Software Encouragement"] pub type SW_ENCOURAGE_R = crate::FieldReader; #[doc = "Field `sw_encourage` writer - Software Encouragement"] -pub type SW_ENCOURAGE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SW_ENCOURAGE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Software Encouragement"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - Software Encouragement"] #[inline(always)] #[must_use] - pub fn sw_encourage(&mut self) -> SW_ENCOURAGE_W { - SW_ENCOURAGE_W::new(self) + pub fn sw_encourage(&mut self) -> SW_ENCOURAGE_W { + SW_ENCOURAGE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/tim.rs b/jh7110-vf2-13b-pac/src/pmu/tim.rs index 521a85c..d7760a3 100644 --- a/jh7110-vf2-13b-pac/src/pmu/tim.rs +++ b/jh7110-vf2-13b-pac/src/pmu/tim.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `seq_done_mask` reader - Mask the sequence complete event. 0: mask, 1: unmask"] pub type SEQ_DONE_MASK_R = crate::BitReader; #[doc = "Field `seq_done_mask` writer - Mask the sequence complete event. 0: mask, 1: unmask"] -pub type SEQ_DONE_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SEQ_DONE_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `hw_req_mask` reader - Mask the hardware encouragement request. 0: mask, 1: unmask"] pub type HW_REQ_MASK_R = crate::BitReader; #[doc = "Field `hw_req_mask` writer - Mask the hardware encouragement request. 0: mask, 1: unmask"] -pub type HW_REQ_MASK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HW_REQ_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sw_fail_mask` reader - Mask the software encouragement failure event. 0: mask, 1: unmask"] pub type SW_FAIL_MASK_R = crate::FieldReader; #[doc = "Field `sw_fail_mask` writer - Mask the software encouragement failure event. 0: mask, 1: unmask"] -pub type SW_FAIL_MASK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SW_FAIL_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `hw_fail_mask` reader - Mask the hardware encouragement failure event. 0: mask, 1: unmask"] pub type HW_FAIL_MASK_R = crate::FieldReader; #[doc = "Field `hw_fail_mask` writer - Mask the hardware encouragement failure event. 0: mask, 1: unmask"] -pub type HW_FAIL_MASK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type HW_FAIL_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pch_fail_mask` reader - Mask the P-channel encouragement failure event. 0: mask, 1: unmask"] pub type PCH_FAIL_MASK_R = crate::FieldReader; #[doc = "Field `pch_fail_mask` writer - Mask the P-channel encouragement failure event. 0: mask, 1: unmask"] -pub type PCH_FAIL_MASK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PCH_FAIL_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bit 0 - Mask the sequence complete event. 0: mask, 1: unmask"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - Mask the sequence complete event. 0: mask, 1: unmask"] #[inline(always)] #[must_use] - pub fn seq_done_mask(&mut self) -> SEQ_DONE_MASK_W { - SEQ_DONE_MASK_W::new(self) + pub fn seq_done_mask(&mut self) -> SEQ_DONE_MASK_W { + SEQ_DONE_MASK_W::new(self, 0) } #[doc = "Bit 1 - Mask the hardware encouragement request. 0: mask, 1: unmask"] #[inline(always)] #[must_use] - pub fn hw_req_mask(&mut self) -> HW_REQ_MASK_W { - HW_REQ_MASK_W::new(self) + pub fn hw_req_mask(&mut self) -> HW_REQ_MASK_W { + HW_REQ_MASK_W::new(self, 1) } #[doc = "Bits 2:3 - Mask the software encouragement failure event. 0: mask, 1: unmask"] #[inline(always)] #[must_use] - pub fn sw_fail_mask(&mut self) -> SW_FAIL_MASK_W { - SW_FAIL_MASK_W::new(self) + pub fn sw_fail_mask(&mut self) -> SW_FAIL_MASK_W { + SW_FAIL_MASK_W::new(self, 2) } #[doc = "Bits 4:5 - Mask the hardware encouragement failure event. 0: mask, 1: unmask"] #[inline(always)] #[must_use] - pub fn hw_fail_mask(&mut self) -> HW_FAIL_MASK_W { - HW_FAIL_MASK_W::new(self) + pub fn hw_fail_mask(&mut self) -> HW_FAIL_MASK_W { + HW_FAIL_MASK_W::new(self, 4) } #[doc = "Bits 6:8 - Mask the P-channel encouragement failure event. 0: mask, 1: unmask"] #[inline(always)] #[must_use] - pub fn pch_fail_mask(&mut self) -> PCH_FAIL_MASK_W { - PCH_FAIL_MASK_W::new(self) + pub fn pch_fail_mask(&mut self) -> PCH_FAIL_MASK_W { + PCH_FAIL_MASK_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/pmu/timeout_seq_thd.rs b/jh7110-vf2-13b-pac/src/pmu/timeout_seq_thd.rs index 09a763c..0ec9877 100644 --- a/jh7110-vf2-13b-pac/src/pmu/timeout_seq_thd.rs +++ b/jh7110-vf2-13b-pac/src/pmu/timeout_seq_thd.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `timeout_seq_thd` reader - Threshold Sequence Timeout"] pub type TIMEOUT_SEQ_THD_R = crate::FieldReader; #[doc = "Field `timeout_seq_thd` writer - Threshold Sequence Timeout"] -pub type TIMEOUT_SEQ_THD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type TIMEOUT_SEQ_THD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Threshold Sequence Timeout"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:15 - Threshold Sequence Timeout"] #[inline(always)] #[must_use] - pub fn timeout_seq_thd(&mut self) -> TIMEOUT_SEQ_THD_W { - TIMEOUT_SEQ_THD_W::new(self) + pub fn timeout_seq_thd(&mut self) -> TIMEOUT_SEQ_THD_W { + TIMEOUT_SEQ_THD_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi.rs b/jh7110-vf2-13b-pac/src/qspi.rs index 1ff3ba9..b17e09f 100644 --- a/jh7110-vf2-13b-pac/src/qspi.rs +++ b/jh7110-vf2-13b-pac/src/qspi.rs @@ -1,226 +1,352 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + config: CONFIG, + rd_instr: RD_INSTR, + wr_instr: WR_INSTR, + delay: DELAY, + read_capture: READ_CAPTURE, + size: SIZE, + sram_partition: SRAM_PARTITION, + indirect_trigger: INDIRECT_TRIGGER, + dma: DMA, + remap: REMAP, + mode_bit: MODE_BIT, + sdram_level: SDRAM_LEVEL, + _reserved12: [u8; 0x08], + wr_completion_ctrl: WR_COMPLETION_CTRL, + _reserved13: [u8; 0x04], + irq_status: IRQ_STATUS, + irq_mask: IRQ_MASK, + _reserved15: [u8; 0x18], + indirect_rd: INDIRECT_RD, + indirect_rd_watermark: INDIRECT_RD_WATERMARK, + indirect_rd_start_addr: INDIRECT_RD_START_ADDR, + indirect_rd_bytes: INDIRECT_RD_BYTES, + indirect_wr: INDIRECT_WR, + indirect_wr_watermark: INDIRECT_WR_WATERMARK, + indirect_wr_start_addr: INDIRECT_WR_START_ADDR, + indirect_wr_bytes: INDIRECT_WR_BYTES, + _reserved23: [u8; 0x10], + cmd_ctrl: CMD_CTRL, + cmd_address: CMD_ADDRESS, + _reserved25: [u8; 0x08], + cmd_read_at_lower: CMD_READ_AT_LOWER, + cmd_read_at_upper: CMD_READ_AT_UPPER, + cmd_write_at_lower: CMD_WRITE_AT_LOWER, + cmd_write_at_upper: CMD_WRITE_AT_UPPER, + polling_status: POLLING_STATUS, + _reserved30: [u8; 0x2c], + ext_lower: EXT_LOWER, +} +impl RegisterBlock { #[doc = "0x00 - Cadence QSPI Configuration"] - pub config: CONFIG, + #[inline(always)] + pub const fn config(&self) -> &CONFIG { + &self.config + } #[doc = "0x04 - Cadence QSPI Read Instruction"] - pub rd_instr: RD_INSTR, + #[inline(always)] + pub const fn rd_instr(&self) -> &RD_INSTR { + &self.rd_instr + } #[doc = "0x08 - Cadence QSPI Write Instruction"] - pub wr_instr: WR_INSTR, + #[inline(always)] + pub const fn wr_instr(&self) -> &WR_INSTR { + &self.wr_instr + } #[doc = "0x0c - Cadence QSPI Delay"] - pub delay: DELAY, + #[inline(always)] + pub const fn delay(&self) -> &DELAY { + &self.delay + } #[doc = "0x10 - Cadence QSPI Read Capture"] - pub read_capture: READ_CAPTURE, + #[inline(always)] + pub const fn read_capture(&self) -> &READ_CAPTURE { + &self.read_capture + } #[doc = "0x14 - Cadence QSPI Size Configuration"] - pub size: SIZE, + #[inline(always)] + pub const fn size(&self) -> &SIZE { + &self.size + } #[doc = "0x18 - Cadence QSPI SRAM Partition Size"] - pub sram_partition: SRAM_PARTITION, + #[inline(always)] + pub const fn sram_partition(&self) -> &SRAM_PARTITION { + &self.sram_partition + } #[doc = "0x1c - Cadence QSPI Indirect Trigger Address"] - pub indirect_trigger: INDIRECT_TRIGGER, + #[inline(always)] + pub const fn indirect_trigger(&self) -> &INDIRECT_TRIGGER { + &self.indirect_trigger + } #[doc = "0x20 - Cadence QSPI Direct Memory Access"] - pub dma: DMA, + #[inline(always)] + pub const fn dma(&self) -> &DMA { + &self.dma + } #[doc = "0x24 - Cadence QSPI Remap Address"] - pub remap: REMAP, + #[inline(always)] + pub const fn remap(&self) -> &REMAP { + &self.remap + } #[doc = "0x28 - Cadence QSPI Mode Bit(s)"] - pub mode_bit: MODE_BIT, + #[inline(always)] + pub const fn mode_bit(&self) -> &MODE_BIT { + &self.mode_bit + } #[doc = "0x2c - Cadence QSPI SDRAM Level"] - pub sdram_level: SDRAM_LEVEL, - _reserved12: [u8; 0x08], + #[inline(always)] + pub const fn sdram_level(&self) -> &SDRAM_LEVEL { + &self.sdram_level + } #[doc = "0x38 - Cadence QSPI Write Completion Control"] - pub wr_completion_ctrl: WR_COMPLETION_CTRL, - _reserved13: [u8; 0x04], + #[inline(always)] + pub const fn wr_completion_ctrl(&self) -> &WR_COMPLETION_CTRL { + &self.wr_completion_ctrl + } #[doc = "0x40 - Cadence QSPI IRQ Status"] - pub irq_status: IRQ_STATUS, + #[inline(always)] + pub const fn irq_status(&self) -> &IRQ_STATUS { + &self.irq_status + } #[doc = "0x44 - Cadence QSPI IRQ Mask"] - pub irq_mask: IRQ_MASK, - _reserved15: [u8; 0x18], + #[inline(always)] + pub const fn irq_mask(&self) -> &IRQ_MASK { + &self.irq_mask + } #[doc = "0x60 - Cadence QSPI Indirect Read"] - pub indirect_rd: INDIRECT_RD, + #[inline(always)] + pub const fn indirect_rd(&self) -> &INDIRECT_RD { + &self.indirect_rd + } #[doc = "0x64 - Cadence QSPI Indirect Read Watermark"] - pub indirect_rd_watermark: INDIRECT_RD_WATERMARK, + #[inline(always)] + pub const fn indirect_rd_watermark(&self) -> &INDIRECT_RD_WATERMARK { + &self.indirect_rd_watermark + } #[doc = "0x68 - Cadence QSPI Indirect Read Start Address"] - pub indirect_rd_start_addr: INDIRECT_RD_START_ADDR, + #[inline(always)] + pub const fn indirect_rd_start_addr(&self) -> &INDIRECT_RD_START_ADDR { + &self.indirect_rd_start_addr + } #[doc = "0x6c - Cadence QSPI Indirect Read Bytes"] - pub indirect_rd_bytes: INDIRECT_RD_BYTES, + #[inline(always)] + pub const fn indirect_rd_bytes(&self) -> &INDIRECT_RD_BYTES { + &self.indirect_rd_bytes + } #[doc = "0x70 - Cadence QSPI Indirect Write"] - pub indirect_wr: INDIRECT_WR, + #[inline(always)] + pub const fn indirect_wr(&self) -> &INDIRECT_WR { + &self.indirect_wr + } #[doc = "0x74 - Cadence QSPI Indirect Write Watermark"] - pub indirect_wr_watermark: INDIRECT_WR_WATERMARK, + #[inline(always)] + pub const fn indirect_wr_watermark(&self) -> &INDIRECT_WR_WATERMARK { + &self.indirect_wr_watermark + } #[doc = "0x78 - Cadence QSPI Indirect Write Start Address"] - pub indirect_wr_start_addr: INDIRECT_WR_START_ADDR, + #[inline(always)] + pub const fn indirect_wr_start_addr(&self) -> &INDIRECT_WR_START_ADDR { + &self.indirect_wr_start_addr + } #[doc = "0x7c - Cadence QSPI Indirect Write Bytes"] - pub indirect_wr_bytes: INDIRECT_WR_BYTES, - _reserved23: [u8; 0x10], + #[inline(always)] + pub const fn indirect_wr_bytes(&self) -> &INDIRECT_WR_BYTES { + &self.indirect_wr_bytes + } #[doc = "0x90 - Cadence QSPI Command Control"] - pub cmd_ctrl: CMD_CTRL, + #[inline(always)] + pub const fn cmd_ctrl(&self) -> &CMD_CTRL { + &self.cmd_ctrl + } #[doc = "0x94 - Cadence QSPI Command Address"] - pub cmd_address: CMD_ADDRESS, - _reserved25: [u8; 0x08], + #[inline(always)] + pub const fn cmd_address(&self) -> &CMD_ADDRESS { + &self.cmd_address + } #[doc = "0xa0 - Cadence QSPI Command Read at Lower"] - pub cmd_read_at_lower: CMD_READ_AT_LOWER, + #[inline(always)] + pub const fn cmd_read_at_lower(&self) -> &CMD_READ_AT_LOWER { + &self.cmd_read_at_lower + } #[doc = "0xa4 - Cadence QSPI Command Read at Upper"] - pub cmd_read_at_upper: CMD_READ_AT_UPPER, + #[inline(always)] + pub const fn cmd_read_at_upper(&self) -> &CMD_READ_AT_UPPER { + &self.cmd_read_at_upper + } #[doc = "0xa8 - Cadence QSPI Command Write at Lower"] - pub cmd_write_at_lower: CMD_WRITE_AT_LOWER, + #[inline(always)] + pub const fn cmd_write_at_lower(&self) -> &CMD_WRITE_AT_LOWER { + &self.cmd_write_at_lower + } #[doc = "0xac - Cadence QSPI Command Write at Upper"] - pub cmd_write_at_upper: CMD_WRITE_AT_UPPER, + #[inline(always)] + pub const fn cmd_write_at_upper(&self) -> &CMD_WRITE_AT_UPPER { + &self.cmd_write_at_upper + } #[doc = "0xb0 - Cadence QSPI Polling Status"] - pub polling_status: POLLING_STATUS, - _reserved30: [u8; 0x2c], + #[inline(always)] + pub const fn polling_status(&self) -> &POLLING_STATUS { + &self.polling_status + } #[doc = "0xe0 - Cadence QSPI Extension Lower"] - pub ext_lower: EXT_LOWER, + #[inline(always)] + pub const fn ext_lower(&self) -> &EXT_LOWER { + &self.ext_lower + } } -#[doc = "config (rw) register accessor: Cadence QSPI Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`config`] +#[doc = "config (rw) register accessor: Cadence QSPI Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] pub type CONFIG = crate::Reg; #[doc = "Cadence QSPI Configuration"] pub mod config; -#[doc = "rd_instr (rw) register accessor: Cadence QSPI Read Instruction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_instr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rd_instr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rd_instr`] +#[doc = "rd_instr (rw) register accessor: Cadence QSPI Read Instruction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_instr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rd_instr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_instr`] module"] pub type RD_INSTR = crate::Reg; #[doc = "Cadence QSPI Read Instruction"] pub mod rd_instr; -#[doc = "wr_instr (rw) register accessor: Cadence QSPI Write Instruction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_instr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_instr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wr_instr`] +#[doc = "wr_instr (rw) register accessor: Cadence QSPI Write Instruction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_instr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_instr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wr_instr`] module"] pub type WR_INSTR = crate::Reg; #[doc = "Cadence QSPI Write Instruction"] pub mod wr_instr; -#[doc = "delay (rw) register accessor: Cadence QSPI Delay\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`delay::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`delay::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`delay`] +#[doc = "delay (rw) register accessor: Cadence QSPI Delay\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`delay::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`delay::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@delay`] module"] pub type DELAY = crate::Reg; #[doc = "Cadence QSPI Delay"] pub mod delay; -#[doc = "read_capture (rw) register accessor: Cadence QSPI Read Capture\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`read_capture::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`read_capture::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`read_capture`] +#[doc = "read_capture (rw) register accessor: Cadence QSPI Read Capture\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`read_capture::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`read_capture::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@read_capture`] module"] pub type READ_CAPTURE = crate::Reg; #[doc = "Cadence QSPI Read Capture"] pub mod read_capture; -#[doc = "size (rw) register accessor: Cadence QSPI Size Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`size`] +#[doc = "size (rw) register accessor: Cadence QSPI Size Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@size`] module"] pub type SIZE = crate::Reg; #[doc = "Cadence QSPI Size Configuration"] pub mod size; -#[doc = "sram_partition (rw) register accessor: Cadence QSPI SRAM Partition Size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sram_partition::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sram_partition::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sram_partition`] +#[doc = "sram_partition (rw) register accessor: Cadence QSPI SRAM Partition Size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sram_partition::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sram_partition::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_partition`] module"] pub type SRAM_PARTITION = crate::Reg; #[doc = "Cadence QSPI SRAM Partition Size"] pub mod sram_partition; -#[doc = "indirect_trigger (rw) register accessor: Cadence QSPI Indirect Trigger Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_trigger::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_trigger::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_trigger`] +#[doc = "indirect_trigger (rw) register accessor: Cadence QSPI Indirect Trigger Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_trigger::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_trigger::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_trigger`] module"] pub type INDIRECT_TRIGGER = crate::Reg; #[doc = "Cadence QSPI Indirect Trigger Address"] pub mod indirect_trigger; -#[doc = "dma (rw) register accessor: Cadence QSPI Direct Memory Access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dma`] +#[doc = "dma (rw) register accessor: Cadence QSPI Direct Memory Access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma`] module"] pub type DMA = crate::Reg; #[doc = "Cadence QSPI Direct Memory Access"] pub mod dma; -#[doc = "remap (rw) register accessor: Cadence QSPI Remap Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`remap::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`remap::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`remap`] +#[doc = "remap (rw) register accessor: Cadence QSPI Remap Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`remap::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`remap::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@remap`] module"] pub type REMAP = crate::Reg; #[doc = "Cadence QSPI Remap Address"] pub mod remap; -#[doc = "mode_bit (rw) register accessor: Cadence QSPI Mode Bit(s)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode_bit::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode_bit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mode_bit`] +#[doc = "mode_bit (rw) register accessor: Cadence QSPI Mode Bit(s)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode_bit::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode_bit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode_bit`] module"] pub type MODE_BIT = crate::Reg; #[doc = "Cadence QSPI Mode Bit(s)"] pub mod mode_bit; -#[doc = "sdram_level (rw) register accessor: Cadence QSPI SDRAM Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdram_level::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdram_level::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sdram_level`] +#[doc = "sdram_level (rw) register accessor: Cadence QSPI SDRAM Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdram_level::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdram_level::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdram_level`] module"] pub type SDRAM_LEVEL = crate::Reg; #[doc = "Cadence QSPI SDRAM Level"] pub mod sdram_level; -#[doc = "wr_completion_ctrl (rw) register accessor: Cadence QSPI Write Completion Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_completion_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_completion_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wr_completion_ctrl`] +#[doc = "wr_completion_ctrl (rw) register accessor: Cadence QSPI Write Completion Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_completion_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_completion_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wr_completion_ctrl`] module"] pub type WR_COMPLETION_CTRL = crate::Reg; #[doc = "Cadence QSPI Write Completion Control"] pub mod wr_completion_ctrl; -#[doc = "irq_status (rw) register accessor: Cadence QSPI IRQ Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`irq_status`] +#[doc = "irq_status (rw) register accessor: Cadence QSPI IRQ Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_status`] module"] pub type IRQ_STATUS = crate::Reg; #[doc = "Cadence QSPI IRQ Status"] pub mod irq_status; -#[doc = "irq_mask (rw) register accessor: Cadence QSPI IRQ Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`irq_mask`] +#[doc = "irq_mask (rw) register accessor: Cadence QSPI IRQ Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_mask`] module"] pub type IRQ_MASK = crate::Reg; #[doc = "Cadence QSPI IRQ Mask"] pub mod irq_mask; -#[doc = "indirect_rd (rw) register accessor: Cadence QSPI Indirect Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_rd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_rd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_rd`] +#[doc = "indirect_rd (rw) register accessor: Cadence QSPI Indirect Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_rd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_rd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_rd`] module"] pub type INDIRECT_RD = crate::Reg; #[doc = "Cadence QSPI Indirect Read"] pub mod indirect_rd; -#[doc = "indirect_rd_watermark (rw) register accessor: Cadence QSPI Indirect Read Watermark\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_rd_watermark::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_rd_watermark::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_rd_watermark`] +#[doc = "indirect_rd_watermark (rw) register accessor: Cadence QSPI Indirect Read Watermark\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_rd_watermark::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_rd_watermark::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_rd_watermark`] module"] pub type INDIRECT_RD_WATERMARK = crate::Reg; #[doc = "Cadence QSPI Indirect Read Watermark"] pub mod indirect_rd_watermark; -#[doc = "indirect_rd_start_addr (rw) register accessor: Cadence QSPI Indirect Read Start Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_rd_start_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_rd_start_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_rd_start_addr`] +#[doc = "indirect_rd_start_addr (rw) register accessor: Cadence QSPI Indirect Read Start Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_rd_start_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_rd_start_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_rd_start_addr`] module"] pub type INDIRECT_RD_START_ADDR = crate::Reg; #[doc = "Cadence QSPI Indirect Read Start Address"] pub mod indirect_rd_start_addr; -#[doc = "indirect_rd_bytes (rw) register accessor: Cadence QSPI Indirect Read Bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_rd_bytes::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_rd_bytes::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_rd_bytes`] +#[doc = "indirect_rd_bytes (rw) register accessor: Cadence QSPI Indirect Read Bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_rd_bytes::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_rd_bytes::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_rd_bytes`] module"] pub type INDIRECT_RD_BYTES = crate::Reg; #[doc = "Cadence QSPI Indirect Read Bytes"] pub mod indirect_rd_bytes; -#[doc = "indirect_wr (rw) register accessor: Cadence QSPI Indirect Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_wr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_wr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_wr`] +#[doc = "indirect_wr (rw) register accessor: Cadence QSPI Indirect Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_wr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_wr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_wr`] module"] pub type INDIRECT_WR = crate::Reg; #[doc = "Cadence QSPI Indirect Write"] pub mod indirect_wr; -#[doc = "indirect_wr_watermark (rw) register accessor: Cadence QSPI Indirect Write Watermark\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_wr_watermark::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_wr_watermark::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_wr_watermark`] +#[doc = "indirect_wr_watermark (rw) register accessor: Cadence QSPI Indirect Write Watermark\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_wr_watermark::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_wr_watermark::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_wr_watermark`] module"] pub type INDIRECT_WR_WATERMARK = crate::Reg; #[doc = "Cadence QSPI Indirect Write Watermark"] pub mod indirect_wr_watermark; -#[doc = "indirect_wr_start_addr (rw) register accessor: Cadence QSPI Indirect Write Start Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_wr_start_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_wr_start_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_wr_start_addr`] +#[doc = "indirect_wr_start_addr (rw) register accessor: Cadence QSPI Indirect Write Start Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_wr_start_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_wr_start_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_wr_start_addr`] module"] pub type INDIRECT_WR_START_ADDR = crate::Reg; #[doc = "Cadence QSPI Indirect Write Start Address"] pub mod indirect_wr_start_addr; -#[doc = "indirect_wr_bytes (rw) register accessor: Cadence QSPI Indirect Write Bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_wr_bytes::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_wr_bytes::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`indirect_wr_bytes`] +#[doc = "indirect_wr_bytes (rw) register accessor: Cadence QSPI Indirect Write Bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indirect_wr_bytes::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`indirect_wr_bytes::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indirect_wr_bytes`] module"] pub type INDIRECT_WR_BYTES = crate::Reg; #[doc = "Cadence QSPI Indirect Write Bytes"] pub mod indirect_wr_bytes; -#[doc = "cmd_ctrl (rw) register accessor: Cadence QSPI Command Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmd_ctrl`] +#[doc = "cmd_ctrl (rw) register accessor: Cadence QSPI Command Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_ctrl`] module"] pub type CMD_CTRL = crate::Reg; #[doc = "Cadence QSPI Command Control"] pub mod cmd_ctrl; -#[doc = "cmd_address (rw) register accessor: Cadence QSPI Command Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_address::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmd_address`] +#[doc = "cmd_address (rw) register accessor: Cadence QSPI Command Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_address::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_address`] module"] pub type CMD_ADDRESS = crate::Reg; #[doc = "Cadence QSPI Command Address"] pub mod cmd_address; -#[doc = "cmd_read_at_lower (rw) register accessor: Cadence QSPI Command Read at Lower\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_read_at_lower::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_read_at_lower::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmd_read_at_lower`] +#[doc = "cmd_read_at_lower (rw) register accessor: Cadence QSPI Command Read at Lower\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_read_at_lower::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_read_at_lower::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_read_at_lower`] module"] pub type CMD_READ_AT_LOWER = crate::Reg; #[doc = "Cadence QSPI Command Read at Lower"] pub mod cmd_read_at_lower; -#[doc = "cmd_read_at_upper (rw) register accessor: Cadence QSPI Command Read at Upper\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_read_at_upper::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_read_at_upper::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmd_read_at_upper`] +#[doc = "cmd_read_at_upper (rw) register accessor: Cadence QSPI Command Read at Upper\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_read_at_upper::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_read_at_upper::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_read_at_upper`] module"] pub type CMD_READ_AT_UPPER = crate::Reg; #[doc = "Cadence QSPI Command Read at Upper"] pub mod cmd_read_at_upper; -#[doc = "cmd_write_at_lower (rw) register accessor: Cadence QSPI Command Write at Lower\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_write_at_lower::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_write_at_lower::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmd_write_at_lower`] +#[doc = "cmd_write_at_lower (rw) register accessor: Cadence QSPI Command Write at Lower\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_write_at_lower::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_write_at_lower::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_write_at_lower`] module"] pub type CMD_WRITE_AT_LOWER = crate::Reg; #[doc = "Cadence QSPI Command Write at Lower"] pub mod cmd_write_at_lower; -#[doc = "cmd_write_at_upper (rw) register accessor: Cadence QSPI Command Write at Upper\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_write_at_upper::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_write_at_upper::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmd_write_at_upper`] +#[doc = "cmd_write_at_upper (rw) register accessor: Cadence QSPI Command Write at Upper\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_write_at_upper::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_write_at_upper::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_write_at_upper`] module"] pub type CMD_WRITE_AT_UPPER = crate::Reg; #[doc = "Cadence QSPI Command Write at Upper"] pub mod cmd_write_at_upper; -#[doc = "polling_status (rw) register accessor: Cadence QSPI Polling Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`polling_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`polling_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`polling_status`] +#[doc = "polling_status (rw) register accessor: Cadence QSPI Polling Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`polling_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`polling_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@polling_status`] module"] pub type POLLING_STATUS = crate::Reg; #[doc = "Cadence QSPI Polling Status"] pub mod polling_status; -#[doc = "ext_lower (rw) register accessor: Cadence QSPI Extension Lower\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_lower::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_lower::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ext_lower`] +#[doc = "ext_lower (rw) register accessor: Cadence QSPI Extension Lower\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_lower::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_lower::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_lower`] module"] pub type EXT_LOWER = crate::Reg; #[doc = "Cadence QSPI Extension Lower"] diff --git a/jh7110-vf2-13b-pac/src/qspi/cmd_address.rs b/jh7110-vf2-13b-pac/src/qspi/cmd_address.rs index d508d41..5f821d2 100644 --- a/jh7110-vf2-13b-pac/src/qspi/cmd_address.rs +++ b/jh7110-vf2-13b-pac/src/qspi/cmd_address.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `address` reader - address"] pub type ADDRESS_R = crate::FieldReader; #[doc = "Field `address` writer - address"] -pub type ADDRESS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - address"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - address"] #[inline(always)] #[must_use] - pub fn address(&mut self) -> ADDRESS_W { - ADDRESS_W::new(self) + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/cmd_ctrl.rs b/jh7110-vf2-13b-pac/src/qspi/cmd_ctrl.rs index 8a263f0..69e1036 100644 --- a/jh7110-vf2-13b-pac/src/qspi/cmd_ctrl.rs +++ b/jh7110-vf2-13b-pac/src/qspi/cmd_ctrl.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `execute` reader - Execute-in-Place (XIP)"] pub type EXECUTE_R = crate::BitReader; #[doc = "Field `execute` writer - Execute-in-Place (XIP)"] -pub type EXECUTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EXECUTE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `in_progress` reader - Command in progress"] pub type IN_PROGRESS_R = crate::BitReader; #[doc = "Field `in_progress` writer - Command in progress"] -pub type IN_PROGRESS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IN_PROGRESS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dummy` reader - Dummy command"] pub type DUMMY_R = crate::FieldReader; #[doc = "Field `dummy` writer - Dummy command"] -pub type DUMMY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type DUMMY_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `wr_bytes` reader - Write bytes"] pub type WR_BYTES_R = crate::FieldReader; #[doc = "Field `wr_bytes` writer - Write bytes"] -pub type WR_BYTES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type WR_BYTES_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `wr_en` reader - Write enable"] pub type WR_EN_R = crate::BitReader; #[doc = "Field `wr_en` writer - Write enable"] -pub type WR_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type WR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `add_bytes` reader - Add command bytes"] pub type ADD_BYTES_R = crate::FieldReader; #[doc = "Field `add_bytes` writer - Add command bytes"] -pub type ADD_BYTES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type ADD_BYTES_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `addr_en` reader - Address enable"] pub type ADDR_EN_R = crate::BitReader; #[doc = "Field `addr_en` writer - Address enable"] -pub type ADDR_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ADDR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rd_bytes` reader - Read bytes"] pub type RD_BYTES_R = crate::FieldReader; #[doc = "Field `rd_bytes` writer - Read bytes"] -pub type RD_BYTES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type RD_BYTES_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `rd_en` reader - Read enable"] pub type RD_EN_R = crate::BitReader; #[doc = "Field `rd_en` writer - Read enable"] -pub type RD_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `opcode` reader - Command opcode"] pub type OPCODE_R = crate::FieldReader; #[doc = "Field `opcode` writer - Command opcode"] -pub type OPCODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type OPCODE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bit 0 - Execute-in-Place (XIP)"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bit 0 - Execute-in-Place (XIP)"] #[inline(always)] #[must_use] - pub fn execute(&mut self) -> EXECUTE_W { - EXECUTE_W::new(self) + pub fn execute(&mut self) -> EXECUTE_W { + EXECUTE_W::new(self, 0) } #[doc = "Bit 1 - Command in progress"] #[inline(always)] #[must_use] - pub fn in_progress(&mut self) -> IN_PROGRESS_W { - IN_PROGRESS_W::new(self) + pub fn in_progress(&mut self) -> IN_PROGRESS_W { + IN_PROGRESS_W::new(self, 1) } #[doc = "Bits 7:11 - Dummy command"] #[inline(always)] #[must_use] - pub fn dummy(&mut self) -> DUMMY_W { - DUMMY_W::new(self) + pub fn dummy(&mut self) -> DUMMY_W { + DUMMY_W::new(self, 7) } #[doc = "Bits 12:14 - Write bytes"] #[inline(always)] #[must_use] - pub fn wr_bytes(&mut self) -> WR_BYTES_W { - WR_BYTES_W::new(self) + pub fn wr_bytes(&mut self) -> WR_BYTES_W { + WR_BYTES_W::new(self, 12) } #[doc = "Bit 15 - Write enable"] #[inline(always)] #[must_use] - pub fn wr_en(&mut self) -> WR_EN_W { - WR_EN_W::new(self) + pub fn wr_en(&mut self) -> WR_EN_W { + WR_EN_W::new(self, 15) } #[doc = "Bits 16:17 - Add command bytes"] #[inline(always)] #[must_use] - pub fn add_bytes(&mut self) -> ADD_BYTES_W { - ADD_BYTES_W::new(self) + pub fn add_bytes(&mut self) -> ADD_BYTES_W { + ADD_BYTES_W::new(self, 16) } #[doc = "Bit 19 - Address enable"] #[inline(always)] #[must_use] - pub fn addr_en(&mut self) -> ADDR_EN_W { - ADDR_EN_W::new(self) + pub fn addr_en(&mut self) -> ADDR_EN_W { + ADDR_EN_W::new(self, 19) } #[doc = "Bits 20:22 - Read bytes"] #[inline(always)] #[must_use] - pub fn rd_bytes(&mut self) -> RD_BYTES_W { - RD_BYTES_W::new(self) + pub fn rd_bytes(&mut self) -> RD_BYTES_W { + RD_BYTES_W::new(self, 20) } #[doc = "Bit 23 - Read enable"] #[inline(always)] #[must_use] - pub fn rd_en(&mut self) -> RD_EN_W { - RD_EN_W::new(self) + pub fn rd_en(&mut self) -> RD_EN_W { + RD_EN_W::new(self, 23) } #[doc = "Bits 24:31 - Command opcode"] #[inline(always)] #[must_use] - pub fn opcode(&mut self) -> OPCODE_W { - OPCODE_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn opcode(&mut self) -> OPCODE_W { + OPCODE_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/cmd_read_at_lower.rs b/jh7110-vf2-13b-pac/src/qspi/cmd_read_at_lower.rs index fb1f108..1604970 100644 --- a/jh7110-vf2-13b-pac/src/qspi/cmd_read_at_lower.rs +++ b/jh7110-vf2-13b-pac/src/qspi/cmd_read_at_lower.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `read_at_lower` reader - read_at_lower"] pub type READ_AT_LOWER_R = crate::FieldReader; #[doc = "Field `read_at_lower` writer - read_at_lower"] -pub type READ_AT_LOWER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type READ_AT_LOWER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - read_at_lower"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - read_at_lower"] #[inline(always)] #[must_use] - pub fn read_at_lower(&mut self) -> READ_AT_LOWER_W { - READ_AT_LOWER_W::new(self) + pub fn read_at_lower(&mut self) -> READ_AT_LOWER_W { + READ_AT_LOWER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/cmd_read_at_upper.rs b/jh7110-vf2-13b-pac/src/qspi/cmd_read_at_upper.rs index f829ee5..6f7d5e6 100644 --- a/jh7110-vf2-13b-pac/src/qspi/cmd_read_at_upper.rs +++ b/jh7110-vf2-13b-pac/src/qspi/cmd_read_at_upper.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `read_at_upper` reader - read_at_upper"] pub type READ_AT_UPPER_R = crate::FieldReader; #[doc = "Field `read_at_upper` writer - read_at_upper"] -pub type READ_AT_UPPER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type READ_AT_UPPER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - read_at_upper"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - read_at_upper"] #[inline(always)] #[must_use] - pub fn read_at_upper(&mut self) -> READ_AT_UPPER_W { - READ_AT_UPPER_W::new(self) + pub fn read_at_upper(&mut self) -> READ_AT_UPPER_W { + READ_AT_UPPER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/cmd_write_at_lower.rs b/jh7110-vf2-13b-pac/src/qspi/cmd_write_at_lower.rs index 719d693..b98a00a 100644 --- a/jh7110-vf2-13b-pac/src/qspi/cmd_write_at_lower.rs +++ b/jh7110-vf2-13b-pac/src/qspi/cmd_write_at_lower.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `write_at_lower` reader - write_at_lower"] pub type WRITE_AT_LOWER_R = crate::FieldReader; #[doc = "Field `write_at_lower` writer - write_at_lower"] -pub type WRITE_AT_LOWER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type WRITE_AT_LOWER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - write_at_lower"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - write_at_lower"] #[inline(always)] #[must_use] - pub fn write_at_lower(&mut self) -> WRITE_AT_LOWER_W { - WRITE_AT_LOWER_W::new(self) + pub fn write_at_lower(&mut self) -> WRITE_AT_LOWER_W { + WRITE_AT_LOWER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/cmd_write_at_upper.rs b/jh7110-vf2-13b-pac/src/qspi/cmd_write_at_upper.rs index 7dc97fd..ebf247e 100644 --- a/jh7110-vf2-13b-pac/src/qspi/cmd_write_at_upper.rs +++ b/jh7110-vf2-13b-pac/src/qspi/cmd_write_at_upper.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `write_at_upper` reader - write_at_upper"] pub type WRITE_AT_UPPER_R = crate::FieldReader; #[doc = "Field `write_at_upper` writer - write_at_upper"] -pub type WRITE_AT_UPPER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type WRITE_AT_UPPER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - write_at_upper"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - write_at_upper"] #[inline(always)] #[must_use] - pub fn write_at_upper(&mut self) -> WRITE_AT_UPPER_W { - WRITE_AT_UPPER_W::new(self) + pub fn write_at_upper(&mut self) -> WRITE_AT_UPPER_W { + WRITE_AT_UPPER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/config.rs b/jh7110-vf2-13b-pac/src/qspi/config.rs index 8db366f..7d63937 100644 --- a/jh7110-vf2-13b-pac/src/qspi/config.rs +++ b/jh7110-vf2-13b-pac/src/qspi/config.rs @@ -5,39 +5,39 @@ pub type W = crate::W; #[doc = "Field `enable` reader - Enable the QSPI controller"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `enable` writer - Enable the QSPI controller"] -pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `enb_dir_acc_ctrl` reader - Enable direct access controller"] pub type ENB_DIR_ACC_CTRL_R = crate::BitReader; #[doc = "Field `enb_dir_acc_ctrl` writer - Enable direct access controller"] -pub type ENB_DIR_ACC_CTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ENB_DIR_ACC_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `decode` reader - Enable the QSPI decoder"] pub type DECODE_R = crate::BitReader; #[doc = "Field `decode` writer - Enable the QSPI decoder"] -pub type DECODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DECODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `chipselect` reader - Chip select - CS0: 0b1110, CS1: 0b1101, CS2: 0b1011, CS3: 0b0111"] pub type CHIPSELECT_R = crate::FieldReader; #[doc = "Field `chipselect` writer - Chip select - CS0: 0b1110, CS1: 0b1101, CS2: 0b1011, CS3: 0b0111"] -pub type CHIPSELECT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type CHIPSELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `dma` reader - Enable Direct Memory Access"] pub type DMA_R = crate::BitReader; #[doc = "Field `dma` writer - Enable Direct Memory Access"] -pub type DMA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `baud` reader - Set the QSPI BAUD rate divisor"] pub type BAUD_R = crate::FieldReader; #[doc = "Field `baud` writer - Set the QSPI BAUD rate divisor"] -pub type BAUD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type BAUD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `dtr_proto` reader - Enable DTR Protocol"] pub type DTR_PROTO_R = crate::BitReader; #[doc = "Field `dtr_proto` writer - Enable DTR Protocol"] -pub type DTR_PROTO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DTR_PROTO_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dual_opcode` reader - Enable Dual Opcode Mode"] pub type DUAL_OPCODE_R = crate::BitReader; #[doc = "Field `dual_opcode` writer - Enable Dual Opcode Mode"] -pub type DUAL_OPCODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DUAL_OPCODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `idle` reader - Set Idle"] pub type IDLE_R = crate::BitReader; #[doc = "Field `idle` writer - Set Idle"] -pub type IDLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IDLE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable the QSPI controller"] #[inline(always)] @@ -89,58 +89,62 @@ impl W { #[doc = "Bit 0 - Enable the QSPI controller"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W { - ENABLE_W::new(self) + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 0) } #[doc = "Bit 7 - Enable direct access controller"] #[inline(always)] #[must_use] - pub fn enb_dir_acc_ctrl(&mut self) -> ENB_DIR_ACC_CTRL_W { - ENB_DIR_ACC_CTRL_W::new(self) + pub fn enb_dir_acc_ctrl(&mut self) -> ENB_DIR_ACC_CTRL_W { + ENB_DIR_ACC_CTRL_W::new(self, 7) } #[doc = "Bit 9 - Enable the QSPI decoder"] #[inline(always)] #[must_use] - pub fn decode(&mut self) -> DECODE_W { - DECODE_W::new(self) + pub fn decode(&mut self) -> DECODE_W { + DECODE_W::new(self, 9) } #[doc = "Bits 10:13 - Chip select - CS0: 0b1110, CS1: 0b1101, CS2: 0b1011, CS3: 0b0111"] #[inline(always)] #[must_use] - pub fn chipselect(&mut self) -> CHIPSELECT_W { - CHIPSELECT_W::new(self) + pub fn chipselect(&mut self) -> CHIPSELECT_W { + CHIPSELECT_W::new(self, 10) } #[doc = "Bit 15 - Enable Direct Memory Access"] #[inline(always)] #[must_use] - pub fn dma(&mut self) -> DMA_W { - DMA_W::new(self) + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 15) } #[doc = "Bits 19:22 - Set the QSPI BAUD rate divisor"] #[inline(always)] #[must_use] - pub fn baud(&mut self) -> BAUD_W { - BAUD_W::new(self) + pub fn baud(&mut self) -> BAUD_W { + BAUD_W::new(self, 19) } #[doc = "Bit 24 - Enable DTR Protocol"] #[inline(always)] #[must_use] - pub fn dtr_proto(&mut self) -> DTR_PROTO_W { - DTR_PROTO_W::new(self) + pub fn dtr_proto(&mut self) -> DTR_PROTO_W { + DTR_PROTO_W::new(self, 24) } #[doc = "Bit 30 - Enable Dual Opcode Mode"] #[inline(always)] #[must_use] - pub fn dual_opcode(&mut self) -> DUAL_OPCODE_W { - DUAL_OPCODE_W::new(self) + pub fn dual_opcode(&mut self) -> DUAL_OPCODE_W { + DUAL_OPCODE_W::new(self, 30) } #[doc = "Bit 31 - Set Idle"] #[inline(always)] #[must_use] - pub fn idle(&mut self) -> IDLE_W { - IDLE_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn idle(&mut self) -> IDLE_W { + IDLE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/delay.rs b/jh7110-vf2-13b-pac/src/qspi/delay.rs index 3614dc4..41252ea 100644 --- a/jh7110-vf2-13b-pac/src/qspi/delay.rs +++ b/jh7110-vf2-13b-pac/src/qspi/delay.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `tslch` reader - TSLCH Delay Value"] pub type TSLCH_R = crate::FieldReader; #[doc = "Field `tslch` writer - TSLCH Delay Value"] -pub type TSLCH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type TSLCH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `tchsh` reader - TCHSH Delay Value"] pub type TCHSH_R = crate::FieldReader; #[doc = "Field `tchsh` writer - TCHSH Delay Value"] -pub type TCHSH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type TCHSH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `tsd2d` reader - TSD2D Delay Value"] pub type TSD2D_R = crate::FieldReader; #[doc = "Field `tsd2d` writer - TSD2D Delay Value"] -pub type TSD2D_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type TSD2D_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `tshsl` reader - TSHSL Delay Value"] pub type TSHSL_R = crate::FieldReader; #[doc = "Field `tshsl` writer - TSHSL Delay Value"] -pub type TSHSL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type TSHSL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - TSLCH Delay Value"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:7 - TSLCH Delay Value"] #[inline(always)] #[must_use] - pub fn tslch(&mut self) -> TSLCH_W { - TSLCH_W::new(self) + pub fn tslch(&mut self) -> TSLCH_W { + TSLCH_W::new(self, 0) } #[doc = "Bits 8:15 - TCHSH Delay Value"] #[inline(always)] #[must_use] - pub fn tchsh(&mut self) -> TCHSH_W { - TCHSH_W::new(self) + pub fn tchsh(&mut self) -> TCHSH_W { + TCHSH_W::new(self, 8) } #[doc = "Bits 16:23 - TSD2D Delay Value"] #[inline(always)] #[must_use] - pub fn tsd2d(&mut self) -> TSD2D_W { - TSD2D_W::new(self) + pub fn tsd2d(&mut self) -> TSD2D_W { + TSD2D_W::new(self, 16) } #[doc = "Bits 24:31 - TSHSL Delay Value"] #[inline(always)] #[must_use] - pub fn tshsl(&mut self) -> TSHSL_W { - TSHSL_W::new(self) + pub fn tshsl(&mut self) -> TSHSL_W { + TSHSL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/dma.rs b/jh7110-vf2-13b-pac/src/qspi/dma.rs index 69f69f7..d092c2c 100644 --- a/jh7110-vf2-13b-pac/src/qspi/dma.rs +++ b/jh7110-vf2-13b-pac/src/qspi/dma.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `single` reader - single"] pub type SINGLE_R = crate::FieldReader; #[doc = "Field `single` writer - single"] -pub type SINGLE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SINGLE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `burst` reader - burst"] pub type BURST_R = crate::FieldReader; #[doc = "Field `burst` writer - burst"] -pub type BURST_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type BURST_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - single"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:7 - single"] #[inline(always)] #[must_use] - pub fn single(&mut self) -> SINGLE_W { - SINGLE_W::new(self) + pub fn single(&mut self) -> SINGLE_W { + SINGLE_W::new(self, 0) } #[doc = "Bits 8:15 - burst"] #[inline(always)] #[must_use] - pub fn burst(&mut self) -> BURST_W { - BURST_W::new(self) + pub fn burst(&mut self) -> BURST_W { + BURST_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/ext_lower.rs b/jh7110-vf2-13b-pac/src/qspi/ext_lower.rs index 680588c..6e216e5 100644 --- a/jh7110-vf2-13b-pac/src/qspi/ext_lower.rs +++ b/jh7110-vf2-13b-pac/src/qspi/ext_lower.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `stig` reader - stig"] pub type STIG_R = crate::FieldReader; #[doc = "Field `stig` writer - stig"] -pub type STIG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type STIG_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; #[doc = "Field `write` reader - write"] pub type WRITE_R = crate::FieldReader; #[doc = "Field `write` writer - write"] -pub type WRITE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type WRITE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `read` reader - read"] pub type READ_R = crate::FieldReader; #[doc = "Field `read` writer - read"] -pub type READ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type READ_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:15 - stig"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:15 - stig"] #[inline(always)] #[must_use] - pub fn stig(&mut self) -> STIG_W { - STIG_W::new(self) + pub fn stig(&mut self) -> STIG_W { + STIG_W::new(self, 0) } #[doc = "Bits 16:23 - write"] #[inline(always)] #[must_use] - pub fn write(&mut self) -> WRITE_W { - WRITE_W::new(self) + pub fn write(&mut self) -> WRITE_W { + WRITE_W::new(self, 16) } #[doc = "Bits 24:31 - read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W { - READ_W::new(self) + pub fn read(&mut self) -> READ_W { + READ_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/indirect_rd.rs b/jh7110-vf2-13b-pac/src/qspi/indirect_rd.rs index 3b7556b..b35b5ac 100644 --- a/jh7110-vf2-13b-pac/src/qspi/indirect_rd.rs +++ b/jh7110-vf2-13b-pac/src/qspi/indirect_rd.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `start` reader - Start indirect read"] pub type START_R = crate::BitReader; #[doc = "Field `start` writer - Start indirect read"] -pub type START_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `cancel` reader - Cancel indirect read"] pub type CANCEL_R = crate::BitReader; #[doc = "Field `cancel` writer - Cancel indirect read"] -pub type CANCEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CANCEL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `done` reader - Indirect read done"] pub type DONE_R = crate::BitReader; #[doc = "Field `done` writer - Indirect read done"] -pub type DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DONE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Start indirect read"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bit 0 - Start indirect read"] #[inline(always)] #[must_use] - pub fn start(&mut self) -> START_W { - START_W::new(self) + pub fn start(&mut self) -> START_W { + START_W::new(self, 0) } #[doc = "Bit 1 - Cancel indirect read"] #[inline(always)] #[must_use] - pub fn cancel(&mut self) -> CANCEL_W { - CANCEL_W::new(self) + pub fn cancel(&mut self) -> CANCEL_W { + CANCEL_W::new(self, 1) } #[doc = "Bit 5 - Indirect read done"] #[inline(always)] #[must_use] - pub fn done(&mut self) -> DONE_W { - DONE_W::new(self) + pub fn done(&mut self) -> DONE_W { + DONE_W::new(self, 5) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/indirect_rd_bytes.rs b/jh7110-vf2-13b-pac/src/qspi/indirect_rd_bytes.rs index a8a6fef..edbb0a9 100644 --- a/jh7110-vf2-13b-pac/src/qspi/indirect_rd_bytes.rs +++ b/jh7110-vf2-13b-pac/src/qspi/indirect_rd_bytes.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `bytes` reader - bytes"] pub type BYTES_R = crate::FieldReader; #[doc = "Field `bytes` writer - bytes"] -pub type BYTES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type BYTES_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - bytes"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - bytes"] #[inline(always)] #[must_use] - pub fn bytes(&mut self) -> BYTES_W { - BYTES_W::new(self) + pub fn bytes(&mut self) -> BYTES_W { + BYTES_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/indirect_rd_start_addr.rs b/jh7110-vf2-13b-pac/src/qspi/indirect_rd_start_addr.rs index aafb690..d10e9ab 100644 --- a/jh7110-vf2-13b-pac/src/qspi/indirect_rd_start_addr.rs +++ b/jh7110-vf2-13b-pac/src/qspi/indirect_rd_start_addr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `address` reader - address"] pub type ADDRESS_R = crate::FieldReader; #[doc = "Field `address` writer - address"] -pub type ADDRESS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - address"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - address"] #[inline(always)] #[must_use] - pub fn address(&mut self) -> ADDRESS_W { - ADDRESS_W::new(self) + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/indirect_rd_watermark.rs b/jh7110-vf2-13b-pac/src/qspi/indirect_rd_watermark.rs index d8c6380..205a080 100644 --- a/jh7110-vf2-13b-pac/src/qspi/indirect_rd_watermark.rs +++ b/jh7110-vf2-13b-pac/src/qspi/indirect_rd_watermark.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `watermark` reader - watermark"] pub type WATERMARK_R = crate::FieldReader; #[doc = "Field `watermark` writer - watermark"] -pub type WATERMARK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type WATERMARK_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - watermark"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - watermark"] #[inline(always)] #[must_use] - pub fn watermark(&mut self) -> WATERMARK_W { - WATERMARK_W::new(self) + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/indirect_trigger.rs b/jh7110-vf2-13b-pac/src/qspi/indirect_trigger.rs index ba6a3fa..464fa57 100644 --- a/jh7110-vf2-13b-pac/src/qspi/indirect_trigger.rs +++ b/jh7110-vf2-13b-pac/src/qspi/indirect_trigger.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `address` reader - address"] pub type ADDRESS_R = crate::FieldReader; #[doc = "Field `address` writer - address"] -pub type ADDRESS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - address"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - address"] #[inline(always)] #[must_use] - pub fn address(&mut self) -> ADDRESS_W { - ADDRESS_W::new(self) + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/indirect_wr.rs b/jh7110-vf2-13b-pac/src/qspi/indirect_wr.rs index b54ed68..6d2d076 100644 --- a/jh7110-vf2-13b-pac/src/qspi/indirect_wr.rs +++ b/jh7110-vf2-13b-pac/src/qspi/indirect_wr.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `start` reader - Start indirect write"] pub type START_R = crate::BitReader; #[doc = "Field `start` writer - Start indirect write"] -pub type START_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `cancel` reader - Cancel indirect write"] pub type CANCEL_R = crate::BitReader; #[doc = "Field `cancel` writer - Cancel indirect write"] -pub type CANCEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CANCEL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `done` reader - Indirect write done"] pub type DONE_R = crate::BitReader; #[doc = "Field `done` writer - Indirect write done"] -pub type DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DONE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Start indirect write"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bit 0 - Start indirect write"] #[inline(always)] #[must_use] - pub fn start(&mut self) -> START_W { - START_W::new(self) + pub fn start(&mut self) -> START_W { + START_W::new(self, 0) } #[doc = "Bit 1 - Cancel indirect write"] #[inline(always)] #[must_use] - pub fn cancel(&mut self) -> CANCEL_W { - CANCEL_W::new(self) + pub fn cancel(&mut self) -> CANCEL_W { + CANCEL_W::new(self, 1) } #[doc = "Bit 5 - Indirect write done"] #[inline(always)] #[must_use] - pub fn done(&mut self) -> DONE_W { - DONE_W::new(self) + pub fn done(&mut self) -> DONE_W { + DONE_W::new(self, 5) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/indirect_wr_bytes.rs b/jh7110-vf2-13b-pac/src/qspi/indirect_wr_bytes.rs index 7fb2291..0732f0a 100644 --- a/jh7110-vf2-13b-pac/src/qspi/indirect_wr_bytes.rs +++ b/jh7110-vf2-13b-pac/src/qspi/indirect_wr_bytes.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `bytes` reader - bytes"] pub type BYTES_R = crate::FieldReader; #[doc = "Field `bytes` writer - bytes"] -pub type BYTES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type BYTES_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - bytes"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - bytes"] #[inline(always)] #[must_use] - pub fn bytes(&mut self) -> BYTES_W { - BYTES_W::new(self) + pub fn bytes(&mut self) -> BYTES_W { + BYTES_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/indirect_wr_start_addr.rs b/jh7110-vf2-13b-pac/src/qspi/indirect_wr_start_addr.rs index a907a11..0ed2591 100644 --- a/jh7110-vf2-13b-pac/src/qspi/indirect_wr_start_addr.rs +++ b/jh7110-vf2-13b-pac/src/qspi/indirect_wr_start_addr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `address` reader - address"] pub type ADDRESS_R = crate::FieldReader; #[doc = "Field `address` writer - address"] -pub type ADDRESS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - address"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - address"] #[inline(always)] #[must_use] - pub fn address(&mut self) -> ADDRESS_W { - ADDRESS_W::new(self) + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/indirect_wr_watermark.rs b/jh7110-vf2-13b-pac/src/qspi/indirect_wr_watermark.rs index 3a95c8d..8d2065c 100644 --- a/jh7110-vf2-13b-pac/src/qspi/indirect_wr_watermark.rs +++ b/jh7110-vf2-13b-pac/src/qspi/indirect_wr_watermark.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `watermark` reader - watermark"] pub type WATERMARK_R = crate::FieldReader; #[doc = "Field `watermark` writer - watermark"] -pub type WATERMARK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type WATERMARK_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - watermark"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - watermark"] #[inline(always)] #[must_use] - pub fn watermark(&mut self) -> WATERMARK_W { - WATERMARK_W::new(self) + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/irq_mask.rs b/jh7110-vf2-13b-pac/src/qspi/irq_mask.rs index 5905f86..0f87114 100644 --- a/jh7110-vf2-13b-pac/src/qspi/irq_mask.rs +++ b/jh7110-vf2-13b-pac/src/qspi/irq_mask.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `mode_err` reader - Mode error interrupt"] pub type MODE_ERR_R = crate::BitReader; #[doc = "Field `mode_err` writer - Mode error interrupt"] -pub type MODE_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `underflow` reader - Buffer underflow interrupt"] pub type UNDERFLOW_R = crate::BitReader; #[doc = "Field `underflow` writer - Buffer underflow interrupt"] -pub type UNDERFLOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type UNDERFLOW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ind_comp` reader - Indirect computation interrupt"] pub type IND_COMP_R = crate::BitReader; #[doc = "Field `ind_comp` writer - Indirect computation interrupt"] -pub type IND_COMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IND_COMP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ind_rd_reject` reader - Indirect read rejection interrupt"] pub type IND_RD_REJECT_R = crate::BitReader; #[doc = "Field `ind_rd_reject` writer - Indirect read rejection interrupt"] -pub type IND_RD_REJECT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IND_RD_REJECT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `wr_protected_err` reader - Write protected error interrupt"] pub type WR_PROTECTED_ERR_R = crate::BitReader; #[doc = "Field `wr_protected_err` writer - Write protected error interrupt"] -pub type WR_PROTECTED_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type WR_PROTECTED_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `illegal_ahb_err` reader - Illegal AHB clock error interrupt"] pub type ILLEGAL_AHB_ERR_R = crate::BitReader; #[doc = "Field `illegal_ahb_err` writer - Illegal AHB clock error interrupt"] -pub type ILLEGAL_AHB_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ILLEGAL_AHB_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `watermark` reader - Watermark interrupt"] pub type WATERMARK_R = crate::BitReader; #[doc = "Field `watermark` writer - Watermark interrupt"] -pub type WATERMARK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type WATERMARK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ind_sram_full` reader - Indirect SRAM full interrupt"] pub type IND_SRAM_FULL_R = crate::BitReader; #[doc = "Field `ind_sram_full` writer - Indirect SRAM full interrupt"] -pub type IND_SRAM_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IND_SRAM_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Mode error interrupt"] #[inline(always)] @@ -80,52 +80,56 @@ impl W { #[doc = "Bit 0 - Mode error interrupt"] #[inline(always)] #[must_use] - pub fn mode_err(&mut self) -> MODE_ERR_W { - MODE_ERR_W::new(self) + pub fn mode_err(&mut self) -> MODE_ERR_W { + MODE_ERR_W::new(self, 0) } #[doc = "Bit 1 - Buffer underflow interrupt"] #[inline(always)] #[must_use] - pub fn underflow(&mut self) -> UNDERFLOW_W { - UNDERFLOW_W::new(self) + pub fn underflow(&mut self) -> UNDERFLOW_W { + UNDERFLOW_W::new(self, 1) } #[doc = "Bit 2 - Indirect computation interrupt"] #[inline(always)] #[must_use] - pub fn ind_comp(&mut self) -> IND_COMP_W { - IND_COMP_W::new(self) + pub fn ind_comp(&mut self) -> IND_COMP_W { + IND_COMP_W::new(self, 2) } #[doc = "Bit 3 - Indirect read rejection interrupt"] #[inline(always)] #[must_use] - pub fn ind_rd_reject(&mut self) -> IND_RD_REJECT_W { - IND_RD_REJECT_W::new(self) + pub fn ind_rd_reject(&mut self) -> IND_RD_REJECT_W { + IND_RD_REJECT_W::new(self, 3) } #[doc = "Bit 4 - Write protected error interrupt"] #[inline(always)] #[must_use] - pub fn wr_protected_err(&mut self) -> WR_PROTECTED_ERR_W { - WR_PROTECTED_ERR_W::new(self) + pub fn wr_protected_err(&mut self) -> WR_PROTECTED_ERR_W { + WR_PROTECTED_ERR_W::new(self, 4) } #[doc = "Bit 5 - Illegal AHB clock error interrupt"] #[inline(always)] #[must_use] - pub fn illegal_ahb_err(&mut self) -> ILLEGAL_AHB_ERR_W { - ILLEGAL_AHB_ERR_W::new(self) + pub fn illegal_ahb_err(&mut self) -> ILLEGAL_AHB_ERR_W { + ILLEGAL_AHB_ERR_W::new(self, 5) } #[doc = "Bit 6 - Watermark interrupt"] #[inline(always)] #[must_use] - pub fn watermark(&mut self) -> WATERMARK_W { - WATERMARK_W::new(self) + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W::new(self, 6) } #[doc = "Bit 12 - Indirect SRAM full interrupt"] #[inline(always)] #[must_use] - pub fn ind_sram_full(&mut self) -> IND_SRAM_FULL_W { - IND_SRAM_FULL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn ind_sram_full(&mut self) -> IND_SRAM_FULL_W { + IND_SRAM_FULL_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/irq_status.rs b/jh7110-vf2-13b-pac/src/qspi/irq_status.rs index 2d399ef..4401e3f 100644 --- a/jh7110-vf2-13b-pac/src/qspi/irq_status.rs +++ b/jh7110-vf2-13b-pac/src/qspi/irq_status.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `mode_err` reader - Mode error interrupt"] pub type MODE_ERR_R = crate::BitReader; #[doc = "Field `mode_err` writer - Mode error interrupt"] -pub type MODE_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `underflow` reader - Buffer underflow interrupt"] pub type UNDERFLOW_R = crate::BitReader; #[doc = "Field `underflow` writer - Buffer underflow interrupt"] -pub type UNDERFLOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type UNDERFLOW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ind_comp` reader - Indirect computation interrupt"] pub type IND_COMP_R = crate::BitReader; #[doc = "Field `ind_comp` writer - Indirect computation interrupt"] -pub type IND_COMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IND_COMP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ind_rd_reject` reader - Indirect read rejection interrupt"] pub type IND_RD_REJECT_R = crate::BitReader; #[doc = "Field `ind_rd_reject` writer - Indirect read rejection interrupt"] -pub type IND_RD_REJECT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IND_RD_REJECT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `wr_protected_err` reader - Write protected error interrupt"] pub type WR_PROTECTED_ERR_R = crate::BitReader; #[doc = "Field `wr_protected_err` writer - Write protected error interrupt"] -pub type WR_PROTECTED_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type WR_PROTECTED_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `illegal_ahb_err` reader - Illegal AHB clock error interrupt"] pub type ILLEGAL_AHB_ERR_R = crate::BitReader; #[doc = "Field `illegal_ahb_err` writer - Illegal AHB clock error interrupt"] -pub type ILLEGAL_AHB_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ILLEGAL_AHB_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `watermark` reader - Watermark interrupt"] pub type WATERMARK_R = crate::BitReader; #[doc = "Field `watermark` writer - Watermark interrupt"] -pub type WATERMARK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type WATERMARK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ind_sram_full` reader - Indirect SRAM full interrupt"] pub type IND_SRAM_FULL_R = crate::BitReader; #[doc = "Field `ind_sram_full` writer - Indirect SRAM full interrupt"] -pub type IND_SRAM_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IND_SRAM_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Mode error interrupt"] #[inline(always)] @@ -80,52 +80,56 @@ impl W { #[doc = "Bit 0 - Mode error interrupt"] #[inline(always)] #[must_use] - pub fn mode_err(&mut self) -> MODE_ERR_W { - MODE_ERR_W::new(self) + pub fn mode_err(&mut self) -> MODE_ERR_W { + MODE_ERR_W::new(self, 0) } #[doc = "Bit 1 - Buffer underflow interrupt"] #[inline(always)] #[must_use] - pub fn underflow(&mut self) -> UNDERFLOW_W { - UNDERFLOW_W::new(self) + pub fn underflow(&mut self) -> UNDERFLOW_W { + UNDERFLOW_W::new(self, 1) } #[doc = "Bit 2 - Indirect computation interrupt"] #[inline(always)] #[must_use] - pub fn ind_comp(&mut self) -> IND_COMP_W { - IND_COMP_W::new(self) + pub fn ind_comp(&mut self) -> IND_COMP_W { + IND_COMP_W::new(self, 2) } #[doc = "Bit 3 - Indirect read rejection interrupt"] #[inline(always)] #[must_use] - pub fn ind_rd_reject(&mut self) -> IND_RD_REJECT_W { - IND_RD_REJECT_W::new(self) + pub fn ind_rd_reject(&mut self) -> IND_RD_REJECT_W { + IND_RD_REJECT_W::new(self, 3) } #[doc = "Bit 4 - Write protected error interrupt"] #[inline(always)] #[must_use] - pub fn wr_protected_err(&mut self) -> WR_PROTECTED_ERR_W { - WR_PROTECTED_ERR_W::new(self) + pub fn wr_protected_err(&mut self) -> WR_PROTECTED_ERR_W { + WR_PROTECTED_ERR_W::new(self, 4) } #[doc = "Bit 5 - Illegal AHB clock error interrupt"] #[inline(always)] #[must_use] - pub fn illegal_ahb_err(&mut self) -> ILLEGAL_AHB_ERR_W { - ILLEGAL_AHB_ERR_W::new(self) + pub fn illegal_ahb_err(&mut self) -> ILLEGAL_AHB_ERR_W { + ILLEGAL_AHB_ERR_W::new(self, 5) } #[doc = "Bit 6 - Watermark interrupt"] #[inline(always)] #[must_use] - pub fn watermark(&mut self) -> WATERMARK_W { - WATERMARK_W::new(self) + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W::new(self, 6) } #[doc = "Bit 12 - Indirect SRAM full interrupt"] #[inline(always)] #[must_use] - pub fn ind_sram_full(&mut self) -> IND_SRAM_FULL_W { - IND_SRAM_FULL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn ind_sram_full(&mut self) -> IND_SRAM_FULL_W { + IND_SRAM_FULL_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/mode_bit.rs b/jh7110-vf2-13b-pac/src/qspi/mode_bit.rs index fd794a8..8190db7 100644 --- a/jh7110-vf2-13b-pac/src/qspi/mode_bit.rs +++ b/jh7110-vf2-13b-pac/src/qspi/mode_bit.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `mode` reader - mode"] pub type MODE_R = crate::FieldReader; #[doc = "Field `mode` writer - mode"] -pub type MODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - mode"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - mode"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W { - MODE_W::new(self) + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/polling_status.rs b/jh7110-vf2-13b-pac/src/qspi/polling_status.rs index a1a1a6b..48c87b0 100644 --- a/jh7110-vf2-13b-pac/src/qspi/polling_status.rs +++ b/jh7110-vf2-13b-pac/src/qspi/polling_status.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `status` reader - status"] pub type STATUS_R = crate::FieldReader; #[doc = "Field `status` writer - status"] -pub type STATUS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type STATUS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; #[doc = "Field `dummy` reader - dummy"] pub type DUMMY_R = crate::FieldReader; #[doc = "Field `dummy` writer - dummy"] -pub type DUMMY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type DUMMY_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; impl R { #[doc = "Bits 0:15 - status"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:15 - status"] #[inline(always)] #[must_use] - pub fn status(&mut self) -> STATUS_W { - STATUS_W::new(self) + pub fn status(&mut self) -> STATUS_W { + STATUS_W::new(self, 0) } #[doc = "Bits 16:20 - dummy"] #[inline(always)] #[must_use] - pub fn dummy(&mut self) -> DUMMY_W { - DUMMY_W::new(self) + pub fn dummy(&mut self) -> DUMMY_W { + DUMMY_W::new(self, 16) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/rd_instr.rs b/jh7110-vf2-13b-pac/src/qspi/rd_instr.rs index 01773c7..a14d7d8 100644 --- a/jh7110-vf2-13b-pac/src/qspi/rd_instr.rs +++ b/jh7110-vf2-13b-pac/src/qspi/rd_instr.rs @@ -5,27 +5,27 @@ pub type W = crate::W; #[doc = "Field `opcode` reader - Instruction Opcode"] pub type OPCODE_R = crate::FieldReader; #[doc = "Field `opcode` writer - Instruction Opcode"] -pub type OPCODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type OPCODE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `type_instr` reader - Type of Instruction"] pub type TYPE_INSTR_R = crate::FieldReader; #[doc = "Field `type_instr` writer - Type of Instruction"] -pub type TYPE_INSTR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TYPE_INSTR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `type_addr` reader - Type of Address"] pub type TYPE_ADDR_R = crate::FieldReader; #[doc = "Field `type_addr` writer - Type of Address"] -pub type TYPE_ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TYPE_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `type_data` reader - type_data"] pub type TYPE_DATA_R = crate::FieldReader; #[doc = "Field `type_data` writer - type_data"] -pub type TYPE_DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TYPE_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `mode_en` reader - Mode"] pub type MODE_EN_R = crate::BitReader; #[doc = "Field `mode_en` writer - Mode"] -pub type MODE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MODE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dummy` reader - Send dummy signal to stall the device"] pub type DUMMY_R = crate::FieldReader; #[doc = "Field `dummy` writer - Send dummy signal to stall the device"] -pub type DUMMY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type DUMMY_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; impl R { #[doc = "Bits 0:7 - Instruction Opcode"] #[inline(always)] @@ -62,40 +62,44 @@ impl W { #[doc = "Bits 0:7 - Instruction Opcode"] #[inline(always)] #[must_use] - pub fn opcode(&mut self) -> OPCODE_W { - OPCODE_W::new(self) + pub fn opcode(&mut self) -> OPCODE_W { + OPCODE_W::new(self, 0) } #[doc = "Bits 8:9 - Type of Instruction"] #[inline(always)] #[must_use] - pub fn type_instr(&mut self) -> TYPE_INSTR_W { - TYPE_INSTR_W::new(self) + pub fn type_instr(&mut self) -> TYPE_INSTR_W { + TYPE_INSTR_W::new(self, 8) } #[doc = "Bits 12:13 - Type of Address"] #[inline(always)] #[must_use] - pub fn type_addr(&mut self) -> TYPE_ADDR_W { - TYPE_ADDR_W::new(self) + pub fn type_addr(&mut self) -> TYPE_ADDR_W { + TYPE_ADDR_W::new(self, 12) } #[doc = "Bits 16:17 - type_data"] #[inline(always)] #[must_use] - pub fn type_data(&mut self) -> TYPE_DATA_W { - TYPE_DATA_W::new(self) + pub fn type_data(&mut self) -> TYPE_DATA_W { + TYPE_DATA_W::new(self, 16) } #[doc = "Bit 20 - Mode"] #[inline(always)] #[must_use] - pub fn mode_en(&mut self) -> MODE_EN_W { - MODE_EN_W::new(self) + pub fn mode_en(&mut self) -> MODE_EN_W { + MODE_EN_W::new(self, 20) } #[doc = "Bits 24:28 - Send dummy signal to stall the device"] #[inline(always)] #[must_use] - pub fn dummy(&mut self) -> DUMMY_W { - DUMMY_W::new(self) + pub fn dummy(&mut self) -> DUMMY_W { + DUMMY_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/read_capture.rs b/jh7110-vf2-13b-pac/src/qspi/read_capture.rs index 95a546d..e9d9683 100644 --- a/jh7110-vf2-13b-pac/src/qspi/read_capture.rs +++ b/jh7110-vf2-13b-pac/src/qspi/read_capture.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `bypass` reader - Bypass the Read Capture"] pub type BYPASS_R = crate::BitReader; #[doc = "Field `bypass` writer - Bypass the Read Capture"] -pub type BYPASS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `delay` reader - Read Capture Delay Value"] pub type DELAY_R = crate::FieldReader; #[doc = "Field `delay` writer - Read Capture Delay Value"] -pub type DELAY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bit 0 - Bypass the Read Capture"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Bypass the Read Capture"] #[inline(always)] #[must_use] - pub fn bypass(&mut self) -> BYPASS_W { - BYPASS_W::new(self) + pub fn bypass(&mut self) -> BYPASS_W { + BYPASS_W::new(self, 0) } #[doc = "Bits 1:4 - Read Capture Delay Value"] #[inline(always)] #[must_use] - pub fn delay(&mut self) -> DELAY_W { - DELAY_W::new(self) + pub fn delay(&mut self) -> DELAY_W { + DELAY_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/remap.rs b/jh7110-vf2-13b-pac/src/qspi/remap.rs index 08817cf..61a35ba 100644 --- a/jh7110-vf2-13b-pac/src/qspi/remap.rs +++ b/jh7110-vf2-13b-pac/src/qspi/remap.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `address` reader - address"] pub type ADDRESS_R = crate::FieldReader; #[doc = "Field `address` writer - address"] -pub type ADDRESS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - address"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - address"] #[inline(always)] #[must_use] - pub fn address(&mut self) -> ADDRESS_W { - ADDRESS_W::new(self) + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/sdram_level.rs b/jh7110-vf2-13b-pac/src/qspi/sdram_level.rs index 9b85b9b..43f3d10 100644 --- a/jh7110-vf2-13b-pac/src/qspi/sdram_level.rs +++ b/jh7110-vf2-13b-pac/src/qspi/sdram_level.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/size.rs b/jh7110-vf2-13b-pac/src/qspi/size.rs index de6de89..bd4058d 100644 --- a/jh7110-vf2-13b-pac/src/qspi/size.rs +++ b/jh7110-vf2-13b-pac/src/qspi/size.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `address` reader - Address Size in Bytes"] pub type ADDRESS_R = crate::FieldReader; #[doc = "Field `address` writer - Address Size in Bytes"] -pub type ADDRESS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `page` reader - Page Size in Bytes"] pub type PAGE_R = crate::FieldReader; #[doc = "Field `page` writer - Page Size in Bytes"] -pub type PAGE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; +pub type PAGE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; #[doc = "Field `block` reader - Block Size in Bytes"] pub type BLOCK_R = crate::FieldReader; #[doc = "Field `block` writer - Block Size in Bytes"] -pub type BLOCK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type BLOCK_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:3 - Address Size in Bytes"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:3 - Address Size in Bytes"] #[inline(always)] #[must_use] - pub fn address(&mut self) -> ADDRESS_W { - ADDRESS_W::new(self) + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) } #[doc = "Bits 4:15 - Page Size in Bytes"] #[inline(always)] #[must_use] - pub fn page(&mut self) -> PAGE_W { - PAGE_W::new(self) + pub fn page(&mut self) -> PAGE_W { + PAGE_W::new(self, 4) } #[doc = "Bits 16:21 - Block Size in Bytes"] #[inline(always)] #[must_use] - pub fn block(&mut self) -> BLOCK_W { - BLOCK_W::new(self) + pub fn block(&mut self) -> BLOCK_W { + BLOCK_W::new(self, 16) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/sram_partition.rs b/jh7110-vf2-13b-pac/src/qspi/sram_partition.rs index c2a5fd0..daf2451 100644 --- a/jh7110-vf2-13b-pac/src/qspi/sram_partition.rs +++ b/jh7110-vf2-13b-pac/src/qspi/sram_partition.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `size` reader - Partition size in bytes"] pub type SIZE_R = crate::FieldReader; #[doc = "Field `size` writer - Partition size in bytes"] -pub type SIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - Partition size in bytes"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - Partition size in bytes"] #[inline(always)] #[must_use] - pub fn size(&mut self) -> SIZE_W { - SIZE_W::new(self) + pub fn size(&mut self) -> SIZE_W { + SIZE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/wr_completion_ctrl.rs b/jh7110-vf2-13b-pac/src/qspi/wr_completion_ctrl.rs index 8413a1e..dbefab4 100644 --- a/jh7110-vf2-13b-pac/src/qspi/wr_completion_ctrl.rs +++ b/jh7110-vf2-13b-pac/src/qspi/wr_completion_ctrl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `disable_auto_poll` reader - SPI NAND flashes require the address of the status register to be passed in the Read SR command. Also, some SPI NOR flashes like the Cypress Semper flash expect a 4-byte dummy address in the Read SR command in DTR mode. But this controller does not support address phase in the Read SR command when doing auto-HW polling. So, disable write completion polling on the controller's side. spi-nand and spi-nor will take care of polling the status register."] pub type DISABLE_AUTO_POLL_R = crate::BitReader; #[doc = "Field `disable_auto_poll` writer - SPI NAND flashes require the address of the status register to be passed in the Read SR command. Also, some SPI NOR flashes like the Cypress Semper flash expect a 4-byte dummy address in the Read SR command in DTR mode. But this controller does not support address phase in the Read SR command when doing auto-HW polling. So, disable write completion polling on the controller's side. spi-nand and spi-nor will take care of polling the status register."] -pub type DISABLE_AUTO_POLL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DISABLE_AUTO_POLL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 14 - SPI NAND flashes require the address of the status register to be passed in the Read SR command. Also, some SPI NOR flashes like the Cypress Semper flash expect a 4-byte dummy address in the Read SR command in DTR mode. But this controller does not support address phase in the Read SR command when doing auto-HW polling. So, disable write completion polling on the controller's side. spi-nand and spi-nor will take care of polling the status register."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 14 - SPI NAND flashes require the address of the status register to be passed in the Read SR command. Also, some SPI NOR flashes like the Cypress Semper flash expect a 4-byte dummy address in the Read SR command in DTR mode. But this controller does not support address phase in the Read SR command when doing auto-HW polling. So, disable write completion polling on the controller's side. spi-nand and spi-nor will take care of polling the status register."] #[inline(always)] #[must_use] - pub fn disable_auto_poll(&mut self) -> DISABLE_AUTO_POLL_W { - DISABLE_AUTO_POLL_W::new(self) + pub fn disable_auto_poll(&mut self) -> DISABLE_AUTO_POLL_W { + DISABLE_AUTO_POLL_W::new(self, 14) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/qspi/wr_instr.rs b/jh7110-vf2-13b-pac/src/qspi/wr_instr.rs index 8a9c951..2d0ba7a 100644 --- a/jh7110-vf2-13b-pac/src/qspi/wr_instr.rs +++ b/jh7110-vf2-13b-pac/src/qspi/wr_instr.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `opcode` reader - Instruction Opcode"] pub type OPCODE_R = crate::FieldReader; #[doc = "Field `opcode` writer - Instruction Opcode"] -pub type OPCODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type OPCODE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `type_addr` reader - Type of Address"] pub type TYPE_ADDR_R = crate::FieldReader; #[doc = "Field `type_addr` writer - Type of Address"] -pub type TYPE_ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TYPE_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `type_data` reader - type_data"] pub type TYPE_DATA_R = crate::FieldReader; #[doc = "Field `type_data` writer - type_data"] -pub type TYPE_DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TYPE_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:7 - Instruction Opcode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:7 - Instruction Opcode"] #[inline(always)] #[must_use] - pub fn opcode(&mut self) -> OPCODE_W { - OPCODE_W::new(self) + pub fn opcode(&mut self) -> OPCODE_W { + OPCODE_W::new(self, 0) } #[doc = "Bits 12:13 - Type of Address"] #[inline(always)] #[must_use] - pub fn type_addr(&mut self) -> TYPE_ADDR_W { - TYPE_ADDR_W::new(self) + pub fn type_addr(&mut self) -> TYPE_ADDR_W { + TYPE_ADDR_W::new(self, 12) } #[doc = "Bits 16:17 - type_data"] #[inline(always)] #[must_use] - pub fn type_data(&mut self) -> TYPE_DATA_W { - TYPE_DATA_W::new(self) + pub fn type_data(&mut self) -> TYPE_DATA_W { + TYPE_DATA_W::new(self, 16) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0.rs b/jh7110-vf2-13b-pac/src/spi0.rs index e1d7fdc..6e69208 100644 --- a/jh7110-vf2-13b-pac/src/spi0.rs +++ b/jh7110-vf2-13b-pac/src/spi0.rs @@ -1,146 +1,220 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] - pub ssp_cr0: SSP_CR0, + ssp_cr0: SSP_CR0, _reserved1: [u8; 0x02], - #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] - pub ssp_cr1: SSP_CR1, + ssp_cr1: SSP_CR1, _reserved2: [u8; 0x02], - #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] - pub ssp_dr: SSP_DR, + ssp_dr: SSP_DR, _reserved3: [u8; 0x02], - #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] - pub ssp_sr: SSP_SR, + ssp_sr: SSP_SR, _reserved4: [u8; 0x02], - #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] - pub ssp_cpsr: SSP_CPSR, + ssp_cpsr: SSP_CPSR, _reserved5: [u8; 0x02], - #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] - pub ssp_imsc: SSP_IMSC, + ssp_imsc: SSP_IMSC, _reserved6: [u8; 0x02], - #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] - pub ssp_ris: SSP_RIS, + ssp_ris: SSP_RIS, _reserved7: [u8; 0x02], - #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] - pub ssp_mis: SSP_MIS, + ssp_mis: SSP_MIS, _reserved8: [u8; 0x02], - #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] - pub ssp_icr: SSP_ICR, + ssp_icr: SSP_ICR, _reserved9: [u8; 0x02], - #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] - pub ssp_dmacr: SSP_DMACR, + ssp_dmacr: SSP_DMACR, _reserved10: [u8; 0x0fba], - #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id0: SSP_PERIPH_ID0, + ssp_periph_id0: SSP_PERIPH_ID0, _reserved11: [u8; 0x02], - #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id1: SSP_PERIPH_ID1, + ssp_periph_id1: SSP_PERIPH_ID1, _reserved12: [u8; 0x02], - #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id2: SSP_PERIPH_ID2, + ssp_periph_id2: SSP_PERIPH_ID2, _reserved13: [u8; 0x02], - #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id3: SSP_PERIPH_ID3, + ssp_periph_id3: SSP_PERIPH_ID3, _reserved14: [u8; 0x02], - #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id0: SSP_PCELL_ID0, + ssp_pcell_id0: SSP_PCELL_ID0, _reserved15: [u8; 0x02], - #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id1: SSP_PCELL_ID1, + ssp_pcell_id1: SSP_PCELL_ID1, _reserved16: [u8; 0x02], - #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id2: SSP_PCELL_ID2, + ssp_pcell_id2: SSP_PCELL_ID2, _reserved17: [u8; 0x02], + ssp_pcell_id3: SSP_PCELL_ID3, +} +impl RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr0(&self) -> &SSP_CR0 { + &self.ssp_cr0 + } + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr1(&self) -> &SSP_CR1 { + &self.ssp_cr1 + } + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + #[inline(always)] + pub const fn ssp_dr(&self) -> &SSP_DR { + &self.ssp_dr + } + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + #[inline(always)] + pub const fn ssp_sr(&self) -> &SSP_SR { + &self.ssp_sr + } + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + #[inline(always)] + pub const fn ssp_cpsr(&self) -> &SSP_CPSR { + &self.ssp_cpsr + } + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + #[inline(always)] + pub const fn ssp_imsc(&self) -> &SSP_IMSC { + &self.ssp_imsc + } + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + #[inline(always)] + pub const fn ssp_ris(&self) -> &SSP_RIS { + &self.ssp_ris + } + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + #[inline(always)] + pub const fn ssp_mis(&self) -> &SSP_MIS { + &self.ssp_mis + } + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + #[inline(always)] + pub const fn ssp_icr(&self) -> &SSP_ICR { + &self.ssp_icr + } + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + #[inline(always)] + pub const fn ssp_dmacr(&self) -> &SSP_DMACR { + &self.ssp_dmacr + } + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id0(&self) -> &SSP_PERIPH_ID0 { + &self.ssp_periph_id0 + } + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id1(&self) -> &SSP_PERIPH_ID1 { + &self.ssp_periph_id1 + } + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id2(&self) -> &SSP_PERIPH_ID2 { + &self.ssp_periph_id2 + } + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id3(&self) -> &SSP_PERIPH_ID3 { + &self.ssp_periph_id3 + } + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id0(&self) -> &SSP_PCELL_ID0 { + &self.ssp_pcell_id0 + } + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id1(&self) -> &SSP_PCELL_ID1 { + &self.ssp_pcell_id1 + } + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id2(&self) -> &SSP_PCELL_ID2 { + &self.ssp_pcell_id2 + } #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id3: SSP_PCELL_ID3, + #[inline(always)] + pub const fn ssp_pcell_id3(&self) -> &SSP_PCELL_ID3 { + &self.ssp_pcell_id3 + } } -#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr0`] module"] pub type SSP_CR0 = crate::Reg; #[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] pub mod ssp_cr0; -#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr1`] module"] pub type SSP_CR1 = crate::Reg; #[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] pub mod ssp_cr1; -#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dr`] module"] pub type SSP_DR = crate::Reg; #[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] pub mod ssp_dr; -#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_sr`] module"] pub type SSP_SR = crate::Reg; #[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] pub mod ssp_sr; -#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cpsr`] module"] pub type SSP_CPSR = crate::Reg; #[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] pub mod ssp_cpsr; -#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_imsc`] module"] pub type SSP_IMSC = crate::Reg; #[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] pub mod ssp_imsc; -#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_ris`] module"] pub type SSP_RIS = crate::Reg; #[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] pub mod ssp_ris; -#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_mis`] module"] pub type SSP_MIS = crate::Reg; #[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] pub mod ssp_mis; -#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_icr`] module"] pub type SSP_ICR = crate::Reg; #[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] pub mod ssp_icr; -#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dmacr`] module"] pub type SSP_DMACR = crate::Reg; #[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] pub mod ssp_dmacr; -#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id0`] module"] pub type SSP_PERIPH_ID0 = crate::Reg; #[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id0; -#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id1`] module"] pub type SSP_PERIPH_ID1 = crate::Reg; #[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id1; -#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id2`] module"] pub type SSP_PERIPH_ID2 = crate::Reg; #[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id2; -#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id3`] module"] pub type SSP_PERIPH_ID3 = crate::Reg; #[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id3; -#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id0`] module"] pub type SSP_PCELL_ID0 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id0; -#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id1`] module"] pub type SSP_PCELL_ID1 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id1; -#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id2`] module"] pub type SSP_PCELL_ID2 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id2; -#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id3`] module"] pub type SSP_PCELL_ID3 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_cpsr.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_cpsr.rs index 214d9da..2fa25a9 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_cpsr.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_cpsr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] pub type CPSDVSR_R = crate::FieldReader; #[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] -pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type CPSDVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] #[must_use] - pub fn cpsdvsr(&mut self) -> CPSDVSR_W { - CPSDVSR_W::new(self) + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_cr0.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_cr0.rs index 1f3740e..b3ee9c6 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_cr0.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_cr0.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `dss` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] pub type DSS_R = crate::FieldReader; #[doc = "Field `dss` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] -pub type DSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type DSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] pub type FRF_R = crate::FieldReader; #[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] -pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] pub type SPO_R = crate::BitReader; #[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] -pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPO_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] pub type SPH_R = crate::BitReader; #[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] -pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPH_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] @@ -56,35 +56,39 @@ impl W { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] #[must_use] - pub fn dss(&mut self) -> DSS_W { - DSS_W::new(self) + pub fn dss(&mut self) -> DSS_W { + DSS_W::new(self, 0) } #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] #[inline(always)] #[must_use] - pub fn frf(&mut self) -> FRF_W { - FRF_W::new(self) + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self, 4) } #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn spo(&mut self) -> SPO_W { - SPO_W::new(self) + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self, 6) } #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn sph(&mut self) -> SPH_W { - SPH_W::new(self) + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self, 6) } #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_cr1.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_cr1.rs index 69dbcbd..b115461 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_cr1.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_cr1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] pub type LBM_R = crate::BitReader; #[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] -pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LBM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] pub type SSE_R = crate::BitReader; #[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] -pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SSE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] pub type MS_R = crate::BitReader; #[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] -pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] pub type SOD_R = crate::BitReader; #[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] -pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SOD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] #[must_use] - pub fn lbm(&mut self) -> LBM_W { - LBM_W::new(self) + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self, 0) } #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] #[inline(always)] #[must_use] - pub fn sse(&mut self) -> SSE_W { - SSE_W::new(self) + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self, 1) } #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] #[inline(always)] #[must_use] - pub fn ms(&mut self) -> MS_W { - MS_W::new(self) + pub fn ms(&mut self) -> MS_W { + MS_W::new(self, 2) } #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] #[inline(always)] #[must_use] - pub fn sod(&mut self) -> SOD_W { - SOD_W::new(self) + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_dmacr.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_dmacr.rs index c20ae0f..d7fd182 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_dmacr.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_dmacr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub type RXDMAE_R = crate::BitReader; #[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] -pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub type TXDMAE_R = crate::BitReader; #[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] -pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W { - RXDMAE_W::new(self) + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self, 0) } #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W { - TXDMAE_W::new(self) + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_dr.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_dr.rs index 019ee7c..ad69481 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_dr.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_dr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub type DATA_R = crate::FieldReader; #[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] -pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W { - DATA_W::new(self) + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_icr.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_icr.rs index 9828eba..78a767d 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_icr.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_icr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] pub type RORIC_R = crate::BitReader; #[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] -pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] pub type RTIC_R = crate::BitReader; #[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] -pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIC_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] #[must_use] - pub fn roric(&mut self) -> RORIC_W { - RORIC_W::new(self) + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self, 0) } #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W { - RTIC_W::new(self) + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_imsc.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_imsc.rs index c628750..63738cd 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_imsc.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_imsc.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] pub type RORIM_R = crate::BitReader; #[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] -pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] pub type RTIM_R = crate::BitReader; #[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] -pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] pub type RXIM_R = crate::BitReader; #[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] -pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] pub type TXIM_R = crate::BitReader; #[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] -pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rorim(&mut self) -> RORIM_W { - RORIM_W::new(self) + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self, 0) } #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W { - RTIM_W::new(self) + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self, 1) } #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W { - RXIM_W::new(self) + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self, 2) } #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W { - TXIM_W::new(self) + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_mis.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_mis.rs index 358b1d4..1c50710 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_mis.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_mis.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id0.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id0.rs index 7210289..9b50e59 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id0.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id1.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id1.rs index 0953ee0..2e23cc7 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id1.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id2.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id2.rs index 5f0696d..1b5fb34 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id2.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id2.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id3.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id3.rs index c532f5c..6642d55 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id3.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_pcell_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_periph_id0.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_periph_id0.rs index 98a341a..c69007a 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_periph_id0.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_periph_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_periph_id1.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_periph_id1.rs index 0c53a92..71907fb 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_periph_id1.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_periph_id1.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_periph_id2.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_periph_id2.rs index 1b49543..2efc3ae 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_periph_id2.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_periph_id2.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_periph_id3.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_periph_id3.rs index 8f18a77..c2f7b1c 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_periph_id3.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_periph_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_ris.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_ris.rs index 46ca4be..27dee48 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_ris.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_ris.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi0/ssp_sr.rs b/jh7110-vf2-13b-pac/src/spi0/ssp_sr.rs index b25ffb6..bf388f5 100644 --- a/jh7110-vf2-13b-pac/src/spi0/ssp_sr.rs +++ b/jh7110-vf2-13b-pac/src/spi0/ssp_sr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1.rs b/jh7110-vf2-13b-pac/src/spi1.rs index e1d7fdc..6e69208 100644 --- a/jh7110-vf2-13b-pac/src/spi1.rs +++ b/jh7110-vf2-13b-pac/src/spi1.rs @@ -1,146 +1,220 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] - pub ssp_cr0: SSP_CR0, + ssp_cr0: SSP_CR0, _reserved1: [u8; 0x02], - #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] - pub ssp_cr1: SSP_CR1, + ssp_cr1: SSP_CR1, _reserved2: [u8; 0x02], - #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] - pub ssp_dr: SSP_DR, + ssp_dr: SSP_DR, _reserved3: [u8; 0x02], - #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] - pub ssp_sr: SSP_SR, + ssp_sr: SSP_SR, _reserved4: [u8; 0x02], - #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] - pub ssp_cpsr: SSP_CPSR, + ssp_cpsr: SSP_CPSR, _reserved5: [u8; 0x02], - #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] - pub ssp_imsc: SSP_IMSC, + ssp_imsc: SSP_IMSC, _reserved6: [u8; 0x02], - #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] - pub ssp_ris: SSP_RIS, + ssp_ris: SSP_RIS, _reserved7: [u8; 0x02], - #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] - pub ssp_mis: SSP_MIS, + ssp_mis: SSP_MIS, _reserved8: [u8; 0x02], - #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] - pub ssp_icr: SSP_ICR, + ssp_icr: SSP_ICR, _reserved9: [u8; 0x02], - #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] - pub ssp_dmacr: SSP_DMACR, + ssp_dmacr: SSP_DMACR, _reserved10: [u8; 0x0fba], - #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id0: SSP_PERIPH_ID0, + ssp_periph_id0: SSP_PERIPH_ID0, _reserved11: [u8; 0x02], - #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id1: SSP_PERIPH_ID1, + ssp_periph_id1: SSP_PERIPH_ID1, _reserved12: [u8; 0x02], - #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id2: SSP_PERIPH_ID2, + ssp_periph_id2: SSP_PERIPH_ID2, _reserved13: [u8; 0x02], - #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id3: SSP_PERIPH_ID3, + ssp_periph_id3: SSP_PERIPH_ID3, _reserved14: [u8; 0x02], - #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id0: SSP_PCELL_ID0, + ssp_pcell_id0: SSP_PCELL_ID0, _reserved15: [u8; 0x02], - #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id1: SSP_PCELL_ID1, + ssp_pcell_id1: SSP_PCELL_ID1, _reserved16: [u8; 0x02], - #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id2: SSP_PCELL_ID2, + ssp_pcell_id2: SSP_PCELL_ID2, _reserved17: [u8; 0x02], + ssp_pcell_id3: SSP_PCELL_ID3, +} +impl RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr0(&self) -> &SSP_CR0 { + &self.ssp_cr0 + } + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr1(&self) -> &SSP_CR1 { + &self.ssp_cr1 + } + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + #[inline(always)] + pub const fn ssp_dr(&self) -> &SSP_DR { + &self.ssp_dr + } + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + #[inline(always)] + pub const fn ssp_sr(&self) -> &SSP_SR { + &self.ssp_sr + } + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + #[inline(always)] + pub const fn ssp_cpsr(&self) -> &SSP_CPSR { + &self.ssp_cpsr + } + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + #[inline(always)] + pub const fn ssp_imsc(&self) -> &SSP_IMSC { + &self.ssp_imsc + } + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + #[inline(always)] + pub const fn ssp_ris(&self) -> &SSP_RIS { + &self.ssp_ris + } + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + #[inline(always)] + pub const fn ssp_mis(&self) -> &SSP_MIS { + &self.ssp_mis + } + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + #[inline(always)] + pub const fn ssp_icr(&self) -> &SSP_ICR { + &self.ssp_icr + } + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + #[inline(always)] + pub const fn ssp_dmacr(&self) -> &SSP_DMACR { + &self.ssp_dmacr + } + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id0(&self) -> &SSP_PERIPH_ID0 { + &self.ssp_periph_id0 + } + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id1(&self) -> &SSP_PERIPH_ID1 { + &self.ssp_periph_id1 + } + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id2(&self) -> &SSP_PERIPH_ID2 { + &self.ssp_periph_id2 + } + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id3(&self) -> &SSP_PERIPH_ID3 { + &self.ssp_periph_id3 + } + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id0(&self) -> &SSP_PCELL_ID0 { + &self.ssp_pcell_id0 + } + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id1(&self) -> &SSP_PCELL_ID1 { + &self.ssp_pcell_id1 + } + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id2(&self) -> &SSP_PCELL_ID2 { + &self.ssp_pcell_id2 + } #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id3: SSP_PCELL_ID3, + #[inline(always)] + pub const fn ssp_pcell_id3(&self) -> &SSP_PCELL_ID3 { + &self.ssp_pcell_id3 + } } -#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr0`] module"] pub type SSP_CR0 = crate::Reg; #[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] pub mod ssp_cr0; -#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr1`] module"] pub type SSP_CR1 = crate::Reg; #[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] pub mod ssp_cr1; -#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dr`] module"] pub type SSP_DR = crate::Reg; #[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] pub mod ssp_dr; -#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_sr`] module"] pub type SSP_SR = crate::Reg; #[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] pub mod ssp_sr; -#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cpsr`] module"] pub type SSP_CPSR = crate::Reg; #[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] pub mod ssp_cpsr; -#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_imsc`] module"] pub type SSP_IMSC = crate::Reg; #[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] pub mod ssp_imsc; -#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_ris`] module"] pub type SSP_RIS = crate::Reg; #[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] pub mod ssp_ris; -#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_mis`] module"] pub type SSP_MIS = crate::Reg; #[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] pub mod ssp_mis; -#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_icr`] module"] pub type SSP_ICR = crate::Reg; #[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] pub mod ssp_icr; -#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dmacr`] module"] pub type SSP_DMACR = crate::Reg; #[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] pub mod ssp_dmacr; -#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id0`] module"] pub type SSP_PERIPH_ID0 = crate::Reg; #[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id0; -#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id1`] module"] pub type SSP_PERIPH_ID1 = crate::Reg; #[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id1; -#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id2`] module"] pub type SSP_PERIPH_ID2 = crate::Reg; #[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id2; -#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id3`] module"] pub type SSP_PERIPH_ID3 = crate::Reg; #[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id3; -#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id0`] module"] pub type SSP_PCELL_ID0 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id0; -#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id1`] module"] pub type SSP_PCELL_ID1 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id1; -#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id2`] module"] pub type SSP_PCELL_ID2 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id2; -#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id3`] module"] pub type SSP_PCELL_ID3 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_cpsr.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_cpsr.rs index 214d9da..2fa25a9 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_cpsr.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_cpsr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] pub type CPSDVSR_R = crate::FieldReader; #[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] -pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type CPSDVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] #[must_use] - pub fn cpsdvsr(&mut self) -> CPSDVSR_W { - CPSDVSR_W::new(self) + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_cr0.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_cr0.rs index 1f3740e..b3ee9c6 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_cr0.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_cr0.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `dss` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] pub type DSS_R = crate::FieldReader; #[doc = "Field `dss` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] -pub type DSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type DSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] pub type FRF_R = crate::FieldReader; #[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] -pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] pub type SPO_R = crate::BitReader; #[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] -pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPO_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] pub type SPH_R = crate::BitReader; #[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] -pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPH_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] @@ -56,35 +56,39 @@ impl W { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] #[must_use] - pub fn dss(&mut self) -> DSS_W { - DSS_W::new(self) + pub fn dss(&mut self) -> DSS_W { + DSS_W::new(self, 0) } #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] #[inline(always)] #[must_use] - pub fn frf(&mut self) -> FRF_W { - FRF_W::new(self) + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self, 4) } #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn spo(&mut self) -> SPO_W { - SPO_W::new(self) + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self, 6) } #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn sph(&mut self) -> SPH_W { - SPH_W::new(self) + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self, 6) } #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_cr1.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_cr1.rs index 69dbcbd..b115461 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_cr1.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_cr1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] pub type LBM_R = crate::BitReader; #[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] -pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LBM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] pub type SSE_R = crate::BitReader; #[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] -pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SSE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] pub type MS_R = crate::BitReader; #[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] -pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] pub type SOD_R = crate::BitReader; #[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] -pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SOD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] #[must_use] - pub fn lbm(&mut self) -> LBM_W { - LBM_W::new(self) + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self, 0) } #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] #[inline(always)] #[must_use] - pub fn sse(&mut self) -> SSE_W { - SSE_W::new(self) + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self, 1) } #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] #[inline(always)] #[must_use] - pub fn ms(&mut self) -> MS_W { - MS_W::new(self) + pub fn ms(&mut self) -> MS_W { + MS_W::new(self, 2) } #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] #[inline(always)] #[must_use] - pub fn sod(&mut self) -> SOD_W { - SOD_W::new(self) + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_dmacr.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_dmacr.rs index c20ae0f..d7fd182 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_dmacr.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_dmacr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub type RXDMAE_R = crate::BitReader; #[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] -pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub type TXDMAE_R = crate::BitReader; #[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] -pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W { - RXDMAE_W::new(self) + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self, 0) } #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W { - TXDMAE_W::new(self) + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_dr.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_dr.rs index 019ee7c..ad69481 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_dr.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_dr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub type DATA_R = crate::FieldReader; #[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] -pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W { - DATA_W::new(self) + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_icr.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_icr.rs index 9828eba..78a767d 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_icr.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_icr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] pub type RORIC_R = crate::BitReader; #[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] -pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] pub type RTIC_R = crate::BitReader; #[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] -pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIC_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] #[must_use] - pub fn roric(&mut self) -> RORIC_W { - RORIC_W::new(self) + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self, 0) } #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W { - RTIC_W::new(self) + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_imsc.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_imsc.rs index c628750..63738cd 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_imsc.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_imsc.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] pub type RORIM_R = crate::BitReader; #[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] -pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] pub type RTIM_R = crate::BitReader; #[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] -pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] pub type RXIM_R = crate::BitReader; #[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] -pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] pub type TXIM_R = crate::BitReader; #[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] -pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rorim(&mut self) -> RORIM_W { - RORIM_W::new(self) + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self, 0) } #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W { - RTIM_W::new(self) + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self, 1) } #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W { - RXIM_W::new(self) + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self, 2) } #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W { - TXIM_W::new(self) + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_mis.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_mis.rs index 358b1d4..1c50710 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_mis.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_mis.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id0.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id0.rs index 7210289..9b50e59 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id0.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id1.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id1.rs index 0953ee0..2e23cc7 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id1.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id2.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id2.rs index 5f0696d..1b5fb34 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id2.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id2.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id3.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id3.rs index c532f5c..6642d55 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id3.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_pcell_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_periph_id0.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_periph_id0.rs index 98a341a..c69007a 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_periph_id0.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_periph_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_periph_id1.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_periph_id1.rs index 0c53a92..71907fb 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_periph_id1.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_periph_id1.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_periph_id2.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_periph_id2.rs index 1b49543..2efc3ae 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_periph_id2.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_periph_id2.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_periph_id3.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_periph_id3.rs index 8f18a77..c2f7b1c 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_periph_id3.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_periph_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_ris.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_ris.rs index 46ca4be..27dee48 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_ris.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_ris.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi1/ssp_sr.rs b/jh7110-vf2-13b-pac/src/spi1/ssp_sr.rs index b25ffb6..bf388f5 100644 --- a/jh7110-vf2-13b-pac/src/spi1/ssp_sr.rs +++ b/jh7110-vf2-13b-pac/src/spi1/ssp_sr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2.rs b/jh7110-vf2-13b-pac/src/spi2.rs index e1d7fdc..6e69208 100644 --- a/jh7110-vf2-13b-pac/src/spi2.rs +++ b/jh7110-vf2-13b-pac/src/spi2.rs @@ -1,146 +1,220 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] - pub ssp_cr0: SSP_CR0, + ssp_cr0: SSP_CR0, _reserved1: [u8; 0x02], - #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] - pub ssp_cr1: SSP_CR1, + ssp_cr1: SSP_CR1, _reserved2: [u8; 0x02], - #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] - pub ssp_dr: SSP_DR, + ssp_dr: SSP_DR, _reserved3: [u8; 0x02], - #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] - pub ssp_sr: SSP_SR, + ssp_sr: SSP_SR, _reserved4: [u8; 0x02], - #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] - pub ssp_cpsr: SSP_CPSR, + ssp_cpsr: SSP_CPSR, _reserved5: [u8; 0x02], - #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] - pub ssp_imsc: SSP_IMSC, + ssp_imsc: SSP_IMSC, _reserved6: [u8; 0x02], - #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] - pub ssp_ris: SSP_RIS, + ssp_ris: SSP_RIS, _reserved7: [u8; 0x02], - #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] - pub ssp_mis: SSP_MIS, + ssp_mis: SSP_MIS, _reserved8: [u8; 0x02], - #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] - pub ssp_icr: SSP_ICR, + ssp_icr: SSP_ICR, _reserved9: [u8; 0x02], - #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] - pub ssp_dmacr: SSP_DMACR, + ssp_dmacr: SSP_DMACR, _reserved10: [u8; 0x0fba], - #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id0: SSP_PERIPH_ID0, + ssp_periph_id0: SSP_PERIPH_ID0, _reserved11: [u8; 0x02], - #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id1: SSP_PERIPH_ID1, + ssp_periph_id1: SSP_PERIPH_ID1, _reserved12: [u8; 0x02], - #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id2: SSP_PERIPH_ID2, + ssp_periph_id2: SSP_PERIPH_ID2, _reserved13: [u8; 0x02], - #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id3: SSP_PERIPH_ID3, + ssp_periph_id3: SSP_PERIPH_ID3, _reserved14: [u8; 0x02], - #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id0: SSP_PCELL_ID0, + ssp_pcell_id0: SSP_PCELL_ID0, _reserved15: [u8; 0x02], - #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id1: SSP_PCELL_ID1, + ssp_pcell_id1: SSP_PCELL_ID1, _reserved16: [u8; 0x02], - #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id2: SSP_PCELL_ID2, + ssp_pcell_id2: SSP_PCELL_ID2, _reserved17: [u8; 0x02], + ssp_pcell_id3: SSP_PCELL_ID3, +} +impl RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr0(&self) -> &SSP_CR0 { + &self.ssp_cr0 + } + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr1(&self) -> &SSP_CR1 { + &self.ssp_cr1 + } + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + #[inline(always)] + pub const fn ssp_dr(&self) -> &SSP_DR { + &self.ssp_dr + } + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + #[inline(always)] + pub const fn ssp_sr(&self) -> &SSP_SR { + &self.ssp_sr + } + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + #[inline(always)] + pub const fn ssp_cpsr(&self) -> &SSP_CPSR { + &self.ssp_cpsr + } + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + #[inline(always)] + pub const fn ssp_imsc(&self) -> &SSP_IMSC { + &self.ssp_imsc + } + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + #[inline(always)] + pub const fn ssp_ris(&self) -> &SSP_RIS { + &self.ssp_ris + } + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + #[inline(always)] + pub const fn ssp_mis(&self) -> &SSP_MIS { + &self.ssp_mis + } + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + #[inline(always)] + pub const fn ssp_icr(&self) -> &SSP_ICR { + &self.ssp_icr + } + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + #[inline(always)] + pub const fn ssp_dmacr(&self) -> &SSP_DMACR { + &self.ssp_dmacr + } + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id0(&self) -> &SSP_PERIPH_ID0 { + &self.ssp_periph_id0 + } + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id1(&self) -> &SSP_PERIPH_ID1 { + &self.ssp_periph_id1 + } + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id2(&self) -> &SSP_PERIPH_ID2 { + &self.ssp_periph_id2 + } + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id3(&self) -> &SSP_PERIPH_ID3 { + &self.ssp_periph_id3 + } + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id0(&self) -> &SSP_PCELL_ID0 { + &self.ssp_pcell_id0 + } + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id1(&self) -> &SSP_PCELL_ID1 { + &self.ssp_pcell_id1 + } + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id2(&self) -> &SSP_PCELL_ID2 { + &self.ssp_pcell_id2 + } #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id3: SSP_PCELL_ID3, + #[inline(always)] + pub const fn ssp_pcell_id3(&self) -> &SSP_PCELL_ID3 { + &self.ssp_pcell_id3 + } } -#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr0`] module"] pub type SSP_CR0 = crate::Reg; #[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] pub mod ssp_cr0; -#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr1`] module"] pub type SSP_CR1 = crate::Reg; #[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] pub mod ssp_cr1; -#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dr`] module"] pub type SSP_DR = crate::Reg; #[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] pub mod ssp_dr; -#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_sr`] module"] pub type SSP_SR = crate::Reg; #[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] pub mod ssp_sr; -#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cpsr`] module"] pub type SSP_CPSR = crate::Reg; #[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] pub mod ssp_cpsr; -#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_imsc`] module"] pub type SSP_IMSC = crate::Reg; #[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] pub mod ssp_imsc; -#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_ris`] module"] pub type SSP_RIS = crate::Reg; #[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] pub mod ssp_ris; -#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_mis`] module"] pub type SSP_MIS = crate::Reg; #[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] pub mod ssp_mis; -#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_icr`] module"] pub type SSP_ICR = crate::Reg; #[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] pub mod ssp_icr; -#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dmacr`] module"] pub type SSP_DMACR = crate::Reg; #[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] pub mod ssp_dmacr; -#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id0`] module"] pub type SSP_PERIPH_ID0 = crate::Reg; #[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id0; -#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id1`] module"] pub type SSP_PERIPH_ID1 = crate::Reg; #[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id1; -#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id2`] module"] pub type SSP_PERIPH_ID2 = crate::Reg; #[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id2; -#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id3`] module"] pub type SSP_PERIPH_ID3 = crate::Reg; #[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id3; -#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id0`] module"] pub type SSP_PCELL_ID0 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id0; -#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id1`] module"] pub type SSP_PCELL_ID1 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id1; -#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id2`] module"] pub type SSP_PCELL_ID2 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id2; -#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id3`] module"] pub type SSP_PCELL_ID3 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_cpsr.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_cpsr.rs index 214d9da..2fa25a9 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_cpsr.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_cpsr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] pub type CPSDVSR_R = crate::FieldReader; #[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] -pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type CPSDVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] #[must_use] - pub fn cpsdvsr(&mut self) -> CPSDVSR_W { - CPSDVSR_W::new(self) + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_cr0.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_cr0.rs index 1f3740e..b3ee9c6 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_cr0.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_cr0.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `dss` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] pub type DSS_R = crate::FieldReader; #[doc = "Field `dss` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] -pub type DSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type DSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] pub type FRF_R = crate::FieldReader; #[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] -pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] pub type SPO_R = crate::BitReader; #[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] -pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPO_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] pub type SPH_R = crate::BitReader; #[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] -pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPH_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] @@ -56,35 +56,39 @@ impl W { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] #[must_use] - pub fn dss(&mut self) -> DSS_W { - DSS_W::new(self) + pub fn dss(&mut self) -> DSS_W { + DSS_W::new(self, 0) } #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] #[inline(always)] #[must_use] - pub fn frf(&mut self) -> FRF_W { - FRF_W::new(self) + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self, 4) } #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn spo(&mut self) -> SPO_W { - SPO_W::new(self) + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self, 6) } #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn sph(&mut self) -> SPH_W { - SPH_W::new(self) + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self, 6) } #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_cr1.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_cr1.rs index 69dbcbd..b115461 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_cr1.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_cr1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] pub type LBM_R = crate::BitReader; #[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] -pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LBM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] pub type SSE_R = crate::BitReader; #[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] -pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SSE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] pub type MS_R = crate::BitReader; #[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] -pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] pub type SOD_R = crate::BitReader; #[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] -pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SOD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] #[must_use] - pub fn lbm(&mut self) -> LBM_W { - LBM_W::new(self) + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self, 0) } #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] #[inline(always)] #[must_use] - pub fn sse(&mut self) -> SSE_W { - SSE_W::new(self) + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self, 1) } #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] #[inline(always)] #[must_use] - pub fn ms(&mut self) -> MS_W { - MS_W::new(self) + pub fn ms(&mut self) -> MS_W { + MS_W::new(self, 2) } #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] #[inline(always)] #[must_use] - pub fn sod(&mut self) -> SOD_W { - SOD_W::new(self) + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_dmacr.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_dmacr.rs index c20ae0f..d7fd182 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_dmacr.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_dmacr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub type RXDMAE_R = crate::BitReader; #[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] -pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub type TXDMAE_R = crate::BitReader; #[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] -pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W { - RXDMAE_W::new(self) + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self, 0) } #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W { - TXDMAE_W::new(self) + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_dr.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_dr.rs index 019ee7c..ad69481 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_dr.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_dr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub type DATA_R = crate::FieldReader; #[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] -pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W { - DATA_W::new(self) + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_icr.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_icr.rs index 9828eba..78a767d 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_icr.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_icr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] pub type RORIC_R = crate::BitReader; #[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] -pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] pub type RTIC_R = crate::BitReader; #[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] -pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIC_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] #[must_use] - pub fn roric(&mut self) -> RORIC_W { - RORIC_W::new(self) + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self, 0) } #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W { - RTIC_W::new(self) + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_imsc.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_imsc.rs index c628750..63738cd 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_imsc.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_imsc.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] pub type RORIM_R = crate::BitReader; #[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] -pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] pub type RTIM_R = crate::BitReader; #[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] -pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] pub type RXIM_R = crate::BitReader; #[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] -pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] pub type TXIM_R = crate::BitReader; #[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] -pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rorim(&mut self) -> RORIM_W { - RORIM_W::new(self) + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self, 0) } #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W { - RTIM_W::new(self) + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self, 1) } #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W { - RXIM_W::new(self) + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self, 2) } #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W { - TXIM_W::new(self) + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_mis.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_mis.rs index 358b1d4..1c50710 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_mis.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_mis.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id0.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id0.rs index 7210289..9b50e59 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id0.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id1.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id1.rs index 0953ee0..2e23cc7 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id1.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id2.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id2.rs index 5f0696d..1b5fb34 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id2.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id2.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id3.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id3.rs index c532f5c..6642d55 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id3.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_pcell_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_periph_id0.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_periph_id0.rs index 98a341a..c69007a 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_periph_id0.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_periph_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_periph_id1.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_periph_id1.rs index 0c53a92..71907fb 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_periph_id1.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_periph_id1.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_periph_id2.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_periph_id2.rs index 1b49543..2efc3ae 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_periph_id2.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_periph_id2.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_periph_id3.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_periph_id3.rs index 8f18a77..c2f7b1c 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_periph_id3.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_periph_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_ris.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_ris.rs index 46ca4be..27dee48 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_ris.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_ris.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi2/ssp_sr.rs b/jh7110-vf2-13b-pac/src/spi2/ssp_sr.rs index b25ffb6..bf388f5 100644 --- a/jh7110-vf2-13b-pac/src/spi2/ssp_sr.rs +++ b/jh7110-vf2-13b-pac/src/spi2/ssp_sr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3.rs b/jh7110-vf2-13b-pac/src/spi3.rs index e1d7fdc..6e69208 100644 --- a/jh7110-vf2-13b-pac/src/spi3.rs +++ b/jh7110-vf2-13b-pac/src/spi3.rs @@ -1,146 +1,220 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] - pub ssp_cr0: SSP_CR0, + ssp_cr0: SSP_CR0, _reserved1: [u8; 0x02], - #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] - pub ssp_cr1: SSP_CR1, + ssp_cr1: SSP_CR1, _reserved2: [u8; 0x02], - #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] - pub ssp_dr: SSP_DR, + ssp_dr: SSP_DR, _reserved3: [u8; 0x02], - #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] - pub ssp_sr: SSP_SR, + ssp_sr: SSP_SR, _reserved4: [u8; 0x02], - #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] - pub ssp_cpsr: SSP_CPSR, + ssp_cpsr: SSP_CPSR, _reserved5: [u8; 0x02], - #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] - pub ssp_imsc: SSP_IMSC, + ssp_imsc: SSP_IMSC, _reserved6: [u8; 0x02], - #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] - pub ssp_ris: SSP_RIS, + ssp_ris: SSP_RIS, _reserved7: [u8; 0x02], - #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] - pub ssp_mis: SSP_MIS, + ssp_mis: SSP_MIS, _reserved8: [u8; 0x02], - #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] - pub ssp_icr: SSP_ICR, + ssp_icr: SSP_ICR, _reserved9: [u8; 0x02], - #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] - pub ssp_dmacr: SSP_DMACR, + ssp_dmacr: SSP_DMACR, _reserved10: [u8; 0x0fba], - #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id0: SSP_PERIPH_ID0, + ssp_periph_id0: SSP_PERIPH_ID0, _reserved11: [u8; 0x02], - #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id1: SSP_PERIPH_ID1, + ssp_periph_id1: SSP_PERIPH_ID1, _reserved12: [u8; 0x02], - #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id2: SSP_PERIPH_ID2, + ssp_periph_id2: SSP_PERIPH_ID2, _reserved13: [u8; 0x02], - #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id3: SSP_PERIPH_ID3, + ssp_periph_id3: SSP_PERIPH_ID3, _reserved14: [u8; 0x02], - #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id0: SSP_PCELL_ID0, + ssp_pcell_id0: SSP_PCELL_ID0, _reserved15: [u8; 0x02], - #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id1: SSP_PCELL_ID1, + ssp_pcell_id1: SSP_PCELL_ID1, _reserved16: [u8; 0x02], - #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id2: SSP_PCELL_ID2, + ssp_pcell_id2: SSP_PCELL_ID2, _reserved17: [u8; 0x02], + ssp_pcell_id3: SSP_PCELL_ID3, +} +impl RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr0(&self) -> &SSP_CR0 { + &self.ssp_cr0 + } + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr1(&self) -> &SSP_CR1 { + &self.ssp_cr1 + } + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + #[inline(always)] + pub const fn ssp_dr(&self) -> &SSP_DR { + &self.ssp_dr + } + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + #[inline(always)] + pub const fn ssp_sr(&self) -> &SSP_SR { + &self.ssp_sr + } + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + #[inline(always)] + pub const fn ssp_cpsr(&self) -> &SSP_CPSR { + &self.ssp_cpsr + } + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + #[inline(always)] + pub const fn ssp_imsc(&self) -> &SSP_IMSC { + &self.ssp_imsc + } + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + #[inline(always)] + pub const fn ssp_ris(&self) -> &SSP_RIS { + &self.ssp_ris + } + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + #[inline(always)] + pub const fn ssp_mis(&self) -> &SSP_MIS { + &self.ssp_mis + } + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + #[inline(always)] + pub const fn ssp_icr(&self) -> &SSP_ICR { + &self.ssp_icr + } + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + #[inline(always)] + pub const fn ssp_dmacr(&self) -> &SSP_DMACR { + &self.ssp_dmacr + } + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id0(&self) -> &SSP_PERIPH_ID0 { + &self.ssp_periph_id0 + } + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id1(&self) -> &SSP_PERIPH_ID1 { + &self.ssp_periph_id1 + } + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id2(&self) -> &SSP_PERIPH_ID2 { + &self.ssp_periph_id2 + } + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id3(&self) -> &SSP_PERIPH_ID3 { + &self.ssp_periph_id3 + } + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id0(&self) -> &SSP_PCELL_ID0 { + &self.ssp_pcell_id0 + } + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id1(&self) -> &SSP_PCELL_ID1 { + &self.ssp_pcell_id1 + } + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id2(&self) -> &SSP_PCELL_ID2 { + &self.ssp_pcell_id2 + } #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id3: SSP_PCELL_ID3, + #[inline(always)] + pub const fn ssp_pcell_id3(&self) -> &SSP_PCELL_ID3 { + &self.ssp_pcell_id3 + } } -#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr0`] module"] pub type SSP_CR0 = crate::Reg; #[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] pub mod ssp_cr0; -#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr1`] module"] pub type SSP_CR1 = crate::Reg; #[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] pub mod ssp_cr1; -#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dr`] module"] pub type SSP_DR = crate::Reg; #[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] pub mod ssp_dr; -#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_sr`] module"] pub type SSP_SR = crate::Reg; #[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] pub mod ssp_sr; -#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cpsr`] module"] pub type SSP_CPSR = crate::Reg; #[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] pub mod ssp_cpsr; -#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_imsc`] module"] pub type SSP_IMSC = crate::Reg; #[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] pub mod ssp_imsc; -#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_ris`] module"] pub type SSP_RIS = crate::Reg; #[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] pub mod ssp_ris; -#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_mis`] module"] pub type SSP_MIS = crate::Reg; #[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] pub mod ssp_mis; -#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_icr`] module"] pub type SSP_ICR = crate::Reg; #[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] pub mod ssp_icr; -#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dmacr`] module"] pub type SSP_DMACR = crate::Reg; #[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] pub mod ssp_dmacr; -#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id0`] module"] pub type SSP_PERIPH_ID0 = crate::Reg; #[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id0; -#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id1`] module"] pub type SSP_PERIPH_ID1 = crate::Reg; #[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id1; -#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id2`] module"] pub type SSP_PERIPH_ID2 = crate::Reg; #[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id2; -#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id3`] module"] pub type SSP_PERIPH_ID3 = crate::Reg; #[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id3; -#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id0`] module"] pub type SSP_PCELL_ID0 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id0; -#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id1`] module"] pub type SSP_PCELL_ID1 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id1; -#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id2`] module"] pub type SSP_PCELL_ID2 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id2; -#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id3`] module"] pub type SSP_PCELL_ID3 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_cpsr.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_cpsr.rs index 214d9da..2fa25a9 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_cpsr.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_cpsr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] pub type CPSDVSR_R = crate::FieldReader; #[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] -pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type CPSDVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] #[must_use] - pub fn cpsdvsr(&mut self) -> CPSDVSR_W { - CPSDVSR_W::new(self) + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_cr0.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_cr0.rs index 1f3740e..b3ee9c6 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_cr0.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_cr0.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `dss` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] pub type DSS_R = crate::FieldReader; #[doc = "Field `dss` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] -pub type DSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type DSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] pub type FRF_R = crate::FieldReader; #[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] -pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] pub type SPO_R = crate::BitReader; #[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] -pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPO_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] pub type SPH_R = crate::BitReader; #[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] -pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPH_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] @@ -56,35 +56,39 @@ impl W { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] #[must_use] - pub fn dss(&mut self) -> DSS_W { - DSS_W::new(self) + pub fn dss(&mut self) -> DSS_W { + DSS_W::new(self, 0) } #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] #[inline(always)] #[must_use] - pub fn frf(&mut self) -> FRF_W { - FRF_W::new(self) + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self, 4) } #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn spo(&mut self) -> SPO_W { - SPO_W::new(self) + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self, 6) } #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn sph(&mut self) -> SPH_W { - SPH_W::new(self) + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self, 6) } #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_cr1.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_cr1.rs index 69dbcbd..b115461 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_cr1.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_cr1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] pub type LBM_R = crate::BitReader; #[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] -pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LBM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] pub type SSE_R = crate::BitReader; #[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] -pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SSE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] pub type MS_R = crate::BitReader; #[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] -pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] pub type SOD_R = crate::BitReader; #[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] -pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SOD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] #[must_use] - pub fn lbm(&mut self) -> LBM_W { - LBM_W::new(self) + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self, 0) } #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] #[inline(always)] #[must_use] - pub fn sse(&mut self) -> SSE_W { - SSE_W::new(self) + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self, 1) } #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] #[inline(always)] #[must_use] - pub fn ms(&mut self) -> MS_W { - MS_W::new(self) + pub fn ms(&mut self) -> MS_W { + MS_W::new(self, 2) } #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] #[inline(always)] #[must_use] - pub fn sod(&mut self) -> SOD_W { - SOD_W::new(self) + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_dmacr.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_dmacr.rs index c20ae0f..d7fd182 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_dmacr.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_dmacr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub type RXDMAE_R = crate::BitReader; #[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] -pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub type TXDMAE_R = crate::BitReader; #[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] -pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W { - RXDMAE_W::new(self) + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self, 0) } #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W { - TXDMAE_W::new(self) + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_dr.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_dr.rs index 019ee7c..ad69481 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_dr.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_dr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub type DATA_R = crate::FieldReader; #[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] -pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W { - DATA_W::new(self) + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_icr.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_icr.rs index 9828eba..78a767d 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_icr.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_icr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] pub type RORIC_R = crate::BitReader; #[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] -pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] pub type RTIC_R = crate::BitReader; #[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] -pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIC_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] #[must_use] - pub fn roric(&mut self) -> RORIC_W { - RORIC_W::new(self) + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self, 0) } #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W { - RTIC_W::new(self) + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_imsc.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_imsc.rs index c628750..63738cd 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_imsc.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_imsc.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] pub type RORIM_R = crate::BitReader; #[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] -pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] pub type RTIM_R = crate::BitReader; #[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] -pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] pub type RXIM_R = crate::BitReader; #[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] -pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] pub type TXIM_R = crate::BitReader; #[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] -pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rorim(&mut self) -> RORIM_W { - RORIM_W::new(self) + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self, 0) } #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W { - RTIM_W::new(self) + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self, 1) } #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W { - RXIM_W::new(self) + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self, 2) } #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W { - TXIM_W::new(self) + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_mis.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_mis.rs index 358b1d4..1c50710 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_mis.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_mis.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id0.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id0.rs index 7210289..9b50e59 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id0.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id1.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id1.rs index 0953ee0..2e23cc7 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id1.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id2.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id2.rs index 5f0696d..1b5fb34 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id2.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id2.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id3.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id3.rs index c532f5c..6642d55 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id3.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_pcell_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_periph_id0.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_periph_id0.rs index 98a341a..c69007a 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_periph_id0.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_periph_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_periph_id1.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_periph_id1.rs index 0c53a92..71907fb 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_periph_id1.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_periph_id1.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_periph_id2.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_periph_id2.rs index 1b49543..2efc3ae 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_periph_id2.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_periph_id2.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_periph_id3.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_periph_id3.rs index 8f18a77..c2f7b1c 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_periph_id3.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_periph_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_ris.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_ris.rs index 46ca4be..27dee48 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_ris.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_ris.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi3/ssp_sr.rs b/jh7110-vf2-13b-pac/src/spi3/ssp_sr.rs index b25ffb6..bf388f5 100644 --- a/jh7110-vf2-13b-pac/src/spi3/ssp_sr.rs +++ b/jh7110-vf2-13b-pac/src/spi3/ssp_sr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4.rs b/jh7110-vf2-13b-pac/src/spi4.rs index e1d7fdc..6e69208 100644 --- a/jh7110-vf2-13b-pac/src/spi4.rs +++ b/jh7110-vf2-13b-pac/src/spi4.rs @@ -1,146 +1,220 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] - pub ssp_cr0: SSP_CR0, + ssp_cr0: SSP_CR0, _reserved1: [u8; 0x02], - #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] - pub ssp_cr1: SSP_CR1, + ssp_cr1: SSP_CR1, _reserved2: [u8; 0x02], - #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] - pub ssp_dr: SSP_DR, + ssp_dr: SSP_DR, _reserved3: [u8; 0x02], - #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] - pub ssp_sr: SSP_SR, + ssp_sr: SSP_SR, _reserved4: [u8; 0x02], - #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] - pub ssp_cpsr: SSP_CPSR, + ssp_cpsr: SSP_CPSR, _reserved5: [u8; 0x02], - #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] - pub ssp_imsc: SSP_IMSC, + ssp_imsc: SSP_IMSC, _reserved6: [u8; 0x02], - #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] - pub ssp_ris: SSP_RIS, + ssp_ris: SSP_RIS, _reserved7: [u8; 0x02], - #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] - pub ssp_mis: SSP_MIS, + ssp_mis: SSP_MIS, _reserved8: [u8; 0x02], - #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] - pub ssp_icr: SSP_ICR, + ssp_icr: SSP_ICR, _reserved9: [u8; 0x02], - #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] - pub ssp_dmacr: SSP_DMACR, + ssp_dmacr: SSP_DMACR, _reserved10: [u8; 0x0fba], - #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id0: SSP_PERIPH_ID0, + ssp_periph_id0: SSP_PERIPH_ID0, _reserved11: [u8; 0x02], - #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id1: SSP_PERIPH_ID1, + ssp_periph_id1: SSP_PERIPH_ID1, _reserved12: [u8; 0x02], - #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id2: SSP_PERIPH_ID2, + ssp_periph_id2: SSP_PERIPH_ID2, _reserved13: [u8; 0x02], - #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id3: SSP_PERIPH_ID3, + ssp_periph_id3: SSP_PERIPH_ID3, _reserved14: [u8; 0x02], - #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id0: SSP_PCELL_ID0, + ssp_pcell_id0: SSP_PCELL_ID0, _reserved15: [u8; 0x02], - #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id1: SSP_PCELL_ID1, + ssp_pcell_id1: SSP_PCELL_ID1, _reserved16: [u8; 0x02], - #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id2: SSP_PCELL_ID2, + ssp_pcell_id2: SSP_PCELL_ID2, _reserved17: [u8; 0x02], + ssp_pcell_id3: SSP_PCELL_ID3, +} +impl RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr0(&self) -> &SSP_CR0 { + &self.ssp_cr0 + } + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr1(&self) -> &SSP_CR1 { + &self.ssp_cr1 + } + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + #[inline(always)] + pub const fn ssp_dr(&self) -> &SSP_DR { + &self.ssp_dr + } + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + #[inline(always)] + pub const fn ssp_sr(&self) -> &SSP_SR { + &self.ssp_sr + } + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + #[inline(always)] + pub const fn ssp_cpsr(&self) -> &SSP_CPSR { + &self.ssp_cpsr + } + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + #[inline(always)] + pub const fn ssp_imsc(&self) -> &SSP_IMSC { + &self.ssp_imsc + } + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + #[inline(always)] + pub const fn ssp_ris(&self) -> &SSP_RIS { + &self.ssp_ris + } + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + #[inline(always)] + pub const fn ssp_mis(&self) -> &SSP_MIS { + &self.ssp_mis + } + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + #[inline(always)] + pub const fn ssp_icr(&self) -> &SSP_ICR { + &self.ssp_icr + } + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + #[inline(always)] + pub const fn ssp_dmacr(&self) -> &SSP_DMACR { + &self.ssp_dmacr + } + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id0(&self) -> &SSP_PERIPH_ID0 { + &self.ssp_periph_id0 + } + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id1(&self) -> &SSP_PERIPH_ID1 { + &self.ssp_periph_id1 + } + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id2(&self) -> &SSP_PERIPH_ID2 { + &self.ssp_periph_id2 + } + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id3(&self) -> &SSP_PERIPH_ID3 { + &self.ssp_periph_id3 + } + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id0(&self) -> &SSP_PCELL_ID0 { + &self.ssp_pcell_id0 + } + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id1(&self) -> &SSP_PCELL_ID1 { + &self.ssp_pcell_id1 + } + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id2(&self) -> &SSP_PCELL_ID2 { + &self.ssp_pcell_id2 + } #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id3: SSP_PCELL_ID3, + #[inline(always)] + pub const fn ssp_pcell_id3(&self) -> &SSP_PCELL_ID3 { + &self.ssp_pcell_id3 + } } -#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr0`] module"] pub type SSP_CR0 = crate::Reg; #[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] pub mod ssp_cr0; -#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr1`] module"] pub type SSP_CR1 = crate::Reg; #[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] pub mod ssp_cr1; -#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dr`] module"] pub type SSP_DR = crate::Reg; #[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] pub mod ssp_dr; -#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_sr`] module"] pub type SSP_SR = crate::Reg; #[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] pub mod ssp_sr; -#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cpsr`] module"] pub type SSP_CPSR = crate::Reg; #[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] pub mod ssp_cpsr; -#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_imsc`] module"] pub type SSP_IMSC = crate::Reg; #[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] pub mod ssp_imsc; -#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_ris`] module"] pub type SSP_RIS = crate::Reg; #[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] pub mod ssp_ris; -#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_mis`] module"] pub type SSP_MIS = crate::Reg; #[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] pub mod ssp_mis; -#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_icr`] module"] pub type SSP_ICR = crate::Reg; #[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] pub mod ssp_icr; -#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dmacr`] module"] pub type SSP_DMACR = crate::Reg; #[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] pub mod ssp_dmacr; -#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id0`] module"] pub type SSP_PERIPH_ID0 = crate::Reg; #[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id0; -#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id1`] module"] pub type SSP_PERIPH_ID1 = crate::Reg; #[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id1; -#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id2`] module"] pub type SSP_PERIPH_ID2 = crate::Reg; #[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id2; -#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id3`] module"] pub type SSP_PERIPH_ID3 = crate::Reg; #[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id3; -#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id0`] module"] pub type SSP_PCELL_ID0 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id0; -#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id1`] module"] pub type SSP_PCELL_ID1 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id1; -#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id2`] module"] pub type SSP_PCELL_ID2 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id2; -#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id3`] module"] pub type SSP_PCELL_ID3 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_cpsr.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_cpsr.rs index 214d9da..2fa25a9 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_cpsr.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_cpsr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] pub type CPSDVSR_R = crate::FieldReader; #[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] -pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type CPSDVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] #[must_use] - pub fn cpsdvsr(&mut self) -> CPSDVSR_W { - CPSDVSR_W::new(self) + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_cr0.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_cr0.rs index 1f3740e..b3ee9c6 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_cr0.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_cr0.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `dss` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] pub type DSS_R = crate::FieldReader; #[doc = "Field `dss` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] -pub type DSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type DSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] pub type FRF_R = crate::FieldReader; #[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] -pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] pub type SPO_R = crate::BitReader; #[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] -pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPO_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] pub type SPH_R = crate::BitReader; #[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] -pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPH_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] @@ -56,35 +56,39 @@ impl W { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] #[must_use] - pub fn dss(&mut self) -> DSS_W { - DSS_W::new(self) + pub fn dss(&mut self) -> DSS_W { + DSS_W::new(self, 0) } #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] #[inline(always)] #[must_use] - pub fn frf(&mut self) -> FRF_W { - FRF_W::new(self) + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self, 4) } #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn spo(&mut self) -> SPO_W { - SPO_W::new(self) + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self, 6) } #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn sph(&mut self) -> SPH_W { - SPH_W::new(self) + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self, 6) } #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_cr1.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_cr1.rs index 69dbcbd..b115461 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_cr1.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_cr1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] pub type LBM_R = crate::BitReader; #[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] -pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LBM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] pub type SSE_R = crate::BitReader; #[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] -pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SSE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] pub type MS_R = crate::BitReader; #[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] -pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] pub type SOD_R = crate::BitReader; #[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] -pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SOD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] #[must_use] - pub fn lbm(&mut self) -> LBM_W { - LBM_W::new(self) + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self, 0) } #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] #[inline(always)] #[must_use] - pub fn sse(&mut self) -> SSE_W { - SSE_W::new(self) + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self, 1) } #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] #[inline(always)] #[must_use] - pub fn ms(&mut self) -> MS_W { - MS_W::new(self) + pub fn ms(&mut self) -> MS_W { + MS_W::new(self, 2) } #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] #[inline(always)] #[must_use] - pub fn sod(&mut self) -> SOD_W { - SOD_W::new(self) + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_dmacr.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_dmacr.rs index c20ae0f..d7fd182 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_dmacr.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_dmacr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub type RXDMAE_R = crate::BitReader; #[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] -pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub type TXDMAE_R = crate::BitReader; #[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] -pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W { - RXDMAE_W::new(self) + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self, 0) } #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W { - TXDMAE_W::new(self) + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_dr.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_dr.rs index 019ee7c..ad69481 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_dr.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_dr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub type DATA_R = crate::FieldReader; #[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] -pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W { - DATA_W::new(self) + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_icr.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_icr.rs index 9828eba..78a767d 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_icr.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_icr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] pub type RORIC_R = crate::BitReader; #[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] -pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] pub type RTIC_R = crate::BitReader; #[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] -pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIC_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] #[must_use] - pub fn roric(&mut self) -> RORIC_W { - RORIC_W::new(self) + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self, 0) } #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W { - RTIC_W::new(self) + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_imsc.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_imsc.rs index c628750..63738cd 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_imsc.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_imsc.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] pub type RORIM_R = crate::BitReader; #[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] -pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] pub type RTIM_R = crate::BitReader; #[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] -pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] pub type RXIM_R = crate::BitReader; #[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] -pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] pub type TXIM_R = crate::BitReader; #[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] -pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rorim(&mut self) -> RORIM_W { - RORIM_W::new(self) + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self, 0) } #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W { - RTIM_W::new(self) + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self, 1) } #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W { - RXIM_W::new(self) + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self, 2) } #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W { - TXIM_W::new(self) + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_mis.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_mis.rs index 358b1d4..1c50710 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_mis.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_mis.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id0.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id0.rs index 7210289..9b50e59 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id0.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id1.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id1.rs index 0953ee0..2e23cc7 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id1.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id2.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id2.rs index 5f0696d..1b5fb34 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id2.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id2.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id3.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id3.rs index c532f5c..6642d55 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id3.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_pcell_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_periph_id0.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_periph_id0.rs index 98a341a..c69007a 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_periph_id0.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_periph_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_periph_id1.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_periph_id1.rs index 0c53a92..71907fb 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_periph_id1.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_periph_id1.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_periph_id2.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_periph_id2.rs index 1b49543..2efc3ae 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_periph_id2.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_periph_id2.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_periph_id3.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_periph_id3.rs index 8f18a77..c2f7b1c 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_periph_id3.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_periph_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_ris.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_ris.rs index 46ca4be..27dee48 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_ris.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_ris.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi4/ssp_sr.rs b/jh7110-vf2-13b-pac/src/spi4/ssp_sr.rs index b25ffb6..bf388f5 100644 --- a/jh7110-vf2-13b-pac/src/spi4/ssp_sr.rs +++ b/jh7110-vf2-13b-pac/src/spi4/ssp_sr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5.rs b/jh7110-vf2-13b-pac/src/spi5.rs index e1d7fdc..6e69208 100644 --- a/jh7110-vf2-13b-pac/src/spi5.rs +++ b/jh7110-vf2-13b-pac/src/spi5.rs @@ -1,146 +1,220 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] - pub ssp_cr0: SSP_CR0, + ssp_cr0: SSP_CR0, _reserved1: [u8; 0x02], - #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] - pub ssp_cr1: SSP_CR1, + ssp_cr1: SSP_CR1, _reserved2: [u8; 0x02], - #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] - pub ssp_dr: SSP_DR, + ssp_dr: SSP_DR, _reserved3: [u8; 0x02], - #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] - pub ssp_sr: SSP_SR, + ssp_sr: SSP_SR, _reserved4: [u8; 0x02], - #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] - pub ssp_cpsr: SSP_CPSR, + ssp_cpsr: SSP_CPSR, _reserved5: [u8; 0x02], - #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] - pub ssp_imsc: SSP_IMSC, + ssp_imsc: SSP_IMSC, _reserved6: [u8; 0x02], - #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] - pub ssp_ris: SSP_RIS, + ssp_ris: SSP_RIS, _reserved7: [u8; 0x02], - #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] - pub ssp_mis: SSP_MIS, + ssp_mis: SSP_MIS, _reserved8: [u8; 0x02], - #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] - pub ssp_icr: SSP_ICR, + ssp_icr: SSP_ICR, _reserved9: [u8; 0x02], - #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] - pub ssp_dmacr: SSP_DMACR, + ssp_dmacr: SSP_DMACR, _reserved10: [u8; 0x0fba], - #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id0: SSP_PERIPH_ID0, + ssp_periph_id0: SSP_PERIPH_ID0, _reserved11: [u8; 0x02], - #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id1: SSP_PERIPH_ID1, + ssp_periph_id1: SSP_PERIPH_ID1, _reserved12: [u8; 0x02], - #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id2: SSP_PERIPH_ID2, + ssp_periph_id2: SSP_PERIPH_ID2, _reserved13: [u8; 0x02], - #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id3: SSP_PERIPH_ID3, + ssp_periph_id3: SSP_PERIPH_ID3, _reserved14: [u8; 0x02], - #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id0: SSP_PCELL_ID0, + ssp_pcell_id0: SSP_PCELL_ID0, _reserved15: [u8; 0x02], - #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id1: SSP_PCELL_ID1, + ssp_pcell_id1: SSP_PCELL_ID1, _reserved16: [u8; 0x02], - #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id2: SSP_PCELL_ID2, + ssp_pcell_id2: SSP_PCELL_ID2, _reserved17: [u8; 0x02], + ssp_pcell_id3: SSP_PCELL_ID3, +} +impl RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr0(&self) -> &SSP_CR0 { + &self.ssp_cr0 + } + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr1(&self) -> &SSP_CR1 { + &self.ssp_cr1 + } + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + #[inline(always)] + pub const fn ssp_dr(&self) -> &SSP_DR { + &self.ssp_dr + } + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + #[inline(always)] + pub const fn ssp_sr(&self) -> &SSP_SR { + &self.ssp_sr + } + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + #[inline(always)] + pub const fn ssp_cpsr(&self) -> &SSP_CPSR { + &self.ssp_cpsr + } + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + #[inline(always)] + pub const fn ssp_imsc(&self) -> &SSP_IMSC { + &self.ssp_imsc + } + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + #[inline(always)] + pub const fn ssp_ris(&self) -> &SSP_RIS { + &self.ssp_ris + } + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + #[inline(always)] + pub const fn ssp_mis(&self) -> &SSP_MIS { + &self.ssp_mis + } + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + #[inline(always)] + pub const fn ssp_icr(&self) -> &SSP_ICR { + &self.ssp_icr + } + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + #[inline(always)] + pub const fn ssp_dmacr(&self) -> &SSP_DMACR { + &self.ssp_dmacr + } + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id0(&self) -> &SSP_PERIPH_ID0 { + &self.ssp_periph_id0 + } + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id1(&self) -> &SSP_PERIPH_ID1 { + &self.ssp_periph_id1 + } + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id2(&self) -> &SSP_PERIPH_ID2 { + &self.ssp_periph_id2 + } + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id3(&self) -> &SSP_PERIPH_ID3 { + &self.ssp_periph_id3 + } + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id0(&self) -> &SSP_PCELL_ID0 { + &self.ssp_pcell_id0 + } + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id1(&self) -> &SSP_PCELL_ID1 { + &self.ssp_pcell_id1 + } + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id2(&self) -> &SSP_PCELL_ID2 { + &self.ssp_pcell_id2 + } #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id3: SSP_PCELL_ID3, + #[inline(always)] + pub const fn ssp_pcell_id3(&self) -> &SSP_PCELL_ID3 { + &self.ssp_pcell_id3 + } } -#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr0`] module"] pub type SSP_CR0 = crate::Reg; #[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] pub mod ssp_cr0; -#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr1`] module"] pub type SSP_CR1 = crate::Reg; #[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] pub mod ssp_cr1; -#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dr`] module"] pub type SSP_DR = crate::Reg; #[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] pub mod ssp_dr; -#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_sr`] module"] pub type SSP_SR = crate::Reg; #[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] pub mod ssp_sr; -#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cpsr`] module"] pub type SSP_CPSR = crate::Reg; #[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] pub mod ssp_cpsr; -#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_imsc`] module"] pub type SSP_IMSC = crate::Reg; #[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] pub mod ssp_imsc; -#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_ris`] module"] pub type SSP_RIS = crate::Reg; #[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] pub mod ssp_ris; -#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_mis`] module"] pub type SSP_MIS = crate::Reg; #[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] pub mod ssp_mis; -#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_icr`] module"] pub type SSP_ICR = crate::Reg; #[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] pub mod ssp_icr; -#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dmacr`] module"] pub type SSP_DMACR = crate::Reg; #[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] pub mod ssp_dmacr; -#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id0`] module"] pub type SSP_PERIPH_ID0 = crate::Reg; #[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id0; -#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id1`] module"] pub type SSP_PERIPH_ID1 = crate::Reg; #[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id1; -#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id2`] module"] pub type SSP_PERIPH_ID2 = crate::Reg; #[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id2; -#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id3`] module"] pub type SSP_PERIPH_ID3 = crate::Reg; #[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id3; -#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id0`] module"] pub type SSP_PCELL_ID0 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id0; -#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id1`] module"] pub type SSP_PCELL_ID1 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id1; -#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id2`] module"] pub type SSP_PCELL_ID2 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id2; -#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id3`] module"] pub type SSP_PCELL_ID3 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_cpsr.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_cpsr.rs index 214d9da..2fa25a9 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_cpsr.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_cpsr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] pub type CPSDVSR_R = crate::FieldReader; #[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] -pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type CPSDVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] #[must_use] - pub fn cpsdvsr(&mut self) -> CPSDVSR_W { - CPSDVSR_W::new(self) + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_cr0.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_cr0.rs index 1f3740e..b3ee9c6 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_cr0.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_cr0.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `dss` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] pub type DSS_R = crate::FieldReader; #[doc = "Field `dss` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] -pub type DSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type DSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] pub type FRF_R = crate::FieldReader; #[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] -pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] pub type SPO_R = crate::BitReader; #[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] -pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPO_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] pub type SPH_R = crate::BitReader; #[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] -pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPH_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] @@ -56,35 +56,39 @@ impl W { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] #[must_use] - pub fn dss(&mut self) -> DSS_W { - DSS_W::new(self) + pub fn dss(&mut self) -> DSS_W { + DSS_W::new(self, 0) } #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] #[inline(always)] #[must_use] - pub fn frf(&mut self) -> FRF_W { - FRF_W::new(self) + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self, 4) } #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn spo(&mut self) -> SPO_W { - SPO_W::new(self) + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self, 6) } #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn sph(&mut self) -> SPH_W { - SPH_W::new(self) + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self, 6) } #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_cr1.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_cr1.rs index 69dbcbd..b115461 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_cr1.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_cr1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] pub type LBM_R = crate::BitReader; #[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] -pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LBM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] pub type SSE_R = crate::BitReader; #[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] -pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SSE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] pub type MS_R = crate::BitReader; #[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] -pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] pub type SOD_R = crate::BitReader; #[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] -pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SOD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] #[must_use] - pub fn lbm(&mut self) -> LBM_W { - LBM_W::new(self) + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self, 0) } #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] #[inline(always)] #[must_use] - pub fn sse(&mut self) -> SSE_W { - SSE_W::new(self) + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self, 1) } #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] #[inline(always)] #[must_use] - pub fn ms(&mut self) -> MS_W { - MS_W::new(self) + pub fn ms(&mut self) -> MS_W { + MS_W::new(self, 2) } #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] #[inline(always)] #[must_use] - pub fn sod(&mut self) -> SOD_W { - SOD_W::new(self) + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_dmacr.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_dmacr.rs index c20ae0f..d7fd182 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_dmacr.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_dmacr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub type RXDMAE_R = crate::BitReader; #[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] -pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub type TXDMAE_R = crate::BitReader; #[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] -pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W { - RXDMAE_W::new(self) + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self, 0) } #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W { - TXDMAE_W::new(self) + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_dr.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_dr.rs index 019ee7c..ad69481 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_dr.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_dr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub type DATA_R = crate::FieldReader; #[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] -pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W { - DATA_W::new(self) + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_icr.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_icr.rs index 9828eba..78a767d 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_icr.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_icr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] pub type RORIC_R = crate::BitReader; #[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] -pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] pub type RTIC_R = crate::BitReader; #[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] -pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIC_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] #[must_use] - pub fn roric(&mut self) -> RORIC_W { - RORIC_W::new(self) + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self, 0) } #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W { - RTIC_W::new(self) + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_imsc.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_imsc.rs index c628750..63738cd 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_imsc.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_imsc.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] pub type RORIM_R = crate::BitReader; #[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] -pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] pub type RTIM_R = crate::BitReader; #[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] -pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] pub type RXIM_R = crate::BitReader; #[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] -pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] pub type TXIM_R = crate::BitReader; #[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] -pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rorim(&mut self) -> RORIM_W { - RORIM_W::new(self) + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self, 0) } #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W { - RTIM_W::new(self) + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self, 1) } #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W { - RXIM_W::new(self) + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self, 2) } #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W { - TXIM_W::new(self) + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_mis.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_mis.rs index 358b1d4..1c50710 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_mis.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_mis.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id0.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id0.rs index 7210289..9b50e59 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id0.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id1.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id1.rs index 0953ee0..2e23cc7 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id1.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id2.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id2.rs index 5f0696d..1b5fb34 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id2.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id2.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id3.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id3.rs index c532f5c..6642d55 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id3.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_pcell_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_periph_id0.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_periph_id0.rs index 98a341a..c69007a 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_periph_id0.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_periph_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_periph_id1.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_periph_id1.rs index 0c53a92..71907fb 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_periph_id1.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_periph_id1.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_periph_id2.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_periph_id2.rs index 1b49543..2efc3ae 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_periph_id2.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_periph_id2.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_periph_id3.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_periph_id3.rs index 8f18a77..c2f7b1c 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_periph_id3.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_periph_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_ris.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_ris.rs index 46ca4be..27dee48 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_ris.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_ris.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi5/ssp_sr.rs b/jh7110-vf2-13b-pac/src/spi5/ssp_sr.rs index b25ffb6..bf388f5 100644 --- a/jh7110-vf2-13b-pac/src/spi5/ssp_sr.rs +++ b/jh7110-vf2-13b-pac/src/spi5/ssp_sr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6.rs b/jh7110-vf2-13b-pac/src/spi6.rs index e1d7fdc..6e69208 100644 --- a/jh7110-vf2-13b-pac/src/spi6.rs +++ b/jh7110-vf2-13b-pac/src/spi6.rs @@ -1,146 +1,220 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] - pub ssp_cr0: SSP_CR0, + ssp_cr0: SSP_CR0, _reserved1: [u8; 0x02], - #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] - pub ssp_cr1: SSP_CR1, + ssp_cr1: SSP_CR1, _reserved2: [u8; 0x02], - #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] - pub ssp_dr: SSP_DR, + ssp_dr: SSP_DR, _reserved3: [u8; 0x02], - #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] - pub ssp_sr: SSP_SR, + ssp_sr: SSP_SR, _reserved4: [u8; 0x02], - #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] - pub ssp_cpsr: SSP_CPSR, + ssp_cpsr: SSP_CPSR, _reserved5: [u8; 0x02], - #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] - pub ssp_imsc: SSP_IMSC, + ssp_imsc: SSP_IMSC, _reserved6: [u8; 0x02], - #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] - pub ssp_ris: SSP_RIS, + ssp_ris: SSP_RIS, _reserved7: [u8; 0x02], - #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] - pub ssp_mis: SSP_MIS, + ssp_mis: SSP_MIS, _reserved8: [u8; 0x02], - #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] - pub ssp_icr: SSP_ICR, + ssp_icr: SSP_ICR, _reserved9: [u8; 0x02], - #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] - pub ssp_dmacr: SSP_DMACR, + ssp_dmacr: SSP_DMACR, _reserved10: [u8; 0x0fba], - #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id0: SSP_PERIPH_ID0, + ssp_periph_id0: SSP_PERIPH_ID0, _reserved11: [u8; 0x02], - #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id1: SSP_PERIPH_ID1, + ssp_periph_id1: SSP_PERIPH_ID1, _reserved12: [u8; 0x02], - #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id2: SSP_PERIPH_ID2, + ssp_periph_id2: SSP_PERIPH_ID2, _reserved13: [u8; 0x02], - #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] - pub ssp_periph_id3: SSP_PERIPH_ID3, + ssp_periph_id3: SSP_PERIPH_ID3, _reserved14: [u8; 0x02], - #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id0: SSP_PCELL_ID0, + ssp_pcell_id0: SSP_PCELL_ID0, _reserved15: [u8; 0x02], - #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id1: SSP_PCELL_ID1, + ssp_pcell_id1: SSP_PCELL_ID1, _reserved16: [u8; 0x02], - #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id2: SSP_PCELL_ID2, + ssp_pcell_id2: SSP_PCELL_ID2, _reserved17: [u8; 0x02], + ssp_pcell_id3: SSP_PCELL_ID3, +} +impl RegisterBlock { + #[doc = "0x00 - SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr0(&self) -> &SSP_CR0 { + &self.ssp_cr0 + } + #[doc = "0x04 - SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] + #[inline(always)] + pub const fn ssp_cr1(&self) -> &SSP_CR1 { + &self.ssp_cr1 + } + #[doc = "0x08 - SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] + #[inline(always)] + pub const fn ssp_dr(&self) -> &SSP_DR { + &self.ssp_dr + } + #[doc = "0x0c - SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] + #[inline(always)] + pub const fn ssp_sr(&self) -> &SSP_SR { + &self.ssp_sr + } + #[doc = "0x10 - SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] + #[inline(always)] + pub const fn ssp_cpsr(&self) -> &SSP_CPSR { + &self.ssp_cpsr + } + #[doc = "0x14 - The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] + #[inline(always)] + pub const fn ssp_imsc(&self) -> &SSP_IMSC { + &self.ssp_imsc + } + #[doc = "0x18 - The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] + #[inline(always)] + pub const fn ssp_ris(&self) -> &SSP_RIS { + &self.ssp_ris + } + #[doc = "0x1c - The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] + #[inline(always)] + pub const fn ssp_mis(&self) -> &SSP_MIS { + &self.ssp_mis + } + #[doc = "0x20 - The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] + #[inline(always)] + pub const fn ssp_icr(&self) -> &SSP_ICR { + &self.ssp_icr + } + #[doc = "0x24 - The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] + #[inline(always)] + pub const fn ssp_dmacr(&self) -> &SSP_DMACR { + &self.ssp_dmacr + } + #[doc = "0xfe0 - The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id0(&self) -> &SSP_PERIPH_ID0 { + &self.ssp_periph_id0 + } + #[doc = "0xfe4 - The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id1(&self) -> &SSP_PERIPH_ID1 { + &self.ssp_periph_id1 + } + #[doc = "0xfe8 - The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id2(&self) -> &SSP_PERIPH_ID2 { + &self.ssp_periph_id2 + } + #[doc = "0xfec - The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] + #[inline(always)] + pub const fn ssp_periph_id3(&self) -> &SSP_PERIPH_ID3 { + &self.ssp_periph_id3 + } + #[doc = "0xff0 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id0(&self) -> &SSP_PCELL_ID0 { + &self.ssp_pcell_id0 + } + #[doc = "0xff4 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id1(&self) -> &SSP_PCELL_ID1 { + &self.ssp_pcell_id1 + } + #[doc = "0xff8 - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] + #[inline(always)] + pub const fn ssp_pcell_id2(&self) -> &SSP_PCELL_ID2 { + &self.ssp_pcell_id2 + } #[doc = "0xffc - The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] - pub ssp_pcell_id3: SSP_PCELL_ID3, + #[inline(always)] + pub const fn ssp_pcell_id3(&self) -> &SSP_PCELL_ID3 { + &self.ssp_pcell_id3 + } } -#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr0`] +#[doc = "ssp_cr0 (rw) register accessor: SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr0`] module"] pub type SSP_CR0 = crate::Reg; #[doc = "SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP."] pub mod ssp_cr0; -#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cr1`] +#[doc = "ssp_cr1 (rw) register accessor: SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cr1`] module"] pub type SSP_CR1 = crate::Reg; #[doc = "SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP."] pub mod ssp_cr1; -#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dr`] +#[doc = "ssp_dr (rw) register accessor: SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dr`] module"] pub type SSP_DR = crate::Reg; #[doc = "SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer."] pub mod ssp_dr; -#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_sr`] +#[doc = "ssp_sr (rw) register accessor: SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_sr`] module"] pub type SSP_SR = crate::Reg; #[doc = "SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status."] pub mod ssp_sr; -#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_cpsr`] +#[doc = "ssp_cpsr (rw) register accessor: SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_cpsr`] module"] pub type SSP_CPSR = crate::Reg; #[doc = "SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between \\[2:254\\]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero."] pub mod ssp_cpsr; -#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_imsc`] +#[doc = "ssp_imsc (rw) register accessor: The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_imsc`] module"] pub type SSP_IMSC = crate::Reg; #[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset."] pub mod ssp_imsc; -#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_ris`] +#[doc = "ssp_ris (rw) register accessor: The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_ris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_ris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_ris`] module"] pub type SSP_RIS = crate::Reg; #[doc = "The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect."] pub mod ssp_ris; -#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_mis`] +#[doc = "ssp_mis (rw) register accessor: The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_mis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_mis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_mis`] module"] pub type SSP_MIS = crate::Reg; #[doc = "The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect."] pub mod ssp_mis; -#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_icr`] +#[doc = "ssp_icr (rw) register accessor: The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_icr`] module"] pub type SSP_ICR = crate::Reg; #[doc = "The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect."] pub mod ssp_icr; -#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_dmacr`] +#[doc = "ssp_dmacr (rw) register accessor: The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_dmacr`] module"] pub type SSP_DMACR = crate::Reg; #[doc = "The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset."] pub mod ssp_dmacr; -#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id0`] +#[doc = "ssp_periph_id0 (rw) register accessor: The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id0`] module"] pub type SSP_PERIPH_ID0 = crate::Reg; #[doc = "The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id0; -#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id1`] +#[doc = "ssp_periph_id1 (rw) register accessor: The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id1`] module"] pub type SSP_PERIPH_ID1 = crate::Reg; #[doc = "The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id1; -#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id2`] +#[doc = "ssp_periph_id2 (rw) register accessor: The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id2`] module"] pub type SSP_PERIPH_ID2 = crate::Reg; #[doc = "The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id2; -#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_periph_id3`] +#[doc = "ssp_periph_id3 (rw) register accessor: The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_periph_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_periph_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_periph_id3`] module"] pub type SSP_PERIPH_ID3 = crate::Reg; #[doc = "The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register."] pub mod ssp_periph_id3; -#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id0`] +#[doc = "ssp_pcell_id0 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id0`] module"] pub type SSP_PCELL_ID0 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id0; -#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id1`] +#[doc = "ssp_pcell_id1 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id1`] module"] pub type SSP_PCELL_ID1 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id1; -#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id2`] +#[doc = "ssp_pcell_id2 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id2`] module"] pub type SSP_PCELL_ID2 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] pub mod ssp_pcell_id2; -#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssp_pcell_id3`] +#[doc = "ssp_pcell_id3 (rw) register accessor: The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp_pcell_id3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp_pcell_id3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp_pcell_id3`] module"] pub type SSP_PCELL_ID3 = crate::Reg; #[doc = "The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D."] diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_cpsr.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_cpsr.rs index 214d9da..2fa25a9 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_cpsr.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_cpsr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `cpsdvsr` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] pub type CPSDVSR_R = crate::FieldReader; #[doc = "Field `cpsdvsr` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] -pub type CPSDVSR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type CPSDVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] #[inline(always)] #[must_use] - pub fn cpsdvsr(&mut self) -> CPSDVSR_W { - CPSDVSR_W::new(self) + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_cr0.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_cr0.rs index 1f3740e..b3ee9c6 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_cr0.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_cr0.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `dss` reader - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] pub type DSS_R = crate::FieldReader; #[doc = "Field `dss` writer - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] -pub type DSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type DSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `frf` reader - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] pub type FRF_R = crate::FieldReader; #[doc = "Field `frf` writer - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] -pub type FRF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `spo` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] pub type SPO_R = crate::BitReader; #[doc = "Field `spo` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] -pub type SPO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPO_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sph` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] pub type SPH_R = crate::BitReader; #[doc = "Field `sph` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] -pub type SPH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SPH_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scr` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] @@ -56,35 +56,39 @@ impl W { #[doc = "Bits 0:3 - Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data"] #[inline(always)] #[must_use] - pub fn dss(&mut self) -> DSS_W { - DSS_W::new(self) + pub fn dss(&mut self) -> DSS_W { + DSS_W::new(self, 0) } #[doc = "Bits 4:5 - Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved"] #[inline(always)] #[must_use] - pub fn frf(&mut self) -> FRF_W { - FRF_W::new(self) + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self, 4) } #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn spo(&mut self) -> SPO_W { - SPO_W::new(self) + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self, 6) } #[doc = "Bit 6 - SSPCLKOUT phase, applicable to Motorola SPI frame format only."] #[inline(always)] #[must_use] - pub fn sph(&mut self) -> SPH_W { - SPH_W::new(self) + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self, 6) } #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F\\[sspclk\\] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from \\[2:254\\], programmed through the SSPCPSR register and SCR is a value from \\[0:255\\]"] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_cr1.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_cr1.rs index 69dbcbd..b115461 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_cr1.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_cr1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `lbm` reader - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] pub type LBM_R = crate::BitReader; #[doc = "Field `lbm` writer - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] -pub type LBM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LBM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sse` reader - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] pub type SSE_R = crate::BitReader; #[doc = "Field `sse` writer - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] -pub type SSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SSE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ms` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] pub type MS_R = crate::BitReader; #[doc = "Field `ms` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] -pub type MS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sod` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] pub type SOD_R = crate::BitReader; #[doc = "Field `sod` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] -pub type SOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SOD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally"] #[inline(always)] #[must_use] - pub fn lbm(&mut self) -> LBM_W { - LBM_W::new(self) + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self, 0) } #[doc = "Bit 1 - Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled"] #[inline(always)] #[must_use] - pub fn sse(&mut self) -> SSE_W { - SSE_W::new(self) + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self, 1) } #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave"] #[inline(always)] #[must_use] - pub fn ms(&mut self) -> MS_W { - MS_W::new(self) + pub fn ms(&mut self) -> MS_W { + MS_W::new(self, 2) } #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode"] #[inline(always)] #[must_use] - pub fn sod(&mut self) -> SOD_W { - SOD_W::new(self) + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_dmacr.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_dmacr.rs index c20ae0f..d7fd182 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_dmacr.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_dmacr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `rxdmae` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] pub type RXDMAE_R = crate::BitReader; #[doc = "Field `rxdmae` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] -pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txdmae` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] pub type TXDMAE_R = crate::BitReader; #[doc = "Field `txdmae` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] -pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W { - RXDMAE_W::new(self) + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self, 0) } #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W { - TXDMAE_W::new(self) + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_dr.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_dr.rs index 019ee7c..ad69481 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_dr.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_dr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `data` reader - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub type DATA_R = crate::FieldReader; #[doc = "Field `data` writer - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] -pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:15 - Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W { - DATA_W::new(self) + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_icr.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_icr.rs index 9828eba..78a767d 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_icr.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_icr.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `roric` reader - Clears the SSPRORINTR interrupt"] pub type RORIC_R = crate::BitReader; #[doc = "Field `roric` writer - Clears the SSPRORINTR interrupt"] -pub type RORIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtic` reader - Clears the SSPRTINTR interrupt"] pub type RTIC_R = crate::BitReader; #[doc = "Field `rtic` writer - Clears the SSPRTINTR interrupt"] -pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIC_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] #[inline(always)] #[must_use] - pub fn roric(&mut self) -> RORIC_W { - RORIC_W::new(self) + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self, 0) } #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W { - RTIC_W::new(self) + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self, 1) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_imsc.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_imsc.rs index c628750..63738cd 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_imsc.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_imsc.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `rorim` reader - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] pub type RORIM_R = crate::BitReader; #[doc = "Field `rorim` writer - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] -pub type RORIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RORIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rtim` reader - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] pub type RTIM_R = crate::BitReader; #[doc = "Field `rtim` writer - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] -pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rxim` reader - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] pub type RXIM_R = crate::BitReader; #[doc = "Field `rxim` writer - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] -pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `txim` reader - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] pub type TXIM_R = crate::BitReader; #[doc = "Field `txim` writer - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] -pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rorim(&mut self) -> RORIM_W { - RORIM_W::new(self) + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self, 0) } #[doc = "Bit 1 - Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W { - RTIM_W::new(self) + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self, 1) } #[doc = "Bit 2 - Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W { - RXIM_W::new(self) + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self, 2) } #[doc = "Bit 2 - Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W { - TXIM_W::new(self) + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_mis.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_mis.rs index 358b1d4..1c50710 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_mis.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_mis.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id0.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id0.rs index 7210289..9b50e59 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id0.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id1.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id1.rs index 0953ee0..2e23cc7 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id1.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id2.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id2.rs index 5f0696d..1b5fb34 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id2.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id2.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id3.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id3.rs index c532f5c..6642d55 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id3.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_pcell_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_periph_id0.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_periph_id0.rs index 98a341a..c69007a 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_periph_id0.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_periph_id0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_periph_id1.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_periph_id1.rs index 0c53a92..71907fb 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_periph_id1.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_periph_id1.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_periph_id2.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_periph_id2.rs index 1b49543..2efc3ae 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_periph_id2.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_periph_id2.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_periph_id3.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_periph_id3.rs index 8f18a77..c2f7b1c 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_periph_id3.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_periph_id3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_ris.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_ris.rs index 46ca4be..27dee48 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_ris.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_ris.rs @@ -33,7 +33,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/spi6/ssp_sr.rs b/jh7110-vf2-13b-pac/src/spi6/ssp_sr.rs index b25ffb6..bf388f5 100644 --- a/jh7110-vf2-13b-pac/src/spi6/ssp_sr.rs +++ b/jh7110-vf2-13b-pac/src/spi6/ssp_sr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon.rs b/jh7110-vf2-13b-pac/src/stg_syscon.rs index 6172b24..477eedb 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon.rs @@ -1,1864 +1,2798 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + stg_sysconsaif_syscfg0: STG_SYSCONSAIF_SYSCFG0, + stg_sysconsaif_syscfg4: STG_SYSCONSAIF_SYSCFG4, + stg_sysconsaif_syscfg8: STG_SYSCONSAIF_SYSCFG8, + stg_sysconsaif_syscfg12: STG_SYSCONSAIF_SYSCFG12, + stg_sysconsaif_syscfg16: STG_SYSCONSAIF_SYSCFG16, + stg_sysconsaif_syscfg20: STG_SYSCONSAIF_SYSCFG20, + stg_sysconsaif_syscfg24: STG_SYSCONSAIF_SYSCFG24, + stg_sysconsaif_syscfg28: STG_SYSCONSAIF_SYSCFG28, + stg_sysconsaif_syscfg32: STG_SYSCONSAIF_SYSCFG32, + stg_sysconsaif_syscfg36: STG_SYSCONSAIF_SYSCFG36, + stg_sysconsaif_syscfg40: STG_SYSCONSAIF_SYSCFG40, + stg_sysconsaif_syscfg44: STG_SYSCONSAIF_SYSCFG44, + stg_sysconsaif_syscfg48: STG_SYSCONSAIF_SYSCFG48, + stg_sysconsaif_syscfg52: STG_SYSCONSAIF_SYSCFG52, + stg_sysconsaif_syscfg56: STG_SYSCONSAIF_SYSCFG56, + stg_sysconsaif_syscfg60: STG_SYSCONSAIF_SYSCFG60, + stg_sysconsaif_syscfg64: STG_SYSCONSAIF_SYSCFG64, + stg_sysconsaif_syscfg68: STG_SYSCONSAIF_SYSCFG68, + stg_sysconsaif_syscfg72: STG_SYSCONSAIF_SYSCFG72, + stg_sysconsaif_syscfg76: STG_SYSCONSAIF_SYSCFG76, + stg_sysconsaif_syscfg80: STG_SYSCONSAIF_SYSCFG80, + stg_sysconsaif_syscfg84: STG_SYSCONSAIF_SYSCFG84, + stg_sysconsaif_syscfg88: STG_SYSCONSAIF_SYSCFG88, + stg_sysconsaif_syscfg92: STG_SYSCONSAIF_SYSCFG92, + stg_sysconsaif_syscfg96: STG_SYSCONSAIF_SYSCFG96, + stg_sysconsaif_syscfg100: STG_SYSCONSAIF_SYSCFG100, + stg_sysconsaif_syscfg104: STG_SYSCONSAIF_SYSCFG104, + stg_sysconsaif_syscfg108: STG_SYSCONSAIF_SYSCFG108, + stg_sysconsaif_syscfg112: STG_SYSCONSAIF_SYSCFG112, + stg_sysconsaif_syscfg116: STG_SYSCONSAIF_SYSCFG116, + stg_sysconsaif_syscfg120: STG_SYSCONSAIF_SYSCFG120, + stg_sysconsaif_syscfg124: STG_SYSCONSAIF_SYSCFG124, + stg_sysconsaif_syscfg128: STG_SYSCONSAIF_SYSCFG128, + stg_sysconsaif_syscfg132: STG_SYSCONSAIF_SYSCFG132, + stg_sysconsaif_syscfg136: STG_SYSCONSAIF_SYSCFG136, + stg_sysconsaif_syscfg140: STG_SYSCONSAIF_SYSCFG140, + stg_sysconsaif_syscfg144: STG_SYSCONSAIF_SYSCFG144, + stg_sysconsaif_syscfg148: STG_SYSCONSAIF_SYSCFG148, + stg_sysconsaif_syscfg152: STG_SYSCONSAIF_SYSCFG152, + stg_sysconsaif_syscfg156: STG_SYSCONSAIF_SYSCFG156, + stg_sysconsaif_syscfg160: STG_SYSCONSAIF_SYSCFG160, + stg_sysconsaif_syscfg164: STG_SYSCONSAIF_SYSCFG164, + stg_sysconsaif_syscfg168: STG_SYSCONSAIF_SYSCFG168, + stg_sysconsaif_syscfg172: STG_SYSCONSAIF_SYSCFG172, + stg_sysconsaif_syscfg176: STG_SYSCONSAIF_SYSCFG176, + stg_sysconsaif_syscfg180: STG_SYSCONSAIF_SYSCFG180, + stg_sysconsaif_syscfg184: STG_SYSCONSAIF_SYSCFG184, + stg_sysconsaif_syscfg188: STG_SYSCONSAIF_SYSCFG188, + stg_sysconsaif_syscfg192: STG_SYSCONSAIF_SYSCFG192, + stg_sysconsaif_syscfg196: STG_SYSCONSAIF_SYSCFG196, + stg_sysconsaif_syscfg200: STG_SYSCONSAIF_SYSCFG200, + stg_sysconsaif_syscfg204: STG_SYSCONSAIF_SYSCFG204, + stg_sysconsaif_syscfg208: STG_SYSCONSAIF_SYSCFG208, + stg_sysconsaif_syscfg212: STG_SYSCONSAIF_SYSCFG212, + stg_sysconsaif_syscfg216: STG_SYSCONSAIF_SYSCFG216, + stg_sysconsaif_syscfg220: STG_SYSCONSAIF_SYSCFG220, + stg_sysconsaif_syscfg224: STG_SYSCONSAIF_SYSCFG224, + stg_sysconsaif_syscfg228: STG_SYSCONSAIF_SYSCFG228, + stg_sysconsaif_syscfg232: STG_SYSCONSAIF_SYSCFG232, + stg_sysconsaif_syscfg236: STG_SYSCONSAIF_SYSCFG236, + stg_sysconsaif_syscfg240: STG_SYSCONSAIF_SYSCFG240, + stg_sysconsaif_syscfg244: STG_SYSCONSAIF_SYSCFG244, + stg_sysconsaif_syscfg248: STG_SYSCONSAIF_SYSCFG248, + stg_sysconsaif_syscfg252: STG_SYSCONSAIF_SYSCFG252, + stg_sysconsaif_syscfg256: STG_SYSCONSAIF_SYSCFG256, + stg_sysconsaif_syscfg260: STG_SYSCONSAIF_SYSCFG260, + stg_sysconsaif_syscfg264: STG_SYSCONSAIF_SYSCFG264, + stg_sysconsaif_syscfg268: STG_SYSCONSAIF_SYSCFG268, + stg_sysconsaif_syscfg272: STG_SYSCONSAIF_SYSCFG272, + stg_sysconsaif_syscfg276: STG_SYSCONSAIF_SYSCFG276, + stg_sysconsaif_syscfg280: STG_SYSCONSAIF_SYSCFG280, + stg_sysconsaif_syscfg284: STG_SYSCONSAIF_SYSCFG284, + stg_sysconsaif_syscfg288: STG_SYSCONSAIF_SYSCFG288, + stg_sysconsaif_syscfg292: STG_SYSCONSAIF_SYSCFG292, + stg_sysconsaif_syscfg296: STG_SYSCONSAIF_SYSCFG296, + stg_sysconsaif_syscfg300: STG_SYSCONSAIF_SYSCFG300, + stg_sysconsaif_syscfg304: STG_SYSCONSAIF_SYSCFG304, + stg_sysconsaif_syscfg308: STG_SYSCONSAIF_SYSCFG308, + stg_sysconsaif_syscfg312: STG_SYSCONSAIF_SYSCFG312, + stg_sysconsaif_syscfg316: STG_SYSCONSAIF_SYSCFG316, + stg_sysconsaif_syscfg320: STG_SYSCONSAIF_SYSCFG320, + stg_sysconsaif_syscfg324: STG_SYSCONSAIF_SYSCFG324, + stg_sysconsaif_syscfg328: STG_SYSCONSAIF_SYSCFG328, + stg_sysconsaif_syscfg332: STG_SYSCONSAIF_SYSCFG332, + stg_sysconsaif_syscfg336: STG_SYSCONSAIF_SYSCFG336, + stg_sysconsaif_syscfg340: STG_SYSCONSAIF_SYSCFG340, + stg_sysconsaif_syscfg344: STG_SYSCONSAIF_SYSCFG344, + stg_sysconsaif_syscfg348: STG_SYSCONSAIF_SYSCFG348, + stg_sysconsaif_syscfg352: STG_SYSCONSAIF_SYSCFG352, + stg_sysconsaif_syscfg356: STG_SYSCONSAIF_SYSCFG356, + stg_sysconsaif_syscfg360: STG_SYSCONSAIF_SYSCFG360, + stg_sysconsaif_syscfg364: STG_SYSCONSAIF_SYSCFG364, + stg_sysconsaif_syscfg368: STG_SYSCONSAIF_SYSCFG368, + stg_sysconsaif_syscfg372: STG_SYSCONSAIF_SYSCFG372, + stg_sysconsaif_syscfg376: STG_SYSCONSAIF_SYSCFG376, + stg_sysconsaif_syscfg380: STG_SYSCONSAIF_SYSCFG380, + stg_sysconsaif_syscfg384: STG_SYSCONSAIF_SYSCFG384, + stg_sysconsaif_syscfg388: STG_SYSCONSAIF_SYSCFG388, + stg_sysconsaif_syscfg392: STG_SYSCONSAIF_SYSCFG392, + stg_sysconsaif_syscfg396: STG_SYSCONSAIF_SYSCFG396, + stg_sysconsaif_syscfg400: STG_SYSCONSAIF_SYSCFG400, + stg_sysconsaif_syscfg404: STG_SYSCONSAIF_SYSCFG404, + stg_sysconsaif_syscfg408: STG_SYSCONSAIF_SYSCFG408, + stg_sysconsaif_syscfg412: STG_SYSCONSAIF_SYSCFG412, + stg_sysconsaif_syscfg416: STG_SYSCONSAIF_SYSCFG416, + stg_sysconsaif_syscfg420: STG_SYSCONSAIF_SYSCFG420, + stg_sysconsaif_syscfg424: STG_SYSCONSAIF_SYSCFG424, + stg_sysconsaif_syscfg428: STG_SYSCONSAIF_SYSCFG428, + stg_sysconsaif_syscfg432: STG_SYSCONSAIF_SYSCFG432, + stg_sysconsaif_syscfg436: STG_SYSCONSAIF_SYSCFG436, + stg_sysconsaif_syscfg440: STG_SYSCONSAIF_SYSCFG440, + stg_sysconsaif_syscfg444: STG_SYSCONSAIF_SYSCFG444, + stg_sysconsaif_syscfg448: STG_SYSCONSAIF_SYSCFG448, + stg_sysconsaif_syscfg452: STG_SYSCONSAIF_SYSCFG452, + stg_sysconsaif_syscfg456: STG_SYSCONSAIF_SYSCFG456, + stg_sysconsaif_syscfg460: STG_SYSCONSAIF_SYSCFG460, + stg_sysconsaif_syscfg464: STG_SYSCONSAIF_SYSCFG464, + stg_sysconsaif_syscfg468: STG_SYSCONSAIF_SYSCFG468, + stg_sysconsaif_syscfg472: STG_SYSCONSAIF_SYSCFG472, + stg_sysconsaif_syscfg476: STG_SYSCONSAIF_SYSCFG476, + stg_sysconsaif_syscfg480: STG_SYSCONSAIF_SYSCFG480, + stg_sysconsaif_syscfg484: STG_SYSCONSAIF_SYSCFG484, + stg_sysconsaif_syscfg488: STG_SYSCONSAIF_SYSCFG488, + stg_sysconsaif_syscfg492: STG_SYSCONSAIF_SYSCFG492, + _reserved124: [u8; 0x04], + stg_sysconsaif_syscfg500: STG_SYSCONSAIF_SYSCFG500, + stg_sysconsaif_syscfg504: STG_SYSCONSAIF_SYSCFG504, + stg_sysconsaif_syscfg508: STG_SYSCONSAIF_SYSCFG508, + stg_sysconsaif_syscfg512: STG_SYSCONSAIF_SYSCFG512, + stg_sysconsaif_syscfg516: STG_SYSCONSAIF_SYSCFG516, + stg_sysconsaif_syscfg520: STG_SYSCONSAIF_SYSCFG520, + stg_sysconsaif_syscfg524: STG_SYSCONSAIF_SYSCFG524, + stg_sysconsaif_syscfg528: STG_SYSCONSAIF_SYSCFG528, + stg_sysconsaif_syscfg532: STG_SYSCONSAIF_SYSCFG532, + stg_sysconsaif_syscfg536: STG_SYSCONSAIF_SYSCFG536, + stg_sysconsaif_syscfg540: STG_SYSCONSAIF_SYSCFG540, + stg_sysconsaif_syscfg544: STG_SYSCONSAIF_SYSCFG544, + stg_sysconsaif_syscfg548: STG_SYSCONSAIF_SYSCFG548, + stg_sysconsaif_syscfg552: STG_SYSCONSAIF_SYSCFG552, + stg_sysconsaif_syscfg556: STG_SYSCONSAIF_SYSCFG556, + stg_sysconsaif_syscfg560: STG_SYSCONSAIF_SYSCFG560, + stg_sysconsaif_syscfg564: STG_SYSCONSAIF_SYSCFG564, + stg_sysconsaif_syscfg568: STG_SYSCONSAIF_SYSCFG568, + stg_sysconsaif_syscfg572: STG_SYSCONSAIF_SYSCFG572, + stg_sysconsaif_syscfg576: STG_SYSCONSAIF_SYSCFG576, + stg_sysconsaif_syscfg580: STG_SYSCONSAIF_SYSCFG580, + stg_sysconsaif_syscfg584: STG_SYSCONSAIF_SYSCFG584, + stg_sysconsaif_syscfg588: STG_SYSCONSAIF_SYSCFG588, + stg_sysconsaif_syscfg592: STG_SYSCONSAIF_SYSCFG592, + stg_sysconsaif_syscfg596: STG_SYSCONSAIF_SYSCFG596, + stg_sysconsaif_syscfg600: STG_SYSCONSAIF_SYSCFG600, + stg_sysconsaif_syscfg604: STG_SYSCONSAIF_SYSCFG604, + stg_sysconsaif_syscfg608: STG_SYSCONSAIF_SYSCFG608, + stg_sysconsaif_syscfg612: STG_SYSCONSAIF_SYSCFG612, + stg_sysconsaif_syscfg616: STG_SYSCONSAIF_SYSCFG616, + stg_sysconsaif_syscfg620: STG_SYSCONSAIF_SYSCFG620, + stg_sysconsaif_syscfg624: STG_SYSCONSAIF_SYSCFG624, + stg_sysconsaif_syscfg628: STG_SYSCONSAIF_SYSCFG628, + stg_sysconsaif_syscfg632: STG_SYSCONSAIF_SYSCFG632, + stg_sysconsaif_syscfg636: STG_SYSCONSAIF_SYSCFG636, + stg_sysconsaif_syscfg640: STG_SYSCONSAIF_SYSCFG640, + stg_sysconsaif_syscfg644: STG_SYSCONSAIF_SYSCFG644, + stg_sysconsaif_syscfg648: STG_SYSCONSAIF_SYSCFG648, + stg_sysconsaif_syscfg652: STG_SYSCONSAIF_SYSCFG652, + stg_sysconsaif_syscfg656: STG_SYSCONSAIF_SYSCFG656, + stg_sysconsaif_syscfg660: STG_SYSCONSAIF_SYSCFG660, + stg_sysconsaif_syscfg664: STG_SYSCONSAIF_SYSCFG664, + stg_sysconsaif_syscfg668: STG_SYSCONSAIF_SYSCFG668, + stg_sysconsaif_syscfg672: STG_SYSCONSAIF_SYSCFG672, + stg_sysconsaif_syscfg676: STG_SYSCONSAIF_SYSCFG676, + stg_sysconsaif_syscfg680: STG_SYSCONSAIF_SYSCFG680, + stg_sysconsaif_syscfg684: STG_SYSCONSAIF_SYSCFG684, + stg_sysconsaif_syscfg688: STG_SYSCONSAIF_SYSCFG688, + stg_sysconsaif_syscfg692: STG_SYSCONSAIF_SYSCFG692, + stg_sysconsaif_syscfg696: STG_SYSCONSAIF_SYSCFG696, + stg_sysconsaif_syscfg700: STG_SYSCONSAIF_SYSCFG700, + stg_sysconsaif_syscfg704: STG_SYSCONSAIF_SYSCFG704, + stg_sysconsaif_syscfg708: STG_SYSCONSAIF_SYSCFG708, + stg_sysconsaif_syscfg712: STG_SYSCONSAIF_SYSCFG712, + stg_sysconsaif_syscfg716: STG_SYSCONSAIF_SYSCFG716, + stg_sysconsaif_syscfg720: STG_SYSCONSAIF_SYSCFG720, + stg_sysconsaif_syscfg724: STG_SYSCONSAIF_SYSCFG724, + stg_sysconsaif_syscfg728: STG_SYSCONSAIF_SYSCFG728, + stg_sysconsaif_syscfg732: STG_SYSCONSAIF_SYSCFG732, + stg_sysconsaif_syscfg736: STG_SYSCONSAIF_SYSCFG736, + stg_sysconsaif_syscfg740: STG_SYSCONSAIF_SYSCFG740, + stg_sysconsaif_syscfg744: STG_SYSCONSAIF_SYSCFG744, + stg_sysconsaif_syscfg748: STG_SYSCONSAIF_SYSCFG748, + stg_sysconsaif_syscfg752: STG_SYSCONSAIF_SYSCFG752, + stg_sysconsaif_syscfg756: STG_SYSCONSAIF_SYSCFG756, + stg_sysconsaif_syscfg760: STG_SYSCONSAIF_SYSCFG760, + stg_sysconsaif_syscfg764: STG_SYSCONSAIF_SYSCFG764, + stg_sysconsaif_syscfg768: STG_SYSCONSAIF_SYSCFG768, + stg_sysconsaif_syscfg772: STG_SYSCONSAIF_SYSCFG772, + stg_sysconsaif_syscfg776: STG_SYSCONSAIF_SYSCFG776, + stg_sysconsaif_syscfg780: STG_SYSCONSAIF_SYSCFG780, + stg_sysconsaif_syscfg784: STG_SYSCONSAIF_SYSCFG784, + stg_sysconsaif_syscfg788: STG_SYSCONSAIF_SYSCFG788, + stg_sysconsaif_syscfg792: STG_SYSCONSAIF_SYSCFG792, + stg_sysconsaif_syscfg796: STG_SYSCONSAIF_SYSCFG796, + stg_sysconsaif_syscfg800: STG_SYSCONSAIF_SYSCFG800, + stg_sysconsaif_syscfg804: STG_SYSCONSAIF_SYSCFG804, + stg_sysconsaif_syscfg808: STG_SYSCONSAIF_SYSCFG808, + stg_sysconsaif_syscfg812: STG_SYSCONSAIF_SYSCFG812, + stg_sysconsaif_syscfg816: STG_SYSCONSAIF_SYSCFG816, + stg_sysconsaif_syscfg820: STG_SYSCONSAIF_SYSCFG820, + stg_sysconsaif_syscfg824: STG_SYSCONSAIF_SYSCFG824, + stg_sysconsaif_syscfg828: STG_SYSCONSAIF_SYSCFG828, + stg_sysconsaif_syscfg832: STG_SYSCONSAIF_SYSCFG832, + stg_sysconsaif_syscfg836: STG_SYSCONSAIF_SYSCFG836, + stg_sysconsaif_syscfg840: STG_SYSCONSAIF_SYSCFG840, + stg_sysconsaif_syscfg844: STG_SYSCONSAIF_SYSCFG844, + stg_sysconsaif_syscfg848: STG_SYSCONSAIF_SYSCFG848, + stg_sysconsaif_syscfg852: STG_SYSCONSAIF_SYSCFG852, + stg_sysconsaif_syscfg856: STG_SYSCONSAIF_SYSCFG856, + stg_sysconsaif_syscfg860: STG_SYSCONSAIF_SYSCFG860, + stg_sysconsaif_syscfg864: STG_SYSCONSAIF_SYSCFG864, + stg_sysconsaif_syscfg868: STG_SYSCONSAIF_SYSCFG868, + stg_sysconsaif_syscfg872: STG_SYSCONSAIF_SYSCFG872, + stg_sysconsaif_syscfg876: STG_SYSCONSAIF_SYSCFG876, + stg_sysconsaif_syscfg880: STG_SYSCONSAIF_SYSCFG880, + stg_sysconsaif_syscfg884: STG_SYSCONSAIF_SYSCFG884, + stg_sysconsaif_syscfg888: STG_SYSCONSAIF_SYSCFG888, + stg_sysconsaif_syscfg892: STG_SYSCONSAIF_SYSCFG892, + stg_sysconsaif_syscfg896: STG_SYSCONSAIF_SYSCFG896, + stg_sysconsaif_syscfg900: STG_SYSCONSAIF_SYSCFG900, + stg_sysconsaif_syscfg904: STG_SYSCONSAIF_SYSCFG904, + stg_sysconsaif_syscfg908: STG_SYSCONSAIF_SYSCFG908, + stg_sysconsaif_syscfg912: STG_SYSCONSAIF_SYSCFG912, + stg_sysconsaif_syscfg916: STG_SYSCONSAIF_SYSCFG916, + stg_sysconsaif_syscfg920: STG_SYSCONSAIF_SYSCFG920, + stg_sysconsaif_syscfg924: STG_SYSCONSAIF_SYSCFG924, + stg_sysconsaif_syscfg928: STG_SYSCONSAIF_SYSCFG928, + stg_sysconsaif_syscfg932: STG_SYSCONSAIF_SYSCFG932, +} +impl RegisterBlock { #[doc = "0x00 - STG SYSCONSAIF SYSCFG 0"] - pub stg_sysconsaif_syscfg0: STG_SYSCONSAIF_SYSCFG0, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg0(&self) -> &STG_SYSCONSAIF_SYSCFG0 { + &self.stg_sysconsaif_syscfg0 + } #[doc = "0x04 - STG SYSCONSAIF SYSCFG 4"] - pub stg_sysconsaif_syscfg4: STG_SYSCONSAIF_SYSCFG4, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg4(&self) -> &STG_SYSCONSAIF_SYSCFG4 { + &self.stg_sysconsaif_syscfg4 + } #[doc = "0x08 - STG SYSCONSAIF SYSCFG 8"] - pub stg_sysconsaif_syscfg8: STG_SYSCONSAIF_SYSCFG8, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg8(&self) -> &STG_SYSCONSAIF_SYSCFG8 { + &self.stg_sysconsaif_syscfg8 + } #[doc = "0x0c - STG SYSCONSAIF SYSCFG 12"] - pub stg_sysconsaif_syscfg12: STG_SYSCONSAIF_SYSCFG12, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg12(&self) -> &STG_SYSCONSAIF_SYSCFG12 { + &self.stg_sysconsaif_syscfg12 + } #[doc = "0x10 - STG SYSCONSAIF SYSCFG 16"] - pub stg_sysconsaif_syscfg16: STG_SYSCONSAIF_SYSCFG16, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg16(&self) -> &STG_SYSCONSAIF_SYSCFG16 { + &self.stg_sysconsaif_syscfg16 + } #[doc = "0x14 - STG SYSCONSAIF SYSCFG 20"] - pub stg_sysconsaif_syscfg20: STG_SYSCONSAIF_SYSCFG20, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg20(&self) -> &STG_SYSCONSAIF_SYSCFG20 { + &self.stg_sysconsaif_syscfg20 + } #[doc = "0x18 - STG SYSCONSAIF SYSCFG 24"] - pub stg_sysconsaif_syscfg24: STG_SYSCONSAIF_SYSCFG24, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg24(&self) -> &STG_SYSCONSAIF_SYSCFG24 { + &self.stg_sysconsaif_syscfg24 + } #[doc = "0x1c - STG SYSCONSAIF SYSCFG 28"] - pub stg_sysconsaif_syscfg28: STG_SYSCONSAIF_SYSCFG28, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg28(&self) -> &STG_SYSCONSAIF_SYSCFG28 { + &self.stg_sysconsaif_syscfg28 + } #[doc = "0x20 - STG SYSCONSAIF SYSCFG 32"] - pub stg_sysconsaif_syscfg32: STG_SYSCONSAIF_SYSCFG32, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg32(&self) -> &STG_SYSCONSAIF_SYSCFG32 { + &self.stg_sysconsaif_syscfg32 + } #[doc = "0x24 - STG SYSCONSAIF SYSCFG 36"] - pub stg_sysconsaif_syscfg36: STG_SYSCONSAIF_SYSCFG36, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg36(&self) -> &STG_SYSCONSAIF_SYSCFG36 { + &self.stg_sysconsaif_syscfg36 + } #[doc = "0x28 - STG SYSCONSAIF SYSCFG 40"] - pub stg_sysconsaif_syscfg40: STG_SYSCONSAIF_SYSCFG40, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg40(&self) -> &STG_SYSCONSAIF_SYSCFG40 { + &self.stg_sysconsaif_syscfg40 + } #[doc = "0x2c - STG SYSCONSAIF SYSCFG 44"] - pub stg_sysconsaif_syscfg44: STG_SYSCONSAIF_SYSCFG44, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg44(&self) -> &STG_SYSCONSAIF_SYSCFG44 { + &self.stg_sysconsaif_syscfg44 + } #[doc = "0x30 - STG SYSCONSAIF SYSCFG 48"] - pub stg_sysconsaif_syscfg48: STG_SYSCONSAIF_SYSCFG48, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg48(&self) -> &STG_SYSCONSAIF_SYSCFG48 { + &self.stg_sysconsaif_syscfg48 + } #[doc = "0x34 - STG SYSCONSAIF SYSCFG 52"] - pub stg_sysconsaif_syscfg52: STG_SYSCONSAIF_SYSCFG52, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg52(&self) -> &STG_SYSCONSAIF_SYSCFG52 { + &self.stg_sysconsaif_syscfg52 + } #[doc = "0x38 - STG SYSCONSAIF SYSCFG 56"] - pub stg_sysconsaif_syscfg56: STG_SYSCONSAIF_SYSCFG56, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg56(&self) -> &STG_SYSCONSAIF_SYSCFG56 { + &self.stg_sysconsaif_syscfg56 + } #[doc = "0x3c - STG SYSCONSAIF SYSCFG 60"] - pub stg_sysconsaif_syscfg60: STG_SYSCONSAIF_SYSCFG60, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg60(&self) -> &STG_SYSCONSAIF_SYSCFG60 { + &self.stg_sysconsaif_syscfg60 + } #[doc = "0x40 - STG SYSCONSAIF SYSCFG 64"] - pub stg_sysconsaif_syscfg64: STG_SYSCONSAIF_SYSCFG64, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg64(&self) -> &STG_SYSCONSAIF_SYSCFG64 { + &self.stg_sysconsaif_syscfg64 + } #[doc = "0x44 - STG SYSCONSAIF SYSCFG 68"] - pub stg_sysconsaif_syscfg68: STG_SYSCONSAIF_SYSCFG68, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg68(&self) -> &STG_SYSCONSAIF_SYSCFG68 { + &self.stg_sysconsaif_syscfg68 + } #[doc = "0x48 - STG SYSCONSAIF SYSCFG 72"] - pub stg_sysconsaif_syscfg72: STG_SYSCONSAIF_SYSCFG72, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg72(&self) -> &STG_SYSCONSAIF_SYSCFG72 { + &self.stg_sysconsaif_syscfg72 + } #[doc = "0x4c - STG SYSCONSAIF SYSCFG 76"] - pub stg_sysconsaif_syscfg76: STG_SYSCONSAIF_SYSCFG76, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg76(&self) -> &STG_SYSCONSAIF_SYSCFG76 { + &self.stg_sysconsaif_syscfg76 + } #[doc = "0x50 - STG SYSCONSAIF SYSCFG 80"] - pub stg_sysconsaif_syscfg80: STG_SYSCONSAIF_SYSCFG80, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg80(&self) -> &STG_SYSCONSAIF_SYSCFG80 { + &self.stg_sysconsaif_syscfg80 + } #[doc = "0x54 - STG SYSCONSAIF SYSCFG 84"] - pub stg_sysconsaif_syscfg84: STG_SYSCONSAIF_SYSCFG84, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg84(&self) -> &STG_SYSCONSAIF_SYSCFG84 { + &self.stg_sysconsaif_syscfg84 + } #[doc = "0x58 - STG SYSCONSAIF SYSCFG 88"] - pub stg_sysconsaif_syscfg88: STG_SYSCONSAIF_SYSCFG88, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg88(&self) -> &STG_SYSCONSAIF_SYSCFG88 { + &self.stg_sysconsaif_syscfg88 + } #[doc = "0x5c - STG SYSCONSAIF SYSCFG 92"] - pub stg_sysconsaif_syscfg92: STG_SYSCONSAIF_SYSCFG92, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg92(&self) -> &STG_SYSCONSAIF_SYSCFG92 { + &self.stg_sysconsaif_syscfg92 + } #[doc = "0x60 - STG SYSCONSAIF SYSCFG 96"] - pub stg_sysconsaif_syscfg96: STG_SYSCONSAIF_SYSCFG96, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg96(&self) -> &STG_SYSCONSAIF_SYSCFG96 { + &self.stg_sysconsaif_syscfg96 + } #[doc = "0x64 - STG SYSCONSAIF SYSCFG 100"] - pub stg_sysconsaif_syscfg100: STG_SYSCONSAIF_SYSCFG100, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg100(&self) -> &STG_SYSCONSAIF_SYSCFG100 { + &self.stg_sysconsaif_syscfg100 + } #[doc = "0x68 - STG SYSCONSAIF SYSCFG 104"] - pub stg_sysconsaif_syscfg104: STG_SYSCONSAIF_SYSCFG104, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg104(&self) -> &STG_SYSCONSAIF_SYSCFG104 { + &self.stg_sysconsaif_syscfg104 + } #[doc = "0x6c - STG SYSCONSAIF SYSCFG 108"] - pub stg_sysconsaif_syscfg108: STG_SYSCONSAIF_SYSCFG108, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg108(&self) -> &STG_SYSCONSAIF_SYSCFG108 { + &self.stg_sysconsaif_syscfg108 + } #[doc = "0x70 - STG SYSCONSAIF SYSCFG 112"] - pub stg_sysconsaif_syscfg112: STG_SYSCONSAIF_SYSCFG112, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg112(&self) -> &STG_SYSCONSAIF_SYSCFG112 { + &self.stg_sysconsaif_syscfg112 + } #[doc = "0x74 - STG SYSCONSAIF SYSCFG 116"] - pub stg_sysconsaif_syscfg116: STG_SYSCONSAIF_SYSCFG116, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg116(&self) -> &STG_SYSCONSAIF_SYSCFG116 { + &self.stg_sysconsaif_syscfg116 + } #[doc = "0x78 - STG SYSCONSAIF SYSCFG 120"] - pub stg_sysconsaif_syscfg120: STG_SYSCONSAIF_SYSCFG120, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg120(&self) -> &STG_SYSCONSAIF_SYSCFG120 { + &self.stg_sysconsaif_syscfg120 + } #[doc = "0x7c - STG SYSCONSAIF SYSCFG 124"] - pub stg_sysconsaif_syscfg124: STG_SYSCONSAIF_SYSCFG124, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg124(&self) -> &STG_SYSCONSAIF_SYSCFG124 { + &self.stg_sysconsaif_syscfg124 + } #[doc = "0x80 - STG SYSCONSAIF SYSCFG 128"] - pub stg_sysconsaif_syscfg128: STG_SYSCONSAIF_SYSCFG128, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg128(&self) -> &STG_SYSCONSAIF_SYSCFG128 { + &self.stg_sysconsaif_syscfg128 + } #[doc = "0x84 - STG SYSCONSAIF SYSCFG 132"] - pub stg_sysconsaif_syscfg132: STG_SYSCONSAIF_SYSCFG132, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg132(&self) -> &STG_SYSCONSAIF_SYSCFG132 { + &self.stg_sysconsaif_syscfg132 + } #[doc = "0x88 - STG SYSCONSAIF SYSCFG 136"] - pub stg_sysconsaif_syscfg136: STG_SYSCONSAIF_SYSCFG136, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg136(&self) -> &STG_SYSCONSAIF_SYSCFG136 { + &self.stg_sysconsaif_syscfg136 + } #[doc = "0x8c - STG SYSCONSAIF SYSCFG 140"] - pub stg_sysconsaif_syscfg140: STG_SYSCONSAIF_SYSCFG140, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg140(&self) -> &STG_SYSCONSAIF_SYSCFG140 { + &self.stg_sysconsaif_syscfg140 + } #[doc = "0x90 - STG SYSCONSAIF SYSCFG 144"] - pub stg_sysconsaif_syscfg144: STG_SYSCONSAIF_SYSCFG144, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg144(&self) -> &STG_SYSCONSAIF_SYSCFG144 { + &self.stg_sysconsaif_syscfg144 + } #[doc = "0x94 - STG SYSCONSAIF SYSCFG 148"] - pub stg_sysconsaif_syscfg148: STG_SYSCONSAIF_SYSCFG148, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg148(&self) -> &STG_SYSCONSAIF_SYSCFG148 { + &self.stg_sysconsaif_syscfg148 + } #[doc = "0x98 - STG SYSCONSAIF SYSCFG 152"] - pub stg_sysconsaif_syscfg152: STG_SYSCONSAIF_SYSCFG152, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg152(&self) -> &STG_SYSCONSAIF_SYSCFG152 { + &self.stg_sysconsaif_syscfg152 + } #[doc = "0x9c - STG SYSCONSAIF SYSCFG 156"] - pub stg_sysconsaif_syscfg156: STG_SYSCONSAIF_SYSCFG156, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg156(&self) -> &STG_SYSCONSAIF_SYSCFG156 { + &self.stg_sysconsaif_syscfg156 + } #[doc = "0xa0 - STG SYSCONSAIF SYSCFG 160"] - pub stg_sysconsaif_syscfg160: STG_SYSCONSAIF_SYSCFG160, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg160(&self) -> &STG_SYSCONSAIF_SYSCFG160 { + &self.stg_sysconsaif_syscfg160 + } #[doc = "0xa4 - STG SYSCONSAIF SYSCFG 164"] - pub stg_sysconsaif_syscfg164: STG_SYSCONSAIF_SYSCFG164, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg164(&self) -> &STG_SYSCONSAIF_SYSCFG164 { + &self.stg_sysconsaif_syscfg164 + } #[doc = "0xa8 - STG SYSCONSAIF SYSCFG 168"] - pub stg_sysconsaif_syscfg168: STG_SYSCONSAIF_SYSCFG168, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg168(&self) -> &STG_SYSCONSAIF_SYSCFG168 { + &self.stg_sysconsaif_syscfg168 + } #[doc = "0xac - STG SYSCONSAIF SYSCFG 172"] - pub stg_sysconsaif_syscfg172: STG_SYSCONSAIF_SYSCFG172, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg172(&self) -> &STG_SYSCONSAIF_SYSCFG172 { + &self.stg_sysconsaif_syscfg172 + } #[doc = "0xb0 - STG SYSCONSAIF SYSCFG 176"] - pub stg_sysconsaif_syscfg176: STG_SYSCONSAIF_SYSCFG176, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg176(&self) -> &STG_SYSCONSAIF_SYSCFG176 { + &self.stg_sysconsaif_syscfg176 + } #[doc = "0xb4 - STG SYSCONSAIF SYSCFG 180"] - pub stg_sysconsaif_syscfg180: STG_SYSCONSAIF_SYSCFG180, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg180(&self) -> &STG_SYSCONSAIF_SYSCFG180 { + &self.stg_sysconsaif_syscfg180 + } #[doc = "0xb8 - STG SYSCONSAIF SYSCFG 184"] - pub stg_sysconsaif_syscfg184: STG_SYSCONSAIF_SYSCFG184, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg184(&self) -> &STG_SYSCONSAIF_SYSCFG184 { + &self.stg_sysconsaif_syscfg184 + } #[doc = "0xbc - STG SYSCONSAIF SYSCFG 188"] - pub stg_sysconsaif_syscfg188: STG_SYSCONSAIF_SYSCFG188, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg188(&self) -> &STG_SYSCONSAIF_SYSCFG188 { + &self.stg_sysconsaif_syscfg188 + } #[doc = "0xc0 - STG SYSCONSAIF SYSCFG 192"] - pub stg_sysconsaif_syscfg192: STG_SYSCONSAIF_SYSCFG192, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg192(&self) -> &STG_SYSCONSAIF_SYSCFG192 { + &self.stg_sysconsaif_syscfg192 + } #[doc = "0xc4 - STG SYSCONSAIF SYSCFG 196"] - pub stg_sysconsaif_syscfg196: STG_SYSCONSAIF_SYSCFG196, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg196(&self) -> &STG_SYSCONSAIF_SYSCFG196 { + &self.stg_sysconsaif_syscfg196 + } #[doc = "0xc8 - STG SYSCONSAIF SYSCFG 200"] - pub stg_sysconsaif_syscfg200: STG_SYSCONSAIF_SYSCFG200, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg200(&self) -> &STG_SYSCONSAIF_SYSCFG200 { + &self.stg_sysconsaif_syscfg200 + } #[doc = "0xcc - STG SYSCONSAIF SYSCFG 204"] - pub stg_sysconsaif_syscfg204: STG_SYSCONSAIF_SYSCFG204, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg204(&self) -> &STG_SYSCONSAIF_SYSCFG204 { + &self.stg_sysconsaif_syscfg204 + } #[doc = "0xd0 - STG SYSCONSAIF SYSCFG 208"] - pub stg_sysconsaif_syscfg208: STG_SYSCONSAIF_SYSCFG208, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg208(&self) -> &STG_SYSCONSAIF_SYSCFG208 { + &self.stg_sysconsaif_syscfg208 + } #[doc = "0xd4 - STG SYSCONSAIF SYSCFG 212"] - pub stg_sysconsaif_syscfg212: STG_SYSCONSAIF_SYSCFG212, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg212(&self) -> &STG_SYSCONSAIF_SYSCFG212 { + &self.stg_sysconsaif_syscfg212 + } #[doc = "0xd8 - STG SYSCONSAIF SYSCFG 216"] - pub stg_sysconsaif_syscfg216: STG_SYSCONSAIF_SYSCFG216, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg216(&self) -> &STG_SYSCONSAIF_SYSCFG216 { + &self.stg_sysconsaif_syscfg216 + } #[doc = "0xdc - STG SYSCONSAIF SYSCFG 220"] - pub stg_sysconsaif_syscfg220: STG_SYSCONSAIF_SYSCFG220, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg220(&self) -> &STG_SYSCONSAIF_SYSCFG220 { + &self.stg_sysconsaif_syscfg220 + } #[doc = "0xe0 - STG SYSCONSAIF SYSCFG 224"] - pub stg_sysconsaif_syscfg224: STG_SYSCONSAIF_SYSCFG224, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg224(&self) -> &STG_SYSCONSAIF_SYSCFG224 { + &self.stg_sysconsaif_syscfg224 + } #[doc = "0xe4 - STG SYSCONSAIF SYSCFG 228"] - pub stg_sysconsaif_syscfg228: STG_SYSCONSAIF_SYSCFG228, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg228(&self) -> &STG_SYSCONSAIF_SYSCFG228 { + &self.stg_sysconsaif_syscfg228 + } #[doc = "0xe8 - STG SYSCONSAIF SYSCFG 232"] - pub stg_sysconsaif_syscfg232: STG_SYSCONSAIF_SYSCFG232, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg232(&self) -> &STG_SYSCONSAIF_SYSCFG232 { + &self.stg_sysconsaif_syscfg232 + } #[doc = "0xec - STG SYSCONSAIF SYSCFG 236"] - pub stg_sysconsaif_syscfg236: STG_SYSCONSAIF_SYSCFG236, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg236(&self) -> &STG_SYSCONSAIF_SYSCFG236 { + &self.stg_sysconsaif_syscfg236 + } #[doc = "0xf0 - STG SYSCONSAIF SYSCFG 240"] - pub stg_sysconsaif_syscfg240: STG_SYSCONSAIF_SYSCFG240, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg240(&self) -> &STG_SYSCONSAIF_SYSCFG240 { + &self.stg_sysconsaif_syscfg240 + } #[doc = "0xf4 - STG SYSCONSAIF SYSCFG 244"] - pub stg_sysconsaif_syscfg244: STG_SYSCONSAIF_SYSCFG244, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg244(&self) -> &STG_SYSCONSAIF_SYSCFG244 { + &self.stg_sysconsaif_syscfg244 + } #[doc = "0xf8 - STG SYSCONSAIF SYSCFG 248"] - pub stg_sysconsaif_syscfg248: STG_SYSCONSAIF_SYSCFG248, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg248(&self) -> &STG_SYSCONSAIF_SYSCFG248 { + &self.stg_sysconsaif_syscfg248 + } #[doc = "0xfc - STG SYSCONSAIF SYSCFG 252"] - pub stg_sysconsaif_syscfg252: STG_SYSCONSAIF_SYSCFG252, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg252(&self) -> &STG_SYSCONSAIF_SYSCFG252 { + &self.stg_sysconsaif_syscfg252 + } #[doc = "0x100 - STG SYSCONSAIF SYSCFG 256"] - pub stg_sysconsaif_syscfg256: STG_SYSCONSAIF_SYSCFG256, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg256(&self) -> &STG_SYSCONSAIF_SYSCFG256 { + &self.stg_sysconsaif_syscfg256 + } #[doc = "0x104 - STG SYSCONSAIF SYSCFG 260"] - pub stg_sysconsaif_syscfg260: STG_SYSCONSAIF_SYSCFG260, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg260(&self) -> &STG_SYSCONSAIF_SYSCFG260 { + &self.stg_sysconsaif_syscfg260 + } #[doc = "0x108 - STG SYSCONSAIF SYSCFG 264"] - pub stg_sysconsaif_syscfg264: STG_SYSCONSAIF_SYSCFG264, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg264(&self) -> &STG_SYSCONSAIF_SYSCFG264 { + &self.stg_sysconsaif_syscfg264 + } #[doc = "0x10c - STG SYSCONSAIF SYSCFG 268"] - pub stg_sysconsaif_syscfg268: STG_SYSCONSAIF_SYSCFG268, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg268(&self) -> &STG_SYSCONSAIF_SYSCFG268 { + &self.stg_sysconsaif_syscfg268 + } #[doc = "0x110 - STG SYSCONSAIF SYSCFG 272"] - pub stg_sysconsaif_syscfg272: STG_SYSCONSAIF_SYSCFG272, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg272(&self) -> &STG_SYSCONSAIF_SYSCFG272 { + &self.stg_sysconsaif_syscfg272 + } #[doc = "0x114 - STG SYSCONSAIF SYSCFG 276"] - pub stg_sysconsaif_syscfg276: STG_SYSCONSAIF_SYSCFG276, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg276(&self) -> &STG_SYSCONSAIF_SYSCFG276 { + &self.stg_sysconsaif_syscfg276 + } #[doc = "0x118 - STG SYSCONSAIF SYSCFG 280"] - pub stg_sysconsaif_syscfg280: STG_SYSCONSAIF_SYSCFG280, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg280(&self) -> &STG_SYSCONSAIF_SYSCFG280 { + &self.stg_sysconsaif_syscfg280 + } #[doc = "0x11c - STG SYSCONSAIF SYSCFG 284"] - pub stg_sysconsaif_syscfg284: STG_SYSCONSAIF_SYSCFG284, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg284(&self) -> &STG_SYSCONSAIF_SYSCFG284 { + &self.stg_sysconsaif_syscfg284 + } #[doc = "0x120 - STG SYSCONSAIF SYSCFG 288"] - pub stg_sysconsaif_syscfg288: STG_SYSCONSAIF_SYSCFG288, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg288(&self) -> &STG_SYSCONSAIF_SYSCFG288 { + &self.stg_sysconsaif_syscfg288 + } #[doc = "0x124 - STG SYSCONSAIF SYSCFG 292"] - pub stg_sysconsaif_syscfg292: STG_SYSCONSAIF_SYSCFG292, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg292(&self) -> &STG_SYSCONSAIF_SYSCFG292 { + &self.stg_sysconsaif_syscfg292 + } #[doc = "0x128 - STG SYSCONSAIF SYSCFG 296"] - pub stg_sysconsaif_syscfg296: STG_SYSCONSAIF_SYSCFG296, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg296(&self) -> &STG_SYSCONSAIF_SYSCFG296 { + &self.stg_sysconsaif_syscfg296 + } #[doc = "0x12c - STG SYSCONSAIF SYSCFG 300"] - pub stg_sysconsaif_syscfg300: STG_SYSCONSAIF_SYSCFG300, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg300(&self) -> &STG_SYSCONSAIF_SYSCFG300 { + &self.stg_sysconsaif_syscfg300 + } #[doc = "0x130 - STG SYSCONSAIF SYSCFG 304"] - pub stg_sysconsaif_syscfg304: STG_SYSCONSAIF_SYSCFG304, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg304(&self) -> &STG_SYSCONSAIF_SYSCFG304 { + &self.stg_sysconsaif_syscfg304 + } #[doc = "0x134 - STG SYSCONSAIF SYSCFG 308"] - pub stg_sysconsaif_syscfg308: STG_SYSCONSAIF_SYSCFG308, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg308(&self) -> &STG_SYSCONSAIF_SYSCFG308 { + &self.stg_sysconsaif_syscfg308 + } #[doc = "0x138 - STG SYSCONSAIF SYSCFG 312"] - pub stg_sysconsaif_syscfg312: STG_SYSCONSAIF_SYSCFG312, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg312(&self) -> &STG_SYSCONSAIF_SYSCFG312 { + &self.stg_sysconsaif_syscfg312 + } #[doc = "0x13c - STG SYSCONSAIF SYSCFG 316"] - pub stg_sysconsaif_syscfg316: STG_SYSCONSAIF_SYSCFG316, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg316(&self) -> &STG_SYSCONSAIF_SYSCFG316 { + &self.stg_sysconsaif_syscfg316 + } #[doc = "0x140 - STG SYSCONSAIF SYSCFG 320"] - pub stg_sysconsaif_syscfg320: STG_SYSCONSAIF_SYSCFG320, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg320(&self) -> &STG_SYSCONSAIF_SYSCFG320 { + &self.stg_sysconsaif_syscfg320 + } #[doc = "0x144 - STG SYSCONSAIF SYSCFG 324"] - pub stg_sysconsaif_syscfg324: STG_SYSCONSAIF_SYSCFG324, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg324(&self) -> &STG_SYSCONSAIF_SYSCFG324 { + &self.stg_sysconsaif_syscfg324 + } #[doc = "0x148 - STG SYSCONSAIF SYSCFG 328"] - pub stg_sysconsaif_syscfg328: STG_SYSCONSAIF_SYSCFG328, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg328(&self) -> &STG_SYSCONSAIF_SYSCFG328 { + &self.stg_sysconsaif_syscfg328 + } #[doc = "0x14c - STG SYSCONSAIF SYSCFG 332"] - pub stg_sysconsaif_syscfg332: STG_SYSCONSAIF_SYSCFG332, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg332(&self) -> &STG_SYSCONSAIF_SYSCFG332 { + &self.stg_sysconsaif_syscfg332 + } #[doc = "0x150 - STG SYSCONSAIF SYSCFG 336"] - pub stg_sysconsaif_syscfg336: STG_SYSCONSAIF_SYSCFG336, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg336(&self) -> &STG_SYSCONSAIF_SYSCFG336 { + &self.stg_sysconsaif_syscfg336 + } #[doc = "0x154 - STG SYSCONSAIF SYSCFG 340"] - pub stg_sysconsaif_syscfg340: STG_SYSCONSAIF_SYSCFG340, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg340(&self) -> &STG_SYSCONSAIF_SYSCFG340 { + &self.stg_sysconsaif_syscfg340 + } #[doc = "0x158 - STG SYSCONSAIF SYSCFG 344"] - pub stg_sysconsaif_syscfg344: STG_SYSCONSAIF_SYSCFG344, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg344(&self) -> &STG_SYSCONSAIF_SYSCFG344 { + &self.stg_sysconsaif_syscfg344 + } #[doc = "0x15c - STG SYSCONSAIF SYSCFG 348"] - pub stg_sysconsaif_syscfg348: STG_SYSCONSAIF_SYSCFG348, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg348(&self) -> &STG_SYSCONSAIF_SYSCFG348 { + &self.stg_sysconsaif_syscfg348 + } #[doc = "0x160 - STG SYSCONSAIF SYSCFG 352"] - pub stg_sysconsaif_syscfg352: STG_SYSCONSAIF_SYSCFG352, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg352(&self) -> &STG_SYSCONSAIF_SYSCFG352 { + &self.stg_sysconsaif_syscfg352 + } #[doc = "0x164 - STG SYSCONSAIF SYSCFG 356"] - pub stg_sysconsaif_syscfg356: STG_SYSCONSAIF_SYSCFG356, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg356(&self) -> &STG_SYSCONSAIF_SYSCFG356 { + &self.stg_sysconsaif_syscfg356 + } #[doc = "0x168 - STG SYSCONSAIF SYSCFG 360"] - pub stg_sysconsaif_syscfg360: STG_SYSCONSAIF_SYSCFG360, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg360(&self) -> &STG_SYSCONSAIF_SYSCFG360 { + &self.stg_sysconsaif_syscfg360 + } #[doc = "0x16c - STG SYSCONSAIF SYSCFG 364"] - pub stg_sysconsaif_syscfg364: STG_SYSCONSAIF_SYSCFG364, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg364(&self) -> &STG_SYSCONSAIF_SYSCFG364 { + &self.stg_sysconsaif_syscfg364 + } #[doc = "0x170 - STG SYSCONSAIF SYSCFG 368"] - pub stg_sysconsaif_syscfg368: STG_SYSCONSAIF_SYSCFG368, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg368(&self) -> &STG_SYSCONSAIF_SYSCFG368 { + &self.stg_sysconsaif_syscfg368 + } #[doc = "0x174 - STG SYSCONSAIF SYSCFG 372"] - pub stg_sysconsaif_syscfg372: STG_SYSCONSAIF_SYSCFG372, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg372(&self) -> &STG_SYSCONSAIF_SYSCFG372 { + &self.stg_sysconsaif_syscfg372 + } #[doc = "0x178 - STG SYSCONSAIF SYSCFG 376"] - pub stg_sysconsaif_syscfg376: STG_SYSCONSAIF_SYSCFG376, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg376(&self) -> &STG_SYSCONSAIF_SYSCFG376 { + &self.stg_sysconsaif_syscfg376 + } #[doc = "0x17c - STG SYSCONSAIF SYSCFG 380"] - pub stg_sysconsaif_syscfg380: STG_SYSCONSAIF_SYSCFG380, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg380(&self) -> &STG_SYSCONSAIF_SYSCFG380 { + &self.stg_sysconsaif_syscfg380 + } #[doc = "0x180 - STG SYSCONSAIF SYSCFG 384"] - pub stg_sysconsaif_syscfg384: STG_SYSCONSAIF_SYSCFG384, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg384(&self) -> &STG_SYSCONSAIF_SYSCFG384 { + &self.stg_sysconsaif_syscfg384 + } #[doc = "0x184 - STG SYSCONSAIF SYSCFG 388"] - pub stg_sysconsaif_syscfg388: STG_SYSCONSAIF_SYSCFG388, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg388(&self) -> &STG_SYSCONSAIF_SYSCFG388 { + &self.stg_sysconsaif_syscfg388 + } #[doc = "0x188 - STG SYSCONSAIF SYSCFG 392"] - pub stg_sysconsaif_syscfg392: STG_SYSCONSAIF_SYSCFG392, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg392(&self) -> &STG_SYSCONSAIF_SYSCFG392 { + &self.stg_sysconsaif_syscfg392 + } #[doc = "0x18c - STG SYSCONSAIF SYSCFG 396"] - pub stg_sysconsaif_syscfg396: STG_SYSCONSAIF_SYSCFG396, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg396(&self) -> &STG_SYSCONSAIF_SYSCFG396 { + &self.stg_sysconsaif_syscfg396 + } #[doc = "0x190 - STG SYSCONSAIF SYSCFG 400"] - pub stg_sysconsaif_syscfg400: STG_SYSCONSAIF_SYSCFG400, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg400(&self) -> &STG_SYSCONSAIF_SYSCFG400 { + &self.stg_sysconsaif_syscfg400 + } #[doc = "0x194 - STG SYSCONSAIF SYSCFG 404"] - pub stg_sysconsaif_syscfg404: STG_SYSCONSAIF_SYSCFG404, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg404(&self) -> &STG_SYSCONSAIF_SYSCFG404 { + &self.stg_sysconsaif_syscfg404 + } #[doc = "0x198 - STG SYSCONSAIF SYSCFG 408"] - pub stg_sysconsaif_syscfg408: STG_SYSCONSAIF_SYSCFG408, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg408(&self) -> &STG_SYSCONSAIF_SYSCFG408 { + &self.stg_sysconsaif_syscfg408 + } #[doc = "0x19c - STG SYSCONSAIF SYSCFG 412"] - pub stg_sysconsaif_syscfg412: STG_SYSCONSAIF_SYSCFG412, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg412(&self) -> &STG_SYSCONSAIF_SYSCFG412 { + &self.stg_sysconsaif_syscfg412 + } #[doc = "0x1a0 - STG SYSCONSAIF SYSCFG 416"] - pub stg_sysconsaif_syscfg416: STG_SYSCONSAIF_SYSCFG416, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg416(&self) -> &STG_SYSCONSAIF_SYSCFG416 { + &self.stg_sysconsaif_syscfg416 + } #[doc = "0x1a4 - STG SYSCONSAIF SYSCFG 420"] - pub stg_sysconsaif_syscfg420: STG_SYSCONSAIF_SYSCFG420, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg420(&self) -> &STG_SYSCONSAIF_SYSCFG420 { + &self.stg_sysconsaif_syscfg420 + } #[doc = "0x1a8 - STG SYSCONSAIF SYSCFG 424"] - pub stg_sysconsaif_syscfg424: STG_SYSCONSAIF_SYSCFG424, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg424(&self) -> &STG_SYSCONSAIF_SYSCFG424 { + &self.stg_sysconsaif_syscfg424 + } #[doc = "0x1ac - STG SYSCONSAIF SYSCFG 428"] - pub stg_sysconsaif_syscfg428: STG_SYSCONSAIF_SYSCFG428, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg428(&self) -> &STG_SYSCONSAIF_SYSCFG428 { + &self.stg_sysconsaif_syscfg428 + } #[doc = "0x1b0 - STG SYSCONSAIF SYSCFG 432"] - pub stg_sysconsaif_syscfg432: STG_SYSCONSAIF_SYSCFG432, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg432(&self) -> &STG_SYSCONSAIF_SYSCFG432 { + &self.stg_sysconsaif_syscfg432 + } #[doc = "0x1b4 - STG SYSCONSAIF SYSCFG 436"] - pub stg_sysconsaif_syscfg436: STG_SYSCONSAIF_SYSCFG436, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg436(&self) -> &STG_SYSCONSAIF_SYSCFG436 { + &self.stg_sysconsaif_syscfg436 + } #[doc = "0x1b8 - STG SYSCONSAIF SYSCFG 440"] - pub stg_sysconsaif_syscfg440: STG_SYSCONSAIF_SYSCFG440, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg440(&self) -> &STG_SYSCONSAIF_SYSCFG440 { + &self.stg_sysconsaif_syscfg440 + } #[doc = "0x1bc - STG SYSCONSAIF SYSCFG 444"] - pub stg_sysconsaif_syscfg444: STG_SYSCONSAIF_SYSCFG444, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg444(&self) -> &STG_SYSCONSAIF_SYSCFG444 { + &self.stg_sysconsaif_syscfg444 + } #[doc = "0x1c0 - STG SYSCONSAIF SYSCFG 448"] - pub stg_sysconsaif_syscfg448: STG_SYSCONSAIF_SYSCFG448, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg448(&self) -> &STG_SYSCONSAIF_SYSCFG448 { + &self.stg_sysconsaif_syscfg448 + } #[doc = "0x1c4 - STG SYSCONSAIF SYSCFG 452"] - pub stg_sysconsaif_syscfg452: STG_SYSCONSAIF_SYSCFG452, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg452(&self) -> &STG_SYSCONSAIF_SYSCFG452 { + &self.stg_sysconsaif_syscfg452 + } #[doc = "0x1c8 - STG SYSCONSAIF SYSCFG 456"] - pub stg_sysconsaif_syscfg456: STG_SYSCONSAIF_SYSCFG456, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg456(&self) -> &STG_SYSCONSAIF_SYSCFG456 { + &self.stg_sysconsaif_syscfg456 + } #[doc = "0x1cc - STG SYSCONSAIF SYSCFG 460"] - pub stg_sysconsaif_syscfg460: STG_SYSCONSAIF_SYSCFG460, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg460(&self) -> &STG_SYSCONSAIF_SYSCFG460 { + &self.stg_sysconsaif_syscfg460 + } #[doc = "0x1d0 - STG SYSCONSAIF SYSCFG 464"] - pub stg_sysconsaif_syscfg464: STG_SYSCONSAIF_SYSCFG464, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg464(&self) -> &STG_SYSCONSAIF_SYSCFG464 { + &self.stg_sysconsaif_syscfg464 + } #[doc = "0x1d4 - STG SYSCONSAIF SYSCFG 468"] - pub stg_sysconsaif_syscfg468: STG_SYSCONSAIF_SYSCFG468, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg468(&self) -> &STG_SYSCONSAIF_SYSCFG468 { + &self.stg_sysconsaif_syscfg468 + } #[doc = "0x1d8 - STG SYSCONSAIF SYSCFG 472"] - pub stg_sysconsaif_syscfg472: STG_SYSCONSAIF_SYSCFG472, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg472(&self) -> &STG_SYSCONSAIF_SYSCFG472 { + &self.stg_sysconsaif_syscfg472 + } #[doc = "0x1dc - STG SYSCONSAIF SYSCFG 476"] - pub stg_sysconsaif_syscfg476: STG_SYSCONSAIF_SYSCFG476, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg476(&self) -> &STG_SYSCONSAIF_SYSCFG476 { + &self.stg_sysconsaif_syscfg476 + } #[doc = "0x1e0 - STG SYSCONSAIF SYSCFG 480"] - pub stg_sysconsaif_syscfg480: STG_SYSCONSAIF_SYSCFG480, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg480(&self) -> &STG_SYSCONSAIF_SYSCFG480 { + &self.stg_sysconsaif_syscfg480 + } #[doc = "0x1e4 - STG SYSCONSAIF SYSCFG 484"] - pub stg_sysconsaif_syscfg484: STG_SYSCONSAIF_SYSCFG484, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg484(&self) -> &STG_SYSCONSAIF_SYSCFG484 { + &self.stg_sysconsaif_syscfg484 + } #[doc = "0x1e8 - STG SYSCONSAIF SYSCFG 488"] - pub stg_sysconsaif_syscfg488: STG_SYSCONSAIF_SYSCFG488, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg488(&self) -> &STG_SYSCONSAIF_SYSCFG488 { + &self.stg_sysconsaif_syscfg488 + } #[doc = "0x1ec - STG SYSCONSAIF SYSCFG 492"] - pub stg_sysconsaif_syscfg492: STG_SYSCONSAIF_SYSCFG492, - _reserved124: [u8; 0x04], + #[inline(always)] + pub const fn stg_sysconsaif_syscfg492(&self) -> &STG_SYSCONSAIF_SYSCFG492 { + &self.stg_sysconsaif_syscfg492 + } #[doc = "0x1f4 - STG SYSCONSAIF SYSCFG 500"] - pub stg_sysconsaif_syscfg500: STG_SYSCONSAIF_SYSCFG500, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg500(&self) -> &STG_SYSCONSAIF_SYSCFG500 { + &self.stg_sysconsaif_syscfg500 + } #[doc = "0x1f8 - STG SYSCONSAIF SYSCFG 504"] - pub stg_sysconsaif_syscfg504: STG_SYSCONSAIF_SYSCFG504, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg504(&self) -> &STG_SYSCONSAIF_SYSCFG504 { + &self.stg_sysconsaif_syscfg504 + } #[doc = "0x1fc - STG SYSCONSAIF SYSCFG 508"] - pub stg_sysconsaif_syscfg508: STG_SYSCONSAIF_SYSCFG508, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg508(&self) -> &STG_SYSCONSAIF_SYSCFG508 { + &self.stg_sysconsaif_syscfg508 + } #[doc = "0x200 - STG SYSCONSAIF SYSCFG 512"] - pub stg_sysconsaif_syscfg512: STG_SYSCONSAIF_SYSCFG512, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg512(&self) -> &STG_SYSCONSAIF_SYSCFG512 { + &self.stg_sysconsaif_syscfg512 + } #[doc = "0x204 - STG SYSCONSAIF SYSCFG 516"] - pub stg_sysconsaif_syscfg516: STG_SYSCONSAIF_SYSCFG516, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg516(&self) -> &STG_SYSCONSAIF_SYSCFG516 { + &self.stg_sysconsaif_syscfg516 + } #[doc = "0x208 - STG SYSCONSAIF SYSCFG 520"] - pub stg_sysconsaif_syscfg520: STG_SYSCONSAIF_SYSCFG520, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg520(&self) -> &STG_SYSCONSAIF_SYSCFG520 { + &self.stg_sysconsaif_syscfg520 + } #[doc = "0x20c - STG SYSCONSAIF SYSCFG 524"] - pub stg_sysconsaif_syscfg524: STG_SYSCONSAIF_SYSCFG524, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg524(&self) -> &STG_SYSCONSAIF_SYSCFG524 { + &self.stg_sysconsaif_syscfg524 + } #[doc = "0x210 - STG SYSCONSAIF SYSCFG 528"] - pub stg_sysconsaif_syscfg528: STG_SYSCONSAIF_SYSCFG528, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg528(&self) -> &STG_SYSCONSAIF_SYSCFG528 { + &self.stg_sysconsaif_syscfg528 + } #[doc = "0x214 - STG SYSCONSAIF SYSCFG 532"] - pub stg_sysconsaif_syscfg532: STG_SYSCONSAIF_SYSCFG532, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg532(&self) -> &STG_SYSCONSAIF_SYSCFG532 { + &self.stg_sysconsaif_syscfg532 + } #[doc = "0x218 - STG SYSCONSAIF SYSCFG 536"] - pub stg_sysconsaif_syscfg536: STG_SYSCONSAIF_SYSCFG536, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg536(&self) -> &STG_SYSCONSAIF_SYSCFG536 { + &self.stg_sysconsaif_syscfg536 + } #[doc = "0x21c - STG SYSCONSAIF SYSCFG 540"] - pub stg_sysconsaif_syscfg540: STG_SYSCONSAIF_SYSCFG540, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg540(&self) -> &STG_SYSCONSAIF_SYSCFG540 { + &self.stg_sysconsaif_syscfg540 + } #[doc = "0x220 - STG SYSCONSAIF SYSCFG 544"] - pub stg_sysconsaif_syscfg544: STG_SYSCONSAIF_SYSCFG544, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg544(&self) -> &STG_SYSCONSAIF_SYSCFG544 { + &self.stg_sysconsaif_syscfg544 + } #[doc = "0x224 - STG SYSCONSAIF SYSCFG 548"] - pub stg_sysconsaif_syscfg548: STG_SYSCONSAIF_SYSCFG548, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg548(&self) -> &STG_SYSCONSAIF_SYSCFG548 { + &self.stg_sysconsaif_syscfg548 + } #[doc = "0x228 - STG SYSCONSAIF SYSCFG 552"] - pub stg_sysconsaif_syscfg552: STG_SYSCONSAIF_SYSCFG552, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg552(&self) -> &STG_SYSCONSAIF_SYSCFG552 { + &self.stg_sysconsaif_syscfg552 + } #[doc = "0x22c - STG SYSCONSAIF SYSCFG 556"] - pub stg_sysconsaif_syscfg556: STG_SYSCONSAIF_SYSCFG556, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg556(&self) -> &STG_SYSCONSAIF_SYSCFG556 { + &self.stg_sysconsaif_syscfg556 + } #[doc = "0x230 - STG SYSCONSAIF SYSCFG 560"] - pub stg_sysconsaif_syscfg560: STG_SYSCONSAIF_SYSCFG560, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg560(&self) -> &STG_SYSCONSAIF_SYSCFG560 { + &self.stg_sysconsaif_syscfg560 + } #[doc = "0x234 - STG SYSCONSAIF SYSCFG 564"] - pub stg_sysconsaif_syscfg564: STG_SYSCONSAIF_SYSCFG564, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg564(&self) -> &STG_SYSCONSAIF_SYSCFG564 { + &self.stg_sysconsaif_syscfg564 + } #[doc = "0x238 - STG SYSCONSAIF SYSCFG 568"] - pub stg_sysconsaif_syscfg568: STG_SYSCONSAIF_SYSCFG568, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg568(&self) -> &STG_SYSCONSAIF_SYSCFG568 { + &self.stg_sysconsaif_syscfg568 + } #[doc = "0x23c - STG SYSCONSAIF SYSCFG 572"] - pub stg_sysconsaif_syscfg572: STG_SYSCONSAIF_SYSCFG572, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg572(&self) -> &STG_SYSCONSAIF_SYSCFG572 { + &self.stg_sysconsaif_syscfg572 + } #[doc = "0x240 - STG SYSCONSAIF SYSCFG 576"] - pub stg_sysconsaif_syscfg576: STG_SYSCONSAIF_SYSCFG576, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg576(&self) -> &STG_SYSCONSAIF_SYSCFG576 { + &self.stg_sysconsaif_syscfg576 + } #[doc = "0x244 - STG SYSCONSAIF SYSCFG 580"] - pub stg_sysconsaif_syscfg580: STG_SYSCONSAIF_SYSCFG580, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg580(&self) -> &STG_SYSCONSAIF_SYSCFG580 { + &self.stg_sysconsaif_syscfg580 + } #[doc = "0x248 - STG SYSCONSAIF SYSCFG 584"] - pub stg_sysconsaif_syscfg584: STG_SYSCONSAIF_SYSCFG584, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg584(&self) -> &STG_SYSCONSAIF_SYSCFG584 { + &self.stg_sysconsaif_syscfg584 + } #[doc = "0x24c - STG SYSCONSAIF SYSCFG 588"] - pub stg_sysconsaif_syscfg588: STG_SYSCONSAIF_SYSCFG588, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg588(&self) -> &STG_SYSCONSAIF_SYSCFG588 { + &self.stg_sysconsaif_syscfg588 + } #[doc = "0x250 - STG SYSCONSAIF SYSCFG 592"] - pub stg_sysconsaif_syscfg592: STG_SYSCONSAIF_SYSCFG592, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg592(&self) -> &STG_SYSCONSAIF_SYSCFG592 { + &self.stg_sysconsaif_syscfg592 + } #[doc = "0x254 - STG SYSCONSAIF SYSCFG 596"] - pub stg_sysconsaif_syscfg596: STG_SYSCONSAIF_SYSCFG596, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg596(&self) -> &STG_SYSCONSAIF_SYSCFG596 { + &self.stg_sysconsaif_syscfg596 + } #[doc = "0x258 - STG SYSCONSAIF SYSCFG 600"] - pub stg_sysconsaif_syscfg600: STG_SYSCONSAIF_SYSCFG600, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg600(&self) -> &STG_SYSCONSAIF_SYSCFG600 { + &self.stg_sysconsaif_syscfg600 + } #[doc = "0x25c - STG SYSCONSAIF SYSCFG 604"] - pub stg_sysconsaif_syscfg604: STG_SYSCONSAIF_SYSCFG604, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg604(&self) -> &STG_SYSCONSAIF_SYSCFG604 { + &self.stg_sysconsaif_syscfg604 + } #[doc = "0x260 - STG SYSCONSAIF SYSCFG 608"] - pub stg_sysconsaif_syscfg608: STG_SYSCONSAIF_SYSCFG608, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg608(&self) -> &STG_SYSCONSAIF_SYSCFG608 { + &self.stg_sysconsaif_syscfg608 + } #[doc = "0x264 - STG SYSCONSAIF SYSCFG 612"] - pub stg_sysconsaif_syscfg612: STG_SYSCONSAIF_SYSCFG612, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg612(&self) -> &STG_SYSCONSAIF_SYSCFG612 { + &self.stg_sysconsaif_syscfg612 + } #[doc = "0x268 - STG SYSCONSAIF SYSCFG 616"] - pub stg_sysconsaif_syscfg616: STG_SYSCONSAIF_SYSCFG616, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg616(&self) -> &STG_SYSCONSAIF_SYSCFG616 { + &self.stg_sysconsaif_syscfg616 + } #[doc = "0x26c - STG SYSCONSAIF SYSCFG 620"] - pub stg_sysconsaif_syscfg620: STG_SYSCONSAIF_SYSCFG620, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg620(&self) -> &STG_SYSCONSAIF_SYSCFG620 { + &self.stg_sysconsaif_syscfg620 + } #[doc = "0x270 - STG SYSCONSAIF SYSCFG 624"] - pub stg_sysconsaif_syscfg624: STG_SYSCONSAIF_SYSCFG624, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg624(&self) -> &STG_SYSCONSAIF_SYSCFG624 { + &self.stg_sysconsaif_syscfg624 + } #[doc = "0x274 - STG SYSCONSAIF SYSCFG 628"] - pub stg_sysconsaif_syscfg628: STG_SYSCONSAIF_SYSCFG628, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg628(&self) -> &STG_SYSCONSAIF_SYSCFG628 { + &self.stg_sysconsaif_syscfg628 + } #[doc = "0x278 - STG SYSCONSAIF SYSCFG 632"] - pub stg_sysconsaif_syscfg632: STG_SYSCONSAIF_SYSCFG632, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg632(&self) -> &STG_SYSCONSAIF_SYSCFG632 { + &self.stg_sysconsaif_syscfg632 + } #[doc = "0x27c - STG SYSCONSAIF SYSCFG 636"] - pub stg_sysconsaif_syscfg636: STG_SYSCONSAIF_SYSCFG636, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg636(&self) -> &STG_SYSCONSAIF_SYSCFG636 { + &self.stg_sysconsaif_syscfg636 + } #[doc = "0x280 - STG SYSCONSAIF SYSCFG 640"] - pub stg_sysconsaif_syscfg640: STG_SYSCONSAIF_SYSCFG640, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg640(&self) -> &STG_SYSCONSAIF_SYSCFG640 { + &self.stg_sysconsaif_syscfg640 + } #[doc = "0x284 - STG SYSCONSAIF SYSCFG 644"] - pub stg_sysconsaif_syscfg644: STG_SYSCONSAIF_SYSCFG644, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg644(&self) -> &STG_SYSCONSAIF_SYSCFG644 { + &self.stg_sysconsaif_syscfg644 + } #[doc = "0x288 - STG SYSCONSAIF SYSCFG 648"] - pub stg_sysconsaif_syscfg648: STG_SYSCONSAIF_SYSCFG648, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg648(&self) -> &STG_SYSCONSAIF_SYSCFG648 { + &self.stg_sysconsaif_syscfg648 + } #[doc = "0x28c - STG SYSCONSAIF SYSCFG 652"] - pub stg_sysconsaif_syscfg652: STG_SYSCONSAIF_SYSCFG652, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg652(&self) -> &STG_SYSCONSAIF_SYSCFG652 { + &self.stg_sysconsaif_syscfg652 + } #[doc = "0x290 - STG SYSCONSAIF SYSCFG 656"] - pub stg_sysconsaif_syscfg656: STG_SYSCONSAIF_SYSCFG656, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg656(&self) -> &STG_SYSCONSAIF_SYSCFG656 { + &self.stg_sysconsaif_syscfg656 + } #[doc = "0x294 - STG SYSCONSAIF SYSCFG 660"] - pub stg_sysconsaif_syscfg660: STG_SYSCONSAIF_SYSCFG660, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg660(&self) -> &STG_SYSCONSAIF_SYSCFG660 { + &self.stg_sysconsaif_syscfg660 + } #[doc = "0x298 - STG SYSCONSAIF SYSCFG 664"] - pub stg_sysconsaif_syscfg664: STG_SYSCONSAIF_SYSCFG664, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg664(&self) -> &STG_SYSCONSAIF_SYSCFG664 { + &self.stg_sysconsaif_syscfg664 + } #[doc = "0x29c - STG SYSCONSAIF SYSCFG 668"] - pub stg_sysconsaif_syscfg668: STG_SYSCONSAIF_SYSCFG668, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg668(&self) -> &STG_SYSCONSAIF_SYSCFG668 { + &self.stg_sysconsaif_syscfg668 + } #[doc = "0x2a0 - STG SYSCONSAIF SYSCFG 672"] - pub stg_sysconsaif_syscfg672: STG_SYSCONSAIF_SYSCFG672, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg672(&self) -> &STG_SYSCONSAIF_SYSCFG672 { + &self.stg_sysconsaif_syscfg672 + } #[doc = "0x2a4 - STG SYSCONSAIF SYSCFG 676"] - pub stg_sysconsaif_syscfg676: STG_SYSCONSAIF_SYSCFG676, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg676(&self) -> &STG_SYSCONSAIF_SYSCFG676 { + &self.stg_sysconsaif_syscfg676 + } #[doc = "0x2a8 - STG SYSCONSAIF SYSCFG 680"] - pub stg_sysconsaif_syscfg680: STG_SYSCONSAIF_SYSCFG680, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg680(&self) -> &STG_SYSCONSAIF_SYSCFG680 { + &self.stg_sysconsaif_syscfg680 + } #[doc = "0x2ac - STG SYSCONSAIF SYSCFG 684"] - pub stg_sysconsaif_syscfg684: STG_SYSCONSAIF_SYSCFG684, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg684(&self) -> &STG_SYSCONSAIF_SYSCFG684 { + &self.stg_sysconsaif_syscfg684 + } #[doc = "0x2b0 - STG SYSCONSAIF SYSCFG 688"] - pub stg_sysconsaif_syscfg688: STG_SYSCONSAIF_SYSCFG688, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg688(&self) -> &STG_SYSCONSAIF_SYSCFG688 { + &self.stg_sysconsaif_syscfg688 + } #[doc = "0x2b4 - STG SYSCONSAIF SYSCFG 692"] - pub stg_sysconsaif_syscfg692: STG_SYSCONSAIF_SYSCFG692, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg692(&self) -> &STG_SYSCONSAIF_SYSCFG692 { + &self.stg_sysconsaif_syscfg692 + } #[doc = "0x2b8 - STG SYSCONSAIF SYSCFG 696"] - pub stg_sysconsaif_syscfg696: STG_SYSCONSAIF_SYSCFG696, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg696(&self) -> &STG_SYSCONSAIF_SYSCFG696 { + &self.stg_sysconsaif_syscfg696 + } #[doc = "0x2bc - STG SYSCONSAIF SYSCFG 700"] - pub stg_sysconsaif_syscfg700: STG_SYSCONSAIF_SYSCFG700, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg700(&self) -> &STG_SYSCONSAIF_SYSCFG700 { + &self.stg_sysconsaif_syscfg700 + } #[doc = "0x2c0 - STG SYSCONSAIF SYSCFG 704"] - pub stg_sysconsaif_syscfg704: STG_SYSCONSAIF_SYSCFG704, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg704(&self) -> &STG_SYSCONSAIF_SYSCFG704 { + &self.stg_sysconsaif_syscfg704 + } #[doc = "0x2c4 - STG SYSCONSAIF SYSCFG 708"] - pub stg_sysconsaif_syscfg708: STG_SYSCONSAIF_SYSCFG708, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg708(&self) -> &STG_SYSCONSAIF_SYSCFG708 { + &self.stg_sysconsaif_syscfg708 + } #[doc = "0x2c8 - STG SYSCONSAIF SYSCFG 712"] - pub stg_sysconsaif_syscfg712: STG_SYSCONSAIF_SYSCFG712, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg712(&self) -> &STG_SYSCONSAIF_SYSCFG712 { + &self.stg_sysconsaif_syscfg712 + } #[doc = "0x2cc - STG SYSCONSAIF SYSCFG 716"] - pub stg_sysconsaif_syscfg716: STG_SYSCONSAIF_SYSCFG716, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg716(&self) -> &STG_SYSCONSAIF_SYSCFG716 { + &self.stg_sysconsaif_syscfg716 + } #[doc = "0x2d0 - STG SYSCONSAIF SYSCFG 720"] - pub stg_sysconsaif_syscfg720: STG_SYSCONSAIF_SYSCFG720, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg720(&self) -> &STG_SYSCONSAIF_SYSCFG720 { + &self.stg_sysconsaif_syscfg720 + } #[doc = "0x2d4 - STG SYSCONSAIF SYSCFG 724"] - pub stg_sysconsaif_syscfg724: STG_SYSCONSAIF_SYSCFG724, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg724(&self) -> &STG_SYSCONSAIF_SYSCFG724 { + &self.stg_sysconsaif_syscfg724 + } #[doc = "0x2d8 - STG SYSCONSAIF SYSCFG 728"] - pub stg_sysconsaif_syscfg728: STG_SYSCONSAIF_SYSCFG728, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg728(&self) -> &STG_SYSCONSAIF_SYSCFG728 { + &self.stg_sysconsaif_syscfg728 + } #[doc = "0x2dc - STG SYSCONSAIF SYSCFG 732"] - pub stg_sysconsaif_syscfg732: STG_SYSCONSAIF_SYSCFG732, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg732(&self) -> &STG_SYSCONSAIF_SYSCFG732 { + &self.stg_sysconsaif_syscfg732 + } #[doc = "0x2e0 - STG SYSCONSAIF SYSCFG 736"] - pub stg_sysconsaif_syscfg736: STG_SYSCONSAIF_SYSCFG736, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg736(&self) -> &STG_SYSCONSAIF_SYSCFG736 { + &self.stg_sysconsaif_syscfg736 + } #[doc = "0x2e4 - STG SYSCONSAIF SYSCFG 740"] - pub stg_sysconsaif_syscfg740: STG_SYSCONSAIF_SYSCFG740, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg740(&self) -> &STG_SYSCONSAIF_SYSCFG740 { + &self.stg_sysconsaif_syscfg740 + } #[doc = "0x2e8 - STG SYSCONSAIF SYSCFG 744"] - pub stg_sysconsaif_syscfg744: STG_SYSCONSAIF_SYSCFG744, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg744(&self) -> &STG_SYSCONSAIF_SYSCFG744 { + &self.stg_sysconsaif_syscfg744 + } #[doc = "0x2ec - STG SYSCONSAIF SYSCFG 748"] - pub stg_sysconsaif_syscfg748: STG_SYSCONSAIF_SYSCFG748, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg748(&self) -> &STG_SYSCONSAIF_SYSCFG748 { + &self.stg_sysconsaif_syscfg748 + } #[doc = "0x2f0 - STG SYSCONSAIF SYSCFG 752"] - pub stg_sysconsaif_syscfg752: STG_SYSCONSAIF_SYSCFG752, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg752(&self) -> &STG_SYSCONSAIF_SYSCFG752 { + &self.stg_sysconsaif_syscfg752 + } #[doc = "0x2f4 - STG SYSCONSAIF SYSCFG 756"] - pub stg_sysconsaif_syscfg756: STG_SYSCONSAIF_SYSCFG756, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg756(&self) -> &STG_SYSCONSAIF_SYSCFG756 { + &self.stg_sysconsaif_syscfg756 + } #[doc = "0x2f8 - STG SYSCONSAIF SYSCFG 760"] - pub stg_sysconsaif_syscfg760: STG_SYSCONSAIF_SYSCFG760, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg760(&self) -> &STG_SYSCONSAIF_SYSCFG760 { + &self.stg_sysconsaif_syscfg760 + } #[doc = "0x2fc - STG SYSCONSAIF SYSCFG 764"] - pub stg_sysconsaif_syscfg764: STG_SYSCONSAIF_SYSCFG764, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg764(&self) -> &STG_SYSCONSAIF_SYSCFG764 { + &self.stg_sysconsaif_syscfg764 + } #[doc = "0x300 - STG SYSCONSAIF SYSCFG 768"] - pub stg_sysconsaif_syscfg768: STG_SYSCONSAIF_SYSCFG768, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg768(&self) -> &STG_SYSCONSAIF_SYSCFG768 { + &self.stg_sysconsaif_syscfg768 + } #[doc = "0x304 - STG SYSCONSAIF SYSCFG 772"] - pub stg_sysconsaif_syscfg772: STG_SYSCONSAIF_SYSCFG772, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg772(&self) -> &STG_SYSCONSAIF_SYSCFG772 { + &self.stg_sysconsaif_syscfg772 + } #[doc = "0x308 - STG SYSCONSAIF SYSCFG 776"] - pub stg_sysconsaif_syscfg776: STG_SYSCONSAIF_SYSCFG776, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg776(&self) -> &STG_SYSCONSAIF_SYSCFG776 { + &self.stg_sysconsaif_syscfg776 + } #[doc = "0x30c - STG SYSCONSAIF SYSCFG 780"] - pub stg_sysconsaif_syscfg780: STG_SYSCONSAIF_SYSCFG780, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg780(&self) -> &STG_SYSCONSAIF_SYSCFG780 { + &self.stg_sysconsaif_syscfg780 + } #[doc = "0x310 - STG SYSCONSAIF SYSCFG 784"] - pub stg_sysconsaif_syscfg784: STG_SYSCONSAIF_SYSCFG784, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg784(&self) -> &STG_SYSCONSAIF_SYSCFG784 { + &self.stg_sysconsaif_syscfg784 + } #[doc = "0x314 - STG SYSCONSAIF SYSCFG 788"] - pub stg_sysconsaif_syscfg788: STG_SYSCONSAIF_SYSCFG788, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg788(&self) -> &STG_SYSCONSAIF_SYSCFG788 { + &self.stg_sysconsaif_syscfg788 + } #[doc = "0x318 - STG SYSCONSAIF SYSCFG 792"] - pub stg_sysconsaif_syscfg792: STG_SYSCONSAIF_SYSCFG792, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg792(&self) -> &STG_SYSCONSAIF_SYSCFG792 { + &self.stg_sysconsaif_syscfg792 + } #[doc = "0x31c - STG SYSCONSAIF SYSCFG 796"] - pub stg_sysconsaif_syscfg796: STG_SYSCONSAIF_SYSCFG796, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg796(&self) -> &STG_SYSCONSAIF_SYSCFG796 { + &self.stg_sysconsaif_syscfg796 + } #[doc = "0x320 - STG SYSCONSAIF SYSCFG 800"] - pub stg_sysconsaif_syscfg800: STG_SYSCONSAIF_SYSCFG800, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg800(&self) -> &STG_SYSCONSAIF_SYSCFG800 { + &self.stg_sysconsaif_syscfg800 + } #[doc = "0x324 - STG SYSCONSAIF SYSCFG 804"] - pub stg_sysconsaif_syscfg804: STG_SYSCONSAIF_SYSCFG804, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg804(&self) -> &STG_SYSCONSAIF_SYSCFG804 { + &self.stg_sysconsaif_syscfg804 + } #[doc = "0x328 - STG SYSCONSAIF SYSCFG 808"] - pub stg_sysconsaif_syscfg808: STG_SYSCONSAIF_SYSCFG808, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg808(&self) -> &STG_SYSCONSAIF_SYSCFG808 { + &self.stg_sysconsaif_syscfg808 + } #[doc = "0x32c - STG SYSCONSAIF SYSCFG 812"] - pub stg_sysconsaif_syscfg812: STG_SYSCONSAIF_SYSCFG812, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg812(&self) -> &STG_SYSCONSAIF_SYSCFG812 { + &self.stg_sysconsaif_syscfg812 + } #[doc = "0x330 - STG SYSCONSAIF SYSCFG 816"] - pub stg_sysconsaif_syscfg816: STG_SYSCONSAIF_SYSCFG816, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg816(&self) -> &STG_SYSCONSAIF_SYSCFG816 { + &self.stg_sysconsaif_syscfg816 + } #[doc = "0x334 - STG SYSCONSAIF SYSCFG 820"] - pub stg_sysconsaif_syscfg820: STG_SYSCONSAIF_SYSCFG820, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg820(&self) -> &STG_SYSCONSAIF_SYSCFG820 { + &self.stg_sysconsaif_syscfg820 + } #[doc = "0x338 - STG SYSCONSAIF SYSCFG 824"] - pub stg_sysconsaif_syscfg824: STG_SYSCONSAIF_SYSCFG824, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg824(&self) -> &STG_SYSCONSAIF_SYSCFG824 { + &self.stg_sysconsaif_syscfg824 + } #[doc = "0x33c - STG SYSCONSAIF SYSCFG 828"] - pub stg_sysconsaif_syscfg828: STG_SYSCONSAIF_SYSCFG828, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg828(&self) -> &STG_SYSCONSAIF_SYSCFG828 { + &self.stg_sysconsaif_syscfg828 + } #[doc = "0x340 - STG SYSCONSAIF SYSCFG 832"] - pub stg_sysconsaif_syscfg832: STG_SYSCONSAIF_SYSCFG832, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg832(&self) -> &STG_SYSCONSAIF_SYSCFG832 { + &self.stg_sysconsaif_syscfg832 + } #[doc = "0x344 - STG SYSCONSAIF SYSCFG 836"] - pub stg_sysconsaif_syscfg836: STG_SYSCONSAIF_SYSCFG836, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg836(&self) -> &STG_SYSCONSAIF_SYSCFG836 { + &self.stg_sysconsaif_syscfg836 + } #[doc = "0x348 - STG SYSCONSAIF SYSCFG 840"] - pub stg_sysconsaif_syscfg840: STG_SYSCONSAIF_SYSCFG840, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg840(&self) -> &STG_SYSCONSAIF_SYSCFG840 { + &self.stg_sysconsaif_syscfg840 + } #[doc = "0x34c - STG SYSCONSAIF SYSCFG 844"] - pub stg_sysconsaif_syscfg844: STG_SYSCONSAIF_SYSCFG844, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg844(&self) -> &STG_SYSCONSAIF_SYSCFG844 { + &self.stg_sysconsaif_syscfg844 + } #[doc = "0x350 - STG SYSCONSAIF SYSCFG 848"] - pub stg_sysconsaif_syscfg848: STG_SYSCONSAIF_SYSCFG848, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg848(&self) -> &STG_SYSCONSAIF_SYSCFG848 { + &self.stg_sysconsaif_syscfg848 + } #[doc = "0x354 - STG SYSCONSAIF SYSCFG 852"] - pub stg_sysconsaif_syscfg852: STG_SYSCONSAIF_SYSCFG852, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg852(&self) -> &STG_SYSCONSAIF_SYSCFG852 { + &self.stg_sysconsaif_syscfg852 + } #[doc = "0x358 - STG SYSCONSAIF SYSCFG 856"] - pub stg_sysconsaif_syscfg856: STG_SYSCONSAIF_SYSCFG856, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg856(&self) -> &STG_SYSCONSAIF_SYSCFG856 { + &self.stg_sysconsaif_syscfg856 + } #[doc = "0x35c - STG SYSCONSAIF SYSCFG 860"] - pub stg_sysconsaif_syscfg860: STG_SYSCONSAIF_SYSCFG860, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg860(&self) -> &STG_SYSCONSAIF_SYSCFG860 { + &self.stg_sysconsaif_syscfg860 + } #[doc = "0x360 - STG SYSCONSAIF SYSCFG 864"] - pub stg_sysconsaif_syscfg864: STG_SYSCONSAIF_SYSCFG864, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg864(&self) -> &STG_SYSCONSAIF_SYSCFG864 { + &self.stg_sysconsaif_syscfg864 + } #[doc = "0x364 - STG SYSCONSAIF SYSCFG 868"] - pub stg_sysconsaif_syscfg868: STG_SYSCONSAIF_SYSCFG868, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg868(&self) -> &STG_SYSCONSAIF_SYSCFG868 { + &self.stg_sysconsaif_syscfg868 + } #[doc = "0x368 - STG SYSCONSAIF SYSCFG 872"] - pub stg_sysconsaif_syscfg872: STG_SYSCONSAIF_SYSCFG872, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg872(&self) -> &STG_SYSCONSAIF_SYSCFG872 { + &self.stg_sysconsaif_syscfg872 + } #[doc = "0x36c - STG SYSCONSAIF SYSCFG 876"] - pub stg_sysconsaif_syscfg876: STG_SYSCONSAIF_SYSCFG876, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg876(&self) -> &STG_SYSCONSAIF_SYSCFG876 { + &self.stg_sysconsaif_syscfg876 + } #[doc = "0x370 - STG SYSCONSAIF SYSCFG 880"] - pub stg_sysconsaif_syscfg880: STG_SYSCONSAIF_SYSCFG880, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg880(&self) -> &STG_SYSCONSAIF_SYSCFG880 { + &self.stg_sysconsaif_syscfg880 + } #[doc = "0x374 - STG SYSCONSAIF SYSCFG 884"] - pub stg_sysconsaif_syscfg884: STG_SYSCONSAIF_SYSCFG884, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg884(&self) -> &STG_SYSCONSAIF_SYSCFG884 { + &self.stg_sysconsaif_syscfg884 + } #[doc = "0x378 - STG SYSCONSAIF SYSCFG 888"] - pub stg_sysconsaif_syscfg888: STG_SYSCONSAIF_SYSCFG888, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg888(&self) -> &STG_SYSCONSAIF_SYSCFG888 { + &self.stg_sysconsaif_syscfg888 + } #[doc = "0x37c - STG SYSCONSAIF SYSCFG 892"] - pub stg_sysconsaif_syscfg892: STG_SYSCONSAIF_SYSCFG892, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg892(&self) -> &STG_SYSCONSAIF_SYSCFG892 { + &self.stg_sysconsaif_syscfg892 + } #[doc = "0x380 - STG SYSCONSAIF SYSCFG 896"] - pub stg_sysconsaif_syscfg896: STG_SYSCONSAIF_SYSCFG896, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg896(&self) -> &STG_SYSCONSAIF_SYSCFG896 { + &self.stg_sysconsaif_syscfg896 + } #[doc = "0x384 - STG SYSCONSAIF SYSCFG 900"] - pub stg_sysconsaif_syscfg900: STG_SYSCONSAIF_SYSCFG900, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg900(&self) -> &STG_SYSCONSAIF_SYSCFG900 { + &self.stg_sysconsaif_syscfg900 + } #[doc = "0x388 - STG SYSCONSAIF SYSCFG 904"] - pub stg_sysconsaif_syscfg904: STG_SYSCONSAIF_SYSCFG904, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg904(&self) -> &STG_SYSCONSAIF_SYSCFG904 { + &self.stg_sysconsaif_syscfg904 + } #[doc = "0x38c - STG SYSCONSAIF SYSCFG 908"] - pub stg_sysconsaif_syscfg908: STG_SYSCONSAIF_SYSCFG908, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg908(&self) -> &STG_SYSCONSAIF_SYSCFG908 { + &self.stg_sysconsaif_syscfg908 + } #[doc = "0x390 - STG SYSCONSAIF SYSCFG 912"] - pub stg_sysconsaif_syscfg912: STG_SYSCONSAIF_SYSCFG912, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg912(&self) -> &STG_SYSCONSAIF_SYSCFG912 { + &self.stg_sysconsaif_syscfg912 + } #[doc = "0x394 - STG SYSCONSAIF SYSCFG 916"] - pub stg_sysconsaif_syscfg916: STG_SYSCONSAIF_SYSCFG916, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg916(&self) -> &STG_SYSCONSAIF_SYSCFG916 { + &self.stg_sysconsaif_syscfg916 + } #[doc = "0x398 - STG SYSCONSAIF SYSCFG 920"] - pub stg_sysconsaif_syscfg920: STG_SYSCONSAIF_SYSCFG920, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg920(&self) -> &STG_SYSCONSAIF_SYSCFG920 { + &self.stg_sysconsaif_syscfg920 + } #[doc = "0x39c - STG SYSCONSAIF SYSCFG 924"] - pub stg_sysconsaif_syscfg924: STG_SYSCONSAIF_SYSCFG924, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg924(&self) -> &STG_SYSCONSAIF_SYSCFG924 { + &self.stg_sysconsaif_syscfg924 + } #[doc = "0x3a0 - STG SYSCONSAIF SYSCFG 928"] - pub stg_sysconsaif_syscfg928: STG_SYSCONSAIF_SYSCFG928, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg928(&self) -> &STG_SYSCONSAIF_SYSCFG928 { + &self.stg_sysconsaif_syscfg928 + } #[doc = "0x3a4 - STG SYSCONSAIF SYSCFG 932"] - pub stg_sysconsaif_syscfg932: STG_SYSCONSAIF_SYSCFG932, + #[inline(always)] + pub const fn stg_sysconsaif_syscfg932(&self) -> &STG_SYSCONSAIF_SYSCFG932 { + &self.stg_sysconsaif_syscfg932 + } } -#[doc = "stg_sysconsaif_syscfg0 (rw) register accessor: STG SYSCONSAIF SYSCFG 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg0`] +#[doc = "stg_sysconsaif_syscfg0 (rw) register accessor: STG SYSCONSAIF SYSCFG 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg0`] module"] pub type STG_SYSCONSAIF_SYSCFG0 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 0"] pub mod stg_sysconsaif_syscfg0; -#[doc = "stg_sysconsaif_syscfg4 (rw) register accessor: STG SYSCONSAIF SYSCFG 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg4`] +#[doc = "stg_sysconsaif_syscfg4 (rw) register accessor: STG SYSCONSAIF SYSCFG 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg4`] module"] pub type STG_SYSCONSAIF_SYSCFG4 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 4"] pub mod stg_sysconsaif_syscfg4; -#[doc = "stg_sysconsaif_syscfg8 (rw) register accessor: STG SYSCONSAIF SYSCFG 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg8`] +#[doc = "stg_sysconsaif_syscfg8 (rw) register accessor: STG SYSCONSAIF SYSCFG 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg8`] module"] pub type STG_SYSCONSAIF_SYSCFG8 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 8"] pub mod stg_sysconsaif_syscfg8; -#[doc = "stg_sysconsaif_syscfg12 (rw) register accessor: STG SYSCONSAIF SYSCFG 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg12::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg12`] +#[doc = "stg_sysconsaif_syscfg12 (rw) register accessor: STG SYSCONSAIF SYSCFG 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg12::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg12`] module"] pub type STG_SYSCONSAIF_SYSCFG12 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 12"] pub mod stg_sysconsaif_syscfg12; -#[doc = "stg_sysconsaif_syscfg16 (rw) register accessor: STG SYSCONSAIF SYSCFG 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg16::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg16`] +#[doc = "stg_sysconsaif_syscfg16 (rw) register accessor: STG SYSCONSAIF SYSCFG 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg16::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg16`] module"] pub type STG_SYSCONSAIF_SYSCFG16 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 16"] pub mod stg_sysconsaif_syscfg16; -#[doc = "stg_sysconsaif_syscfg20 (rw) register accessor: STG SYSCONSAIF SYSCFG 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg20::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg20`] +#[doc = "stg_sysconsaif_syscfg20 (rw) register accessor: STG SYSCONSAIF SYSCFG 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg20::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg20`] module"] pub type STG_SYSCONSAIF_SYSCFG20 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 20"] pub mod stg_sysconsaif_syscfg20; -#[doc = "stg_sysconsaif_syscfg24 (rw) register accessor: STG SYSCONSAIF SYSCFG 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg24::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg24`] +#[doc = "stg_sysconsaif_syscfg24 (rw) register accessor: STG SYSCONSAIF SYSCFG 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg24::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg24`] module"] pub type STG_SYSCONSAIF_SYSCFG24 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 24"] pub mod stg_sysconsaif_syscfg24; -#[doc = "stg_sysconsaif_syscfg28 (rw) register accessor: STG SYSCONSAIF SYSCFG 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg28::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg28`] +#[doc = "stg_sysconsaif_syscfg28 (rw) register accessor: STG SYSCONSAIF SYSCFG 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg28::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg28`] module"] pub type STG_SYSCONSAIF_SYSCFG28 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 28"] pub mod stg_sysconsaif_syscfg28; -#[doc = "stg_sysconsaif_syscfg32 (rw) register accessor: STG SYSCONSAIF SYSCFG 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg32::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg32`] +#[doc = "stg_sysconsaif_syscfg32 (rw) register accessor: STG SYSCONSAIF SYSCFG 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg32::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg32`] module"] pub type STG_SYSCONSAIF_SYSCFG32 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 32"] pub mod stg_sysconsaif_syscfg32; -#[doc = "stg_sysconsaif_syscfg36 (rw) register accessor: STG SYSCONSAIF SYSCFG 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg36::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg36`] +#[doc = "stg_sysconsaif_syscfg36 (rw) register accessor: STG SYSCONSAIF SYSCFG 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg36::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg36`] module"] pub type STG_SYSCONSAIF_SYSCFG36 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 36"] pub mod stg_sysconsaif_syscfg36; -#[doc = "stg_sysconsaif_syscfg40 (rw) register accessor: STG SYSCONSAIF SYSCFG 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg40::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg40`] +#[doc = "stg_sysconsaif_syscfg40 (rw) register accessor: STG SYSCONSAIF SYSCFG 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg40::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg40`] module"] pub type STG_SYSCONSAIF_SYSCFG40 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 40"] pub mod stg_sysconsaif_syscfg40; -#[doc = "stg_sysconsaif_syscfg44 (rw) register accessor: STG SYSCONSAIF SYSCFG 44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg44::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg44`] +#[doc = "stg_sysconsaif_syscfg44 (rw) register accessor: STG SYSCONSAIF SYSCFG 44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg44::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg44`] module"] pub type STG_SYSCONSAIF_SYSCFG44 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 44"] pub mod stg_sysconsaif_syscfg44; -#[doc = "stg_sysconsaif_syscfg48 (rw) register accessor: STG SYSCONSAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg48`] +#[doc = "stg_sysconsaif_syscfg48 (rw) register accessor: STG SYSCONSAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg48`] module"] pub type STG_SYSCONSAIF_SYSCFG48 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 48"] pub mod stg_sysconsaif_syscfg48; -#[doc = "stg_sysconsaif_syscfg52 (rw) register accessor: STG SYSCONSAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg52`] +#[doc = "stg_sysconsaif_syscfg52 (rw) register accessor: STG SYSCONSAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg52`] module"] pub type STG_SYSCONSAIF_SYSCFG52 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 52"] pub mod stg_sysconsaif_syscfg52; -#[doc = "stg_sysconsaif_syscfg56 (rw) register accessor: STG SYSCONSAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg56`] +#[doc = "stg_sysconsaif_syscfg56 (rw) register accessor: STG SYSCONSAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg56`] module"] pub type STG_SYSCONSAIF_SYSCFG56 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 56"] pub mod stg_sysconsaif_syscfg56; -#[doc = "stg_sysconsaif_syscfg60 (rw) register accessor: STG SYSCONSAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg60`] +#[doc = "stg_sysconsaif_syscfg60 (rw) register accessor: STG SYSCONSAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg60`] module"] pub type STG_SYSCONSAIF_SYSCFG60 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 60"] pub mod stg_sysconsaif_syscfg60; -#[doc = "stg_sysconsaif_syscfg64 (rw) register accessor: STG SYSCONSAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg64`] +#[doc = "stg_sysconsaif_syscfg64 (rw) register accessor: STG SYSCONSAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg64`] module"] pub type STG_SYSCONSAIF_SYSCFG64 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 64"] pub mod stg_sysconsaif_syscfg64; -#[doc = "stg_sysconsaif_syscfg68 (rw) register accessor: STG SYSCONSAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg68`] +#[doc = "stg_sysconsaif_syscfg68 (rw) register accessor: STG SYSCONSAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg68`] module"] pub type STG_SYSCONSAIF_SYSCFG68 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 68"] pub mod stg_sysconsaif_syscfg68; -#[doc = "stg_sysconsaif_syscfg72 (rw) register accessor: STG SYSCONSAIF SYSCFG 72\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg72::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg72::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg72`] +#[doc = "stg_sysconsaif_syscfg72 (rw) register accessor: STG SYSCONSAIF SYSCFG 72\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg72::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg72::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg72`] module"] pub type STG_SYSCONSAIF_SYSCFG72 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 72"] pub mod stg_sysconsaif_syscfg72; -#[doc = "stg_sysconsaif_syscfg76 (rw) register accessor: STG SYSCONSAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg76`] +#[doc = "stg_sysconsaif_syscfg76 (rw) register accessor: STG SYSCONSAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg76`] module"] pub type STG_SYSCONSAIF_SYSCFG76 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 76"] pub mod stg_sysconsaif_syscfg76; -#[doc = "stg_sysconsaif_syscfg80 (rw) register accessor: STG SYSCONSAIF SYSCFG 80\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg80::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg80::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg80`] +#[doc = "stg_sysconsaif_syscfg80 (rw) register accessor: STG SYSCONSAIF SYSCFG 80\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg80::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg80::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg80`] module"] pub type STG_SYSCONSAIF_SYSCFG80 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 80"] pub mod stg_sysconsaif_syscfg80; -#[doc = "stg_sysconsaif_syscfg84 (rw) register accessor: STG SYSCONSAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg84`] +#[doc = "stg_sysconsaif_syscfg84 (rw) register accessor: STG SYSCONSAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg84`] module"] pub type STG_SYSCONSAIF_SYSCFG84 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 84"] pub mod stg_sysconsaif_syscfg84; -#[doc = "stg_sysconsaif_syscfg88 (rw) register accessor: STG SYSCONSAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg88`] +#[doc = "stg_sysconsaif_syscfg88 (rw) register accessor: STG SYSCONSAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg88`] module"] pub type STG_SYSCONSAIF_SYSCFG88 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 88"] pub mod stg_sysconsaif_syscfg88; -#[doc = "stg_sysconsaif_syscfg92 (rw) register accessor: STG SYSCONSAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg92`] +#[doc = "stg_sysconsaif_syscfg92 (rw) register accessor: STG SYSCONSAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg92`] module"] pub type STG_SYSCONSAIF_SYSCFG92 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 92"] pub mod stg_sysconsaif_syscfg92; -#[doc = "stg_sysconsaif_syscfg96 (rw) register accessor: STG SYSCONSAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg96`] +#[doc = "stg_sysconsaif_syscfg96 (rw) register accessor: STG SYSCONSAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg96`] module"] pub type STG_SYSCONSAIF_SYSCFG96 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 96"] pub mod stg_sysconsaif_syscfg96; -#[doc = "stg_sysconsaif_syscfg100 (rw) register accessor: STG SYSCONSAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg100`] +#[doc = "stg_sysconsaif_syscfg100 (rw) register accessor: STG SYSCONSAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg100`] module"] pub type STG_SYSCONSAIF_SYSCFG100 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 100"] pub mod stg_sysconsaif_syscfg100; -#[doc = "stg_sysconsaif_syscfg104 (rw) register accessor: STG SYSCONSAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg104`] +#[doc = "stg_sysconsaif_syscfg104 (rw) register accessor: STG SYSCONSAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg104`] module"] pub type STG_SYSCONSAIF_SYSCFG104 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 104"] pub mod stg_sysconsaif_syscfg104; -#[doc = "stg_sysconsaif_syscfg108 (rw) register accessor: STG SYSCONSAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg108`] +#[doc = "stg_sysconsaif_syscfg108 (rw) register accessor: STG SYSCONSAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg108`] module"] pub type STG_SYSCONSAIF_SYSCFG108 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 108"] pub mod stg_sysconsaif_syscfg108; -#[doc = "stg_sysconsaif_syscfg112 (rw) register accessor: STG SYSCONSAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg112`] +#[doc = "stg_sysconsaif_syscfg112 (rw) register accessor: STG SYSCONSAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg112`] module"] pub type STG_SYSCONSAIF_SYSCFG112 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 112"] pub mod stg_sysconsaif_syscfg112; -#[doc = "stg_sysconsaif_syscfg116 (rw) register accessor: STG SYSCONSAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg116`] +#[doc = "stg_sysconsaif_syscfg116 (rw) register accessor: STG SYSCONSAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg116`] module"] pub type STG_SYSCONSAIF_SYSCFG116 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 116"] pub mod stg_sysconsaif_syscfg116; -#[doc = "stg_sysconsaif_syscfg120 (rw) register accessor: STG SYSCONSAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg120`] +#[doc = "stg_sysconsaif_syscfg120 (rw) register accessor: STG SYSCONSAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg120`] module"] pub type STG_SYSCONSAIF_SYSCFG120 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 120"] pub mod stg_sysconsaif_syscfg120; -#[doc = "stg_sysconsaif_syscfg124 (rw) register accessor: STG SYSCONSAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg124`] +#[doc = "stg_sysconsaif_syscfg124 (rw) register accessor: STG SYSCONSAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg124`] module"] pub type STG_SYSCONSAIF_SYSCFG124 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 124"] pub mod stg_sysconsaif_syscfg124; -#[doc = "stg_sysconsaif_syscfg128 (rw) register accessor: STG SYSCONSAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg128`] +#[doc = "stg_sysconsaif_syscfg128 (rw) register accessor: STG SYSCONSAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg128`] module"] pub type STG_SYSCONSAIF_SYSCFG128 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 128"] pub mod stg_sysconsaif_syscfg128; -#[doc = "stg_sysconsaif_syscfg132 (rw) register accessor: STG SYSCONSAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg132::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg132::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg132`] +#[doc = "stg_sysconsaif_syscfg132 (rw) register accessor: STG SYSCONSAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg132::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg132::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg132`] module"] pub type STG_SYSCONSAIF_SYSCFG132 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 132"] pub mod stg_sysconsaif_syscfg132; -#[doc = "stg_sysconsaif_syscfg136 (rw) register accessor: STG SYSCONSAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg136`] +#[doc = "stg_sysconsaif_syscfg136 (rw) register accessor: STG SYSCONSAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg136`] module"] pub type STG_SYSCONSAIF_SYSCFG136 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 136"] pub mod stg_sysconsaif_syscfg136; -#[doc = "stg_sysconsaif_syscfg140 (rw) register accessor: STG SYSCONSAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg140::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg140::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg140`] +#[doc = "stg_sysconsaif_syscfg140 (rw) register accessor: STG SYSCONSAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg140::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg140::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg140`] module"] pub type STG_SYSCONSAIF_SYSCFG140 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 140"] pub mod stg_sysconsaif_syscfg140; -#[doc = "stg_sysconsaif_syscfg144 (rw) register accessor: STG SYSCONSAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg144::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg144::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg144`] +#[doc = "stg_sysconsaif_syscfg144 (rw) register accessor: STG SYSCONSAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg144::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg144::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg144`] module"] pub type STG_SYSCONSAIF_SYSCFG144 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 144"] pub mod stg_sysconsaif_syscfg144; -#[doc = "stg_sysconsaif_syscfg148 (rw) register accessor: STG SYSCONSAIF SYSCFG 148\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg148::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg148::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg148`] +#[doc = "stg_sysconsaif_syscfg148 (rw) register accessor: STG SYSCONSAIF SYSCFG 148\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg148::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg148::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg148`] module"] pub type STG_SYSCONSAIF_SYSCFG148 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 148"] pub mod stg_sysconsaif_syscfg148; -#[doc = "stg_sysconsaif_syscfg152 (rw) register accessor: STG SYSCONSAIF SYSCFG 152\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg152::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg152::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg152`] +#[doc = "stg_sysconsaif_syscfg152 (rw) register accessor: STG SYSCONSAIF SYSCFG 152\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg152::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg152::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg152`] module"] pub type STG_SYSCONSAIF_SYSCFG152 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 152"] pub mod stg_sysconsaif_syscfg152; -#[doc = "stg_sysconsaif_syscfg156 (rw) register accessor: STG SYSCONSAIF SYSCFG 156\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg156::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg156::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg156`] +#[doc = "stg_sysconsaif_syscfg156 (rw) register accessor: STG SYSCONSAIF SYSCFG 156\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg156::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg156::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg156`] module"] pub type STG_SYSCONSAIF_SYSCFG156 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 156"] pub mod stg_sysconsaif_syscfg156; -#[doc = "stg_sysconsaif_syscfg160 (rw) register accessor: STG SYSCONSAIF SYSCFG 160\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg160::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg160::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg160`] +#[doc = "stg_sysconsaif_syscfg160 (rw) register accessor: STG SYSCONSAIF SYSCFG 160\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg160::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg160::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg160`] module"] pub type STG_SYSCONSAIF_SYSCFG160 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 160"] pub mod stg_sysconsaif_syscfg160; -#[doc = "stg_sysconsaif_syscfg164 (rw) register accessor: STG SYSCONSAIF SYSCFG 164\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg164::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg164::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg164`] +#[doc = "stg_sysconsaif_syscfg164 (rw) register accessor: STG SYSCONSAIF SYSCFG 164\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg164::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg164::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg164`] module"] pub type STG_SYSCONSAIF_SYSCFG164 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 164"] pub mod stg_sysconsaif_syscfg164; -#[doc = "stg_sysconsaif_syscfg168 (rw) register accessor: STG SYSCONSAIF SYSCFG 168\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg168::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg168::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg168`] +#[doc = "stg_sysconsaif_syscfg168 (rw) register accessor: STG SYSCONSAIF SYSCFG 168\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg168::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg168::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg168`] module"] pub type STG_SYSCONSAIF_SYSCFG168 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 168"] pub mod stg_sysconsaif_syscfg168; -#[doc = "stg_sysconsaif_syscfg172 (rw) register accessor: STG SYSCONSAIF SYSCFG 172\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg172::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg172::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg172`] +#[doc = "stg_sysconsaif_syscfg172 (rw) register accessor: STG SYSCONSAIF SYSCFG 172\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg172::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg172::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg172`] module"] pub type STG_SYSCONSAIF_SYSCFG172 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 172"] pub mod stg_sysconsaif_syscfg172; -#[doc = "stg_sysconsaif_syscfg176 (rw) register accessor: STG SYSCONSAIF SYSCFG 176\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg176::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg176::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg176`] +#[doc = "stg_sysconsaif_syscfg176 (rw) register accessor: STG SYSCONSAIF SYSCFG 176\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg176::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg176::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg176`] module"] pub type STG_SYSCONSAIF_SYSCFG176 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 176"] pub mod stg_sysconsaif_syscfg176; -#[doc = "stg_sysconsaif_syscfg180 (rw) register accessor: STG SYSCONSAIF SYSCFG 180\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg180::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg180::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg180`] +#[doc = "stg_sysconsaif_syscfg180 (rw) register accessor: STG SYSCONSAIF SYSCFG 180\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg180::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg180::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg180`] module"] pub type STG_SYSCONSAIF_SYSCFG180 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 180"] pub mod stg_sysconsaif_syscfg180; -#[doc = "stg_sysconsaif_syscfg184 (rw) register accessor: STG SYSCONSAIF SYSCFG 184\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg184::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg184::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg184`] +#[doc = "stg_sysconsaif_syscfg184 (rw) register accessor: STG SYSCONSAIF SYSCFG 184\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg184::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg184::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg184`] module"] pub type STG_SYSCONSAIF_SYSCFG184 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 184"] pub mod stg_sysconsaif_syscfg184; -#[doc = "stg_sysconsaif_syscfg188 (rw) register accessor: STG SYSCONSAIF SYSCFG 188\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg188::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg188::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg188`] +#[doc = "stg_sysconsaif_syscfg188 (rw) register accessor: STG SYSCONSAIF SYSCFG 188\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg188::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg188::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg188`] module"] pub type STG_SYSCONSAIF_SYSCFG188 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 188"] pub mod stg_sysconsaif_syscfg188; -#[doc = "stg_sysconsaif_syscfg192 (rw) register accessor: STG SYSCONSAIF SYSCFG 192\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg192::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg192::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg192`] +#[doc = "stg_sysconsaif_syscfg192 (rw) register accessor: STG SYSCONSAIF SYSCFG 192\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg192::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg192::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg192`] module"] pub type STG_SYSCONSAIF_SYSCFG192 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 192"] pub mod stg_sysconsaif_syscfg192; -#[doc = "stg_sysconsaif_syscfg196 (rw) register accessor: STG SYSCONSAIF SYSCFG 196\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg196::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg196::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg196`] +#[doc = "stg_sysconsaif_syscfg196 (rw) register accessor: STG SYSCONSAIF SYSCFG 196\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg196::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg196::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg196`] module"] pub type STG_SYSCONSAIF_SYSCFG196 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 196"] pub mod stg_sysconsaif_syscfg196; -#[doc = "stg_sysconsaif_syscfg200 (rw) register accessor: STG SYSCONSAIF SYSCFG 200\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg200::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg200::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg200`] +#[doc = "stg_sysconsaif_syscfg200 (rw) register accessor: STG SYSCONSAIF SYSCFG 200\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg200::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg200::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg200`] module"] pub type STG_SYSCONSAIF_SYSCFG200 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 200"] pub mod stg_sysconsaif_syscfg200; -#[doc = "stg_sysconsaif_syscfg204 (rw) register accessor: STG SYSCONSAIF SYSCFG 204\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg204::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg204::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg204`] +#[doc = "stg_sysconsaif_syscfg204 (rw) register accessor: STG SYSCONSAIF SYSCFG 204\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg204::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg204::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg204`] module"] pub type STG_SYSCONSAIF_SYSCFG204 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 204"] pub mod stg_sysconsaif_syscfg204; -#[doc = "stg_sysconsaif_syscfg208 (rw) register accessor: STG SYSCONSAIF SYSCFG 208\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg208::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg208::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg208`] +#[doc = "stg_sysconsaif_syscfg208 (rw) register accessor: STG SYSCONSAIF SYSCFG 208\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg208::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg208::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg208`] module"] pub type STG_SYSCONSAIF_SYSCFG208 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 208"] pub mod stg_sysconsaif_syscfg208; -#[doc = "stg_sysconsaif_syscfg212 (rw) register accessor: STG SYSCONSAIF SYSCFG 212\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg212::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg212::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg212`] +#[doc = "stg_sysconsaif_syscfg212 (rw) register accessor: STG SYSCONSAIF SYSCFG 212\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg212::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg212::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg212`] module"] pub type STG_SYSCONSAIF_SYSCFG212 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 212"] pub mod stg_sysconsaif_syscfg212; -#[doc = "stg_sysconsaif_syscfg216 (rw) register accessor: STG SYSCONSAIF SYSCFG 216\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg216::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg216::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg216`] +#[doc = "stg_sysconsaif_syscfg216 (rw) register accessor: STG SYSCONSAIF SYSCFG 216\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg216::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg216::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg216`] module"] pub type STG_SYSCONSAIF_SYSCFG216 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 216"] pub mod stg_sysconsaif_syscfg216; -#[doc = "stg_sysconsaif_syscfg220 (rw) register accessor: STG SYSCONSAIF SYSCFG 220\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg220::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg220::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg220`] +#[doc = "stg_sysconsaif_syscfg220 (rw) register accessor: STG SYSCONSAIF SYSCFG 220\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg220::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg220::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg220`] module"] pub type STG_SYSCONSAIF_SYSCFG220 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 220"] pub mod stg_sysconsaif_syscfg220; -#[doc = "stg_sysconsaif_syscfg224 (rw) register accessor: STG SYSCONSAIF SYSCFG 224\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg224::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg224::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg224`] +#[doc = "stg_sysconsaif_syscfg224 (rw) register accessor: STG SYSCONSAIF SYSCFG 224\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg224::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg224::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg224`] module"] pub type STG_SYSCONSAIF_SYSCFG224 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 224"] pub mod stg_sysconsaif_syscfg224; -#[doc = "stg_sysconsaif_syscfg228 (rw) register accessor: STG SYSCONSAIF SYSCFG 228\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg228::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg228::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg228`] +#[doc = "stg_sysconsaif_syscfg228 (rw) register accessor: STG SYSCONSAIF SYSCFG 228\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg228::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg228::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg228`] module"] pub type STG_SYSCONSAIF_SYSCFG228 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 228"] pub mod stg_sysconsaif_syscfg228; -#[doc = "stg_sysconsaif_syscfg232 (rw) register accessor: STG SYSCONSAIF SYSCFG 232\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg232::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg232::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg232`] +#[doc = "stg_sysconsaif_syscfg232 (rw) register accessor: STG SYSCONSAIF SYSCFG 232\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg232::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg232::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg232`] module"] pub type STG_SYSCONSAIF_SYSCFG232 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 232"] pub mod stg_sysconsaif_syscfg232; -#[doc = "stg_sysconsaif_syscfg236 (rw) register accessor: STG SYSCONSAIF SYSCFG 236\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg236::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg236::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg236`] +#[doc = "stg_sysconsaif_syscfg236 (rw) register accessor: STG SYSCONSAIF SYSCFG 236\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg236::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg236::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg236`] module"] pub type STG_SYSCONSAIF_SYSCFG236 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 236"] pub mod stg_sysconsaif_syscfg236; -#[doc = "stg_sysconsaif_syscfg240 (rw) register accessor: STG SYSCONSAIF SYSCFG 240\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg240::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg240::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg240`] +#[doc = "stg_sysconsaif_syscfg240 (rw) register accessor: STG SYSCONSAIF SYSCFG 240\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg240::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg240::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg240`] module"] pub type STG_SYSCONSAIF_SYSCFG240 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 240"] pub mod stg_sysconsaif_syscfg240; -#[doc = "stg_sysconsaif_syscfg244 (rw) register accessor: STG SYSCONSAIF SYSCFG 244\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg244::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg244::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg244`] +#[doc = "stg_sysconsaif_syscfg244 (rw) register accessor: STG SYSCONSAIF SYSCFG 244\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg244::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg244::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg244`] module"] pub type STG_SYSCONSAIF_SYSCFG244 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 244"] pub mod stg_sysconsaif_syscfg244; -#[doc = "stg_sysconsaif_syscfg248 (rw) register accessor: STG SYSCONSAIF SYSCFG 248\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg248::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg248::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg248`] +#[doc = "stg_sysconsaif_syscfg248 (rw) register accessor: STG SYSCONSAIF SYSCFG 248\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg248::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg248::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg248`] module"] pub type STG_SYSCONSAIF_SYSCFG248 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 248"] pub mod stg_sysconsaif_syscfg248; -#[doc = "stg_sysconsaif_syscfg252 (rw) register accessor: STG SYSCONSAIF SYSCFG 252\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg252::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg252::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg252`] +#[doc = "stg_sysconsaif_syscfg252 (rw) register accessor: STG SYSCONSAIF SYSCFG 252\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg252::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg252::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg252`] module"] pub type STG_SYSCONSAIF_SYSCFG252 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 252"] pub mod stg_sysconsaif_syscfg252; -#[doc = "stg_sysconsaif_syscfg256 (rw) register accessor: STG SYSCONSAIF SYSCFG 256\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg256::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg256::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg256`] +#[doc = "stg_sysconsaif_syscfg256 (rw) register accessor: STG SYSCONSAIF SYSCFG 256\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg256::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg256::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg256`] module"] pub type STG_SYSCONSAIF_SYSCFG256 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 256"] pub mod stg_sysconsaif_syscfg256; -#[doc = "stg_sysconsaif_syscfg260 (rw) register accessor: STG SYSCONSAIF SYSCFG 260\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg260::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg260::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg260`] +#[doc = "stg_sysconsaif_syscfg260 (rw) register accessor: STG SYSCONSAIF SYSCFG 260\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg260::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg260::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg260`] module"] pub type STG_SYSCONSAIF_SYSCFG260 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 260"] pub mod stg_sysconsaif_syscfg260; -#[doc = "stg_sysconsaif_syscfg264 (rw) register accessor: STG SYSCONSAIF SYSCFG 264\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg264::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg264::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg264`] +#[doc = "stg_sysconsaif_syscfg264 (rw) register accessor: STG SYSCONSAIF SYSCFG 264\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg264::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg264::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg264`] module"] pub type STG_SYSCONSAIF_SYSCFG264 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 264"] pub mod stg_sysconsaif_syscfg264; -#[doc = "stg_sysconsaif_syscfg268 (rw) register accessor: STG SYSCONSAIF SYSCFG 268\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg268::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg268::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg268`] +#[doc = "stg_sysconsaif_syscfg268 (rw) register accessor: STG SYSCONSAIF SYSCFG 268\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg268::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg268::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg268`] module"] pub type STG_SYSCONSAIF_SYSCFG268 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 268"] pub mod stg_sysconsaif_syscfg268; -#[doc = "stg_sysconsaif_syscfg272 (rw) register accessor: STG SYSCONSAIF SYSCFG 272\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg272::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg272::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg272`] +#[doc = "stg_sysconsaif_syscfg272 (rw) register accessor: STG SYSCONSAIF SYSCFG 272\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg272::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg272::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg272`] module"] pub type STG_SYSCONSAIF_SYSCFG272 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 272"] pub mod stg_sysconsaif_syscfg272; -#[doc = "stg_sysconsaif_syscfg276 (rw) register accessor: STG SYSCONSAIF SYSCFG 276\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg276::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg276::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg276`] +#[doc = "stg_sysconsaif_syscfg276 (rw) register accessor: STG SYSCONSAIF SYSCFG 276\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg276::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg276::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg276`] module"] pub type STG_SYSCONSAIF_SYSCFG276 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 276"] pub mod stg_sysconsaif_syscfg276; -#[doc = "stg_sysconsaif_syscfg280 (rw) register accessor: STG SYSCONSAIF SYSCFG 280\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg280::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg280::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg280`] +#[doc = "stg_sysconsaif_syscfg280 (rw) register accessor: STG SYSCONSAIF SYSCFG 280\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg280::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg280::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg280`] module"] pub type STG_SYSCONSAIF_SYSCFG280 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 280"] pub mod stg_sysconsaif_syscfg280; -#[doc = "stg_sysconsaif_syscfg284 (rw) register accessor: STG SYSCONSAIF SYSCFG 284\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg284::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg284::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg284`] +#[doc = "stg_sysconsaif_syscfg284 (rw) register accessor: STG SYSCONSAIF SYSCFG 284\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg284::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg284::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg284`] module"] pub type STG_SYSCONSAIF_SYSCFG284 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 284"] pub mod stg_sysconsaif_syscfg284; -#[doc = "stg_sysconsaif_syscfg288 (rw) register accessor: STG SYSCONSAIF SYSCFG 288\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg288::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg288::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg288`] +#[doc = "stg_sysconsaif_syscfg288 (rw) register accessor: STG SYSCONSAIF SYSCFG 288\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg288::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg288::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg288`] module"] pub type STG_SYSCONSAIF_SYSCFG288 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 288"] pub mod stg_sysconsaif_syscfg288; -#[doc = "stg_sysconsaif_syscfg292 (rw) register accessor: STG SYSCONSAIF SYSCFG 292\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg292::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg292::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg292`] +#[doc = "stg_sysconsaif_syscfg292 (rw) register accessor: STG SYSCONSAIF SYSCFG 292\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg292::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg292::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg292`] module"] pub type STG_SYSCONSAIF_SYSCFG292 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 292"] pub mod stg_sysconsaif_syscfg292; -#[doc = "stg_sysconsaif_syscfg296 (rw) register accessor: STG SYSCONSAIF SYSCFG 296\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg296::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg296::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg296`] +#[doc = "stg_sysconsaif_syscfg296 (rw) register accessor: STG SYSCONSAIF SYSCFG 296\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg296::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg296::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg296`] module"] pub type STG_SYSCONSAIF_SYSCFG296 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 296"] pub mod stg_sysconsaif_syscfg296; -#[doc = "stg_sysconsaif_syscfg300 (rw) register accessor: STG SYSCONSAIF SYSCFG 300\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg300::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg300::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg300`] +#[doc = "stg_sysconsaif_syscfg300 (rw) register accessor: STG SYSCONSAIF SYSCFG 300\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg300::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg300::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg300`] module"] pub type STG_SYSCONSAIF_SYSCFG300 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 300"] pub mod stg_sysconsaif_syscfg300; -#[doc = "stg_sysconsaif_syscfg304 (rw) register accessor: STG SYSCONSAIF SYSCFG 304\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg304::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg304::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg304`] +#[doc = "stg_sysconsaif_syscfg304 (rw) register accessor: STG SYSCONSAIF SYSCFG 304\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg304::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg304::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg304`] module"] pub type STG_SYSCONSAIF_SYSCFG304 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 304"] pub mod stg_sysconsaif_syscfg304; -#[doc = "stg_sysconsaif_syscfg308 (rw) register accessor: STG SYSCONSAIF SYSCFG 308\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg308::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg308::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg308`] +#[doc = "stg_sysconsaif_syscfg308 (rw) register accessor: STG SYSCONSAIF SYSCFG 308\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg308::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg308::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg308`] module"] pub type STG_SYSCONSAIF_SYSCFG308 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 308"] pub mod stg_sysconsaif_syscfg308; -#[doc = "stg_sysconsaif_syscfg312 (rw) register accessor: STG SYSCONSAIF SYSCFG 312\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg312::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg312::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg312`] +#[doc = "stg_sysconsaif_syscfg312 (rw) register accessor: STG SYSCONSAIF SYSCFG 312\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg312::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg312::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg312`] module"] pub type STG_SYSCONSAIF_SYSCFG312 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 312"] pub mod stg_sysconsaif_syscfg312; -#[doc = "stg_sysconsaif_syscfg316 (rw) register accessor: STG SYSCONSAIF SYSCFG 316\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg316::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg316::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg316`] +#[doc = "stg_sysconsaif_syscfg316 (rw) register accessor: STG SYSCONSAIF SYSCFG 316\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg316::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg316::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg316`] module"] pub type STG_SYSCONSAIF_SYSCFG316 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 316"] pub mod stg_sysconsaif_syscfg316; -#[doc = "stg_sysconsaif_syscfg320 (rw) register accessor: STG SYSCONSAIF SYSCFG 320\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg320::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg320::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg320`] +#[doc = "stg_sysconsaif_syscfg320 (rw) register accessor: STG SYSCONSAIF SYSCFG 320\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg320::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg320::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg320`] module"] pub type STG_SYSCONSAIF_SYSCFG320 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 320"] pub mod stg_sysconsaif_syscfg320; -#[doc = "stg_sysconsaif_syscfg324 (rw) register accessor: STG SYSCONSAIF SYSCFG 324\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg324::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg324::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg324`] +#[doc = "stg_sysconsaif_syscfg324 (rw) register accessor: STG SYSCONSAIF SYSCFG 324\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg324::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg324::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg324`] module"] pub type STG_SYSCONSAIF_SYSCFG324 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 324"] pub mod stg_sysconsaif_syscfg324; -#[doc = "stg_sysconsaif_syscfg328 (rw) register accessor: STG SYSCONSAIF SYSCFG 328\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg328::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg328::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg328`] +#[doc = "stg_sysconsaif_syscfg328 (rw) register accessor: STG SYSCONSAIF SYSCFG 328\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg328::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg328::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg328`] module"] pub type STG_SYSCONSAIF_SYSCFG328 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 328"] pub mod stg_sysconsaif_syscfg328; -#[doc = "stg_sysconsaif_syscfg332 (rw) register accessor: STG SYSCONSAIF SYSCFG 332\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg332::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg332::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg332`] +#[doc = "stg_sysconsaif_syscfg332 (rw) register accessor: STG SYSCONSAIF SYSCFG 332\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg332::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg332::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg332`] module"] pub type STG_SYSCONSAIF_SYSCFG332 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 332"] pub mod stg_sysconsaif_syscfg332; -#[doc = "stg_sysconsaif_syscfg336 (rw) register accessor: STG SYSCONSAIF SYSCFG 336\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg336::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg336::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg336`] +#[doc = "stg_sysconsaif_syscfg336 (rw) register accessor: STG SYSCONSAIF SYSCFG 336\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg336::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg336::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg336`] module"] pub type STG_SYSCONSAIF_SYSCFG336 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 336"] pub mod stg_sysconsaif_syscfg336; -#[doc = "stg_sysconsaif_syscfg340 (rw) register accessor: STG SYSCONSAIF SYSCFG 340\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg340::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg340::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg340`] +#[doc = "stg_sysconsaif_syscfg340 (rw) register accessor: STG SYSCONSAIF SYSCFG 340\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg340::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg340::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg340`] module"] pub type STG_SYSCONSAIF_SYSCFG340 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 340"] pub mod stg_sysconsaif_syscfg340; -#[doc = "stg_sysconsaif_syscfg344 (rw) register accessor: STG SYSCONSAIF SYSCFG 344\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg344::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg344::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg344`] +#[doc = "stg_sysconsaif_syscfg344 (rw) register accessor: STG SYSCONSAIF SYSCFG 344\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg344::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg344::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg344`] module"] pub type STG_SYSCONSAIF_SYSCFG344 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 344"] pub mod stg_sysconsaif_syscfg344; -#[doc = "stg_sysconsaif_syscfg348 (rw) register accessor: STG SYSCONSAIF SYSCFG 348\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg348::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg348::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg348`] +#[doc = "stg_sysconsaif_syscfg348 (rw) register accessor: STG SYSCONSAIF SYSCFG 348\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg348::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg348::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg348`] module"] pub type STG_SYSCONSAIF_SYSCFG348 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 348"] pub mod stg_sysconsaif_syscfg348; -#[doc = "stg_sysconsaif_syscfg352 (rw) register accessor: STG SYSCONSAIF SYSCFG 352\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg352::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg352::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg352`] +#[doc = "stg_sysconsaif_syscfg352 (rw) register accessor: STG SYSCONSAIF SYSCFG 352\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg352::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg352::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg352`] module"] pub type STG_SYSCONSAIF_SYSCFG352 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 352"] pub mod stg_sysconsaif_syscfg352; -#[doc = "stg_sysconsaif_syscfg356 (rw) register accessor: STG SYSCONSAIF SYSCFG 356\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg356::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg356::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg356`] +#[doc = "stg_sysconsaif_syscfg356 (rw) register accessor: STG SYSCONSAIF SYSCFG 356\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg356::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg356::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg356`] module"] pub type STG_SYSCONSAIF_SYSCFG356 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 356"] pub mod stg_sysconsaif_syscfg356; -#[doc = "stg_sysconsaif_syscfg360 (rw) register accessor: STG SYSCONSAIF SYSCFG 360\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg360::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg360::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg360`] +#[doc = "stg_sysconsaif_syscfg360 (rw) register accessor: STG SYSCONSAIF SYSCFG 360\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg360::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg360::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg360`] module"] pub type STG_SYSCONSAIF_SYSCFG360 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 360"] pub mod stg_sysconsaif_syscfg360; -#[doc = "stg_sysconsaif_syscfg364 (rw) register accessor: STG SYSCONSAIF SYSCFG 364\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg364::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg364::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg364`] +#[doc = "stg_sysconsaif_syscfg364 (rw) register accessor: STG SYSCONSAIF SYSCFG 364\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg364::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg364::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg364`] module"] pub type STG_SYSCONSAIF_SYSCFG364 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 364"] pub mod stg_sysconsaif_syscfg364; -#[doc = "stg_sysconsaif_syscfg368 (rw) register accessor: STG SYSCONSAIF SYSCFG 368\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg368::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg368::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg368`] +#[doc = "stg_sysconsaif_syscfg368 (rw) register accessor: STG SYSCONSAIF SYSCFG 368\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg368::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg368::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg368`] module"] pub type STG_SYSCONSAIF_SYSCFG368 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 368"] pub mod stg_sysconsaif_syscfg368; -#[doc = "stg_sysconsaif_syscfg372 (rw) register accessor: STG SYSCONSAIF SYSCFG 372\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg372::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg372::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg372`] +#[doc = "stg_sysconsaif_syscfg372 (rw) register accessor: STG SYSCONSAIF SYSCFG 372\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg372::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg372::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg372`] module"] pub type STG_SYSCONSAIF_SYSCFG372 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 372"] pub mod stg_sysconsaif_syscfg372; -#[doc = "stg_sysconsaif_syscfg376 (rw) register accessor: STG SYSCONSAIF SYSCFG 376\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg376::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg376::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg376`] +#[doc = "stg_sysconsaif_syscfg376 (rw) register accessor: STG SYSCONSAIF SYSCFG 376\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg376::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg376::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg376`] module"] pub type STG_SYSCONSAIF_SYSCFG376 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 376"] pub mod stg_sysconsaif_syscfg376; -#[doc = "stg_sysconsaif_syscfg380 (rw) register accessor: STG SYSCONSAIF SYSCFG 380\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg380::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg380::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg380`] +#[doc = "stg_sysconsaif_syscfg380 (rw) register accessor: STG SYSCONSAIF SYSCFG 380\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg380::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg380::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg380`] module"] pub type STG_SYSCONSAIF_SYSCFG380 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 380"] pub mod stg_sysconsaif_syscfg380; -#[doc = "stg_sysconsaif_syscfg384 (rw) register accessor: STG SYSCONSAIF SYSCFG 384\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg384::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg384::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg384`] +#[doc = "stg_sysconsaif_syscfg384 (rw) register accessor: STG SYSCONSAIF SYSCFG 384\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg384::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg384::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg384`] module"] pub type STG_SYSCONSAIF_SYSCFG384 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 384"] pub mod stg_sysconsaif_syscfg384; -#[doc = "stg_sysconsaif_syscfg388 (rw) register accessor: STG SYSCONSAIF SYSCFG 388\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg388::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg388::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg388`] +#[doc = "stg_sysconsaif_syscfg388 (rw) register accessor: STG SYSCONSAIF SYSCFG 388\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg388::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg388::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg388`] module"] pub type STG_SYSCONSAIF_SYSCFG388 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 388"] pub mod stg_sysconsaif_syscfg388; -#[doc = "stg_sysconsaif_syscfg392 (rw) register accessor: STG SYSCONSAIF SYSCFG 392\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg392::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg392::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg392`] +#[doc = "stg_sysconsaif_syscfg392 (rw) register accessor: STG SYSCONSAIF SYSCFG 392\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg392::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg392::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg392`] module"] pub type STG_SYSCONSAIF_SYSCFG392 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 392"] pub mod stg_sysconsaif_syscfg392; -#[doc = "stg_sysconsaif_syscfg396 (rw) register accessor: STG SYSCONSAIF SYSCFG 396\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg396::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg396::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg396`] +#[doc = "stg_sysconsaif_syscfg396 (rw) register accessor: STG SYSCONSAIF SYSCFG 396\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg396::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg396::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg396`] module"] pub type STG_SYSCONSAIF_SYSCFG396 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 396"] pub mod stg_sysconsaif_syscfg396; -#[doc = "stg_sysconsaif_syscfg400 (rw) register accessor: STG SYSCONSAIF SYSCFG 400\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg400::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg400::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg400`] +#[doc = "stg_sysconsaif_syscfg400 (rw) register accessor: STG SYSCONSAIF SYSCFG 400\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg400::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg400::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg400`] module"] pub type STG_SYSCONSAIF_SYSCFG400 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 400"] pub mod stg_sysconsaif_syscfg400; -#[doc = "stg_sysconsaif_syscfg404 (rw) register accessor: STG SYSCONSAIF SYSCFG 404\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg404::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg404::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg404`] +#[doc = "stg_sysconsaif_syscfg404 (rw) register accessor: STG SYSCONSAIF SYSCFG 404\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg404::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg404::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg404`] module"] pub type STG_SYSCONSAIF_SYSCFG404 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 404"] pub mod stg_sysconsaif_syscfg404; -#[doc = "stg_sysconsaif_syscfg408 (rw) register accessor: STG SYSCONSAIF SYSCFG 408\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg408::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg408::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg408`] +#[doc = "stg_sysconsaif_syscfg408 (rw) register accessor: STG SYSCONSAIF SYSCFG 408\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg408::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg408::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg408`] module"] pub type STG_SYSCONSAIF_SYSCFG408 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 408"] pub mod stg_sysconsaif_syscfg408; -#[doc = "stg_sysconsaif_syscfg412 (rw) register accessor: STG SYSCONSAIF SYSCFG 412\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg412::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg412::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg412`] +#[doc = "stg_sysconsaif_syscfg412 (rw) register accessor: STG SYSCONSAIF SYSCFG 412\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg412::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg412::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg412`] module"] pub type STG_SYSCONSAIF_SYSCFG412 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 412"] pub mod stg_sysconsaif_syscfg412; -#[doc = "stg_sysconsaif_syscfg416 (rw) register accessor: STG SYSCONSAIF SYSCFG 416\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg416::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg416::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg416`] +#[doc = "stg_sysconsaif_syscfg416 (rw) register accessor: STG SYSCONSAIF SYSCFG 416\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg416::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg416::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg416`] module"] pub type STG_SYSCONSAIF_SYSCFG416 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 416"] pub mod stg_sysconsaif_syscfg416; -#[doc = "stg_sysconsaif_syscfg420 (rw) register accessor: STG SYSCONSAIF SYSCFG 420\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg420::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg420::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg420`] +#[doc = "stg_sysconsaif_syscfg420 (rw) register accessor: STG SYSCONSAIF SYSCFG 420\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg420::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg420::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg420`] module"] pub type STG_SYSCONSAIF_SYSCFG420 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 420"] pub mod stg_sysconsaif_syscfg420; -#[doc = "stg_sysconsaif_syscfg424 (rw) register accessor: STG SYSCONSAIF SYSCFG 424\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg424::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg424::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg424`] +#[doc = "stg_sysconsaif_syscfg424 (rw) register accessor: STG SYSCONSAIF SYSCFG 424\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg424::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg424::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg424`] module"] pub type STG_SYSCONSAIF_SYSCFG424 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 424"] pub mod stg_sysconsaif_syscfg424; -#[doc = "stg_sysconsaif_syscfg428 (rw) register accessor: STG SYSCONSAIF SYSCFG 428\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg428::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg428::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg428`] +#[doc = "stg_sysconsaif_syscfg428 (rw) register accessor: STG SYSCONSAIF SYSCFG 428\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg428::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg428::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg428`] module"] pub type STG_SYSCONSAIF_SYSCFG428 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 428"] pub mod stg_sysconsaif_syscfg428; -#[doc = "stg_sysconsaif_syscfg432 (rw) register accessor: STG SYSCONSAIF SYSCFG 432\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg432::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg432::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg432`] +#[doc = "stg_sysconsaif_syscfg432 (rw) register accessor: STG SYSCONSAIF SYSCFG 432\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg432::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg432::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg432`] module"] pub type STG_SYSCONSAIF_SYSCFG432 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 432"] pub mod stg_sysconsaif_syscfg432; -#[doc = "stg_sysconsaif_syscfg436 (rw) register accessor: STG SYSCONSAIF SYSCFG 436\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg436::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg436::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg436`] +#[doc = "stg_sysconsaif_syscfg436 (rw) register accessor: STG SYSCONSAIF SYSCFG 436\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg436::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg436::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg436`] module"] pub type STG_SYSCONSAIF_SYSCFG436 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 436"] pub mod stg_sysconsaif_syscfg436; -#[doc = "stg_sysconsaif_syscfg440 (rw) register accessor: STG SYSCONSAIF SYSCFG 440\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg440::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg440::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg440`] +#[doc = "stg_sysconsaif_syscfg440 (rw) register accessor: STG SYSCONSAIF SYSCFG 440\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg440::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg440::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg440`] module"] pub type STG_SYSCONSAIF_SYSCFG440 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 440"] pub mod stg_sysconsaif_syscfg440; -#[doc = "stg_sysconsaif_syscfg444 (rw) register accessor: STG SYSCONSAIF SYSCFG 444\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg444::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg444::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg444`] +#[doc = "stg_sysconsaif_syscfg444 (rw) register accessor: STG SYSCONSAIF SYSCFG 444\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg444::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg444::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg444`] module"] pub type STG_SYSCONSAIF_SYSCFG444 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 444"] pub mod stg_sysconsaif_syscfg444; -#[doc = "stg_sysconsaif_syscfg448 (rw) register accessor: STG SYSCONSAIF SYSCFG 448\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg448::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg448::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg448`] +#[doc = "stg_sysconsaif_syscfg448 (rw) register accessor: STG SYSCONSAIF SYSCFG 448\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg448::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg448::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg448`] module"] pub type STG_SYSCONSAIF_SYSCFG448 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 448"] pub mod stg_sysconsaif_syscfg448; -#[doc = "stg_sysconsaif_syscfg452 (rw) register accessor: STG SYSCONSAIF SYSCFG 452\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg452::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg452::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg452`] +#[doc = "stg_sysconsaif_syscfg452 (rw) register accessor: STG SYSCONSAIF SYSCFG 452\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg452::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg452::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg452`] module"] pub type STG_SYSCONSAIF_SYSCFG452 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 452"] pub mod stg_sysconsaif_syscfg452; -#[doc = "stg_sysconsaif_syscfg456 (rw) register accessor: STG SYSCONSAIF SYSCFG 456\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg456::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg456::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg456`] +#[doc = "stg_sysconsaif_syscfg456 (rw) register accessor: STG SYSCONSAIF SYSCFG 456\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg456::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg456::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg456`] module"] pub type STG_SYSCONSAIF_SYSCFG456 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 456"] pub mod stg_sysconsaif_syscfg456; -#[doc = "stg_sysconsaif_syscfg460 (rw) register accessor: STG SYSCONSAIF SYSCFG 460\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg460::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg460::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg460`] +#[doc = "stg_sysconsaif_syscfg460 (rw) register accessor: STG SYSCONSAIF SYSCFG 460\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg460::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg460::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg460`] module"] pub type STG_SYSCONSAIF_SYSCFG460 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 460"] pub mod stg_sysconsaif_syscfg460; -#[doc = "stg_sysconsaif_syscfg464 (rw) register accessor: STG SYSCONSAIF SYSCFG 464\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg464::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg464::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg464`] +#[doc = "stg_sysconsaif_syscfg464 (rw) register accessor: STG SYSCONSAIF SYSCFG 464\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg464::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg464::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg464`] module"] pub type STG_SYSCONSAIF_SYSCFG464 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 464"] pub mod stg_sysconsaif_syscfg464; -#[doc = "stg_sysconsaif_syscfg468 (rw) register accessor: STG SYSCONSAIF SYSCFG 468\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg468::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg468::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg468`] +#[doc = "stg_sysconsaif_syscfg468 (rw) register accessor: STG SYSCONSAIF SYSCFG 468\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg468::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg468::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg468`] module"] pub type STG_SYSCONSAIF_SYSCFG468 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 468"] pub mod stg_sysconsaif_syscfg468; -#[doc = "stg_sysconsaif_syscfg472 (rw) register accessor: STG SYSCONSAIF SYSCFG 472\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg472::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg472::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg472`] +#[doc = "stg_sysconsaif_syscfg472 (rw) register accessor: STG SYSCONSAIF SYSCFG 472\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg472::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg472::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg472`] module"] pub type STG_SYSCONSAIF_SYSCFG472 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 472"] pub mod stg_sysconsaif_syscfg472; -#[doc = "stg_sysconsaif_syscfg476 (rw) register accessor: STG SYSCONSAIF SYSCFG 476\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg476::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg476::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg476`] +#[doc = "stg_sysconsaif_syscfg476 (rw) register accessor: STG SYSCONSAIF SYSCFG 476\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg476::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg476::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg476`] module"] pub type STG_SYSCONSAIF_SYSCFG476 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 476"] pub mod stg_sysconsaif_syscfg476; -#[doc = "stg_sysconsaif_syscfg480 (rw) register accessor: STG SYSCONSAIF SYSCFG 480\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg480::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg480::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg480`] +#[doc = "stg_sysconsaif_syscfg480 (rw) register accessor: STG SYSCONSAIF SYSCFG 480\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg480::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg480::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg480`] module"] pub type STG_SYSCONSAIF_SYSCFG480 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 480"] pub mod stg_sysconsaif_syscfg480; -#[doc = "stg_sysconsaif_syscfg484 (rw) register accessor: STG SYSCONSAIF SYSCFG 484\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg484::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg484::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg484`] +#[doc = "stg_sysconsaif_syscfg484 (rw) register accessor: STG SYSCONSAIF SYSCFG 484\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg484::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg484::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg484`] module"] pub type STG_SYSCONSAIF_SYSCFG484 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 484"] pub mod stg_sysconsaif_syscfg484; -#[doc = "stg_sysconsaif_syscfg488 (rw) register accessor: STG SYSCONSAIF SYSCFG 488\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg488::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg488::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg488`] +#[doc = "stg_sysconsaif_syscfg488 (rw) register accessor: STG SYSCONSAIF SYSCFG 488\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg488::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg488::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg488`] module"] pub type STG_SYSCONSAIF_SYSCFG488 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 488"] pub mod stg_sysconsaif_syscfg488; -#[doc = "stg_sysconsaif_syscfg492 (rw) register accessor: STG SYSCONSAIF SYSCFG 492\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg492::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg492::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg492`] +#[doc = "stg_sysconsaif_syscfg492 (rw) register accessor: STG SYSCONSAIF SYSCFG 492\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg492::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg492::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg492`] module"] pub type STG_SYSCONSAIF_SYSCFG492 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 492"] pub mod stg_sysconsaif_syscfg492; -#[doc = "stg_sysconsaif_syscfg500 (rw) register accessor: STG SYSCONSAIF SYSCFG 500\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg500::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg500::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg500`] +#[doc = "stg_sysconsaif_syscfg500 (rw) register accessor: STG SYSCONSAIF SYSCFG 500\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg500::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg500::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg500`] module"] pub type STG_SYSCONSAIF_SYSCFG500 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 500"] pub mod stg_sysconsaif_syscfg500; -#[doc = "stg_sysconsaif_syscfg504 (rw) register accessor: STG SYSCONSAIF SYSCFG 504\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg504::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg504::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg504`] +#[doc = "stg_sysconsaif_syscfg504 (rw) register accessor: STG SYSCONSAIF SYSCFG 504\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg504::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg504::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg504`] module"] pub type STG_SYSCONSAIF_SYSCFG504 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 504"] pub mod stg_sysconsaif_syscfg504; -#[doc = "stg_sysconsaif_syscfg508 (rw) register accessor: STG SYSCONSAIF SYSCFG 508\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg508::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg508::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg508`] +#[doc = "stg_sysconsaif_syscfg508 (rw) register accessor: STG SYSCONSAIF SYSCFG 508\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg508::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg508::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg508`] module"] pub type STG_SYSCONSAIF_SYSCFG508 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 508"] pub mod stg_sysconsaif_syscfg508; -#[doc = "stg_sysconsaif_syscfg512 (rw) register accessor: STG SYSCONSAIF SYSCFG 512\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg512::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg512::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg512`] +#[doc = "stg_sysconsaif_syscfg512 (rw) register accessor: STG SYSCONSAIF SYSCFG 512\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg512::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg512::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg512`] module"] pub type STG_SYSCONSAIF_SYSCFG512 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 512"] pub mod stg_sysconsaif_syscfg512; -#[doc = "stg_sysconsaif_syscfg516 (rw) register accessor: STG SYSCONSAIF SYSCFG 516\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg516::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg516::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg516`] +#[doc = "stg_sysconsaif_syscfg516 (rw) register accessor: STG SYSCONSAIF SYSCFG 516\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg516::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg516::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg516`] module"] pub type STG_SYSCONSAIF_SYSCFG516 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 516"] pub mod stg_sysconsaif_syscfg516; -#[doc = "stg_sysconsaif_syscfg520 (rw) register accessor: STG SYSCONSAIF SYSCFG 520\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg520::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg520::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg520`] +#[doc = "stg_sysconsaif_syscfg520 (rw) register accessor: STG SYSCONSAIF SYSCFG 520\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg520::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg520::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg520`] module"] pub type STG_SYSCONSAIF_SYSCFG520 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 520"] pub mod stg_sysconsaif_syscfg520; -#[doc = "stg_sysconsaif_syscfg524 (rw) register accessor: STG SYSCONSAIF SYSCFG 524\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg524::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg524::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg524`] +#[doc = "stg_sysconsaif_syscfg524 (rw) register accessor: STG SYSCONSAIF SYSCFG 524\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg524::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg524::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg524`] module"] pub type STG_SYSCONSAIF_SYSCFG524 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 524"] pub mod stg_sysconsaif_syscfg524; -#[doc = "stg_sysconsaif_syscfg528 (rw) register accessor: STG SYSCONSAIF SYSCFG 528\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg528::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg528::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg528`] +#[doc = "stg_sysconsaif_syscfg528 (rw) register accessor: STG SYSCONSAIF SYSCFG 528\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg528::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg528::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg528`] module"] pub type STG_SYSCONSAIF_SYSCFG528 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 528"] pub mod stg_sysconsaif_syscfg528; -#[doc = "stg_sysconsaif_syscfg532 (rw) register accessor: STG SYSCONSAIF SYSCFG 532\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg532::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg532::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg532`] +#[doc = "stg_sysconsaif_syscfg532 (rw) register accessor: STG SYSCONSAIF SYSCFG 532\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg532::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg532::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg532`] module"] pub type STG_SYSCONSAIF_SYSCFG532 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 532"] pub mod stg_sysconsaif_syscfg532; -#[doc = "stg_sysconsaif_syscfg536 (rw) register accessor: STG SYSCONSAIF SYSCFG 536\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg536::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg536::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg536`] +#[doc = "stg_sysconsaif_syscfg536 (rw) register accessor: STG SYSCONSAIF SYSCFG 536\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg536::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg536::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg536`] module"] pub type STG_SYSCONSAIF_SYSCFG536 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 536"] pub mod stg_sysconsaif_syscfg536; -#[doc = "stg_sysconsaif_syscfg540 (rw) register accessor: STG SYSCONSAIF SYSCFG 540\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg540::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg540::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg540`] +#[doc = "stg_sysconsaif_syscfg540 (rw) register accessor: STG SYSCONSAIF SYSCFG 540\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg540::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg540::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg540`] module"] pub type STG_SYSCONSAIF_SYSCFG540 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 540"] pub mod stg_sysconsaif_syscfg540; -#[doc = "stg_sysconsaif_syscfg544 (rw) register accessor: STG SYSCONSAIF SYSCFG 544\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg544::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg544::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg544`] +#[doc = "stg_sysconsaif_syscfg544 (rw) register accessor: STG SYSCONSAIF SYSCFG 544\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg544::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg544::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg544`] module"] pub type STG_SYSCONSAIF_SYSCFG544 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 544"] pub mod stg_sysconsaif_syscfg544; -#[doc = "stg_sysconsaif_syscfg548 (rw) register accessor: STG SYSCONSAIF SYSCFG 548\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg548::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg548::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg548`] +#[doc = "stg_sysconsaif_syscfg548 (rw) register accessor: STG SYSCONSAIF SYSCFG 548\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg548::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg548::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg548`] module"] pub type STG_SYSCONSAIF_SYSCFG548 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 548"] pub mod stg_sysconsaif_syscfg548; -#[doc = "stg_sysconsaif_syscfg552 (rw) register accessor: STG SYSCONSAIF SYSCFG 552\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg552::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg552::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg552`] +#[doc = "stg_sysconsaif_syscfg552 (rw) register accessor: STG SYSCONSAIF SYSCFG 552\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg552::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg552::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg552`] module"] pub type STG_SYSCONSAIF_SYSCFG552 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 552"] pub mod stg_sysconsaif_syscfg552; -#[doc = "stg_sysconsaif_syscfg556 (rw) register accessor: STG SYSCONSAIF SYSCFG 556\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg556::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg556::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg556`] +#[doc = "stg_sysconsaif_syscfg556 (rw) register accessor: STG SYSCONSAIF SYSCFG 556\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg556::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg556::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg556`] module"] pub type STG_SYSCONSAIF_SYSCFG556 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 556"] pub mod stg_sysconsaif_syscfg556; -#[doc = "stg_sysconsaif_syscfg560 (rw) register accessor: STG SYSCONSAIF SYSCFG 560\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg560::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg560::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg560`] +#[doc = "stg_sysconsaif_syscfg560 (rw) register accessor: STG SYSCONSAIF SYSCFG 560\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg560::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg560::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg560`] module"] pub type STG_SYSCONSAIF_SYSCFG560 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 560"] pub mod stg_sysconsaif_syscfg560; -#[doc = "stg_sysconsaif_syscfg564 (rw) register accessor: STG SYSCONSAIF SYSCFG 564\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg564::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg564::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg564`] +#[doc = "stg_sysconsaif_syscfg564 (rw) register accessor: STG SYSCONSAIF SYSCFG 564\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg564::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg564::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg564`] module"] pub type STG_SYSCONSAIF_SYSCFG564 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 564"] pub mod stg_sysconsaif_syscfg564; -#[doc = "stg_sysconsaif_syscfg568 (rw) register accessor: STG SYSCONSAIF SYSCFG 568\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg568::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg568::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg568`] +#[doc = "stg_sysconsaif_syscfg568 (rw) register accessor: STG SYSCONSAIF SYSCFG 568\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg568::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg568::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg568`] module"] pub type STG_SYSCONSAIF_SYSCFG568 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 568"] pub mod stg_sysconsaif_syscfg568; -#[doc = "stg_sysconsaif_syscfg572 (rw) register accessor: STG SYSCONSAIF SYSCFG 572\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg572::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg572::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg572`] +#[doc = "stg_sysconsaif_syscfg572 (rw) register accessor: STG SYSCONSAIF SYSCFG 572\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg572::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg572::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg572`] module"] pub type STG_SYSCONSAIF_SYSCFG572 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 572"] pub mod stg_sysconsaif_syscfg572; -#[doc = "stg_sysconsaif_syscfg576 (rw) register accessor: STG SYSCONSAIF SYSCFG 576\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg576::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg576::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg576`] +#[doc = "stg_sysconsaif_syscfg576 (rw) register accessor: STG SYSCONSAIF SYSCFG 576\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg576::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg576::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg576`] module"] pub type STG_SYSCONSAIF_SYSCFG576 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 576"] pub mod stg_sysconsaif_syscfg576; -#[doc = "stg_sysconsaif_syscfg580 (rw) register accessor: STG SYSCONSAIF SYSCFG 580\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg580::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg580::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg580`] +#[doc = "stg_sysconsaif_syscfg580 (rw) register accessor: STG SYSCONSAIF SYSCFG 580\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg580::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg580::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg580`] module"] pub type STG_SYSCONSAIF_SYSCFG580 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 580"] pub mod stg_sysconsaif_syscfg580; -#[doc = "stg_sysconsaif_syscfg584 (rw) register accessor: STG SYSCONSAIF SYSCFG 584\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg584::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg584::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg584`] +#[doc = "stg_sysconsaif_syscfg584 (rw) register accessor: STG SYSCONSAIF SYSCFG 584\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg584::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg584::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg584`] module"] pub type STG_SYSCONSAIF_SYSCFG584 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 584"] pub mod stg_sysconsaif_syscfg584; -#[doc = "stg_sysconsaif_syscfg588 (rw) register accessor: STG SYSCONSAIF SYSCFG 588\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg588::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg588::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg588`] +#[doc = "stg_sysconsaif_syscfg588 (rw) register accessor: STG SYSCONSAIF SYSCFG 588\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg588::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg588::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg588`] module"] pub type STG_SYSCONSAIF_SYSCFG588 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 588"] pub mod stg_sysconsaif_syscfg588; -#[doc = "stg_sysconsaif_syscfg592 (rw) register accessor: STG SYSCONSAIF SYSCFG 592\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg592::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg592::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg592`] +#[doc = "stg_sysconsaif_syscfg592 (rw) register accessor: STG SYSCONSAIF SYSCFG 592\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg592::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg592::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg592`] module"] pub type STG_SYSCONSAIF_SYSCFG592 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 592"] pub mod stg_sysconsaif_syscfg592; -#[doc = "stg_sysconsaif_syscfg596 (rw) register accessor: STG SYSCONSAIF SYSCFG 596\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg596::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg596::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg596`] +#[doc = "stg_sysconsaif_syscfg596 (rw) register accessor: STG SYSCONSAIF SYSCFG 596\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg596::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg596::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg596`] module"] pub type STG_SYSCONSAIF_SYSCFG596 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 596"] pub mod stg_sysconsaif_syscfg596; -#[doc = "stg_sysconsaif_syscfg600 (rw) register accessor: STG SYSCONSAIF SYSCFG 600\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg600::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg600::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg600`] +#[doc = "stg_sysconsaif_syscfg600 (rw) register accessor: STG SYSCONSAIF SYSCFG 600\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg600::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg600::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg600`] module"] pub type STG_SYSCONSAIF_SYSCFG600 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 600"] pub mod stg_sysconsaif_syscfg600; -#[doc = "stg_sysconsaif_syscfg604 (rw) register accessor: STG SYSCONSAIF SYSCFG 604\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg604::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg604::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg604`] +#[doc = "stg_sysconsaif_syscfg604 (rw) register accessor: STG SYSCONSAIF SYSCFG 604\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg604::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg604::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg604`] module"] pub type STG_SYSCONSAIF_SYSCFG604 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 604"] pub mod stg_sysconsaif_syscfg604; -#[doc = "stg_sysconsaif_syscfg608 (rw) register accessor: STG SYSCONSAIF SYSCFG 608\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg608::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg608::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg608`] +#[doc = "stg_sysconsaif_syscfg608 (rw) register accessor: STG SYSCONSAIF SYSCFG 608\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg608::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg608::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg608`] module"] pub type STG_SYSCONSAIF_SYSCFG608 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 608"] pub mod stg_sysconsaif_syscfg608; -#[doc = "stg_sysconsaif_syscfg612 (rw) register accessor: STG SYSCONSAIF SYSCFG 612\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg612::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg612::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg612`] +#[doc = "stg_sysconsaif_syscfg612 (rw) register accessor: STG SYSCONSAIF SYSCFG 612\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg612::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg612::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg612`] module"] pub type STG_SYSCONSAIF_SYSCFG612 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 612"] pub mod stg_sysconsaif_syscfg612; -#[doc = "stg_sysconsaif_syscfg616 (rw) register accessor: STG SYSCONSAIF SYSCFG 616\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg616::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg616::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg616`] +#[doc = "stg_sysconsaif_syscfg616 (rw) register accessor: STG SYSCONSAIF SYSCFG 616\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg616::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg616::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg616`] module"] pub type STG_SYSCONSAIF_SYSCFG616 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 616"] pub mod stg_sysconsaif_syscfg616; -#[doc = "stg_sysconsaif_syscfg620 (rw) register accessor: STG SYSCONSAIF SYSCFG 620\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg620::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg620::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg620`] +#[doc = "stg_sysconsaif_syscfg620 (rw) register accessor: STG SYSCONSAIF SYSCFG 620\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg620::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg620::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg620`] module"] pub type STG_SYSCONSAIF_SYSCFG620 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 620"] pub mod stg_sysconsaif_syscfg620; -#[doc = "stg_sysconsaif_syscfg624 (rw) register accessor: STG SYSCONSAIF SYSCFG 624\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg624::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg624::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg624`] +#[doc = "stg_sysconsaif_syscfg624 (rw) register accessor: STG SYSCONSAIF SYSCFG 624\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg624::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg624::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg624`] module"] pub type STG_SYSCONSAIF_SYSCFG624 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 624"] pub mod stg_sysconsaif_syscfg624; -#[doc = "stg_sysconsaif_syscfg628 (rw) register accessor: STG SYSCONSAIF SYSCFG 628\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg628::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg628::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg628`] +#[doc = "stg_sysconsaif_syscfg628 (rw) register accessor: STG SYSCONSAIF SYSCFG 628\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg628::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg628::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg628`] module"] pub type STG_SYSCONSAIF_SYSCFG628 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 628"] pub mod stg_sysconsaif_syscfg628; -#[doc = "stg_sysconsaif_syscfg632 (rw) register accessor: STG SYSCONSAIF SYSCFG 632\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg632::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg632::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg632`] +#[doc = "stg_sysconsaif_syscfg632 (rw) register accessor: STG SYSCONSAIF SYSCFG 632\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg632::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg632::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg632`] module"] pub type STG_SYSCONSAIF_SYSCFG632 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 632"] pub mod stg_sysconsaif_syscfg632; -#[doc = "stg_sysconsaif_syscfg636 (rw) register accessor: STG SYSCONSAIF SYSCFG 636\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg636::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg636::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg636`] +#[doc = "stg_sysconsaif_syscfg636 (rw) register accessor: STG SYSCONSAIF SYSCFG 636\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg636::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg636::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg636`] module"] pub type STG_SYSCONSAIF_SYSCFG636 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 636"] pub mod stg_sysconsaif_syscfg636; -#[doc = "stg_sysconsaif_syscfg640 (rw) register accessor: STG SYSCONSAIF SYSCFG 640\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg640::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg640::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg640`] +#[doc = "stg_sysconsaif_syscfg640 (rw) register accessor: STG SYSCONSAIF SYSCFG 640\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg640::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg640::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg640`] module"] pub type STG_SYSCONSAIF_SYSCFG640 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 640"] pub mod stg_sysconsaif_syscfg640; -#[doc = "stg_sysconsaif_syscfg644 (rw) register accessor: STG SYSCONSAIF SYSCFG 644\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg644::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg644::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg644`] +#[doc = "stg_sysconsaif_syscfg644 (rw) register accessor: STG SYSCONSAIF SYSCFG 644\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg644::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg644::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg644`] module"] pub type STG_SYSCONSAIF_SYSCFG644 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 644"] pub mod stg_sysconsaif_syscfg644; -#[doc = "stg_sysconsaif_syscfg648 (rw) register accessor: STG SYSCONSAIF SYSCFG 648\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg648::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg648::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg648`] +#[doc = "stg_sysconsaif_syscfg648 (rw) register accessor: STG SYSCONSAIF SYSCFG 648\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg648::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg648::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg648`] module"] pub type STG_SYSCONSAIF_SYSCFG648 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 648"] pub mod stg_sysconsaif_syscfg648; -#[doc = "stg_sysconsaif_syscfg652 (rw) register accessor: STG SYSCONSAIF SYSCFG 652\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg652::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg652::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg652`] +#[doc = "stg_sysconsaif_syscfg652 (rw) register accessor: STG SYSCONSAIF SYSCFG 652\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg652::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg652::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg652`] module"] pub type STG_SYSCONSAIF_SYSCFG652 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 652"] pub mod stg_sysconsaif_syscfg652; -#[doc = "stg_sysconsaif_syscfg656 (rw) register accessor: STG SYSCONSAIF SYSCFG 656\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg656::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg656::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg656`] +#[doc = "stg_sysconsaif_syscfg656 (rw) register accessor: STG SYSCONSAIF SYSCFG 656\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg656::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg656::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg656`] module"] pub type STG_SYSCONSAIF_SYSCFG656 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 656"] pub mod stg_sysconsaif_syscfg656; -#[doc = "stg_sysconsaif_syscfg660 (rw) register accessor: STG SYSCONSAIF SYSCFG 660\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg660::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg660::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg660`] +#[doc = "stg_sysconsaif_syscfg660 (rw) register accessor: STG SYSCONSAIF SYSCFG 660\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg660::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg660::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg660`] module"] pub type STG_SYSCONSAIF_SYSCFG660 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 660"] pub mod stg_sysconsaif_syscfg660; -#[doc = "stg_sysconsaif_syscfg664 (rw) register accessor: STG SYSCONSAIF SYSCFG 664\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg664::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg664::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg664`] +#[doc = "stg_sysconsaif_syscfg664 (rw) register accessor: STG SYSCONSAIF SYSCFG 664\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg664::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg664::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg664`] module"] pub type STG_SYSCONSAIF_SYSCFG664 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 664"] pub mod stg_sysconsaif_syscfg664; -#[doc = "stg_sysconsaif_syscfg668 (rw) register accessor: STG SYSCONSAIF SYSCFG 668\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg668::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg668::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg668`] +#[doc = "stg_sysconsaif_syscfg668 (rw) register accessor: STG SYSCONSAIF SYSCFG 668\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg668::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg668::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg668`] module"] pub type STG_SYSCONSAIF_SYSCFG668 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 668"] pub mod stg_sysconsaif_syscfg668; -#[doc = "stg_sysconsaif_syscfg672 (rw) register accessor: STG SYSCONSAIF SYSCFG 672\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg672::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg672::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg672`] +#[doc = "stg_sysconsaif_syscfg672 (rw) register accessor: STG SYSCONSAIF SYSCFG 672\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg672::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg672::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg672`] module"] pub type STG_SYSCONSAIF_SYSCFG672 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 672"] pub mod stg_sysconsaif_syscfg672; -#[doc = "stg_sysconsaif_syscfg676 (rw) register accessor: STG SYSCONSAIF SYSCFG 676\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg676::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg676::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg676`] +#[doc = "stg_sysconsaif_syscfg676 (rw) register accessor: STG SYSCONSAIF SYSCFG 676\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg676::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg676::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg676`] module"] pub type STG_SYSCONSAIF_SYSCFG676 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 676"] pub mod stg_sysconsaif_syscfg676; -#[doc = "stg_sysconsaif_syscfg680 (rw) register accessor: STG SYSCONSAIF SYSCFG 680\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg680::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg680::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg680`] +#[doc = "stg_sysconsaif_syscfg680 (rw) register accessor: STG SYSCONSAIF SYSCFG 680\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg680::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg680::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg680`] module"] pub type STG_SYSCONSAIF_SYSCFG680 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 680"] pub mod stg_sysconsaif_syscfg680; -#[doc = "stg_sysconsaif_syscfg684 (rw) register accessor: STG SYSCONSAIF SYSCFG 684\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg684::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg684::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg684`] +#[doc = "stg_sysconsaif_syscfg684 (rw) register accessor: STG SYSCONSAIF SYSCFG 684\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg684::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg684::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg684`] module"] pub type STG_SYSCONSAIF_SYSCFG684 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 684"] pub mod stg_sysconsaif_syscfg684; -#[doc = "stg_sysconsaif_syscfg688 (rw) register accessor: STG SYSCONSAIF SYSCFG 688\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg688::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg688::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg688`] +#[doc = "stg_sysconsaif_syscfg688 (rw) register accessor: STG SYSCONSAIF SYSCFG 688\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg688::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg688::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg688`] module"] pub type STG_SYSCONSAIF_SYSCFG688 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 688"] pub mod stg_sysconsaif_syscfg688; -#[doc = "stg_sysconsaif_syscfg692 (rw) register accessor: STG SYSCONSAIF SYSCFG 692\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg692::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg692::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg692`] +#[doc = "stg_sysconsaif_syscfg692 (rw) register accessor: STG SYSCONSAIF SYSCFG 692\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg692::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg692::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg692`] module"] pub type STG_SYSCONSAIF_SYSCFG692 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 692"] pub mod stg_sysconsaif_syscfg692; -#[doc = "stg_sysconsaif_syscfg696 (rw) register accessor: STG SYSCONSAIF SYSCFG 696\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg696::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg696::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg696`] +#[doc = "stg_sysconsaif_syscfg696 (rw) register accessor: STG SYSCONSAIF SYSCFG 696\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg696::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg696::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg696`] module"] pub type STG_SYSCONSAIF_SYSCFG696 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 696"] pub mod stg_sysconsaif_syscfg696; -#[doc = "stg_sysconsaif_syscfg700 (rw) register accessor: STG SYSCONSAIF SYSCFG 700\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg700::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg700::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg700`] +#[doc = "stg_sysconsaif_syscfg700 (rw) register accessor: STG SYSCONSAIF SYSCFG 700\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg700::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg700::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg700`] module"] pub type STG_SYSCONSAIF_SYSCFG700 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 700"] pub mod stg_sysconsaif_syscfg700; -#[doc = "stg_sysconsaif_syscfg704 (rw) register accessor: STG SYSCONSAIF SYSCFG 704\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg704::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg704::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg704`] +#[doc = "stg_sysconsaif_syscfg704 (rw) register accessor: STG SYSCONSAIF SYSCFG 704\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg704::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg704::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg704`] module"] pub type STG_SYSCONSAIF_SYSCFG704 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 704"] pub mod stg_sysconsaif_syscfg704; -#[doc = "stg_sysconsaif_syscfg708 (rw) register accessor: STG SYSCONSAIF SYSCFG 708\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg708::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg708::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg708`] +#[doc = "stg_sysconsaif_syscfg708 (rw) register accessor: STG SYSCONSAIF SYSCFG 708\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg708::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg708::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg708`] module"] pub type STG_SYSCONSAIF_SYSCFG708 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 708"] pub mod stg_sysconsaif_syscfg708; -#[doc = "stg_sysconsaif_syscfg712 (rw) register accessor: STG SYSCONSAIF SYSCFG 712\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg712::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg712::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg712`] +#[doc = "stg_sysconsaif_syscfg712 (rw) register accessor: STG SYSCONSAIF SYSCFG 712\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg712::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg712::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg712`] module"] pub type STG_SYSCONSAIF_SYSCFG712 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 712"] pub mod stg_sysconsaif_syscfg712; -#[doc = "stg_sysconsaif_syscfg716 (rw) register accessor: STG SYSCONSAIF SYSCFG 716\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg716::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg716::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg716`] +#[doc = "stg_sysconsaif_syscfg716 (rw) register accessor: STG SYSCONSAIF SYSCFG 716\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg716::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg716::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg716`] module"] pub type STG_SYSCONSAIF_SYSCFG716 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 716"] pub mod stg_sysconsaif_syscfg716; -#[doc = "stg_sysconsaif_syscfg720 (rw) register accessor: STG SYSCONSAIF SYSCFG 720\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg720::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg720::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg720`] +#[doc = "stg_sysconsaif_syscfg720 (rw) register accessor: STG SYSCONSAIF SYSCFG 720\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg720::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg720::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg720`] module"] pub type STG_SYSCONSAIF_SYSCFG720 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 720"] pub mod stg_sysconsaif_syscfg720; -#[doc = "stg_sysconsaif_syscfg724 (rw) register accessor: STG SYSCONSAIF SYSCFG 724\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg724::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg724::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg724`] +#[doc = "stg_sysconsaif_syscfg724 (rw) register accessor: STG SYSCONSAIF SYSCFG 724\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg724::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg724::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg724`] module"] pub type STG_SYSCONSAIF_SYSCFG724 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 724"] pub mod stg_sysconsaif_syscfg724; -#[doc = "stg_sysconsaif_syscfg728 (rw) register accessor: STG SYSCONSAIF SYSCFG 728\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg728::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg728::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg728`] +#[doc = "stg_sysconsaif_syscfg728 (rw) register accessor: STG SYSCONSAIF SYSCFG 728\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg728::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg728::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg728`] module"] pub type STG_SYSCONSAIF_SYSCFG728 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 728"] pub mod stg_sysconsaif_syscfg728; -#[doc = "stg_sysconsaif_syscfg732 (rw) register accessor: STG SYSCONSAIF SYSCFG 732\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg732::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg732::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg732`] +#[doc = "stg_sysconsaif_syscfg732 (rw) register accessor: STG SYSCONSAIF SYSCFG 732\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg732::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg732::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg732`] module"] pub type STG_SYSCONSAIF_SYSCFG732 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 732"] pub mod stg_sysconsaif_syscfg732; -#[doc = "stg_sysconsaif_syscfg736 (rw) register accessor: STG SYSCONSAIF SYSCFG 736\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg736::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg736::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg736`] +#[doc = "stg_sysconsaif_syscfg736 (rw) register accessor: STG SYSCONSAIF SYSCFG 736\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg736::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg736::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg736`] module"] pub type STG_SYSCONSAIF_SYSCFG736 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 736"] pub mod stg_sysconsaif_syscfg736; -#[doc = "stg_sysconsaif_syscfg740 (rw) register accessor: STG SYSCONSAIF SYSCFG 740\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg740::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg740::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg740`] +#[doc = "stg_sysconsaif_syscfg740 (rw) register accessor: STG SYSCONSAIF SYSCFG 740\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg740::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg740::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg740`] module"] pub type STG_SYSCONSAIF_SYSCFG740 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 740"] pub mod stg_sysconsaif_syscfg740; -#[doc = "stg_sysconsaif_syscfg744 (rw) register accessor: STG SYSCONSAIF SYSCFG 744\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg744::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg744::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg744`] +#[doc = "stg_sysconsaif_syscfg744 (rw) register accessor: STG SYSCONSAIF SYSCFG 744\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg744::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg744::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg744`] module"] pub type STG_SYSCONSAIF_SYSCFG744 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 744"] pub mod stg_sysconsaif_syscfg744; -#[doc = "stg_sysconsaif_syscfg748 (rw) register accessor: STG SYSCONSAIF SYSCFG 748\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg748::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg748::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg748`] +#[doc = "stg_sysconsaif_syscfg748 (rw) register accessor: STG SYSCONSAIF SYSCFG 748\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg748::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg748::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg748`] module"] pub type STG_SYSCONSAIF_SYSCFG748 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 748"] pub mod stg_sysconsaif_syscfg748; -#[doc = "stg_sysconsaif_syscfg752 (rw) register accessor: STG SYSCONSAIF SYSCFG 752\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg752::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg752::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg752`] +#[doc = "stg_sysconsaif_syscfg752 (rw) register accessor: STG SYSCONSAIF SYSCFG 752\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg752::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg752::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg752`] module"] pub type STG_SYSCONSAIF_SYSCFG752 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 752"] pub mod stg_sysconsaif_syscfg752; -#[doc = "stg_sysconsaif_syscfg756 (rw) register accessor: STG SYSCONSAIF SYSCFG 756\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg756::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg756::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg756`] +#[doc = "stg_sysconsaif_syscfg756 (rw) register accessor: STG SYSCONSAIF SYSCFG 756\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg756::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg756::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg756`] module"] pub type STG_SYSCONSAIF_SYSCFG756 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 756"] pub mod stg_sysconsaif_syscfg756; -#[doc = "stg_sysconsaif_syscfg760 (rw) register accessor: STG SYSCONSAIF SYSCFG 760\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg760::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg760::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg760`] +#[doc = "stg_sysconsaif_syscfg760 (rw) register accessor: STG SYSCONSAIF SYSCFG 760\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg760::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg760::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg760`] module"] pub type STG_SYSCONSAIF_SYSCFG760 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 760"] pub mod stg_sysconsaif_syscfg760; -#[doc = "stg_sysconsaif_syscfg764 (rw) register accessor: STG SYSCONSAIF SYSCFG 764\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg764::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg764::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg764`] +#[doc = "stg_sysconsaif_syscfg764 (rw) register accessor: STG SYSCONSAIF SYSCFG 764\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg764::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg764::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg764`] module"] pub type STG_SYSCONSAIF_SYSCFG764 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 764"] pub mod stg_sysconsaif_syscfg764; -#[doc = "stg_sysconsaif_syscfg768 (rw) register accessor: STG SYSCONSAIF SYSCFG 768\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg768::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg768::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg768`] +#[doc = "stg_sysconsaif_syscfg768 (rw) register accessor: STG SYSCONSAIF SYSCFG 768\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg768::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg768::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg768`] module"] pub type STG_SYSCONSAIF_SYSCFG768 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 768"] pub mod stg_sysconsaif_syscfg768; -#[doc = "stg_sysconsaif_syscfg772 (rw) register accessor: STG SYSCONSAIF SYSCFG 772\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg772::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg772::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg772`] +#[doc = "stg_sysconsaif_syscfg772 (rw) register accessor: STG SYSCONSAIF SYSCFG 772\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg772::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg772::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg772`] module"] pub type STG_SYSCONSAIF_SYSCFG772 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 772"] pub mod stg_sysconsaif_syscfg772; -#[doc = "stg_sysconsaif_syscfg776 (rw) register accessor: STG SYSCONSAIF SYSCFG 776\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg776::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg776::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg776`] +#[doc = "stg_sysconsaif_syscfg776 (rw) register accessor: STG SYSCONSAIF SYSCFG 776\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg776::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg776::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg776`] module"] pub type STG_SYSCONSAIF_SYSCFG776 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 776"] pub mod stg_sysconsaif_syscfg776; -#[doc = "stg_sysconsaif_syscfg780 (rw) register accessor: STG SYSCONSAIF SYSCFG 780\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg780::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg780::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg780`] +#[doc = "stg_sysconsaif_syscfg780 (rw) register accessor: STG SYSCONSAIF SYSCFG 780\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg780::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg780::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg780`] module"] pub type STG_SYSCONSAIF_SYSCFG780 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 780"] pub mod stg_sysconsaif_syscfg780; -#[doc = "stg_sysconsaif_syscfg784 (rw) register accessor: STG SYSCONSAIF SYSCFG 784\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg784::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg784::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg784`] +#[doc = "stg_sysconsaif_syscfg784 (rw) register accessor: STG SYSCONSAIF SYSCFG 784\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg784::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg784::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg784`] module"] pub type STG_SYSCONSAIF_SYSCFG784 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 784"] pub mod stg_sysconsaif_syscfg784; -#[doc = "stg_sysconsaif_syscfg788 (rw) register accessor: STG SYSCONSAIF SYSCFG 788\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg788::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg788::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg788`] +#[doc = "stg_sysconsaif_syscfg788 (rw) register accessor: STG SYSCONSAIF SYSCFG 788\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg788::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg788::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg788`] module"] pub type STG_SYSCONSAIF_SYSCFG788 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 788"] pub mod stg_sysconsaif_syscfg788; -#[doc = "stg_sysconsaif_syscfg792 (rw) register accessor: STG SYSCONSAIF SYSCFG 792\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg792::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg792::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg792`] +#[doc = "stg_sysconsaif_syscfg792 (rw) register accessor: STG SYSCONSAIF SYSCFG 792\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg792::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg792::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg792`] module"] pub type STG_SYSCONSAIF_SYSCFG792 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 792"] pub mod stg_sysconsaif_syscfg792; -#[doc = "stg_sysconsaif_syscfg796 (rw) register accessor: STG SYSCONSAIF SYSCFG 796\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg796::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg796::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg796`] +#[doc = "stg_sysconsaif_syscfg796 (rw) register accessor: STG SYSCONSAIF SYSCFG 796\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg796::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg796::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg796`] module"] pub type STG_SYSCONSAIF_SYSCFG796 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 796"] pub mod stg_sysconsaif_syscfg796; -#[doc = "stg_sysconsaif_syscfg800 (rw) register accessor: STG SYSCONSAIF SYSCFG 800\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg800::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg800::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg800`] +#[doc = "stg_sysconsaif_syscfg800 (rw) register accessor: STG SYSCONSAIF SYSCFG 800\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg800::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg800::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg800`] module"] pub type STG_SYSCONSAIF_SYSCFG800 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 800"] pub mod stg_sysconsaif_syscfg800; -#[doc = "stg_sysconsaif_syscfg804 (rw) register accessor: STG SYSCONSAIF SYSCFG 804\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg804::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg804::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg804`] +#[doc = "stg_sysconsaif_syscfg804 (rw) register accessor: STG SYSCONSAIF SYSCFG 804\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg804::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg804::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg804`] module"] pub type STG_SYSCONSAIF_SYSCFG804 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 804"] pub mod stg_sysconsaif_syscfg804; -#[doc = "stg_sysconsaif_syscfg808 (rw) register accessor: STG SYSCONSAIF SYSCFG 808\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg808::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg808::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg808`] +#[doc = "stg_sysconsaif_syscfg808 (rw) register accessor: STG SYSCONSAIF SYSCFG 808\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg808::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg808::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg808`] module"] pub type STG_SYSCONSAIF_SYSCFG808 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 808"] pub mod stg_sysconsaif_syscfg808; -#[doc = "stg_sysconsaif_syscfg812 (rw) register accessor: STG SYSCONSAIF SYSCFG 812\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg812::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg812::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg812`] +#[doc = "stg_sysconsaif_syscfg812 (rw) register accessor: STG SYSCONSAIF SYSCFG 812\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg812::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg812::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg812`] module"] pub type STG_SYSCONSAIF_SYSCFG812 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 812"] pub mod stg_sysconsaif_syscfg812; -#[doc = "stg_sysconsaif_syscfg816 (rw) register accessor: STG SYSCONSAIF SYSCFG 816\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg816::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg816::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg816`] +#[doc = "stg_sysconsaif_syscfg816 (rw) register accessor: STG SYSCONSAIF SYSCFG 816\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg816::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg816::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg816`] module"] pub type STG_SYSCONSAIF_SYSCFG816 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 816"] pub mod stg_sysconsaif_syscfg816; -#[doc = "stg_sysconsaif_syscfg820 (rw) register accessor: STG SYSCONSAIF SYSCFG 820\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg820::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg820::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg820`] +#[doc = "stg_sysconsaif_syscfg820 (rw) register accessor: STG SYSCONSAIF SYSCFG 820\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg820::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg820::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg820`] module"] pub type STG_SYSCONSAIF_SYSCFG820 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 820"] pub mod stg_sysconsaif_syscfg820; -#[doc = "stg_sysconsaif_syscfg824 (rw) register accessor: STG SYSCONSAIF SYSCFG 824\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg824::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg824::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg824`] +#[doc = "stg_sysconsaif_syscfg824 (rw) register accessor: STG SYSCONSAIF SYSCFG 824\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg824::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg824::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg824`] module"] pub type STG_SYSCONSAIF_SYSCFG824 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 824"] pub mod stg_sysconsaif_syscfg824; -#[doc = "stg_sysconsaif_syscfg828 (rw) register accessor: STG SYSCONSAIF SYSCFG 828\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg828::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg828::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg828`] +#[doc = "stg_sysconsaif_syscfg828 (rw) register accessor: STG SYSCONSAIF SYSCFG 828\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg828::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg828::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg828`] module"] pub type STG_SYSCONSAIF_SYSCFG828 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 828"] pub mod stg_sysconsaif_syscfg828; -#[doc = "stg_sysconsaif_syscfg832 (rw) register accessor: STG SYSCONSAIF SYSCFG 832\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg832::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg832::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg832`] +#[doc = "stg_sysconsaif_syscfg832 (rw) register accessor: STG SYSCONSAIF SYSCFG 832\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg832::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg832::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg832`] module"] pub type STG_SYSCONSAIF_SYSCFG832 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 832"] pub mod stg_sysconsaif_syscfg832; -#[doc = "stg_sysconsaif_syscfg836 (rw) register accessor: STG SYSCONSAIF SYSCFG 836\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg836::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg836::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg836`] +#[doc = "stg_sysconsaif_syscfg836 (rw) register accessor: STG SYSCONSAIF SYSCFG 836\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg836::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg836::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg836`] module"] pub type STG_SYSCONSAIF_SYSCFG836 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 836"] pub mod stg_sysconsaif_syscfg836; -#[doc = "stg_sysconsaif_syscfg840 (rw) register accessor: STG SYSCONSAIF SYSCFG 840\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg840::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg840::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg840`] +#[doc = "stg_sysconsaif_syscfg840 (rw) register accessor: STG SYSCONSAIF SYSCFG 840\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg840::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg840::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg840`] module"] pub type STG_SYSCONSAIF_SYSCFG840 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 840"] pub mod stg_sysconsaif_syscfg840; -#[doc = "stg_sysconsaif_syscfg844 (rw) register accessor: STG SYSCONSAIF SYSCFG 844\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg844::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg844::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg844`] +#[doc = "stg_sysconsaif_syscfg844 (rw) register accessor: STG SYSCONSAIF SYSCFG 844\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg844::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg844::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg844`] module"] pub type STG_SYSCONSAIF_SYSCFG844 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 844"] pub mod stg_sysconsaif_syscfg844; -#[doc = "stg_sysconsaif_syscfg848 (rw) register accessor: STG SYSCONSAIF SYSCFG 848\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg848::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg848::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg848`] +#[doc = "stg_sysconsaif_syscfg848 (rw) register accessor: STG SYSCONSAIF SYSCFG 848\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg848::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg848::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg848`] module"] pub type STG_SYSCONSAIF_SYSCFG848 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 848"] pub mod stg_sysconsaif_syscfg848; -#[doc = "stg_sysconsaif_syscfg852 (rw) register accessor: STG SYSCONSAIF SYSCFG 852\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg852::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg852::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg852`] +#[doc = "stg_sysconsaif_syscfg852 (rw) register accessor: STG SYSCONSAIF SYSCFG 852\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg852::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg852::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg852`] module"] pub type STG_SYSCONSAIF_SYSCFG852 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 852"] pub mod stg_sysconsaif_syscfg852; -#[doc = "stg_sysconsaif_syscfg856 (rw) register accessor: STG SYSCONSAIF SYSCFG 856\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg856::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg856::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg856`] +#[doc = "stg_sysconsaif_syscfg856 (rw) register accessor: STG SYSCONSAIF SYSCFG 856\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg856::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg856::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg856`] module"] pub type STG_SYSCONSAIF_SYSCFG856 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 856"] pub mod stg_sysconsaif_syscfg856; -#[doc = "stg_sysconsaif_syscfg860 (rw) register accessor: STG SYSCONSAIF SYSCFG 860\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg860::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg860::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg860`] +#[doc = "stg_sysconsaif_syscfg860 (rw) register accessor: STG SYSCONSAIF SYSCFG 860\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg860::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg860::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg860`] module"] pub type STG_SYSCONSAIF_SYSCFG860 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 860"] pub mod stg_sysconsaif_syscfg860; -#[doc = "stg_sysconsaif_syscfg864 (rw) register accessor: STG SYSCONSAIF SYSCFG 864\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg864::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg864::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg864`] +#[doc = "stg_sysconsaif_syscfg864 (rw) register accessor: STG SYSCONSAIF SYSCFG 864\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg864::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg864::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg864`] module"] pub type STG_SYSCONSAIF_SYSCFG864 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 864"] pub mod stg_sysconsaif_syscfg864; -#[doc = "stg_sysconsaif_syscfg868 (rw) register accessor: STG SYSCONSAIF SYSCFG 868\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg868::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg868::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg868`] +#[doc = "stg_sysconsaif_syscfg868 (rw) register accessor: STG SYSCONSAIF SYSCFG 868\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg868::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg868::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg868`] module"] pub type STG_SYSCONSAIF_SYSCFG868 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 868"] pub mod stg_sysconsaif_syscfg868; -#[doc = "stg_sysconsaif_syscfg872 (rw) register accessor: STG SYSCONSAIF SYSCFG 872\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg872::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg872::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg872`] +#[doc = "stg_sysconsaif_syscfg872 (rw) register accessor: STG SYSCONSAIF SYSCFG 872\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg872::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg872::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg872`] module"] pub type STG_SYSCONSAIF_SYSCFG872 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 872"] pub mod stg_sysconsaif_syscfg872; -#[doc = "stg_sysconsaif_syscfg876 (rw) register accessor: STG SYSCONSAIF SYSCFG 876\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg876::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg876::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg876`] +#[doc = "stg_sysconsaif_syscfg876 (rw) register accessor: STG SYSCONSAIF SYSCFG 876\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg876::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg876::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg876`] module"] pub type STG_SYSCONSAIF_SYSCFG876 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 876"] pub mod stg_sysconsaif_syscfg876; -#[doc = "stg_sysconsaif_syscfg880 (rw) register accessor: STG SYSCONSAIF SYSCFG 880\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg880::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg880::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg880`] +#[doc = "stg_sysconsaif_syscfg880 (rw) register accessor: STG SYSCONSAIF SYSCFG 880\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg880::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg880::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg880`] module"] pub type STG_SYSCONSAIF_SYSCFG880 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 880"] pub mod stg_sysconsaif_syscfg880; -#[doc = "stg_sysconsaif_syscfg884 (rw) register accessor: STG SYSCONSAIF SYSCFG 884\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg884::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg884::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg884`] +#[doc = "stg_sysconsaif_syscfg884 (rw) register accessor: STG SYSCONSAIF SYSCFG 884\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg884::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg884::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg884`] module"] pub type STG_SYSCONSAIF_SYSCFG884 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 884"] pub mod stg_sysconsaif_syscfg884; -#[doc = "stg_sysconsaif_syscfg888 (rw) register accessor: STG SYSCONSAIF SYSCFG 888\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg888::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg888::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg888`] +#[doc = "stg_sysconsaif_syscfg888 (rw) register accessor: STG SYSCONSAIF SYSCFG 888\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg888::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg888::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg888`] module"] pub type STG_SYSCONSAIF_SYSCFG888 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 888"] pub mod stg_sysconsaif_syscfg888; -#[doc = "stg_sysconsaif_syscfg892 (rw) register accessor: STG SYSCONSAIF SYSCFG 892\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg892::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg892::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg892`] +#[doc = "stg_sysconsaif_syscfg892 (rw) register accessor: STG SYSCONSAIF SYSCFG 892\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg892::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg892::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg892`] module"] pub type STG_SYSCONSAIF_SYSCFG892 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 892"] pub mod stg_sysconsaif_syscfg892; -#[doc = "stg_sysconsaif_syscfg896 (rw) register accessor: STG SYSCONSAIF SYSCFG 896\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg896::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg896::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg896`] +#[doc = "stg_sysconsaif_syscfg896 (rw) register accessor: STG SYSCONSAIF SYSCFG 896\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg896::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg896::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg896`] module"] pub type STG_SYSCONSAIF_SYSCFG896 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 896"] pub mod stg_sysconsaif_syscfg896; -#[doc = "stg_sysconsaif_syscfg900 (rw) register accessor: STG SYSCONSAIF SYSCFG 900\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg900::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg900::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg900`] +#[doc = "stg_sysconsaif_syscfg900 (rw) register accessor: STG SYSCONSAIF SYSCFG 900\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg900::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg900::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg900`] module"] pub type STG_SYSCONSAIF_SYSCFG900 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 900"] pub mod stg_sysconsaif_syscfg900; -#[doc = "stg_sysconsaif_syscfg904 (rw) register accessor: STG SYSCONSAIF SYSCFG 904\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg904::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg904::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg904`] +#[doc = "stg_sysconsaif_syscfg904 (rw) register accessor: STG SYSCONSAIF SYSCFG 904\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg904::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg904::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg904`] module"] pub type STG_SYSCONSAIF_SYSCFG904 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 904"] pub mod stg_sysconsaif_syscfg904; -#[doc = "stg_sysconsaif_syscfg908 (rw) register accessor: STG SYSCONSAIF SYSCFG 908\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg908::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg908::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg908`] +#[doc = "stg_sysconsaif_syscfg908 (rw) register accessor: STG SYSCONSAIF SYSCFG 908\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg908::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg908::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg908`] module"] pub type STG_SYSCONSAIF_SYSCFG908 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 908"] pub mod stg_sysconsaif_syscfg908; -#[doc = "stg_sysconsaif_syscfg912 (rw) register accessor: STG SYSCONSAIF SYSCFG 912\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg912::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg912::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg912`] +#[doc = "stg_sysconsaif_syscfg912 (rw) register accessor: STG SYSCONSAIF SYSCFG 912\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg912::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg912::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg912`] module"] pub type STG_SYSCONSAIF_SYSCFG912 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 912"] pub mod stg_sysconsaif_syscfg912; -#[doc = "stg_sysconsaif_syscfg916 (rw) register accessor: STG SYSCONSAIF SYSCFG 916\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg916::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg916::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg916`] +#[doc = "stg_sysconsaif_syscfg916 (rw) register accessor: STG SYSCONSAIF SYSCFG 916\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg916::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg916::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg916`] module"] pub type STG_SYSCONSAIF_SYSCFG916 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 916"] pub mod stg_sysconsaif_syscfg916; -#[doc = "stg_sysconsaif_syscfg920 (rw) register accessor: STG SYSCONSAIF SYSCFG 920\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg920::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg920::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg920`] +#[doc = "stg_sysconsaif_syscfg920 (rw) register accessor: STG SYSCONSAIF SYSCFG 920\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg920::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg920::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg920`] module"] pub type STG_SYSCONSAIF_SYSCFG920 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 920"] pub mod stg_sysconsaif_syscfg920; -#[doc = "stg_sysconsaif_syscfg924 (rw) register accessor: STG SYSCONSAIF SYSCFG 924\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg924::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg924::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg924`] +#[doc = "stg_sysconsaif_syscfg924 (rw) register accessor: STG SYSCONSAIF SYSCFG 924\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg924::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg924::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg924`] module"] pub type STG_SYSCONSAIF_SYSCFG924 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 924"] pub mod stg_sysconsaif_syscfg924; -#[doc = "stg_sysconsaif_syscfg928 (rw) register accessor: STG SYSCONSAIF SYSCFG 928\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg928::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg928::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg928`] +#[doc = "stg_sysconsaif_syscfg928 (rw) register accessor: STG SYSCONSAIF SYSCFG 928\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg928::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg928::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg928`] module"] pub type STG_SYSCONSAIF_SYSCFG928 = crate::Reg; #[doc = "STG SYSCONSAIF SYSCFG 928"] pub mod stg_sysconsaif_syscfg928; -#[doc = "stg_sysconsaif_syscfg932 (rw) register accessor: STG SYSCONSAIF SYSCFG 932\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg932::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg932::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stg_sysconsaif_syscfg932`] +#[doc = "stg_sysconsaif_syscfg932 (rw) register accessor: STG SYSCONSAIF SYSCFG 932\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stg_sysconsaif_syscfg932::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stg_sysconsaif_syscfg932::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stg_sysconsaif_syscfg932`] module"] pub type STG_SYSCONSAIF_SYSCFG932 = crate::Reg; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg0.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg0.rs index 38458b8..d85514a 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg0.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg0.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `scfg_hprot_sd0` reader - scfg_hprot_sd0"] pub type SCFG_HPROT_SD0_R = crate::FieldReader; #[doc = "Field `scfg_hprot_sd0` writer - scfg_hprot_sd0"] -pub type SCFG_HPROT_SD0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_HPROT_SD0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_hprot_sd1` reader - scfg_hprot_sd1"] pub type SCFG_HPROT_SD1_R = crate::FieldReader; #[doc = "Field `scfg_hprot_sd1` writer - scfg_hprot_sd1"] -pub type SCFG_HPROT_SD1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_HPROT_SD1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `u0_cdn_usb_adp_en` reader - u0_cdn_usb_adp_en"] pub type U0_CDN_USB_ADP_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_adp_probe_ana` reader - u0_cdn_usb_adp_probe_ana"] pub type U0_CDN_USB_ADP_PROBE_ANA_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_adp_probe_ana` writer - u0_cdn_usb_adp_probe_ana"] -pub type U0_CDN_USB_ADP_PROBE_ANA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_ADP_PROBE_ANA_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_adp_probe_en` reader - u0_cdn_usb_adp_probe_en"] pub type U0_CDN_USB_ADP_PROBE_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_adp_sense_ana` reader - u0_cdn_usb_adp_sense_ana"] pub type U0_CDN_USB_ADP_SENSE_ANA_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_adp_sense_ana` writer - u0_cdn_usb_adp_sense_ana"] -pub type U0_CDN_USB_ADP_SENSE_ANA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_ADP_SENSE_ANA_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_adp_sense_en` reader - u0_cdn_usb_adp_sense_en"] pub type U0_CDN_USB_ADP_SENSE_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_adp_sink_current_en` reader - u0_cdn_usb_adp_sink_current_en"] @@ -33,37 +33,37 @@ pub type U0_CDN_USB_BC_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_chrg_vbus` reader - u0_cdn_usb_chrg_vbus"] pub type U0_CDN_USB_CHRG_VBUS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_chrg_vbus` writer - u0_cdn_usb_chrg_vbus"] -pub type U0_CDN_USB_CHRG_VBUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_CHRG_VBUS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_dcd_comp_sts` reader - u0_cdn_usb_dcd_comp_sts"] pub type U0_CDN_USB_DCD_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_dcd_comp_sts` writer - u0_cdn_usb_dcd_comp_sts"] -pub type U0_CDN_USB_DCD_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_DCD_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_dischrg_vbus` reader - u0_cdn_usb_dischrg_vbus"] pub type U0_CDN_USB_DISCHRG_VBUS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_dischrg_vbus` writer - u0_cdn_usb_dischrg_vbus"] -pub type U0_CDN_USB_DISCHRG_VBUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_DISCHRG_VBUS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_dm_vdat_ref_comp_en` reader - u0_cdn_usb_dm_vdat_ref_comp_en"] pub type U0_CDN_USB_DM_VDAT_REF_COMP_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_dm_vdat_ref_comp_sts` reader - u0_cdn_usb_dm_vdat_ref_comp_sts"] pub type U0_CDN_USB_DM_VDAT_REF_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_dm_vdat_ref_comp_sts` writer - u0_cdn_usb_dm_vdat_ref_comp_sts"] -pub type U0_CDN_USB_DM_VDAT_REF_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_DM_VDAT_REF_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_dm_vlgc_comp_en` reader - u0_cdn_usb_dm_vlgc_comp_en"] pub type U0_CDN_USB_DM_VLGC_COMP_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_dm_vlgc_comp_sts` reader - u0_cdn_usb_dm_vlgc_comp_sts"] pub type U0_CDN_USB_DM_VLGC_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_dm_vlgc_comp_sts` writer - u0_cdn_usb_dm_vlgc_comp_sts"] -pub type U0_CDN_USB_DM_VLGC_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_DM_VLGC_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_dp_vdat_ref_comp_en` reader - u0_cdn_usb_dp_vdat_ref_comp_en"] pub type U0_CDN_USB_DP_VDAT_REF_COMP_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_dp_vdat_ref_comp_sts` reader - u0_cdn_usb_dp_vdat_ref_comp_sts"] pub type U0_CDN_USB_DP_VDAT_REF_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_dp_vdat_ref_comp_sts` writer - u0_cdn_usb_dp_vdat_ref_comp_sts"] -pub type U0_CDN_USB_DP_VDAT_REF_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_DP_VDAT_REF_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_host_system_err` reader - u0_cdn_usb_host_system_err"] pub type U0_CDN_USB_HOST_SYSTEM_ERR_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_host_system_err` writer - u0_cdn_usb_host_system_err"] -pub type U0_CDN_USB_HOST_SYSTEM_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_HOST_SYSTEM_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_hsystem_err_ext` reader - u0_cdn_usb_hsystem_err_ext"] pub type U0_CDN_USB_HSYSTEM_ERR_EXT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_idm_sink_en` reader - u0_cdn_usb_idm_sink_en"] @@ -198,88 +198,90 @@ impl W { #[doc = "Bits 0:3 - scfg_hprot_sd0"] #[inline(always)] #[must_use] - pub fn scfg_hprot_sd0(&mut self) -> SCFG_HPROT_SD0_W { - SCFG_HPROT_SD0_W::new(self) + pub fn scfg_hprot_sd0(&mut self) -> SCFG_HPROT_SD0_W { + SCFG_HPROT_SD0_W::new(self, 0) } #[doc = "Bits 4:7 - scfg_hprot_sd1"] #[inline(always)] #[must_use] - pub fn scfg_hprot_sd1(&mut self) -> SCFG_HPROT_SD1_W { - SCFG_HPROT_SD1_W::new(self) + pub fn scfg_hprot_sd1(&mut self) -> SCFG_HPROT_SD1_W { + SCFG_HPROT_SD1_W::new(self, 4) } #[doc = "Bit 9 - u0_cdn_usb_adp_probe_ana"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_adp_probe_ana( &mut self, - ) -> U0_CDN_USB_ADP_PROBE_ANA_W { - U0_CDN_USB_ADP_PROBE_ANA_W::new(self) + ) -> U0_CDN_USB_ADP_PROBE_ANA_W { + U0_CDN_USB_ADP_PROBE_ANA_W::new(self, 9) } #[doc = "Bit 11 - u0_cdn_usb_adp_sense_ana"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_adp_sense_ana( &mut self, - ) -> U0_CDN_USB_ADP_SENSE_ANA_W { - U0_CDN_USB_ADP_SENSE_ANA_W::new(self) + ) -> U0_CDN_USB_ADP_SENSE_ANA_W { + U0_CDN_USB_ADP_SENSE_ANA_W::new(self, 11) } #[doc = "Bit 16 - u0_cdn_usb_chrg_vbus"] #[inline(always)] #[must_use] - pub fn u0_cdn_usb_chrg_vbus( - &mut self, - ) -> U0_CDN_USB_CHRG_VBUS_W { - U0_CDN_USB_CHRG_VBUS_W::new(self) + pub fn u0_cdn_usb_chrg_vbus(&mut self) -> U0_CDN_USB_CHRG_VBUS_W { + U0_CDN_USB_CHRG_VBUS_W::new(self, 16) } #[doc = "Bit 17 - u0_cdn_usb_dcd_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_dcd_comp_sts( &mut self, - ) -> U0_CDN_USB_DCD_COMP_STS_W { - U0_CDN_USB_DCD_COMP_STS_W::new(self) + ) -> U0_CDN_USB_DCD_COMP_STS_W { + U0_CDN_USB_DCD_COMP_STS_W::new(self, 17) } #[doc = "Bit 18 - u0_cdn_usb_dischrg_vbus"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_dischrg_vbus( &mut self, - ) -> U0_CDN_USB_DISCHRG_VBUS_W { - U0_CDN_USB_DISCHRG_VBUS_W::new(self) + ) -> U0_CDN_USB_DISCHRG_VBUS_W { + U0_CDN_USB_DISCHRG_VBUS_W::new(self, 18) } #[doc = "Bit 20 - u0_cdn_usb_dm_vdat_ref_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_dm_vdat_ref_comp_sts( &mut self, - ) -> U0_CDN_USB_DM_VDAT_REF_COMP_STS_W { - U0_CDN_USB_DM_VDAT_REF_COMP_STS_W::new(self) + ) -> U0_CDN_USB_DM_VDAT_REF_COMP_STS_W { + U0_CDN_USB_DM_VDAT_REF_COMP_STS_W::new(self, 20) } #[doc = "Bit 22 - u0_cdn_usb_dm_vlgc_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_dm_vlgc_comp_sts( &mut self, - ) -> U0_CDN_USB_DM_VLGC_COMP_STS_W { - U0_CDN_USB_DM_VLGC_COMP_STS_W::new(self) + ) -> U0_CDN_USB_DM_VLGC_COMP_STS_W { + U0_CDN_USB_DM_VLGC_COMP_STS_W::new(self, 22) } #[doc = "Bit 24 - u0_cdn_usb_dp_vdat_ref_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_dp_vdat_ref_comp_sts( &mut self, - ) -> U0_CDN_USB_DP_VDAT_REF_COMP_STS_W { - U0_CDN_USB_DP_VDAT_REF_COMP_STS_W::new(self) + ) -> U0_CDN_USB_DP_VDAT_REF_COMP_STS_W { + U0_CDN_USB_DP_VDAT_REF_COMP_STS_W::new(self, 24) } #[doc = "Bit 25 - u0_cdn_usb_host_system_err"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_host_system_err( &mut self, - ) -> U0_CDN_USB_HOST_SYSTEM_ERR_W { - U0_CDN_USB_HOST_SYSTEM_ERR_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_CDN_USB_HOST_SYSTEM_ERR_W { + U0_CDN_USB_HOST_SYSTEM_ERR_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg100.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg100.rs index 80dd684..45bc433 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg100.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg100.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg104.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg104.rs index 1adda62..4f179ca 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg104.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg104.rs @@ -28,7 +28,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg108.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg108.rs index 492434f..f583a5d 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg108.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg108.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg112.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg112.rs index 6c6e60a..00c20e4 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg112.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg112.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg116.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg116.rs index 0f63978..0256435 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg116.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg116.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg12.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg12.rs index 8ecb8dc..bd51844 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg12.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg12.rs @@ -7,44 +7,43 @@ pub type U0_CDN_USB_UTMI_RXVALIDH_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_sessvld` reader - u0_cdn_usb_utmi_sessvld"] pub type U0_CDN_USB_UTMI_SESSVLD_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_sessvld` writer - u0_cdn_usb_utmi_sessvld"] -pub type U0_CDN_USB_UTMI_SESSVLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_SESSVLD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_termselect_sit` reader - u0_cdn_usb_utmi_termselect_sit"] pub type U0_CDN_USB_UTMI_TERMSELECT_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_termselect_sit` writer - u0_cdn_usb_utmi_termselect_sit"] -pub type U0_CDN_USB_UTMI_TERMSELECT_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_TERMSELECT_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_tx_dat_sit` reader - u0_cdn_usb_utmi_tx_dat_sit"] pub type U0_CDN_USB_UTMI_TX_DAT_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_tx_dat_sit` writer - u0_cdn_usb_utmi_tx_dat_sit"] -pub type U0_CDN_USB_UTMI_TX_DAT_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_TX_DAT_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_tx_enable_n_sit` reader - u0_cdn_usb_utmi_tx_enable_n_sit"] pub type U0_CDN_USB_UTMI_TX_ENABLE_N_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_tx_enable_n_sit` writer - u0_cdn_usb_utmi_tx_enable_n_sit"] -pub type U0_CDN_USB_UTMI_TX_ENABLE_N_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_TX_ENABLE_N_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_tx_se0_sit` reader - u0_cdn_usb_utmi_tx_se0_sit"] pub type U0_CDN_USB_UTMI_TX_SE0_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_tx_se0_sit` writer - u0_cdn_usb_utmi_tx_se0_sit"] -pub type U0_CDN_USB_UTMI_TX_SE0_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_TX_SE0_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_txbitstuffenable_sit` reader - u0_cdn_usb_utmi_txbitstuffenable_sit"] pub type U0_CDN_USB_UTMI_TXBITSTUFFENABLE_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_txbitstuffenable_sit` writer - u0_cdn_usb_utmi_txbitstuffenable_sit"] -pub type U0_CDN_USB_UTMI_TXBITSTUFFENABLE_SIT_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_TXBITSTUFFENABLE_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_txready_sit` reader - u0_cdn_usb_utmi_txready_sit"] pub type U0_CDN_USB_UTMI_TXREADY_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_txvalid_sit` reader - u0_cdn_usb_utmi_txvalid_sit"] pub type U0_CDN_USB_UTMI_TXVALID_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_txvalid_sit` writer - u0_cdn_usb_utmi_txvalid_sit"] -pub type U0_CDN_USB_UTMI_TXVALID_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_TXVALID_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_txvalidh_sit` reader - u0_cdn_usb_utmi_txvalidh_sit"] pub type U0_CDN_USB_UTMI_TXVALIDH_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_txvalidh_sit` writer - u0_cdn_usb_utmi_txvalidh_sit"] -pub type U0_CDN_USB_UTMI_TXVALIDH_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_TXVALIDH_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_vbusvalid_sit` reader - u0_cdn_usb_utmi_vbusvalid_sit"] pub type U0_CDN_USB_UTMI_VBUSVALID_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_xcvrselect_sit` reader - u0_cdn_usb_utmi_xcvrselect_sit"] pub type U0_CDN_USB_UTMI_XCVRSELECT_SIT_R = crate::FieldReader; #[doc = "Field `u0_cdn_usb_utmi_xcvrselect_sit` writer - u0_cdn_usb_utmi_xcvrselect_sit"] -pub type U0_CDN_USB_UTMI_XCVRSELECT_SIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDN_USB_UTMI_XCVRSELECT_SIT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdn_usb_utmi_vdm_src_en` reader - u0_cdn_usb_utmi_vdm_src_en"] pub type U0_CDN_USB_UTMI_VDM_SRC_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_vdp_src_en` reader - u0_cdn_usb_utmi_vdp_src_en"] @@ -52,13 +51,13 @@ pub type U0_CDN_USB_UTMI_VDP_SRC_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_wakeup` reader - u0_cdn_usb_wakeup"] pub type U0_CDN_USB_WAKEUP_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_wakeup` writer - u0_cdn_usb_wakeup"] -pub type U0_CDN_USB_WAKEUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_WAKEUP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_xhc_d0_ack` reader - u0_cdn_usb_xhc_d0_ack"] pub type U0_CDN_USB_XHC_D0_ACK_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhc_d0_req` reader - u0_cdn_usb_xhc_d0_req"] pub type U0_CDN_USB_XHC_D0_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhc_d0_req` writer - u0_cdn_usb_xhc_d0_req"] -pub type U0_CDN_USB_XHC_D0_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_XHC_D0_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - u0_cdn_usb_utmi_rxvalidh_sit"] #[inline(always)] @@ -152,88 +151,92 @@ impl W { #[must_use] pub fn u0_cdn_usb_utmi_sessvld( &mut self, - ) -> U0_CDN_USB_UTMI_SESSVLD_W { - U0_CDN_USB_UTMI_SESSVLD_W::new(self) + ) -> U0_CDN_USB_UTMI_SESSVLD_W { + U0_CDN_USB_UTMI_SESSVLD_W::new(self, 1) } #[doc = "Bit 2 - u0_cdn_usb_utmi_termselect_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_termselect_sit( &mut self, - ) -> U0_CDN_USB_UTMI_TERMSELECT_SIT_W { - U0_CDN_USB_UTMI_TERMSELECT_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_TERMSELECT_SIT_W { + U0_CDN_USB_UTMI_TERMSELECT_SIT_W::new(self, 2) } #[doc = "Bit 3 - u0_cdn_usb_utmi_tx_dat_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_tx_dat_sit( &mut self, - ) -> U0_CDN_USB_UTMI_TX_DAT_SIT_W { - U0_CDN_USB_UTMI_TX_DAT_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_TX_DAT_SIT_W { + U0_CDN_USB_UTMI_TX_DAT_SIT_W::new(self, 3) } #[doc = "Bit 4 - u0_cdn_usb_utmi_tx_enable_n_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_tx_enable_n_sit( &mut self, - ) -> U0_CDN_USB_UTMI_TX_ENABLE_N_SIT_W { - U0_CDN_USB_UTMI_TX_ENABLE_N_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_TX_ENABLE_N_SIT_W { + U0_CDN_USB_UTMI_TX_ENABLE_N_SIT_W::new(self, 4) } #[doc = "Bit 5 - u0_cdn_usb_utmi_tx_se0_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_tx_se0_sit( &mut self, - ) -> U0_CDN_USB_UTMI_TX_SE0_SIT_W { - U0_CDN_USB_UTMI_TX_SE0_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_TX_SE0_SIT_W { + U0_CDN_USB_UTMI_TX_SE0_SIT_W::new(self, 5) } #[doc = "Bit 6 - u0_cdn_usb_utmi_txbitstuffenable_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_txbitstuffenable_sit( &mut self, - ) -> U0_CDN_USB_UTMI_TXBITSTUFFENABLE_SIT_W { - U0_CDN_USB_UTMI_TXBITSTUFFENABLE_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_TXBITSTUFFENABLE_SIT_W { + U0_CDN_USB_UTMI_TXBITSTUFFENABLE_SIT_W::new(self, 6) } #[doc = "Bit 8 - u0_cdn_usb_utmi_txvalid_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_txvalid_sit( &mut self, - ) -> U0_CDN_USB_UTMI_TXVALID_SIT_W { - U0_CDN_USB_UTMI_TXVALID_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_TXVALID_SIT_W { + U0_CDN_USB_UTMI_TXVALID_SIT_W::new(self, 8) } #[doc = "Bit 9 - u0_cdn_usb_utmi_txvalidh_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_txvalidh_sit( &mut self, - ) -> U0_CDN_USB_UTMI_TXVALIDH_SIT_W { - U0_CDN_USB_UTMI_TXVALIDH_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_TXVALIDH_SIT_W { + U0_CDN_USB_UTMI_TXVALIDH_SIT_W::new(self, 9) } #[doc = "Bits 11:12 - u0_cdn_usb_utmi_xcvrselect_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_xcvrselect_sit( &mut self, - ) -> U0_CDN_USB_UTMI_XCVRSELECT_SIT_W { - U0_CDN_USB_UTMI_XCVRSELECT_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_XCVRSELECT_SIT_W { + U0_CDN_USB_UTMI_XCVRSELECT_SIT_W::new(self, 11) } #[doc = "Bit 15 - u0_cdn_usb_wakeup"] #[inline(always)] #[must_use] - pub fn u0_cdn_usb_wakeup(&mut self) -> U0_CDN_USB_WAKEUP_W { - U0_CDN_USB_WAKEUP_W::new(self) + pub fn u0_cdn_usb_wakeup(&mut self) -> U0_CDN_USB_WAKEUP_W { + U0_CDN_USB_WAKEUP_W::new(self, 15) } #[doc = "Bit 17 - u0_cdn_usb_xhc_d0_req"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_xhc_d0_req( &mut self, - ) -> U0_CDN_USB_XHC_D0_REQ_W { - U0_CDN_USB_XHC_D0_REQ_W::new(self) + ) -> U0_CDN_USB_XHC_D0_REQ_W { + U0_CDN_USB_XHC_D0_REQ_W::new(self, 17) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg120.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg120.rs index 86c1c12..caa5895 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg120.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg120.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg124.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg124.rs index ac94c10..574a1b2 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg124.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg124.rs @@ -7,7 +7,7 @@ pub type U0_PLDA_PCIE_AXI4_MST0_AWUSER_42_32_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_mst0_rderr` reader - u0_plda_pcie_axi4_mst0_rderr"] pub type U0_PLDA_PCIE_AXI4_MST0_RDERR_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_mst0_rderr` writer - u0_plda_pcie_axi4_mst0_rderr"] -pub type U0_PLDA_PCIE_AXI4_MST0_RDERR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type U0_PLDA_PCIE_AXI4_MST0_RDERR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:10 - u0_plda_pcie_axi4_mst0_awuser_42_32"] #[inline(always)] @@ -26,10 +26,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_mst0_rderr( &mut self, - ) -> U0_PLDA_PCIE_AXI4_MST0_RDERR_W { - U0_PLDA_PCIE_AXI4_MST0_RDERR_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_MST0_RDERR_W { + U0_PLDA_PCIE_AXI4_MST0_RDERR_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg128.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg128.rs index 7f6e88e..805761e 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg128.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg128.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_mst0_ruser` reader - u0_plda_pcie_axi4_mst0_ruser"] pub type U0_PLDA_PCIE_AXI4_MST0_RUSER_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_mst0_ruser` writer - u0_plda_pcie_axi4_mst0_ruser"] -pub type U0_PLDA_PCIE_AXI4_MST0_RUSER_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_MST0_RUSER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_mst0_ruser"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_mst0_ruser( &mut self, - ) -> U0_PLDA_PCIE_AXI4_MST0_RUSER_W { - U0_PLDA_PCIE_AXI4_MST0_RUSER_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_MST0_RUSER_W { + U0_PLDA_PCIE_AXI4_MST0_RUSER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg132.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg132.rs index 1073759..9e2b614 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg132.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg132.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg136.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg136.rs index 9c0fe6d..285abf3 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg136.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg136.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_31_0` reader - u0_plda_pcie_axi4_slv0_aratomop_31_0"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_31_0` writer - u0_plda_pcie_axi4_slv0_aratomop_31_0"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aratomop_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_31_0( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg140.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg140.rs index 8d1537e..26fd0a6 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg140.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg140.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_63_32` reader - u0_plda_pcie_axi4_slv0_aratomop_63_32"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_63_32` writer - u0_plda_pcie_axi4_slv0_aratomop_63_32"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aratomop_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_63_32( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg144.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg144.rs index ebfe682..d4ecc58 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg144.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg144.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_95_64` reader - u0_plda_pcie_axi4_slv0_aratomop_95_64"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_95_64` writer - u0_plda_pcie_axi4_slv0_aratomop_95_64"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aratomop_95_64"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_95_64( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg148.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg148.rs index ea53397..58ea16a 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg148.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg148.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_127_96` reader - u0_plda_pcie_axi4_slv0_aratomop_127_96"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_127_96` writer - u0_plda_pcie_axi4_slv0_aratomop_127_96"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aratomop_127_96"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_127_96( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg152.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg152.rs index dc75b37..e7368cd 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg152.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg152.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_159_128` reader - u0_plda_pcie_axi4_slv0_aratomop_159_128"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_159_128` writer - u0_plda_pcie_axi4_slv0_aratomop_159_128"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aratomop_159_128"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_159_128( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg156.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg156.rs index 44cd4f4..7deb5ac 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg156.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg156.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_191_160` reader - u0_plda_pcie_axi4_slv0_aratomop_191_160"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_191_160` writer - u0_plda_pcie_axi4_slv0_aratomop_191_160"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aratomop_191_160"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_191_160( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg16.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg16.rs index 37cc577..62aa5a5 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg16.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg16.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg160.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg160.rs index 63f2ff0..0c3d846 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg160.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg160.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_223_192` reader - u0_plda_pcie_axi4_slv0_aratomop_223_192"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_223_192` writer - u0_plda_pcie_axi4_slv0_aratomop_223_192"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aratomop_223_192"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_223_192( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg164.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg164.rs index a929878..26a4df4 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg164.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg164.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_255_224` reader - u0_plda_pcie_axi4_slv0_aratomop_255_224"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_255_224` writer - u0_plda_pcie_axi4_slv0_aratomop_255_224"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aratomop_255_224"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_255_224( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg168.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg168.rs index 4805eed..cf6b171 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg168.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg168.rs @@ -5,18 +5,15 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_257_256` reader - u0_plda_pcie_axi4_slv0_aratomop_257_256"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_257_256_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aratomop_257_256` writer - u0_plda_pcie_axi4_slv0_aratomop_257_256"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_257_256_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_257_256_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_plda_pcie_axi4_slv0_arfunc` reader - u0_plda_pcie_axi4_slv0_arfunc"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARFUNC_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_arfunc` writer - u0_plda_pcie_axi4_slv0_arfunc"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARFUNC_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 15, O, u16>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARFUNC_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; #[doc = "Field `u0_plda_pcie_axi4_slv0_arregion` reader - u0_plda_pcie_axi4_slv0_arregion"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARREGION_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_arregion` writer - u0_plda_pcie_axi4_slv0_arregion"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARREGION_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 4, O>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARREGION_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:1 - u0_plda_pcie_axi4_slv0_aratomop_257_256"] #[inline(always)] @@ -42,26 +39,30 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aratomop_257_256( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_257_256_W { - U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_257_256_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_257_256_W { + U0_PLDA_PCIE_AXI4_SLV0_ARATOMOP_257_256_W::new(self, 0) } #[doc = "Bits 2:16 - u0_plda_pcie_axi4_slv0_arfunc"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_axi4_slv0_arfunc( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARFUNC_W { - U0_PLDA_PCIE_AXI4_SLV0_ARFUNC_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARFUNC_W { + U0_PLDA_PCIE_AXI4_SLV0_ARFUNC_W::new(self, 2) } #[doc = "Bits 17:20 - u0_plda_pcie_axi4_slv0_arregion"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_axi4_slv0_arregion( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARREGION_W { - U0_PLDA_PCIE_AXI4_SLV0_ARREGION_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARREGION_W { + U0_PLDA_PCIE_AXI4_SLV0_ARREGION_W::new(self, 17) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg172.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg172.rs index d4fca62..fe8a65a 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg172.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg172.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aruser_31_0` reader - u0_plda_pcie_axi4_slv0_aruser_31_0"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aruser_31_0` writer - u0_plda_pcie_axi4_slv0_aruser_31_0"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_aruser_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aruser_31_0( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W { - U0_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W { + U0_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg176.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg176.rs index a4e74f2..3e00342 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg176.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg176.rs @@ -5,18 +5,15 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_aruser_40_32` reader - u0_plda_pcie_axi4_slv0_aruser_40_32"] pub type U0_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_aruser_40_32` writer - u0_plda_pcie_axi4_slv0_aruser_40_32"] -pub type U0_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 9, O, u16>; +pub type U0_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; #[doc = "Field `u0_plda_pcie_axi4_slv0_awfunc` reader - u0_plda_pcie_axi4_slv0_awfunc"] pub type U0_PLDA_PCIE_AXI4_SLV0_AWFUNC_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_awfunc` writer - u0_plda_pcie_axi4_slv0_awfunc"] -pub type U0_PLDA_PCIE_AXI4_SLV0_AWFUNC_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 15, O, u16>; +pub type U0_PLDA_PCIE_AXI4_SLV0_AWFUNC_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; #[doc = "Field `u0_plda_pcie_axi4_slv0_awregion` reader - u0_plda_pcie_axi4_slv0_awregion"] pub type U0_PLDA_PCIE_AXI4_SLV0_AWREGION_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_awregion` writer - u0_plda_pcie_axi4_slv0_awregion"] -pub type U0_PLDA_PCIE_AXI4_SLV0_AWREGION_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 4, O>; +pub type U0_PLDA_PCIE_AXI4_SLV0_AWREGION_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:8 - u0_plda_pcie_axi4_slv0_aruser_40_32"] #[inline(always)] @@ -40,26 +37,30 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_aruser_40_32( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W { - U0_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W { + U0_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W::new(self, 0) } #[doc = "Bits 9:23 - u0_plda_pcie_axi4_slv0_awfunc"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_axi4_slv0_awfunc( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_AWFUNC_W { - U0_PLDA_PCIE_AXI4_SLV0_AWFUNC_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_AWFUNC_W { + U0_PLDA_PCIE_AXI4_SLV0_AWFUNC_W::new(self, 9) } #[doc = "Bits 24:27 - u0_plda_pcie_axi4_slv0_awregion"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_axi4_slv0_awregion( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_AWREGION_W { - U0_PLDA_PCIE_AXI4_SLV0_AWREGION_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_AWREGION_W { + U0_PLDA_PCIE_AXI4_SLV0_AWREGION_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg180.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg180.rs index f840e71..dd6d1f4 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg180.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg180.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_awuser_31_0` reader - u0_plda_pcie_axi4_slv0_awuser_31_0"] pub type U0_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_awuser_31_0` writer - u0_plda_pcie_axi4_slv0_awuser_31_0"] -pub type U0_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_axi4_slv0_awuser_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_awuser_31_0( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W { - U0_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W { + U0_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg184.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg184.rs index 97e85af..003d48c 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg184.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg184.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_awuser_40_32` reader - u0_plda_pcie_axi4_slv0_awuser_40_32"] pub type U0_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_awuser_40_32` writer - u0_plda_pcie_axi4_slv0_awuser_40_32"] -pub type U0_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 9, O, u16>; +pub type U0_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; #[doc = "Field `u0_plda_pcie_axi4_slv0_rderr` reader - u0_plda_pcie_axi4_slv0_rderr"] pub type U0_PLDA_PCIE_AXI4_SLV0_RDERR_R = crate::FieldReader; impl R { @@ -27,10 +26,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_awuser_40_32( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W { - U0_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W { + U0_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg188.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg188.rs index 34d0d9e..3d0bc55 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg188.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg188.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg192.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg192.rs index 2f8132e..b7bd395 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg192.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg192.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slv0_wderr` reader - u0_plda_pcie_axi4_slv0_wderr"] pub type U0_PLDA_PCIE_AXI4_SLV0_WDERR_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slv0_wderr` writer - u0_plda_pcie_axi4_slv0_wderr"] -pub type U0_PLDA_PCIE_AXI4_SLV0_WDERR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type U0_PLDA_PCIE_AXI4_SLV0_WDERR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `u0_plda_pcie_axi4_slvl_arfunc` reader - u0_plda_pcie_axi4_slvl_arfunc"] pub type U0_PLDA_PCIE_AXI4_SLVL_ARFUNC_R = crate::FieldReader; impl R { @@ -26,10 +26,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slv0_wderr( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLV0_WDERR_W { - U0_PLDA_PCIE_AXI4_SLV0_WDERR_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLV0_WDERR_W { + U0_PLDA_PCIE_AXI4_SLV0_WDERR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg196.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg196.rs index d37d50b..281bc93 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg196.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg196.rs @@ -5,26 +5,25 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_axi4_slvl_awfunc` reader - u0_plda_pcie_axi4_slvl_awfunc"] pub type U0_PLDA_PCIE_AXI4_SLVL_AWFUNC_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_axi4_slvl_awfunc` writer - u0_plda_pcie_axi4_slvl_awfunc"] -pub type U0_PLDA_PCIE_AXI4_SLVL_AWFUNC_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 15, O, u16>; +pub type U0_PLDA_PCIE_AXI4_SLVL_AWFUNC_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; #[doc = "Field `u0_plda_pcie_bus_width_o` reader - u0_plda_pcie_bus_width_o"] pub type U0_PLDA_PCIE_BUS_WIDTH_O_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_bypass_codec` reader - u0_plda_pcie_bypass_codec"] pub type U0_PLDA_PCIE_BYPASS_CODEC_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_bypass_codec` writer - u0_plda_pcie_bypass_codec"] -pub type U0_PLDA_PCIE_BYPASS_CODEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_BYPASS_CODEC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_ckref_src` reader - u0_plda_pcie_ckref_src"] pub type U0_PLDA_PCIE_CKREF_SRC_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_ckref_src` writer - u0_plda_pcie_ckref_src"] -pub type U0_PLDA_PCIE_CKREF_SRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLDA_PCIE_CKREF_SRC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_plda_pcie_clk_sel` reader - u0_plda_pcie_clk_sel"] pub type U0_PLDA_PCIE_CLK_SEL_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_clk_sel` writer - u0_plda_pcie_clk_sel"] -pub type U0_PLDA_PCIE_CLK_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLDA_PCIE_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_plda_pcie_clkreq` reader - u0_plda_pcie_clkreq"] pub type U0_PLDA_PCIE_CLKREQ_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_clkreq` writer - u0_plda_pcie_clkreq"] -pub type U0_PLDA_PCIE_CLKREQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_CLKREQ_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:14 - u0_plda_pcie_axi4_slvl_awfunc"] #[inline(always)] @@ -63,42 +62,44 @@ impl W { #[must_use] pub fn u0_plda_pcie_axi4_slvl_awfunc( &mut self, - ) -> U0_PLDA_PCIE_AXI4_SLVL_AWFUNC_W { - U0_PLDA_PCIE_AXI4_SLVL_AWFUNC_W::new(self) + ) -> U0_PLDA_PCIE_AXI4_SLVL_AWFUNC_W { + U0_PLDA_PCIE_AXI4_SLVL_AWFUNC_W::new(self, 0) } #[doc = "Bit 17 - u0_plda_pcie_bypass_codec"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_bypass_codec( &mut self, - ) -> U0_PLDA_PCIE_BYPASS_CODEC_W { - U0_PLDA_PCIE_BYPASS_CODEC_W::new(self) + ) -> U0_PLDA_PCIE_BYPASS_CODEC_W { + U0_PLDA_PCIE_BYPASS_CODEC_W::new(self, 17) } #[doc = "Bits 18:19 - u0_plda_pcie_ckref_src"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_ckref_src( &mut self, - ) -> U0_PLDA_PCIE_CKREF_SRC_W { - U0_PLDA_PCIE_CKREF_SRC_W::new(self) + ) -> U0_PLDA_PCIE_CKREF_SRC_W { + U0_PLDA_PCIE_CKREF_SRC_W::new(self, 18) } #[doc = "Bits 20:21 - u0_plda_pcie_clk_sel"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_clk_sel( &mut self, - ) -> U0_PLDA_PCIE_CLK_SEL_W { - U0_PLDA_PCIE_CLK_SEL_W::new(self) + ) -> U0_PLDA_PCIE_CLK_SEL_W { + U0_PLDA_PCIE_CLK_SEL_W::new(self, 20) } #[doc = "Bit 22 - u0_plda_pcie_clkreq"] #[inline(always)] #[must_use] - pub fn u0_plda_pcie_clkreq( - &mut self, - ) -> U0_PLDA_PCIE_CLKREQ_W { - U0_PLDA_PCIE_CLKREQ_W::new(self) + pub fn u0_plda_pcie_clkreq(&mut self) -> U0_PLDA_PCIE_CLKREQ_W { + U0_PLDA_PCIE_CLKREQ_W::new(self, 22) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg20.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg20.rs index 0873486..5d98f12 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg20.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg20.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg200.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg200.rs index c1d847e..598ac36 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg200.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg200.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_31_0` reader - u0_plda_pcie_k_phyparam_31_0"] pub type U0_PLDA_PCIE_K_PHYPARAM_31_0_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_31_0` writer - u0_plda_pcie_k_phyparam_31_0"] -pub type U0_PLDA_PCIE_K_PHYPARAM_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_31_0( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_31_0_W { - U0_PLDA_PCIE_K_PHYPARAM_31_0_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_31_0_W { + U0_PLDA_PCIE_K_PHYPARAM_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg204.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg204.rs index 5bbcdfb..d2b37e7 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg204.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg204.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_63_32` reader - u0_plda_pcie_k_phyparam_63_32"] pub type U0_PLDA_PCIE_K_PHYPARAM_63_32_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_63_32` writer - u0_plda_pcie_k_phyparam_63_32"] -pub type U0_PLDA_PCIE_K_PHYPARAM_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_63_32( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_63_32_W { - U0_PLDA_PCIE_K_PHYPARAM_63_32_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_63_32_W { + U0_PLDA_PCIE_K_PHYPARAM_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg208.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg208.rs index 531f21d..2466778 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg208.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg208.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_95_64` reader - u0_plda_pcie_k_phyparam_95_64"] pub type U0_PLDA_PCIE_K_PHYPARAM_95_64_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_95_64` writer - u0_plda_pcie_k_phyparam_95_64"] -pub type U0_PLDA_PCIE_K_PHYPARAM_95_64_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_95_64_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_95_64"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_95_64( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_95_64_W { - U0_PLDA_PCIE_K_PHYPARAM_95_64_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_95_64_W { + U0_PLDA_PCIE_K_PHYPARAM_95_64_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg212.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg212.rs index 491907b..3e8f2e8 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg212.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg212.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_127_96` reader - u0_plda_pcie_k_phyparam_127_96"] pub type U0_PLDA_PCIE_K_PHYPARAM_127_96_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_127_96` writer - u0_plda_pcie_k_phyparam_127_96"] -pub type U0_PLDA_PCIE_K_PHYPARAM_127_96_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_127_96_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_127_96"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_127_96( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_127_96_W { - U0_PLDA_PCIE_K_PHYPARAM_127_96_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_127_96_W { + U0_PLDA_PCIE_K_PHYPARAM_127_96_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg216.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg216.rs index a68a7f3..118ea10 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg216.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg216.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_159_128` reader - u0_plda_pcie_k_phyparam_159_128"] pub type U0_PLDA_PCIE_K_PHYPARAM_159_128_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_159_128` writer - u0_plda_pcie_k_phyparam_159_128"] -pub type U0_PLDA_PCIE_K_PHYPARAM_159_128_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_159_128_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_159_128"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_159_128( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_159_128_W { - U0_PLDA_PCIE_K_PHYPARAM_159_128_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_159_128_W { + U0_PLDA_PCIE_K_PHYPARAM_159_128_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg220.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg220.rs index cda6df2..38e3cd3 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg220.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg220.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_191_160` reader - u0_plda_pcie_k_phyparam_191_160"] pub type U0_PLDA_PCIE_K_PHYPARAM_191_160_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_191_160` writer - u0_plda_pcie_k_phyparam_191_160"] -pub type U0_PLDA_PCIE_K_PHYPARAM_191_160_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_191_160_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_191_160"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_191_160( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_191_160_W { - U0_PLDA_PCIE_K_PHYPARAM_191_160_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_191_160_W { + U0_PLDA_PCIE_K_PHYPARAM_191_160_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg224.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg224.rs index a907bba..791783f 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg224.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg224.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_223_192` reader - u0_plda_pcie_k_phyparam_223_192"] pub type U0_PLDA_PCIE_K_PHYPARAM_223_192_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_223_192` writer - u0_plda_pcie_k_phyparam_223_192"] -pub type U0_PLDA_PCIE_K_PHYPARAM_223_192_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_223_192_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_223_192"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_223_192( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_223_192_W { - U0_PLDA_PCIE_K_PHYPARAM_223_192_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_223_192_W { + U0_PLDA_PCIE_K_PHYPARAM_223_192_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg228.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg228.rs index d00df8e..f108222 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg228.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg228.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_255_224` reader - u0_plda_pcie_k_phyparam_255_224"] pub type U0_PLDA_PCIE_K_PHYPARAM_255_224_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_255_224` writer - u0_plda_pcie_k_phyparam_255_224"] -pub type U0_PLDA_PCIE_K_PHYPARAM_255_224_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_255_224_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_255_224"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_255_224( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_255_224_W { - U0_PLDA_PCIE_K_PHYPARAM_255_224_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_255_224_W { + U0_PLDA_PCIE_K_PHYPARAM_255_224_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg232.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg232.rs index b885c46..19b95e2 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg232.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg232.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_287_256` reader - u0_plda_pcie_k_phyparam_287_256"] pub type U0_PLDA_PCIE_K_PHYPARAM_287_256_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_287_256` writer - u0_plda_pcie_k_phyparam_287_256"] -pub type U0_PLDA_PCIE_K_PHYPARAM_287_256_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_287_256_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_287_256"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_287_256( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_287_256_W { - U0_PLDA_PCIE_K_PHYPARAM_287_256_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_287_256_W { + U0_PLDA_PCIE_K_PHYPARAM_287_256_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg236.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg236.rs index 358059f..770d70a 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg236.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg236.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_319_288` reader - u0_plda_pcie_k_phyparam_319_288"] pub type U0_PLDA_PCIE_K_PHYPARAM_319_288_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_319_288` writer - u0_plda_pcie_k_phyparam_319_288"] -pub type U0_PLDA_PCIE_K_PHYPARAM_319_288_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_319_288_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_319_288"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_319_288( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_319_288_W { - U0_PLDA_PCIE_K_PHYPARAM_319_288_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_319_288_W { + U0_PLDA_PCIE_K_PHYPARAM_319_288_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg24.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg24.rs index c49afbe..6ecfa1c 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg24.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg24.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_cdn_usb_xhci_debug_sel` reader - u0_cdn_usb_xhci_debug_sel"] pub type U0_CDN_USB_XHCI_DEBUG_SEL_R = crate::FieldReader; #[doc = "Field `u0_cdn_usb_xhci_debug_sel` writer - u0_cdn_usb_xhci_debug_sel"] -pub type U0_CDN_USB_XHCI_DEBUG_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_CDN_USB_XHCI_DEBUG_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_cdn_usb_xhci_main_power_off_ack` reader - u0_cdn_usb_xhci_main_power_off_ack"] pub type U0_CDN_USB_XHCI_MAIN_POWER_OFF_ACK_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_main_power_off_req` reader - u0_cdn_usb_xhci_main_power_off_req"] @@ -13,13 +13,13 @@ pub type U0_CDN_USB_XHCI_MAIN_POWER_OFF_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_main_power_on_ready` reader - u0_cdn_usb_xhci_main_power_on_ready"] pub type U0_CDN_USB_XHCI_MAIN_POWER_ON_READY_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_main_power_on_ready` writer - u0_cdn_usb_xhci_main_power_on_ready"] -pub type U0_CDN_USB_XHCI_MAIN_POWER_ON_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_XHCI_MAIN_POWER_ON_READY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_xhci_main_power_on_req` reader - u0_cdn_usb_xhci_main_power_on_req"] pub type U0_CDN_USB_XHCI_MAIN_POWER_ON_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_main_power_on_valid` reader - u0_cdn_usb_xhci_main_power_on_valid"] pub type U0_CDN_USB_XHCI_MAIN_POWER_ON_VALID_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_main_power_on_valid` writer - u0_cdn_usb_xhci_main_power_on_valid"] -pub type U0_CDN_USB_XHCI_MAIN_POWER_ON_VALID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_XHCI_MAIN_POWER_ON_VALID_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_xhci_power_off_ack` reader - u0_cdn_usb_xhci_power_off_ack"] pub type U0_CDN_USB_XHCI_POWER_OFF_ACK_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_power_off_ready` reader - u0_cdn_usb_xhci_power_off_ready"] @@ -27,7 +27,7 @@ pub type U0_CDN_USB_XHCI_POWER_OFF_READY_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_power_off_req` reader - u0_cdn_usb_xhci_power_off_req"] pub type U0_CDN_USB_XHCI_POWER_OFF_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_power_off_req` writer - u0_cdn_usb_xhci_power_off_req"] -pub type U0_CDN_USB_XHCI_POWER_OFF_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_XHCI_POWER_OFF_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_xhci_power_on_ready` reader - u0_cdn_usb_xhci_power_on_ready"] pub type U0_CDN_USB_XHCI_POWER_ON_READY_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_power_on_req` reader - u0_cdn_usb_xhci_power_on_req"] @@ -35,7 +35,7 @@ pub type U0_CDN_USB_XHCI_POWER_ON_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_power_on_valid` reader - u0_cdn_usb_xhci_power_on_valid"] pub type U0_CDN_USB_XHCI_POWER_ON_VALID_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_xhci_power_on_valid` writer - u0_cdn_usb_xhci_power_on_valid"] -pub type U0_CDN_USB_XHCI_POWER_ON_VALID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_XHCI_POWER_ON_VALID_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_e2_sft7110_cease_from_tile_0` reader - u0_e2_sft7110_cease_from_tile_0"] pub type U0_E2_SFT7110_CEASE_FROM_TILE_0_R = crate::BitReader; #[doc = "Field `u0_e2_sft7110_debug_from_tile_0` reader - u0_e2_sft7110_debug_from_tile_0"] @@ -125,42 +125,46 @@ impl W { #[must_use] pub fn u0_cdn_usb_xhci_debug_sel( &mut self, - ) -> U0_CDN_USB_XHCI_DEBUG_SEL_W { - U0_CDN_USB_XHCI_DEBUG_SEL_W::new(self) + ) -> U0_CDN_USB_XHCI_DEBUG_SEL_W { + U0_CDN_USB_XHCI_DEBUG_SEL_W::new(self, 0) } #[doc = "Bit 7 - u0_cdn_usb_xhci_main_power_on_ready"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_xhci_main_power_on_ready( &mut self, - ) -> U0_CDN_USB_XHCI_MAIN_POWER_ON_READY_W { - U0_CDN_USB_XHCI_MAIN_POWER_ON_READY_W::new(self) + ) -> U0_CDN_USB_XHCI_MAIN_POWER_ON_READY_W { + U0_CDN_USB_XHCI_MAIN_POWER_ON_READY_W::new(self, 7) } #[doc = "Bit 9 - u0_cdn_usb_xhci_main_power_on_valid"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_xhci_main_power_on_valid( &mut self, - ) -> U0_CDN_USB_XHCI_MAIN_POWER_ON_VALID_W { - U0_CDN_USB_XHCI_MAIN_POWER_ON_VALID_W::new(self) + ) -> U0_CDN_USB_XHCI_MAIN_POWER_ON_VALID_W { + U0_CDN_USB_XHCI_MAIN_POWER_ON_VALID_W::new(self, 9) } #[doc = "Bit 12 - u0_cdn_usb_xhci_power_off_req"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_xhci_power_off_req( &mut self, - ) -> U0_CDN_USB_XHCI_POWER_OFF_REQ_W { - U0_CDN_USB_XHCI_POWER_OFF_REQ_W::new(self) + ) -> U0_CDN_USB_XHCI_POWER_OFF_REQ_W { + U0_CDN_USB_XHCI_POWER_OFF_REQ_W::new(self, 12) } #[doc = "Bit 15 - u0_cdn_usb_xhci_power_on_valid"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_xhci_power_on_valid( &mut self, - ) -> U0_CDN_USB_XHCI_POWER_ON_VALID_W { - U0_CDN_USB_XHCI_POWER_ON_VALID_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_CDN_USB_XHCI_POWER_ON_VALID_W { + U0_CDN_USB_XHCI_POWER_ON_VALID_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg240.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg240.rs index 993cc37..7cdce70 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg240.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg240.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_351_320` reader - u0_plda_pcie_k_phyparam_351_320"] pub type U0_PLDA_PCIE_K_PHYPARAM_351_320_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_351_320` writer - u0_plda_pcie_k_phyparam_351_320"] -pub type U0_PLDA_PCIE_K_PHYPARAM_351_320_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_351_320_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_351_320"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_351_320( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_351_320_W { - U0_PLDA_PCIE_K_PHYPARAM_351_320_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_351_320_W { + U0_PLDA_PCIE_K_PHYPARAM_351_320_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg244.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg244.rs index 8c7599a..80a76d8 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg244.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg244.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_383_352` reader - u0_plda_pcie_k_phyparam_383_352"] pub type U0_PLDA_PCIE_K_PHYPARAM_383_352_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_383_352` writer - u0_plda_pcie_k_phyparam_383_352"] -pub type U0_PLDA_PCIE_K_PHYPARAM_383_352_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_383_352_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_383_352"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_383_352( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_383_352_W { - U0_PLDA_PCIE_K_PHYPARAM_383_352_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_383_352_W { + U0_PLDA_PCIE_K_PHYPARAM_383_352_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg248.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg248.rs index 70d62ce..efaec9f 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg248.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg248.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_415_384` reader - u0_plda_pcie_k_phyparam_415_384"] pub type U0_PLDA_PCIE_K_PHYPARAM_415_384_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_415_384` writer - u0_plda_pcie_k_phyparam_415_384"] -pub type U0_PLDA_PCIE_K_PHYPARAM_415_384_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_415_384_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_415_384"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_415_384( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_415_384_W { - U0_PLDA_PCIE_K_PHYPARAM_415_384_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_415_384_W { + U0_PLDA_PCIE_K_PHYPARAM_415_384_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg252.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg252.rs index 0cd1a0f..d87d0a8 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg252.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg252.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_447_416` reader - u0_plda_pcie_k_phyparam_447_416"] pub type U0_PLDA_PCIE_K_PHYPARAM_447_416_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_447_416` writer - u0_plda_pcie_k_phyparam_447_416"] -pub type U0_PLDA_PCIE_K_PHYPARAM_447_416_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_447_416_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_447_416"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_447_416( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_447_416_W { - U0_PLDA_PCIE_K_PHYPARAM_447_416_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_447_416_W { + U0_PLDA_PCIE_K_PHYPARAM_447_416_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg256.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg256.rs index b5f63c9..1e2030f 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg256.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg256.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_479_448` reader - u0_plda_pcie_k_phyparam_479_448"] pub type U0_PLDA_PCIE_K_PHYPARAM_479_448_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_479_448` writer - u0_plda_pcie_k_phyparam_479_448"] -pub type U0_PLDA_PCIE_K_PHYPARAM_479_448_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_479_448_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_479_448"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_479_448( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_479_448_W { - U0_PLDA_PCIE_K_PHYPARAM_479_448_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_479_448_W { + U0_PLDA_PCIE_K_PHYPARAM_479_448_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg260.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg260.rs index 5ba063c..534d29d 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg260.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg260.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_511_480` reader - u0_plda_pcie_k_phyparam_511_480"] pub type U0_PLDA_PCIE_K_PHYPARAM_511_480_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_511_480` writer - u0_plda_pcie_k_phyparam_511_480"] -pub type U0_PLDA_PCIE_K_PHYPARAM_511_480_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_511_480_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_511_480"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_511_480( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_511_480_W { - U0_PLDA_PCIE_K_PHYPARAM_511_480_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_511_480_W { + U0_PLDA_PCIE_K_PHYPARAM_511_480_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg264.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg264.rs index cd6f826..5d4c4bc 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg264.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg264.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_543_512` reader - u0_plda_pcie_k_phyparam_543_512"] pub type U0_PLDA_PCIE_K_PHYPARAM_543_512_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_543_512` writer - u0_plda_pcie_k_phyparam_543_512"] -pub type U0_PLDA_PCIE_K_PHYPARAM_543_512_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_543_512_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_543_512"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_543_512( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_543_512_W { - U0_PLDA_PCIE_K_PHYPARAM_543_512_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_543_512_W { + U0_PLDA_PCIE_K_PHYPARAM_543_512_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg268.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg268.rs index 4e9b839..a34dc7b 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg268.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg268.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_575_544` reader - u0_plda_pcie_k_phyparam_575_544"] pub type U0_PLDA_PCIE_K_PHYPARAM_575_544_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_575_544` writer - u0_plda_pcie_k_phyparam_575_544"] -pub type U0_PLDA_PCIE_K_PHYPARAM_575_544_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_575_544_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_575_544"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_575_544( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_575_544_W { - U0_PLDA_PCIE_K_PHYPARAM_575_544_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_575_544_W { + U0_PLDA_PCIE_K_PHYPARAM_575_544_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg272.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg272.rs index c3c56ae..cdab83a 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg272.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg272.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_607_576` reader - u0_plda_pcie_k_phyparam_607_576"] pub type U0_PLDA_PCIE_K_PHYPARAM_607_576_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_607_576` writer - u0_plda_pcie_k_phyparam_607_576"] -pub type U0_PLDA_PCIE_K_PHYPARAM_607_576_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_607_576_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_607_576"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_607_576( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_607_576_W { - U0_PLDA_PCIE_K_PHYPARAM_607_576_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_607_576_W { + U0_PLDA_PCIE_K_PHYPARAM_607_576_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg276.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg276.rs index d1993a0..1ec64a9 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg276.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg276.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_639_608` reader - u0_plda_pcie_k_phyparam_639_608"] pub type U0_PLDA_PCIE_K_PHYPARAM_639_608_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_639_608` writer - u0_plda_pcie_k_phyparam_639_608"] -pub type U0_PLDA_PCIE_K_PHYPARAM_639_608_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_639_608_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_639_608"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_639_608( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_639_608_W { - U0_PLDA_PCIE_K_PHYPARAM_639_608_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_639_608_W { + U0_PLDA_PCIE_K_PHYPARAM_639_608_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg28.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg28.rs index f03ff50..2d392e1 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg28.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg28.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_e2_sft7110_nmi_0_rnmi_exception_vector` reader - u0_e2_sft7110_nmi_0_rnmi_exception_vector"] pub type U0_E2_SFT7110_NMI_0_RNMI_EXCEPTION_VECTOR_R = crate::FieldReader; #[doc = "Field `u0_e2_sft7110_nmi_0_rnmi_exception_vector` writer - u0_e2_sft7110_nmi_0_rnmi_exception_vector"] -pub type U0_E2_SFT7110_NMI_0_RNMI_EXCEPTION_VECTOR_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_E2_SFT7110_NMI_0_RNMI_EXCEPTION_VECTOR_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_e2_sft7110_nmi_0_rnmi_exception_vector"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_e2_sft7110_nmi_0_rnmi_exception_vector( &mut self, - ) -> U0_E2_SFT7110_NMI_0_RNMI_EXCEPTION_VECTOR_W { - U0_E2_SFT7110_NMI_0_RNMI_EXCEPTION_VECTOR_W::new(self) + ) -> U0_E2_SFT7110_NMI_0_RNMI_EXCEPTION_VECTOR_W { + U0_E2_SFT7110_NMI_0_RNMI_EXCEPTION_VECTOR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg280.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg280.rs index e11240d..f0d3af8 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg280.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg280.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_671_640` reader - u0_plda_pcie_k_phyparam_671_640"] pub type U0_PLDA_PCIE_K_PHYPARAM_671_640_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_671_640` writer - u0_plda_pcie_k_phyparam_671_640"] -pub type U0_PLDA_PCIE_K_PHYPARAM_671_640_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_671_640_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_671_640"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_671_640( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_671_640_W { - U0_PLDA_PCIE_K_PHYPARAM_671_640_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_671_640_W { + U0_PLDA_PCIE_K_PHYPARAM_671_640_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg284.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg284.rs index 605b20d..efaf516 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg284.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg284.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_703_672` reader - u0_plda_pcie_k_phyparam_703_672"] pub type U0_PLDA_PCIE_K_PHYPARAM_703_672_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_703_672` writer - u0_plda_pcie_k_phyparam_703_672"] -pub type U0_PLDA_PCIE_K_PHYPARAM_703_672_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_703_672_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_703_672"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_703_672( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_703_672_W { - U0_PLDA_PCIE_K_PHYPARAM_703_672_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_703_672_W { + U0_PLDA_PCIE_K_PHYPARAM_703_672_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg288.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg288.rs index 08c3c6c..a589513 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg288.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg288.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_735_704` reader - u0_plda_pcie_k_phyparam_735_704"] pub type U0_PLDA_PCIE_K_PHYPARAM_735_704_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_735_704` writer - u0_plda_pcie_k_phyparam_735_704"] -pub type U0_PLDA_PCIE_K_PHYPARAM_735_704_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_735_704_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_735_704"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_735_704( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_735_704_W { - U0_PLDA_PCIE_K_PHYPARAM_735_704_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_735_704_W { + U0_PLDA_PCIE_K_PHYPARAM_735_704_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg292.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg292.rs index 9120a9d..039ebee 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg292.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg292.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_767_736` reader - u0_plda_pcie_k_phyparam_767_736"] pub type U0_PLDA_PCIE_K_PHYPARAM_767_736_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_767_736` writer - u0_plda_pcie_k_phyparam_767_736"] -pub type U0_PLDA_PCIE_K_PHYPARAM_767_736_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_767_736_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_767_736"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_767_736( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_767_736_W { - U0_PLDA_PCIE_K_PHYPARAM_767_736_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_767_736_W { + U0_PLDA_PCIE_K_PHYPARAM_767_736_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg296.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg296.rs index 43a2c2d..cd11754 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg296.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg296.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_799_768` reader - u0_plda_pcie_k_phyparam_799_768"] pub type U0_PLDA_PCIE_K_PHYPARAM_799_768_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_799_768` writer - u0_plda_pcie_k_phyparam_799_768"] -pub type U0_PLDA_PCIE_K_PHYPARAM_799_768_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_799_768_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_799_768"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_799_768( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_799_768_W { - U0_PLDA_PCIE_K_PHYPARAM_799_768_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_799_768_W { + U0_PLDA_PCIE_K_PHYPARAM_799_768_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg300.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg300.rs index 595421a..a028736 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg300.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg300.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_831_800` reader - u0_plda_pcie_k_phyparam_831_800"] pub type U0_PLDA_PCIE_K_PHYPARAM_831_800_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_831_800` writer - u0_plda_pcie_k_phyparam_831_800"] -pub type U0_PLDA_PCIE_K_PHYPARAM_831_800_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_K_PHYPARAM_831_800_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_k_phyparam_831_800"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_831_800( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_831_800_W { - U0_PLDA_PCIE_K_PHYPARAM_831_800_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_831_800_W { + U0_PLDA_PCIE_K_PHYPARAM_831_800_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg304.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg304.rs index 595d2be..0d116b1 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg304.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg304.rs @@ -5,18 +5,17 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_k_phyparam_839_832` reader - u0_plda_pcie_k_phyparam_839_832"] pub type U0_PLDA_PCIE_K_PHYPARAM_839_832_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_k_phyparam_839_832` writer - u0_plda_pcie_k_phyparam_839_832"] -pub type U0_PLDA_PCIE_K_PHYPARAM_839_832_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 8, O>; +pub type U0_PLDA_PCIE_K_PHYPARAM_839_832_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `u0_plda_pcie_k_rp_nep` reader - u0_plda_pcie_k_rp_nep"] pub type U0_PLDA_PCIE_K_RP_NEP_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_k_rp_nep` writer - u0_plda_pcie_k_rp_nep"] -pub type U0_PLDA_PCIE_K_RP_NEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_K_RP_NEP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_l1sub_entack` reader - u0_plda_pcie_l1sub_entack"] pub type U0_PLDA_PCIE_L1SUB_ENTACK_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_l1sub_entreq` reader - u0_plda_pcie_l1sub_entreq"] pub type U0_PLDA_PCIE_L1SUB_ENTREQ_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_l1sub_entreq` writer - u0_plda_pcie_l1sub_entreq"] -pub type U0_PLDA_PCIE_L1SUB_ENTREQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_L1SUB_ENTREQ_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - u0_plda_pcie_k_phyparam_839_832"] #[inline(always)] @@ -45,26 +44,30 @@ impl W { #[must_use] pub fn u0_plda_pcie_k_phyparam_839_832( &mut self, - ) -> U0_PLDA_PCIE_K_PHYPARAM_839_832_W { - U0_PLDA_PCIE_K_PHYPARAM_839_832_W::new(self) + ) -> U0_PLDA_PCIE_K_PHYPARAM_839_832_W { + U0_PLDA_PCIE_K_PHYPARAM_839_832_W::new(self, 0) } #[doc = "Bit 8 - u0_plda_pcie_k_rp_nep"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_k_rp_nep( &mut self, - ) -> U0_PLDA_PCIE_K_RP_NEP_W { - U0_PLDA_PCIE_K_RP_NEP_W::new(self) + ) -> U0_PLDA_PCIE_K_RP_NEP_W { + U0_PLDA_PCIE_K_RP_NEP_W::new(self, 8) } #[doc = "Bit 10 - u0_plda_pcie_l1sub_entreq"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_l1sub_entreq( &mut self, - ) -> U0_PLDA_PCIE_L1SUB_ENTREQ_W { - U0_PLDA_PCIE_L1SUB_ENTREQ_W::new(self) + ) -> U0_PLDA_PCIE_L1SUB_ENTREQ_W { + U0_PLDA_PCIE_L1SUB_ENTREQ_W::new(self, 10) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg308.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg308.rs index 5526eab..2e356df 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg308.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg308.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_local_interrupt_in` reader - u0_plda_pcie_local_interrupt_in"] pub type U0_PLDA_PCIE_LOCAL_INTERRUPT_IN_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_local_interrupt_in` writer - u0_plda_pcie_local_interrupt_in"] -pub type U0_PLDA_PCIE_LOCAL_INTERRUPT_IN_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_LOCAL_INTERRUPT_IN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_local_interrupt_in"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_local_interrupt_in( &mut self, - ) -> U0_PLDA_PCIE_LOCAL_INTERRUPT_IN_W { - U0_PLDA_PCIE_LOCAL_INTERRUPT_IN_W::new(self) + ) -> U0_PLDA_PCIE_LOCAL_INTERRUPT_IN_W { + U0_PLDA_PCIE_LOCAL_INTERRUPT_IN_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg312.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg312.rs index c592a42..8983459 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg312.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg312.rs @@ -5,28 +5,27 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_mperstn` reader - u0_plda_pcie_mperstn"] pub type U0_PLDA_PCIE_MPERSTN_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_mperstn` writer - u0_plda_pcie_mperstn"] -pub type U0_PLDA_PCIE_MPERSTN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_MPERSTN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_pcie_ebuf_mode` reader - u0_plda_pcie_pcie_ebuf_mode"] pub type U0_PLDA_PCIE_PCIE_EBUF_MODE_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_pcie_ebuf_mode` writer - u0_plda_pcie_pcie_ebuf_mode"] -pub type U0_PLDA_PCIE_PCIE_EBUF_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_PCIE_EBUF_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_pcie_phy_test_cfg` reader - u0_plda_pcie_pcie_phy_test_cfg"] pub type U0_PLDA_PCIE_PCIE_PHY_TEST_CFG_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_pcie_phy_test_cfg` writer - u0_plda_pcie_pcie_phy_test_cfg"] -pub type U0_PLDA_PCIE_PCIE_PHY_TEST_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 23, O, u32>; +pub type U0_PLDA_PCIE_PCIE_PHY_TEST_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>; #[doc = "Field `u0_plda_pcie_pcie_rx_eq_training` reader - u0_plda_pcie_pcie_rx_eq_training"] pub type U0_PLDA_PCIE_PCIE_RX_EQ_TRAINING_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_pcie_rx_eq_training` writer - u0_plda_pcie_pcie_rx_eq_training"] -pub type U0_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_pcie_rxterm_en` reader - u0_plda_pcie_pcie_rxterm_en"] pub type U0_PLDA_PCIE_PCIE_RXTERM_EN_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_pcie_rxterm_en` writer - u0_plda_pcie_pcie_rxterm_en"] -pub type U0_PLDA_PCIE_PCIE_RXTERM_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_PCIE_RXTERM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_pcie_tx_onezeros` reader - u0_plda_pcie_pcie_tx_onezeros"] pub type U0_PLDA_PCIE_PCIE_TX_ONEZEROS_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_pcie_tx_onezeros` writer - u0_plda_pcie_pcie_tx_onezeros"] -pub type U0_PLDA_PCIE_PCIE_TX_ONEZEROS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_PCIE_TX_ONEZEROS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - u0_plda_pcie_mperstn"] #[inline(always)] @@ -65,50 +64,54 @@ impl W { #[must_use] pub fn u0_plda_pcie_mperstn( &mut self, - ) -> U0_PLDA_PCIE_MPERSTN_W { - U0_PLDA_PCIE_MPERSTN_W::new(self) + ) -> U0_PLDA_PCIE_MPERSTN_W { + U0_PLDA_PCIE_MPERSTN_W::new(self, 0) } #[doc = "Bit 1 - u0_plda_pcie_pcie_ebuf_mode"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_pcie_ebuf_mode( &mut self, - ) -> U0_PLDA_PCIE_PCIE_EBUF_MODE_W { - U0_PLDA_PCIE_PCIE_EBUF_MODE_W::new(self) + ) -> U0_PLDA_PCIE_PCIE_EBUF_MODE_W { + U0_PLDA_PCIE_PCIE_EBUF_MODE_W::new(self, 1) } #[doc = "Bits 2:24 - u0_plda_pcie_pcie_phy_test_cfg"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_pcie_phy_test_cfg( &mut self, - ) -> U0_PLDA_PCIE_PCIE_PHY_TEST_CFG_W { - U0_PLDA_PCIE_PCIE_PHY_TEST_CFG_W::new(self) + ) -> U0_PLDA_PCIE_PCIE_PHY_TEST_CFG_W { + U0_PLDA_PCIE_PCIE_PHY_TEST_CFG_W::new(self, 2) } #[doc = "Bit 25 - u0_plda_pcie_pcie_rx_eq_training"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_pcie_rx_eq_training( &mut self, - ) -> U0_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W { - U0_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W::new(self) + ) -> U0_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W { + U0_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W::new(self, 25) } #[doc = "Bit 26 - u0_plda_pcie_pcie_rxterm_en"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_pcie_rxterm_en( &mut self, - ) -> U0_PLDA_PCIE_PCIE_RXTERM_EN_W { - U0_PLDA_PCIE_PCIE_RXTERM_EN_W::new(self) + ) -> U0_PLDA_PCIE_PCIE_RXTERM_EN_W { + U0_PLDA_PCIE_PCIE_RXTERM_EN_W::new(self, 26) } #[doc = "Bit 27 - u0_plda_pcie_pcie_tx_onezeros"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_pcie_tx_onezeros( &mut self, - ) -> U0_PLDA_PCIE_PCIE_TX_ONEZEROS_W { - U0_PLDA_PCIE_PCIE_TX_ONEZEROS_W::new(self) + ) -> U0_PLDA_PCIE_PCIE_TX_ONEZEROS_W { + U0_PLDA_PCIE_PCIE_TX_ONEZEROS_W::new(self, 27) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg316.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg316.rs index 3f2e652..2554ee2 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg316.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg316.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_pf0_offset` reader - u0_plda_pcie_pf0_offset"] pub type U0_PLDA_PCIE_PF0_OFFSET_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_pf0_offset` writer - u0_plda_pcie_pf0_offset"] -pub type U0_PLDA_PCIE_PF0_OFFSET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; +pub type U0_PLDA_PCIE_PF0_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; impl R { #[doc = "Bits 0:19 - u0_plda_pcie_pf0_offset"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_pf0_offset( &mut self, - ) -> U0_PLDA_PCIE_PF0_OFFSET_W { - U0_PLDA_PCIE_PF0_OFFSET_W::new(self) + ) -> U0_PLDA_PCIE_PF0_OFFSET_W { + U0_PLDA_PCIE_PF0_OFFSET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg32.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg32.rs index b78cbcf..ca43a2e 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg32.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg32.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_e2_sft7110_nmi_0_rnmi_interrupt_vector` reader - u0_e2_sft7110_nmi_0_rnmi_interrupt_vector"] pub type U0_E2_SFT7110_NMI_0_RNMI_INTERRUPT_VECTOR_R = crate::FieldReader; #[doc = "Field `u0_e2_sft7110_nmi_0_rnmi_interrupt_vector` writer - u0_e2_sft7110_nmi_0_rnmi_interrupt_vector"] -pub type U0_E2_SFT7110_NMI_0_RNMI_INTERRUPT_VECTOR_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_E2_SFT7110_NMI_0_RNMI_INTERRUPT_VECTOR_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_e2_sft7110_nmi_0_rnmi_interrupt_vector"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_e2_sft7110_nmi_0_rnmi_interrupt_vector( &mut self, - ) -> U0_E2_SFT7110_NMI_0_RNMI_INTERRUPT_VECTOR_W { - U0_E2_SFT7110_NMI_0_RNMI_INTERRUPT_VECTOR_W::new(self) + ) -> U0_E2_SFT7110_NMI_0_RNMI_INTERRUPT_VECTOR_W { + U0_E2_SFT7110_NMI_0_RNMI_INTERRUPT_VECTOR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg320.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg320.rs index 1a1370d..918e7c8 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg320.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg320.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_pf1_offset` reader - u0_plda_pcie_pf1_offset"] pub type U0_PLDA_PCIE_PF1_OFFSET_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_pf1_offset` writer - u0_plda_pcie_pf1_offset"] -pub type U0_PLDA_PCIE_PF1_OFFSET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; +pub type U0_PLDA_PCIE_PF1_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; impl R { #[doc = "Bits 0:19 - u0_plda_pcie_pf1_offset"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_pf1_offset( &mut self, - ) -> U0_PLDA_PCIE_PF1_OFFSET_W { - U0_PLDA_PCIE_PF1_OFFSET_W::new(self) + ) -> U0_PLDA_PCIE_PF1_OFFSET_W { + U0_PLDA_PCIE_PF1_OFFSET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg324.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg324.rs index 57b9bf4..83abed6 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg324.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg324.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_pf2_offset` reader - u0_plda_pcie_pf2_offset"] pub type U0_PLDA_PCIE_PF2_OFFSET_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_pf2_offset` writer - u0_plda_pcie_pf2_offset"] -pub type U0_PLDA_PCIE_PF2_OFFSET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; +pub type U0_PLDA_PCIE_PF2_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; impl R { #[doc = "Bits 0:19 - u0_plda_pcie_pf2_offset"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_pf2_offset( &mut self, - ) -> U0_PLDA_PCIE_PF2_OFFSET_W { - U0_PLDA_PCIE_PF2_OFFSET_W::new(self) + ) -> U0_PLDA_PCIE_PF2_OFFSET_W { + U0_PLDA_PCIE_PF2_OFFSET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg328.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg328.rs index 2b56b64..cada965 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg328.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg328.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_pf3_offset` reader - u0_plda_pcie_pf3_offset"] pub type U0_PLDA_PCIE_PF3_OFFSET_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_pf3_offset` writer - u0_plda_pcie_pf3_offset"] -pub type U0_PLDA_PCIE_PF3_OFFSET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; +pub type U0_PLDA_PCIE_PF3_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; #[doc = "Field `u0_plda_pcie_phy_mode` reader - u0_plda_pcie_phy_mode"] pub type U0_PLDA_PCIE_PHY_MODE_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_phy_mode` writer - u0_plda_pcie_phy_mode"] -pub type U0_PLDA_PCIE_PHY_MODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLDA_PCIE_PHY_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_plda_pcie_pl_clkrem_allow` reader - u0_plda_pcie_pl_clkrem_allow"] pub type U0_PLDA_PCIE_PL_CLKREM_ALLOW_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_pl_clkrem_allow` writer - u0_plda_pcie_pl_clkrem_allow"] -pub type U0_PLDA_PCIE_PL_CLKREM_ALLOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_PL_CLKREM_ALLOW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_pl_clkreq_oen` reader - u0_plda_pcie_pl_clkreq_oen"] pub type U0_PLDA_PCIE_PL_CLKREQ_OEN_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_pl_equ_phase` reader - u0_plda_pcie_pl_equ_phase"] @@ -58,26 +58,30 @@ impl W { #[must_use] pub fn u0_plda_pcie_pf3_offset( &mut self, - ) -> U0_PLDA_PCIE_PF3_OFFSET_W { - U0_PLDA_PCIE_PF3_OFFSET_W::new(self) + ) -> U0_PLDA_PCIE_PF3_OFFSET_W { + U0_PLDA_PCIE_PF3_OFFSET_W::new(self, 0) } #[doc = "Bits 20:21 - u0_plda_pcie_phy_mode"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_phy_mode( &mut self, - ) -> U0_PLDA_PCIE_PHY_MODE_W { - U0_PLDA_PCIE_PHY_MODE_W::new(self) + ) -> U0_PLDA_PCIE_PHY_MODE_W { + U0_PLDA_PCIE_PHY_MODE_W::new(self, 20) } #[doc = "Bit 22 - u0_plda_pcie_pl_clkrem_allow"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_pl_clkrem_allow( &mut self, - ) -> U0_PLDA_PCIE_PL_CLKREM_ALLOW_W { - U0_PLDA_PCIE_PL_CLKREM_ALLOW_W::new(self) + ) -> U0_PLDA_PCIE_PL_CLKREM_ALLOW_W { + U0_PLDA_PCIE_PL_CLKREM_ALLOW_W::new(self, 22) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg332.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg332.rs index 91c5625..711bf58 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg332.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg332.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg336.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg336.rs index 36a70a2..e3bfc4e 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg336.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg336.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg340.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg340.rs index a6bff6a..46a79e1 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg340.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg340.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg344.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg344.rs index 8541bb7..be9e5a0 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg344.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg344.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg348.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg348.rs index 7030ca6..7c00d97 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg348.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg348.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg352.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg352.rs index 123e71d..0ec9da5 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg352.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg352.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_pl_wake_in` reader - u0_plda_pcie_pl_wake_in"] pub type U0_PLDA_PCIE_PL_WAKE_IN_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_pl_wake_in` writer - u0_plda_pcie_pl_wake_in"] -pub type U0_PLDA_PCIE_PL_WAKE_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_PL_WAKE_IN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_pl_wake_oen` reader - u0_plda_pcie_pl_wake_oen"] pub type U0_PLDA_PCIE_PL_WAKE_OEN_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_rx_standby_0` reader - u0_plda_pcie_rx_standby_0"] @@ -33,10 +33,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_pl_wake_in( &mut self, - ) -> U0_PLDA_PCIE_PL_WAKE_IN_W { - U0_PLDA_PCIE_PL_WAKE_IN_W::new(self) + ) -> U0_PLDA_PCIE_PL_WAKE_IN_W { + U0_PLDA_PCIE_PL_WAKE_IN_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg356.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg356.rs index 78e62ba..66e8f21 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg356.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg356.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_test_in_31_0` reader - u0_plda_pcie_test_in_31_0"] pub type U0_PLDA_PCIE_TEST_IN_31_0_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_test_in_31_0` writer - u0_plda_pcie_test_in_31_0"] -pub type U0_PLDA_PCIE_TEST_IN_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_TEST_IN_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_test_in_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_test_in_31_0( &mut self, - ) -> U0_PLDA_PCIE_TEST_IN_31_0_W { - U0_PLDA_PCIE_TEST_IN_31_0_W::new(self) + ) -> U0_PLDA_PCIE_TEST_IN_31_0_W { + U0_PLDA_PCIE_TEST_IN_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg36.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg36.rs index 79e2657..b468b57 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg36.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg36.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_e2_sft7110_reset_vector_0` reader - u0_e2_sft7110_reset_vector_0"] pub type U0_E2_SFT7110_RESET_VECTOR_0_R = crate::FieldReader; #[doc = "Field `u0_e2_sft7110_reset_vector_0` writer - u0_e2_sft7110_reset_vector_0"] -pub type U0_E2_SFT7110_RESET_VECTOR_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_E2_SFT7110_RESET_VECTOR_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_e2_sft7110_reset_vector_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_e2_sft7110_reset_vector_0( &mut self, - ) -> U0_E2_SFT7110_RESET_VECTOR_0_W { - U0_E2_SFT7110_RESET_VECTOR_0_W::new(self) + ) -> U0_E2_SFT7110_RESET_VECTOR_0_W { + U0_E2_SFT7110_RESET_VECTOR_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg360.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg360.rs index 6d5c176..489a26d 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg360.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg360.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_test_in_63_32` reader - u0_plda_pcie_test_in_63_32"] pub type U0_PLDA_PCIE_TEST_IN_63_32_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_test_in_63_32` writer - u0_plda_pcie_test_in_63_32"] -pub type U0_PLDA_PCIE_TEST_IN_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_PLDA_PCIE_TEST_IN_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_plda_pcie_test_in_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_plda_pcie_test_in_63_32( &mut self, - ) -> U0_PLDA_PCIE_TEST_IN_63_32_W { - U0_PLDA_PCIE_TEST_IN_63_32_W::new(self) + ) -> U0_PLDA_PCIE_TEST_IN_63_32_W { + U0_PLDA_PCIE_TEST_IN_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg364.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg364.rs index 12486e8..0b3817b 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg364.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg364.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg368.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg368.rs index a4bd073..25c6a1a 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg368.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg368.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg372.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg372.rs index dfa2533..3305bbc 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg372.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg372.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg376.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg376.rs index c78a775..a2c4edc 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg376.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg376.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg380.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg380.rs index 6e739d6..3c51564 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg380.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg380.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg384.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg384.rs index 251e0f6..16f5d9a 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg384.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg384.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg388.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg388.rs index c547c66..14abb5c 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg388.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg388.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg392.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg392.rs index edea5d4..3367405 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg392.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg392.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg396.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg396.rs index 8b92e32..93fc2a9 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg396.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg396.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg4.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg4.rs index d5a8ee4..0f8272f 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg4.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg4.rs @@ -9,57 +9,57 @@ pub type U0_CDN_USB_LTM_HOST_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_ltm_host_req_halt` reader - LTM interface to software"] pub type U0_CDN_USB_LTM_HOST_REQ_HALT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_ltm_host_req_halt` writer - LTM interface to software"] -pub type U0_CDN_USB_LTM_HOST_REQ_HALT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_LTM_HOST_REQ_HALT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_mdctrl_clk_sel` reader - u0_cdn_usb_mdctrl_clk_sel"] pub type U0_CDN_USB_MDCTRL_CLK_SEL_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_mdctrl_clk_sel` writer - u0_cdn_usb_mdctrl_clk_sel"] -pub type U0_CDN_USB_MDCTRL_CLK_SEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_MDCTRL_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_mdctrl_clk_status` reader - u0_cdn_usb_mdctrl_clk_status"] pub type U0_CDN_USB_MDCTRL_CLK_STATUS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_mode_strap` reader - Can onlly be changed when pwrup_rst_n is low"] pub type U0_CDN_USB_MODE_STRAP_R = crate::FieldReader; #[doc = "Field `u0_cdn_usb_mode_strap` writer - Can onlly be changed when pwrup_rst_n is low"] -pub type U0_CDN_USB_MODE_STRAP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U0_CDN_USB_MODE_STRAP_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_cdn_usb_otg_suspendm` reader - u0_cdn_usb_otg_suspendm"] pub type U0_CDN_USB_OTG_SUSPENDM_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_otg_suspendm` writer - u0_cdn_usb_otg_suspendm"] -pub type U0_CDN_USB_OTG_SUSPENDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_OTG_SUSPENDM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_otg_suspendm_byps` reader - u0_cdn_usb_otg_suspendm_byps"] pub type U0_CDN_USB_OTG_SUSPENDM_BYPS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_otg_suspendm_byps` writer - u0_cdn_usb_otg_suspendm_byps"] -pub type U0_CDN_USB_OTG_SUSPENDM_BYPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_OTG_SUSPENDM_BYPS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_phy_bvalid` reader - u0_cdn_usb_phy_bvalid"] pub type U0_CDN_USB_PHY_BVALID_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_pll_en` reader - u0_cdn_usb_pll_en"] pub type U0_CDN_USB_PLL_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_pll_en` writer - u0_cdn_usb_pll_en"] -pub type U0_CDN_USB_PLL_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_PLL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_refclk_mode` reader - u0_cdn_usb_refclk_mode"] pub type U0_CDN_USB_REFCLK_MODE_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_refclk_mode` writer - u0_cdn_usb_refclk_mode"] -pub type U0_CDN_USB_REFCLK_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_REFCLK_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_rid_a_comp_sts` reader - u0_cdn_usb_rid_a_comp_sts"] pub type U0_CDN_USB_RID_A_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_rid_a_comp_sts` writer - u0_cdn_usb_rid_a_comp_sts"] -pub type U0_CDN_USB_RID_A_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_RID_A_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_rid_b_comp_sts` reader - u0_cdn_usb_rid_b_comp_sts"] pub type U0_CDN_USB_RID_B_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_rid_b_comp_sts` writer - u0_cdn_usb_rid_b_comp_sts"] -pub type U0_CDN_USB_RID_B_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_RID_B_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_rid_c_comp_sts` reader - u0_cdn_usb_rid_c_comp_sts"] pub type U0_CDN_USB_RID_C_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_rid_c_comp_sts` writer - u0_cdn_usb_rid_c_comp_sts"] -pub type U0_CDN_USB_RID_C_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_RID_C_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_rid_float_comp_en` reader - u0_cdn_usb_rid_float_comp_en"] pub type U0_CDN_USB_RID_FLOAT_COMP_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_rid_float_comp_sts` reader - u0_cdn_usb_rid_float_comp_sts"] pub type U0_CDN_USB_RID_FLOAT_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_rid_float_comp_sts` writer - u0_cdn_usb_rid_float_comp_sts"] -pub type U0_CDN_USB_RID_FLOAT_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_RID_FLOAT_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_rid_gnd_comp_sts` reader - u0_cdn_usb_rid_gnd_comp_sts"] pub type U0_CDN_USB_RID_GND_COMP_STS_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_rid_gnd_comp_sts` writer - u0_cdn_usb_rid_gnd_comp_sts"] -pub type U0_CDN_USB_RID_GND_COMP_STS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_RID_GND_COMP_STS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_rid_nonfloat_comp_en` reader - u0_cdn_usb_rid_nonfloat_comp_en"] pub type U0_CDN_USB_RID_NONFLOAT_COMP_EN_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_rx_dm` reader - u0_cdn_usb_rx_dm"] @@ -167,96 +167,100 @@ impl W { #[must_use] pub fn u0_cdn_usb_ltm_host_req_halt( &mut self, - ) -> U0_CDN_USB_LTM_HOST_REQ_HALT_W { - U0_CDN_USB_LTM_HOST_REQ_HALT_W::new(self) + ) -> U0_CDN_USB_LTM_HOST_REQ_HALT_W { + U0_CDN_USB_LTM_HOST_REQ_HALT_W::new(self, 13) } #[doc = "Bit 14 - u0_cdn_usb_mdctrl_clk_sel"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_mdctrl_clk_sel( &mut self, - ) -> U0_CDN_USB_MDCTRL_CLK_SEL_W { - U0_CDN_USB_MDCTRL_CLK_SEL_W::new(self) + ) -> U0_CDN_USB_MDCTRL_CLK_SEL_W { + U0_CDN_USB_MDCTRL_CLK_SEL_W::new(self, 14) } #[doc = "Bits 16:18 - Can onlly be changed when pwrup_rst_n is low"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_mode_strap( &mut self, - ) -> U0_CDN_USB_MODE_STRAP_W { - U0_CDN_USB_MODE_STRAP_W::new(self) + ) -> U0_CDN_USB_MODE_STRAP_W { + U0_CDN_USB_MODE_STRAP_W::new(self, 16) } #[doc = "Bit 19 - u0_cdn_usb_otg_suspendm"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_otg_suspendm( &mut self, - ) -> U0_CDN_USB_OTG_SUSPENDM_W { - U0_CDN_USB_OTG_SUSPENDM_W::new(self) + ) -> U0_CDN_USB_OTG_SUSPENDM_W { + U0_CDN_USB_OTG_SUSPENDM_W::new(self, 19) } #[doc = "Bit 20 - u0_cdn_usb_otg_suspendm_byps"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_otg_suspendm_byps( &mut self, - ) -> U0_CDN_USB_OTG_SUSPENDM_BYPS_W { - U0_CDN_USB_OTG_SUSPENDM_BYPS_W::new(self) + ) -> U0_CDN_USB_OTG_SUSPENDM_BYPS_W { + U0_CDN_USB_OTG_SUSPENDM_BYPS_W::new(self, 20) } #[doc = "Bit 22 - u0_cdn_usb_pll_en"] #[inline(always)] #[must_use] - pub fn u0_cdn_usb_pll_en(&mut self) -> U0_CDN_USB_PLL_EN_W { - U0_CDN_USB_PLL_EN_W::new(self) + pub fn u0_cdn_usb_pll_en(&mut self) -> U0_CDN_USB_PLL_EN_W { + U0_CDN_USB_PLL_EN_W::new(self, 22) } #[doc = "Bit 23 - u0_cdn_usb_refclk_mode"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_refclk_mode( &mut self, - ) -> U0_CDN_USB_REFCLK_MODE_W { - U0_CDN_USB_REFCLK_MODE_W::new(self) + ) -> U0_CDN_USB_REFCLK_MODE_W { + U0_CDN_USB_REFCLK_MODE_W::new(self, 23) } #[doc = "Bit 24 - u0_cdn_usb_rid_a_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_rid_a_comp_sts( &mut self, - ) -> U0_CDN_USB_RID_A_COMP_STS_W { - U0_CDN_USB_RID_A_COMP_STS_W::new(self) + ) -> U0_CDN_USB_RID_A_COMP_STS_W { + U0_CDN_USB_RID_A_COMP_STS_W::new(self, 24) } #[doc = "Bit 25 - u0_cdn_usb_rid_b_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_rid_b_comp_sts( &mut self, - ) -> U0_CDN_USB_RID_B_COMP_STS_W { - U0_CDN_USB_RID_B_COMP_STS_W::new(self) + ) -> U0_CDN_USB_RID_B_COMP_STS_W { + U0_CDN_USB_RID_B_COMP_STS_W::new(self, 25) } #[doc = "Bit 26 - u0_cdn_usb_rid_c_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_rid_c_comp_sts( &mut self, - ) -> U0_CDN_USB_RID_C_COMP_STS_W { - U0_CDN_USB_RID_C_COMP_STS_W::new(self) + ) -> U0_CDN_USB_RID_C_COMP_STS_W { + U0_CDN_USB_RID_C_COMP_STS_W::new(self, 26) } #[doc = "Bit 28 - u0_cdn_usb_rid_float_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_rid_float_comp_sts( &mut self, - ) -> U0_CDN_USB_RID_FLOAT_COMP_STS_W { - U0_CDN_USB_RID_FLOAT_COMP_STS_W::new(self) + ) -> U0_CDN_USB_RID_FLOAT_COMP_STS_W { + U0_CDN_USB_RID_FLOAT_COMP_STS_W::new(self, 28) } #[doc = "Bit 29 - u0_cdn_usb_rid_gnd_comp_sts"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_rid_gnd_comp_sts( &mut self, - ) -> U0_CDN_USB_RID_GND_COMP_STS_W { - U0_CDN_USB_RID_GND_COMP_STS_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_CDN_USB_RID_GND_COMP_STS_W { + U0_CDN_USB_RID_GND_COMP_STS_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg40.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg40.rs index d19ee7a..5ed0182 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg40.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg40.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg400.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg400.rs index fea4c03..8ac81dc 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg400.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg400.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg404.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg404.rs index be1b755..fc7e19d 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg404.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg404.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg408.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg408.rs index 996784a..89b57d6 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg408.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg408.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg412.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg412.rs index 4979d21..e9d14f9 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg412.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg412.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg416.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg416.rs index eeeb1ce..6a877df 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg416.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg416.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg420.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg420.rs index eb2a132..e778111 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg420.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg420.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg424.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg424.rs index cfe423e..c039be5 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg424.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg424.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg428.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg428.rs index 73a74d1..5e04dc5 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg428.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg428.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg432.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg432.rs index 6116c00..5b74195 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg432.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg432.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg436.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg436.rs index f881fd9..8aa222b 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg436.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg436.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg44.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg44.rs index d10499c..673cb30 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg44.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg44.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_hifi4_altresetvec` reader - Reset Vector Address"] pub type U0_HIFI4_ALTRESETVEC_R = crate::FieldReader; #[doc = "Field `u0_hifi4_altresetvec` writer - Reset Vector Address"] -pub type U0_HIFI4_ALTRESETVEC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_HIFI4_ALTRESETVEC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - Reset Vector Address"] #[inline(always)] @@ -17,12 +17,14 @@ impl W { #[doc = "Bits 0:31 - Reset Vector Address"] #[inline(always)] #[must_use] - pub fn u0_hifi4_altresetvec( - &mut self, - ) -> U0_HIFI4_ALTRESETVEC_W { - U0_HIFI4_ALTRESETVEC_W::new(self) + pub fn u0_hifi4_altresetvec(&mut self) -> U0_HIFI4_ALTRESETVEC_W { + U0_HIFI4_ALTRESETVEC_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg440.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg440.rs index 006978d..978a42e 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg440.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg440.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg444.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg444.rs index 9f77601..b46ba5f 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg444.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg444.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg448.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg448.rs index 64d4cb1..11be6dc 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg448.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg448.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg452.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg452.rs index 06874f4..f06dbfe 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg452.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg452.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg456.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg456.rs index 7ddb0e9..c1fae0b 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg456.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg456.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg460.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg460.rs index c85a88c..2c41c2c 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg460.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg460.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg464.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg464.rs index 95ccb26..16b0ae3 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg464.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg464.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg468.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg468.rs index 6becc4e..9fcae7e 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg468.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg468.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg472.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg472.rs index 6e50753..9b6b493 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg472.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg472.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg476.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg476.rs index c680d12..99803e3 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg476.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg476.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg48.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg48.rs index 5b28a96..4b91c36 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg48.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg48.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_hifi4_breakin` reader - Debug signal"] pub type U0_HIFI4_BREAKIN_R = crate::BitReader; #[doc = "Field `u0_hifi4_breakin` writer - Debug signal"] -pub type U0_HIFI4_BREAKIN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_BREAKIN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_breakinack` reader - Debug signal"] pub type U0_HIFI4_BREAKINACK_R = crate::BitReader; #[doc = "Field `u0_hifi4_breakout` reader - Debug signal"] @@ -13,7 +13,7 @@ pub type U0_HIFI4_BREAKOUT_R = crate::BitReader; #[doc = "Field `u0_hifi4_breakoutack` reader - Debug signal"] pub type U0_HIFI4_BREAKOUTACK_R = crate::BitReader; #[doc = "Field `u0_hifi4_breakoutack` writer - Debug signal"] -pub type U0_HIFI4_BREAKOUTACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_BREAKOUTACK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_debugmode` reader - Debug signal"] pub type U0_HIFI4_DEBUGMODE_R = crate::BitReader; #[doc = "Field `u0_hifi4_doubleexceptionerror` reader - Fault Handling Signals"] @@ -25,7 +25,7 @@ pub type U0_HIFI4_IRAM1LOADSTORE_R = crate::BitReader; #[doc = "Field `u0_hifi4_ocdhaltonreset` reader - Debug signal"] pub type U0_HIFI4_OCDHALTONRESET_R = crate::BitReader; #[doc = "Field `u0_hifi4_ocdhaltonreset` writer - Debug signal"] -pub type U0_HIFI4_OCDHALTONRESET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_OCDHALTONRESET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_pfatalerror` reader - Fault Handling Signals"] pub type U0_HIFI4_PFATALERROR_R = crate::BitReader; impl R { @@ -84,26 +84,28 @@ impl W { #[doc = "Bit 0 - Debug signal"] #[inline(always)] #[must_use] - pub fn u0_hifi4_breakin(&mut self) -> U0_HIFI4_BREAKIN_W { - U0_HIFI4_BREAKIN_W::new(self) + pub fn u0_hifi4_breakin(&mut self) -> U0_HIFI4_BREAKIN_W { + U0_HIFI4_BREAKIN_W::new(self, 0) } #[doc = "Bit 3 - Debug signal"] #[inline(always)] #[must_use] - pub fn u0_hifi4_breakoutack( - &mut self, - ) -> U0_HIFI4_BREAKOUTACK_W { - U0_HIFI4_BREAKOUTACK_W::new(self) + pub fn u0_hifi4_breakoutack(&mut self) -> U0_HIFI4_BREAKOUTACK_W { + U0_HIFI4_BREAKOUTACK_W::new(self, 3) } #[doc = "Bit 8 - Debug signal"] #[inline(always)] #[must_use] pub fn u0_hifi4_ocdhaltonreset( &mut self, - ) -> U0_HIFI4_OCDHALTONRESET_W { - U0_HIFI4_OCDHALTONRESET_W::new(self) + ) -> U0_HIFI4_OCDHALTONRESET_W { + U0_HIFI4_OCDHALTONRESET_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg480.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg480.rs index ce9e85e..974e094 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg480.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg480.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg484.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg484.rs index 80780a3..16d685c 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg484.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg484.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg488.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg488.rs index 39f28b0..fde5249 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg488.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg488.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg492.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg492.rs index 886a46c..aa6f149 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg492.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg492.rs @@ -5,12 +5,11 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_test_sel` reader - u0_plda_pcie_test_sel"] pub type U0_PLDA_PCIE_TEST_SEL_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_test_sel` writer - u0_plda_pcie_test_sel"] -pub type U0_PLDA_PCIE_TEST_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type U0_PLDA_PCIE_TEST_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `u0_plda_pcie_tl_clock_freq` reader - u0_plda_pcie_tl_clock_freq"] pub type U0_PLDA_PCIE_TL_CLOCK_FREQ_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_tl_clock_freq` writer - u0_plda_pcie_tl_clock_freq"] -pub type U0_PLDA_PCIE_TL_CLOCK_FREQ_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 22, O, u32>; +pub type U0_PLDA_PCIE_TL_CLOCK_FREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; impl R { #[doc = "Bits 0:3 - u0_plda_pcie_test_sel"] #[inline(always)] @@ -29,18 +28,22 @@ impl W { #[must_use] pub fn u0_plda_pcie_test_sel( &mut self, - ) -> U0_PLDA_PCIE_TEST_SEL_W { - U0_PLDA_PCIE_TEST_SEL_W::new(self) + ) -> U0_PLDA_PCIE_TEST_SEL_W { + U0_PLDA_PCIE_TEST_SEL_W::new(self, 0) } #[doc = "Bits 4:25 - u0_plda_pcie_tl_clock_freq"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_tl_clock_freq( &mut self, - ) -> U0_PLDA_PCIE_TL_CLOCK_FREQ_W { - U0_PLDA_PCIE_TL_CLOCK_FREQ_W::new(self) + ) -> U0_PLDA_PCIE_TL_CLOCK_FREQ_W { + U0_PLDA_PCIE_TL_CLOCK_FREQ_W::new(self, 4) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg500.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg500.rs index 85d492a..d55fe25 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg500.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg500.rs @@ -5,63 +5,63 @@ pub type W = crate::W; #[doc = "Field `u0_plda_pcie_tx_pattern` reader - u0_plda_pcie_tx_pattern"] pub type U0_PLDA_PCIE_TX_PATTERN_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_tx_pattern` writer - u0_plda_pcie_tx_pattern"] -pub type U0_PLDA_PCIE_TX_PATTERN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLDA_PCIE_TX_PATTERN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_plda_pcie_usb3_bus_width` reader - u0_plda_pcie_usb3_bus_width"] pub type U0_PLDA_PCIE_USB3_BUS_WIDTH_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_usb3_bus_width` writer - u0_plda_pcie_usb3_bus_width"] -pub type U0_PLDA_PCIE_USB3_BUS_WIDTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLDA_PCIE_USB3_BUS_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_plda_pcie_usb3_phy_enable` reader - u0_plda_pcie_usb3_phy_enable"] pub type U0_PLDA_PCIE_USB3_PHY_ENABLE_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_usb3_phy_enable` writer - u0_plda_pcie_usb3_phy_enable"] -pub type U0_PLDA_PCIE_USB3_PHY_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_USB3_PHY_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_usb3_rate` reader - u0_plda_pcie_usb3_rate"] pub type U0_PLDA_PCIE_USB3_RATE_R = crate::FieldReader; #[doc = "Field `u0_plda_pcie_usb3_rate` writer - u0_plda_pcie_usb3_rate"] -pub type U0_PLDA_PCIE_USB3_RATE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLDA_PCIE_USB3_RATE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_plda_pcie_usb3_rx_standby` reader - u0_plda_pcie_usb3_rx_standby"] pub type U0_PLDA_PCIE_USB3_RX_STANDBY_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_usb3_rx_standby` writer - u0_plda_pcie_usb3_rx_standby"] -pub type U0_PLDA_PCIE_USB3_RX_STANDBY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_USB3_RX_STANDBY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_xwdecerr` reader - u0_plda_pcie_xwdecerr"] pub type U0_PLDA_PCIE_XWDECERR_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_xwerrclr` reader - u0_plda_pcie_xwerrclr"] pub type U0_PLDA_PCIE_XWERRCLR_R = crate::BitReader; #[doc = "Field `u0_plda_pcie_xwerrclr` writer - u0_plda_pcie_xwerrclr"] -pub type U0_PLDA_PCIE_XWERRCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLDA_PCIE_XWERRCLR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_xwslverr` reader - u0_plda_pcie_xwslverr"] pub type U0_PLDA_PCIE_XWSLVERR_R = crate::BitReader; #[doc = "Field `u0_sec_top_sramcfg_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] pub type U0_SEC_TOP_SRAMCFG_SLP_R = crate::BitReader; #[doc = "Field `u0_sec_top_sramcfg_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] -pub type U0_SEC_TOP_SRAMCFG_SLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_SEC_TOP_SRAMCFG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sec_top_sramcfg_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] pub type U0_SEC_TOP_SRAMCFG_SRAM_CONFIG_SD_R = crate::BitReader; #[doc = "Field `u0_sec_top_sramcfg_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] -pub type U0_SEC_TOP_SRAMCFG_SRAM_CONFIG_SD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_SEC_TOP_SRAMCFG_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sec_top_sramcfg_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_SEC_TOP_SRAMCFG_RTSEL_R = crate::FieldReader; #[doc = "Field `u0_sec_top_sramcfg_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_SEC_TOP_SRAMCFG_RTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_SEC_TOP_SRAMCFG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_sec_top_sramcfg_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_SEC_TOP_SRAMCFG_PTSEL_R = crate::FieldReader; #[doc = "Field `u0_sec_top_sramcfg_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_SEC_TOP_SRAMCFG_PTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_SEC_TOP_SRAMCFG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_sec_top_sramcfg_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] pub type U0_SEC_TOP_SRAMCFG_TRB_R = crate::FieldReader; #[doc = "Field `u0_sec_top_sramcfg_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] -pub type U0_SEC_TOP_SRAMCFG_TRB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_SEC_TOP_SRAMCFG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_sec_top_sramcfg_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_SEC_TOP_SRAMCFG_WTSEL_R = crate::FieldReader; #[doc = "Field `u0_sec_top_sramcfg_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_SEC_TOP_SRAMCFG_WTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_SEC_TOP_SRAMCFG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_sec_top_sramcfg_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] pub type U0_SEC_TOP_SRAMCFG_VS_R = crate::BitReader; #[doc = "Field `u0_sec_top_sramcfg_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] -pub type U0_SEC_TOP_SRAMCFG_VS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_SEC_TOP_SRAMCFG_VS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sec_top_sramcfg_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] pub type U0_SEC_TOP_SRAMCFG_VG_R = crate::BitReader; #[doc = "Field `u0_sec_top_sramcfg_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] -pub type U0_SEC_TOP_SRAMCFG_VG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_SEC_TOP_SRAMCFG_VG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_plda_pcie_align_detect` reader - u0_plda_pcie_align_detect"] pub type U0_PLDA_PCIE_ALIGN_DETECT_R = crate::BitReader; impl R { @@ -157,114 +157,118 @@ impl W { #[must_use] pub fn u0_plda_pcie_tx_pattern( &mut self, - ) -> U0_PLDA_PCIE_TX_PATTERN_W { - U0_PLDA_PCIE_TX_PATTERN_W::new(self) + ) -> U0_PLDA_PCIE_TX_PATTERN_W { + U0_PLDA_PCIE_TX_PATTERN_W::new(self, 0) } #[doc = "Bits 2:3 - u0_plda_pcie_usb3_bus_width"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_usb3_bus_width( &mut self, - ) -> U0_PLDA_PCIE_USB3_BUS_WIDTH_W { - U0_PLDA_PCIE_USB3_BUS_WIDTH_W::new(self) + ) -> U0_PLDA_PCIE_USB3_BUS_WIDTH_W { + U0_PLDA_PCIE_USB3_BUS_WIDTH_W::new(self, 2) } #[doc = "Bit 4 - u0_plda_pcie_usb3_phy_enable"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_usb3_phy_enable( &mut self, - ) -> U0_PLDA_PCIE_USB3_PHY_ENABLE_W { - U0_PLDA_PCIE_USB3_PHY_ENABLE_W::new(self) + ) -> U0_PLDA_PCIE_USB3_PHY_ENABLE_W { + U0_PLDA_PCIE_USB3_PHY_ENABLE_W::new(self, 4) } #[doc = "Bits 5:6 - u0_plda_pcie_usb3_rate"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_usb3_rate( &mut self, - ) -> U0_PLDA_PCIE_USB3_RATE_W { - U0_PLDA_PCIE_USB3_RATE_W::new(self) + ) -> U0_PLDA_PCIE_USB3_RATE_W { + U0_PLDA_PCIE_USB3_RATE_W::new(self, 5) } #[doc = "Bit 7 - u0_plda_pcie_usb3_rx_standby"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_usb3_rx_standby( &mut self, - ) -> U0_PLDA_PCIE_USB3_RX_STANDBY_W { - U0_PLDA_PCIE_USB3_RX_STANDBY_W::new(self) + ) -> U0_PLDA_PCIE_USB3_RX_STANDBY_W { + U0_PLDA_PCIE_USB3_RX_STANDBY_W::new(self, 7) } #[doc = "Bit 9 - u0_plda_pcie_xwerrclr"] #[inline(always)] #[must_use] pub fn u0_plda_pcie_xwerrclr( &mut self, - ) -> U0_PLDA_PCIE_XWERRCLR_W { - U0_PLDA_PCIE_XWERRCLR_W::new(self) + ) -> U0_PLDA_PCIE_XWERRCLR_W { + U0_PLDA_PCIE_XWERRCLR_W::new(self, 9) } #[doc = "Bit 11 - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_sec_top_sramcfg_slp( &mut self, - ) -> U0_SEC_TOP_SRAMCFG_SLP_W { - U0_SEC_TOP_SRAMCFG_SLP_W::new(self) + ) -> U0_SEC_TOP_SRAMCFG_SLP_W { + U0_SEC_TOP_SRAMCFG_SLP_W::new(self, 11) } #[doc = "Bit 12 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_sec_top_sramcfg_sram_config_sd( &mut self, - ) -> U0_SEC_TOP_SRAMCFG_SRAM_CONFIG_SD_W { - U0_SEC_TOP_SRAMCFG_SRAM_CONFIG_SD_W::new(self) + ) -> U0_SEC_TOP_SRAMCFG_SRAM_CONFIG_SD_W { + U0_SEC_TOP_SRAMCFG_SRAM_CONFIG_SD_W::new(self, 12) } #[doc = "Bits 13:14 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_sec_top_sramcfg_rtsel( &mut self, - ) -> U0_SEC_TOP_SRAMCFG_RTSEL_W { - U0_SEC_TOP_SRAMCFG_RTSEL_W::new(self) + ) -> U0_SEC_TOP_SRAMCFG_RTSEL_W { + U0_SEC_TOP_SRAMCFG_RTSEL_W::new(self, 13) } #[doc = "Bits 15:16 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_sec_top_sramcfg_ptsel( &mut self, - ) -> U0_SEC_TOP_SRAMCFG_PTSEL_W { - U0_SEC_TOP_SRAMCFG_PTSEL_W::new(self) + ) -> U0_SEC_TOP_SRAMCFG_PTSEL_W { + U0_SEC_TOP_SRAMCFG_PTSEL_W::new(self, 15) } #[doc = "Bits 17:18 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_sec_top_sramcfg_trb( &mut self, - ) -> U0_SEC_TOP_SRAMCFG_TRB_W { - U0_SEC_TOP_SRAMCFG_TRB_W::new(self) + ) -> U0_SEC_TOP_SRAMCFG_TRB_W { + U0_SEC_TOP_SRAMCFG_TRB_W::new(self, 17) } #[doc = "Bits 19:20 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_sec_top_sramcfg_wtsel( &mut self, - ) -> U0_SEC_TOP_SRAMCFG_WTSEL_W { - U0_SEC_TOP_SRAMCFG_WTSEL_W::new(self) + ) -> U0_SEC_TOP_SRAMCFG_WTSEL_W { + U0_SEC_TOP_SRAMCFG_WTSEL_W::new(self, 19) } #[doc = "Bit 21 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_sec_top_sramcfg_vs( &mut self, - ) -> U0_SEC_TOP_SRAMCFG_VS_W { - U0_SEC_TOP_SRAMCFG_VS_W::new(self) + ) -> U0_SEC_TOP_SRAMCFG_VS_W { + U0_SEC_TOP_SRAMCFG_VS_W::new(self, 21) } #[doc = "Bit 22 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_sec_top_sramcfg_vg( &mut self, - ) -> U0_SEC_TOP_SRAMCFG_VG_W { - U0_SEC_TOP_SRAMCFG_VG_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_SEC_TOP_SRAMCFG_VG_W { + U0_SEC_TOP_SRAMCFG_VG_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg504.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg504.rs index f324066..260e8e7 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg504.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg504.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg508.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg508.rs index 630ebea..4790af3 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg508.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg508.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg512.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg512.rs index 7819245..ee3d556 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg512.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg512.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg516.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg516.rs index d520e8a..61b702a 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg516.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg516.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg52.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg52.rs index 91c2777..988049b 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg52.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg52.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg520.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg520.rs index 78cfc8b..94c6643 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg520.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg520.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg524.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg524.rs index 0e69a54..863f4b0 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg524.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg524.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg528.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg528.rs index 86aab47..0e5f4c8 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg528.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg528.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg532.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg532.rs index 0c7f5a9..37cb7e2 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg532.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg532.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg536.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg536.rs index 5a86fce..ac0616d 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg536.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg536.rs @@ -28,7 +28,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg540.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg540.rs index f98ec21..f3c6c11 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg540.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg540.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg544.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg544.rs index 01dc464..6b3aa74 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg544.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg544.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg548.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg548.rs index fa7a210..641c91a 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg548.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg548.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg552.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg552.rs index 995c7af..b2df9f1 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg552.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg552.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg556.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg556.rs index 445e741..7249981 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg556.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg556.rs @@ -7,7 +7,7 @@ pub type U1_PLDA_PCIE_AXI4_MST0_AWUSER_42_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_mst0_rderr` reader - u1_plda_pcie_axi4_mst0_rderr"] pub type U1_PLDA_PCIE_AXI4_MST0_RDERR_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_mst0_rderr` writer - u1_plda_pcie_axi4_mst0_rderr"] -pub type U1_PLDA_PCIE_AXI4_MST0_RDERR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type U1_PLDA_PCIE_AXI4_MST0_RDERR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:10 - u1_plda_pcie_axi4_mst0_awuser_42_32"] #[inline(always)] @@ -26,10 +26,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_mst0_rderr( &mut self, - ) -> U1_PLDA_PCIE_AXI4_MST0_RDERR_W { - U1_PLDA_PCIE_AXI4_MST0_RDERR_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_MST0_RDERR_W { + U1_PLDA_PCIE_AXI4_MST0_RDERR_W::new(self, 11) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg56.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg56.rs index 85f9fdb..16bb481 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg56.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg56.rs @@ -7,13 +7,13 @@ pub type U0_HIFI4_PFAULTINFOVALID_R = crate::BitReader; #[doc = "Field `u0_hifi4_prid` reader - Module ID"] pub type U0_HIFI4_PRID_R = crate::FieldReader; #[doc = "Field `u0_hifi4_prid` writer - Module ID"] -pub type U0_HIFI4_PRID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type U0_HIFI4_PRID_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; #[doc = "Field `u0_hifi4_pwaitmode` reader - Wait Mode"] pub type U0_HIFI4_PWAITMODE_R = crate::BitReader; #[doc = "Field `u0_hifi4_runstall` reader - Run Stall"] pub type U0_HIFI4_RUNSTALL_R = crate::BitReader; #[doc = "Field `u0_hifi4_runstall` writer - Run Stall"] -pub type U0_HIFI4_RUNSTALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_RUNSTALL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Fault Handling Signals"] #[inline(always)] @@ -40,16 +40,20 @@ impl W { #[doc = "Bits 1:16 - Module ID"] #[inline(always)] #[must_use] - pub fn u0_hifi4_prid(&mut self) -> U0_HIFI4_PRID_W { - U0_HIFI4_PRID_W::new(self) + pub fn u0_hifi4_prid(&mut self) -> U0_HIFI4_PRID_W { + U0_HIFI4_PRID_W::new(self, 1) } #[doc = "Bit 18 - Run Stall"] #[inline(always)] #[must_use] - pub fn u0_hifi4_runstall(&mut self) -> U0_HIFI4_RUNSTALL_W { - U0_HIFI4_RUNSTALL_W::new(self) + pub fn u0_hifi4_runstall(&mut self) -> U0_HIFI4_RUNSTALL_W { + U0_HIFI4_RUNSTALL_W::new(self, 18) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg560.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg560.rs index eefe4c9..a4f627a 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg560.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg560.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_mst0_ruser` reader - u1_plda_pcie_axi4_mst0_ruser"] pub type U1_PLDA_PCIE_AXI4_MST0_RUSER_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_mst0_ruser` writer - u1_plda_pcie_axi4_mst0_ruser"] -pub type U1_PLDA_PCIE_AXI4_MST0_RUSER_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_MST0_RUSER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_mst0_ruser"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_mst0_ruser( &mut self, - ) -> U1_PLDA_PCIE_AXI4_MST0_RUSER_W { - U1_PLDA_PCIE_AXI4_MST0_RUSER_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_MST0_RUSER_W { + U1_PLDA_PCIE_AXI4_MST0_RUSER_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg564.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg564.rs index 236f4f1..dadb069 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg564.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg564.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg568.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg568.rs index 456eed2..260a5df 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg568.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg568.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_31_0` reader - u1_plda_pcie_axi4_slv0_aratomop_31_0"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_31_0` writer - u1_plda_pcie_axi4_slv0_aratomop_31_0"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aratomop_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aratomop_31_0( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W { - U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W { + U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg572.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg572.rs index 2f76870..5f71a70 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg572.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg572.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_63_32` reader - u1_plda_pcie_axi4_slv0_aratomop_63_32"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_63_32` writer - u1_plda_pcie_axi4_slv0_aratomop_63_32"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aratomop_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aratomop_63_32( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W { - U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W { + U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg576.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg576.rs index c9a3ae3..22dd9d8 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg576.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg576.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_95_64` reader - u1_plda_pcie_axi4_slv0_aratomop_95_64"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_95_64` writer - u1_plda_pcie_axi4_slv0_aratomop_95_64"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aratomop_95_64"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aratomop_95_64( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W { - U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W { + U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_95_64_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg580.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg580.rs index 2fa0778..4dcce3c 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg580.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg580.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_127_96` reader - u1_plda_pcie_axi4_slv0_aratomop_127_96"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_127_96` writer - u1_plda_pcie_axi4_slv0_aratomop_127_96"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aratomop_127_96"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aratomop_127_96( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W { - U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W { + U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_127_96_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg584.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg584.rs index c67e8b4..bc16b4a 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg584.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg584.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_159_128` reader - u1_plda_pcie_axi4_slv0_aratomop_159_128"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_159_128` writer - u1_plda_pcie_axi4_slv0_aratomop_159_128"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aratomop_159_128"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aratomop_159_128( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W { - U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W { + U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_159_128_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg588.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg588.rs index 66ecf25..40a8580 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg588.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg588.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_191_160` reader - u1_plda_pcie_axi4_slv0_aratomop_191_160"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_191_160` writer - u1_plda_pcie_axi4_slv0_aratomop_191_160"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aratomop_191_160"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aratomop_191_160( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W { - U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W { + U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_191_160_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg592.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg592.rs index 64eb476..d17e158 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg592.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg592.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_223_192` reader - u1_plda_pcie_axi4_slv0_aratomop_223_192"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_223_192` writer - u1_plda_pcie_axi4_slv0_aratomop_223_192"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aratomop_223_192"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aratomop_223_192( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W { - U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W { + U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_223_192_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg596.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg596.rs index e7d14c6..c16ab9f 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg596.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg596.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_255_224` reader - u1_plda_pcie_axi4_slv0_aratomop_255_224"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aratomop_255_224` writer - u1_plda_pcie_axi4_slv0_aratomop_255_224"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aratomop_255_224"] #[inline(always)] @@ -22,10 +21,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aratomop_255_224( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W { - U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W { + U1_PLDA_PCIE_AXI4_SLV0_ARATOMOP_255_224_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg60.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg60.rs index 15a792a..5908a6e 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg60.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg60.rs @@ -5,13 +5,11 @@ pub type W = crate::W; #[doc = "Field `u0_hifi4_scfg_dsp_mst_offset_master` reader - Indicates that master port remap address"] pub type U0_HIFI4_SCFG_DSP_MST_OFFSET_MASTER_R = crate::FieldReader; #[doc = "Field `u0_hifi4_scfg_dsp_mst_offset_master` writer - Indicates that master port remap address"] -pub type U0_HIFI4_SCFG_DSP_MST_OFFSET_MASTER_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 12, O, u16>; +pub type U0_HIFI4_SCFG_DSP_MST_OFFSET_MASTER_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; #[doc = "Field `u0_hifi4_scfg_dsp_mst_offset_dma` reader - Indicates the DMA port remap address"] pub type U0_HIFI4_SCFG_DSP_MST_OFFSET_DMA_R = crate::FieldReader; #[doc = "Field `u0_hifi4_scfg_dsp_mst_offset_dma` writer - Indicates the DMA port remap address"] -pub type U0_HIFI4_SCFG_DSP_MST_OFFSET_DMA_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 12, O, u16>; +pub type U0_HIFI4_SCFG_DSP_MST_OFFSET_DMA_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; impl R { #[doc = "Bits 0:11 - Indicates that master port remap address"] #[inline(always)] @@ -30,18 +28,22 @@ impl W { #[must_use] pub fn u0_hifi4_scfg_dsp_mst_offset_master( &mut self, - ) -> U0_HIFI4_SCFG_DSP_MST_OFFSET_MASTER_W { - U0_HIFI4_SCFG_DSP_MST_OFFSET_MASTER_W::new(self) + ) -> U0_HIFI4_SCFG_DSP_MST_OFFSET_MASTER_W { + U0_HIFI4_SCFG_DSP_MST_OFFSET_MASTER_W::new(self, 0) } #[doc = "Bits 16:27 - Indicates the DMA port remap address"] #[inline(always)] #[must_use] pub fn u0_hifi4_scfg_dsp_mst_offset_dma( &mut self, - ) -> U0_HIFI4_SCFG_DSP_MST_OFFSET_DMA_W { - U0_HIFI4_SCFG_DSP_MST_OFFSET_DMA_W::new(self) + ) -> U0_HIFI4_SCFG_DSP_MST_OFFSET_DMA_W { + U0_HIFI4_SCFG_DSP_MST_OFFSET_DMA_W::new(self, 16) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg600.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg600.rs index b9b6a5d..8f9e468 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg600.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg600.rs @@ -5,18 +5,15 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_mst0_aratomop_257_256` reader - u1_plda_pcie_axi4_mst0_aratomop_257_256"] pub type U1_PLDA_PCIE_AXI4_MST0_ARATOMOP_257_256_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_mst0_aratomop_257_256` writer - u1_plda_pcie_axi4_mst0_aratomop_257_256"] -pub type U1_PLDA_PCIE_AXI4_MST0_ARATOMOP_257_256_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U1_PLDA_PCIE_AXI4_MST0_ARATOMOP_257_256_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_plda_pcie_axi4_slv0_arfunc` reader - u1_plda_pcie_axi4_slv0_arfunc"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARFUNC_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_arfunc` writer - u1_plda_pcie_axi4_slv0_arfunc"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARFUNC_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 15, O, u16>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARFUNC_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; #[doc = "Field `u1_plda_pcie_axi4_slv0_arregion` reader - u1_plda_pcie_axi4_slv0_arregion"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARREGION_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_arregion` writer - u1_plda_pcie_axi4_slv0_arregion"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARREGION_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 4, O>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARREGION_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:1 - u1_plda_pcie_axi4_mst0_aratomop_257_256"] #[inline(always)] @@ -42,26 +39,30 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_mst0_aratomop_257_256( &mut self, - ) -> U1_PLDA_PCIE_AXI4_MST0_ARATOMOP_257_256_W { - U1_PLDA_PCIE_AXI4_MST0_ARATOMOP_257_256_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_MST0_ARATOMOP_257_256_W { + U1_PLDA_PCIE_AXI4_MST0_ARATOMOP_257_256_W::new(self, 0) } #[doc = "Bits 2:16 - u1_plda_pcie_axi4_slv0_arfunc"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_axi4_slv0_arfunc( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARFUNC_W { - U1_PLDA_PCIE_AXI4_SLV0_ARFUNC_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARFUNC_W { + U1_PLDA_PCIE_AXI4_SLV0_ARFUNC_W::new(self, 2) } #[doc = "Bits 17:20 - u1_plda_pcie_axi4_slv0_arregion"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_axi4_slv0_arregion( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARREGION_W { - U1_PLDA_PCIE_AXI4_SLV0_ARREGION_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARREGION_W { + U1_PLDA_PCIE_AXI4_SLV0_ARREGION_W::new(self, 17) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg604.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg604.rs index 955085c..7cf769c 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg604.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg604.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aruser_31_0` reader - u1_plda_pcie_axi4_slv0_aruser_31_0"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aruser_31_0` writer - u1_plda_pcie_axi4_slv0_aruser_31_0"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_aruser_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aruser_31_0( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W { - U1_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W { + U1_PLDA_PCIE_AXI4_SLV0_ARUSER_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg608.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg608.rs index 2def256..732cdb9 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg608.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg608.rs @@ -5,18 +5,15 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_aruser_40_32` reader - u1_plda_pcie_axi4_slv0_aruser_40_32"] pub type U1_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_aruser_40_32` writer - u1_plda_pcie_axi4_slv0_aruser_40_32"] -pub type U1_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 9, O, u16>; +pub type U1_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; #[doc = "Field `u1_plda_pcie_axi4_slv0_awfunc` reader - u1_plda_pcie_axi4_slv0_awfunc"] pub type U1_PLDA_PCIE_AXI4_SLV0_AWFUNC_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_awfunc` writer - u1_plda_pcie_axi4_slv0_awfunc"] -pub type U1_PLDA_PCIE_AXI4_SLV0_AWFUNC_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 15, O, u16>; +pub type U1_PLDA_PCIE_AXI4_SLV0_AWFUNC_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; #[doc = "Field `u1_plda_pcie_axi4_slv0_awregion` reader - u1_plda_pcie_axi4_slv0_awregion"] pub type U1_PLDA_PCIE_AXI4_SLV0_AWREGION_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_awregion` writer - u1_plda_pcie_axi4_slv0_awregion"] -pub type U1_PLDA_PCIE_AXI4_SLV0_AWREGION_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 4, O>; +pub type U1_PLDA_PCIE_AXI4_SLV0_AWREGION_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:8 - u1_plda_pcie_axi4_slv0_aruser_40_32"] #[inline(always)] @@ -40,26 +37,30 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_aruser_40_32( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W { - U1_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W { + U1_PLDA_PCIE_AXI4_SLV0_ARUSER_40_32_W::new(self, 0) } #[doc = "Bits 9:23 - u1_plda_pcie_axi4_slv0_awfunc"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_axi4_slv0_awfunc( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_AWFUNC_W { - U1_PLDA_PCIE_AXI4_SLV0_AWFUNC_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_AWFUNC_W { + U1_PLDA_PCIE_AXI4_SLV0_AWFUNC_W::new(self, 9) } #[doc = "Bits 24:27 - u1_plda_pcie_axi4_slv0_awregion"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_axi4_slv0_awregion( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_AWREGION_W { - U1_PLDA_PCIE_AXI4_SLV0_AWREGION_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_AWREGION_W { + U1_PLDA_PCIE_AXI4_SLV0_AWREGION_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg612.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg612.rs index fbdc25e..88dbf6f 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg612.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg612.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_awuser_31_0` reader - u1_plda_pcie_axi4_slv0_awuser_31_0"] pub type U1_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_awuser_31_0` writer - u1_plda_pcie_axi4_slv0_awuser_31_0"] -pub type U1_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_axi4_slv0_awuser_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_awuser_31_0( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W { - U1_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W { + U1_PLDA_PCIE_AXI4_SLV0_AWUSER_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg616.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg616.rs index 734c21d..b0410ad 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg616.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg616.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_awuser_40_32` reader - u1_plda_pcie_axi4_slv0_awuser_40_32"] pub type U1_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_awuser_40_32` writer - u1_plda_pcie_axi4_slv0_awuser_40_32"] -pub type U1_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 9, O, u16>; +pub type U1_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; #[doc = "Field `u1_plda_pcie_axi4_slv0_rderr` reader - u1_plda_pcie_axi4_slv0_rderr"] pub type U1_PLDA_PCIE_AXI4_SLV0_RDERR_R = crate::FieldReader; impl R { @@ -27,10 +26,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_awuser_40_32( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W { - U1_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W { + U1_PLDA_PCIE_AXI4_SLV0_AWUSER_40_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg620.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg620.rs index 0e4b321..3d6a433 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg620.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg620.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg624.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg624.rs index a6e9054..5c35c14 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg624.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg624.rs @@ -5,12 +5,11 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slv0_wderr` reader - u1_plda_pcie_axi4_slv0_wderr"] pub type U1_PLDA_PCIE_AXI4_SLV0_WDERR_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slv0_wderr` writer - u1_plda_pcie_axi4_slv0_wderr"] -pub type U1_PLDA_PCIE_AXI4_SLV0_WDERR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type U1_PLDA_PCIE_AXI4_SLV0_WDERR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `u1_plda_pcie_axi4_slvl_arfunc` reader - u1_plda_pcie_axi4_slvl_arfunc"] pub type U1_PLDA_PCIE_AXI4_SLVL_ARFUNC_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slvl_arfunc` writer - u1_plda_pcie_axi4_slvl_arfunc"] -pub type U1_PLDA_PCIE_AXI4_SLVL_ARFUNC_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 15, O, u16>; +pub type U1_PLDA_PCIE_AXI4_SLVL_ARFUNC_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; impl R { #[doc = "Bits 0:7 - u1_plda_pcie_axi4_slv0_wderr"] #[inline(always)] @@ -29,18 +28,22 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slv0_wderr( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLV0_WDERR_W { - U1_PLDA_PCIE_AXI4_SLV0_WDERR_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLV0_WDERR_W { + U1_PLDA_PCIE_AXI4_SLV0_WDERR_W::new(self, 0) } #[doc = "Bits 8:22 - u1_plda_pcie_axi4_slvl_arfunc"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_axi4_slvl_arfunc( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLVL_ARFUNC_W { - U1_PLDA_PCIE_AXI4_SLVL_ARFUNC_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLVL_ARFUNC_W { + U1_PLDA_PCIE_AXI4_SLVL_ARFUNC_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg628.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg628.rs index a660c88..e60fff2 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg628.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg628.rs @@ -5,26 +5,25 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_axi4_slvl_awfunc` reader - u1_plda_pcie_axi4_slvl_awfunc"] pub type U1_PLDA_PCIE_AXI4_SLVL_AWFUNC_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_axi4_slvl_awfunc` writer - u1_plda_pcie_axi4_slvl_awfunc"] -pub type U1_PLDA_PCIE_AXI4_SLVL_AWFUNC_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 15, O, u16>; +pub type U1_PLDA_PCIE_AXI4_SLVL_AWFUNC_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; #[doc = "Field `u1_plda_pcie_bus_width_o` reader - u1_plda_pcie_bus_width_o"] pub type U1_PLDA_PCIE_BUS_WIDTH_O_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_bypass_codec` reader - u1_plda_pcie_bypass_codec"] pub type U1_PLDA_PCIE_BYPASS_CODEC_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_bypass_codec` writer - u1_plda_pcie_bypass_codec"] -pub type U1_PLDA_PCIE_BYPASS_CODEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_BYPASS_CODEC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_ckref_src` reader - u1_plda_pcie_ckref_src"] pub type U1_PLDA_PCIE_CKREF_SRC_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_ckref_src` writer - u1_plda_pcie_ckref_src"] -pub type U1_PLDA_PCIE_CKREF_SRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U1_PLDA_PCIE_CKREF_SRC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_plda_pcie_clk_sel` reader - u1_plda_pcie_clk_sel"] pub type U1_PLDA_PCIE_CLK_SEL_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_clk_sel` writer - u1_plda_pcie_clk_sel"] -pub type U1_PLDA_PCIE_CLK_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U1_PLDA_PCIE_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_plda_pcie_clkreq` reader - u1_plda_pcie_clkreq"] pub type U1_PLDA_PCIE_CLKREQ_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_clkreq` writer - u1_plda_pcie_clkreq"] -pub type U1_PLDA_PCIE_CLKREQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_CLKREQ_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:14 - u1_plda_pcie_axi4_slvl_awfunc"] #[inline(always)] @@ -63,42 +62,44 @@ impl W { #[must_use] pub fn u1_plda_pcie_axi4_slvl_awfunc( &mut self, - ) -> U1_PLDA_PCIE_AXI4_SLVL_AWFUNC_W { - U1_PLDA_PCIE_AXI4_SLVL_AWFUNC_W::new(self) + ) -> U1_PLDA_PCIE_AXI4_SLVL_AWFUNC_W { + U1_PLDA_PCIE_AXI4_SLVL_AWFUNC_W::new(self, 0) } #[doc = "Bit 17 - u1_plda_pcie_bypass_codec"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_bypass_codec( &mut self, - ) -> U1_PLDA_PCIE_BYPASS_CODEC_W { - U1_PLDA_PCIE_BYPASS_CODEC_W::new(self) + ) -> U1_PLDA_PCIE_BYPASS_CODEC_W { + U1_PLDA_PCIE_BYPASS_CODEC_W::new(self, 17) } #[doc = "Bits 18:19 - u1_plda_pcie_ckref_src"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_ckref_src( &mut self, - ) -> U1_PLDA_PCIE_CKREF_SRC_W { - U1_PLDA_PCIE_CKREF_SRC_W::new(self) + ) -> U1_PLDA_PCIE_CKREF_SRC_W { + U1_PLDA_PCIE_CKREF_SRC_W::new(self, 18) } #[doc = "Bits 20:21 - u1_plda_pcie_clk_sel"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_clk_sel( &mut self, - ) -> U1_PLDA_PCIE_CLK_SEL_W { - U1_PLDA_PCIE_CLK_SEL_W::new(self) + ) -> U1_PLDA_PCIE_CLK_SEL_W { + U1_PLDA_PCIE_CLK_SEL_W::new(self, 20) } #[doc = "Bit 22 - u1_plda_pcie_clkreq"] #[inline(always)] #[must_use] - pub fn u1_plda_pcie_clkreq( - &mut self, - ) -> U1_PLDA_PCIE_CLKREQ_W { - U1_PLDA_PCIE_CLKREQ_W::new(self) + pub fn u1_plda_pcie_clkreq(&mut self) -> U1_PLDA_PCIE_CLKREQ_W { + U1_PLDA_PCIE_CLKREQ_W::new(self, 22) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg632.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg632.rs index 7386447..469c29a 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg632.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg632.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_31_0` reader - u1_plda_pcie_k_phyparam_31_0"] pub type U1_PLDA_PCIE_K_PHYPARAM_31_0_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_31_0` writer - u1_plda_pcie_k_phyparam_31_0"] -pub type U1_PLDA_PCIE_K_PHYPARAM_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_31_0( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_31_0_W { - U1_PLDA_PCIE_K_PHYPARAM_31_0_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_31_0_W { + U1_PLDA_PCIE_K_PHYPARAM_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg636.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg636.rs index 6c3fbd3..39cdb50 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg636.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg636.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_63_32` reader - u1_plda_pcie_k_phyparam_63_32"] pub type U1_PLDA_PCIE_K_PHYPARAM_63_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_63_32` writer - u1_plda_pcie_k_phyparam_63_32"] -pub type U1_PLDA_PCIE_K_PHYPARAM_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_63_32( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_63_32_W { - U1_PLDA_PCIE_K_PHYPARAM_63_32_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_63_32_W { + U1_PLDA_PCIE_K_PHYPARAM_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg64.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg64.rs index ff0dd4d..8329950 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg64.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg64.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_hifi4_scfg_dsp_slv_offset` reader - The value indicates the slave port remap address"] pub type U0_HIFI4_SCFG_DSP_SLV_OFFSET_R = crate::FieldReader; #[doc = "Field `u0_hifi4_scfg_dsp_slv_offset` writer - The value indicates the slave port remap address"] -pub type U0_HIFI4_SCFG_DSP_SLV_OFFSET_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_HIFI4_SCFG_DSP_SLV_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - The value indicates the slave port remap address"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_hifi4_scfg_dsp_slv_offset( &mut self, - ) -> U0_HIFI4_SCFG_DSP_SLV_OFFSET_W { - U0_HIFI4_SCFG_DSP_SLV_OFFSET_W::new(self) + ) -> U0_HIFI4_SCFG_DSP_SLV_OFFSET_W { + U0_HIFI4_SCFG_DSP_SLV_OFFSET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg640.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg640.rs index 55e5c11..f333d10 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg640.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg640.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_95_64` reader - u1_plda_pcie_k_phyparam_95_64"] pub type U1_PLDA_PCIE_K_PHYPARAM_95_64_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_95_64` writer - u1_plda_pcie_k_phyparam_95_64"] -pub type U1_PLDA_PCIE_K_PHYPARAM_95_64_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_95_64_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_95_64"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_95_64( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_95_64_W { - U1_PLDA_PCIE_K_PHYPARAM_95_64_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_95_64_W { + U1_PLDA_PCIE_K_PHYPARAM_95_64_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg644.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg644.rs index 6c9eb06..b716f8a 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg644.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg644.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_127_96` reader - u1_plda_pcie_k_phyparam_127_96"] pub type U1_PLDA_PCIE_K_PHYPARAM_127_96_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_127_96` writer - u1_plda_pcie_k_phyparam_127_96"] -pub type U1_PLDA_PCIE_K_PHYPARAM_127_96_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_127_96_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_127_96"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_127_96( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_127_96_W { - U1_PLDA_PCIE_K_PHYPARAM_127_96_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_127_96_W { + U1_PLDA_PCIE_K_PHYPARAM_127_96_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg648.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg648.rs index 39452ce..8ea0bb4 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg648.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg648.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_159_128` reader - u1_plda_pcie_k_phyparam_159_128"] pub type U1_PLDA_PCIE_K_PHYPARAM_159_128_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_159_128` writer - u1_plda_pcie_k_phyparam_159_128"] -pub type U1_PLDA_PCIE_K_PHYPARAM_159_128_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_159_128_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_159_128"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_159_128( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_159_128_W { - U1_PLDA_PCIE_K_PHYPARAM_159_128_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_159_128_W { + U1_PLDA_PCIE_K_PHYPARAM_159_128_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg652.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg652.rs index 8275e9e..cbdae14 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg652.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg652.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_191_160` reader - u1_plda_pcie_k_phyparam_191_160"] pub type U1_PLDA_PCIE_K_PHYPARAM_191_160_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_191_160` writer - u1_plda_pcie_k_phyparam_191_160"] -pub type U1_PLDA_PCIE_K_PHYPARAM_191_160_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_191_160_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_191_160"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_191_160( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_191_160_W { - U1_PLDA_PCIE_K_PHYPARAM_191_160_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_191_160_W { + U1_PLDA_PCIE_K_PHYPARAM_191_160_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg656.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg656.rs index 6c97434..7559a4f 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg656.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg656.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_223_192` reader - u1_plda_pcie_k_phyparam_223_192"] pub type U1_PLDA_PCIE_K_PHYPARAM_223_192_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_223_192` writer - u1_plda_pcie_k_phyparam_223_192"] -pub type U1_PLDA_PCIE_K_PHYPARAM_223_192_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_223_192_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_223_192"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_223_192( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_223_192_W { - U1_PLDA_PCIE_K_PHYPARAM_223_192_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_223_192_W { + U1_PLDA_PCIE_K_PHYPARAM_223_192_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg660.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg660.rs index ccc8f56..6d595e5 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg660.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg660.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_255_224` reader - u1_plda_pcie_k_phyparam_255_224"] pub type U1_PLDA_PCIE_K_PHYPARAM_255_224_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_255_224` writer - u1_plda_pcie_k_phyparam_255_224"] -pub type U1_PLDA_PCIE_K_PHYPARAM_255_224_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_255_224_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_255_224"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_255_224( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_255_224_W { - U1_PLDA_PCIE_K_PHYPARAM_255_224_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_255_224_W { + U1_PLDA_PCIE_K_PHYPARAM_255_224_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg664.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg664.rs index ad2e18d..e87eac6 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg664.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg664.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_287_256` reader - u1_plda_pcie_k_phyparam_287_256"] pub type U1_PLDA_PCIE_K_PHYPARAM_287_256_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_287_256` writer - u1_plda_pcie_k_phyparam_287_256"] -pub type U1_PLDA_PCIE_K_PHYPARAM_287_256_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_287_256_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_287_256"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_287_256( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_287_256_W { - U1_PLDA_PCIE_K_PHYPARAM_287_256_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_287_256_W { + U1_PLDA_PCIE_K_PHYPARAM_287_256_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg668.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg668.rs index e077094..bad773b 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg668.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg668.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_319_288` reader - u1_plda_pcie_k_phyparam_319_288"] pub type U1_PLDA_PCIE_K_PHYPARAM_319_288_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_319_288` writer - u1_plda_pcie_k_phyparam_319_288"] -pub type U1_PLDA_PCIE_K_PHYPARAM_319_288_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_319_288_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_319_288"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_319_288( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_319_288_W { - U1_PLDA_PCIE_K_PHYPARAM_319_288_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_319_288_W { + U1_PLDA_PCIE_K_PHYPARAM_319_288_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg672.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg672.rs index f9366d2..c844238 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg672.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg672.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_351_320` reader - u1_plda_pcie_k_phyparam_351_320"] pub type U1_PLDA_PCIE_K_PHYPARAM_351_320_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_351_320` writer - u1_plda_pcie_k_phyparam_351_320"] -pub type U1_PLDA_PCIE_K_PHYPARAM_351_320_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_351_320_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_351_320"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_351_320( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_351_320_W { - U1_PLDA_PCIE_K_PHYPARAM_351_320_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_351_320_W { + U1_PLDA_PCIE_K_PHYPARAM_351_320_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg676.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg676.rs index e0a8c78..9b4d7ac 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg676.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg676.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_383_352` reader - u1_plda_pcie_k_phyparam_383_352"] pub type U1_PLDA_PCIE_K_PHYPARAM_383_352_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_383_352` writer - u1_plda_pcie_k_phyparam_383_352"] -pub type U1_PLDA_PCIE_K_PHYPARAM_383_352_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_383_352_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_383_352"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_383_352( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_383_352_W { - U1_PLDA_PCIE_K_PHYPARAM_383_352_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_383_352_W { + U1_PLDA_PCIE_K_PHYPARAM_383_352_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg68.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg68.rs index 5cfb7f6..29b2617 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg68.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg68.rs @@ -5,47 +5,43 @@ pub type W = crate::W; #[doc = "Field `u0_hifi4_scfg_sram_config_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] pub type U0_HIFI4_SCFG_SRAM_CONFIG_SLP_R = crate::BitReader; #[doc = "Field `u0_hifi4_scfg_sram_config_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] -pub type U0_HIFI4_SCFG_SRAM_CONFIG_SLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_SCFG_SRAM_CONFIG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_scfg_sram_config_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] pub type U0_HIFI4_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_R = crate::BitReader; #[doc = "Field `u0_hifi4_scfg_sram_config_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] -pub type U0_HIFI4_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_scfg_sram_config_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_HIFI4_SCFG_SRAM_CONFIG_RTSEL_R = crate::FieldReader; #[doc = "Field `u0_hifi4_scfg_sram_config_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_HIFI4_SCFG_SRAM_CONFIG_RTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_HIFI4_SCFG_SRAM_CONFIG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_hifi4_scfg_sram_config_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_HIFI4_SCFG_SRAM_CONFIG_PTSEL_R = crate::FieldReader; #[doc = "Field `u0_hifi4_scfg_sram_config_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_HIFI4_SCFG_SRAM_CONFIG_PTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_HIFI4_SCFG_SRAM_CONFIG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_hifi4_scfg_sram_config_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] pub type U0_HIFI4_SCFG_SRAM_CONFIG_TRB_R = crate::FieldReader; #[doc = "Field `u0_hifi4_scfg_sram_config_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] -pub type U0_HIFI4_SCFG_SRAM_CONFIG_TRB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_HIFI4_SCFG_SRAM_CONFIG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_hifi4_scfg_sram_config_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_HIFI4_SCFG_SRAM_CONFIG_WTSEL_R = crate::FieldReader; #[doc = "Field `u0_hifi4_scfg_sram_config_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_HIFI4_SCFG_SRAM_CONFIG_WTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_HIFI4_SCFG_SRAM_CONFIG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_hifi4_scfg_sram_config_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] pub type U0_HIFI4_SCFG_SRAM_CONFIG_VS_R = crate::BitReader; #[doc = "Field `u0_hifi4_scfg_sram_config_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] -pub type U0_HIFI4_SCFG_SRAM_CONFIG_VS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_SCFG_SRAM_CONFIG_VS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_scfg_sram_config_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] pub type U0_HIFI4_SCFG_SRAM_CONFIG_VG_R = crate::BitReader; #[doc = "Field `u0_hifi4_scfg_sram_config_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] -pub type U0_HIFI4_SCFG_SRAM_CONFIG_VG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_SCFG_SRAM_CONFIG_VG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_statvectorsel` reader - When the value is 1, it indicates that the AltResetVec is valid"] pub type U0_HIFI4_STATVECTORSEL_R = crate::BitReader; #[doc = "Field `u0_hifi4_statvectorsel` writer - When the value is 1, it indicates that the AltResetVec is valid"] -pub type U0_HIFI4_STATVECTORSEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_STATVECTORSEL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_trigin_idma` reader - DMA port trigger"] pub type U0_HIFI4_TRIGIN_IDMA_R = crate::BitReader; #[doc = "Field `u0_hifi4_trigin_idma` writer - DMA port trigger"] -pub type U0_HIFI4_TRIGIN_IDMA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_HIFI4_TRIGIN_IDMA_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_hifi4_trigout_idma` reader - DMA port trigger"] pub type U0_HIFI4_TRIGOUT_IDMA_R = crate::BitReader; #[doc = "Field `u0_hifi4_xocdmode` reader - Debug signal"] @@ -127,82 +123,84 @@ impl W { #[must_use] pub fn u0_hifi4_scfg_sram_config_slp( &mut self, - ) -> U0_HIFI4_SCFG_SRAM_CONFIG_SLP_W { - U0_HIFI4_SCFG_SRAM_CONFIG_SLP_W::new(self) + ) -> U0_HIFI4_SCFG_SRAM_CONFIG_SLP_W { + U0_HIFI4_SCFG_SRAM_CONFIG_SLP_W::new(self, 0) } #[doc = "Bit 1 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_hifi4_scfg_sram_config_sram_config_sd( &mut self, - ) -> U0_HIFI4_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W { - U0_HIFI4_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self) + ) -> U0_HIFI4_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W { + U0_HIFI4_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self, 1) } #[doc = "Bits 2:3 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_hifi4_scfg_sram_config_rtsel( &mut self, - ) -> U0_HIFI4_SCFG_SRAM_CONFIG_RTSEL_W { - U0_HIFI4_SCFG_SRAM_CONFIG_RTSEL_W::new(self) + ) -> U0_HIFI4_SCFG_SRAM_CONFIG_RTSEL_W { + U0_HIFI4_SCFG_SRAM_CONFIG_RTSEL_W::new(self, 2) } #[doc = "Bits 4:5 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_hifi4_scfg_sram_config_ptsel( &mut self, - ) -> U0_HIFI4_SCFG_SRAM_CONFIG_PTSEL_W { - U0_HIFI4_SCFG_SRAM_CONFIG_PTSEL_W::new(self) + ) -> U0_HIFI4_SCFG_SRAM_CONFIG_PTSEL_W { + U0_HIFI4_SCFG_SRAM_CONFIG_PTSEL_W::new(self, 4) } #[doc = "Bits 6:7 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_hifi4_scfg_sram_config_trb( &mut self, - ) -> U0_HIFI4_SCFG_SRAM_CONFIG_TRB_W { - U0_HIFI4_SCFG_SRAM_CONFIG_TRB_W::new(self) + ) -> U0_HIFI4_SCFG_SRAM_CONFIG_TRB_W { + U0_HIFI4_SCFG_SRAM_CONFIG_TRB_W::new(self, 6) } #[doc = "Bits 8:9 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_hifi4_scfg_sram_config_wtsel( &mut self, - ) -> U0_HIFI4_SCFG_SRAM_CONFIG_WTSEL_W { - U0_HIFI4_SCFG_SRAM_CONFIG_WTSEL_W::new(self) + ) -> U0_HIFI4_SCFG_SRAM_CONFIG_WTSEL_W { + U0_HIFI4_SCFG_SRAM_CONFIG_WTSEL_W::new(self, 8) } #[doc = "Bit 10 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_hifi4_scfg_sram_config_vs( &mut self, - ) -> U0_HIFI4_SCFG_SRAM_CONFIG_VS_W { - U0_HIFI4_SCFG_SRAM_CONFIG_VS_W::new(self) + ) -> U0_HIFI4_SCFG_SRAM_CONFIG_VS_W { + U0_HIFI4_SCFG_SRAM_CONFIG_VS_W::new(self, 10) } #[doc = "Bit 11 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_hifi4_scfg_sram_config_vg( &mut self, - ) -> U0_HIFI4_SCFG_SRAM_CONFIG_VG_W { - U0_HIFI4_SCFG_SRAM_CONFIG_VG_W::new(self) + ) -> U0_HIFI4_SCFG_SRAM_CONFIG_VG_W { + U0_HIFI4_SCFG_SRAM_CONFIG_VG_W::new(self, 11) } #[doc = "Bit 12 - When the value is 1, it indicates that the AltResetVec is valid"] #[inline(always)] #[must_use] pub fn u0_hifi4_statvectorsel( &mut self, - ) -> U0_HIFI4_STATVECTORSEL_W { - U0_HIFI4_STATVECTORSEL_W::new(self) + ) -> U0_HIFI4_STATVECTORSEL_W { + U0_HIFI4_STATVECTORSEL_W::new(self, 12) } #[doc = "Bit 13 - DMA port trigger"] #[inline(always)] #[must_use] - pub fn u0_hifi4_trigin_idma( - &mut self, - ) -> U0_HIFI4_TRIGIN_IDMA_W { - U0_HIFI4_TRIGIN_IDMA_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn u0_hifi4_trigin_idma(&mut self) -> U0_HIFI4_TRIGIN_IDMA_W { + U0_HIFI4_TRIGIN_IDMA_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg680.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg680.rs index 777ecfb..6511134 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg680.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg680.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_415_384` reader - u1_plda_pcie_k_phyparam_415_384"] pub type U1_PLDA_PCIE_K_PHYPARAM_415_384_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_415_384` writer - u1_plda_pcie_k_phyparam_415_384"] -pub type U1_PLDA_PCIE_K_PHYPARAM_415_384_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_415_384_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_415_384"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_415_384( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_415_384_W { - U1_PLDA_PCIE_K_PHYPARAM_415_384_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_415_384_W { + U1_PLDA_PCIE_K_PHYPARAM_415_384_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg684.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg684.rs index c2373e8..3730b51 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg684.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg684.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_447_416` reader - u1_plda_pcie_k_phyparam_447_416"] pub type U1_PLDA_PCIE_K_PHYPARAM_447_416_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_447_416` writer - u1_plda_pcie_k_phyparam_447_416"] -pub type U1_PLDA_PCIE_K_PHYPARAM_447_416_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_447_416_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_447_416"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_447_416( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_447_416_W { - U1_PLDA_PCIE_K_PHYPARAM_447_416_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_447_416_W { + U1_PLDA_PCIE_K_PHYPARAM_447_416_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg688.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg688.rs index c2441b3..42d0273 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg688.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg688.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_479_448` reader - u1_plda_pcie_k_phyparam_479_448"] pub type U1_PLDA_PCIE_K_PHYPARAM_479_448_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_479_448` writer - u1_plda_pcie_k_phyparam_479_448"] -pub type U1_PLDA_PCIE_K_PHYPARAM_479_448_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_479_448_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_479_448"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_479_448( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_479_448_W { - U1_PLDA_PCIE_K_PHYPARAM_479_448_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_479_448_W { + U1_PLDA_PCIE_K_PHYPARAM_479_448_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg692.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg692.rs index 0961da4..78bdbd1 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg692.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg692.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_511_480` reader - u1_plda_pcie_k_phyparam_511_480"] pub type U1_PLDA_PCIE_K_PHYPARAM_511_480_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_511_480` writer - u1_plda_pcie_k_phyparam_511_480"] -pub type U1_PLDA_PCIE_K_PHYPARAM_511_480_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_511_480_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_511_480"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_511_480( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_511_480_W { - U1_PLDA_PCIE_K_PHYPARAM_511_480_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_511_480_W { + U1_PLDA_PCIE_K_PHYPARAM_511_480_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg696.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg696.rs index 131098f..b092a7d 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg696.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg696.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_543_512` reader - u1_plda_pcie_k_phyparam_543_512"] pub type U1_PLDA_PCIE_K_PHYPARAM_543_512_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_543_512` writer - u1_plda_pcie_k_phyparam_543_512"] -pub type U1_PLDA_PCIE_K_PHYPARAM_543_512_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_543_512_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_543_512"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_543_512( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_543_512_W { - U1_PLDA_PCIE_K_PHYPARAM_543_512_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_543_512_W { + U1_PLDA_PCIE_K_PHYPARAM_543_512_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg700.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg700.rs index 5a64c84..1a3f809 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg700.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg700.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_575_544` reader - u1_plda_pcie_k_phyparam_575_544"] pub type U1_PLDA_PCIE_K_PHYPARAM_575_544_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_575_544` writer - u1_plda_pcie_k_phyparam_575_544"] -pub type U1_PLDA_PCIE_K_PHYPARAM_575_544_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_575_544_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_575_544"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_575_544( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_575_544_W { - U1_PLDA_PCIE_K_PHYPARAM_575_544_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_575_544_W { + U1_PLDA_PCIE_K_PHYPARAM_575_544_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg704.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg704.rs index 74c01cf..b1d0ac8 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg704.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg704.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_607_576` reader - u1_plda_pcie_k_phyparam_607_576"] pub type U1_PLDA_PCIE_K_PHYPARAM_607_576_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_607_576` writer - u1_plda_pcie_k_phyparam_607_576"] -pub type U1_PLDA_PCIE_K_PHYPARAM_607_576_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_607_576_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_607_576"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_607_576( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_607_576_W { - U1_PLDA_PCIE_K_PHYPARAM_607_576_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_607_576_W { + U1_PLDA_PCIE_K_PHYPARAM_607_576_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg708.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg708.rs index 1d38d31..774d93e 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg708.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg708.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_639_608` reader - u1_plda_pcie_k_phyparam_639_608"] pub type U1_PLDA_PCIE_K_PHYPARAM_639_608_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_639_608` writer - u1_plda_pcie_k_phyparam_639_608"] -pub type U1_PLDA_PCIE_K_PHYPARAM_639_608_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_639_608_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_639_608"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_639_608( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_639_608_W { - U1_PLDA_PCIE_K_PHYPARAM_639_608_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_639_608_W { + U1_PLDA_PCIE_K_PHYPARAM_639_608_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg712.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg712.rs index 1e583dd..9e83df8 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg712.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg712.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_671_640` reader - u1_plda_pcie_k_phyparam_671_640"] pub type U1_PLDA_PCIE_K_PHYPARAM_671_640_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_671_640` writer - u1_plda_pcie_k_phyparam_671_640"] -pub type U1_PLDA_PCIE_K_PHYPARAM_671_640_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_671_640_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_671_640"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_671_640( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_671_640_W { - U1_PLDA_PCIE_K_PHYPARAM_671_640_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_671_640_W { + U1_PLDA_PCIE_K_PHYPARAM_671_640_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg716.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg716.rs index 030c5a8..a7ba456 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg716.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg716.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_703_672` reader - u1_plda_pcie_k_phyparam_703_672"] pub type U1_PLDA_PCIE_K_PHYPARAM_703_672_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_703_672` writer - u1_plda_pcie_k_phyparam_703_672"] -pub type U1_PLDA_PCIE_K_PHYPARAM_703_672_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_703_672_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_703_672"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_703_672( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_703_672_W { - U1_PLDA_PCIE_K_PHYPARAM_703_672_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_703_672_W { + U1_PLDA_PCIE_K_PHYPARAM_703_672_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg72.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg72.rs index bae7518..fc60c54 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg72.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg72.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg720.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg720.rs index aae170d..b03d03c 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg720.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg720.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_735_704` reader - u1_plda_pcie_k_phyparam_735_704"] pub type U1_PLDA_PCIE_K_PHYPARAM_735_704_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_735_704` writer - u1_plda_pcie_k_phyparam_735_704"] -pub type U1_PLDA_PCIE_K_PHYPARAM_735_704_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_735_704_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_735_704"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_735_704( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_735_704_W { - U1_PLDA_PCIE_K_PHYPARAM_735_704_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_735_704_W { + U1_PLDA_PCIE_K_PHYPARAM_735_704_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg724.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg724.rs index 9659d58..596c1ba 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg724.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg724.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_767_736` reader - u1_plda_pcie_k_phyparam_767_736"] pub type U1_PLDA_PCIE_K_PHYPARAM_767_736_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_767_736` writer - u1_plda_pcie_k_phyparam_767_736"] -pub type U1_PLDA_PCIE_K_PHYPARAM_767_736_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_767_736_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_767_736"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_767_736( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_767_736_W { - U1_PLDA_PCIE_K_PHYPARAM_767_736_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_767_736_W { + U1_PLDA_PCIE_K_PHYPARAM_767_736_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg728.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg728.rs index 0c676a9..2328a2e 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg728.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg728.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_799_768` reader - u1_plda_pcie_k_phyparam_799_768"] pub type U1_PLDA_PCIE_K_PHYPARAM_799_768_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_799_768` writer - u1_plda_pcie_k_phyparam_799_768"] -pub type U1_PLDA_PCIE_K_PHYPARAM_799_768_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_799_768_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_799_768"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_799_768( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_799_768_W { - U1_PLDA_PCIE_K_PHYPARAM_799_768_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_799_768_W { + U1_PLDA_PCIE_K_PHYPARAM_799_768_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg732.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg732.rs index 447ba10..c930a10 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg732.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg732.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_831_800` reader - u1_plda_pcie_k_phyparam_831_800"] pub type U1_PLDA_PCIE_K_PHYPARAM_831_800_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_831_800` writer - u1_plda_pcie_k_phyparam_831_800"] -pub type U1_PLDA_PCIE_K_PHYPARAM_831_800_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_K_PHYPARAM_831_800_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_k_phyparam_831_800"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_831_800( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_831_800_W { - U1_PLDA_PCIE_K_PHYPARAM_831_800_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_831_800_W { + U1_PLDA_PCIE_K_PHYPARAM_831_800_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg736.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg736.rs index a5b0cf6..8722485 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg736.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg736.rs @@ -5,18 +5,17 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_k_phyparam_839_832` reader - u1_plda_pcie_k_phyparam_839_832"] pub type U1_PLDA_PCIE_K_PHYPARAM_839_832_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_k_phyparam_839_832` writer - u1_plda_pcie_k_phyparam_839_832"] -pub type U1_PLDA_PCIE_K_PHYPARAM_839_832_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 8, O>; +pub type U1_PLDA_PCIE_K_PHYPARAM_839_832_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `u1_plda_pcie_k_rp_nep` reader - u1_plda_pcie_k_rp_nep"] pub type U1_PLDA_PCIE_K_RP_NEP_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_k_rp_nep` writer - u1_plda_pcie_k_rp_nep"] -pub type U1_PLDA_PCIE_K_RP_NEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_K_RP_NEP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_l1sub_entack` reader - u1_plda_pcie_l1sub_entack"] pub type U1_PLDA_PCIE_L1SUB_ENTACK_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_l1sub_entreq` reader - u1_plda_pcie_l1sub_entreq"] pub type U1_PLDA_PCIE_L1SUB_ENTREQ_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_l1sub_entreq` writer - u1_plda_pcie_l1sub_entreq"] -pub type U1_PLDA_PCIE_L1SUB_ENTREQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_L1SUB_ENTREQ_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:7 - u1_plda_pcie_k_phyparam_839_832"] #[inline(always)] @@ -45,26 +44,30 @@ impl W { #[must_use] pub fn u1_plda_pcie_k_phyparam_839_832( &mut self, - ) -> U1_PLDA_PCIE_K_PHYPARAM_839_832_W { - U1_PLDA_PCIE_K_PHYPARAM_839_832_W::new(self) + ) -> U1_PLDA_PCIE_K_PHYPARAM_839_832_W { + U1_PLDA_PCIE_K_PHYPARAM_839_832_W::new(self, 0) } #[doc = "Bit 8 - u1_plda_pcie_k_rp_nep"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_k_rp_nep( &mut self, - ) -> U1_PLDA_PCIE_K_RP_NEP_W { - U1_PLDA_PCIE_K_RP_NEP_W::new(self) + ) -> U1_PLDA_PCIE_K_RP_NEP_W { + U1_PLDA_PCIE_K_RP_NEP_W::new(self, 8) } #[doc = "Bit 10 - u1_plda_pcie_l1sub_entreq"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_l1sub_entreq( &mut self, - ) -> U1_PLDA_PCIE_L1SUB_ENTREQ_W { - U1_PLDA_PCIE_L1SUB_ENTREQ_W::new(self) + ) -> U1_PLDA_PCIE_L1SUB_ENTREQ_W { + U1_PLDA_PCIE_L1SUB_ENTREQ_W::new(self, 10) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg740.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg740.rs index c23e470..8dfb9f4 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg740.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg740.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_local_interrupt_in` reader - u1_plda_pcie_local_interrupt_in"] pub type U1_PLDA_PCIE_LOCAL_INTERRUPT_IN_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_local_interrupt_in` writer - u1_plda_pcie_local_interrupt_in"] -pub type U1_PLDA_PCIE_LOCAL_INTERRUPT_IN_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_LOCAL_INTERRUPT_IN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_local_interrupt_in"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_local_interrupt_in( &mut self, - ) -> U1_PLDA_PCIE_LOCAL_INTERRUPT_IN_W { - U1_PLDA_PCIE_LOCAL_INTERRUPT_IN_W::new(self) + ) -> U1_PLDA_PCIE_LOCAL_INTERRUPT_IN_W { + U1_PLDA_PCIE_LOCAL_INTERRUPT_IN_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg744.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg744.rs index 37dc7fe..fe77514 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg744.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg744.rs @@ -5,28 +5,27 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_mperstn` reader - u1_plda_pcie_mperstn"] pub type U1_PLDA_PCIE_MPERSTN_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_mperstn` writer - u1_plda_pcie_mperstn"] -pub type U1_PLDA_PCIE_MPERSTN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_MPERSTN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_pcie_ebuf_mode` reader - u1_plda_pcie_pcie_ebuf_mode"] pub type U1_PLDA_PCIE_PCIE_EBUF_MODE_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_pcie_ebuf_mode` writer - u1_plda_pcie_pcie_ebuf_mode"] -pub type U1_PLDA_PCIE_PCIE_EBUF_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_PCIE_EBUF_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_pcie_phy_test_cfg` reader - u1_plda_pcie_pcie_phy_test_cfg"] pub type U1_PLDA_PCIE_PCIE_PHY_TEST_CFG_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pcie_phy_test_cfg` writer - u1_plda_pcie_pcie_phy_test_cfg"] -pub type U1_PLDA_PCIE_PCIE_PHY_TEST_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 23, O, u32>; +pub type U1_PLDA_PCIE_PCIE_PHY_TEST_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>; #[doc = "Field `u1_plda_pcie_pcie_rx_eq_training` reader - u1_plda_pcie_pcie_rx_eq_training"] pub type U1_PLDA_PCIE_PCIE_RX_EQ_TRAINING_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_pcie_rx_eq_training` writer - u1_plda_pcie_pcie_rx_eq_training"] -pub type U1_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_pcie_rxterm_en` reader - u1_plda_pcie_pcie_rxterm_en"] pub type U1_PLDA_PCIE_PCIE_RXTERM_EN_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_pcie_rxterm_en` writer - u1_plda_pcie_pcie_rxterm_en"] -pub type U1_PLDA_PCIE_PCIE_RXTERM_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_PCIE_RXTERM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_pcie_tx_oneszeros` reader - u1_plda_pcie_pcie_tx_oneszeros"] pub type U1_PLDA_PCIE_PCIE_TX_ONESZEROS_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_pcie_tx_oneszeros` writer - u1_plda_pcie_pcie_tx_oneszeros"] -pub type U1_PLDA_PCIE_PCIE_TX_ONESZEROS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_PCIE_TX_ONESZEROS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - u1_plda_pcie_mperstn"] #[inline(always)] @@ -65,50 +64,54 @@ impl W { #[must_use] pub fn u1_plda_pcie_mperstn( &mut self, - ) -> U1_PLDA_PCIE_MPERSTN_W { - U1_PLDA_PCIE_MPERSTN_W::new(self) + ) -> U1_PLDA_PCIE_MPERSTN_W { + U1_PLDA_PCIE_MPERSTN_W::new(self, 0) } #[doc = "Bit 1 - u1_plda_pcie_pcie_ebuf_mode"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_pcie_ebuf_mode( &mut self, - ) -> U1_PLDA_PCIE_PCIE_EBUF_MODE_W { - U1_PLDA_PCIE_PCIE_EBUF_MODE_W::new(self) + ) -> U1_PLDA_PCIE_PCIE_EBUF_MODE_W { + U1_PLDA_PCIE_PCIE_EBUF_MODE_W::new(self, 1) } #[doc = "Bits 2:24 - u1_plda_pcie_pcie_phy_test_cfg"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_pcie_phy_test_cfg( &mut self, - ) -> U1_PLDA_PCIE_PCIE_PHY_TEST_CFG_W { - U1_PLDA_PCIE_PCIE_PHY_TEST_CFG_W::new(self) + ) -> U1_PLDA_PCIE_PCIE_PHY_TEST_CFG_W { + U1_PLDA_PCIE_PCIE_PHY_TEST_CFG_W::new(self, 2) } #[doc = "Bit 25 - u1_plda_pcie_pcie_rx_eq_training"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_pcie_rx_eq_training( &mut self, - ) -> U1_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W { - U1_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W::new(self) + ) -> U1_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W { + U1_PLDA_PCIE_PCIE_RX_EQ_TRAINING_W::new(self, 25) } #[doc = "Bit 26 - u1_plda_pcie_pcie_rxterm_en"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_pcie_rxterm_en( &mut self, - ) -> U1_PLDA_PCIE_PCIE_RXTERM_EN_W { - U1_PLDA_PCIE_PCIE_RXTERM_EN_W::new(self) + ) -> U1_PLDA_PCIE_PCIE_RXTERM_EN_W { + U1_PLDA_PCIE_PCIE_RXTERM_EN_W::new(self, 26) } #[doc = "Bit 27 - u1_plda_pcie_pcie_tx_oneszeros"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_pcie_tx_oneszeros( &mut self, - ) -> U1_PLDA_PCIE_PCIE_TX_ONESZEROS_W { - U1_PLDA_PCIE_PCIE_TX_ONESZEROS_W::new(self) + ) -> U1_PLDA_PCIE_PCIE_TX_ONESZEROS_W { + U1_PLDA_PCIE_PCIE_TX_ONESZEROS_W::new(self, 27) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg748.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg748.rs index 934c7e8..5219008 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg748.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg748.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pf0_offset` reader - u1_plda_pcie_pf0_offset"] pub type U1_PLDA_PCIE_PF0_OFFSET_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pf0_offset` writer - u1_plda_pcie_pf0_offset"] -pub type U1_PLDA_PCIE_PF0_OFFSET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; +pub type U1_PLDA_PCIE_PF0_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; impl R { #[doc = "Bits 0:19 - u1_plda_pcie_pf0_offset"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_pf0_offset( &mut self, - ) -> U1_PLDA_PCIE_PF0_OFFSET_W { - U1_PLDA_PCIE_PF0_OFFSET_W::new(self) + ) -> U1_PLDA_PCIE_PF0_OFFSET_W { + U1_PLDA_PCIE_PF0_OFFSET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg752.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg752.rs index dcf3eff..2aaea4c 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg752.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg752.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pf1_offset` reader - u1_plda_pcie_pf1_offset"] pub type U1_PLDA_PCIE_PF1_OFFSET_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pf1_offset` writer - u1_plda_pcie_pf1_offset"] -pub type U1_PLDA_PCIE_PF1_OFFSET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; +pub type U1_PLDA_PCIE_PF1_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; impl R { #[doc = "Bits 0:19 - u1_plda_pcie_pf1_offset"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_pf1_offset( &mut self, - ) -> U1_PLDA_PCIE_PF1_OFFSET_W { - U1_PLDA_PCIE_PF1_OFFSET_W::new(self) + ) -> U1_PLDA_PCIE_PF1_OFFSET_W { + U1_PLDA_PCIE_PF1_OFFSET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg756.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg756.rs index c723c87..0368fef 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg756.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg756.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pf2_offset` reader - u1_plda_pcie_pf2_offset"] pub type U1_PLDA_PCIE_PF2_OFFSET_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pf2_offset` writer - u1_plda_pcie_pf2_offset"] -pub type U1_PLDA_PCIE_PF2_OFFSET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; +pub type U1_PLDA_PCIE_PF2_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; impl R { #[doc = "Bits 0:19 - u1_plda_pcie_pf2_offset"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_pf2_offset( &mut self, - ) -> U1_PLDA_PCIE_PF2_OFFSET_W { - U1_PLDA_PCIE_PF2_OFFSET_W::new(self) + ) -> U1_PLDA_PCIE_PF2_OFFSET_W { + U1_PLDA_PCIE_PF2_OFFSET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg76.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg76.rs index 51aad11..6eb35c2 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg76.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg76.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg760.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg760.rs index d85e5b0..544aa4b 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg760.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg760.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pf3_offset` reader - u1_plda_pcie_pf3_offset"] pub type U1_PLDA_PCIE_PF3_OFFSET_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pf3_offset` writer - u1_plda_pcie_pf3_offset"] -pub type U1_PLDA_PCIE_PF3_OFFSET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; +pub type U1_PLDA_PCIE_PF3_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; #[doc = "Field `u1_plda_pcie_phy_mode` reader - u1_plda_pcie_phy_mode"] pub type U1_PLDA_PCIE_PHY_MODE_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_phy_mode` writer - u1_plda_pcie_phy_mode"] -pub type U1_PLDA_PCIE_PHY_MODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U1_PLDA_PCIE_PHY_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_plda_pcie_pl_clkrem_allow` reader - u1_plda_pcie_pl_clkrem_allow"] pub type U1_PLDA_PCIE_PL_CLKREM_ALLOW_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_pl_clkrem_allow` writer - u1_plda_pcie_pl_clkrem_allow"] -pub type U1_PLDA_PCIE_PL_CLKREM_ALLOW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_PL_CLKREM_ALLOW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_pl_clkreq_oen` reader - u1_plda_pcie_pl_clkreq_oen"] pub type U1_PLDA_PCIE_PL_CLKREQ_OEN_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_pl_equ_phase` reader - u1_plda_pcie_pl_equ_phase"] @@ -58,26 +58,30 @@ impl W { #[must_use] pub fn u1_plda_pcie_pf3_offset( &mut self, - ) -> U1_PLDA_PCIE_PF3_OFFSET_W { - U1_PLDA_PCIE_PF3_OFFSET_W::new(self) + ) -> U1_PLDA_PCIE_PF3_OFFSET_W { + U1_PLDA_PCIE_PF3_OFFSET_W::new(self, 0) } #[doc = "Bits 20:21 - u1_plda_pcie_phy_mode"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_phy_mode( &mut self, - ) -> U1_PLDA_PCIE_PHY_MODE_W { - U1_PLDA_PCIE_PHY_MODE_W::new(self) + ) -> U1_PLDA_PCIE_PHY_MODE_W { + U1_PLDA_PCIE_PHY_MODE_W::new(self, 20) } #[doc = "Bit 22 - u1_plda_pcie_pl_clkrem_allow"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_pl_clkrem_allow( &mut self, - ) -> U1_PLDA_PCIE_PL_CLKREM_ALLOW_W { - U1_PLDA_PCIE_PL_CLKREM_ALLOW_W::new(self) + ) -> U1_PLDA_PCIE_PL_CLKREM_ALLOW_W { + U1_PLDA_PCIE_PL_CLKREM_ALLOW_W::new(self, 22) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg764.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg764.rs index ac9e3f7..86b5eb5 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg764.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg764.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg768.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg768.rs index 04830e2..ff4f581 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg768.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg768.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pl_sideband_in_31_0` reader - u1_plda_pcie_pl_sideband_in_31_0"] pub type U1_PLDA_PCIE_PL_SIDEBAND_IN_31_0_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pl_sideband_in_31_0` writer - u1_plda_pcie_pl_sideband_in_31_0"] -pub type U1_PLDA_PCIE_PL_SIDEBAND_IN_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_PL_SIDEBAND_IN_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_pl_sideband_in_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_pl_sideband_in_31_0( &mut self, - ) -> U1_PLDA_PCIE_PL_SIDEBAND_IN_31_0_W { - U1_PLDA_PCIE_PL_SIDEBAND_IN_31_0_W::new(self) + ) -> U1_PLDA_PCIE_PL_SIDEBAND_IN_31_0_W { + U1_PLDA_PCIE_PL_SIDEBAND_IN_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg772.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg772.rs index 882a27a..3552f55 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg772.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg772.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pl_sideband_in_63_32` reader - u1_plda_pcie_pl_sideband_in_63_32"] pub type U1_PLDA_PCIE_PL_SIDEBAND_IN_63_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pl_sideband_in_63_32` writer - u1_plda_pcie_pl_sideband_in_63_32"] -pub type U1_PLDA_PCIE_PL_SIDEBAND_IN_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_PL_SIDEBAND_IN_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_pl_sideband_in_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_pl_sideband_in_63_32( &mut self, - ) -> U1_PLDA_PCIE_PL_SIDEBAND_IN_63_32_W { - U1_PLDA_PCIE_PL_SIDEBAND_IN_63_32_W::new(self) + ) -> U1_PLDA_PCIE_PL_SIDEBAND_IN_63_32_W { + U1_PLDA_PCIE_PL_SIDEBAND_IN_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg776.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg776.rs index f543076..8da58f1 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg776.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg776.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pl_sideband_out_31_0` reader - u1_plda_pcie_pl_sideband_out_31_0"] pub type U1_PLDA_PCIE_PL_SIDEBAND_OUT_31_0_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pl_sideband_out_31_0` writer - u1_plda_pcie_pl_sideband_out_31_0"] -pub type U1_PLDA_PCIE_PL_SIDEBAND_OUT_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_PL_SIDEBAND_OUT_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_pl_sideband_out_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_pl_sideband_out_31_0( &mut self, - ) -> U1_PLDA_PCIE_PL_SIDEBAND_OUT_31_0_W { - U1_PLDA_PCIE_PL_SIDEBAND_OUT_31_0_W::new(self) + ) -> U1_PLDA_PCIE_PL_SIDEBAND_OUT_31_0_W { + U1_PLDA_PCIE_PL_SIDEBAND_OUT_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg780.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg780.rs index c517118..c667cd4 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg780.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg780.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pl_sideband_out_63_32` reader - u1_plda_pcie_pl_sideband_out_63_32"] pub type U1_PLDA_PCIE_PL_SIDEBAND_OUT_63_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_pl_sideband_out_63_32` writer - u1_plda_pcie_pl_sideband_out_63_32"] -pub type U1_PLDA_PCIE_PL_SIDEBAND_OUT_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_PL_SIDEBAND_OUT_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_pl_sideband_out_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_pl_sideband_out_63_32( &mut self, - ) -> U1_PLDA_PCIE_PL_SIDEBAND_OUT_63_32_W { - U1_PLDA_PCIE_PL_SIDEBAND_OUT_63_32_W::new(self) + ) -> U1_PLDA_PCIE_PL_SIDEBAND_OUT_63_32_W { + U1_PLDA_PCIE_PL_SIDEBAND_OUT_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg784.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg784.rs index 881e651..7e6a043 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg784.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg784.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_pl_wake_in` reader - u1_plda_pcie_pl_wake_in"] pub type U1_PLDA_PCIE_PL_WAKE_IN_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_pl_wake_in` writer - u1_plda_pcie_pl_wake_in"] -pub type U1_PLDA_PCIE_PL_WAKE_IN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_PL_WAKE_IN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_pl_wake_oen` reader - u1_plda_pcie_pl_wake_oen"] pub type U1_PLDA_PCIE_PL_WAKE_OEN_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_rx_standby_o` reader - u1_plda_pcie_rx_standby_o"] @@ -33,10 +33,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_pl_wake_in( &mut self, - ) -> U1_PLDA_PCIE_PL_WAKE_IN_W { - U1_PLDA_PCIE_PL_WAKE_IN_W::new(self) + ) -> U1_PLDA_PCIE_PL_WAKE_IN_W { + U1_PLDA_PCIE_PL_WAKE_IN_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg788.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg788.rs index acb4c51..08151e7 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg788.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg788.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_in_31_0` reader - u1_plda_pcie_test_in_31_0"] pub type U1_PLDA_PCIE_TEST_IN_31_0_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_in_31_0` writer - u1_plda_pcie_test_in_31_0"] -pub type U1_PLDA_PCIE_TEST_IN_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_IN_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_in_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_in_31_0( &mut self, - ) -> U1_PLDA_PCIE_TEST_IN_31_0_W { - U1_PLDA_PCIE_TEST_IN_31_0_W::new(self) + ) -> U1_PLDA_PCIE_TEST_IN_31_0_W { + U1_PLDA_PCIE_TEST_IN_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg792.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg792.rs index 7ffb829..3c5c847 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg792.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg792.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_in_63_32` reader - u1_plda_pcie_test_in_63_32"] pub type U1_PLDA_PCIE_TEST_IN_63_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_in_63_32` writer - u1_plda_pcie_test_in_63_32"] -pub type U1_PLDA_PCIE_TEST_IN_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_IN_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_in_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_in_63_32( &mut self, - ) -> U1_PLDA_PCIE_TEST_IN_63_32_W { - U1_PLDA_PCIE_TEST_IN_63_32_W::new(self) + ) -> U1_PLDA_PCIE_TEST_IN_63_32_W { + U1_PLDA_PCIE_TEST_IN_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg796.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg796.rs index a713f23..4e2d314 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg796.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg796.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_31_0` reader - u1_plda_pcie_test_out_bridge_31_0"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_31_0_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_31_0` writer - u1_plda_pcie_test_out_bridge_31_0"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_31_0( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_31_0_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_31_0_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_31_0_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg8.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg8.rs index 5eca371..3aff8cd 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg8.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg8.rs @@ -9,7 +9,7 @@ pub type U0_CDN_USB_RX_RCV_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_self_test` reader - For software bist_test"] pub type U0_CDN_USB_SELF_TEST_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_self_test` writer - For software bist_test"] -pub type U0_CDN_USB_SELF_TEST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_SELF_TEST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_sessend` reader - u0_cdn_usb_sessend"] pub type U0_CDN_USB_SESSEND_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_sessvalid` reader - u0_cdn_usb_sessvalid"] @@ -25,8 +25,7 @@ pub type U0_CDN_USB_USBDEV_MAIN_POWER_OFF_READY_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_main_power_off_req` reader - u0_cdn_usb_usbdev_main_power_off_req"] pub type U0_CDN_USB_USBDEV_MAIN_POWER_OFF_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_main_power_off_req` writer - u0_cdn_usb_usbdev_main_power_off_req"] -pub type U0_CDN_USB_USBDEV_MAIN_POWER_OFF_REQ_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_USBDEV_MAIN_POWER_OFF_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_usbdev_main_power_on_ready` reader - u0_cdn_usb_usbdev_main_power_on_ready"] pub type U0_CDN_USB_USBDEV_MAIN_POWER_ON_READY_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_main_power_on_req` reader - u0_cdn_usb_usbdev_main_power_on_req"] @@ -34,8 +33,7 @@ pub type U0_CDN_USB_USBDEV_MAIN_POWER_ON_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_main_power_on_valid` reader - u0_cdn_usb_usbdev_main_power_on_valid"] pub type U0_CDN_USB_USBDEV_MAIN_POWER_ON_VALID_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_main_power_on_valid` writer - u0_cdn_usb_usbdev_main_power_on_valid"] -pub type U0_CDN_USB_USBDEV_MAIN_POWER_ON_VALID_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_USBDEV_MAIN_POWER_ON_VALID_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_usbdev_power_off_ack` reader - u0_cdn_usb_usbdev_power_off_ack"] pub type U0_CDN_USB_USBDEV_POWER_OFF_ACK_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_power_off_ready` reader - u0_cdn_usb_usbdev_power_off_ready"] @@ -43,7 +41,7 @@ pub type U0_CDN_USB_USBDEV_POWER_OFF_READY_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_power_off_req` reader - u0_cdn_usb_usbdev_power_off_req"] pub type U0_CDN_USB_USBDEV_POWER_OFF_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_power_off_req` writer - u0_cdn_usb_usbdev_power_off_req"] -pub type U0_CDN_USB_USBDEV_POWER_OFF_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_USBDEV_POWER_OFF_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_usbdev_power_on_ready` reader - u0_cdn_usb_usbdev_power_on_ready"] pub type U0_CDN_USB_USBDEV_POWER_ON_READY_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_power_on_req` reader - u0_cdn_usb_usbdev_power_on_req"] @@ -51,19 +49,19 @@ pub type U0_CDN_USB_USBDEV_POWER_ON_REQ_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_power_on_valid` reader - u0_cdn_usb_usbdev_power_on_valid"] pub type U0_CDN_USB_USBDEV_POWER_ON_VALID_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_usbdev_power_on_valid` writer - u0_cdn_usb_usbdev_power_on_valid"] -pub type U0_CDN_USB_USBDEV_POWER_ON_VALID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_USBDEV_POWER_ON_VALID_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_dmpulldown_sit` reader - u0_cdn_usb_utmi_dmpulldown_sit"] pub type U0_CDN_USB_UTMI_DMPULLDOWN_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_dmpulldown_sit` writer - u0_cdn_usb_utmi_dmpulldown_sit"] -pub type U0_CDN_USB_UTMI_DMPULLDOWN_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_DMPULLDOWN_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_dppulldown_sit` reader - u0_cdn_usb_utmi_dppulldown_sit"] pub type U0_CDN_USB_UTMI_DPPULLDOWN_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_dppulldown_sit` writer - u0_cdn_usb_utmi_dppulldown_sit"] -pub type U0_CDN_USB_UTMI_DPPULLDOWN_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_DPPULLDOWN_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_fslsserialmode_sit` reader - u0_cdn_usb_utmi_fslsserialmode_sit"] pub type U0_CDN_USB_UTMI_FSLSSERIALMODE_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_fslsserialmode_sit` writer - u0_cdn_usb_utmi_fslsserialmode_sit"] -pub type U0_CDN_USB_UTMI_FSLSSERIALMODE_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_FSLSSERIALMODE_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_hostdisconnect_sit` reader - u0_cdn_usb_utmi_hostdisconnect_sit"] pub type U0_CDN_USB_UTMI_HOSTDISCONNECT_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_iddig_sit` reader - u0_cdn_usb_utmi_iddig_sit"] @@ -71,13 +69,13 @@ pub type U0_CDN_USB_UTMI_IDDIG_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_idpullup_sit` reader - u0_cdn_usb_utmi_idpullup_sit"] pub type U0_CDN_USB_UTMI_IDPULLUP_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_idpullup_sit` writer - u0_cdn_usb_utmi_idpullup_sit"] -pub type U0_CDN_USB_UTMI_IDPULLUP_SIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDN_USB_UTMI_IDPULLUP_SIT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdn_usb_utmi_linestate_sit` reader - u0_cdn_usb_utmi_linestate_sit"] pub type U0_CDN_USB_UTMI_LINESTATE_SIT_R = crate::FieldReader; #[doc = "Field `u0_cdn_usb_utmi_opmode_sit` reader - u0_cdn_usb_utmi_opmode_sit"] pub type U0_CDN_USB_UTMI_OPMODE_SIT_R = crate::FieldReader; #[doc = "Field `u0_cdn_usb_utmi_opmode_sit` writer - u0_cdn_usb_utmi_opmode_sit"] -pub type U0_CDN_USB_UTMI_OPMODE_SIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDN_USB_UTMI_OPMODE_SIT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdn_usb_utmi_rxactive_sit` reader - u0_cdn_usb_utmi_rxactive_sit"] pub type U0_CDN_USB_UTMI_RXACTIVE_SIT_R = crate::BitReader; #[doc = "Field `u0_cdn_usb_utmi_rxerror_sit` reader - u0_cdn_usb_utmi_rxerror_sit"] @@ -242,84 +240,86 @@ impl W { #[doc = "Bit 2 - For software bist_test"] #[inline(always)] #[must_use] - pub fn u0_cdn_usb_self_test( - &mut self, - ) -> U0_CDN_USB_SELF_TEST_W { - U0_CDN_USB_SELF_TEST_W::new(self) + pub fn u0_cdn_usb_self_test(&mut self) -> U0_CDN_USB_SELF_TEST_W { + U0_CDN_USB_SELF_TEST_W::new(self, 2) } #[doc = "Bit 9 - u0_cdn_usb_usbdev_main_power_off_req"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_usbdev_main_power_off_req( &mut self, - ) -> U0_CDN_USB_USBDEV_MAIN_POWER_OFF_REQ_W { - U0_CDN_USB_USBDEV_MAIN_POWER_OFF_REQ_W::new(self) + ) -> U0_CDN_USB_USBDEV_MAIN_POWER_OFF_REQ_W { + U0_CDN_USB_USBDEV_MAIN_POWER_OFF_REQ_W::new(self, 9) } #[doc = "Bit 12 - u0_cdn_usb_usbdev_main_power_on_valid"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_usbdev_main_power_on_valid( &mut self, - ) -> U0_CDN_USB_USBDEV_MAIN_POWER_ON_VALID_W { - U0_CDN_USB_USBDEV_MAIN_POWER_ON_VALID_W::new(self) + ) -> U0_CDN_USB_USBDEV_MAIN_POWER_ON_VALID_W { + U0_CDN_USB_USBDEV_MAIN_POWER_ON_VALID_W::new(self, 12) } #[doc = "Bit 15 - u0_cdn_usb_usbdev_power_off_req"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_usbdev_power_off_req( &mut self, - ) -> U0_CDN_USB_USBDEV_POWER_OFF_REQ_W { - U0_CDN_USB_USBDEV_POWER_OFF_REQ_W::new(self) + ) -> U0_CDN_USB_USBDEV_POWER_OFF_REQ_W { + U0_CDN_USB_USBDEV_POWER_OFF_REQ_W::new(self, 15) } #[doc = "Bit 18 - u0_cdn_usb_usbdev_power_on_valid"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_usbdev_power_on_valid( &mut self, - ) -> U0_CDN_USB_USBDEV_POWER_ON_VALID_W { - U0_CDN_USB_USBDEV_POWER_ON_VALID_W::new(self) + ) -> U0_CDN_USB_USBDEV_POWER_ON_VALID_W { + U0_CDN_USB_USBDEV_POWER_ON_VALID_W::new(self, 18) } #[doc = "Bit 19 - u0_cdn_usb_utmi_dmpulldown_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_dmpulldown_sit( &mut self, - ) -> U0_CDN_USB_UTMI_DMPULLDOWN_SIT_W { - U0_CDN_USB_UTMI_DMPULLDOWN_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_DMPULLDOWN_SIT_W { + U0_CDN_USB_UTMI_DMPULLDOWN_SIT_W::new(self, 19) } #[doc = "Bit 20 - u0_cdn_usb_utmi_dppulldown_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_dppulldown_sit( &mut self, - ) -> U0_CDN_USB_UTMI_DPPULLDOWN_SIT_W { - U0_CDN_USB_UTMI_DPPULLDOWN_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_DPPULLDOWN_SIT_W { + U0_CDN_USB_UTMI_DPPULLDOWN_SIT_W::new(self, 20) } #[doc = "Bit 21 - u0_cdn_usb_utmi_fslsserialmode_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_fslsserialmode_sit( &mut self, - ) -> U0_CDN_USB_UTMI_FSLSSERIALMODE_SIT_W { - U0_CDN_USB_UTMI_FSLSSERIALMODE_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_FSLSSERIALMODE_SIT_W { + U0_CDN_USB_UTMI_FSLSSERIALMODE_SIT_W::new(self, 21) } #[doc = "Bit 24 - u0_cdn_usb_utmi_idpullup_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_idpullup_sit( &mut self, - ) -> U0_CDN_USB_UTMI_IDPULLUP_SIT_W { - U0_CDN_USB_UTMI_IDPULLUP_SIT_W::new(self) + ) -> U0_CDN_USB_UTMI_IDPULLUP_SIT_W { + U0_CDN_USB_UTMI_IDPULLUP_SIT_W::new(self, 24) } #[doc = "Bits 27:28 - u0_cdn_usb_utmi_opmode_sit"] #[inline(always)] #[must_use] pub fn u0_cdn_usb_utmi_opmode_sit( &mut self, - ) -> U0_CDN_USB_UTMI_OPMODE_SIT_W { - U0_CDN_USB_UTMI_OPMODE_SIT_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_CDN_USB_UTMI_OPMODE_SIT_W { + U0_CDN_USB_UTMI_OPMODE_SIT_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg80.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg80.rs index 6cfbbe4..830be3f 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg80.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg80.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg800.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg800.rs index 563a0ff..13c21d2 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg800.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg800.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_63_32` reader - u1_plda_pcie_test_out_bridge_63_32"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_63_32_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_63_32` writer - u1_plda_pcie_test_out_bridge_63_32"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_63_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_63_32_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_63_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_63_32( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_63_32_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_63_32_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_63_32_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_63_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg804.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg804.rs index 728e5a1..6a91287 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg804.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg804.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_95_64` reader - u1_plda_pcie_test_out_bridge_95_64"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_95_64_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_95_64` writer - u1_plda_pcie_test_out_bridge_95_64"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_95_64_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_95_64_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_95_64"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_95_64( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_95_64_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_95_64_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_95_64_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_95_64_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg808.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg808.rs index 5a64cbc..999071b 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg808.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg808.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_127_96` reader - u1_plda_pcie_test_out_bridge_127_96"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_127_96_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_127_96` writer - u1_plda_pcie_test_out_bridge_127_96"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_127_96_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_127_96_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_127_96"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_127_96( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_127_96_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_127_96_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_127_96_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_127_96_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg812.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg812.rs index 16b4fbc..d046c29 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg812.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg812.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_159_128` reader - u1_plda_pcie_test_out_bridge_159_128"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_159_128_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_159_128` writer - u1_plda_pcie_test_out_bridge_159_128"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_159_128_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_159_128_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_159_128"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_159_128( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_159_128_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_159_128_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_159_128_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_159_128_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg816.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg816.rs index 7d7894a..5bbb50e 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg816.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg816.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_191_160` reader - u1_plda_pcie_test_out_bridge_191_160"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_191_160_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_191_160` writer - u1_plda_pcie_test_out_bridge_191_160"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_191_160_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_191_160_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_191_160"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_191_160( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_191_160_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_191_160_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_191_160_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_191_160_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg820.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg820.rs index 9a9f6a8..c11e306 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg820.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg820.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_223_192` reader - u1_plda_pcie_test_out_bridge_223_192"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_223_192_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_223_192` writer - u1_plda_pcie_test_out_bridge_223_192"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_223_192_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_223_192_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_223_192"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_223_192( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_223_192_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_223_192_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_223_192_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_223_192_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg824.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg824.rs index 6f10dd4..ba51067 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg824.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg824.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_255_224` reader - u1_plda_pcie_test_out_bridge_255_224"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_255_224_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_255_224` writer - u1_plda_pcie_test_out_bridge_255_224"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_255_224_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_255_224_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_255_224"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_255_224( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_255_224_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_255_224_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_255_224_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_255_224_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg828.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg828.rs index 9110f51..622aa1c 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg828.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg828.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_287_256` reader - u1_plda_pcie_test_out_bridge_287_256"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_287_256_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_287_256` writer - u1_plda_pcie_test_out_bridge_287_256"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_287_256_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_287_256_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_287_256"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_287_256( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_287_256_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_287_256_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_287_256_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_287_256_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg832.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg832.rs index e15a256..f7c65d6 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg832.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg832.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_319_288` reader - u1_plda_pcie_test_out_bridge_319_288"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_319_288_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_319_288` writer - u1_plda_pcie_test_out_bridge_319_288"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_319_288_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_319_288_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_319_288"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_319_288( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_319_288_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_319_288_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_319_288_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_319_288_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg836.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg836.rs index 99401ff..fb792da 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg836.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg836.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_351_320` reader - u1_plda_pcie_test_out_bridge_351_320"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_351_320_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_351_320` writer - u1_plda_pcie_test_out_bridge_351_320"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_351_320_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_351_320_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_351_320"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_351_320( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_351_320_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_351_320_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_351_320_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_351_320_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg84.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg84.rs index 52520dc..8658803 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg84.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg84.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg840.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg840.rs index c2a4eb8..842a3bf 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg840.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg840.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_383_352` reader - u1_plda_pcie_test_out_bridge_383_352"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_383_352_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_383_352` writer - u1_plda_pcie_test_out_bridge_383_352"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_383_352_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_383_352_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_383_352"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_383_352( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_383_352_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_383_352_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_383_352_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_383_352_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg844.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg844.rs index ad2290b..4ec4202 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg844.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg844.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_415_384` reader - u1_plda_pcie_test_out_bridge_415_384"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_415_384_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_415_384` writer - u1_plda_pcie_test_out_bridge_415_384"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_415_384_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_415_384_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_415_384"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_415_384( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_415_384_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_415_384_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_415_384_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_415_384_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg848.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg848.rs index 599a9b0..fa8f59a 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg848.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg848.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_447_416` reader - u1_plda_pcie_test_out_bridge_447_416"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_447_416_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_447_416` writer - u1_plda_pcie_test_out_bridge_447_416"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_447_416_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_447_416_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_447_416"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_447_416( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_447_416_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_447_416_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_447_416_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_447_416_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg852.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg852.rs index 7fa112f..323ccd1 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg852.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg852.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_479_448` reader - u1_plda_pcie_test_out_bridge_479_448"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_479_448_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_479_448` writer - u1_plda_pcie_test_out_bridge_479_448"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_479_448_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_479_448_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_479_448"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_479_448( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_479_448_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_479_448_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_479_448_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_479_448_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg856.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg856.rs index 79732b0..bb9f9c8 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg856.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg856.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_out_bridge_511_480` reader - u1_plda_pcie_test_out_bridge_511_480"] pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_511_480_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_out_bridge_511_480` writer - u1_plda_pcie_test_out_bridge_511_480"] -pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_511_480_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U1_PLDA_PCIE_TEST_OUT_BRIDGE_511_480_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u1_plda_pcie_test_out_bridge_511_480"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_out_bridge_511_480( &mut self, - ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_511_480_W { - U1_PLDA_PCIE_TEST_OUT_BRIDGE_511_480_W::new(self) + ) -> U1_PLDA_PCIE_TEST_OUT_BRIDGE_511_480_W { + U1_PLDA_PCIE_TEST_OUT_BRIDGE_511_480_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg860.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg860.rs index c380594..683947b 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg860.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg860.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg864.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg864.rs index 757638f..8a2f015 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg864.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg864.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg868.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg868.rs index a8d630d..fb6aeb0 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg868.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg868.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg872.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg872.rs index 2329ebe..bd4f69d 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg872.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg872.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg876.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg876.rs index 66c0517..ceb690c 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg876.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg876.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg88.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg88.rs index 0a65c73..46873db 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg88.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg88.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg880.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg880.rs index 63bbb42..c1f6a05 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg880.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg880.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg884.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg884.rs index b4297a5..93d4bed 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg884.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg884.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg888.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg888.rs index 4b879f4..bb30140 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg888.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg888.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg892.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg892.rs index 19f1f61..4b35fbb 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg892.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg892.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg896.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg896.rs index 47a7e79..4029ccf 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg896.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg896.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg900.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg900.rs index 6ebdb5b..31fb9ef 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg900.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg900.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg904.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg904.rs index 981fe96..578f91f 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg904.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg904.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg908.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg908.rs index 443d43c..32b5e7f 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg908.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg908.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg912.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg912.rs index d12bb2b..2727f3a 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg912.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg912.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg916.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg916.rs index 325b174..37ac21c 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg916.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg916.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg92.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg92.rs index 2872a53..b4b2cea 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg92.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg92.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg920.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg920.rs index e58f2b8..7309fd3 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg920.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg920.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg924.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg924.rs index 3980f06..d09dbb2 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg924.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg924.rs @@ -5,12 +5,11 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_test_sel` reader - u1_plda_pcie_test_sel"] pub type U1_PLDA_PCIE_TEST_SEL_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_test_sel` writer - u1_plda_pcie_test_sel"] -pub type U1_PLDA_PCIE_TEST_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type U1_PLDA_PCIE_TEST_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `u1_plda_pcie_tl_clock_freq` reader - u1_plda_pcie_tl_clock_freq"] pub type U1_PLDA_PCIE_TL_CLOCK_FREQ_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_tl_clock_freq` writer - u1_plda_pcie_tl_clock_freq"] -pub type U1_PLDA_PCIE_TL_CLOCK_FREQ_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 22, O, u32>; +pub type U1_PLDA_PCIE_TL_CLOCK_FREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; impl R { #[doc = "Bits 0:3 - u1_plda_pcie_test_sel"] #[inline(always)] @@ -29,18 +28,22 @@ impl W { #[must_use] pub fn u1_plda_pcie_test_sel( &mut self, - ) -> U1_PLDA_PCIE_TEST_SEL_W { - U1_PLDA_PCIE_TEST_SEL_W::new(self) + ) -> U1_PLDA_PCIE_TEST_SEL_W { + U1_PLDA_PCIE_TEST_SEL_W::new(self, 0) } #[doc = "Bits 4:25 - u1_plda_pcie_tl_clock_freq"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_tl_clock_freq( &mut self, - ) -> U1_PLDA_PCIE_TL_CLOCK_FREQ_W { - U1_PLDA_PCIE_TL_CLOCK_FREQ_W::new(self) + ) -> U1_PLDA_PCIE_TL_CLOCK_FREQ_W { + U1_PLDA_PCIE_TL_CLOCK_FREQ_W::new(self, 4) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg928.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg928.rs index 60d4b3d..aeec659 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg928.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg928.rs @@ -7,8 +7,7 @@ pub type U1_PLDA_PCIE_TL_CTRL_HOTPLUG_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_tl_report_hotplug` reader - u1_plda_pcie_tl_report_hotplug"] pub type U1_PLDA_PCIE_TL_REPORT_HOTPLUG_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_tl_report_hotplug` writer - u1_plda_pcie_tl_report_hotplug"] -pub type U1_PLDA_PCIE_TL_REPORT_HOTPLUG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 16, O, u16>; +pub type U1_PLDA_PCIE_TL_REPORT_HOTPLUG_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - u1_plda_pcie_tl_ctrl_hotplug"] #[inline(always)] @@ -27,10 +26,14 @@ impl W { #[must_use] pub fn u1_plda_pcie_tl_report_hotplug( &mut self, - ) -> U1_PLDA_PCIE_TL_REPORT_HOTPLUG_W { - U1_PLDA_PCIE_TL_REPORT_HOTPLUG_W::new(self) + ) -> U1_PLDA_PCIE_TL_REPORT_HOTPLUG_W { + U1_PLDA_PCIE_TL_REPORT_HOTPLUG_W::new(self, 16) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg932.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg932.rs index 852dcd8..277ae10 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg932.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg932.rs @@ -5,29 +5,29 @@ pub type W = crate::W; #[doc = "Field `u1_plda_pcie_tx_pattern` reader - u1_plda_pcie_tx_pattern"] pub type U1_PLDA_PCIE_TX_PATTERN_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_tx_pattern` writer - u1_plda_pcie_tx_pattern"] -pub type U1_PLDA_PCIE_TX_PATTERN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U1_PLDA_PCIE_TX_PATTERN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_plda_pcie_usb3_bus_width` reader - u1_plda_pcie_usb3_bus_width"] pub type U1_PLDA_PCIE_USB3_BUS_WIDTH_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_usb3_bus_width` writer - u1_plda_pcie_usb3_bus_width"] -pub type U1_PLDA_PCIE_USB3_BUS_WIDTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U1_PLDA_PCIE_USB3_BUS_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_plda_pcie_usb3_phy_enable` reader - u1_plda_pcie_usb3_phy_enable"] pub type U1_PLDA_PCIE_USB3_PHY_ENABLE_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_usb3_phy_enable` writer - u1_plda_pcie_usb3_phy_enable"] -pub type U1_PLDA_PCIE_USB3_PHY_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_USB3_PHY_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_usb3_rate` reader - u1_plda_pcie_usb3_rate"] pub type U1_PLDA_PCIE_USB3_RATE_R = crate::FieldReader; #[doc = "Field `u1_plda_pcie_usb3_rate` writer - u1_plda_pcie_usb3_rate"] -pub type U1_PLDA_PCIE_USB3_RATE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U1_PLDA_PCIE_USB3_RATE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_plda_pcie_usb3_rx_standby` reader - u1_plda_pcie_usb3_rx_standby"] pub type U1_PLDA_PCIE_USB3_RX_STANDBY_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_usb3_rx_standby` writer - u1_plda_pcie_usb3_rx_standby"] -pub type U1_PLDA_PCIE_USB3_RX_STANDBY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_USB3_RX_STANDBY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_xwdecerr` reader - u1_plda_pcie_xwdecerr"] pub type U1_PLDA_PCIE_XWDECERR_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_xwerrclr` reader - u1_plda_pcie_xwerrclr"] pub type U1_PLDA_PCIE_XWERRCLR_R = crate::BitReader; #[doc = "Field `u1_plda_pcie_xwerrclr` writer - u1_plda_pcie_xwerrclr"] -pub type U1_PLDA_PCIE_XWERRCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_PLDA_PCIE_XWERRCLR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_plda_pcie_xwslverr` reader - u1_plda_pcie_xwslverr"] pub type U1_PLDA_PCIE_XWSLVERR_R = crate::BitReader; impl R { @@ -78,50 +78,54 @@ impl W { #[must_use] pub fn u1_plda_pcie_tx_pattern( &mut self, - ) -> U1_PLDA_PCIE_TX_PATTERN_W { - U1_PLDA_PCIE_TX_PATTERN_W::new(self) + ) -> U1_PLDA_PCIE_TX_PATTERN_W { + U1_PLDA_PCIE_TX_PATTERN_W::new(self, 0) } #[doc = "Bits 2:3 - u1_plda_pcie_usb3_bus_width"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_usb3_bus_width( &mut self, - ) -> U1_PLDA_PCIE_USB3_BUS_WIDTH_W { - U1_PLDA_PCIE_USB3_BUS_WIDTH_W::new(self) + ) -> U1_PLDA_PCIE_USB3_BUS_WIDTH_W { + U1_PLDA_PCIE_USB3_BUS_WIDTH_W::new(self, 2) } #[doc = "Bit 4 - u1_plda_pcie_usb3_phy_enable"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_usb3_phy_enable( &mut self, - ) -> U1_PLDA_PCIE_USB3_PHY_ENABLE_W { - U1_PLDA_PCIE_USB3_PHY_ENABLE_W::new(self) + ) -> U1_PLDA_PCIE_USB3_PHY_ENABLE_W { + U1_PLDA_PCIE_USB3_PHY_ENABLE_W::new(self, 4) } #[doc = "Bits 5:6 - u1_plda_pcie_usb3_rate"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_usb3_rate( &mut self, - ) -> U1_PLDA_PCIE_USB3_RATE_W { - U1_PLDA_PCIE_USB3_RATE_W::new(self) + ) -> U1_PLDA_PCIE_USB3_RATE_W { + U1_PLDA_PCIE_USB3_RATE_W::new(self, 5) } #[doc = "Bit 7 - u1_plda_pcie_usb3_rx_standby"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_usb3_rx_standby( &mut self, - ) -> U1_PLDA_PCIE_USB3_RX_STANDBY_W { - U1_PLDA_PCIE_USB3_RX_STANDBY_W::new(self) + ) -> U1_PLDA_PCIE_USB3_RX_STANDBY_W { + U1_PLDA_PCIE_USB3_RX_STANDBY_W::new(self, 7) } #[doc = "Bit 9 - u1_plda_pcie_xwerrclr"] #[inline(always)] #[must_use] pub fn u1_plda_pcie_xwerrclr( &mut self, - ) -> U1_PLDA_PCIE_XWERRCLR_W { - U1_PLDA_PCIE_XWERRCLR_W::new(self) + ) -> U1_PLDA_PCIE_XWERRCLR_W { + U1_PLDA_PCIE_XWERRCLR_W::new(self, 9) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg96.rs b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg96.rs index 705affa..aec28ef 100644 --- a/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg96.rs +++ b/jh7110-vf2-13b-pac/src/stg_syscon/stg_sysconsaif_syscfg96.rs @@ -14,7 +14,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg.rs b/jh7110-vf2-13b-pac/src/stgcrg.rs index f689ce7..52b9cf6 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg.rs @@ -1,228 +1,354 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + clk_hifi4_core: CLK_HIFI4_CORE, + clk_usb_apb: CLK_USB_APB, + clk_usb_utmi_apb: CLK_USB_UTMI_APB, + clk_usb_axi: CLK_USB_AXI, + clk_usb_ipm: CLK_USB_IPM, + clk_usb_stb: CLK_USB_STB, + clk_usb_app125: CLK_USB_APP125, + clk_usb_refclk: CLK_USB_REFCLK, + clk_u0_pcie_axi_mst0: CLK_U0_PCIE_AXI_MST0, + clk_u0_pcie_apb: CLK_U0_PCIE_APB, + clk_u0_pcie_tl: CLK_U0_PCIE_TL, + clk_u1_pcie_axi_mst0: CLK_U1_PCIE_AXI_MST0, + clk_u1_pcie_apb: CLK_U1_PCIE_APB, + clk_u1_pcie_tl: CLK_U1_PCIE_TL, + clk_pcie01_slv_dec_main: CLK_PCIE01_SLV_DEC_MAIN, + clk_sec_hclk: CLK_SEC_HCLK, + clk_sec_misc_ahb: CLK_SEC_MISC_AHB, + clk_stg_mtrx_group0_main: CLK_STG_MTRX_GROUP0_MAIN, + clk_stg_mtrx_group0_bus: CLK_STG_MTRX_GROUP0_BUS, + clk_stg_mtrx_group0_stg: CLK_STG_MTRX_GROUP0_STG, + clk_stg_mtrx_group1_main: CLK_STG_MTRX_GROUP1_MAIN, + clk_stg_mtrx_group1_bus: CLK_STG_MTRX_GROUP1_BUS, + clk_stg_mtrx_group1_stg: CLK_STG_MTRX_GROUP1_STG, + clk_stg_mtrx_group1_hifi: CLK_STG_MTRX_GROUP1_HIFI, + clk_e2_rtc: CLK_E2_RTC, + clk_e2_core: CLK_E2_CORE, + clk_e2_dbg: CLK_E2_DBG, + clk_dma_axi: CLK_DMA_AXI, + clk_dma_ahb: CLK_DMA_AHB, + soft_rst_addr_sel: SOFT_RST_ADDR_SEL, + stgcrg_rst_stat: STGCRG_RST_STAT, +} +impl RegisterBlock { #[doc = "0x00 - Clock HIFI4 Core"] - pub clk_hifi4_core: CLK_HIFI4_CORE, + #[inline(always)] + pub const fn clk_hifi4_core(&self) -> &CLK_HIFI4_CORE { + &self.clk_hifi4_core + } #[doc = "0x04 - Clock USB APB"] - pub clk_usb_apb: CLK_USB_APB, + #[inline(always)] + pub const fn clk_usb_apb(&self) -> &CLK_USB_APB { + &self.clk_usb_apb + } #[doc = "0x08 - Clock USB UTMI APB"] - pub clk_usb_utmi_apb: CLK_USB_UTMI_APB, + #[inline(always)] + pub const fn clk_usb_utmi_apb(&self) -> &CLK_USB_UTMI_APB { + &self.clk_usb_utmi_apb + } #[doc = "0x0c - Clock USB AXI"] - pub clk_usb_axi: CLK_USB_AXI, + #[inline(always)] + pub const fn clk_usb_axi(&self) -> &CLK_USB_AXI { + &self.clk_usb_axi + } #[doc = "0x10 - Clock USB AXI"] - pub clk_usb_ipm: CLK_USB_IPM, + #[inline(always)] + pub const fn clk_usb_ipm(&self) -> &CLK_USB_IPM { + &self.clk_usb_ipm + } #[doc = "0x14 - Clock USB STB"] - pub clk_usb_stb: CLK_USB_STB, + #[inline(always)] + pub const fn clk_usb_stb(&self) -> &CLK_USB_STB { + &self.clk_usb_stb + } #[doc = "0x18 - Clock USB APP 125"] - pub clk_usb_app125: CLK_USB_APP125, + #[inline(always)] + pub const fn clk_usb_app125(&self) -> &CLK_USB_APP125 { + &self.clk_usb_app125 + } #[doc = "0x1c - Clock USB Reference Clock"] - pub clk_usb_refclk: CLK_USB_REFCLK, + #[inline(always)] + pub const fn clk_usb_refclk(&self) -> &CLK_USB_REFCLK { + &self.clk_usb_refclk + } #[doc = "0x20 - U0 Clock PCIe AXI MST 0"] - pub clk_u0_pcie_axi_mst0: CLK_U0_PCIE_AXI_MST0, + #[inline(always)] + pub const fn clk_u0_pcie_axi_mst0(&self) -> &CLK_U0_PCIE_AXI_MST0 { + &self.clk_u0_pcie_axi_mst0 + } #[doc = "0x24 - U0 Clock PCIe APB"] - pub clk_u0_pcie_apb: CLK_U0_PCIE_APB, + #[inline(always)] + pub const fn clk_u0_pcie_apb(&self) -> &CLK_U0_PCIE_APB { + &self.clk_u0_pcie_apb + } #[doc = "0x28 - U0 Clock PCIe TL"] - pub clk_u0_pcie_tl: CLK_U0_PCIE_TL, + #[inline(always)] + pub const fn clk_u0_pcie_tl(&self) -> &CLK_U0_PCIE_TL { + &self.clk_u0_pcie_tl + } #[doc = "0x2c - U1 Clock PCIe AXI MST 0"] - pub clk_u1_pcie_axi_mst0: CLK_U1_PCIE_AXI_MST0, + #[inline(always)] + pub const fn clk_u1_pcie_axi_mst0(&self) -> &CLK_U1_PCIE_AXI_MST0 { + &self.clk_u1_pcie_axi_mst0 + } #[doc = "0x30 - U1 Clock PCIe APB"] - pub clk_u1_pcie_apb: CLK_U1_PCIE_APB, + #[inline(always)] + pub const fn clk_u1_pcie_apb(&self) -> &CLK_U1_PCIE_APB { + &self.clk_u1_pcie_apb + } #[doc = "0x34 - U1 Clock PCIe TL"] - pub clk_u1_pcie_tl: CLK_U1_PCIE_TL, + #[inline(always)] + pub const fn clk_u1_pcie_tl(&self) -> &CLK_U1_PCIE_TL { + &self.clk_u1_pcie_tl + } #[doc = "0x38 - Clock PCIe 01 SLV DEC Main"] - pub clk_pcie01_slv_dec_main: CLK_PCIE01_SLV_DEC_MAIN, + #[inline(always)] + pub const fn clk_pcie01_slv_dec_main(&self) -> &CLK_PCIE01_SLV_DEC_MAIN { + &self.clk_pcie01_slv_dec_main + } #[doc = "0x3c - Clock Security HCLK"] - pub clk_sec_hclk: CLK_SEC_HCLK, + #[inline(always)] + pub const fn clk_sec_hclk(&self) -> &CLK_SEC_HCLK { + &self.clk_sec_hclk + } #[doc = "0x40 - Clock Security Miscellaneous AHB"] - pub clk_sec_misc_ahb: CLK_SEC_MISC_AHB, + #[inline(always)] + pub const fn clk_sec_misc_ahb(&self) -> &CLK_SEC_MISC_AHB { + &self.clk_sec_misc_ahb + } #[doc = "0x44 - Clock STG MTRX Group 0 Main"] - pub clk_stg_mtrx_group0_main: CLK_STG_MTRX_GROUP0_MAIN, + #[inline(always)] + pub const fn clk_stg_mtrx_group0_main(&self) -> &CLK_STG_MTRX_GROUP0_MAIN { + &self.clk_stg_mtrx_group0_main + } #[doc = "0x48 - Clock STG MTRX Group 0 Bus"] - pub clk_stg_mtrx_group0_bus: CLK_STG_MTRX_GROUP0_BUS, + #[inline(always)] + pub const fn clk_stg_mtrx_group0_bus(&self) -> &CLK_STG_MTRX_GROUP0_BUS { + &self.clk_stg_mtrx_group0_bus + } #[doc = "0x4c - Clock STG MTRX Group 0 STG"] - pub clk_stg_mtrx_group0_stg: CLK_STG_MTRX_GROUP0_STG, + #[inline(always)] + pub const fn clk_stg_mtrx_group0_stg(&self) -> &CLK_STG_MTRX_GROUP0_STG { + &self.clk_stg_mtrx_group0_stg + } #[doc = "0x50 - Clock STG MTRX Group 1 Main"] - pub clk_stg_mtrx_group1_main: CLK_STG_MTRX_GROUP1_MAIN, + #[inline(always)] + pub const fn clk_stg_mtrx_group1_main(&self) -> &CLK_STG_MTRX_GROUP1_MAIN { + &self.clk_stg_mtrx_group1_main + } #[doc = "0x54 - Clock STG MTRX Group 1 Bus"] - pub clk_stg_mtrx_group1_bus: CLK_STG_MTRX_GROUP1_BUS, + #[inline(always)] + pub const fn clk_stg_mtrx_group1_bus(&self) -> &CLK_STG_MTRX_GROUP1_BUS { + &self.clk_stg_mtrx_group1_bus + } #[doc = "0x58 - Clock STG MTRX Group 1 STG"] - pub clk_stg_mtrx_group1_stg: CLK_STG_MTRX_GROUP1_STG, + #[inline(always)] + pub const fn clk_stg_mtrx_group1_stg(&self) -> &CLK_STG_MTRX_GROUP1_STG { + &self.clk_stg_mtrx_group1_stg + } #[doc = "0x5c - Clock STG MTRX Group 1 HIFI"] - pub clk_stg_mtrx_group1_hifi: CLK_STG_MTRX_GROUP1_HIFI, + #[inline(always)] + pub const fn clk_stg_mtrx_group1_hifi(&self) -> &CLK_STG_MTRX_GROUP1_HIFI { + &self.clk_stg_mtrx_group1_hifi + } #[doc = "0x60 - Clock E2 RTC"] - pub clk_e2_rtc: CLK_E2_RTC, + #[inline(always)] + pub const fn clk_e2_rtc(&self) -> &CLK_E2_RTC { + &self.clk_e2_rtc + } #[doc = "0x64 - Clock E2 Core"] - pub clk_e2_core: CLK_E2_CORE, + #[inline(always)] + pub const fn clk_e2_core(&self) -> &CLK_E2_CORE { + &self.clk_e2_core + } #[doc = "0x68 - Clock E2 DBG"] - pub clk_e2_dbg: CLK_E2_DBG, + #[inline(always)] + pub const fn clk_e2_dbg(&self) -> &CLK_E2_DBG { + &self.clk_e2_dbg + } #[doc = "0x6c - Clock DMA AXI"] - pub clk_dma_axi: CLK_DMA_AXI, + #[inline(always)] + pub const fn clk_dma_axi(&self) -> &CLK_DMA_AXI { + &self.clk_dma_axi + } #[doc = "0x70 - Clock DMA AHB"] - pub clk_dma_ahb: CLK_DMA_AHB, + #[inline(always)] + pub const fn clk_dma_ahb(&self) -> &CLK_DMA_AHB { + &self.clk_dma_ahb + } #[doc = "0x74 - Software RESET Address Selector"] - pub soft_rst_addr_sel: SOFT_RST_ADDR_SEL, + #[inline(always)] + pub const fn soft_rst_addr_sel(&self) -> &SOFT_RST_ADDR_SEL { + &self.soft_rst_addr_sel + } #[doc = "0x78 - STGCRG RESET Status"] - pub stgcrg_rst_stat: STGCRG_RST_STAT, + #[inline(always)] + pub const fn stgcrg_rst_stat(&self) -> &STGCRG_RST_STAT { + &self.stgcrg_rst_stat + } } -#[doc = "clk_hifi4_core (rw) register accessor: Clock HIFI4 Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_hifi4_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_hifi4_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_hifi4_core`] +#[doc = "clk_hifi4_core (rw) register accessor: Clock HIFI4 Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_hifi4_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_hifi4_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_hifi4_core`] module"] pub type CLK_HIFI4_CORE = crate::Reg; #[doc = "Clock HIFI4 Core"] pub mod clk_hifi4_core; -#[doc = "clk_usb_apb (rw) register accessor: Clock USB APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_usb_apb`] +#[doc = "clk_usb_apb (rw) register accessor: Clock USB APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_usb_apb`] module"] pub type CLK_USB_APB = crate::Reg; #[doc = "Clock USB APB"] pub mod clk_usb_apb; -#[doc = "clk_usb_utmi_apb (rw) register accessor: Clock USB UTMI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_utmi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_utmi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_usb_utmi_apb`] +#[doc = "clk_usb_utmi_apb (rw) register accessor: Clock USB UTMI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_utmi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_utmi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_usb_utmi_apb`] module"] pub type CLK_USB_UTMI_APB = crate::Reg; #[doc = "Clock USB UTMI APB"] pub mod clk_usb_utmi_apb; -#[doc = "clk_usb_axi (rw) register accessor: Clock USB AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_usb_axi`] +#[doc = "clk_usb_axi (rw) register accessor: Clock USB AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_usb_axi`] module"] pub type CLK_USB_AXI = crate::Reg; #[doc = "Clock USB AXI"] pub mod clk_usb_axi; -#[doc = "clk_usb_ipm (rw) register accessor: Clock USB AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_ipm::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_ipm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_usb_ipm`] +#[doc = "clk_usb_ipm (rw) register accessor: Clock USB AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_ipm::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_ipm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_usb_ipm`] module"] pub type CLK_USB_IPM = crate::Reg; #[doc = "Clock USB AXI"] pub mod clk_usb_ipm; -#[doc = "clk_usb_stb (rw) register accessor: Clock USB STB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_stb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_stb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_usb_stb`] +#[doc = "clk_usb_stb (rw) register accessor: Clock USB STB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_stb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_stb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_usb_stb`] module"] pub type CLK_USB_STB = crate::Reg; #[doc = "Clock USB STB"] pub mod clk_usb_stb; -#[doc = "clk_usb_app125 (rw) register accessor: Clock USB APP 125\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_app125::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_app125::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_usb_app125`] +#[doc = "clk_usb_app125 (rw) register accessor: Clock USB APP 125\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_app125::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_app125::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_usb_app125`] module"] pub type CLK_USB_APP125 = crate::Reg; #[doc = "Clock USB APP 125"] pub mod clk_usb_app125; -#[doc = "clk_usb_refclk (rw) register accessor: Clock USB Reference Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_refclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_refclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_usb_refclk`] +#[doc = "clk_usb_refclk (rw) register accessor: Clock USB Reference Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_refclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_refclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_usb_refclk`] module"] pub type CLK_USB_REFCLK = crate::Reg; #[doc = "Clock USB Reference Clock"] pub mod clk_usb_refclk; -#[doc = "clk_u0_pcie_axi_mst0 (rw) register accessor: U0 Clock PCIe AXI MST 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_pcie_axi_mst0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_pcie_axi_mst0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_pcie_axi_mst0`] +#[doc = "clk_u0_pcie_axi_mst0 (rw) register accessor: U0 Clock PCIe AXI MST 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_pcie_axi_mst0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_pcie_axi_mst0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_pcie_axi_mst0`] module"] pub type CLK_U0_PCIE_AXI_MST0 = crate::Reg; #[doc = "U0 Clock PCIe AXI MST 0"] pub mod clk_u0_pcie_axi_mst0; -#[doc = "clk_u0_pcie_apb (rw) register accessor: U0 Clock PCIe APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_pcie_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_pcie_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_pcie_apb`] +#[doc = "clk_u0_pcie_apb (rw) register accessor: U0 Clock PCIe APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_pcie_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_pcie_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_pcie_apb`] module"] pub type CLK_U0_PCIE_APB = crate::Reg; #[doc = "U0 Clock PCIe APB"] pub mod clk_u0_pcie_apb; -#[doc = "clk_u0_pcie_tl (rw) register accessor: U0 Clock PCIe TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_pcie_tl::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_pcie_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_pcie_tl`] +#[doc = "clk_u0_pcie_tl (rw) register accessor: U0 Clock PCIe TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_pcie_tl::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_pcie_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_pcie_tl`] module"] pub type CLK_U0_PCIE_TL = crate::Reg; #[doc = "U0 Clock PCIe TL"] pub mod clk_u0_pcie_tl; -#[doc = "clk_u1_pcie_axi_mst0 (rw) register accessor: U1 Clock PCIe AXI MST 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_pcie_axi_mst0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_pcie_axi_mst0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_pcie_axi_mst0`] +#[doc = "clk_u1_pcie_axi_mst0 (rw) register accessor: U1 Clock PCIe AXI MST 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_pcie_axi_mst0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_pcie_axi_mst0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_pcie_axi_mst0`] module"] pub type CLK_U1_PCIE_AXI_MST0 = crate::Reg; #[doc = "U1 Clock PCIe AXI MST 0"] pub mod clk_u1_pcie_axi_mst0; -#[doc = "clk_u1_pcie_apb (rw) register accessor: U1 Clock PCIe APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_pcie_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_pcie_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_pcie_apb`] +#[doc = "clk_u1_pcie_apb (rw) register accessor: U1 Clock PCIe APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_pcie_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_pcie_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_pcie_apb`] module"] pub type CLK_U1_PCIE_APB = crate::Reg; #[doc = "U1 Clock PCIe APB"] pub mod clk_u1_pcie_apb; -#[doc = "clk_u1_pcie_tl (rw) register accessor: U1 Clock PCIe TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_pcie_tl::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_pcie_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_pcie_tl`] +#[doc = "clk_u1_pcie_tl (rw) register accessor: U1 Clock PCIe TL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_pcie_tl::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_pcie_tl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_pcie_tl`] module"] pub type CLK_U1_PCIE_TL = crate::Reg; #[doc = "U1 Clock PCIe TL"] pub mod clk_u1_pcie_tl; -#[doc = "clk_pcie01_slv_dec_main (rw) register accessor: Clock PCIe 01 SLV DEC Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pcie01_slv_dec_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pcie01_slv_dec_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pcie01_slv_dec_main`] +#[doc = "clk_pcie01_slv_dec_main (rw) register accessor: Clock PCIe 01 SLV DEC Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pcie01_slv_dec_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pcie01_slv_dec_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pcie01_slv_dec_main`] module"] pub type CLK_PCIE01_SLV_DEC_MAIN = crate::Reg; #[doc = "Clock PCIe 01 SLV DEC Main"] pub mod clk_pcie01_slv_dec_main; -#[doc = "clk_sec_hclk (rw) register accessor: Clock Security HCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_sec_hclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sec_hclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_sec_hclk`] +#[doc = "clk_sec_hclk (rw) register accessor: Clock Security HCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_sec_hclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sec_hclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_sec_hclk`] module"] pub type CLK_SEC_HCLK = crate::Reg; #[doc = "Clock Security HCLK"] pub mod clk_sec_hclk; -#[doc = "clk_sec_misc_ahb (rw) register accessor: Clock Security Miscellaneous AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_sec_misc_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sec_misc_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_sec_misc_ahb`] +#[doc = "clk_sec_misc_ahb (rw) register accessor: Clock Security Miscellaneous AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_sec_misc_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sec_misc_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_sec_misc_ahb`] module"] pub type CLK_SEC_MISC_AHB = crate::Reg; #[doc = "Clock Security Miscellaneous AHB"] pub mod clk_sec_misc_ahb; -#[doc = "clk_stg_mtrx_group0_main (rw) register accessor: Clock STG MTRX Group 0 Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group0_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group0_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_stg_mtrx_group0_main`] +#[doc = "clk_stg_mtrx_group0_main (rw) register accessor: Clock STG MTRX Group 0 Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group0_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group0_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_stg_mtrx_group0_main`] module"] pub type CLK_STG_MTRX_GROUP0_MAIN = crate::Reg; #[doc = "Clock STG MTRX Group 0 Main"] pub mod clk_stg_mtrx_group0_main; -#[doc = "clk_stg_mtrx_group0_bus (rw) register accessor: Clock STG MTRX Group 0 Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group0_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group0_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_stg_mtrx_group0_bus`] +#[doc = "clk_stg_mtrx_group0_bus (rw) register accessor: Clock STG MTRX Group 0 Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group0_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group0_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_stg_mtrx_group0_bus`] module"] pub type CLK_STG_MTRX_GROUP0_BUS = crate::Reg; #[doc = "Clock STG MTRX Group 0 Bus"] pub mod clk_stg_mtrx_group0_bus; -#[doc = "clk_stg_mtrx_group0_stg (rw) register accessor: Clock STG MTRX Group 0 STG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group0_stg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group0_stg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_stg_mtrx_group0_stg`] +#[doc = "clk_stg_mtrx_group0_stg (rw) register accessor: Clock STG MTRX Group 0 STG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group0_stg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group0_stg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_stg_mtrx_group0_stg`] module"] pub type CLK_STG_MTRX_GROUP0_STG = crate::Reg; #[doc = "Clock STG MTRX Group 0 STG"] pub mod clk_stg_mtrx_group0_stg; -#[doc = "clk_stg_mtrx_group1_main (rw) register accessor: Clock STG MTRX Group 1 Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group1_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group1_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_stg_mtrx_group1_main`] +#[doc = "clk_stg_mtrx_group1_main (rw) register accessor: Clock STG MTRX Group 1 Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group1_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group1_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_stg_mtrx_group1_main`] module"] pub type CLK_STG_MTRX_GROUP1_MAIN = crate::Reg; #[doc = "Clock STG MTRX Group 1 Main"] pub mod clk_stg_mtrx_group1_main; -#[doc = "clk_stg_mtrx_group1_bus (rw) register accessor: Clock STG MTRX Group 1 Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group1_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group1_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_stg_mtrx_group1_bus`] +#[doc = "clk_stg_mtrx_group1_bus (rw) register accessor: Clock STG MTRX Group 1 Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group1_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group1_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_stg_mtrx_group1_bus`] module"] pub type CLK_STG_MTRX_GROUP1_BUS = crate::Reg; #[doc = "Clock STG MTRX Group 1 Bus"] pub mod clk_stg_mtrx_group1_bus; -#[doc = "clk_stg_mtrx_group1_stg (rw) register accessor: Clock STG MTRX Group 1 STG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group1_stg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group1_stg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_stg_mtrx_group1_stg`] +#[doc = "clk_stg_mtrx_group1_stg (rw) register accessor: Clock STG MTRX Group 1 STG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group1_stg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group1_stg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_stg_mtrx_group1_stg`] module"] pub type CLK_STG_MTRX_GROUP1_STG = crate::Reg; #[doc = "Clock STG MTRX Group 1 STG"] pub mod clk_stg_mtrx_group1_stg; -#[doc = "clk_stg_mtrx_group1_hifi (rw) register accessor: Clock STG MTRX Group 1 HIFI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group1_hifi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group1_hifi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_stg_mtrx_group1_hifi`] +#[doc = "clk_stg_mtrx_group1_hifi (rw) register accessor: Clock STG MTRX Group 1 HIFI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_mtrx_group1_hifi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_mtrx_group1_hifi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_stg_mtrx_group1_hifi`] module"] pub type CLK_STG_MTRX_GROUP1_HIFI = crate::Reg; #[doc = "Clock STG MTRX Group 1 HIFI"] pub mod clk_stg_mtrx_group1_hifi; -#[doc = "clk_e2_rtc (rw) register accessor: Clock E2 RTC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_e2_rtc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_e2_rtc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_e2_rtc`] +#[doc = "clk_e2_rtc (rw) register accessor: Clock E2 RTC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_e2_rtc::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_e2_rtc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_e2_rtc`] module"] pub type CLK_E2_RTC = crate::Reg; #[doc = "Clock E2 RTC"] pub mod clk_e2_rtc; -#[doc = "clk_e2_core (rw) register accessor: Clock E2 Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_e2_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_e2_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_e2_core`] +#[doc = "clk_e2_core (rw) register accessor: Clock E2 Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_e2_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_e2_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_e2_core`] module"] pub type CLK_E2_CORE = crate::Reg; #[doc = "Clock E2 Core"] pub mod clk_e2_core; -#[doc = "clk_e2_dbg (rw) register accessor: Clock E2 DBG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_e2_dbg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_e2_dbg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_e2_dbg`] +#[doc = "clk_e2_dbg (rw) register accessor: Clock E2 DBG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_e2_dbg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_e2_dbg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_e2_dbg`] module"] pub type CLK_E2_DBG = crate::Reg; #[doc = "Clock E2 DBG"] pub mod clk_e2_dbg; -#[doc = "clk_dma_axi (rw) register accessor: Clock DMA AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_dma_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_dma_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_dma_axi`] +#[doc = "clk_dma_axi (rw) register accessor: Clock DMA AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_dma_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_dma_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_dma_axi`] module"] pub type CLK_DMA_AXI = crate::Reg; #[doc = "Clock DMA AXI"] pub mod clk_dma_axi; -#[doc = "clk_dma_ahb (rw) register accessor: Clock DMA AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_dma_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_dma_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_dma_ahb`] +#[doc = "clk_dma_ahb (rw) register accessor: Clock DMA AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_dma_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_dma_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_dma_ahb`] module"] pub type CLK_DMA_AHB = crate::Reg; #[doc = "Clock DMA AHB"] pub mod clk_dma_ahb; -#[doc = "soft_rst_addr_sel (rw) register accessor: Software RESET Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_rst_addr_sel`] +#[doc = "soft_rst_addr_sel (rw) register accessor: Software RESET Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_rst_addr_sel`] module"] pub type SOFT_RST_ADDR_SEL = crate::Reg; #[doc = "Software RESET Address Selector"] pub mod soft_rst_addr_sel; -#[doc = "stgcrg_rst_stat (rw) register accessor: STGCRG RESET Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stgcrg_rst_stat::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stgcrg_rst_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stgcrg_rst_stat`] +#[doc = "stgcrg_rst_stat (rw) register accessor: STGCRG RESET Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stgcrg_rst_stat::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stgcrg_rst_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stgcrg_rst_stat`] module"] pub type STGCRG_RST_STAT = crate::Reg; #[doc = "STGCRG RESET Status"] diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_dma_ahb.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_dma_ahb.rs index 3b6fbfc..5fa8ca5 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_dma_ahb.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_dma_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_dma_axi.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_dma_axi.rs index 5894036..3f0cac3 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_dma_axi.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_dma_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_e2_core.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_e2_core.rs index 327bb44..8e7f48a 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_e2_core.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_e2_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_e2_dbg.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_e2_dbg.rs index c82c736..d776b89 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_e2_dbg.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_e2_dbg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_e2_rtc.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_e2_rtc.rs index f22780e..ac6cb39 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_e2_rtc.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_e2_rtc.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_hifi4_core.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_hifi4_core.rs index 714463f..ddcfd09 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_hifi4_core.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_hifi4_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_pcie01_slv_dec_main.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_pcie01_slv_dec_main.rs index 9546e89..f37f28b 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_pcie01_slv_dec_main.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_pcie01_slv_dec_main.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_sec_hclk.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_sec_hclk.rs index 2659357..f33ff15 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_sec_hclk.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_sec_hclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_sec_misc_ahb.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_sec_misc_ahb.rs index c178517..34c498a 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_sec_misc_ahb.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_sec_misc_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group0_bus.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group0_bus.rs index 8781f81..a13ef5a 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group0_bus.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group0_bus.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group0_main.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group0_main.rs index eabd069..174fc50 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group0_main.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group0_main.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group0_stg.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group0_stg.rs index cb6584b..9717b67 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group0_stg.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group0_stg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group1_bus.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group1_bus.rs index a330c2d..27b97b0 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group1_bus.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group1_bus.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group1_hifi.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group1_hifi.rs index b8c7a2c..0f70e97 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group1_hifi.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group1_hifi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group1_main.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group1_main.rs index 6ec8ada..9322888 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group1_main.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group1_main.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group1_stg.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group1_stg.rs index 0b22c38..1a14908 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group1_stg.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_stg_mtrx_group1_stg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_u0_pcie_apb.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_u0_pcie_apb.rs index dea7684..b10c31d 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_u0_pcie_apb.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_u0_pcie_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_u0_pcie_axi_mst0.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_u0_pcie_axi_mst0.rs index ca2abf5..4064560 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_u0_pcie_axi_mst0.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_u0_pcie_axi_mst0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_u0_pcie_tl.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_u0_pcie_tl.rs index 0ef62c0..51ef398 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_u0_pcie_tl.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_u0_pcie_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_u1_pcie_apb.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_u1_pcie_apb.rs index c860b6b..50cf831 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_u1_pcie_apb.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_u1_pcie_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_u1_pcie_axi_mst0.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_u1_pcie_axi_mst0.rs index 9408a60..b0b0f08 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_u1_pcie_axi_mst0.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_u1_pcie_axi_mst0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_u1_pcie_tl.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_u1_pcie_tl.rs index 43ded3a..c2eddb9 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_u1_pcie_tl.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_u1_pcie_tl.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_apb.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_apb.rs index 7ce629a..0efd0a4 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_apb.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_app125.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_app125.rs index 3e3af58..c100e0f 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_app125.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_app125.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_axi.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_axi.rs index 2882c29..bdd6de4 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_axi.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_ipm.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_ipm.rs index 66c4fd1..5cae745 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_ipm.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_ipm.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_refclk.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_refclk.rs index b49c4fb..1ac3115 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_refclk.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_refclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_stb.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_stb.rs index ed474f9..4470877 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_stb.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_stb.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_utmi_apb.rs b/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_utmi_apb.rs index 45a42e3..e1ad342 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_utmi_apb.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/clk_usb_utmi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/soft_rst_addr_sel.rs b/jh7110-vf2-13b-pac/src/stgcrg/soft_rst_addr_sel.rs index 829170e..734359d 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/soft_rst_addr_sel.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/soft_rst_addr_sel.rs @@ -5,95 +5,95 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_stg_syscon_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_STG_SYSCON_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_stg_syscon_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_STG_SYSCON_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_STG_SYSCON_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_hifi4_rst_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_HIFI4_RST_CORE_R = crate::BitReader; #[doc = "Field `rst_u0_hifi4_rst_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_HIFI4_RST_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_HIFI4_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_hifi4_rst_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_HIFI4_RST_AXI_R = crate::BitReader; #[doc = "Field `rst_u0_hifi4_rst_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_HIFI4_RST_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_HIFI4_RST_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_sec_top_hreesetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SEC_TOP_HREESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_sec_top_hreesetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SEC_TOP_HREESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SEC_TOP_HREESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_e2_sft7110_rst_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_E2_SFT7110_RST_CORE_R = crate::BitReader; #[doc = "Field `rst_u0_e2_sft7110_rst_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_E2_SFT7110_RST_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_E2_SFT7110_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dma1p_8ch_56hs_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_dma1p_8ch_56hs_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dma1p_8ch_56hs_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_dma1p_8ch_56hs_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdn_usb_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDN_USB_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_cdn_usb_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDN_USB_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDN_USB_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdn_usb_rstn_usb_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDN_USB_RSTN_USB_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdn_usb_rstn_usb_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDN_USB_RSTN_USB_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDN_USB_RSTN_USB_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdn_usb_rstn_utmi_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDN_USB_RSTN_UTMI_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdn_usb_rstn_utmi_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDN_USB_RSTN_UTMI_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDN_USB_RSTN_UTMI_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdn_usb_rstn_pwrup` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDN_USB_RSTN_PWRUP_R = crate::BitReader; #[doc = "Field `rstn_u0_cdn_usb_rstn_pwrup` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDN_USB_RSTN_PWRUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDN_USB_RSTN_PWRUP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_mst0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_mst0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_slv0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_slv0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_slv` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_slv` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pci_rstn_brg` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCI_RSTN_BRG_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pci_rstn_brg` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCI_RSTN_BRG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCI_RSTN_BRG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_pcie` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_PCIE_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_pcie` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_PCIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_PCIE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_mst0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_mst0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_slv0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_slv0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_slv` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_slv` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_brg` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_BRG_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_brg` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_BRG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_BRG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_pcie` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_PCIE_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_pcie` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_PCIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_PCIE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -217,182 +217,186 @@ impl W { #[must_use] pub fn rstn_u0_stg_syscon_presetn( &mut self, - ) -> RSTN_U0_STG_SYSCON_PRESETN_W { - RSTN_U0_STG_SYSCON_PRESETN_W::new(self) + ) -> RSTN_U0_STG_SYSCON_PRESETN_W { + RSTN_U0_STG_SYSCON_PRESETN_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rst_u0_hifi4_rst_core(&mut self) -> RST_U0_HIFI4_RST_CORE_W { - RST_U0_HIFI4_RST_CORE_W::new(self) + pub fn rst_u0_hifi4_rst_core(&mut self) -> RST_U0_HIFI4_RST_CORE_W { + RST_U0_HIFI4_RST_CORE_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rst_u0_hifi4_rst_axi(&mut self) -> RST_U0_HIFI4_RST_AXI_W { - RST_U0_HIFI4_RST_AXI_W::new(self) + pub fn rst_u0_hifi4_rst_axi(&mut self) -> RST_U0_HIFI4_RST_AXI_W { + RST_U0_HIFI4_RST_AXI_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_sec_top_hreesetn( &mut self, - ) -> RSTN_U0_SEC_TOP_HREESETN_W { - RSTN_U0_SEC_TOP_HREESETN_W::new(self) + ) -> RSTN_U0_SEC_TOP_HREESETN_W { + RSTN_U0_SEC_TOP_HREESETN_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_e2_sft7110_rst_core( &mut self, - ) -> RST_U0_E2_SFT7110_RST_CORE_W { - RST_U0_E2_SFT7110_RST_CORE_W::new(self) + ) -> RST_U0_E2_SFT7110_RST_CORE_W { + RST_U0_E2_SFT7110_RST_CORE_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dma1p_8ch_56hs_rstn_axi( &mut self, - ) -> RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W { - RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W::new(self) + ) -> RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W { + RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dma1p_8ch_56hs_rstn_ahb( &mut self, - ) -> RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W { - RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W::new(self) + ) -> RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W { + RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdn_usb_rstn_axi( &mut self, - ) -> RSTN_U0_CDN_USB_RSTN_AXI_W { - RSTN_U0_CDN_USB_RSTN_AXI_W::new(self) + ) -> RSTN_U0_CDN_USB_RSTN_AXI_W { + RSTN_U0_CDN_USB_RSTN_AXI_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdn_usb_rstn_usb_apb( &mut self, - ) -> RSTN_U0_CDN_USB_RSTN_USB_APB_W { - RSTN_U0_CDN_USB_RSTN_USB_APB_W::new(self) + ) -> RSTN_U0_CDN_USB_RSTN_USB_APB_W { + RSTN_U0_CDN_USB_RSTN_USB_APB_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdn_usb_rstn_utmi_apb( &mut self, - ) -> RSTN_U0_CDN_USB_RSTN_UTMI_APB_W { - RSTN_U0_CDN_USB_RSTN_UTMI_APB_W::new(self) + ) -> RSTN_U0_CDN_USB_RSTN_UTMI_APB_W { + RSTN_U0_CDN_USB_RSTN_UTMI_APB_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdn_usb_rstn_pwrup( &mut self, - ) -> RSTN_U0_CDN_USB_RSTN_PWRUP_W { - RSTN_U0_CDN_USB_RSTN_PWRUP_W::new(self) + ) -> RSTN_U0_CDN_USB_RSTN_PWRUP_W { + RSTN_U0_CDN_USB_RSTN_PWRUP_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_axi_mst0( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W { - RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W { + RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_axi_slv0( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W { - RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W { + RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_axi_slv( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W { - RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W { + RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pci_rstn_brg( &mut self, - ) -> RSTN_U0_PLDA_PCI_RSTN_BRG_W { - RSTN_U0_PLDA_PCI_RSTN_BRG_W::new(self) + ) -> RSTN_U0_PLDA_PCI_RSTN_BRG_W { + RSTN_U0_PLDA_PCI_RSTN_BRG_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_pcie( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_PCIE_W { - RSTN_U0_PLDA_PCIE_RSTN_PCIE_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_PCIE_W { + RSTN_U0_PLDA_PCIE_RSTN_PCIE_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_apb( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_APB_W { - RSTN_U0_PLDA_PCIE_RSTN_APB_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_APB_W { + RSTN_U0_PLDA_PCIE_RSTN_APB_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_axi_mst0( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W { - RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W { + RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_axi_slv0( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W { - RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W { + RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_axi_slv( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W { - RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W { + RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_brg( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_BRG_W { - RSTN_U1_PLDA_PCIE_RSTN_BRG_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_BRG_W { + RSTN_U1_PLDA_PCIE_RSTN_BRG_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_pcie( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_PCIE_W { - RSTN_U1_PLDA_PCIE_RSTN_PCIE_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_PCIE_W { + RSTN_U1_PLDA_PCIE_RSTN_PCIE_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_apb( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_APB_W { - RSTN_U1_PLDA_PCIE_RSTN_APB_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> RSTN_U1_PLDA_PCIE_RSTN_APB_W { + RSTN_U1_PLDA_PCIE_RSTN_APB_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/stgcrg/stgcrg_rst_stat.rs b/jh7110-vf2-13b-pac/src/stgcrg/stgcrg_rst_stat.rs index 1ae80fa..6eff18f 100644 --- a/jh7110-vf2-13b-pac/src/stgcrg/stgcrg_rst_stat.rs +++ b/jh7110-vf2-13b-pac/src/stgcrg/stgcrg_rst_stat.rs @@ -5,95 +5,95 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_stg_syscon_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_STG_SYSCON_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_stg_syscon_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_STG_SYSCON_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_STG_SYSCON_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_hifi4_rst_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_HIFI4_RST_CORE_R = crate::BitReader; #[doc = "Field `rst_u0_hifi4_rst_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_HIFI4_RST_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_HIFI4_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_hifi4_rst_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_HIFI4_RST_AXI_R = crate::BitReader; #[doc = "Field `rst_u0_hifi4_rst_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_HIFI4_RST_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_HIFI4_RST_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_sec_top_hreesetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SEC_TOP_HREESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_sec_top_hreesetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SEC_TOP_HREESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SEC_TOP_HREESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_e2_sft7110_rst_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_E2_SFT7110_RST_CORE_R = crate::BitReader; #[doc = "Field `rst_u0_e2_sft7110_rst_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_E2_SFT7110_RST_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_E2_SFT7110_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dma1p_8ch_56hs_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_dma1p_8ch_56hs_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dma1p_8ch_56hs_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_dma1p_8ch_56hs_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdn_usb_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDN_USB_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_cdn_usb_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDN_USB_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDN_USB_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdn_usb_rstn_usb_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDN_USB_RSTN_USB_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdn_usb_rstn_usb_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDN_USB_RSTN_USB_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDN_USB_RSTN_USB_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdn_usb_rstn_utmi_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDN_USB_RSTN_UTMI_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdn_usb_rstn_utmi_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDN_USB_RSTN_UTMI_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDN_USB_RSTN_UTMI_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdn_usb_rstn_pwrup` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDN_USB_RSTN_PWRUP_R = crate::BitReader; #[doc = "Field `rstn_u0_cdn_usb_rstn_pwrup` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDN_USB_RSTN_PWRUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDN_USB_RSTN_PWRUP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_mst0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_mst0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_slv0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_slv0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_slv` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_axi_slv` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pci_rstn_brg` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCI_RSTN_BRG_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pci_rstn_brg` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCI_RSTN_BRG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCI_RSTN_BRG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_pcie` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_PCIE_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_pcie` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_PCIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_PCIE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_plda_pcie_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PLDA_PCIE_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_plda_pcie_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PLDA_PCIE_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PLDA_PCIE_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_mst0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_mst0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_slv0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_slv0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_slv` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_axi_slv` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_brg` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_BRG_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_brg` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_BRG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_BRG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_pcie` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_PCIE_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_pcie` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_PCIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_PCIE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_plda_pcie_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_PLDA_PCIE_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_plda_pcie_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_PLDA_PCIE_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_PLDA_PCIE_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -217,182 +217,182 @@ impl W { #[must_use] pub fn rstn_u0_stg_syscon_presetn( &mut self, - ) -> RSTN_U0_STG_SYSCON_PRESETN_W { - RSTN_U0_STG_SYSCON_PRESETN_W::new(self) + ) -> RSTN_U0_STG_SYSCON_PRESETN_W { + RSTN_U0_STG_SYSCON_PRESETN_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rst_u0_hifi4_rst_core(&mut self) -> RST_U0_HIFI4_RST_CORE_W { - RST_U0_HIFI4_RST_CORE_W::new(self) + pub fn rst_u0_hifi4_rst_core(&mut self) -> RST_U0_HIFI4_RST_CORE_W { + RST_U0_HIFI4_RST_CORE_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rst_u0_hifi4_rst_axi(&mut self) -> RST_U0_HIFI4_RST_AXI_W { - RST_U0_HIFI4_RST_AXI_W::new(self) + pub fn rst_u0_hifi4_rst_axi(&mut self) -> RST_U0_HIFI4_RST_AXI_W { + RST_U0_HIFI4_RST_AXI_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_sec_top_hreesetn( - &mut self, - ) -> RSTN_U0_SEC_TOP_HREESETN_W { - RSTN_U0_SEC_TOP_HREESETN_W::new(self) + pub fn rstn_u0_sec_top_hreesetn(&mut self) -> RSTN_U0_SEC_TOP_HREESETN_W { + RSTN_U0_SEC_TOP_HREESETN_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_e2_sft7110_rst_core( &mut self, - ) -> RST_U0_E2_SFT7110_RST_CORE_W { - RST_U0_E2_SFT7110_RST_CORE_W::new(self) + ) -> RST_U0_E2_SFT7110_RST_CORE_W { + RST_U0_E2_SFT7110_RST_CORE_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dma1p_8ch_56hs_rstn_axi( &mut self, - ) -> RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W { - RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W::new(self) + ) -> RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W { + RSTN_U0_DMA1P_8CH_56HS_RSTN_AXI_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dma1p_8ch_56hs_rstn_ahb( &mut self, - ) -> RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W { - RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W::new(self) + ) -> RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W { + RSTN_U0_DMA1P_8CH_56HS_RSTN_AHB_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_cdn_usb_rstn_axi( - &mut self, - ) -> RSTN_U0_CDN_USB_RSTN_AXI_W { - RSTN_U0_CDN_USB_RSTN_AXI_W::new(self) + pub fn rstn_u0_cdn_usb_rstn_axi(&mut self) -> RSTN_U0_CDN_USB_RSTN_AXI_W { + RSTN_U0_CDN_USB_RSTN_AXI_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdn_usb_rstn_usb_apb( &mut self, - ) -> RSTN_U0_CDN_USB_RSTN_USB_APB_W { - RSTN_U0_CDN_USB_RSTN_USB_APB_W::new(self) + ) -> RSTN_U0_CDN_USB_RSTN_USB_APB_W { + RSTN_U0_CDN_USB_RSTN_USB_APB_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdn_usb_rstn_utmi_apb( &mut self, - ) -> RSTN_U0_CDN_USB_RSTN_UTMI_APB_W { - RSTN_U0_CDN_USB_RSTN_UTMI_APB_W::new(self) + ) -> RSTN_U0_CDN_USB_RSTN_UTMI_APB_W { + RSTN_U0_CDN_USB_RSTN_UTMI_APB_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdn_usb_rstn_pwrup( &mut self, - ) -> RSTN_U0_CDN_USB_RSTN_PWRUP_W { - RSTN_U0_CDN_USB_RSTN_PWRUP_W::new(self) + ) -> RSTN_U0_CDN_USB_RSTN_PWRUP_W { + RSTN_U0_CDN_USB_RSTN_PWRUP_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_axi_mst0( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W { - RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W { + RSTN_U0_PLDA_PCIE_RSTN_AXI_MST0_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_axi_slv0( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W { - RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W { + RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV0_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_axi_slv( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W { - RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W { + RSTN_U0_PLDA_PCIE_RSTN_AXI_SLV_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pci_rstn_brg( &mut self, - ) -> RSTN_U0_PLDA_PCI_RSTN_BRG_W { - RSTN_U0_PLDA_PCI_RSTN_BRG_W::new(self) + ) -> RSTN_U0_PLDA_PCI_RSTN_BRG_W { + RSTN_U0_PLDA_PCI_RSTN_BRG_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_pcie( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_PCIE_W { - RSTN_U0_PLDA_PCIE_RSTN_PCIE_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_PCIE_W { + RSTN_U0_PLDA_PCIE_RSTN_PCIE_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_plda_pcie_rstn_apb( &mut self, - ) -> RSTN_U0_PLDA_PCIE_RSTN_APB_W { - RSTN_U0_PLDA_PCIE_RSTN_APB_W::new(self) + ) -> RSTN_U0_PLDA_PCIE_RSTN_APB_W { + RSTN_U0_PLDA_PCIE_RSTN_APB_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_axi_mst0( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W { - RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W { + RSTN_U1_PLDA_PCIE_RSTN_AXI_MST0_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_axi_slv0( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W { - RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W { + RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV0_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_axi_slv( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W { - RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W { + RSTN_U1_PLDA_PCIE_RSTN_AXI_SLV_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_brg( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_BRG_W { - RSTN_U1_PLDA_PCIE_RSTN_BRG_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_BRG_W { + RSTN_U1_PLDA_PCIE_RSTN_BRG_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_pcie( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_PCIE_W { - RSTN_U1_PLDA_PCIE_RSTN_PCIE_W::new(self) + ) -> RSTN_U1_PLDA_PCIE_RSTN_PCIE_W { + RSTN_U1_PLDA_PCIE_RSTN_PCIE_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_plda_pcie_rstn_apb( &mut self, - ) -> RSTN_U1_PLDA_PCIE_RSTN_APB_W { - RSTN_U1_PLDA_PCIE_RSTN_APB_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> RSTN_U1_PLDA_PCIE_RSTN_APB_W { + RSTN_U1_PLDA_PCIE_RSTN_APB_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl.rs index 8dfa43c..d38021b 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl.rs @@ -1,1422 +1,1890 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { - #[doc = "0x00 - SYS IOMUX CFG SAIF SYSCFG FMUX 0 DOEN"] - pub gpo_doen0: GPO_DOEN0, - #[doc = "0x04 - SYS IOMUX CFG SAIF SYSCFG FMUX 1 DOEN"] - pub gpo_doen1: GPO_DOEN1, - #[doc = "0x08 - SYS IOMUX CFG SAIF SYSCFG FMUX 2 DOEN"] - pub gpo_doen2: GPO_DOEN2, - #[doc = "0x0c - SYS IOMUX CFG SAIF SYSCFG FMUX 3 DOEN"] - pub gpo_doen3: GPO_DOEN3, - #[doc = "0x10 - SYS IOMUX CFG SAIF SYSCFG FMUX 4 DOEN"] - pub gpo_doen4: GPO_DOEN4, - #[doc = "0x14 - SYS IOMUX CFG SAIF SYSCFG FMUX 5 DOEN"] - pub gpo_doen5: GPO_DOEN5, - #[doc = "0x18 - SYS IOMUX CFG SAIF SYSCFG FMUX 6 DOEN"] - pub gpo_doen6: GPO_DOEN6, - #[doc = "0x1c - SYS IOMUX CFG SAIF SYSCFG FMUX 7 DOEN"] - pub gpo_doen7: GPO_DOEN7, - #[doc = "0x20 - SYS IOMUX CFG SAIF SYSCFG FMUX 8 DOEN"] - pub gpo_doen8: GPO_DOEN8, - #[doc = "0x24 - SYS IOMUX CFG SAIF SYSCFG FMUX 9 DOEN"] - pub gpo_doen9: GPO_DOEN9, - #[doc = "0x28 - SYS IOMUX CFG SAIF SYSCFG FMUX 10 DOEN"] - pub gpo_doen10: GPO_DOEN10, - #[doc = "0x2c - SYS IOMUX CFG SAIF SYSCFG FMUX 11 DOEN"] - pub gpo_doen11: GPO_DOEN11, - #[doc = "0x30 - SYS IOMUX CFG SAIF SYSCFG FMUX 12 DOEN"] - pub gpo_doen12: GPO_DOEN12, - #[doc = "0x34 - SYS IOMUX CFG SAIF SYSCFG FMUX 13 DOEN"] - pub gpo_doen13: GPO_DOEN13, + gpo_doen0: GPO_DOEN0, + gpo_doen1: GPO_DOEN1, + gpo_doen2: GPO_DOEN2, + gpo_doen3: GPO_DOEN3, + gpo_doen4: GPO_DOEN4, + gpo_doen5: GPO_DOEN5, + gpo_doen6: GPO_DOEN6, + gpo_doen7: GPO_DOEN7, + gpo_doen8: GPO_DOEN8, + gpo_doen9: GPO_DOEN9, + gpo_doen10: GPO_DOEN10, + gpo_doen11: GPO_DOEN11, + gpo_doen12: GPO_DOEN12, + gpo_doen13: GPO_DOEN13, _reserved_14_gpi0: [u8; 0x4c], - #[doc = "0x84 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 4 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi4: GPI4, - #[doc = "0x88 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 8 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi8: GPI8, - #[doc = "0x8c - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 12 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi12: GPI12, - #[doc = "0x90 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 16 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi16: GPI16, - #[doc = "0x94 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 20 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi20: GPI20, - #[doc = "0x98 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 24 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi24: GPI24, - #[doc = "0x9c - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 28 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi28: GPI28, - #[doc = "0xa0 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 32 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi32: GPI32, - #[doc = "0xa4 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 36 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi36: GPI36, - #[doc = "0xa8 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 40 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi40: GPI40, - #[doc = "0xac - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 44 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi44: GPI44, - #[doc = "0xb0 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 48 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi48: GPI48, - #[doc = "0xb4 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 52 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi52: GPI52, - #[doc = "0xb8 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 56 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi56: GPI56, - #[doc = "0xbc - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 60 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi60: GPI60, - #[doc = "0xc0 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 64 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi64: GPI64, - #[doc = "0xc4 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 68 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi68: GPI68, - #[doc = "0xc8 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 72 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi72: GPI72, - #[doc = "0xcc - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 76 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi76: GPI76, - #[doc = "0xd0 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 80 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi80: GPI80, - #[doc = "0xd4 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 84 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi84: GPI84, - #[doc = "0xd8 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 88 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] - pub gpi88: GPI88, - #[doc = "0xdc - Enable GPIO IRQ function"] - pub ioirq0: IOIRQ0, + gpi4: GPI4, + gpi8: GPI8, + gpi12: GPI12, + gpi16: GPI16, + gpi20: GPI20, + gpi24: GPI24, + gpi28: GPI28, + gpi32: GPI32, + gpi36: GPI36, + gpi40: GPI40, + gpi44: GPI44, + gpi48: GPI48, + gpi52: GPI52, + gpi56: GPI56, + gpi60: GPI60, + gpi64: GPI64, + gpi68: GPI68, + gpi72: GPI72, + gpi76: GPI76, + gpi80: GPI80, + gpi84: GPI84, + gpi88: GPI88, + ioirq0: IOIRQ0, _reserved38: [u8; 0x40], - #[doc = "0x120 - SYS IOMUX CFG SAIF SYSCFG PADCFG 288: GPIO0"] - pub padcfg_gpio0: PADCFG_GPIO0, - #[doc = "0x124 - SYS IOMUX CFG SAIF SYSCFG PADCFG 292: GPIO1"] - pub padcfg_gpio1: PADCFG_GPIO1, - #[doc = "0x128 - SYS IOMUX CFG SAIF SYSCFG PADCFG 296: GPIO2"] - pub padcfg_gpio2: PADCFG_GPIO2, - #[doc = "0x12c - SYS IOMUX CFG SAIF SYSCFG PADCFG 300: GPIO3"] - pub padcfg_gpio3: PADCFG_GPIO3, - #[doc = "0x130 - SYS IOMUX CFG SAIF SYSCFG PADCFG 304: GPIO4"] - pub padcfg_gpio4: PADCFG_GPIO4, - #[doc = "0x134 - SYS IOMUX CFG SAIF SYSCFG PADCFG 308: GPIO5"] - pub padcfg_gpio5: PADCFG_GPIO5, - #[doc = "0x138 - SYS IOMUX CFG SAIF SYSCFG PADCFG 312: GPIO6"] - pub padcfg_gpio6: PADCFG_GPIO6, - #[doc = "0x13c - SYS IOMUX CFG SAIF SYSCFG PADCFG 316: GPIO7"] - pub padcfg_gpio7: PADCFG_GPIO7, - #[doc = "0x140 - SYS IOMUX CFG SAIF SYSCFG PADCFG 320: GPIO8"] - pub padcfg_gpio8: PADCFG_GPIO8, - #[doc = "0x144 - SYS IOMUX CFG SAIF SYSCFG PADCFG 324: GPIO9"] - pub padcfg_gpio9: PADCFG_GPIO9, - #[doc = "0x148 - SYS IOMUX CFG SAIF SYSCFG PADCFG 328: GPIO10"] - pub padcfg_gpio10: PADCFG_GPIO10, - #[doc = "0x14c - SYS IOMUX CFG SAIF SYSCFG PADCFG 332: GPIO11"] - pub padcfg_gpio11: PADCFG_GPIO11, - #[doc = "0x150 - SYS IOMUX CFG SAIF SYSCFG PADCFG 336: GPIO12"] - pub padcfg_gpio12: PADCFG_GPIO12, - #[doc = "0x154 - SYS IOMUX CFG SAIF SYSCFG PADCFG 340: GPIO13"] - pub padcfg_gpio13: PADCFG_GPIO13, - #[doc = "0x158 - SYS IOMUX CFG SAIF SYSCFG PADCFG 344: GPIO14"] - pub padcfg_gpio14: PADCFG_GPIO14, - #[doc = "0x15c - SYS IOMUX CFG SAIF SYSCFG PADCFG 348: GPIO15"] - pub padcfg_gpio15: PADCFG_GPIO15, - #[doc = "0x160 - SYS IOMUX CFG SAIF SYSCFG PADCFG 352: GPIO16"] - pub padcfg_gpio16: PADCFG_GPIO16, - #[doc = "0x164 - SYS IOMUX CFG SAIF SYSCFG PADCFG 356: GPIO17"] - pub padcfg_gpio17: PADCFG_GPIO17, - #[doc = "0x168 - SYS IOMUX CFG SAIF SYSCFG PADCFG 360: GPIO18"] - pub padcfg_gpio18: PADCFG_GPIO18, - #[doc = "0x16c - SYS IOMUX CFG SAIF SYSCFG PADCFG 364: GPIO19"] - pub padcfg_gpio19: PADCFG_GPIO19, - #[doc = "0x170 - SYS IOMUX CFG SAIF SYSCFG PADCFG 368: GPIO20"] - pub padcfg_gpio20: PADCFG_GPIO20, - #[doc = "0x174 - SYS IOMUX CFG SAIF SYSCFG PADCFG 372: GPIO21"] - pub padcfg_gpio21: PADCFG_GPIO21, - #[doc = "0x178 - SYS IOMUX CFG SAIF SYSCFG PADCFG 376: GPIO22"] - pub padcfg_gpio22: PADCFG_GPIO22, - #[doc = "0x17c - SYS IOMUX CFG SAIF SYSCFG PADCFG 380: GPIO23"] - pub padcfg_gpio23: PADCFG_GPIO23, - #[doc = "0x180 - SYS IOMUX CFG SAIF SYSCFG PADCFG 384: GPIO24"] - pub padcfg_gpio24: PADCFG_GPIO24, - #[doc = "0x184 - SYS IOMUX CFG SAIF SYSCFG PADCFG 388: GPIO25"] - pub padcfg_gpio25: PADCFG_GPIO25, - #[doc = "0x188 - SYS IOMUX CFG SAIF SYSCFG PADCFG 392: GPIO26"] - pub padcfg_gpio26: PADCFG_GPIO26, - #[doc = "0x18c - SYS IOMUX CFG SAIF SYSCFG PADCFG 396: GPIO27"] - pub padcfg_gpio27: PADCFG_GPIO27, - #[doc = "0x190 - SYS IOMUX CFG SAIF SYSCFG PADCFG 400: GPIO28"] - pub padcfg_gpio28: PADCFG_GPIO28, - #[doc = "0x194 - SYS IOMUX CFG SAIF SYSCFG PADCFG 404: GPIO29"] - pub padcfg_gpio29: PADCFG_GPIO29, - #[doc = "0x198 - SYS IOMUX CFG SAIF SYSCFG PADCFG 408: GPIO30"] - pub padcfg_gpio30: PADCFG_GPIO30, - #[doc = "0x19c - SYS IOMUX CFG SAIF SYSCFG PADCFG 412: GPIO31"] - pub padcfg_gpio31: PADCFG_GPIO31, - #[doc = "0x1a0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 416: GPIO32"] - pub padcfg_gpio32: PADCFG_GPIO32, - #[doc = "0x1a4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 420: GPIO33"] - pub padcfg_gpio33: PADCFG_GPIO33, - #[doc = "0x1a8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 424: GPIO34"] - pub padcfg_gpio34: PADCFG_GPIO34, - #[doc = "0x1ac - SYS IOMUX CFG SAIF SYSCFG PADCFG 428: GPIO35"] - pub padcfg_gpio35: PADCFG_GPIO35, - #[doc = "0x1b0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 432: GPIO36"] - pub padcfg_gpio36: PADCFG_GPIO36, - #[doc = "0x1b4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 436: GPIO37"] - pub padcfg_gpio37: PADCFG_GPIO37, - #[doc = "0x1b8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 440: GPIO38"] - pub padcfg_gpio38: PADCFG_GPIO38, - #[doc = "0x1bc - SYS IOMUX CFG SAIF SYSCFG PADCFG 444: GPIO39"] - pub padcfg_gpio39: PADCFG_GPIO39, - #[doc = "0x1c0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 448: GPIO40"] - pub padcfg_gpio40: PADCFG_GPIO40, - #[doc = "0x1c4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 452: GPIO41"] - pub padcfg_gpio41: PADCFG_GPIO41, - #[doc = "0x1c8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 456: GPIO42"] - pub padcfg_gpio42: PADCFG_GPIO42, - #[doc = "0x1cc - SYS IOMUX CFG SAIF SYSCFG PADCFG 460: GPIO43"] - pub padcfg_gpio43: PADCFG_GPIO43, - #[doc = "0x1d0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 464: GPIO44"] - pub padcfg_gpio44: PADCFG_GPIO44, - #[doc = "0x1d4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 468: GPIO45"] - pub padcfg_gpio45: PADCFG_GPIO45, - #[doc = "0x1d8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 472: GPIO46"] - pub padcfg_gpio46: PADCFG_GPIO46, - #[doc = "0x1dc - SYS IOMUX CFG SAIF SYSCFG PADCFG 476: GPIO47"] - pub padcfg_gpio47: PADCFG_GPIO47, - #[doc = "0x1e0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 480: GPIO48"] - pub padcfg_gpio48: PADCFG_GPIO48, - #[doc = "0x1e4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 484: GPIO49"] - pub padcfg_gpio49: PADCFG_GPIO49, - #[doc = "0x1e8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 488: GPIO50"] - pub padcfg_gpio50: PADCFG_GPIO50, - #[doc = "0x1ec - SYS IOMUX CFG SAIF SYSCFG PADCFG 492: GPIO51"] - pub padcfg_gpio51: PADCFG_GPIO51, - #[doc = "0x1f0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 496: GPIO52"] - pub padcfg_gpio52: PADCFG_GPIO52, - #[doc = "0x1f4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 500: GPIO53"] - pub padcfg_gpio53: PADCFG_GPIO53, - #[doc = "0x1f8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 504: GPIO54"] - pub padcfg_gpio54: PADCFG_GPIO54, - #[doc = "0x1fc - SYS IOMUX CFG SAIF SYSCFG PADCFG 508: GPIO55"] - pub padcfg_gpio55: PADCFG_GPIO55, - #[doc = "0x200 - SYS IOMUX CFG SAIF SYSCFG PADCFG 512: GPIO56"] - pub padcfg_gpio56: PADCFG_GPIO56, - #[doc = "0x204 - SYS IOMUX CFG SAIF SYSCFG PADCFG 516: GPIO57"] - pub padcfg_gpio57: PADCFG_GPIO57, - #[doc = "0x208 - SYS IOMUX CFG SAIF SYSCFG PADCFG 520: GPIO58"] - pub padcfg_gpio58: PADCFG_GPIO58, - #[doc = "0x20c - SYS IOMUX CFG SAIF SYSCFG PADCFG 524: GPIO59"] - pub padcfg_gpio59: PADCFG_GPIO59, - #[doc = "0x210 - SYS IOMUX CFG SAIF SYSCFG PADCFG 528: GPIO60"] - pub padcfg_gpio60: PADCFG_GPIO60, - #[doc = "0x214 - SYS IOMUX CFG SAIF SYSCFG PADCFG 532: GPIO61"] - pub padcfg_gpio61: PADCFG_GPIO61, - #[doc = "0x218 - SYS IOMUX CFG SAIF SYSCFG PADCFG 536: GPIO62"] - pub padcfg_gpio62: PADCFG_GPIO62, - #[doc = "0x21c - SYS IOMUX CFG SAIF SYSCFG PADCFG 540: GPIO63"] - pub padcfg_gpio63: PADCFG_GPIO63, - #[doc = "0x220 - SYS IOMUX CFG SAIF SYSCFG PADCFG 544: SD0_CLK"] - pub padcfg_sd0_clk: PADCFG_SD0_CLK, - #[doc = "0x224 - SYS IOMUX CFG SAIF SYSCFG PADCFG 548: SD0_CMD"] - pub padcfg_sd0_cmd: PADCFG_SD0_CMD, - #[doc = "0x228 - SYS IOMUX CFG SAIF SYSCFG PADCFG 552: SD0_DATA0"] - pub padcfg_sd0_data0: PADCFG_SD0_DATA0, + padcfg_gpio0: PADCFG_GPIO0, + padcfg_gpio1: PADCFG_GPIO1, + padcfg_gpio2: PADCFG_GPIO2, + padcfg_gpio3: PADCFG_GPIO3, + padcfg_gpio4: PADCFG_GPIO4, + padcfg_gpio5: PADCFG_GPIO5, + padcfg_gpio6: PADCFG_GPIO6, + padcfg_gpio7: PADCFG_GPIO7, + padcfg_gpio8: PADCFG_GPIO8, + padcfg_gpio9: PADCFG_GPIO9, + padcfg_gpio10: PADCFG_GPIO10, + padcfg_gpio11: PADCFG_GPIO11, + padcfg_gpio12: PADCFG_GPIO12, + padcfg_gpio13: PADCFG_GPIO13, + padcfg_gpio14: PADCFG_GPIO14, + padcfg_gpio15: PADCFG_GPIO15, + padcfg_gpio16: PADCFG_GPIO16, + padcfg_gpio17: PADCFG_GPIO17, + padcfg_gpio18: PADCFG_GPIO18, + padcfg_gpio19: PADCFG_GPIO19, + padcfg_gpio20: PADCFG_GPIO20, + padcfg_gpio21: PADCFG_GPIO21, + padcfg_gpio22: PADCFG_GPIO22, + padcfg_gpio23: PADCFG_GPIO23, + padcfg_gpio24: PADCFG_GPIO24, + padcfg_gpio25: PADCFG_GPIO25, + padcfg_gpio26: PADCFG_GPIO26, + padcfg_gpio27: PADCFG_GPIO27, + padcfg_gpio28: PADCFG_GPIO28, + padcfg_gpio29: PADCFG_GPIO29, + padcfg_gpio30: PADCFG_GPIO30, + padcfg_gpio31: PADCFG_GPIO31, + padcfg_gpio32: PADCFG_GPIO32, + padcfg_gpio33: PADCFG_GPIO33, + padcfg_gpio34: PADCFG_GPIO34, + padcfg_gpio35: PADCFG_GPIO35, + padcfg_gpio36: PADCFG_GPIO36, + padcfg_gpio37: PADCFG_GPIO37, + padcfg_gpio38: PADCFG_GPIO38, + padcfg_gpio39: PADCFG_GPIO39, + padcfg_gpio40: PADCFG_GPIO40, + padcfg_gpio41: PADCFG_GPIO41, + padcfg_gpio42: PADCFG_GPIO42, + padcfg_gpio43: PADCFG_GPIO43, + padcfg_gpio44: PADCFG_GPIO44, + padcfg_gpio45: PADCFG_GPIO45, + padcfg_gpio46: PADCFG_GPIO46, + padcfg_gpio47: PADCFG_GPIO47, + padcfg_gpio48: PADCFG_GPIO48, + padcfg_gpio49: PADCFG_GPIO49, + padcfg_gpio50: PADCFG_GPIO50, + padcfg_gpio51: PADCFG_GPIO51, + padcfg_gpio52: PADCFG_GPIO52, + padcfg_gpio53: PADCFG_GPIO53, + padcfg_gpio54: PADCFG_GPIO54, + padcfg_gpio55: PADCFG_GPIO55, + padcfg_gpio56: PADCFG_GPIO56, + padcfg_gpio57: PADCFG_GPIO57, + padcfg_gpio58: PADCFG_GPIO58, + padcfg_gpio59: PADCFG_GPIO59, + padcfg_gpio60: PADCFG_GPIO60, + padcfg_gpio61: PADCFG_GPIO61, + padcfg_gpio62: PADCFG_GPIO62, + padcfg_gpio63: PADCFG_GPIO63, + padcfg_sd0_clk: PADCFG_SD0_CLK, + padcfg_sd0_cmd: PADCFG_SD0_CMD, + padcfg_sd0_data0: PADCFG_SD0_DATA0, _reserved105: [u8; 0x0c], - #[doc = "0x238 - SYS IOMUX CFG SAIF SYSCFG PADCFG 568: SD0_DATA1"] - pub padcfg_sd0_data1: PADCFG_SD0_DATA1, + padcfg_sd0_data1: PADCFG_SD0_DATA1, _reserved106: [u8; 0x0c], _reserved_106_padcfg_sd0: [u8; 0x04], _reserved107: [u8; 0x0c], - #[doc = "0x258 - SYS IOMUX CFG SAIF SYSCFG PADCFG 600: SD0_DATA3"] - pub padcfg_sd0_data3: PADCFG_SD0_DATA3, + padcfg_sd0_data3: PADCFG_SD0_DATA3, _reserved108: [u8; 0x0c], - #[doc = "0x268 - SYS IOMUX CFG SAIF SYSCFG PADCFG 616: SD0_DATA4"] - pub padcfg_sd0_data4: PADCFG_SD0_DATA4, + padcfg_sd0_data4: PADCFG_SD0_DATA4, _reserved109: [u8; 0x0c], - #[doc = "0x278 - SYS IOMUX CFG SAIF SYSCFG PADCFG 632: SD0_DATA5"] - pub padcfg_sd0_data5: PADCFG_SD0_DATA5, + padcfg_sd0_data5: PADCFG_SD0_DATA5, _reserved110: [u8; 0x08], - #[doc = "0x284 - SYS IOMUX CFG SAIF SYSCFG PADCFG 644: QSPI_SCLK"] - pub padcfg_qspi_sclk: PADCFG_QSPI_SCLK, + padcfg_qspi_sclk: PADCFG_QSPI_SCLK, _reserved_111_padcfg: [u8; 0x04], - #[doc = "0x28c - SYS IOMUX CFG SAIF SYSCFG PADCFG 652: QSPI_DATA0"] - pub padcfg_qspi_data0: PADCFG_QSPI_DATA0, + padcfg_qspi_data0: PADCFG_QSPI_DATA0, _reserved113: [u8; 0x08], - #[doc = "0x298 - SYS IOMUX CFG SAIF SYSCFG PADCFG 664: SD0_DATA7"] - pub padcfg_sd0_data7: PADCFG_SD0_DATA7, + padcfg_sd0_data7: PADCFG_SD0_DATA7, _reserved_114_func_sel0: [u8; 0x04], - #[doc = "0x2a0 - SYS IOMUX CFG SAIF SYSCFG 1"] - pub func_sel1: FUNC_SEL1, - #[doc = "0x2a4 - SYS IOMUX CFG SAIF SYSCFG 2"] - pub func_sel2: FUNC_SEL2, - #[doc = "0x2a8 - SYS IOMUX CFG SAIF SYSCFG 3"] - pub func_sel3: FUNC_SEL3, + func_sel1: FUNC_SEL1, + func_sel2: FUNC_SEL2, + func_sel3: FUNC_SEL3, _reserved_118_func_sel4: [u8; 0x04], - #[doc = "0x2b0 - SYS IOMUX CFG SAIF SYSCFG 5"] - pub func_sel5: FUNC_SEL5, - #[doc = "0x2b4 - SYS IOMUX CFG SAIF SYSCFG 6"] - pub func_sel6: FUNC_SEL6, + func_sel5: FUNC_SEL5, + func_sel6: FUNC_SEL6, _reserved121: [u8; 0x04], - #[doc = "0x2bc - SYS IOMUX CFG SAIF SYSCFG PADCFG 700: QSPI_DATA3"] - pub padcfg_qspi_data3: PADCFG_QSPI_DATA3, + padcfg_qspi_data3: PADCFG_QSPI_DATA3, } impl RegisterBlock { + #[doc = "0x00 - SYS IOMUX CFG SAIF SYSCFG FMUX 0 DOEN"] + #[inline(always)] + pub const fn gpo_doen0(&self) -> &GPO_DOEN0 { + &self.gpo_doen0 + } + #[doc = "0x04 - SYS IOMUX CFG SAIF SYSCFG FMUX 1 DOEN"] + #[inline(always)] + pub const fn gpo_doen1(&self) -> &GPO_DOEN1 { + &self.gpo_doen1 + } + #[doc = "0x08 - SYS IOMUX CFG SAIF SYSCFG FMUX 2 DOEN"] + #[inline(always)] + pub const fn gpo_doen2(&self) -> &GPO_DOEN2 { + &self.gpo_doen2 + } + #[doc = "0x0c - SYS IOMUX CFG SAIF SYSCFG FMUX 3 DOEN"] + #[inline(always)] + pub const fn gpo_doen3(&self) -> &GPO_DOEN3 { + &self.gpo_doen3 + } + #[doc = "0x10 - SYS IOMUX CFG SAIF SYSCFG FMUX 4 DOEN"] + #[inline(always)] + pub const fn gpo_doen4(&self) -> &GPO_DOEN4 { + &self.gpo_doen4 + } + #[doc = "0x14 - SYS IOMUX CFG SAIF SYSCFG FMUX 5 DOEN"] + #[inline(always)] + pub const fn gpo_doen5(&self) -> &GPO_DOEN5 { + &self.gpo_doen5 + } + #[doc = "0x18 - SYS IOMUX CFG SAIF SYSCFG FMUX 6 DOEN"] + #[inline(always)] + pub const fn gpo_doen6(&self) -> &GPO_DOEN6 { + &self.gpo_doen6 + } + #[doc = "0x1c - SYS IOMUX CFG SAIF SYSCFG FMUX 7 DOEN"] + #[inline(always)] + pub const fn gpo_doen7(&self) -> &GPO_DOEN7 { + &self.gpo_doen7 + } + #[doc = "0x20 - SYS IOMUX CFG SAIF SYSCFG FMUX 8 DOEN"] + #[inline(always)] + pub const fn gpo_doen8(&self) -> &GPO_DOEN8 { + &self.gpo_doen8 + } + #[doc = "0x24 - SYS IOMUX CFG SAIF SYSCFG FMUX 9 DOEN"] + #[inline(always)] + pub const fn gpo_doen9(&self) -> &GPO_DOEN9 { + &self.gpo_doen9 + } + #[doc = "0x28 - SYS IOMUX CFG SAIF SYSCFG FMUX 10 DOEN"] + #[inline(always)] + pub const fn gpo_doen10(&self) -> &GPO_DOEN10 { + &self.gpo_doen10 + } + #[doc = "0x2c - SYS IOMUX CFG SAIF SYSCFG FMUX 11 DOEN"] + #[inline(always)] + pub const fn gpo_doen11(&self) -> &GPO_DOEN11 { + &self.gpo_doen11 + } + #[doc = "0x30 - SYS IOMUX CFG SAIF SYSCFG FMUX 12 DOEN"] + #[inline(always)] + pub const fn gpo_doen12(&self) -> &GPO_DOEN12 { + &self.gpo_doen12 + } + #[doc = "0x34 - SYS IOMUX CFG SAIF SYSCFG FMUX 13 DOEN"] + #[inline(always)] + pub const fn gpo_doen13(&self) -> &GPO_DOEN13 { + &self.gpo_doen13 + } #[doc = "0x38 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 56: GPIO Interrupt Edge Trigger Selector"] #[inline(always)] pub const fn ioirq1(&self) -> &IOIRQ1 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x38 - SYS IOMUX CFG SAIF SYSCFG FMUX 14 DOEN"] #[inline(always)] pub const fn gpo_doen14(&self) -> &GPO_DOEN14 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x39 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 57: GPIO Interrupt Edge Trigger Selector"] #[inline(always)] pub const fn ioirq2(&self) -> &IOIRQ2 { - unsafe { &*(self as *const Self).cast::().add(57usize).cast() } + unsafe { &*(self as *const Self).cast::().add(57).cast() } } #[doc = "0x3a - SYS IOMUX CFGSAIF SYSCFG IOIRQ 58: GPIO Interrupt Clear"] #[inline(always)] pub const fn ioirq3(&self) -> &IOIRQ3 { - unsafe { &*(self as *const Self).cast::().add(58usize).cast() } + unsafe { &*(self as *const Self).cast::().add(58).cast() } } #[doc = "0x3b - SYS IOMUX CFGSAIF SYSCFG IOIRQ 59: GPIO Interrupt Clear"] #[inline(always)] pub const fn ioirq4(&self) -> &IOIRQ4 { - unsafe { &*(self as *const Self).cast::().add(59usize).cast() } + unsafe { &*(self as *const Self).cast::().add(59).cast() } } #[doc = "0x3c - SYS IOMUX CFGSAIF SYSCFG IOIRQ 60: GPIO Interrupt Both Edge Trigger Selector"] #[inline(always)] pub const fn ioirq5(&self) -> &IOIRQ5 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x3c - SYS IOMUX CFG SAIF SYSCFG FMUX 15 DOEN"] #[inline(always)] pub const fn gpo_doen15(&self) -> &GPO_DOEN15 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x3d - SYS IOMUX CFGSAIF SYSCFG IOIRQ 61: GPIO Interrupt Both Edge Trigger Selector"] #[inline(always)] pub const fn ioirq6(&self) -> &IOIRQ6 { - unsafe { &*(self as *const Self).cast::().add(61usize).cast() } + unsafe { &*(self as *const Self).cast::().add(61).cast() } } #[doc = "0x3e - SYS IOMUX CFGSAIF SYSCFG IOIRQ 62: GPIO Interrupt Edge Value"] #[inline(always)] pub const fn ioirq7(&self) -> &IOIRQ7 { - unsafe { &*(self as *const Self).cast::().add(62usize).cast() } + unsafe { &*(self as *const Self).cast::().add(62).cast() } } #[doc = "0x3f - SYS IOMUX CFGSAIF SYSCFG IOIRQ 63: GPIO Interrupt Edge Value"] #[inline(always)] pub const fn ioirq8(&self) -> &IOIRQ8 { - unsafe { &*(self as *const Self).cast::().add(63usize).cast() } + unsafe { &*(self as *const Self).cast::().add(63).cast() } } #[doc = "0x40 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 64: GPIO Interrupt Edge Mask Selector"] #[inline(always)] pub const fn ioirq9(&self) -> &IOIRQ9 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x40 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 0-3 DOUT"] #[inline(always)] pub const fn gpo_dout0_3(&self) -> &GPO_DOUT0_3 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x41 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 65: GPIO Interrupt Edge Mask Selector"] #[inline(always)] pub const fn ioirq10(&self) -> &IOIRQ10 { - unsafe { &*(self as *const Self).cast::().add(65usize).cast() } + unsafe { &*(self as *const Self).cast::().add(65).cast() } } #[doc = "0x42 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 66: GPIO Register Interrupt Status"] #[inline(always)] pub const fn ioirq11(&self) -> &IOIRQ11 { - unsafe { &*(self as *const Self).cast::().add(66usize).cast() } + unsafe { &*(self as *const Self).cast::().add(66).cast() } } #[doc = "0x43 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 67: GPIO Register Interrupt Status"] #[inline(always)] pub const fn ioirq12(&self) -> &IOIRQ12 { - unsafe { &*(self as *const Self).cast::().add(67usize).cast() } + unsafe { &*(self as *const Self).cast::().add(67).cast() } } #[doc = "0x44 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 68: GPIO Masked Interrupt Status"] #[inline(always)] pub const fn ioirq13(&self) -> &IOIRQ13 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x44 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 4-7 DOUT"] #[inline(always)] pub const fn gpo_dout4_7(&self) -> &GPO_DOUT4_7 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x45 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 69: GPIO Masked Interrupt Status"] #[inline(always)] pub const fn ioirq14(&self) -> &IOIRQ14 { - unsafe { &*(self as *const Self).cast::().add(69usize).cast() } + unsafe { &*(self as *const Self).cast::().add(69).cast() } } #[doc = "0x46 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 70: GPIO Synchronization Status"] #[inline(always)] pub const fn ioirq15(&self) -> &IOIRQ15 { - unsafe { &*(self as *const Self).cast::().add(70usize).cast() } + unsafe { &*(self as *const Self).cast::().add(70).cast() } } #[doc = "0x47 - SYS IOMUX CFGSAIF SYSCFG IOIRQ 71: GPIO Synchronization Status"] #[inline(always)] pub const fn ioirq16(&self) -> &IOIRQ16 { - unsafe { &*(self as *const Self).cast::().add(71usize).cast() } + unsafe { &*(self as *const Self).cast::().add(71).cast() } } #[doc = "0x48 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 8-11 DOUT"] #[inline(always)] pub const fn gpo_dout8_11(&self) -> &GPO_DOUT8_11 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x4b - GPIO GMAC1 MDC Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_mdc_syscon(&self) -> &PADCFG_GMAC1_MDC_SYSCON { - unsafe { &*(self as *const Self).cast::().add(75usize).cast() } + unsafe { &*(self as *const Self).cast::().add(75).cast() } } #[doc = "0x4c - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 12-15 DOUT"] #[inline(always)] pub const fn gpo_dout12_15(&self) -> &GPO_DOUT12_15 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x4f - GPIO GMAC1 MDIO Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_mdio_syscon(&self) -> &PADCFG_GMAC1_MDIO_SYSCON { - unsafe { &*(self as *const Self).cast::().add(79usize).cast() } + unsafe { &*(self as *const Self).cast::().add(79).cast() } } #[doc = "0x50 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 16-19 DOUT"] #[inline(always)] pub const fn gpo_dout16_19(&self) -> &GPO_DOUT16_19 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x53 - GPIO GMAC1 RXD0 Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_rxd0_syscon(&self) -> &PADCFG_GMAC1_RXD0_SYSCON { - unsafe { &*(self as *const Self).cast::().add(83usize).cast() } + unsafe { &*(self as *const Self).cast::().add(83).cast() } } #[doc = "0x54 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 20-23 DOUT"] #[inline(always)] pub const fn gpo_dout20_23(&self) -> &GPO_DOUT20_23 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x57 - GPIO GMAC1 RXD1 Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_rxd1_syscon(&self) -> &PADCFG_GMAC1_RXD1_SYSCON { - unsafe { &*(self as *const Self).cast::().add(87usize).cast() } + unsafe { &*(self as *const Self).cast::().add(87).cast() } } #[doc = "0x58 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 24-27 DOUT"] #[inline(always)] pub const fn gpo_dout24_27(&self) -> &GPO_DOUT24_27 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x5b - GPIO GMAC1 RXD2 Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_rxd2_syscon(&self) -> &PADCFG_GMAC1_RXD2_SYSCON { - unsafe { &*(self as *const Self).cast::().add(91usize).cast() } + unsafe { &*(self as *const Self).cast::().add(91).cast() } } #[doc = "0x5c - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 28-31 DOUT"] #[inline(always)] pub const fn gpo_dout28_31(&self) -> &GPO_DOUT28_31 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x5f - GPIO GMAC1 RXD3 Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_rxd3_syscon(&self) -> &PADCFG_GMAC1_RXD3_SYSCON { - unsafe { &*(self as *const Self).cast::().add(95usize).cast() } + unsafe { &*(self as *const Self).cast::().add(95).cast() } } #[doc = "0x60 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 32-35 DOUT"] #[inline(always)] pub const fn gpo_dout32_35(&self) -> &GPO_DOUT32_35 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x63 - GPIO GMAC1 RXDV Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_rxdv_syscon(&self) -> &PADCFG_GMAC1_RXDV_SYSCON { - unsafe { &*(self as *const Self).cast::().add(99usize).cast() } + unsafe { &*(self as *const Self).cast::().add(99).cast() } } #[doc = "0x64 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 36-39 DOUT"] #[inline(always)] pub const fn gpo_dout36_39(&self) -> &GPO_DOUT36_39 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x67 - GPIO GMAC1 RXC Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_rxc_syscon(&self) -> &PADCFG_GMAC1_RXC_SYSCON { - unsafe { &*(self as *const Self).cast::().add(103usize).cast() } + unsafe { &*(self as *const Self).cast::().add(103).cast() } } #[doc = "0x68 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 40-43 DOUT"] #[inline(always)] pub const fn gpo_dout40_43(&self) -> &GPO_DOUT40_43 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x6b - GPIO GMAC1 TXD0 Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_txd0_syscon(&self) -> &PADCFG_GMAC1_TXD0_SYSCON { - unsafe { &*(self as *const Self).cast::().add(107usize).cast() } + unsafe { &*(self as *const Self).cast::().add(107).cast() } } #[doc = "0x6c - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 44-47 DOUT"] #[inline(always)] pub const fn gpo_dout44_47(&self) -> &GPO_DOUT44_47 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } } #[doc = "0x6f - GPIO GMAC1 TXD1 Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_txd1_syscon(&self) -> &PADCFG_GMAC1_TXD1_SYSCON { - unsafe { &*(self as *const Self).cast::().add(111usize).cast() } + unsafe { &*(self as *const Self).cast::().add(111).cast() } } #[doc = "0x70 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 48-51 DOUT"] #[inline(always)] pub const fn gpo_dout48_51(&self) -> &GPO_DOUT48_51 { - unsafe { &*(self as *const Self).cast::().add(112usize).cast() } + unsafe { &*(self as *const Self).cast::().add(112).cast() } } #[doc = "0x73 - GPIO GMAC1 TXD2 Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_txd2_syscon(&self) -> &PADCFG_GMAC1_TXD2_SYSCON { - unsafe { &*(self as *const Self).cast::().add(115usize).cast() } + unsafe { &*(self as *const Self).cast::().add(115).cast() } } #[doc = "0x74 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 52-55 DOUT"] #[inline(always)] pub const fn gpo_dout52_55(&self) -> &GPO_DOUT52_55 { - unsafe { &*(self as *const Self).cast::().add(116usize).cast() } + unsafe { &*(self as *const Self).cast::().add(116).cast() } } #[doc = "0x77 - GPIO GMAC1 TXD3 Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_txd3_syscon(&self) -> &PADCFG_GMAC1_TXD3_SYSCON { - unsafe { &*(self as *const Self).cast::().add(119usize).cast() } + unsafe { &*(self as *const Self).cast::().add(119).cast() } } #[doc = "0x78 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 56-59 DOUT"] #[inline(always)] pub const fn gpo_dout56_59(&self) -> &GPO_DOUT56_59 { - unsafe { &*(self as *const Self).cast::().add(120usize).cast() } + unsafe { &*(self as *const Self).cast::().add(120).cast() } } #[doc = "0x7b - GPIO GMAC1 TXEN Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_txen_syscon(&self) -> &PADCFG_GMAC1_TXEN_SYSCON { - unsafe { &*(self as *const Self).cast::().add(123usize).cast() } + unsafe { &*(self as *const Self).cast::().add(123).cast() } } #[doc = "0x7c - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 60-63 DOUT"] #[inline(always)] pub const fn gpo_dout60_63(&self) -> &GPO_DOUT60_63 { - unsafe { &*(self as *const Self).cast::().add(124usize).cast() } + unsafe { &*(self as *const Self).cast::().add(124).cast() } } #[doc = "0x7f - GPIO GMAC1 TXC Pad Configuration"] #[inline(always)] pub const fn padcfg_gmac1_txc_syscon(&self) -> &PADCFG_GMAC1_TXC_SYSCON { - unsafe { &*(self as *const Self).cast::().add(127usize).cast() } + unsafe { &*(self as *const Self).cast::().add(127).cast() } } #[doc = "0x80 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 0 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] #[inline(always)] pub const fn gpi0(&self) -> &GPI0 { - unsafe { &*(self as *const Self).cast::().add(128usize).cast() } + unsafe { &*(self as *const Self).cast::().add(128).cast() } + } + #[doc = "0x84 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 4 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi4(&self) -> &GPI4 { + &self.gpi4 + } + #[doc = "0x88 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 8 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi8(&self) -> &GPI8 { + &self.gpi8 + } + #[doc = "0x8c - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 12 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi12(&self) -> &GPI12 { + &self.gpi12 + } + #[doc = "0x90 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 16 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi16(&self) -> &GPI16 { + &self.gpi16 + } + #[doc = "0x94 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 20 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi20(&self) -> &GPI20 { + &self.gpi20 + } + #[doc = "0x98 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 24 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi24(&self) -> &GPI24 { + &self.gpi24 + } + #[doc = "0x9c - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 28 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi28(&self) -> &GPI28 { + &self.gpi28 + } + #[doc = "0xa0 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 32 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi32(&self) -> &GPI32 { + &self.gpi32 + } + #[doc = "0xa4 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 36 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi36(&self) -> &GPI36 { + &self.gpi36 + } + #[doc = "0xa8 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 40 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi40(&self) -> &GPI40 { + &self.gpi40 + } + #[doc = "0xac - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 44 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi44(&self) -> &GPI44 { + &self.gpi44 + } + #[doc = "0xb0 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 48 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi48(&self) -> &GPI48 { + &self.gpi48 + } + #[doc = "0xb4 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 52 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi52(&self) -> &GPI52 { + &self.gpi52 + } + #[doc = "0xb8 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 56 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi56(&self) -> &GPI56 { + &self.gpi56 + } + #[doc = "0xbc - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 60 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi60(&self) -> &GPI60 { + &self.gpi60 + } + #[doc = "0xc0 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 64 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi64(&self) -> &GPI64 { + &self.gpi64 + } + #[doc = "0xc4 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 68 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi68(&self) -> &GPI68 { + &self.gpi68 + } + #[doc = "0xc8 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 72 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi72(&self) -> &GPI72 { + &self.gpi72 + } + #[doc = "0xcc - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 76 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi76(&self) -> &GPI76 { + &self.gpi76 + } + #[doc = "0xd0 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 80 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi80(&self) -> &GPI80 { + &self.gpi80 + } + #[doc = "0xd4 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 84 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi84(&self) -> &GPI84 { + &self.gpi84 + } + #[doc = "0xd8 - SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 88 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] + #[inline(always)] + pub const fn gpi88(&self) -> &GPI88 { + &self.gpi88 + } + #[doc = "0xdc - Enable GPIO IRQ function"] + #[inline(always)] + pub const fn ioirq0(&self) -> &IOIRQ0 { + &self.ioirq0 + } + #[doc = "0x120 - SYS IOMUX CFG SAIF SYSCFG PADCFG 288: GPIO0"] + #[inline(always)] + pub const fn padcfg_gpio0(&self) -> &PADCFG_GPIO0 { + &self.padcfg_gpio0 + } + #[doc = "0x124 - SYS IOMUX CFG SAIF SYSCFG PADCFG 292: GPIO1"] + #[inline(always)] + pub const fn padcfg_gpio1(&self) -> &PADCFG_GPIO1 { + &self.padcfg_gpio1 + } + #[doc = "0x128 - SYS IOMUX CFG SAIF SYSCFG PADCFG 296: GPIO2"] + #[inline(always)] + pub const fn padcfg_gpio2(&self) -> &PADCFG_GPIO2 { + &self.padcfg_gpio2 + } + #[doc = "0x12c - SYS IOMUX CFG SAIF SYSCFG PADCFG 300: GPIO3"] + #[inline(always)] + pub const fn padcfg_gpio3(&self) -> &PADCFG_GPIO3 { + &self.padcfg_gpio3 + } + #[doc = "0x130 - SYS IOMUX CFG SAIF SYSCFG PADCFG 304: GPIO4"] + #[inline(always)] + pub const fn padcfg_gpio4(&self) -> &PADCFG_GPIO4 { + &self.padcfg_gpio4 + } + #[doc = "0x134 - SYS IOMUX CFG SAIF SYSCFG PADCFG 308: GPIO5"] + #[inline(always)] + pub const fn padcfg_gpio5(&self) -> &PADCFG_GPIO5 { + &self.padcfg_gpio5 + } + #[doc = "0x138 - SYS IOMUX CFG SAIF SYSCFG PADCFG 312: GPIO6"] + #[inline(always)] + pub const fn padcfg_gpio6(&self) -> &PADCFG_GPIO6 { + &self.padcfg_gpio6 + } + #[doc = "0x13c - SYS IOMUX CFG SAIF SYSCFG PADCFG 316: GPIO7"] + #[inline(always)] + pub const fn padcfg_gpio7(&self) -> &PADCFG_GPIO7 { + &self.padcfg_gpio7 + } + #[doc = "0x140 - SYS IOMUX CFG SAIF SYSCFG PADCFG 320: GPIO8"] + #[inline(always)] + pub const fn padcfg_gpio8(&self) -> &PADCFG_GPIO8 { + &self.padcfg_gpio8 + } + #[doc = "0x144 - SYS IOMUX CFG SAIF SYSCFG PADCFG 324: GPIO9"] + #[inline(always)] + pub const fn padcfg_gpio9(&self) -> &PADCFG_GPIO9 { + &self.padcfg_gpio9 + } + #[doc = "0x148 - SYS IOMUX CFG SAIF SYSCFG PADCFG 328: GPIO10"] + #[inline(always)] + pub const fn padcfg_gpio10(&self) -> &PADCFG_GPIO10 { + &self.padcfg_gpio10 + } + #[doc = "0x14c - SYS IOMUX CFG SAIF SYSCFG PADCFG 332: GPIO11"] + #[inline(always)] + pub const fn padcfg_gpio11(&self) -> &PADCFG_GPIO11 { + &self.padcfg_gpio11 + } + #[doc = "0x150 - SYS IOMUX CFG SAIF SYSCFG PADCFG 336: GPIO12"] + #[inline(always)] + pub const fn padcfg_gpio12(&self) -> &PADCFG_GPIO12 { + &self.padcfg_gpio12 + } + #[doc = "0x154 - SYS IOMUX CFG SAIF SYSCFG PADCFG 340: GPIO13"] + #[inline(always)] + pub const fn padcfg_gpio13(&self) -> &PADCFG_GPIO13 { + &self.padcfg_gpio13 + } + #[doc = "0x158 - SYS IOMUX CFG SAIF SYSCFG PADCFG 344: GPIO14"] + #[inline(always)] + pub const fn padcfg_gpio14(&self) -> &PADCFG_GPIO14 { + &self.padcfg_gpio14 + } + #[doc = "0x15c - SYS IOMUX CFG SAIF SYSCFG PADCFG 348: GPIO15"] + #[inline(always)] + pub const fn padcfg_gpio15(&self) -> &PADCFG_GPIO15 { + &self.padcfg_gpio15 + } + #[doc = "0x160 - SYS IOMUX CFG SAIF SYSCFG PADCFG 352: GPIO16"] + #[inline(always)] + pub const fn padcfg_gpio16(&self) -> &PADCFG_GPIO16 { + &self.padcfg_gpio16 + } + #[doc = "0x164 - SYS IOMUX CFG SAIF SYSCFG PADCFG 356: GPIO17"] + #[inline(always)] + pub const fn padcfg_gpio17(&self) -> &PADCFG_GPIO17 { + &self.padcfg_gpio17 + } + #[doc = "0x168 - SYS IOMUX CFG SAIF SYSCFG PADCFG 360: GPIO18"] + #[inline(always)] + pub const fn padcfg_gpio18(&self) -> &PADCFG_GPIO18 { + &self.padcfg_gpio18 + } + #[doc = "0x16c - SYS IOMUX CFG SAIF SYSCFG PADCFG 364: GPIO19"] + #[inline(always)] + pub const fn padcfg_gpio19(&self) -> &PADCFG_GPIO19 { + &self.padcfg_gpio19 + } + #[doc = "0x170 - SYS IOMUX CFG SAIF SYSCFG PADCFG 368: GPIO20"] + #[inline(always)] + pub const fn padcfg_gpio20(&self) -> &PADCFG_GPIO20 { + &self.padcfg_gpio20 + } + #[doc = "0x174 - SYS IOMUX CFG SAIF SYSCFG PADCFG 372: GPIO21"] + #[inline(always)] + pub const fn padcfg_gpio21(&self) -> &PADCFG_GPIO21 { + &self.padcfg_gpio21 + } + #[doc = "0x178 - SYS IOMUX CFG SAIF SYSCFG PADCFG 376: GPIO22"] + #[inline(always)] + pub const fn padcfg_gpio22(&self) -> &PADCFG_GPIO22 { + &self.padcfg_gpio22 + } + #[doc = "0x17c - SYS IOMUX CFG SAIF SYSCFG PADCFG 380: GPIO23"] + #[inline(always)] + pub const fn padcfg_gpio23(&self) -> &PADCFG_GPIO23 { + &self.padcfg_gpio23 + } + #[doc = "0x180 - SYS IOMUX CFG SAIF SYSCFG PADCFG 384: GPIO24"] + #[inline(always)] + pub const fn padcfg_gpio24(&self) -> &PADCFG_GPIO24 { + &self.padcfg_gpio24 + } + #[doc = "0x184 - SYS IOMUX CFG SAIF SYSCFG PADCFG 388: GPIO25"] + #[inline(always)] + pub const fn padcfg_gpio25(&self) -> &PADCFG_GPIO25 { + &self.padcfg_gpio25 + } + #[doc = "0x188 - SYS IOMUX CFG SAIF SYSCFG PADCFG 392: GPIO26"] + #[inline(always)] + pub const fn padcfg_gpio26(&self) -> &PADCFG_GPIO26 { + &self.padcfg_gpio26 + } + #[doc = "0x18c - SYS IOMUX CFG SAIF SYSCFG PADCFG 396: GPIO27"] + #[inline(always)] + pub const fn padcfg_gpio27(&self) -> &PADCFG_GPIO27 { + &self.padcfg_gpio27 + } + #[doc = "0x190 - SYS IOMUX CFG SAIF SYSCFG PADCFG 400: GPIO28"] + #[inline(always)] + pub const fn padcfg_gpio28(&self) -> &PADCFG_GPIO28 { + &self.padcfg_gpio28 + } + #[doc = "0x194 - SYS IOMUX CFG SAIF SYSCFG PADCFG 404: GPIO29"] + #[inline(always)] + pub const fn padcfg_gpio29(&self) -> &PADCFG_GPIO29 { + &self.padcfg_gpio29 + } + #[doc = "0x198 - SYS IOMUX CFG SAIF SYSCFG PADCFG 408: GPIO30"] + #[inline(always)] + pub const fn padcfg_gpio30(&self) -> &PADCFG_GPIO30 { + &self.padcfg_gpio30 + } + #[doc = "0x19c - SYS IOMUX CFG SAIF SYSCFG PADCFG 412: GPIO31"] + #[inline(always)] + pub const fn padcfg_gpio31(&self) -> &PADCFG_GPIO31 { + &self.padcfg_gpio31 + } + #[doc = "0x1a0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 416: GPIO32"] + #[inline(always)] + pub const fn padcfg_gpio32(&self) -> &PADCFG_GPIO32 { + &self.padcfg_gpio32 + } + #[doc = "0x1a4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 420: GPIO33"] + #[inline(always)] + pub const fn padcfg_gpio33(&self) -> &PADCFG_GPIO33 { + &self.padcfg_gpio33 + } + #[doc = "0x1a8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 424: GPIO34"] + #[inline(always)] + pub const fn padcfg_gpio34(&self) -> &PADCFG_GPIO34 { + &self.padcfg_gpio34 + } + #[doc = "0x1ac - SYS IOMUX CFG SAIF SYSCFG PADCFG 428: GPIO35"] + #[inline(always)] + pub const fn padcfg_gpio35(&self) -> &PADCFG_GPIO35 { + &self.padcfg_gpio35 + } + #[doc = "0x1b0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 432: GPIO36"] + #[inline(always)] + pub const fn padcfg_gpio36(&self) -> &PADCFG_GPIO36 { + &self.padcfg_gpio36 + } + #[doc = "0x1b4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 436: GPIO37"] + #[inline(always)] + pub const fn padcfg_gpio37(&self) -> &PADCFG_GPIO37 { + &self.padcfg_gpio37 + } + #[doc = "0x1b8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 440: GPIO38"] + #[inline(always)] + pub const fn padcfg_gpio38(&self) -> &PADCFG_GPIO38 { + &self.padcfg_gpio38 + } + #[doc = "0x1bc - SYS IOMUX CFG SAIF SYSCFG PADCFG 444: GPIO39"] + #[inline(always)] + pub const fn padcfg_gpio39(&self) -> &PADCFG_GPIO39 { + &self.padcfg_gpio39 + } + #[doc = "0x1c0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 448: GPIO40"] + #[inline(always)] + pub const fn padcfg_gpio40(&self) -> &PADCFG_GPIO40 { + &self.padcfg_gpio40 + } + #[doc = "0x1c4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 452: GPIO41"] + #[inline(always)] + pub const fn padcfg_gpio41(&self) -> &PADCFG_GPIO41 { + &self.padcfg_gpio41 + } + #[doc = "0x1c8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 456: GPIO42"] + #[inline(always)] + pub const fn padcfg_gpio42(&self) -> &PADCFG_GPIO42 { + &self.padcfg_gpio42 + } + #[doc = "0x1cc - SYS IOMUX CFG SAIF SYSCFG PADCFG 460: GPIO43"] + #[inline(always)] + pub const fn padcfg_gpio43(&self) -> &PADCFG_GPIO43 { + &self.padcfg_gpio43 + } + #[doc = "0x1d0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 464: GPIO44"] + #[inline(always)] + pub const fn padcfg_gpio44(&self) -> &PADCFG_GPIO44 { + &self.padcfg_gpio44 + } + #[doc = "0x1d4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 468: GPIO45"] + #[inline(always)] + pub const fn padcfg_gpio45(&self) -> &PADCFG_GPIO45 { + &self.padcfg_gpio45 + } + #[doc = "0x1d8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 472: GPIO46"] + #[inline(always)] + pub const fn padcfg_gpio46(&self) -> &PADCFG_GPIO46 { + &self.padcfg_gpio46 + } + #[doc = "0x1dc - SYS IOMUX CFG SAIF SYSCFG PADCFG 476: GPIO47"] + #[inline(always)] + pub const fn padcfg_gpio47(&self) -> &PADCFG_GPIO47 { + &self.padcfg_gpio47 + } + #[doc = "0x1e0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 480: GPIO48"] + #[inline(always)] + pub const fn padcfg_gpio48(&self) -> &PADCFG_GPIO48 { + &self.padcfg_gpio48 + } + #[doc = "0x1e4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 484: GPIO49"] + #[inline(always)] + pub const fn padcfg_gpio49(&self) -> &PADCFG_GPIO49 { + &self.padcfg_gpio49 + } + #[doc = "0x1e8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 488: GPIO50"] + #[inline(always)] + pub const fn padcfg_gpio50(&self) -> &PADCFG_GPIO50 { + &self.padcfg_gpio50 + } + #[doc = "0x1ec - SYS IOMUX CFG SAIF SYSCFG PADCFG 492: GPIO51"] + #[inline(always)] + pub const fn padcfg_gpio51(&self) -> &PADCFG_GPIO51 { + &self.padcfg_gpio51 + } + #[doc = "0x1f0 - SYS IOMUX CFG SAIF SYSCFG PADCFG 496: GPIO52"] + #[inline(always)] + pub const fn padcfg_gpio52(&self) -> &PADCFG_GPIO52 { + &self.padcfg_gpio52 + } + #[doc = "0x1f4 - SYS IOMUX CFG SAIF SYSCFG PADCFG 500: GPIO53"] + #[inline(always)] + pub const fn padcfg_gpio53(&self) -> &PADCFG_GPIO53 { + &self.padcfg_gpio53 + } + #[doc = "0x1f8 - SYS IOMUX CFG SAIF SYSCFG PADCFG 504: GPIO54"] + #[inline(always)] + pub const fn padcfg_gpio54(&self) -> &PADCFG_GPIO54 { + &self.padcfg_gpio54 + } + #[doc = "0x1fc - SYS IOMUX CFG SAIF SYSCFG PADCFG 508: GPIO55"] + #[inline(always)] + pub const fn padcfg_gpio55(&self) -> &PADCFG_GPIO55 { + &self.padcfg_gpio55 + } + #[doc = "0x200 - SYS IOMUX CFG SAIF SYSCFG PADCFG 512: GPIO56"] + #[inline(always)] + pub const fn padcfg_gpio56(&self) -> &PADCFG_GPIO56 { + &self.padcfg_gpio56 + } + #[doc = "0x204 - SYS IOMUX CFG SAIF SYSCFG PADCFG 516: GPIO57"] + #[inline(always)] + pub const fn padcfg_gpio57(&self) -> &PADCFG_GPIO57 { + &self.padcfg_gpio57 + } + #[doc = "0x208 - SYS IOMUX CFG SAIF SYSCFG PADCFG 520: GPIO58"] + #[inline(always)] + pub const fn padcfg_gpio58(&self) -> &PADCFG_GPIO58 { + &self.padcfg_gpio58 + } + #[doc = "0x20c - SYS IOMUX CFG SAIF SYSCFG PADCFG 524: GPIO59"] + #[inline(always)] + pub const fn padcfg_gpio59(&self) -> &PADCFG_GPIO59 { + &self.padcfg_gpio59 + } + #[doc = "0x210 - SYS IOMUX CFG SAIF SYSCFG PADCFG 528: GPIO60"] + #[inline(always)] + pub const fn padcfg_gpio60(&self) -> &PADCFG_GPIO60 { + &self.padcfg_gpio60 + } + #[doc = "0x214 - SYS IOMUX CFG SAIF SYSCFG PADCFG 532: GPIO61"] + #[inline(always)] + pub const fn padcfg_gpio61(&self) -> &PADCFG_GPIO61 { + &self.padcfg_gpio61 + } + #[doc = "0x218 - SYS IOMUX CFG SAIF SYSCFG PADCFG 536: GPIO62"] + #[inline(always)] + pub const fn padcfg_gpio62(&self) -> &PADCFG_GPIO62 { + &self.padcfg_gpio62 + } + #[doc = "0x21c - SYS IOMUX CFG SAIF SYSCFG PADCFG 540: GPIO63"] + #[inline(always)] + pub const fn padcfg_gpio63(&self) -> &PADCFG_GPIO63 { + &self.padcfg_gpio63 + } + #[doc = "0x220 - SYS IOMUX CFG SAIF SYSCFG PADCFG 544: SD0_CLK"] + #[inline(always)] + pub const fn padcfg_sd0_clk(&self) -> &PADCFG_SD0_CLK { + &self.padcfg_sd0_clk + } + #[doc = "0x224 - SYS IOMUX CFG SAIF SYSCFG PADCFG 548: SD0_CMD"] + #[inline(always)] + pub const fn padcfg_sd0_cmd(&self) -> &PADCFG_SD0_CMD { + &self.padcfg_sd0_cmd + } + #[doc = "0x228 - SYS IOMUX CFG SAIF SYSCFG PADCFG 552: SD0_DATA0"] + #[inline(always)] + pub const fn padcfg_sd0_data0(&self) -> &PADCFG_SD0_DATA0 { + &self.padcfg_sd0_data0 + } + #[doc = "0x238 - SYS IOMUX CFG SAIF SYSCFG PADCFG 568: SD0_DATA1"] + #[inline(always)] + pub const fn padcfg_sd0_data1(&self) -> &PADCFG_SD0_DATA1 { + &self.padcfg_sd0_data1 } #[doc = "0x248 - SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_STRB"] #[inline(always)] pub const fn padcfg_sd0_strb(&self) -> &PADCFG_SD0_STRB { - unsafe { &*(self as *const Self).cast::().add(584usize).cast() } + unsafe { &*(self as *const Self).cast::().add(584).cast() } } #[doc = "0x248 - SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_DATA2"] #[inline(always)] pub const fn padcfg_sd0_data2(&self) -> &PADCFG_SD0_DATA2 { - unsafe { &*(self as *const Self).cast::().add(584usize).cast() } + unsafe { &*(self as *const Self).cast::().add(584).cast() } + } + #[doc = "0x258 - SYS IOMUX CFG SAIF SYSCFG PADCFG 600: SD0_DATA3"] + #[inline(always)] + pub const fn padcfg_sd0_data3(&self) -> &PADCFG_SD0_DATA3 { + &self.padcfg_sd0_data3 + } + #[doc = "0x268 - SYS IOMUX CFG SAIF SYSCFG PADCFG 616: SD0_DATA4"] + #[inline(always)] + pub const fn padcfg_sd0_data4(&self) -> &PADCFG_SD0_DATA4 { + &self.padcfg_sd0_data4 + } + #[doc = "0x278 - SYS IOMUX CFG SAIF SYSCFG PADCFG 632: SD0_DATA5"] + #[inline(always)] + pub const fn padcfg_sd0_data5(&self) -> &PADCFG_SD0_DATA5 { + &self.padcfg_sd0_data5 + } + #[doc = "0x284 - SYS IOMUX CFG SAIF SYSCFG PADCFG 644: QSPI_SCLK"] + #[inline(always)] + pub const fn padcfg_qspi_sclk(&self) -> &PADCFG_QSPI_SCLK { + &self.padcfg_qspi_sclk } #[doc = "0x288 - SYS IOMUX CFG SAIF SYSCFG PADCFG 648: QSPI_CSN0"] #[inline(always)] pub const fn padcfg_qspi_csn0(&self) -> &PADCFG_QSPI_CSN0 { - unsafe { &*(self as *const Self).cast::().add(648usize).cast() } + unsafe { &*(self as *const Self).cast::().add(648).cast() } } #[doc = "0x288 - SYS IOMUX CFG SAIF SYSCFG PADCFG 648: SD0_DATA6"] #[inline(always)] pub const fn padcfg_sd0_data6(&self) -> &PADCFG_SD0_DATA6 { - unsafe { &*(self as *const Self).cast::().add(648usize).cast() } + unsafe { &*(self as *const Self).cast::().add(648).cast() } + } + #[doc = "0x28c - SYS IOMUX CFG SAIF SYSCFG PADCFG 652: QSPI_DATA0"] + #[inline(always)] + pub const fn padcfg_qspi_data0(&self) -> &PADCFG_QSPI_DATA0 { + &self.padcfg_qspi_data0 + } + #[doc = "0x298 - SYS IOMUX CFG SAIF SYSCFG PADCFG 664: SD0_DATA7"] + #[inline(always)] + pub const fn padcfg_sd0_data7(&self) -> &PADCFG_SD0_DATA7 { + &self.padcfg_sd0_data7 } #[doc = "0x29c - SYS IOMUX CFG SAIF SYSCFG 0"] #[inline(always)] pub const fn func_sel0(&self) -> &FUNC_SEL0 { - unsafe { &*(self as *const Self).cast::().add(668usize).cast() } + unsafe { &*(self as *const Self).cast::().add(668).cast() } } #[doc = "0x29c - SYS IOMUX CFG SAIF SYSCFG PADCFG 668: QSPI_DATA1"] #[inline(always)] pub const fn padcfg_qspi_data1(&self) -> &PADCFG_QSPI_DATA1 { - unsafe { &*(self as *const Self).cast::().add(668usize).cast() } + unsafe { &*(self as *const Self).cast::().add(668).cast() } + } + #[doc = "0x2a0 - SYS IOMUX CFG SAIF SYSCFG 1"] + #[inline(always)] + pub const fn func_sel1(&self) -> &FUNC_SEL1 { + &self.func_sel1 + } + #[doc = "0x2a4 - SYS IOMUX CFG SAIF SYSCFG 2"] + #[inline(always)] + pub const fn func_sel2(&self) -> &FUNC_SEL2 { + &self.func_sel2 + } + #[doc = "0x2a8 - SYS IOMUX CFG SAIF SYSCFG 3"] + #[inline(always)] + pub const fn func_sel3(&self) -> &FUNC_SEL3 { + &self.func_sel3 } #[doc = "0x2ac - SYS IOMUX CFG SAIF SYSCFG 4"] #[inline(always)] pub const fn func_sel4(&self) -> &FUNC_SEL4 { - unsafe { &*(self as *const Self).cast::().add(684usize).cast() } + unsafe { &*(self as *const Self).cast::().add(684).cast() } } #[doc = "0x2ac - SYS IOMUX CFG SAIF SYSCFG PADCFG 684: QSPI_DATA2"] #[inline(always)] pub const fn padcfg_qspi_data2(&self) -> &PADCFG_QSPI_DATA2 { - unsafe { &*(self as *const Self).cast::().add(684usize).cast() } + unsafe { &*(self as *const Self).cast::().add(684).cast() } + } + #[doc = "0x2b0 - SYS IOMUX CFG SAIF SYSCFG 5"] + #[inline(always)] + pub const fn func_sel5(&self) -> &FUNC_SEL5 { + &self.func_sel5 + } + #[doc = "0x2b4 - SYS IOMUX CFG SAIF SYSCFG 6"] + #[inline(always)] + pub const fn func_sel6(&self) -> &FUNC_SEL6 { + &self.func_sel6 + } + #[doc = "0x2bc - SYS IOMUX CFG SAIF SYSCFG PADCFG 700: QSPI_DATA3"] + #[inline(always)] + pub const fn padcfg_qspi_data3(&self) -> &PADCFG_QSPI_DATA3 { + &self.padcfg_qspi_data3 } } -#[doc = "gpo_doen0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 0 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen0`] +#[doc = "gpo_doen0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 0 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen0`] module"] pub type GPO_DOEN0 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 0 DOEN"] pub mod gpo_doen0; -#[doc = "gpo_doen1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 1 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen1`] +#[doc = "gpo_doen1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 1 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen1`] module"] pub type GPO_DOEN1 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 1 DOEN"] pub mod gpo_doen1; -#[doc = "gpo_doen2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 2 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen2`] +#[doc = "gpo_doen2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 2 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen2`] module"] pub type GPO_DOEN2 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 2 DOEN"] pub mod gpo_doen2; -#[doc = "gpo_doen3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 3 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen3`] +#[doc = "gpo_doen3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 3 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen3`] module"] pub type GPO_DOEN3 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 3 DOEN"] pub mod gpo_doen3; -#[doc = "gpo_doen4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 4 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen4`] +#[doc = "gpo_doen4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 4 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen4`] module"] pub type GPO_DOEN4 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 4 DOEN"] pub mod gpo_doen4; -#[doc = "gpo_doen5 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 5 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen5`] +#[doc = "gpo_doen5 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 5 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen5`] module"] pub type GPO_DOEN5 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 5 DOEN"] pub mod gpo_doen5; -#[doc = "gpo_doen6 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 6 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen6`] +#[doc = "gpo_doen6 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 6 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen6`] module"] pub type GPO_DOEN6 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 6 DOEN"] pub mod gpo_doen6; -#[doc = "gpo_doen7 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 7 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen7`] +#[doc = "gpo_doen7 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 7 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen7`] module"] pub type GPO_DOEN7 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 7 DOEN"] pub mod gpo_doen7; -#[doc = "gpo_doen8 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 8 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen8`] +#[doc = "gpo_doen8 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 8 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen8`] module"] pub type GPO_DOEN8 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 8 DOEN"] pub mod gpo_doen8; -#[doc = "gpo_doen9 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 9 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen9`] +#[doc = "gpo_doen9 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 9 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen9`] module"] pub type GPO_DOEN9 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 9 DOEN"] pub mod gpo_doen9; -#[doc = "gpo_doen10 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 10 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen10`] +#[doc = "gpo_doen10 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 10 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen10`] module"] pub type GPO_DOEN10 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 10 DOEN"] pub mod gpo_doen10; -#[doc = "gpo_doen11 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 11 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen11`] +#[doc = "gpo_doen11 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 11 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen11`] module"] pub type GPO_DOEN11 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 11 DOEN"] pub mod gpo_doen11; -#[doc = "gpo_doen12 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 12 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen12`] +#[doc = "gpo_doen12 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 12 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen12`] module"] pub type GPO_DOEN12 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 12 DOEN"] pub mod gpo_doen12; -#[doc = "gpo_doen13 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 13 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen13`] +#[doc = "gpo_doen13 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 13 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen13`] module"] pub type GPO_DOEN13 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 13 DOEN"] pub mod gpo_doen13; -#[doc = "gpo_doen14 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 14 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen14`] +#[doc = "gpo_doen14 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 14 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen14`] module"] pub type GPO_DOEN14 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 14 DOEN"] pub mod gpo_doen14; -#[doc = "gpo_doen15 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 15 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_doen15`] +#[doc = "gpo_doen15 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX 15 DOEN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_doen15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_doen15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_doen15`] module"] pub type GPO_DOEN15 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX 15 DOEN"] pub mod gpo_doen15; -#[doc = "gpo_dout0_3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 0-3 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout0_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout0_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout0_3`] +#[doc = "gpo_dout0_3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 0-3 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout0_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout0_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout0_3`] module"] pub type GPO_DOUT0_3 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 0-3 DOUT"] pub mod gpo_dout0_3; -#[doc = "gpo_dout4_7 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 4-7 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout4_7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout4_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout4_7`] +#[doc = "gpo_dout4_7 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 4-7 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout4_7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout4_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout4_7`] module"] pub type GPO_DOUT4_7 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 4-7 DOUT"] pub mod gpo_dout4_7; -#[doc = "gpo_dout8_11 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 8-11 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout8_11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout8_11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout8_11`] +#[doc = "gpo_dout8_11 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 8-11 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout8_11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout8_11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout8_11`] module"] pub type GPO_DOUT8_11 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 8-11 DOUT"] pub mod gpo_dout8_11; -#[doc = "gpo_dout12_15 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 12-15 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout12_15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout12_15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout12_15`] +#[doc = "gpo_dout12_15 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 12-15 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout12_15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout12_15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout12_15`] module"] pub type GPO_DOUT12_15 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 12-15 DOUT"] pub mod gpo_dout12_15; -#[doc = "gpo_dout16_19 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 16-19 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout16_19::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout16_19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout16_19`] +#[doc = "gpo_dout16_19 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 16-19 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout16_19::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout16_19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout16_19`] module"] pub type GPO_DOUT16_19 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 16-19 DOUT"] pub mod gpo_dout16_19; -#[doc = "gpo_dout20_23 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 20-23 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout20_23::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout20_23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout20_23`] +#[doc = "gpo_dout20_23 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 20-23 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout20_23::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout20_23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout20_23`] module"] pub type GPO_DOUT20_23 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 20-23 DOUT"] pub mod gpo_dout20_23; -#[doc = "gpo_dout24_27 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 24-27 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout24_27::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout24_27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout24_27`] +#[doc = "gpo_dout24_27 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 24-27 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout24_27::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout24_27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout24_27`] module"] pub type GPO_DOUT24_27 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 24-27 DOUT"] pub mod gpo_dout24_27; -#[doc = "gpo_dout28_31 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 28-31 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout28_31::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout28_31::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout28_31`] +#[doc = "gpo_dout28_31 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 28-31 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout28_31::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout28_31::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout28_31`] module"] pub type GPO_DOUT28_31 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 28-31 DOUT"] pub mod gpo_dout28_31; -#[doc = "gpo_dout32_35 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 32-35 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout32_35::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout32_35::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout32_35`] +#[doc = "gpo_dout32_35 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 32-35 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout32_35::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout32_35::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout32_35`] module"] pub type GPO_DOUT32_35 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 32-35 DOUT"] pub mod gpo_dout32_35; -#[doc = "gpo_dout36_39 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 36-39 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout36_39::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout36_39::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout36_39`] +#[doc = "gpo_dout36_39 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 36-39 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout36_39::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout36_39::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout36_39`] module"] pub type GPO_DOUT36_39 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 36-39 DOUT"] pub mod gpo_dout36_39; -#[doc = "gpo_dout40_43 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 40-43 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout40_43::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout40_43::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout40_43`] +#[doc = "gpo_dout40_43 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 40-43 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout40_43::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout40_43::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout40_43`] module"] pub type GPO_DOUT40_43 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 40-43 DOUT"] pub mod gpo_dout40_43; -#[doc = "gpo_dout44_47 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 44-47 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout44_47::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout44_47::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout44_47`] +#[doc = "gpo_dout44_47 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 44-47 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout44_47::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout44_47::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout44_47`] module"] pub type GPO_DOUT44_47 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 44-47 DOUT"] pub mod gpo_dout44_47; -#[doc = "gpo_dout48_51 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 48-51 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout48_51::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout48_51::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout48_51`] +#[doc = "gpo_dout48_51 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 48-51 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout48_51::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout48_51::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout48_51`] module"] pub type GPO_DOUT48_51 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 48-51 DOUT"] pub mod gpo_dout48_51; -#[doc = "gpo_dout52_55 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 52-55 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout52_55::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout52_55::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout52_55`] +#[doc = "gpo_dout52_55 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 52-55 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout52_55::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout52_55::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout52_55`] module"] pub type GPO_DOUT52_55 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 52-55 DOUT"] pub mod gpo_dout52_55; -#[doc = "gpo_dout56_59 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 56-59 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout56_59::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout56_59::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout56_59`] +#[doc = "gpo_dout56_59 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 56-59 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout56_59::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout56_59::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout56_59`] module"] pub type GPO_DOUT56_59 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 56-59 DOUT"] pub mod gpo_dout56_59; -#[doc = "gpo_dout60_63 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 60-63 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout60_63::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout60_63::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpo_dout60_63`] +#[doc = "gpo_dout60_63 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 60-63 DOUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpo_dout60_63::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpo_dout60_63::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpo_dout60_63`] module"] pub type GPO_DOUT60_63 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 60-63 DOUT"] pub mod gpo_dout60_63; -#[doc = "gpi0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 0 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi0`] +#[doc = "gpi0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 0 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi0`] module"] pub type GPI0 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 0 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi0; -#[doc = "gpi4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 4 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi4`] +#[doc = "gpi4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 4 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi4`] module"] pub type GPI4 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 4 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi4; -#[doc = "gpi8 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 8 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi8`] +#[doc = "gpi8 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 8 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi8`] module"] pub type GPI8 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 8 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi8; -#[doc = "gpi12 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 12 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi12`] +#[doc = "gpi12 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 12 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi12`] module"] pub type GPI12 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 12 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi12; -#[doc = "gpi16 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 16 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi16`] +#[doc = "gpi16 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 16 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi16`] module"] pub type GPI16 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 16 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi16; -#[doc = "gpi20 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 20 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi20::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi20`] +#[doc = "gpi20 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 20 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi20::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi20`] module"] pub type GPI20 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 20 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi20; -#[doc = "gpi24 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 24 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi24::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi24`] +#[doc = "gpi24 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 24 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi24::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi24`] module"] pub type GPI24 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 24 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi24; -#[doc = "gpi28 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 28 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi28::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi28`] +#[doc = "gpi28 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 28 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi28::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi28`] module"] pub type GPI28 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 28 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi28; -#[doc = "gpi32 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 32 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi32::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi32`] +#[doc = "gpi32 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 32 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi32::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi32`] module"] pub type GPI32 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 32 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi32; -#[doc = "gpi36 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 36 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi36::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi36`] +#[doc = "gpi36 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 36 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi36::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi36`] module"] pub type GPI36 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 36 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi36; -#[doc = "gpi40 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 40 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi40::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi40`] +#[doc = "gpi40 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 40 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi40::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi40`] module"] pub type GPI40 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 40 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi40; -#[doc = "gpi44 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 44 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi44::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi44`] +#[doc = "gpi44 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 44 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi44::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi44`] module"] pub type GPI44 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 44 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi44; -#[doc = "gpi48 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 48 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi48::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi48`] +#[doc = "gpi48 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 48 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi48::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi48`] module"] pub type GPI48 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 48 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi48; -#[doc = "gpi52 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 52 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi52::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi52`] +#[doc = "gpi52 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 52 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi52::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi52`] module"] pub type GPI52 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 52 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi52; -#[doc = "gpi56 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 56 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi56::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi56`] +#[doc = "gpi56 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 56 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi56::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi56`] module"] pub type GPI56 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 56 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi56; -#[doc = "gpi60 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 60 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi60::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi60`] +#[doc = "gpi60 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 60 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi60::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi60`] module"] pub type GPI60 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 60 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi60; -#[doc = "gpi64 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 64 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi64::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi64`] +#[doc = "gpi64 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 64 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi64::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi64`] module"] pub type GPI64 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 64 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi64; -#[doc = "gpi68 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 68 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi68::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi68`] +#[doc = "gpi68 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 68 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi68::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi68`] module"] pub type GPI68 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 68 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi68; -#[doc = "gpi72 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 72 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi72::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi72::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi72`] +#[doc = "gpi72 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 72 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi72::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi72::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi72`] module"] pub type GPI72 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 72 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi72; -#[doc = "gpi76 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 76 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi76::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi76`] +#[doc = "gpi76 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 76 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi76::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi76`] module"] pub type GPI76 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 76 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi76; -#[doc = "gpi80 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 80 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi80::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi80::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi80`] +#[doc = "gpi80 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 80 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi80::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi80::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi80`] module"] pub type GPI80 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 80 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi80; -#[doc = "gpi84 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 84 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi84::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi84`] +#[doc = "gpi84 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 84 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi84::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi84`] module"] pub type GPI84 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 84 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi84; -#[doc = "gpi88 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 88 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi88::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gpi88`] +#[doc = "gpi88 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 88 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpi88::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpi88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpi88`] module"] pub type GPI88 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 88 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the \"Name\" column of the following table per StarFive naming conventions. For example, name \"u0_WAVE511_i_uart_rxsin_cfg\" indicates the corresponding input signal is \"u0_WAVE511.i_uart_rxsin\". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals."] pub mod gpi88; -#[doc = "ioirq0 (rw) register accessor: Enable GPIO IRQ function\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq0`] +#[doc = "ioirq0 (rw) register accessor: Enable GPIO IRQ function\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq0`] module"] pub type IOIRQ0 = crate::Reg; #[doc = "Enable GPIO IRQ function"] pub mod ioirq0; -#[doc = "ioirq1 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 56: GPIO Interrupt Edge Trigger Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq1`] +#[doc = "ioirq1 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 56: GPIO Interrupt Edge Trigger Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq1`] module"] pub type IOIRQ1 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 56: GPIO Interrupt Edge Trigger Selector"] pub mod ioirq1; -#[doc = "ioirq2 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 57: GPIO Interrupt Edge Trigger Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq2`] +#[doc = "ioirq2 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 57: GPIO Interrupt Edge Trigger Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq2`] module"] pub type IOIRQ2 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 57: GPIO Interrupt Edge Trigger Selector"] pub mod ioirq2; -#[doc = "ioirq3 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 58: GPIO Interrupt Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq3`] +#[doc = "ioirq3 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 58: GPIO Interrupt Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq3`] module"] pub type IOIRQ3 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 58: GPIO Interrupt Clear"] pub mod ioirq3; -#[doc = "ioirq4 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 59: GPIO Interrupt Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq4`] +#[doc = "ioirq4 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 59: GPIO Interrupt Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq4`] module"] pub type IOIRQ4 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 59: GPIO Interrupt Clear"] pub mod ioirq4; -#[doc = "ioirq5 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 60: GPIO Interrupt Both Edge Trigger Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq5`] +#[doc = "ioirq5 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 60: GPIO Interrupt Both Edge Trigger Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq5`] module"] pub type IOIRQ5 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 60: GPIO Interrupt Both Edge Trigger Selector"] pub mod ioirq5; -#[doc = "ioirq6 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 61: GPIO Interrupt Both Edge Trigger Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq6`] +#[doc = "ioirq6 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 61: GPIO Interrupt Both Edge Trigger Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq6`] module"] pub type IOIRQ6 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 61: GPIO Interrupt Both Edge Trigger Selector"] pub mod ioirq6; -#[doc = "ioirq7 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 62: GPIO Interrupt Edge Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq7`] +#[doc = "ioirq7 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 62: GPIO Interrupt Edge Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq7`] module"] pub type IOIRQ7 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 62: GPIO Interrupt Edge Value"] pub mod ioirq7; -#[doc = "ioirq8 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 63: GPIO Interrupt Edge Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq8`] +#[doc = "ioirq8 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 63: GPIO Interrupt Edge Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq8`] module"] pub type IOIRQ8 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 63: GPIO Interrupt Edge Value"] pub mod ioirq8; -#[doc = "ioirq9 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 64: GPIO Interrupt Edge Mask Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq9`] +#[doc = "ioirq9 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 64: GPIO Interrupt Edge Mask Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq9`] module"] pub type IOIRQ9 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 64: GPIO Interrupt Edge Mask Selector"] pub mod ioirq9; -#[doc = "ioirq10 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 65: GPIO Interrupt Edge Mask Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq10`] +#[doc = "ioirq10 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 65: GPIO Interrupt Edge Mask Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq10`] module"] pub type IOIRQ10 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 65: GPIO Interrupt Edge Mask Selector"] pub mod ioirq10; -#[doc = "ioirq11 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 66: GPIO Register Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq11`] +#[doc = "ioirq11 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 66: GPIO Register Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq11`] module"] pub type IOIRQ11 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 66: GPIO Register Interrupt Status"] pub mod ioirq11; -#[doc = "ioirq12 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 67: GPIO Register Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq12`] +#[doc = "ioirq12 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 67: GPIO Register Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq12`] module"] pub type IOIRQ12 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 67: GPIO Register Interrupt Status"] pub mod ioirq12; -#[doc = "ioirq13 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 68: GPIO Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq13`] +#[doc = "ioirq13 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 68: GPIO Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq13`] module"] pub type IOIRQ13 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 68: GPIO Masked Interrupt Status"] pub mod ioirq13; -#[doc = "ioirq14 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 69: GPIO Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq14`] +#[doc = "ioirq14 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 69: GPIO Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq14`] module"] pub type IOIRQ14 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 69: GPIO Masked Interrupt Status"] pub mod ioirq14; -#[doc = "ioirq15 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 70: GPIO Synchronization Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq15`] +#[doc = "ioirq15 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 70: GPIO Synchronization Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq15`] module"] pub type IOIRQ15 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 70: GPIO Synchronization Status"] pub mod ioirq15; -#[doc = "ioirq16 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 71: GPIO Synchronization Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ioirq16`] +#[doc = "ioirq16 (rw) register accessor: SYS IOMUX CFGSAIF SYSCFG IOIRQ 71: GPIO Synchronization Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioirq16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioirq16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioirq16`] module"] pub type IOIRQ16 = crate::Reg; #[doc = "SYS IOMUX CFGSAIF SYSCFG IOIRQ 71: GPIO Synchronization Status"] pub mod ioirq16; -#[doc = "padcfg_gpio0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 288: GPIO0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio0`] +#[doc = "padcfg_gpio0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 288: GPIO0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio0`] module"] pub type PADCFG_GPIO0 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 288: GPIO0"] pub mod padcfg_gpio0; -#[doc = "padcfg_gpio1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 292: GPIO1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio1`] +#[doc = "padcfg_gpio1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 292: GPIO1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio1`] module"] pub type PADCFG_GPIO1 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 292: GPIO1"] pub mod padcfg_gpio1; -#[doc = "padcfg_gpio2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 296: GPIO2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio2`] +#[doc = "padcfg_gpio2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 296: GPIO2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio2`] module"] pub type PADCFG_GPIO2 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 296: GPIO2"] pub mod padcfg_gpio2; -#[doc = "padcfg_gpio3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 300: GPIO3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio3`] +#[doc = "padcfg_gpio3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 300: GPIO3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio3`] module"] pub type PADCFG_GPIO3 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 300: GPIO3"] pub mod padcfg_gpio3; -#[doc = "padcfg_gpio4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 304: GPIO4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio4`] +#[doc = "padcfg_gpio4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 304: GPIO4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio4`] module"] pub type PADCFG_GPIO4 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 304: GPIO4"] pub mod padcfg_gpio4; -#[doc = "padcfg_gpio5 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 308: GPIO5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio5`] +#[doc = "padcfg_gpio5 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 308: GPIO5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio5`] module"] pub type PADCFG_GPIO5 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 308: GPIO5"] pub mod padcfg_gpio5; -#[doc = "padcfg_gpio6 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 312: GPIO6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio6`] +#[doc = "padcfg_gpio6 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 312: GPIO6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio6`] module"] pub type PADCFG_GPIO6 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 312: GPIO6"] pub mod padcfg_gpio6; -#[doc = "padcfg_gpio7 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 316: GPIO7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio7`] +#[doc = "padcfg_gpio7 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 316: GPIO7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio7`] module"] pub type PADCFG_GPIO7 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 316: GPIO7"] pub mod padcfg_gpio7; -#[doc = "padcfg_gpio8 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 320: GPIO8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio8`] +#[doc = "padcfg_gpio8 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 320: GPIO8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio8`] module"] pub type PADCFG_GPIO8 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 320: GPIO8"] pub mod padcfg_gpio8; -#[doc = "padcfg_gpio9 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 324: GPIO9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio9`] +#[doc = "padcfg_gpio9 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 324: GPIO9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio9`] module"] pub type PADCFG_GPIO9 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 324: GPIO9"] pub mod padcfg_gpio9; -#[doc = "padcfg_gpio10 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 328: GPIO10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio10`] +#[doc = "padcfg_gpio10 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 328: GPIO10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio10`] module"] pub type PADCFG_GPIO10 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 328: GPIO10"] pub mod padcfg_gpio10; -#[doc = "padcfg_gpio11 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 332: GPIO11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio11`] +#[doc = "padcfg_gpio11 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 332: GPIO11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio11`] module"] pub type PADCFG_GPIO11 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 332: GPIO11"] pub mod padcfg_gpio11; -#[doc = "padcfg_gpio12 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 336: GPIO12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio12`] +#[doc = "padcfg_gpio12 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 336: GPIO12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio12`] module"] pub type PADCFG_GPIO12 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 336: GPIO12"] pub mod padcfg_gpio12; -#[doc = "padcfg_gpio13 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 340: GPIO13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio13`] +#[doc = "padcfg_gpio13 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 340: GPIO13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio13`] module"] pub type PADCFG_GPIO13 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 340: GPIO13"] pub mod padcfg_gpio13; -#[doc = "padcfg_gpio14 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 344: GPIO14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio14`] +#[doc = "padcfg_gpio14 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 344: GPIO14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio14`] module"] pub type PADCFG_GPIO14 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 344: GPIO14"] pub mod padcfg_gpio14; -#[doc = "padcfg_gpio15 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 348: GPIO15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio15`] +#[doc = "padcfg_gpio15 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 348: GPIO15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio15`] module"] pub type PADCFG_GPIO15 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 348: GPIO15"] pub mod padcfg_gpio15; -#[doc = "padcfg_gpio16 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 352: GPIO16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio16`] +#[doc = "padcfg_gpio16 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 352: GPIO16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio16`] module"] pub type PADCFG_GPIO16 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 352: GPIO16"] pub mod padcfg_gpio16; -#[doc = "padcfg_gpio17 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 356: GPIO17\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio17::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio17::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio17`] +#[doc = "padcfg_gpio17 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 356: GPIO17\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio17::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio17::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio17`] module"] pub type PADCFG_GPIO17 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 356: GPIO17"] pub mod padcfg_gpio17; -#[doc = "padcfg_gpio18 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 360: GPIO18\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio18::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio18::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio18`] +#[doc = "padcfg_gpio18 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 360: GPIO18\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio18::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio18::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio18`] module"] pub type PADCFG_GPIO18 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 360: GPIO18"] pub mod padcfg_gpio18; -#[doc = "padcfg_gpio19 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 364: GPIO19\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio19::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio19`] +#[doc = "padcfg_gpio19 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 364: GPIO19\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio19::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio19`] module"] pub type PADCFG_GPIO19 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 364: GPIO19"] pub mod padcfg_gpio19; -#[doc = "padcfg_gpio20 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 368: GPIO20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio20::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio20`] +#[doc = "padcfg_gpio20 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 368: GPIO20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio20::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio20`] module"] pub type PADCFG_GPIO20 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 368: GPIO20"] pub mod padcfg_gpio20; -#[doc = "padcfg_gpio21 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 372: GPIO21\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio21::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio21::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio21`] +#[doc = "padcfg_gpio21 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 372: GPIO21\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio21::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio21::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio21`] module"] pub type PADCFG_GPIO21 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 372: GPIO21"] pub mod padcfg_gpio21; -#[doc = "padcfg_gpio22 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 376: GPIO22\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio22::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio22::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio22`] +#[doc = "padcfg_gpio22 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 376: GPIO22\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio22::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio22::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio22`] module"] pub type PADCFG_GPIO22 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 376: GPIO22"] pub mod padcfg_gpio22; -#[doc = "padcfg_gpio23 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 380: GPIO23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio23::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio23`] +#[doc = "padcfg_gpio23 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 380: GPIO23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio23::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio23`] module"] pub type PADCFG_GPIO23 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 380: GPIO23"] pub mod padcfg_gpio23; -#[doc = "padcfg_gpio24 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 384: GPIO24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio24::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio24`] +#[doc = "padcfg_gpio24 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 384: GPIO24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio24::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio24`] module"] pub type PADCFG_GPIO24 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 384: GPIO24"] pub mod padcfg_gpio24; -#[doc = "padcfg_gpio25 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 388: GPIO25\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio25::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio25::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio25`] +#[doc = "padcfg_gpio25 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 388: GPIO25\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio25::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio25::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio25`] module"] pub type PADCFG_GPIO25 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 388: GPIO25"] pub mod padcfg_gpio25; -#[doc = "padcfg_gpio26 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 392: GPIO26\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio26::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio26::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio26`] +#[doc = "padcfg_gpio26 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 392: GPIO26\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio26::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio26::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio26`] module"] pub type PADCFG_GPIO26 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 392: GPIO26"] pub mod padcfg_gpio26; -#[doc = "padcfg_gpio27 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 396: GPIO27\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio27::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio27`] +#[doc = "padcfg_gpio27 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 396: GPIO27\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio27::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio27`] module"] pub type PADCFG_GPIO27 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 396: GPIO27"] pub mod padcfg_gpio27; -#[doc = "padcfg_gpio28 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 400: GPIO28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio28::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio28`] +#[doc = "padcfg_gpio28 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 400: GPIO28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio28::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio28`] module"] pub type PADCFG_GPIO28 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 400: GPIO28"] pub mod padcfg_gpio28; -#[doc = "padcfg_gpio29 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 404: GPIO29\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio29::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio29::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio29`] +#[doc = "padcfg_gpio29 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 404: GPIO29\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio29::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio29::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio29`] module"] pub type PADCFG_GPIO29 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 404: GPIO29"] pub mod padcfg_gpio29; -#[doc = "padcfg_gpio30 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 408: GPIO30\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio30::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio30::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio30`] +#[doc = "padcfg_gpio30 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 408: GPIO30\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio30::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio30::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio30`] module"] pub type PADCFG_GPIO30 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 408: GPIO30"] pub mod padcfg_gpio30; -#[doc = "padcfg_gpio31 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 412: GPIO31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio31::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio31::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio31`] +#[doc = "padcfg_gpio31 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 412: GPIO31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio31::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio31::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio31`] module"] pub type PADCFG_GPIO31 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 412: GPIO31"] pub mod padcfg_gpio31; -#[doc = "padcfg_gpio32 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 416: GPIO32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio32::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio32`] +#[doc = "padcfg_gpio32 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 416: GPIO32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio32::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio32`] module"] pub type PADCFG_GPIO32 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 416: GPIO32"] pub mod padcfg_gpio32; -#[doc = "padcfg_gpio33 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 420: GPIO33\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio33::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio33::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio33`] +#[doc = "padcfg_gpio33 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 420: GPIO33\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio33::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio33::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio33`] module"] pub type PADCFG_GPIO33 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 420: GPIO33"] pub mod padcfg_gpio33; -#[doc = "padcfg_gpio34 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 424: GPIO34\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio34::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio34::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio34`] +#[doc = "padcfg_gpio34 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 424: GPIO34\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio34::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio34::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio34`] module"] pub type PADCFG_GPIO34 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 424: GPIO34"] pub mod padcfg_gpio34; -#[doc = "padcfg_gpio35 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 428: GPIO35\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio35::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio35::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio35`] +#[doc = "padcfg_gpio35 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 428: GPIO35\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio35::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio35::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio35`] module"] pub type PADCFG_GPIO35 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 428: GPIO35"] pub mod padcfg_gpio35; -#[doc = "padcfg_gpio36 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 432: GPIO36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio36::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio36`] +#[doc = "padcfg_gpio36 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 432: GPIO36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio36::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio36`] module"] pub type PADCFG_GPIO36 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 432: GPIO36"] pub mod padcfg_gpio36; -#[doc = "padcfg_gpio37 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 436: GPIO37\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio37::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio37::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio37`] +#[doc = "padcfg_gpio37 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 436: GPIO37\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio37::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio37::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio37`] module"] pub type PADCFG_GPIO37 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 436: GPIO37"] pub mod padcfg_gpio37; -#[doc = "padcfg_gpio38 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 440: GPIO38\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio38::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio38::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio38`] +#[doc = "padcfg_gpio38 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 440: GPIO38\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio38::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio38::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio38`] module"] pub type PADCFG_GPIO38 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 440: GPIO38"] pub mod padcfg_gpio38; -#[doc = "padcfg_gpio39 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 444: GPIO39\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio39::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio39::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio39`] +#[doc = "padcfg_gpio39 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 444: GPIO39\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio39::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio39::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio39`] module"] pub type PADCFG_GPIO39 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 444: GPIO39"] pub mod padcfg_gpio39; -#[doc = "padcfg_gpio40 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 448: GPIO40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio40::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio40`] +#[doc = "padcfg_gpio40 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 448: GPIO40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio40::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio40`] module"] pub type PADCFG_GPIO40 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 448: GPIO40"] pub mod padcfg_gpio40; -#[doc = "padcfg_gpio41 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 452: GPIO41\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio41::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio41::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio41`] +#[doc = "padcfg_gpio41 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 452: GPIO41\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio41::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio41::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio41`] module"] pub type PADCFG_GPIO41 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 452: GPIO41"] pub mod padcfg_gpio41; -#[doc = "padcfg_gpio42 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 456: GPIO42\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio42::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio42::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio42`] +#[doc = "padcfg_gpio42 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 456: GPIO42\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio42::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio42::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio42`] module"] pub type PADCFG_GPIO42 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 456: GPIO42"] pub mod padcfg_gpio42; -#[doc = "padcfg_gpio43 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 460: GPIO43\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio43::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio43::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio43`] +#[doc = "padcfg_gpio43 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 460: GPIO43\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio43::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio43::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio43`] module"] pub type PADCFG_GPIO43 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 460: GPIO43"] pub mod padcfg_gpio43; -#[doc = "padcfg_gpio44 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 464: GPIO44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio44::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio44`] +#[doc = "padcfg_gpio44 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 464: GPIO44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio44::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio44`] module"] pub type PADCFG_GPIO44 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 464: GPIO44"] pub mod padcfg_gpio44; -#[doc = "padcfg_gpio45 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 468: GPIO45\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio45::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio45::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio45`] +#[doc = "padcfg_gpio45 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 468: GPIO45\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio45::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio45::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio45`] module"] pub type PADCFG_GPIO45 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 468: GPIO45"] pub mod padcfg_gpio45; -#[doc = "padcfg_gpio46 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 472: GPIO46\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio46::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio46::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio46`] +#[doc = "padcfg_gpio46 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 472: GPIO46\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio46::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio46::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio46`] module"] pub type PADCFG_GPIO46 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 472: GPIO46"] pub mod padcfg_gpio46; -#[doc = "padcfg_gpio47 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 476: GPIO47\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio47::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio47::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio47`] +#[doc = "padcfg_gpio47 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 476: GPIO47\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio47::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio47::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio47`] module"] pub type PADCFG_GPIO47 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 476: GPIO47"] pub mod padcfg_gpio47; -#[doc = "padcfg_gpio48 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 480: GPIO48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio48::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio48`] +#[doc = "padcfg_gpio48 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 480: GPIO48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio48::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio48`] module"] pub type PADCFG_GPIO48 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 480: GPIO48"] pub mod padcfg_gpio48; -#[doc = "padcfg_gpio49 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 484: GPIO49\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio49::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio49::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio49`] +#[doc = "padcfg_gpio49 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 484: GPIO49\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio49::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio49::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio49`] module"] pub type PADCFG_GPIO49 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 484: GPIO49"] pub mod padcfg_gpio49; -#[doc = "padcfg_gpio50 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 488: GPIO50\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio50::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio50::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio50`] +#[doc = "padcfg_gpio50 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 488: GPIO50\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio50::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio50::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio50`] module"] pub type PADCFG_GPIO50 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 488: GPIO50"] pub mod padcfg_gpio50; -#[doc = "padcfg_gpio51 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 492: GPIO51\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio51::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio51::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio51`] +#[doc = "padcfg_gpio51 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 492: GPIO51\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio51::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio51::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio51`] module"] pub type PADCFG_GPIO51 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 492: GPIO51"] pub mod padcfg_gpio51; -#[doc = "padcfg_gpio52 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 496: GPIO52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio52::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio52`] +#[doc = "padcfg_gpio52 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 496: GPIO52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio52::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio52`] module"] pub type PADCFG_GPIO52 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 496: GPIO52"] pub mod padcfg_gpio52; -#[doc = "padcfg_gpio53 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 500: GPIO53\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio53::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio53::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio53`] +#[doc = "padcfg_gpio53 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 500: GPIO53\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio53::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio53::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio53`] module"] pub type PADCFG_GPIO53 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 500: GPIO53"] pub mod padcfg_gpio53; -#[doc = "padcfg_gpio54 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 504: GPIO54\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio54::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio54::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio54`] +#[doc = "padcfg_gpio54 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 504: GPIO54\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio54::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio54::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio54`] module"] pub type PADCFG_GPIO54 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 504: GPIO54"] pub mod padcfg_gpio54; -#[doc = "padcfg_gpio55 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 508: GPIO55\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio55::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio55::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio55`] +#[doc = "padcfg_gpio55 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 508: GPIO55\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio55::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio55::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio55`] module"] pub type PADCFG_GPIO55 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 508: GPIO55"] pub mod padcfg_gpio55; -#[doc = "padcfg_gpio56 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 512: GPIO56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio56::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio56`] +#[doc = "padcfg_gpio56 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 512: GPIO56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio56::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio56`] module"] pub type PADCFG_GPIO56 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 512: GPIO56"] pub mod padcfg_gpio56; -#[doc = "padcfg_gpio57 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 516: GPIO57\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio57::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio57::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio57`] +#[doc = "padcfg_gpio57 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 516: GPIO57\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio57::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio57::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio57`] module"] pub type PADCFG_GPIO57 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 516: GPIO57"] pub mod padcfg_gpio57; -#[doc = "padcfg_gpio58 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 520: GPIO58\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio58::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio58::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio58`] +#[doc = "padcfg_gpio58 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 520: GPIO58\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio58::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio58::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio58`] module"] pub type PADCFG_GPIO58 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 520: GPIO58"] pub mod padcfg_gpio58; -#[doc = "padcfg_gpio59 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 524: GPIO59\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio59::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio59::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio59`] +#[doc = "padcfg_gpio59 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 524: GPIO59\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio59::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio59::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio59`] module"] pub type PADCFG_GPIO59 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 524: GPIO59"] pub mod padcfg_gpio59; -#[doc = "padcfg_gpio60 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 528: GPIO60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio60::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio60`] +#[doc = "padcfg_gpio60 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 528: GPIO60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio60::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio60`] module"] pub type PADCFG_GPIO60 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 528: GPIO60"] pub mod padcfg_gpio60; -#[doc = "padcfg_gpio61 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 532: GPIO61\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio61::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio61::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio61`] +#[doc = "padcfg_gpio61 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 532: GPIO61\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio61::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio61::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio61`] module"] pub type PADCFG_GPIO61 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 532: GPIO61"] pub mod padcfg_gpio61; -#[doc = "padcfg_gpio62 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 536: GPIO62\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio62::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio62::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio62`] +#[doc = "padcfg_gpio62 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 536: GPIO62\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio62::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio62::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio62`] module"] pub type PADCFG_GPIO62 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 536: GPIO62"] pub mod padcfg_gpio62; -#[doc = "padcfg_gpio63 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 540: GPIO63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio63::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio63::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gpio63`] +#[doc = "padcfg_gpio63 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 540: GPIO63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gpio63::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gpio63::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gpio63`] module"] pub type PADCFG_GPIO63 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 540: GPIO63"] pub mod padcfg_gpio63; -#[doc = "padcfg_sd0_clk (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 544: SD0_CLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_clk`] +#[doc = "padcfg_sd0_clk (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 544: SD0_CLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_clk`] module"] pub type PADCFG_SD0_CLK = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 544: SD0_CLK"] pub mod padcfg_sd0_clk; -#[doc = "padcfg_sd0_cmd (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 548: SD0_CMD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_cmd`] +#[doc = "padcfg_sd0_cmd (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 548: SD0_CMD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_cmd`] module"] pub type PADCFG_SD0_CMD = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 548: SD0_CMD"] pub mod padcfg_sd0_cmd; -#[doc = "padcfg_sd0_data0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 552: SD0_DATA0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_data0`] +#[doc = "padcfg_sd0_data0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 552: SD0_DATA0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_data0`] module"] pub type PADCFG_SD0_DATA0 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 552: SD0_DATA0"] pub mod padcfg_sd0_data0; -#[doc = "padcfg_sd0_data1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 568: SD0_DATA1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_data1`] +#[doc = "padcfg_sd0_data1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 568: SD0_DATA1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_data1`] module"] pub type PADCFG_SD0_DATA1 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 568: SD0_DATA1"] pub mod padcfg_sd0_data1; -#[doc = "padcfg_sd0_data2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_DATA2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_data2`] +#[doc = "padcfg_sd0_data2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_DATA2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_data2`] module"] pub type PADCFG_SD0_DATA2 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_DATA2"] pub mod padcfg_sd0_data2; -#[doc = "padcfg_sd0_data3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 600: SD0_DATA3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_data3`] +#[doc = "padcfg_sd0_data3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 600: SD0_DATA3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_data3`] module"] pub type PADCFG_SD0_DATA3 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 600: SD0_DATA3"] pub mod padcfg_sd0_data3; -#[doc = "padcfg_sd0_data4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 616: SD0_DATA4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_data4`] +#[doc = "padcfg_sd0_data4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 616: SD0_DATA4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_data4`] module"] pub type PADCFG_SD0_DATA4 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 616: SD0_DATA4"] pub mod padcfg_sd0_data4; -#[doc = "padcfg_sd0_data5 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 632: SD0_DATA5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_data5`] +#[doc = "padcfg_sd0_data5 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 632: SD0_DATA5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_data5`] module"] pub type PADCFG_SD0_DATA5 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 632: SD0_DATA5"] pub mod padcfg_sd0_data5; -#[doc = "padcfg_sd0_data6 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 648: SD0_DATA6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_data6`] +#[doc = "padcfg_sd0_data6 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 648: SD0_DATA6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_data6`] module"] pub type PADCFG_SD0_DATA6 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 648: SD0_DATA6"] pub mod padcfg_sd0_data6; -#[doc = "padcfg_sd0_data7 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 664: SD0_DATA7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_data7`] +#[doc = "padcfg_sd0_data7 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 664: SD0_DATA7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_data7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_data7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_data7`] module"] pub type PADCFG_SD0_DATA7 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 664: SD0_DATA7"] pub mod padcfg_sd0_data7; -#[doc = "padcfg_sd0_strb (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_STRB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_strb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_strb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_sd0_strb`] +#[doc = "padcfg_sd0_strb (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_STRB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_sd0_strb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_sd0_strb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_sd0_strb`] module"] pub type PADCFG_SD0_STRB = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_STRB"] pub mod padcfg_sd0_strb; -#[doc = "padcfg_gmac1_mdc_syscon (rw) register accessor: GPIO GMAC1 MDC Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_mdc_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_mdc_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_mdc_syscon`] +#[doc = "padcfg_gmac1_mdc_syscon (rw) register accessor: GPIO GMAC1 MDC Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_mdc_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_mdc_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_mdc_syscon`] module"] pub type PADCFG_GMAC1_MDC_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 MDC Pad Configuration"] pub mod padcfg_gmac1_mdc_syscon; -#[doc = "padcfg_gmac1_mdio_syscon (rw) register accessor: GPIO GMAC1 MDIO Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_mdio_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_mdio_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_mdio_syscon`] +#[doc = "padcfg_gmac1_mdio_syscon (rw) register accessor: GPIO GMAC1 MDIO Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_mdio_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_mdio_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_mdio_syscon`] module"] pub type PADCFG_GMAC1_MDIO_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 MDIO Pad Configuration"] pub mod padcfg_gmac1_mdio_syscon; -#[doc = "padcfg_gmac1_rxd0_syscon (rw) register accessor: GPIO GMAC1 RXD0 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxd0_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxd0_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_rxd0_syscon`] +#[doc = "padcfg_gmac1_rxd0_syscon (rw) register accessor: GPIO GMAC1 RXD0 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxd0_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxd0_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_rxd0_syscon`] module"] pub type PADCFG_GMAC1_RXD0_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 RXD0 Pad Configuration"] pub mod padcfg_gmac1_rxd0_syscon; -#[doc = "padcfg_gmac1_rxd1_syscon (rw) register accessor: GPIO GMAC1 RXD1 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxd1_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxd1_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_rxd1_syscon`] +#[doc = "padcfg_gmac1_rxd1_syscon (rw) register accessor: GPIO GMAC1 RXD1 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxd1_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxd1_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_rxd1_syscon`] module"] pub type PADCFG_GMAC1_RXD1_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 RXD1 Pad Configuration"] pub mod padcfg_gmac1_rxd1_syscon; -#[doc = "padcfg_gmac1_rxd2_syscon (rw) register accessor: GPIO GMAC1 RXD2 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxd2_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxd2_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_rxd2_syscon`] +#[doc = "padcfg_gmac1_rxd2_syscon (rw) register accessor: GPIO GMAC1 RXD2 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxd2_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxd2_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_rxd2_syscon`] module"] pub type PADCFG_GMAC1_RXD2_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 RXD2 Pad Configuration"] pub mod padcfg_gmac1_rxd2_syscon; -#[doc = "padcfg_gmac1_rxd3_syscon (rw) register accessor: GPIO GMAC1 RXD3 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxd3_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxd3_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_rxd3_syscon`] +#[doc = "padcfg_gmac1_rxd3_syscon (rw) register accessor: GPIO GMAC1 RXD3 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxd3_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxd3_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_rxd3_syscon`] module"] pub type PADCFG_GMAC1_RXD3_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 RXD3 Pad Configuration"] pub mod padcfg_gmac1_rxd3_syscon; -#[doc = "padcfg_gmac1_rxdv_syscon (rw) register accessor: GPIO GMAC1 RXDV Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxdv_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxdv_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_rxdv_syscon`] +#[doc = "padcfg_gmac1_rxdv_syscon (rw) register accessor: GPIO GMAC1 RXDV Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxdv_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxdv_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_rxdv_syscon`] module"] pub type PADCFG_GMAC1_RXDV_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 RXDV Pad Configuration"] pub mod padcfg_gmac1_rxdv_syscon; -#[doc = "padcfg_gmac1_rxc_syscon (rw) register accessor: GPIO GMAC1 RXC Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxc_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxc_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_rxc_syscon`] +#[doc = "padcfg_gmac1_rxc_syscon (rw) register accessor: GPIO GMAC1 RXC Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_rxc_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_rxc_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_rxc_syscon`] module"] pub type PADCFG_GMAC1_RXC_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 RXC Pad Configuration"] pub mod padcfg_gmac1_rxc_syscon; -#[doc = "padcfg_gmac1_txd0_syscon (rw) register accessor: GPIO GMAC1 TXD0 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txd0_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txd0_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_txd0_syscon`] +#[doc = "padcfg_gmac1_txd0_syscon (rw) register accessor: GPIO GMAC1 TXD0 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txd0_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txd0_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_txd0_syscon`] module"] pub type PADCFG_GMAC1_TXD0_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 TXD0 Pad Configuration"] pub mod padcfg_gmac1_txd0_syscon; -#[doc = "padcfg_gmac1_txd1_syscon (rw) register accessor: GPIO GMAC1 TXD1 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txd1_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txd1_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_txd1_syscon`] +#[doc = "padcfg_gmac1_txd1_syscon (rw) register accessor: GPIO GMAC1 TXD1 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txd1_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txd1_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_txd1_syscon`] module"] pub type PADCFG_GMAC1_TXD1_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 TXD1 Pad Configuration"] pub mod padcfg_gmac1_txd1_syscon; -#[doc = "padcfg_gmac1_txd2_syscon (rw) register accessor: GPIO GMAC1 TXD2 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txd2_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txd2_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_txd2_syscon`] +#[doc = "padcfg_gmac1_txd2_syscon (rw) register accessor: GPIO GMAC1 TXD2 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txd2_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txd2_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_txd2_syscon`] module"] pub type PADCFG_GMAC1_TXD2_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 TXD2 Pad Configuration"] pub mod padcfg_gmac1_txd2_syscon; -#[doc = "padcfg_gmac1_txd3_syscon (rw) register accessor: GPIO GMAC1 TXD3 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txd3_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txd3_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_txd3_syscon`] +#[doc = "padcfg_gmac1_txd3_syscon (rw) register accessor: GPIO GMAC1 TXD3 Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txd3_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txd3_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_txd3_syscon`] module"] pub type PADCFG_GMAC1_TXD3_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 TXD3 Pad Configuration"] pub mod padcfg_gmac1_txd3_syscon; -#[doc = "padcfg_gmac1_txen_syscon (rw) register accessor: GPIO GMAC1 TXEN Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txen_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txen_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_txen_syscon`] +#[doc = "padcfg_gmac1_txen_syscon (rw) register accessor: GPIO GMAC1 TXEN Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txen_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txen_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_txen_syscon`] module"] pub type PADCFG_GMAC1_TXEN_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 TXEN Pad Configuration"] pub mod padcfg_gmac1_txen_syscon; -#[doc = "padcfg_gmac1_txc_syscon (rw) register accessor: GPIO GMAC1 TXC Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txc_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txc_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_gmac1_txc_syscon`] +#[doc = "padcfg_gmac1_txc_syscon (rw) register accessor: GPIO GMAC1 TXC Pad Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_gmac1_txc_syscon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_gmac1_txc_syscon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_gmac1_txc_syscon`] module"] pub type PADCFG_GMAC1_TXC_SYSCON = crate::Reg; #[doc = "GPIO GMAC1 TXC Pad Configuration"] pub mod padcfg_gmac1_txc_syscon; -#[doc = "padcfg_qspi_sclk (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 644: QSPI_SCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_sclk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_sclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_qspi_sclk`] +#[doc = "padcfg_qspi_sclk (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 644: QSPI_SCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_sclk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_sclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_qspi_sclk`] module"] pub type PADCFG_QSPI_SCLK = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 644: QSPI_SCLK"] pub mod padcfg_qspi_sclk; -#[doc = "padcfg_qspi_csn0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 648: QSPI_CSN0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_csn0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_csn0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_qspi_csn0`] +#[doc = "padcfg_qspi_csn0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 648: QSPI_CSN0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_csn0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_csn0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_qspi_csn0`] module"] pub type PADCFG_QSPI_CSN0 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 648: QSPI_CSN0"] pub mod padcfg_qspi_csn0; -#[doc = "padcfg_qspi_data0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 652: QSPI_DATA0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_data0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_data0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_qspi_data0`] +#[doc = "padcfg_qspi_data0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 652: QSPI_DATA0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_data0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_data0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_qspi_data0`] module"] pub type PADCFG_QSPI_DATA0 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 652: QSPI_DATA0"] pub mod padcfg_qspi_data0; -#[doc = "padcfg_qspi_data1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 668: QSPI_DATA1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_data1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_data1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_qspi_data1`] +#[doc = "padcfg_qspi_data1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 668: QSPI_DATA1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_data1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_data1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_qspi_data1`] module"] pub type PADCFG_QSPI_DATA1 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 668: QSPI_DATA1"] pub mod padcfg_qspi_data1; -#[doc = "padcfg_qspi_data2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 684: QSPI_DATA2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_data2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_data2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_qspi_data2`] +#[doc = "padcfg_qspi_data2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 684: QSPI_DATA2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_data2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_data2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_qspi_data2`] module"] pub type PADCFG_QSPI_DATA2 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 684: QSPI_DATA2"] pub mod padcfg_qspi_data2; -#[doc = "padcfg_qspi_data3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 700: QSPI_DATA3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_data3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_data3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`padcfg_qspi_data3`] +#[doc = "padcfg_qspi_data3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG PADCFG 700: QSPI_DATA3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`padcfg_qspi_data3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`padcfg_qspi_data3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@padcfg_qspi_data3`] module"] pub type PADCFG_QSPI_DATA3 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG PADCFG 700: QSPI_DATA3"] pub mod padcfg_qspi_data3; -#[doc = "func_sel0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`func_sel0`] +#[doc = "func_sel0 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func_sel0`] module"] pub type FUNC_SEL0 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG 0"] pub mod func_sel0; -#[doc = "func_sel1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`func_sel1`] +#[doc = "func_sel1 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func_sel1`] module"] pub type FUNC_SEL1 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG 1"] pub mod func_sel1; -#[doc = "func_sel2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`func_sel2`] +#[doc = "func_sel2 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func_sel2`] module"] pub type FUNC_SEL2 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG 2"] pub mod func_sel2; -#[doc = "func_sel3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`func_sel3`] +#[doc = "func_sel3 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func_sel3`] module"] pub type FUNC_SEL3 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG 3"] pub mod func_sel3; -#[doc = "func_sel4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`func_sel4`] +#[doc = "func_sel4 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func_sel4`] module"] pub type FUNC_SEL4 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG 4"] pub mod func_sel4; -#[doc = "func_sel5 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`func_sel5`] +#[doc = "func_sel5 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func_sel5`] module"] pub type FUNC_SEL5 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG 5"] pub mod func_sel5; -#[doc = "func_sel6 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`func_sel6`] +#[doc = "func_sel6 (rw) register accessor: SYS IOMUX CFG SAIF SYSCFG 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_sel6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_sel6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func_sel6`] module"] pub type FUNC_SEL6 = crate::Reg; #[doc = "SYS IOMUX CFG SAIF SYSCFG 6"] diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel0.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel0.rs index 289f275..ba518ea 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel0.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel0.rs @@ -5,47 +5,47 @@ pub type W = crate::W; #[doc = "Field `pad_gmac1_rxc_func_sel` reader - Function selector of GMAC1_RXC: * Function 0: u0_sys_crg.clk_gmac1_rgmii_rx, * Function 1: u0_sys_crg.clk_gmac1_rmii_ref, * Function 2: None, * Function 3: None"] pub type PAD_GMAC1_RXC_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gmac1_rxc_func_sel` writer - Function selector of GMAC1_RXC: * Function 0: u0_sys_crg.clk_gmac1_rgmii_rx, * Function 1: u0_sys_crg.clk_gmac1_rmii_ref, * Function 2: None, * Function 3: None"] -pub type PAD_GMAC1_RXC_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PAD_GMAC1_RXC_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pad_gpio10_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO10_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio10_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO10_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO10_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio11_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO11_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio11_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO11_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO11_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio12_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO12_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio12_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO12_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO12_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio13_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO13_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio13_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO13_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO13_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio14_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO14_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio14_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO14_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO14_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio15_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO15_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio15_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO15_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO15_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio16_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO16_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio16_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO16_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO16_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio17_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO17_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio17_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO17_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO17_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio18_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO18_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio18_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO18_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO18_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio19_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO19_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio19_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO19_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO19_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:1 - Function selector of GMAC1_RXC: * Function 0: u0_sys_crg.clk_gmac1_rgmii_rx, * Function 1: u0_sys_crg.clk_gmac1_rmii_ref, * Function 2: None, * Function 3: None"] #[inline(always)] @@ -107,70 +107,74 @@ impl W { #[doc = "Bits 0:1 - Function selector of GMAC1_RXC: * Function 0: u0_sys_crg.clk_gmac1_rgmii_rx, * Function 1: u0_sys_crg.clk_gmac1_rmii_ref, * Function 2: None, * Function 3: None"] #[inline(always)] #[must_use] - pub fn pad_gmac1_rxc_func_sel(&mut self) -> PAD_GMAC1_RXC_FUNC_SEL_W { - PAD_GMAC1_RXC_FUNC_SEL_W::new(self) + pub fn pad_gmac1_rxc_func_sel(&mut self) -> PAD_GMAC1_RXC_FUNC_SEL_W { + PAD_GMAC1_RXC_FUNC_SEL_W::new(self, 0) } #[doc = "Bits 2:4 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio10_func_sel(&mut self) -> PAD_GPIO10_FUNC_SEL_W { - PAD_GPIO10_FUNC_SEL_W::new(self) + pub fn pad_gpio10_func_sel(&mut self) -> PAD_GPIO10_FUNC_SEL_W { + PAD_GPIO10_FUNC_SEL_W::new(self, 2) } #[doc = "Bits 5:7 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio11_func_sel(&mut self) -> PAD_GPIO11_FUNC_SEL_W { - PAD_GPIO11_FUNC_SEL_W::new(self) + pub fn pad_gpio11_func_sel(&mut self) -> PAD_GPIO11_FUNC_SEL_W { + PAD_GPIO11_FUNC_SEL_W::new(self, 5) } #[doc = "Bits 8:10 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio12_func_sel(&mut self) -> PAD_GPIO12_FUNC_SEL_W { - PAD_GPIO12_FUNC_SEL_W::new(self) + pub fn pad_gpio12_func_sel(&mut self) -> PAD_GPIO12_FUNC_SEL_W { + PAD_GPIO12_FUNC_SEL_W::new(self, 8) } #[doc = "Bits 11:13 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio13_func_sel(&mut self) -> PAD_GPIO13_FUNC_SEL_W { - PAD_GPIO13_FUNC_SEL_W::new(self) + pub fn pad_gpio13_func_sel(&mut self) -> PAD_GPIO13_FUNC_SEL_W { + PAD_GPIO13_FUNC_SEL_W::new(self, 11) } #[doc = "Bits 14:16 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio14_func_sel(&mut self) -> PAD_GPIO14_FUNC_SEL_W { - PAD_GPIO14_FUNC_SEL_W::new(self) + pub fn pad_gpio14_func_sel(&mut self) -> PAD_GPIO14_FUNC_SEL_W { + PAD_GPIO14_FUNC_SEL_W::new(self, 14) } #[doc = "Bits 17:19 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio15_func_sel(&mut self) -> PAD_GPIO15_FUNC_SEL_W { - PAD_GPIO15_FUNC_SEL_W::new(self) + pub fn pad_gpio15_func_sel(&mut self) -> PAD_GPIO15_FUNC_SEL_W { + PAD_GPIO15_FUNC_SEL_W::new(self, 17) } #[doc = "Bits 20:22 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio16_func_sel(&mut self) -> PAD_GPIO16_FUNC_SEL_W { - PAD_GPIO16_FUNC_SEL_W::new(self) + pub fn pad_gpio16_func_sel(&mut self) -> PAD_GPIO16_FUNC_SEL_W { + PAD_GPIO16_FUNC_SEL_W::new(self, 20) } #[doc = "Bits 23:25 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio17_func_sel(&mut self) -> PAD_GPIO17_FUNC_SEL_W { - PAD_GPIO17_FUNC_SEL_W::new(self) + pub fn pad_gpio17_func_sel(&mut self) -> PAD_GPIO17_FUNC_SEL_W { + PAD_GPIO17_FUNC_SEL_W::new(self, 23) } #[doc = "Bits 26:28 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio18_func_sel(&mut self) -> PAD_GPIO18_FUNC_SEL_W { - PAD_GPIO18_FUNC_SEL_W::new(self) + pub fn pad_gpio18_func_sel(&mut self) -> PAD_GPIO18_FUNC_SEL_W { + PAD_GPIO18_FUNC_SEL_W::new(self, 26) } #[doc = "Bits 29:31 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio19_func_sel(&mut self) -> PAD_GPIO19_FUNC_SEL_W { - PAD_GPIO19_FUNC_SEL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn pad_gpio19_func_sel(&mut self) -> PAD_GPIO19_FUNC_SEL_W { + PAD_GPIO19_FUNC_SEL_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel1.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel1.rs index 6ec694c..cd5a02b 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel1.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel1.rs @@ -5,43 +5,43 @@ pub type W = crate::W; #[doc = "Field `pad_gpio20_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO20_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio20_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO20_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO20_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio21_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO21_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio21_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO21_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO21_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio22_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO22_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio22_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO22_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO22_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio23_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO23_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio23_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO23_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO23_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio24_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO24_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio24_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO24_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO24_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio25_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO25_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio25_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO25_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO25_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio26_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO26_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio26_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO26_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO26_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio27_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO27_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio27_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO27_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO27_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio28_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO28_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio28_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO28_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO28_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio29_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO29_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio29_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO29_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO29_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:2 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] @@ -98,64 +98,68 @@ impl W { #[doc = "Bits 0:2 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio20_func_sel(&mut self) -> PAD_GPIO20_FUNC_SEL_W { - PAD_GPIO20_FUNC_SEL_W::new(self) + pub fn pad_gpio20_func_sel(&mut self) -> PAD_GPIO20_FUNC_SEL_W { + PAD_GPIO20_FUNC_SEL_W::new(self, 0) } #[doc = "Bits 3:5 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio21_func_sel(&mut self) -> PAD_GPIO21_FUNC_SEL_W { - PAD_GPIO21_FUNC_SEL_W::new(self) + pub fn pad_gpio21_func_sel(&mut self) -> PAD_GPIO21_FUNC_SEL_W { + PAD_GPIO21_FUNC_SEL_W::new(self, 3) } #[doc = "Bits 6:8 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio22_func_sel(&mut self) -> PAD_GPIO22_FUNC_SEL_W { - PAD_GPIO22_FUNC_SEL_W::new(self) + pub fn pad_gpio22_func_sel(&mut self) -> PAD_GPIO22_FUNC_SEL_W { + PAD_GPIO22_FUNC_SEL_W::new(self, 6) } #[doc = "Bits 9:11 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio23_func_sel(&mut self) -> PAD_GPIO23_FUNC_SEL_W { - PAD_GPIO23_FUNC_SEL_W::new(self) + pub fn pad_gpio23_func_sel(&mut self) -> PAD_GPIO23_FUNC_SEL_W { + PAD_GPIO23_FUNC_SEL_W::new(self, 9) } #[doc = "Bits 12:14 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio24_func_sel(&mut self) -> PAD_GPIO24_FUNC_SEL_W { - PAD_GPIO24_FUNC_SEL_W::new(self) + pub fn pad_gpio24_func_sel(&mut self) -> PAD_GPIO24_FUNC_SEL_W { + PAD_GPIO24_FUNC_SEL_W::new(self, 12) } #[doc = "Bits 15:17 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio25_func_sel(&mut self) -> PAD_GPIO25_FUNC_SEL_W { - PAD_GPIO25_FUNC_SEL_W::new(self) + pub fn pad_gpio25_func_sel(&mut self) -> PAD_GPIO25_FUNC_SEL_W { + PAD_GPIO25_FUNC_SEL_W::new(self, 15) } #[doc = "Bits 18:20 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio26_func_sel(&mut self) -> PAD_GPIO26_FUNC_SEL_W { - PAD_GPIO26_FUNC_SEL_W::new(self) + pub fn pad_gpio26_func_sel(&mut self) -> PAD_GPIO26_FUNC_SEL_W { + PAD_GPIO26_FUNC_SEL_W::new(self, 18) } #[doc = "Bits 21:23 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio27_func_sel(&mut self) -> PAD_GPIO27_FUNC_SEL_W { - PAD_GPIO27_FUNC_SEL_W::new(self) + pub fn pad_gpio27_func_sel(&mut self) -> PAD_GPIO27_FUNC_SEL_W { + PAD_GPIO27_FUNC_SEL_W::new(self, 21) } #[doc = "Bits 24:26 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio28_func_sel(&mut self) -> PAD_GPIO28_FUNC_SEL_W { - PAD_GPIO28_FUNC_SEL_W::new(self) + pub fn pad_gpio28_func_sel(&mut self) -> PAD_GPIO28_FUNC_SEL_W { + PAD_GPIO28_FUNC_SEL_W::new(self, 24) } #[doc = "Bits 27:29 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio29_func_sel(&mut self) -> PAD_GPIO29_FUNC_SEL_W { - PAD_GPIO29_FUNC_SEL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn pad_gpio29_func_sel(&mut self) -> PAD_GPIO29_FUNC_SEL_W { + PAD_GPIO29_FUNC_SEL_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel2.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel2.rs index e2a9acb..ccc33b3 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel2.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel2.rs @@ -5,47 +5,47 @@ pub type W = crate::W; #[doc = "Field `pad_gpio30_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO30_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio30_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO30_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO30_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio31_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO31_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio31_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO31_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO31_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio32_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO32_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio32_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO32_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO32_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio33_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO33_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio33_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO33_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO33_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio34_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO34_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio34_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO34_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO34_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio35_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO35_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio35_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO35_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO35_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio36_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO36_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio36_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO36_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO36_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio37_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO37_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio37_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO37_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO37_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio38_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO38_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio38_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO38_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO38_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio39_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO39_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio39_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO39_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO39_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio40_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO40_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio40_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO40_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO40_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:2 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] @@ -107,70 +107,74 @@ impl W { #[doc = "Bits 0:2 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio30_func_sel(&mut self) -> PAD_GPIO30_FUNC_SEL_W { - PAD_GPIO30_FUNC_SEL_W::new(self) + pub fn pad_gpio30_func_sel(&mut self) -> PAD_GPIO30_FUNC_SEL_W { + PAD_GPIO30_FUNC_SEL_W::new(self, 0) } #[doc = "Bits 3:5 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio31_func_sel(&mut self) -> PAD_GPIO31_FUNC_SEL_W { - PAD_GPIO31_FUNC_SEL_W::new(self) + pub fn pad_gpio31_func_sel(&mut self) -> PAD_GPIO31_FUNC_SEL_W { + PAD_GPIO31_FUNC_SEL_W::new(self, 3) } #[doc = "Bits 6:8 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio32_func_sel(&mut self) -> PAD_GPIO32_FUNC_SEL_W { - PAD_GPIO32_FUNC_SEL_W::new(self) + pub fn pad_gpio32_func_sel(&mut self) -> PAD_GPIO32_FUNC_SEL_W { + PAD_GPIO32_FUNC_SEL_W::new(self, 6) } #[doc = "Bits 9:11 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio33_func_sel(&mut self) -> PAD_GPIO33_FUNC_SEL_W { - PAD_GPIO33_FUNC_SEL_W::new(self) + pub fn pad_gpio33_func_sel(&mut self) -> PAD_GPIO33_FUNC_SEL_W { + PAD_GPIO33_FUNC_SEL_W::new(self, 9) } #[doc = "Bits 12:14 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio34_func_sel(&mut self) -> PAD_GPIO34_FUNC_SEL_W { - PAD_GPIO34_FUNC_SEL_W::new(self) + pub fn pad_gpio34_func_sel(&mut self) -> PAD_GPIO34_FUNC_SEL_W { + PAD_GPIO34_FUNC_SEL_W::new(self, 12) } #[doc = "Bits 15:17 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio35_func_sel(&mut self) -> PAD_GPIO35_FUNC_SEL_W { - PAD_GPIO35_FUNC_SEL_W::new(self) + pub fn pad_gpio35_func_sel(&mut self) -> PAD_GPIO35_FUNC_SEL_W { + PAD_GPIO35_FUNC_SEL_W::new(self, 15) } #[doc = "Bits 18:20 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio36_func_sel(&mut self) -> PAD_GPIO36_FUNC_SEL_W { - PAD_GPIO36_FUNC_SEL_W::new(self) + pub fn pad_gpio36_func_sel(&mut self) -> PAD_GPIO36_FUNC_SEL_W { + PAD_GPIO36_FUNC_SEL_W::new(self, 18) } #[doc = "Bits 21:23 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio37_func_sel(&mut self) -> PAD_GPIO37_FUNC_SEL_W { - PAD_GPIO37_FUNC_SEL_W::new(self) + pub fn pad_gpio37_func_sel(&mut self) -> PAD_GPIO37_FUNC_SEL_W { + PAD_GPIO37_FUNC_SEL_W::new(self, 21) } #[doc = "Bits 24:26 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio38_func_sel(&mut self) -> PAD_GPIO38_FUNC_SEL_W { - PAD_GPIO38_FUNC_SEL_W::new(self) + pub fn pad_gpio38_func_sel(&mut self) -> PAD_GPIO38_FUNC_SEL_W { + PAD_GPIO38_FUNC_SEL_W::new(self, 24) } #[doc = "Bits 27:29 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio39_func_sel(&mut self) -> PAD_GPIO39_FUNC_SEL_W { - PAD_GPIO39_FUNC_SEL_W::new(self) + pub fn pad_gpio39_func_sel(&mut self) -> PAD_GPIO39_FUNC_SEL_W { + PAD_GPIO39_FUNC_SEL_W::new(self, 27) } #[doc = "Bits 30:32 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio40_func_sel(&mut self) -> PAD_GPIO40_FUNC_SEL_W { - PAD_GPIO40_FUNC_SEL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn pad_gpio40_func_sel(&mut self) -> PAD_GPIO40_FUNC_SEL_W { + PAD_GPIO40_FUNC_SEL_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel3.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel3.rs index bba5823..dea7ae5 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel3.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel3.rs @@ -5,47 +5,47 @@ pub type W = crate::W; #[doc = "Field `pad_gpio41_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO41_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio41_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO41_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO41_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio42_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO42_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio42_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO42_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO42_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio43_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO43_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio43_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO43_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO43_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio44_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO44_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio44_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO44_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO44_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio45_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO45_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio45_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO45_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO45_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio46_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO46_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio46_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO46_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO46_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio47_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO47_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio47_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO47_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO47_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio48_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO48_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio48_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO48_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO48_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio49_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO49_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio49_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO49_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO49_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio50_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO50_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio50_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO50_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO50_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio51_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO51_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio51_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO51_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO51_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:2 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] @@ -107,70 +107,74 @@ impl W { #[doc = "Bits 0:2 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio41_func_sel(&mut self) -> PAD_GPIO41_FUNC_SEL_W { - PAD_GPIO41_FUNC_SEL_W::new(self) + pub fn pad_gpio41_func_sel(&mut self) -> PAD_GPIO41_FUNC_SEL_W { + PAD_GPIO41_FUNC_SEL_W::new(self, 0) } #[doc = "Bits 3:5 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio42_func_sel(&mut self) -> PAD_GPIO42_FUNC_SEL_W { - PAD_GPIO42_FUNC_SEL_W::new(self) + pub fn pad_gpio42_func_sel(&mut self) -> PAD_GPIO42_FUNC_SEL_W { + PAD_GPIO42_FUNC_SEL_W::new(self, 3) } #[doc = "Bits 6:8 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio43_func_sel(&mut self) -> PAD_GPIO43_FUNC_SEL_W { - PAD_GPIO43_FUNC_SEL_W::new(self) + pub fn pad_gpio43_func_sel(&mut self) -> PAD_GPIO43_FUNC_SEL_W { + PAD_GPIO43_FUNC_SEL_W::new(self, 6) } #[doc = "Bits 9:11 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio44_func_sel(&mut self) -> PAD_GPIO44_FUNC_SEL_W { - PAD_GPIO44_FUNC_SEL_W::new(self) + pub fn pad_gpio44_func_sel(&mut self) -> PAD_GPIO44_FUNC_SEL_W { + PAD_GPIO44_FUNC_SEL_W::new(self, 9) } #[doc = "Bits 12:14 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio45_func_sel(&mut self) -> PAD_GPIO45_FUNC_SEL_W { - PAD_GPIO45_FUNC_SEL_W::new(self) + pub fn pad_gpio45_func_sel(&mut self) -> PAD_GPIO45_FUNC_SEL_W { + PAD_GPIO45_FUNC_SEL_W::new(self, 12) } #[doc = "Bits 15:17 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio46_func_sel(&mut self) -> PAD_GPIO46_FUNC_SEL_W { - PAD_GPIO46_FUNC_SEL_W::new(self) + pub fn pad_gpio46_func_sel(&mut self) -> PAD_GPIO46_FUNC_SEL_W { + PAD_GPIO46_FUNC_SEL_W::new(self, 15) } #[doc = "Bits 18:20 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio47_func_sel(&mut self) -> PAD_GPIO47_FUNC_SEL_W { - PAD_GPIO47_FUNC_SEL_W::new(self) + pub fn pad_gpio47_func_sel(&mut self) -> PAD_GPIO47_FUNC_SEL_W { + PAD_GPIO47_FUNC_SEL_W::new(self, 18) } #[doc = "Bits 21:23 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio48_func_sel(&mut self) -> PAD_GPIO48_FUNC_SEL_W { - PAD_GPIO48_FUNC_SEL_W::new(self) + pub fn pad_gpio48_func_sel(&mut self) -> PAD_GPIO48_FUNC_SEL_W { + PAD_GPIO48_FUNC_SEL_W::new(self, 21) } #[doc = "Bits 24:26 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio49_func_sel(&mut self) -> PAD_GPIO49_FUNC_SEL_W { - PAD_GPIO49_FUNC_SEL_W::new(self) + pub fn pad_gpio49_func_sel(&mut self) -> PAD_GPIO49_FUNC_SEL_W { + PAD_GPIO49_FUNC_SEL_W::new(self, 24) } #[doc = "Bits 27:29 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio50_func_sel(&mut self) -> PAD_GPIO50_FUNC_SEL_W { - PAD_GPIO50_FUNC_SEL_W::new(self) + pub fn pad_gpio50_func_sel(&mut self) -> PAD_GPIO50_FUNC_SEL_W { + PAD_GPIO50_FUNC_SEL_W::new(self, 27) } #[doc = "Bits 30:32 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio51_func_sel(&mut self) -> PAD_GPIO51_FUNC_SEL_W { - PAD_GPIO51_FUNC_SEL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn pad_gpio51_func_sel(&mut self) -> PAD_GPIO51_FUNC_SEL_W { + PAD_GPIO51_FUNC_SEL_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel4.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel4.rs index e564c59..4c65a27 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel4.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel4.rs @@ -5,47 +5,47 @@ pub type W = crate::W; #[doc = "Field `pad_gpio52_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO52_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio52_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO52_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PAD_GPIO52_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pad_gpio53_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO53_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio53_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO53_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PAD_GPIO53_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pad_gpio54_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO54_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio54_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO54_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PAD_GPIO54_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pad_gpio56_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO56_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio56_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO56_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO56_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio57_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO57_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio57_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO57_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO57_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio58_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO58_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio58_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO58_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO58_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio59_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO59_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio59_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO59_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO59_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio60_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO60_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio60_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO60_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO60_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio61_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO61_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio61_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO61_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO61_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio62_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO62_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio62_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO62_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO62_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio63_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO63_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio63_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO63_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PAD_GPIO63_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] @@ -107,70 +107,74 @@ impl W { #[doc = "Bits 0:1 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio52_func_sel(&mut self) -> PAD_GPIO52_FUNC_SEL_W { - PAD_GPIO52_FUNC_SEL_W::new(self) + pub fn pad_gpio52_func_sel(&mut self) -> PAD_GPIO52_FUNC_SEL_W { + PAD_GPIO52_FUNC_SEL_W::new(self, 0) } #[doc = "Bits 2:3 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio53_func_sel(&mut self) -> PAD_GPIO53_FUNC_SEL_W { - PAD_GPIO53_FUNC_SEL_W::new(self) + pub fn pad_gpio53_func_sel(&mut self) -> PAD_GPIO53_FUNC_SEL_W { + PAD_GPIO53_FUNC_SEL_W::new(self, 2) } #[doc = "Bits 4:5 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio54_func_sel(&mut self) -> PAD_GPIO54_FUNC_SEL_W { - PAD_GPIO54_FUNC_SEL_W::new(self) + pub fn pad_gpio54_func_sel(&mut self) -> PAD_GPIO54_FUNC_SEL_W { + PAD_GPIO54_FUNC_SEL_W::new(self, 4) } #[doc = "Bits 12:14 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio56_func_sel(&mut self) -> PAD_GPIO56_FUNC_SEL_W { - PAD_GPIO56_FUNC_SEL_W::new(self) + pub fn pad_gpio56_func_sel(&mut self) -> PAD_GPIO56_FUNC_SEL_W { + PAD_GPIO56_FUNC_SEL_W::new(self, 12) } #[doc = "Bits 15:17 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio57_func_sel(&mut self) -> PAD_GPIO57_FUNC_SEL_W { - PAD_GPIO57_FUNC_SEL_W::new(self) + pub fn pad_gpio57_func_sel(&mut self) -> PAD_GPIO57_FUNC_SEL_W { + PAD_GPIO57_FUNC_SEL_W::new(self, 15) } #[doc = "Bits 18:20 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio58_func_sel(&mut self) -> PAD_GPIO58_FUNC_SEL_W { - PAD_GPIO58_FUNC_SEL_W::new(self) + pub fn pad_gpio58_func_sel(&mut self) -> PAD_GPIO58_FUNC_SEL_W { + PAD_GPIO58_FUNC_SEL_W::new(self, 18) } #[doc = "Bits 21:23 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio59_func_sel(&mut self) -> PAD_GPIO59_FUNC_SEL_W { - PAD_GPIO59_FUNC_SEL_W::new(self) + pub fn pad_gpio59_func_sel(&mut self) -> PAD_GPIO59_FUNC_SEL_W { + PAD_GPIO59_FUNC_SEL_W::new(self, 21) } #[doc = "Bits 24:26 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio60_func_sel(&mut self) -> PAD_GPIO60_FUNC_SEL_W { - PAD_GPIO60_FUNC_SEL_W::new(self) + pub fn pad_gpio60_func_sel(&mut self) -> PAD_GPIO60_FUNC_SEL_W { + PAD_GPIO60_FUNC_SEL_W::new(self, 24) } #[doc = "Bits 27:29 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio61_func_sel(&mut self) -> PAD_GPIO61_FUNC_SEL_W { - PAD_GPIO61_FUNC_SEL_W::new(self) + pub fn pad_gpio61_func_sel(&mut self) -> PAD_GPIO61_FUNC_SEL_W { + PAD_GPIO61_FUNC_SEL_W::new(self, 27) } #[doc = "Bits 30:32 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio62_func_sel(&mut self) -> PAD_GPIO62_FUNC_SEL_W { - PAD_GPIO62_FUNC_SEL_W::new(self) + pub fn pad_gpio62_func_sel(&mut self) -> PAD_GPIO62_FUNC_SEL_W { + PAD_GPIO62_FUNC_SEL_W::new(self, 30) } #[doc = "Bits 30:31 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio63_func_sel(&mut self) -> PAD_GPIO63_FUNC_SEL_W { - PAD_GPIO63_FUNC_SEL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn pad_gpio63_func_sel(&mut self) -> PAD_GPIO63_FUNC_SEL_W { + PAD_GPIO63_FUNC_SEL_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel5.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel5.rs index be6fe81..1721cf4 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel5.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel5.rs @@ -5,54 +5,47 @@ pub type W = crate::W; #[doc = "Field `pad_gpio6_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO6_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio6_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO6_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PAD_GPIO6_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pad_gpio7_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO7_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio7_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO7_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO7_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio8_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO8_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio8_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO8_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO8_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `pad_gpio9_func_sel` reader - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] pub type PAD_GPIO9_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `pad_gpio9_func_sel` writer - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] -pub type PAD_GPIO9_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type PAD_GPIO9_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c0_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c0_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c10_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c10_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c11_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c11_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c1_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c1_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c2_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c2_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c3_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c3_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c4_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c4_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:1 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] @@ -128,84 +121,88 @@ impl W { #[doc = "Bits 0:1 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio6_func_sel(&mut self) -> PAD_GPIO6_FUNC_SEL_W { - PAD_GPIO6_FUNC_SEL_W::new(self) + pub fn pad_gpio6_func_sel(&mut self) -> PAD_GPIO6_FUNC_SEL_W { + PAD_GPIO6_FUNC_SEL_W::new(self, 0) } #[doc = "Bits 3:5 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio7_func_sel(&mut self) -> PAD_GPIO7_FUNC_SEL_W { - PAD_GPIO7_FUNC_SEL_W::new(self) + pub fn pad_gpio7_func_sel(&mut self) -> PAD_GPIO7_FUNC_SEL_W { + PAD_GPIO7_FUNC_SEL_W::new(self, 3) } #[doc = "Bits 6:8 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio8_func_sel(&mut self) -> PAD_GPIO8_FUNC_SEL_W { - PAD_GPIO8_FUNC_SEL_W::new(self) + pub fn pad_gpio8_func_sel(&mut self) -> PAD_GPIO8_FUNC_SEL_W { + PAD_GPIO8_FUNC_SEL_W::new(self, 6) } #[doc = "Bits 9:11 - GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information"] #[inline(always)] #[must_use] - pub fn pad_gpio9_func_sel(&mut self) -> PAD_GPIO9_FUNC_SEL_W { - PAD_GPIO9_FUNC_SEL_W::new(self) + pub fn pad_gpio9_func_sel(&mut self) -> PAD_GPIO9_FUNC_SEL_W { + PAD_GPIO9_FUNC_SEL_W::new(self, 9) } #[doc = "Bits 11:13 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c0_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_W::new(self, 11) } #[doc = "Bits 14:16 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c10_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_W::new(self, 14) } #[doc = "Bits 17:19 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c11_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_W::new(self, 17) } #[doc = "Bits 20:22 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c1_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_W::new(self, 20) } #[doc = "Bits 23:25 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c2_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_W::new(self, 23) } #[doc = "Bits 26:28 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c3_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_W::new(self, 26) } #[doc = "Bits 29:31 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c4_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel6.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel6.rs index e98f782..508e9f3 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel6.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/func_sel6.rs @@ -5,42 +5,35 @@ pub type W = crate::W; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c5_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c5_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c6_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c6_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c7_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c7_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c8_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c8_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c9_func_sel` reader - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_data_c9_func_sel` writer - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_hvalid_c_func_sel` reader - Function Selector of DVP_HSYNC, see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_hvalid_c_func_sel` writer - Function Selector of DVP_HSYNC, see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_vvalid_c_func_sel` reader - Function Selector of DVP_VSYNC, see Function 2 for more information"] pub type U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_dom_isp_top_u0_vin_dvp_vvalid_c_func_sel` writer - Function Selector of DVP_VSYNC, see Function 2 for more information"] -pub type U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_sys_crg_dvp_clk_func_sel` reader - Function Selector of DVP_CLK, see Function 2 for more information"] pub type U0_SYS_CRG_DVP_CLK_FUNC_SEL_R = crate::FieldReader; #[doc = "Field `u0_sys_crg_dvp_clk_func_sel` writer - Function Selector of DVP_CLK, see Function 2 for more information"] -pub type U0_SYS_CRG_DVP_CLK_FUNC_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U0_SYS_CRG_DVP_CLK_FUNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:2 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] @@ -103,66 +96,68 @@ impl W { #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c5_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_W::new(self, 0) } #[doc = "Bits 3:5 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c6_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_W::new(self, 3) } #[doc = "Bits 6:8 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c7_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_W::new(self, 6) } #[doc = "Bits 9:11 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c8_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_W::new(self, 9) } #[doc = "Bits 12:14 - Function Selector of DVP_DATA\\[idx\\], see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_data_c9_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_W::new(self, 12) } #[doc = "Bits 15:17 - Function Selector of DVP_HSYNC, see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_hvalid_c_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_W::new(self, 15) } #[doc = "Bits 18:20 - Function Selector of DVP_VSYNC, see Function 2 for more information"] #[inline(always)] #[must_use] pub fn u0_dom_isp_top_u0_vin_dvp_vvalid_c_func_sel( &mut self, - ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_W { - U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_W::new(self) + ) -> U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_W { + U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_W::new(self, 18) } #[doc = "Bits 21:23 - Function Selector of DVP_CLK, see Function 2 for more information"] #[inline(always)] #[must_use] - pub fn u0_sys_crg_dvp_clk_func_sel( - &mut self, - ) -> U0_SYS_CRG_DVP_CLK_FUNC_SEL_W { - U0_SYS_CRG_DVP_CLK_FUNC_SEL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn u0_sys_crg_dvp_clk_func_sel(&mut self) -> U0_SYS_CRG_DVP_CLK_FUNC_SEL_W { + U0_SYS_CRG_DVP_CLK_FUNC_SEL_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi0.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi0.rs index 705d94b..1df2325 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi0.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi0.rs @@ -5,20 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_WAVE511_i_uart_rxsin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_WAVE511_I_UART_RXSIN_CFG_R = crate::FieldReader; #[doc = "Field `u0_WAVE511_i_uart_rxsin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_WAVE511_I_UART_RXSIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_WAVE511_I_UART_RXSIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_can_ctrl_rxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_CAN_CTRL_RXD_CFG_R = crate::FieldReader; #[doc = "Field `u0_can_ctrl_rxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_CAN_CTRL_RXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_CAN_CTRL_RXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_cdn_usb_over_current_n_io_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_CDN_USB_OVER_CURRENT_N_IO_CFG_R = crate::FieldReader; #[doc = "Field `u0_cdn_usb_over_current_n_io_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_CDN_USB_OVER_CURRENT_N_IO_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_CDN_USB_OVER_CURRENT_N_IO_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_cdns_spdif_spdi_fi_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_CDNS_SPDIF_SPDI_FI_CFG_R = crate::FieldReader; #[doc = "Field `u0_cdns_spdif_spdi_fi_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_CDNS_SPDIF_SPDI_FI_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_CDNS_SPDIF_SPDI_FI_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -45,30 +44,34 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_wave511_i_uart_rxsin_cfg(&mut self) -> U0_WAVE511_I_UART_RXSIN_CFG_W { - U0_WAVE511_I_UART_RXSIN_CFG_W::new(self) + pub fn u0_wave511_i_uart_rxsin_cfg(&mut self) -> U0_WAVE511_I_UART_RXSIN_CFG_W { + U0_WAVE511_I_UART_RXSIN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_can_ctrl_rxd_cfg(&mut self) -> U0_CAN_CTRL_RXD_CFG_W { - U0_CAN_CTRL_RXD_CFG_W::new(self) + pub fn u0_can_ctrl_rxd_cfg(&mut self) -> U0_CAN_CTRL_RXD_CFG_W { + U0_CAN_CTRL_RXD_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn u0_cdn_usb_over_current_n_io_cfg( &mut self, - ) -> U0_CDN_USB_OVER_CURRENT_N_IO_CFG_W { - U0_CDN_USB_OVER_CURRENT_N_IO_CFG_W::new(self) + ) -> U0_CDN_USB_OVER_CURRENT_N_IO_CFG_W { + U0_CDN_USB_OVER_CURRENT_N_IO_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_cdns_spdif_spdi_fi_cfg(&mut self) -> U0_CDNS_SPDIF_SPDI_FI_CFG_W { - U0_CDNS_SPDIF_SPDI_FI_CFG_W::new(self) + pub fn u0_cdns_spdif_spdi_fi_cfg(&mut self) -> U0_CDNS_SPDIF_SPDI_FI_CFG_W { + U0_CDNS_SPDIF_SPDI_FI_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi12.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi12.rs index 7e979fb..54b823b 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi12.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi12.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_sdio_card_int_n_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SDIO_CARD_INT_N_CFG_R = crate::FieldReader; #[doc = "Field `u0_sdio_card_int_n_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SDIO_CARD_INT_N_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SDIO_CARD_INT_N_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_sdio_card_write_prt_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SDIO_CARD_WRITE_PRT_CFG_R = crate::FieldReader; #[doc = "Field `u0_sdio_card_write_prt_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SDIO_CARD_WRITE_PRT_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SDIO_CARD_WRITE_PRT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_uart_sin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_UART_SIN_CFG_R = crate::FieldReader; #[doc = "Field `u0_uart_sin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_UART_SIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_UART_SIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_hifi4_jtck_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_HIFI4_JTCK_CFG_R = crate::FieldReader; #[doc = "Field `u0_hifi4_jtck_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_HIFI4_JTCK_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_HIFI4_JTCK_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sdio_card_int_n_cfg(&mut self) -> U0_SDIO_CARD_INT_N_CFG_W { - U0_SDIO_CARD_INT_N_CFG_W::new(self) + pub fn u0_sdio_card_int_n_cfg(&mut self) -> U0_SDIO_CARD_INT_N_CFG_W { + U0_SDIO_CARD_INT_N_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sdio_card_write_prt_cfg(&mut self) -> U0_SDIO_CARD_WRITE_PRT_CFG_W { - U0_SDIO_CARD_WRITE_PRT_CFG_W::new(self) + pub fn u0_sdio_card_write_prt_cfg(&mut self) -> U0_SDIO_CARD_WRITE_PRT_CFG_W { + U0_SDIO_CARD_WRITE_PRT_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_uart_sin_cfg(&mut self) -> U0_UART_SIN_CFG_W { - U0_UART_SIN_CFG_W::new(self) + pub fn u0_uart_sin_cfg(&mut self) -> U0_UART_SIN_CFG_W { + U0_UART_SIN_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_hifi4_jtck_cfg(&mut self) -> U0_HIFI4_JTCK_CFG_W { - U0_HIFI4_JTCK_CFG_W::new(self) + pub fn u0_hifi4_jtck_cfg(&mut self) -> U0_HIFI4_JTCK_CFG_W { + U0_HIFI4_JTCK_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi16.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi16.rs index 117acfd..6b6c6f6 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi16.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi16.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_hifi4_jtdi_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_HIFI4_JTDI_CFG_R = crate::FieldReader; #[doc = "Field `u0_hifi4_jtdi_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_HIFI4_JTDI_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_HIFI4_JTDI_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_hifi4_jtms_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_HIFI4_JTMS_CFG_R = crate::FieldReader; #[doc = "Field `u0_hifi4_jtms_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_HIFI4_JTMS_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_HIFI4_JTMS_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_hifi4_jtrstn_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_HIFI4_JTRSTN_CFG_R = crate::FieldReader; #[doc = "Field `u0_hifi4_jtrstn_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_HIFI4_JTRSTN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_HIFI4_JTRSTN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_jtag_certification_tdi_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_JTAG_CERTIFICATION_TDI_CFG_R = crate::FieldReader; #[doc = "Field `u0_jtag_certification_tdi_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_JTAG_CERTIFICATION_TDI_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_JTAG_CERTIFICATION_TDI_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,30 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_hifi4_jtdi_cfg(&mut self) -> U0_HIFI4_JTDI_CFG_W { - U0_HIFI4_JTDI_CFG_W::new(self) + pub fn u0_hifi4_jtdi_cfg(&mut self) -> U0_HIFI4_JTDI_CFG_W { + U0_HIFI4_JTDI_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_hifi4_jtms_cfg(&mut self) -> U0_HIFI4_JTMS_CFG_W { - U0_HIFI4_JTMS_CFG_W::new(self) + pub fn u0_hifi4_jtms_cfg(&mut self) -> U0_HIFI4_JTMS_CFG_W { + U0_HIFI4_JTMS_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_hifi4_jtrstn_cfg(&mut self) -> U0_HIFI4_JTRSTN_CFG_W { - U0_HIFI4_JTRSTN_CFG_W::new(self) + pub fn u0_hifi4_jtrstn_cfg(&mut self) -> U0_HIFI4_JTRSTN_CFG_W { + U0_HIFI4_JTRSTN_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_jtag_certification_tdi_cfg( - &mut self, - ) -> U0_JTAG_CERTIFICATION_TDI_CFG_W { - U0_JTAG_CERTIFICATION_TDI_CFG_W::new(self) + pub fn u0_jtag_certification_tdi_cfg(&mut self) -> U0_JTAG_CERTIFICATION_TDI_CFG_W { + U0_JTAG_CERTIFICATION_TDI_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi20.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi20.rs index 52b33cc..4b86ebd 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi20.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi20.rs @@ -5,20 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_jtag_certification_tms_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_JTAG_CERTIFICATION_TMS_CFG_R = crate::FieldReader; #[doc = "Field `u0_jtag_certification_tms_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_JTAG_CERTIFICATION_TMS_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_JTAG_CERTIFICATION_TMS_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_pdm_4mic_dmic0_din_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_PDM_4MIC_DMIC0_DIN_CFG_R = crate::FieldReader; #[doc = "Field `u0_pdm_4mic_dmic0_din_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_PDM_4MIC_DMIC0_DIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_PDM_4MIC_DMIC0_DIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_pdm_4mic_dmic1_din_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_PDM_4MIC_DMIC1_DIN_CFG_R = crate::FieldReader; #[doc = "Field `u0_pdm_4mic_dmic1_din_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_PDM_4MIC_DMIC1_DIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_PDM_4MIC_DMIC1_DIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_saif_audio_sdin_mux_i2srx_ext_sdin0_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0_CFG_R = crate::FieldReader; #[doc = "Field `u0_saif_audio_sdin_mux_i2srx_ext_sdin0_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -47,32 +46,34 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_jtag_certification_tms_cfg( - &mut self, - ) -> U0_JTAG_CERTIFICATION_TMS_CFG_W { - U0_JTAG_CERTIFICATION_TMS_CFG_W::new(self) + pub fn u0_jtag_certification_tms_cfg(&mut self) -> U0_JTAG_CERTIFICATION_TMS_CFG_W { + U0_JTAG_CERTIFICATION_TMS_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_pdm_4mic_dmic0_din_cfg(&mut self) -> U0_PDM_4MIC_DMIC0_DIN_CFG_W { - U0_PDM_4MIC_DMIC0_DIN_CFG_W::new(self) + pub fn u0_pdm_4mic_dmic0_din_cfg(&mut self) -> U0_PDM_4MIC_DMIC0_DIN_CFG_W { + U0_PDM_4MIC_DMIC0_DIN_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_pdm_4mic_dmic1_din_cfg(&mut self) -> U0_PDM_4MIC_DMIC1_DIN_CFG_W { - U0_PDM_4MIC_DMIC1_DIN_CFG_W::new(self) + pub fn u0_pdm_4mic_dmic1_din_cfg(&mut self) -> U0_PDM_4MIC_DMIC1_DIN_CFG_W { + U0_PDM_4MIC_DMIC1_DIN_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn u0_saif_audio_sdin_mux_i2srx_ext_sdin0_cfg( &mut self, - ) -> U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0_CFG_W { - U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0_CFG_W::new(self) + ) -> U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0_CFG_W { + U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi24.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi24.rs index 2a9380f..8e75e01 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi24.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi24.rs @@ -5,21 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_saif_audio_sdin_mux_i2srx_ext_sdin1_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1_CFG_R = crate::FieldReader; #[doc = "Field `u0_saif_audio_sdin_mux_i2srx_ext_sdin1_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_saif_audio_sdin_mux_i2srx_ext_sdin2_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2_CFG_R = crate::FieldReader; #[doc = "Field `u0_saif_audio_sdin_mux_i2srx_ext_sdin2_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_ssp_spi_sspclkin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SSP_SPI_SSPCLKIN_CFG_R = crate::FieldReader; #[doc = "Field `u0_ssp_spi_sspclkin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SSP_SPI_SSPCLKIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SSP_SPI_SSPCLKIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_ssp_spi_sspfssin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SSP_SPI_SSPFSSIN_CFG_R = crate::FieldReader; #[doc = "Field `u0_ssp_spi_sspfssin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SSP_SPI_SSPFSSIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SSP_SPI_SSPFSSIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -52,30 +50,34 @@ impl W { #[must_use] pub fn u0_saif_audio_sdin_mux_i2srx_ext_sdin1_cfg( &mut self, - ) -> U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1_CFG_W { - U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1_CFG_W::new(self) + ) -> U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1_CFG_W { + U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn u0_saif_audio_sdin_mux_i2srx_ext_sdin2_cfg( &mut self, - ) -> U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2_CFG_W { - U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2_CFG_W::new(self) + ) -> U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2_CFG_W { + U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_ssp_spi_sspclkin_cfg(&mut self) -> U0_SSP_SPI_SSPCLKIN_CFG_W { - U0_SSP_SPI_SSPCLKIN_CFG_W::new(self) + pub fn u0_ssp_spi_sspclkin_cfg(&mut self) -> U0_SSP_SPI_SSPCLKIN_CFG_W { + U0_SSP_SPI_SSPCLKIN_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_ssp_spi_sspfssin_cfg(&mut self) -> U0_SSP_SPI_SSPFSSIN_CFG_W { - U0_SSP_SPI_SSPFSSIN_CFG_W::new(self) + pub fn u0_ssp_spi_sspfssin_cfg(&mut self) -> U0_SSP_SPI_SSPFSSIN_CFG_W { + U0_SSP_SPI_SSPFSSIN_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi28.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi28.rs index 7383675..1de1e81 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi28.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi28.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_ssp_spi_ssprxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SSP_SPI_SSPRXD_CFG_R = crate::FieldReader; #[doc = "Field `u0_ssp_spi_ssprxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SSP_SPI_SSPRXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SSP_SPI_SSPRXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_sys_crg_clk_jtag_tck_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SYS_CRG_CLK_JTAG_TCK_CFG_R = crate::FieldReader; #[doc = "Field `u0_sys_crg_clk_jtag_tck_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SYS_CRG_CLK_JTAG_TCK_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SYS_CRG_CLK_JTAG_TCK_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_sys_crg_ext_mclk_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SYS_CRG_EXT_MCLK_CFG_R = crate::FieldReader; #[doc = "Field `u0_sys_crg_ext_mclk_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SYS_CRG_EXT_MCLK_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SYS_CRG_EXT_MCLK_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_sys_crg_i2srx_bclk_slv_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SYS_CRG_I2SRX_BCLK_SLV_CFG_R = crate::FieldReader; #[doc = "Field `u0_sys_crg_i2srx_bclk_slv_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SYS_CRG_I2SRX_BCLK_SLV_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SYS_CRG_I2SRX_BCLK_SLV_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,30 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_ssp_spi_ssprxd_cfg(&mut self) -> U0_SSP_SPI_SSPRXD_CFG_W { - U0_SSP_SPI_SSPRXD_CFG_W::new(self) + pub fn u0_ssp_spi_ssprxd_cfg(&mut self) -> U0_SSP_SPI_SSPRXD_CFG_W { + U0_SSP_SPI_SSPRXD_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sys_crg_clk_jtag_tck_cfg(&mut self) -> U0_SYS_CRG_CLK_JTAG_TCK_CFG_W { - U0_SYS_CRG_CLK_JTAG_TCK_CFG_W::new(self) + pub fn u0_sys_crg_clk_jtag_tck_cfg(&mut self) -> U0_SYS_CRG_CLK_JTAG_TCK_CFG_W { + U0_SYS_CRG_CLK_JTAG_TCK_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sys_crg_ext_mclk_cfg(&mut self) -> U0_SYS_CRG_EXT_MCLK_CFG_W { - U0_SYS_CRG_EXT_MCLK_CFG_W::new(self) + pub fn u0_sys_crg_ext_mclk_cfg(&mut self) -> U0_SYS_CRG_EXT_MCLK_CFG_W { + U0_SYS_CRG_EXT_MCLK_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sys_crg_i2srx_bclk_slv_cfg( - &mut self, - ) -> U0_SYS_CRG_I2SRX_BCLK_SLV_CFG_W { - U0_SYS_CRG_I2SRX_BCLK_SLV_CFG_W::new(self) + pub fn u0_sys_crg_i2srx_bclk_slv_cfg(&mut self) -> U0_SYS_CRG_I2SRX_BCLK_SLV_CFG_W { + U0_SYS_CRG_I2SRX_BCLK_SLV_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi32.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi32.rs index 04c2284..bc1c4a7 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi32.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi32.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_sys_crg_i2srx_lrck_slv_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SYS_CRG_I2SRX_LRCK_SLV_CFG_R = crate::FieldReader; #[doc = "Field `u0_sys_crg_i2srx_lrck_slv_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SYS_CRG_I2SRX_LRCK_SLV_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SYS_CRG_I2SRX_LRCK_SLV_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_sys_crg_i2stx_bclk_slv_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SYS_CRG_I2STX_BCLK_SLV_CFG_R = crate::FieldReader; #[doc = "Field `u0_sys_crg_i2stx_bclk_slv_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SYS_CRG_I2STX_BCLK_SLV_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SYS_CRG_I2STX_BCLK_SLV_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_sys_crg_i2stx_lrck_slv_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SYS_CRG_I2STX_LRCK_SLV_CFG_R = crate::FieldReader; #[doc = "Field `u0_sys_crg_i2stx_lrck_slv_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SYS_CRG_I2STX_LRCK_SLV_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SYS_CRG_I2STX_LRCK_SLV_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_sys_crg_tdm_clk_slv_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SYS_CRG_TDM_CLK_SLV_CFG_R = crate::FieldReader; #[doc = "Field `u0_sys_crg_tdm_clk_slv_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SYS_CRG_TDM_CLK_SLV_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SYS_CRG_TDM_CLK_SLV_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,34 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sys_crg_i2srx_lrck_slv_cfg( - &mut self, - ) -> U0_SYS_CRG_I2SRX_LRCK_SLV_CFG_W { - U0_SYS_CRG_I2SRX_LRCK_SLV_CFG_W::new(self) + pub fn u0_sys_crg_i2srx_lrck_slv_cfg(&mut self) -> U0_SYS_CRG_I2SRX_LRCK_SLV_CFG_W { + U0_SYS_CRG_I2SRX_LRCK_SLV_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sys_crg_i2stx_bclk_slv_cfg( - &mut self, - ) -> U0_SYS_CRG_I2STX_BCLK_SLV_CFG_W { - U0_SYS_CRG_I2STX_BCLK_SLV_CFG_W::new(self) + pub fn u0_sys_crg_i2stx_bclk_slv_cfg(&mut self) -> U0_SYS_CRG_I2STX_BCLK_SLV_CFG_W { + U0_SYS_CRG_I2STX_BCLK_SLV_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sys_crg_i2stx_lrck_slv_cfg( - &mut self, - ) -> U0_SYS_CRG_I2STX_LRCK_SLV_CFG_W { - U0_SYS_CRG_I2STX_LRCK_SLV_CFG_W::new(self) + pub fn u0_sys_crg_i2stx_lrck_slv_cfg(&mut self) -> U0_SYS_CRG_I2STX_LRCK_SLV_CFG_W { + U0_SYS_CRG_I2STX_LRCK_SLV_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sys_crg_tdm_clk_slv_cfg(&mut self) -> U0_SYS_CRG_TDM_CLK_SLV_CFG_W { - U0_SYS_CRG_TDM_CLK_SLV_CFG_W::new(self) + pub fn u0_sys_crg_tdm_clk_slv_cfg(&mut self) -> U0_SYS_CRG_TDM_CLK_SLV_CFG_W { + U0_SYS_CRG_TDM_CLK_SLV_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi36.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi36.rs index 7dc6816..4215463 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi36.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi36.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_tdm16slot_pcm_rxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_TDM16SLOT_PCM_RXD_CFG_R = crate::FieldReader; #[doc = "Field `u0_tdm16slot_pcm_rxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_TDM16SLOT_PCM_RXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_TDM16SLOT_PCM_RXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_tdm16slot_pcm_synon_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_TDM16SLOT_PCM_SYNON_CFG_R = crate::FieldReader; #[doc = "Field `u0_tdm16slot_pcm_synon_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_TDM16SLOT_PCM_SYNON_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_TDM16SLOT_PCM_SYNON_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_can_ctrl_rxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_CAN_CTRL_RXD_CFG_R = crate::FieldReader; #[doc = "Field `u1_can_ctrl_rxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_CAN_CTRL_RXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_CAN_CTRL_RXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_i2c_ic_clk_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_I2C_IC_CLK_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u1_i2c_ic_clk_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_I2C_IC_CLK_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_I2C_IC_CLK_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_tdm16slot_pcm_rxd_cfg(&mut self) -> U0_TDM16SLOT_PCM_RXD_CFG_W { - U0_TDM16SLOT_PCM_RXD_CFG_W::new(self) + pub fn u0_tdm16slot_pcm_rxd_cfg(&mut self) -> U0_TDM16SLOT_PCM_RXD_CFG_W { + U0_TDM16SLOT_PCM_RXD_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_tdm16slot_pcm_synon_cfg(&mut self) -> U0_TDM16SLOT_PCM_SYNON_CFG_W { - U0_TDM16SLOT_PCM_SYNON_CFG_W::new(self) + pub fn u0_tdm16slot_pcm_synon_cfg(&mut self) -> U0_TDM16SLOT_PCM_SYNON_CFG_W { + U0_TDM16SLOT_PCM_SYNON_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_can_ctrl_rxd_cfg(&mut self) -> U1_CAN_CTRL_RXD_CFG_W { - U1_CAN_CTRL_RXD_CFG_W::new(self) + pub fn u1_can_ctrl_rxd_cfg(&mut self) -> U1_CAN_CTRL_RXD_CFG_W { + U1_CAN_CTRL_RXD_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_i2c_ic_clk_in_a_cfg(&mut self) -> U1_I2C_IC_CLK_IN_A_CFG_W { - U1_I2C_IC_CLK_IN_A_CFG_W::new(self) + pub fn u1_i2c_ic_clk_in_a_cfg(&mut self) -> U1_I2C_IC_CLK_IN_A_CFG_W { + U1_I2C_IC_CLK_IN_A_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi4.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi4.rs index 4c2a437..86cefd5 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi4.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi4.rs @@ -5,23 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_clkrst_src_bypass_jtag_trstn_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_CLKRST_SRC_BYPASS_JTAG_TRSTN_CFG_R = crate::FieldReader; #[doc = "Field `u0_clkrst_src_bypass_jtag_trstn_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_CLKRST_SRC_BYPASS_JTAG_TRSTN_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_CLKRST_SRC_BYPASS_JTAG_TRSTN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_dom_vout_top_u0_hdmi_tx_pin_cec_sda_in_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN_CFG_R = crate::FieldReader; #[doc = "Field `u0_dom_vout_top_u0_hdmi_tx_pin_cec_sda_in_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_dom_vout_top_u0_hdmi_tx_pin_ddc_scl_in_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN_CFG_R = crate::FieldReader; #[doc = "Field `u0_dom_vout_top_u0_hdmi_tx_pin_ddc_scl_in_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_dom_vout_top_u0_hdmi_tx_pin_ddc_sda_in_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN_CFG_R = crate::FieldReader; #[doc = "Field `u0_dom_vout_top_u0_hdmi_tx_pin_ddc_sda_in_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -56,34 +52,38 @@ impl W { #[must_use] pub fn u0_clkrst_src_bypass_jtag_trstn_cfg( &mut self, - ) -> U0_CLKRST_SRC_BYPASS_JTAG_TRSTN_CFG_W { - U0_CLKRST_SRC_BYPASS_JTAG_TRSTN_CFG_W::new(self) + ) -> U0_CLKRST_SRC_BYPASS_JTAG_TRSTN_CFG_W { + U0_CLKRST_SRC_BYPASS_JTAG_TRSTN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn u0_dom_vout_top_u0_hdmi_tx_pin_cec_sda_in_cfg( &mut self, - ) -> U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN_CFG_W { - U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN_CFG_W::new(self) + ) -> U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN_CFG_W { + U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn u0_dom_vout_top_u0_hdmi_tx_pin_ddc_scl_in_cfg( &mut self, - ) -> U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN_CFG_W { - U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN_CFG_W::new(self) + ) -> U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN_CFG_W { + U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] pub fn u0_dom_vout_top_u0_hdmi_tx_pin_ddc_sda_in_cfg( &mut self, - ) -> U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN_CFG_W { - U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN_CFG_W::new(self) + ) -> U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN_CFG_W { + U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi40.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi40.rs index f5f4dc6..11bed88 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi40.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi40.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u1_i2c_ic_data_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_I2C_IC_DATA_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u1_i2c_ic_data_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_I2C_IC_DATA_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_I2C_IC_DATA_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_card_detect_n_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CARD_DETECT_N_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_card_detect_n_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CARD_DETECT_N_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CARD_DETECT_N_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_card_int_n_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CARD_INT_N_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_card_int_n_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CARD_INT_N_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CARD_INT_N_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_card_write_prt_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CARD_WRITE_PRT_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_card_write_prt_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CARD_WRITE_PRT_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CARD_WRITE_PRT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_i2c_ic_data_in_a_cfg(&mut self) -> U1_I2C_IC_DATA_IN_A_CFG_W { - U1_I2C_IC_DATA_IN_A_CFG_W::new(self) + pub fn u1_i2c_ic_data_in_a_cfg(&mut self) -> U1_I2C_IC_DATA_IN_A_CFG_W { + U1_I2C_IC_DATA_IN_A_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_card_detect_n_cfg(&mut self) -> U1_SDIO_CARD_DETECT_N_CFG_W { - U1_SDIO_CARD_DETECT_N_CFG_W::new(self) + pub fn u1_sdio_card_detect_n_cfg(&mut self) -> U1_SDIO_CARD_DETECT_N_CFG_W { + U1_SDIO_CARD_DETECT_N_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_card_int_n_cfg(&mut self) -> U1_SDIO_CARD_INT_N_CFG_W { - U1_SDIO_CARD_INT_N_CFG_W::new(self) + pub fn u1_sdio_card_int_n_cfg(&mut self) -> U1_SDIO_CARD_INT_N_CFG_W { + U1_SDIO_CARD_INT_N_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_card_write_prt_cfg(&mut self) -> U1_SDIO_CARD_WRITE_PRT_CFG_W { - U1_SDIO_CARD_WRITE_PRT_CFG_W::new(self) + pub fn u1_sdio_card_write_prt_cfg(&mut self) -> U1_SDIO_CARD_WRITE_PRT_CFG_W { + U1_SDIO_CARD_WRITE_PRT_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi44.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi44.rs index 12e3082..e3b363b 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi44.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi44.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u1_sdio_ccmd_in_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CCMD_IN_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_ccmd_in_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CCMD_IN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CCMD_IN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_cdata_in_0_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CDATA_IN_0_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_cdata_in_0_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CDATA_IN_0_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CDATA_IN_0_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_cdata_in_1_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CDATA_IN_1_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_cdata_in_1_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CDATA_IN_1_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CDATA_IN_1_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_cdata_in_2_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CDATA_IN_2_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_cdata_in_2_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CDATA_IN_2_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CDATA_IN_2_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_ccmd_in_cfg(&mut self) -> U1_SDIO_CCMD_IN_CFG_W { - U1_SDIO_CCMD_IN_CFG_W::new(self) + pub fn u1_sdio_ccmd_in_cfg(&mut self) -> U1_SDIO_CCMD_IN_CFG_W { + U1_SDIO_CCMD_IN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_cdata_in_0_cfg(&mut self) -> U1_SDIO_CDATA_IN_0_CFG_W { - U1_SDIO_CDATA_IN_0_CFG_W::new(self) + pub fn u1_sdio_cdata_in_0_cfg(&mut self) -> U1_SDIO_CDATA_IN_0_CFG_W { + U1_SDIO_CDATA_IN_0_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_cdata_in_1_cfg(&mut self) -> U1_SDIO_CDATA_IN_1_CFG_W { - U1_SDIO_CDATA_IN_1_CFG_W::new(self) + pub fn u1_sdio_cdata_in_1_cfg(&mut self) -> U1_SDIO_CDATA_IN_1_CFG_W { + U1_SDIO_CDATA_IN_1_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_cdata_in_2_cfg(&mut self) -> U1_SDIO_CDATA_IN_2_CFG_W { - U1_SDIO_CDATA_IN_2_CFG_W::new(self) + pub fn u1_sdio_cdata_in_2_cfg(&mut self) -> U1_SDIO_CDATA_IN_2_CFG_W { + U1_SDIO_CDATA_IN_2_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi48.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi48.rs index 94f4962..271a793 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi48.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi48.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u1_sdio_cdata_in_3_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CDATA_IN_3_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_cdata_in_3_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CDATA_IN_3_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CDATA_IN_3_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_cdata_in_4_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CDATA_IN_4_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_cdata_in_4_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CDATA_IN_4_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CDATA_IN_4_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_cdata_in_5_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CDATA_IN_5_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_cdata_in_5_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CDATA_IN_5_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CDATA_IN_5_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_cdata_in_6_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CDATA_IN_6_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_cdata_in_6_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CDATA_IN_6_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CDATA_IN_6_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_cdata_in_3_cfg(&mut self) -> U1_SDIO_CDATA_IN_3_CFG_W { - U1_SDIO_CDATA_IN_3_CFG_W::new(self) + pub fn u1_sdio_cdata_in_3_cfg(&mut self) -> U1_SDIO_CDATA_IN_3_CFG_W { + U1_SDIO_CDATA_IN_3_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_cdata_in_4_cfg(&mut self) -> U1_SDIO_CDATA_IN_4_CFG_W { - U1_SDIO_CDATA_IN_4_CFG_W::new(self) + pub fn u1_sdio_cdata_in_4_cfg(&mut self) -> U1_SDIO_CDATA_IN_4_CFG_W { + U1_SDIO_CDATA_IN_4_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_cdata_in_5_cfg(&mut self) -> U1_SDIO_CDATA_IN_5_CFG_W { - U1_SDIO_CDATA_IN_5_CFG_W::new(self) + pub fn u1_sdio_cdata_in_5_cfg(&mut self) -> U1_SDIO_CDATA_IN_5_CFG_W { + U1_SDIO_CDATA_IN_5_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_cdata_in_6_cfg(&mut self) -> U1_SDIO_CDATA_IN_6_CFG_W { - U1_SDIO_CDATA_IN_6_CFG_W::new(self) + pub fn u1_sdio_cdata_in_6_cfg(&mut self) -> U1_SDIO_CDATA_IN_6_CFG_W { + U1_SDIO_CDATA_IN_6_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi52.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi52.rs index aa2e6c9..f67ed50 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi52.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi52.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u1_sdio_cdata_in_7_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_CDATA_IN_7_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_cdata_in_7_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_CDATA_IN_7_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_CDATA_IN_7_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_sdio_data_strobe_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SDIO_DATA_STROBE_CFG_R = crate::FieldReader; #[doc = "Field `u1_sdio_data_strobe_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SDIO_DATA_STROBE_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SDIO_DATA_STROBE_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_uart_cts_n_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_UART_CTS_N_CFG_R = crate::FieldReader; #[doc = "Field `u1_uart_cts_n_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_UART_CTS_N_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_UART_CTS_N_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_uart_sin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_UART_SIN_CFG_R = crate::FieldReader; #[doc = "Field `u1_uart_sin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_UART_SIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_UART_SIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_cdata_in_7_cfg(&mut self) -> U1_SDIO_CDATA_IN_7_CFG_W { - U1_SDIO_CDATA_IN_7_CFG_W::new(self) + pub fn u1_sdio_cdata_in_7_cfg(&mut self) -> U1_SDIO_CDATA_IN_7_CFG_W { + U1_SDIO_CDATA_IN_7_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_sdio_data_strobe_cfg(&mut self) -> U1_SDIO_DATA_STROBE_CFG_W { - U1_SDIO_DATA_STROBE_CFG_W::new(self) + pub fn u1_sdio_data_strobe_cfg(&mut self) -> U1_SDIO_DATA_STROBE_CFG_W { + U1_SDIO_DATA_STROBE_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_uart_cts_n_cfg(&mut self) -> U1_UART_CTS_N_CFG_W { - U1_UART_CTS_N_CFG_W::new(self) + pub fn u1_uart_cts_n_cfg(&mut self) -> U1_UART_CTS_N_CFG_W { + U1_UART_CTS_N_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_uart_sin_cfg(&mut self) -> U1_UART_SIN_CFG_W { - U1_UART_SIN_CFG_W::new(self) + pub fn u1_uart_sin_cfg(&mut self) -> U1_UART_SIN_CFG_W { + U1_UART_SIN_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi56.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi56.rs index b368295..3bd8dde 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi56.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi56.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u1_ssp_spi_ssp_clkin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SSP_SPI_SSP_CLKIN_CFG_R = crate::FieldReader; #[doc = "Field `u1_ssp_spi_ssp_clkin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SSP_SPI_SSP_CLKIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SSP_SPI_SSP_CLKIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_ssp_spi_sspfssin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SSP_SPI_SSPFSSIN_CFG_R = crate::FieldReader; #[doc = "Field `u1_ssp_spi_sspfssin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SSP_SPI_SSPFSSIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SSP_SPI_SSPFSSIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u1_ssp_spi_ssprxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U1_SSP_SPI_SSPRXD_CFG_R = crate::FieldReader; #[doc = "Field `u1_ssp_spi_ssprxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U1_SSP_SPI_SSPRXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U1_SSP_SPI_SSPRXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u2_i2c_ic_clk_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U2_I2C_IC_CLK_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u2_i2c_ic_clk_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U2_I2C_IC_CLK_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U2_I2C_IC_CLK_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_ssp_spi_ssp_clkin_cfg(&mut self) -> U1_SSP_SPI_SSP_CLKIN_CFG_W { - U1_SSP_SPI_SSP_CLKIN_CFG_W::new(self) + pub fn u1_ssp_spi_ssp_clkin_cfg(&mut self) -> U1_SSP_SPI_SSP_CLKIN_CFG_W { + U1_SSP_SPI_SSP_CLKIN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_ssp_spi_sspfssin_cfg(&mut self) -> U1_SSP_SPI_SSPFSSIN_CFG_W { - U1_SSP_SPI_SSPFSSIN_CFG_W::new(self) + pub fn u1_ssp_spi_sspfssin_cfg(&mut self) -> U1_SSP_SPI_SSPFSSIN_CFG_W { + U1_SSP_SPI_SSPFSSIN_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u1_ssp_spi_ssprxd_cfg(&mut self) -> U1_SSP_SPI_SSPRXD_CFG_W { - U1_SSP_SPI_SSPRXD_CFG_W::new(self) + pub fn u1_ssp_spi_ssprxd_cfg(&mut self) -> U1_SSP_SPI_SSPRXD_CFG_W { + U1_SSP_SPI_SSPRXD_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u2_i2c_ic_clk_in_a_cfg(&mut self) -> U2_I2C_IC_CLK_IN_A_CFG_W { - U2_I2C_IC_CLK_IN_A_CFG_W::new(self) + pub fn u2_i2c_ic_clk_in_a_cfg(&mut self) -> U2_I2C_IC_CLK_IN_A_CFG_W { + U2_I2C_IC_CLK_IN_A_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi60.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi60.rs index 5b55320..821d0f9 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi60.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi60.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u2_i2c_ic_data_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U2_I2C_IC_DATA_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u2_i2c_ic_data_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U2_I2C_IC_DATA_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U2_I2C_IC_DATA_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u2_uart_cts_n_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U2_UART_CTS_N_CFG_R = crate::FieldReader; #[doc = "Field `u2_uart_cts_n_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U2_UART_CTS_N_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U2_UART_CTS_N_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u2_uart_sin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U2_UART_SIN_CFG_R = crate::FieldReader; #[doc = "Field `u2_uart_sin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U2_UART_SIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U2_UART_SIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u2_ssp_spi_sspclkin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U2_SSP_SPI_SSPCLKIN_CFG_R = crate::FieldReader; #[doc = "Field `u2_ssp_spi_sspclkin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U2_SSP_SPI_SSPCLKIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U2_SSP_SPI_SSPCLKIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u2_i2c_ic_data_in_a_cfg(&mut self) -> U2_I2C_IC_DATA_IN_A_CFG_W { - U2_I2C_IC_DATA_IN_A_CFG_W::new(self) + pub fn u2_i2c_ic_data_in_a_cfg(&mut self) -> U2_I2C_IC_DATA_IN_A_CFG_W { + U2_I2C_IC_DATA_IN_A_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u2_uart_cts_n_cfg(&mut self) -> U2_UART_CTS_N_CFG_W { - U2_UART_CTS_N_CFG_W::new(self) + pub fn u2_uart_cts_n_cfg(&mut self) -> U2_UART_CTS_N_CFG_W { + U2_UART_CTS_N_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u2_uart_sin_cfg(&mut self) -> U2_UART_SIN_CFG_W { - U2_UART_SIN_CFG_W::new(self) + pub fn u2_uart_sin_cfg(&mut self) -> U2_UART_SIN_CFG_W { + U2_UART_SIN_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u2_ssp_spi_sspclkin_cfg(&mut self) -> U2_SSP_SPI_SSPCLKIN_CFG_W { - U2_SSP_SPI_SSPCLKIN_CFG_W::new(self) + pub fn u2_ssp_spi_sspclkin_cfg(&mut self) -> U2_SSP_SPI_SSPCLKIN_CFG_W { + U2_SSP_SPI_SSPCLKIN_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi64.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi64.rs index 417b4f5..2688fb2 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi64.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi64.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u2_ssp_spi_sspfssin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U2_SSP_SPI_SSPFSSIN_CFG_R = crate::FieldReader; #[doc = "Field `u2_ssp_spi_sspfssin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U2_SSP_SPI_SSPFSSIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U2_SSP_SPI_SSPFSSIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u2_ssp_spi_ssprxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U2_SSP_SPI_SSPRXD_CFG_R = crate::FieldReader; #[doc = "Field `u2_ssp_spi_ssprxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U2_SSP_SPI_SSPRXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U2_SSP_SPI_SSPRXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u3_i2c_ic_clk_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U3_I2C_IC_CLK_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u3_i2c_ic_clk_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U3_I2C_IC_CLK_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U3_I2C_IC_CLK_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u3_i2c_ic_data_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U3_I2C_IC_DATA_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u3_i2c_ic_data_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U3_I2C_IC_DATA_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U3_I2C_IC_DATA_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u2_ssp_spi_sspfssin_cfg(&mut self) -> U2_SSP_SPI_SSPFSSIN_CFG_W { - U2_SSP_SPI_SSPFSSIN_CFG_W::new(self) + pub fn u2_ssp_spi_sspfssin_cfg(&mut self) -> U2_SSP_SPI_SSPFSSIN_CFG_W { + U2_SSP_SPI_SSPFSSIN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u2_ssp_spi_ssprxd_cfg(&mut self) -> U2_SSP_SPI_SSPRXD_CFG_W { - U2_SSP_SPI_SSPRXD_CFG_W::new(self) + pub fn u2_ssp_spi_ssprxd_cfg(&mut self) -> U2_SSP_SPI_SSPRXD_CFG_W { + U2_SSP_SPI_SSPRXD_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u3_i2c_ic_clk_in_a_cfg(&mut self) -> U3_I2C_IC_CLK_IN_A_CFG_W { - U3_I2C_IC_CLK_IN_A_CFG_W::new(self) + pub fn u3_i2c_ic_clk_in_a_cfg(&mut self) -> U3_I2C_IC_CLK_IN_A_CFG_W { + U3_I2C_IC_CLK_IN_A_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u3_i2c_ic_data_in_a_cfg(&mut self) -> U3_I2C_IC_DATA_IN_A_CFG_W { - U3_I2C_IC_DATA_IN_A_CFG_W::new(self) + pub fn u3_i2c_ic_data_in_a_cfg(&mut self) -> U3_I2C_IC_DATA_IN_A_CFG_W { + U3_I2C_IC_DATA_IN_A_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi68.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi68.rs index afd8a13..da670a0 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi68.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi68.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u3_uart_sin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U3_UART_SIN_CFG_R = crate::FieldReader; #[doc = "Field `u3_uart_sin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U3_UART_SIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U3_UART_SIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u3_ssp_spi_sspclkin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U3_SSP_SPI_SSPCLKIN_CFG_R = crate::FieldReader; #[doc = "Field `u3_ssp_spi_sspclkin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U3_SSP_SPI_SSPCLKIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U3_SSP_SPI_SSPCLKIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u3_ssp_spi_sspfssin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U3_SSP_SPI_SSPFSSIN_CFG_R = crate::FieldReader; #[doc = "Field `u3_ssp_spi_sspfssin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U3_SSP_SPI_SSPFSSIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U3_SSP_SPI_SSPFSSIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u3_ssp_spi_ssprxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U3_SSP_SPI_SSPRXD_CFG_R = crate::FieldReader; #[doc = "Field `u3_ssp_spi_ssprxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U3_SSP_SPI_SSPRXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U3_SSP_SPI_SSPRXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u3_uart_sin_cfg(&mut self) -> U3_UART_SIN_CFG_W { - U3_UART_SIN_CFG_W::new(self) + pub fn u3_uart_sin_cfg(&mut self) -> U3_UART_SIN_CFG_W { + U3_UART_SIN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u3_ssp_spi_sspclkin_cfg(&mut self) -> U3_SSP_SPI_SSPCLKIN_CFG_W { - U3_SSP_SPI_SSPCLKIN_CFG_W::new(self) + pub fn u3_ssp_spi_sspclkin_cfg(&mut self) -> U3_SSP_SPI_SSPCLKIN_CFG_W { + U3_SSP_SPI_SSPCLKIN_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u3_ssp_spi_sspfssin_cfg(&mut self) -> U3_SSP_SPI_SSPFSSIN_CFG_W { - U3_SSP_SPI_SSPFSSIN_CFG_W::new(self) + pub fn u3_ssp_spi_sspfssin_cfg(&mut self) -> U3_SSP_SPI_SSPFSSIN_CFG_W { + U3_SSP_SPI_SSPFSSIN_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u3_ssp_spi_ssprxd_cfg(&mut self) -> U3_SSP_SPI_SSPRXD_CFG_W { - U3_SSP_SPI_SSPRXD_CFG_W::new(self) + pub fn u3_ssp_spi_ssprxd_cfg(&mut self) -> U3_SSP_SPI_SSPRXD_CFG_W { + U3_SSP_SPI_SSPRXD_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi72.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi72.rs index 3ddd0a5..e635fb1 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi72.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi72.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u4_i2c_ic_clk_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U4_I2C_IC_CLK_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u4_i2c_ic_clk_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U4_I2C_IC_CLK_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U4_I2C_IC_CLK_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u4_i2c_ic_data_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U4_I2C_IC_DATA_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u4_i2c_ic_data_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U4_I2C_IC_DATA_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U4_I2C_IC_DATA_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u4_uart_cts_n_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U4_UART_CTS_N_CFG_R = crate::FieldReader; #[doc = "Field `u4_uart_cts_n_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U4_UART_CTS_N_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U4_UART_CTS_N_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u4_uart_sin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U4_UART_SIN_CFG_R = crate::FieldReader; #[doc = "Field `u4_uart_sin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U4_UART_SIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U4_UART_SIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u4_i2c_ic_clk_in_a_cfg(&mut self) -> U4_I2C_IC_CLK_IN_A_CFG_W { - U4_I2C_IC_CLK_IN_A_CFG_W::new(self) + pub fn u4_i2c_ic_clk_in_a_cfg(&mut self) -> U4_I2C_IC_CLK_IN_A_CFG_W { + U4_I2C_IC_CLK_IN_A_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u4_i2c_ic_data_in_a_cfg(&mut self) -> U4_I2C_IC_DATA_IN_A_CFG_W { - U4_I2C_IC_DATA_IN_A_CFG_W::new(self) + pub fn u4_i2c_ic_data_in_a_cfg(&mut self) -> U4_I2C_IC_DATA_IN_A_CFG_W { + U4_I2C_IC_DATA_IN_A_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u4_uart_cts_n_cfg(&mut self) -> U4_UART_CTS_N_CFG_W { - U4_UART_CTS_N_CFG_W::new(self) + pub fn u4_uart_cts_n_cfg(&mut self) -> U4_UART_CTS_N_CFG_W { + U4_UART_CTS_N_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u4_uart_sin_cfg(&mut self) -> U4_UART_SIN_CFG_W { - U4_UART_SIN_CFG_W::new(self) + pub fn u4_uart_sin_cfg(&mut self) -> U4_UART_SIN_CFG_W { + U4_UART_SIN_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi76.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi76.rs index 4c808bf..29ec06b 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi76.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi76.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u4_ssp_spi_sspclkin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U4_SSP_SPI_SSPCLKIN_CFG_R = crate::FieldReader; #[doc = "Field `u4_ssp_spi_sspclkin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U4_SSP_SPI_SSPCLKIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U4_SSP_SPI_SSPCLKIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u4_ssp_spi_sspfssin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U4_SSP_SPI_SSPFSSIN_CFG_R = crate::FieldReader; #[doc = "Field `u4_ssp_spi_sspfssin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U4_SSP_SPI_SSPFSSIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U4_SSP_SPI_SSPFSSIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u4_ssp_spi_ssprxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U4_SSP_SPI_SSPRXD_CFG_R = crate::FieldReader; #[doc = "Field `u4_ssp_spi_ssprxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U4_SSP_SPI_SSPRXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U4_SSP_SPI_SSPRXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u5_i2c_ic_clk_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U5_I2C_IC_CLK_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u5_i2c_ic_clk_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U5_I2C_IC_CLK_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U5_I2C_IC_CLK_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u4_ssp_spi_sspclkin_cfg(&mut self) -> U4_SSP_SPI_SSPCLKIN_CFG_W { - U4_SSP_SPI_SSPCLKIN_CFG_W::new(self) + pub fn u4_ssp_spi_sspclkin_cfg(&mut self) -> U4_SSP_SPI_SSPCLKIN_CFG_W { + U4_SSP_SPI_SSPCLKIN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u4_ssp_spi_sspfssin_cfg(&mut self) -> U4_SSP_SPI_SSPFSSIN_CFG_W { - U4_SSP_SPI_SSPFSSIN_CFG_W::new(self) + pub fn u4_ssp_spi_sspfssin_cfg(&mut self) -> U4_SSP_SPI_SSPFSSIN_CFG_W { + U4_SSP_SPI_SSPFSSIN_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u4_ssp_spi_ssprxd_cfg(&mut self) -> U4_SSP_SPI_SSPRXD_CFG_W { - U4_SSP_SPI_SSPRXD_CFG_W::new(self) + pub fn u4_ssp_spi_ssprxd_cfg(&mut self) -> U4_SSP_SPI_SSPRXD_CFG_W { + U4_SSP_SPI_SSPRXD_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u5_i2c_ic_clk_in_a_cfg(&mut self) -> U5_I2C_IC_CLK_IN_A_CFG_W { - U5_I2C_IC_CLK_IN_A_CFG_W::new(self) + pub fn u5_i2c_ic_clk_in_a_cfg(&mut self) -> U5_I2C_IC_CLK_IN_A_CFG_W { + U5_I2C_IC_CLK_IN_A_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi8.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi8.rs index b08bd05..c232295 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi8.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi8.rs @@ -5,20 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_dom_vout_top_u0_hdmi_tx_pin_hpd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD_CFG_R = crate::FieldReader; #[doc = "Field `u0_dom_vout_top_u0_hdmi_tx_pin_hpd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD_CFG_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 7, O>; +pub type U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_i2c_ic_clk_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_I2C_IC_CLK_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u0_i2c_ic_clk_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_I2C_IC_CLK_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_I2C_IC_CLK_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_i2c_ic_data_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_I2C_IC_DATA_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u0_i2c_ic_data_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_I2C_IC_DATA_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_I2C_IC_DATA_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u0_sdio_card_detect_n_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U0_SDIO_CARD_DETECT_N_CFG_R = crate::FieldReader; #[doc = "Field `u0_sdio_card_detect_n_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U0_SDIO_CARD_DETECT_N_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U0_SDIO_CARD_DETECT_N_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -49,28 +48,32 @@ impl W { #[must_use] pub fn u0_dom_vout_top_u0_hdmi_tx_pin_hpd_cfg( &mut self, - ) -> U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD_CFG_W { - U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD_CFG_W::new(self) + ) -> U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD_CFG_W { + U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_i2c_ic_clk_in_a_cfg(&mut self) -> U0_I2C_IC_CLK_IN_A_CFG_W { - U0_I2C_IC_CLK_IN_A_CFG_W::new(self) + pub fn u0_i2c_ic_clk_in_a_cfg(&mut self) -> U0_I2C_IC_CLK_IN_A_CFG_W { + U0_I2C_IC_CLK_IN_A_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_i2c_ic_data_in_a_cfg(&mut self) -> U0_I2C_IC_DATA_IN_A_CFG_W { - U0_I2C_IC_DATA_IN_A_CFG_W::new(self) + pub fn u0_i2c_ic_data_in_a_cfg(&mut self) -> U0_I2C_IC_DATA_IN_A_CFG_W { + U0_I2C_IC_DATA_IN_A_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u0_sdio_card_detect_n_cfg(&mut self) -> U0_SDIO_CARD_DETECT_N_CFG_W { - U0_SDIO_CARD_DETECT_N_CFG_W::new(self) + pub fn u0_sdio_card_detect_n_cfg(&mut self) -> U0_SDIO_CARD_DETECT_N_CFG_W { + U0_SDIO_CARD_DETECT_N_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi80.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi80.rs index d553591..b73a4ea 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi80.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi80.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u5_i2c_ic_data_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U5_I2C_IC_DATA_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u5_i2c_ic_data_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U5_I2C_IC_DATA_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U5_I2C_IC_DATA_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u5_uart_cts_n_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U5_UART_CTS_N_CFG_R = crate::FieldReader; #[doc = "Field `u5_uart_cts_n_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U5_UART_CTS_N_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U5_UART_CTS_N_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u5_uart_sin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U5_UART_SIN_CFG_R = crate::FieldReader; #[doc = "Field `u5_uart_sin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U5_UART_SIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U5_UART_SIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u5_ssp_spi_sspclkin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U5_SSP_SPI_SSPCLKIN_CFG_R = crate::FieldReader; #[doc = "Field `u5_ssp_spi_sspclkin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U5_SSP_SPI_SSPCLKIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U5_SSP_SPI_SSPCLKIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u5_i2c_ic_data_in_a_cfg(&mut self) -> U5_I2C_IC_DATA_IN_A_CFG_W { - U5_I2C_IC_DATA_IN_A_CFG_W::new(self) + pub fn u5_i2c_ic_data_in_a_cfg(&mut self) -> U5_I2C_IC_DATA_IN_A_CFG_W { + U5_I2C_IC_DATA_IN_A_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u5_uart_cts_n_cfg(&mut self) -> U5_UART_CTS_N_CFG_W { - U5_UART_CTS_N_CFG_W::new(self) + pub fn u5_uart_cts_n_cfg(&mut self) -> U5_UART_CTS_N_CFG_W { + U5_UART_CTS_N_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u5_uart_sin_cfg(&mut self) -> U5_UART_SIN_CFG_W { - U5_UART_SIN_CFG_W::new(self) + pub fn u5_uart_sin_cfg(&mut self) -> U5_UART_SIN_CFG_W { + U5_UART_SIN_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u5_ssp_spi_sspclkin_cfg(&mut self) -> U5_SSP_SPI_SSPCLKIN_CFG_W { - U5_SSP_SPI_SSPCLKIN_CFG_W::new(self) + pub fn u5_ssp_spi_sspclkin_cfg(&mut self) -> U5_SSP_SPI_SSPCLKIN_CFG_W { + U5_SSP_SPI_SSPCLKIN_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi84.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi84.rs index d9bf866..0105ddf 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi84.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi84.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u5_ssp_spi_sspfssin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U5_SSP_SPI_SSPFSSIN_CFG_R = crate::FieldReader; #[doc = "Field `u5_ssp_spi_sspfssin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U5_SSP_SPI_SSPFSSIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U5_SSP_SPI_SSPFSSIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u5_ssp_spi_ssprxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U5_SSP_SPI_SSPRXD_CFG_R = crate::FieldReader; #[doc = "Field `u5_ssp_spi_ssprxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U5_SSP_SPI_SSPRXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U5_SSP_SPI_SSPRXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u6_i2c_ic_clk_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U6_I2C_IC_CLK_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u6_i2c_ic_clk_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U6_I2C_IC_CLK_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U6_I2C_IC_CLK_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u6_i2c_ic_data_in_a_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U6_I2C_IC_DATA_IN_A_CFG_R = crate::FieldReader; #[doc = "Field `u6_i2c_ic_data_in_a_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U6_I2C_IC_DATA_IN_A_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U6_I2C_IC_DATA_IN_A_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u5_ssp_spi_sspfssin_cfg(&mut self) -> U5_SSP_SPI_SSPFSSIN_CFG_W { - U5_SSP_SPI_SSPFSSIN_CFG_W::new(self) + pub fn u5_ssp_spi_sspfssin_cfg(&mut self) -> U5_SSP_SPI_SSPFSSIN_CFG_W { + U5_SSP_SPI_SSPFSSIN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u5_ssp_spi_ssprxd_cfg(&mut self) -> U5_SSP_SPI_SSPRXD_CFG_W { - U5_SSP_SPI_SSPRXD_CFG_W::new(self) + pub fn u5_ssp_spi_ssprxd_cfg(&mut self) -> U5_SSP_SPI_SSPRXD_CFG_W { + U5_SSP_SPI_SSPRXD_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u6_i2c_ic_clk_in_a_cfg(&mut self) -> U6_I2C_IC_CLK_IN_A_CFG_W { - U6_I2C_IC_CLK_IN_A_CFG_W::new(self) + pub fn u6_i2c_ic_clk_in_a_cfg(&mut self) -> U6_I2C_IC_CLK_IN_A_CFG_W { + U6_I2C_IC_CLK_IN_A_CFG_W::new(self, 16) } #[doc = "Bits 24:30 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u6_i2c_ic_data_in_a_cfg(&mut self) -> U6_I2C_IC_DATA_IN_A_CFG_W { - U6_I2C_IC_DATA_IN_A_CFG_W::new(self) + pub fn u6_i2c_ic_data_in_a_cfg(&mut self) -> U6_I2C_IC_DATA_IN_A_CFG_W { + U6_I2C_IC_DATA_IN_A_CFG_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi88.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi88.rs index 434a4f8..24a4519 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi88.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpi88.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `u6_ssp_spi_sspclkin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U6_SSP_SPI_SSPCLKIN_CFG_R = crate::FieldReader; #[doc = "Field `u6_ssp_spi_sspclkin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U6_SSP_SPI_SSPCLKIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U6_SSP_SPI_SSPCLKIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u6_ssp_spi_sspfssin_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U6_SSP_SPI_SSPFSSIN_CFG_R = crate::FieldReader; #[doc = "Field `u6_ssp_spi_sspfssin_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U6_SSP_SPI_SSPFSSIN_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U6_SSP_SPI_SSPFSSIN_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `u6_ssp_spi_ssprxd_cfg` reader - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] pub type U6_SSP_SPI_SSPRXD_CFG_R = crate::FieldReader; #[doc = "Field `u6_ssp_spi_ssprxd_cfg` writer - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] -pub type U6_SSP_SPI_SSPRXD_CFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type U6_SSP_SPI_SSPRXD_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bits 0:6 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u6_ssp_spi_sspclkin_cfg(&mut self) -> U6_SSP_SPI_SSPCLKIN_CFG_W { - U6_SSP_SPI_SSPCLKIN_CFG_W::new(self) + pub fn u6_ssp_spi_sspclkin_cfg(&mut self) -> U6_SSP_SPI_SSPCLKIN_CFG_W { + U6_SSP_SPI_SSPCLKIN_CFG_W::new(self, 0) } #[doc = "Bits 8:14 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u6_ssp_spi_sspfssin_cfg(&mut self) -> U6_SSP_SPI_SSPFSSIN_CFG_W { - U6_SSP_SPI_SSPFSSIN_CFG_W::new(self) + pub fn u6_ssp_spi_sspfssin_cfg(&mut self) -> U6_SSP_SPI_SSPFSSIN_CFG_W { + U6_SSP_SPI_SSPFSSIN_CFG_W::new(self, 8) } #[doc = "Bits 16:22 - The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal."] #[inline(always)] #[must_use] - pub fn u6_ssp_spi_ssprxd_cfg(&mut self) -> U6_SSP_SPI_SSPRXD_CFG_W { - U6_SSP_SPI_SSPRXD_CFG_W::new(self) + pub fn u6_ssp_spi_ssprxd_cfg(&mut self) -> U6_SSP_SPI_SSPRXD_CFG_W { + U6_SSP_SPI_SSPRXD_CFG_W::new(self, 16) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen0.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen0.rs index 5611e71..b7112dd 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen0.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen0.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo0_doen` reader - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO0_DOEN_R = crate::FieldReader; #[doc = "Field `gpo0_doen` writer - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO0_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO0_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo1_doen` reader - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO1_DOEN_R = crate::FieldReader; #[doc = "Field `gpo1_doen` writer - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO1_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO1_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo2_doen` reader - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO2_DOEN_R = crate::FieldReader; #[doc = "Field `gpo2_doen` writer - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO2_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO2_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo3_doen` reader - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO3_DOEN_R = crate::FieldReader; #[doc = "Field `gpo3_doen` writer - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO3_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO3_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo0_doen(&mut self) -> GPO0_DOEN_W { - GPO0_DOEN_W::new(self) + pub fn gpo0_doen(&mut self) -> GPO0_DOEN_W { + GPO0_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo1_doen(&mut self) -> GPO1_DOEN_W { - GPO1_DOEN_W::new(self) + pub fn gpo1_doen(&mut self) -> GPO1_DOEN_W { + GPO1_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo2_doen(&mut self) -> GPO2_DOEN_W { - GPO2_DOEN_W::new(self) + pub fn gpo2_doen(&mut self) -> GPO2_DOEN_W { + GPO2_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo3_doen(&mut self) -> GPO3_DOEN_W { - GPO3_DOEN_W::new(self) + pub fn gpo3_doen(&mut self) -> GPO3_DOEN_W { + GPO3_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen1.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen1.rs index e207bda..01b3e21 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen1.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen1.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo4_doen` reader - The selected OEN signal for GPIO4. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO4_DOEN_R = crate::FieldReader; #[doc = "Field `gpo4_doen` writer - The selected OEN signal for GPIO4. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO4_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO4_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo5_doen` reader - The selected OEN signal for GPIO5. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO5_DOEN_R = crate::FieldReader; #[doc = "Field `gpo5_doen` writer - The selected OEN signal for GPIO5. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO5_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO5_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo6_doen` reader - The selected OEN signal for GPIO6. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO6_DOEN_R = crate::FieldReader; #[doc = "Field `gpo6_doen` writer - The selected OEN signal for GPIO6. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO6_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO6_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo7_doen` reader - The selected OEN signal for GPIO7. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO7_DOEN_R = crate::FieldReader; #[doc = "Field `gpo7_doen` writer - The selected OEN signal for GPIO7. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO7_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO7_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO4. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO4. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo4_doen(&mut self) -> GPO4_DOEN_W { - GPO4_DOEN_W::new(self) + pub fn gpo4_doen(&mut self) -> GPO4_DOEN_W { + GPO4_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO5. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo5_doen(&mut self) -> GPO5_DOEN_W { - GPO5_DOEN_W::new(self) + pub fn gpo5_doen(&mut self) -> GPO5_DOEN_W { + GPO5_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO6. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo6_doen(&mut self) -> GPO6_DOEN_W { - GPO6_DOEN_W::new(self) + pub fn gpo6_doen(&mut self) -> GPO6_DOEN_W { + GPO6_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO7. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo7_doen(&mut self) -> GPO7_DOEN_W { - GPO7_DOEN_W::new(self) + pub fn gpo7_doen(&mut self) -> GPO7_DOEN_W { + GPO7_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen10.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen10.rs index 7151d68..2b83644 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen10.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen10.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo40_doen` reader - The selected OEN signal for GPIO40. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO40_DOEN_R = crate::FieldReader; #[doc = "Field `gpo40_doen` writer - The selected OEN signal for GPIO40. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO40_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO40_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo41_doen` reader - The selected OEN signal for GPIO41. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO41_DOEN_R = crate::FieldReader; #[doc = "Field `gpo41_doen` writer - The selected OEN signal for GPIO41. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO41_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO41_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo42_doen` reader - The selected OEN signal for GPIO42. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO42_DOEN_R = crate::FieldReader; #[doc = "Field `gpo42_doen` writer - The selected OEN signal for GPIO42. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO42_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO42_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo43_doen` reader - The selected OEN signal for GPIO43. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO43_DOEN_R = crate::FieldReader; #[doc = "Field `gpo43_doen` writer - The selected OEN signal for GPIO43. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO43_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO43_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO40. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO40. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo40_doen(&mut self) -> GPO40_DOEN_W { - GPO40_DOEN_W::new(self) + pub fn gpo40_doen(&mut self) -> GPO40_DOEN_W { + GPO40_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO41. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo41_doen(&mut self) -> GPO41_DOEN_W { - GPO41_DOEN_W::new(self) + pub fn gpo41_doen(&mut self) -> GPO41_DOEN_W { + GPO41_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO42. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo42_doen(&mut self) -> GPO42_DOEN_W { - GPO42_DOEN_W::new(self) + pub fn gpo42_doen(&mut self) -> GPO42_DOEN_W { + GPO42_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO43. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo43_doen(&mut self) -> GPO43_DOEN_W { - GPO43_DOEN_W::new(self) + pub fn gpo43_doen(&mut self) -> GPO43_DOEN_W { + GPO43_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen11.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen11.rs index 8fca58e..01e66b1 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen11.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen11.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo44_doen` reader - The selected OEN signal for GPIO44. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO44_DOEN_R = crate::FieldReader; #[doc = "Field `gpo44_doen` writer - The selected OEN signal for GPIO44. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO44_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO44_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo45_doen` reader - The selected OEN signal for GPIO45. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO45_DOEN_R = crate::FieldReader; #[doc = "Field `gpo45_doen` writer - The selected OEN signal for GPIO45. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO45_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO45_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo46_doen` reader - The selected OEN signal for GPIO46. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO46_DOEN_R = crate::FieldReader; #[doc = "Field `gpo46_doen` writer - The selected OEN signal for GPIO46. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO46_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO46_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo47_doen` reader - The selected OEN signal for GPIO47. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO47_DOEN_R = crate::FieldReader; #[doc = "Field `gpo47_doen` writer - The selected OEN signal for GPIO47. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO47_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO47_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO44. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO44. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo44_doen(&mut self) -> GPO44_DOEN_W { - GPO44_DOEN_W::new(self) + pub fn gpo44_doen(&mut self) -> GPO44_DOEN_W { + GPO44_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO45. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo45_doen(&mut self) -> GPO45_DOEN_W { - GPO45_DOEN_W::new(self) + pub fn gpo45_doen(&mut self) -> GPO45_DOEN_W { + GPO45_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO46. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo46_doen(&mut self) -> GPO46_DOEN_W { - GPO46_DOEN_W::new(self) + pub fn gpo46_doen(&mut self) -> GPO46_DOEN_W { + GPO46_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO47. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo47_doen(&mut self) -> GPO47_DOEN_W { - GPO47_DOEN_W::new(self) + pub fn gpo47_doen(&mut self) -> GPO47_DOEN_W { + GPO47_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen12.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen12.rs index 9e4ea16..bf2ebe9 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen12.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen12.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo48_doen` reader - The selected OEN signal for GPIO48. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO48_DOEN_R = crate::FieldReader; #[doc = "Field `gpo48_doen` writer - The selected OEN signal for GPIO48. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO48_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO48_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo49_doen` reader - The selected OEN signal for GPIO49. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO49_DOEN_R = crate::FieldReader; #[doc = "Field `gpo49_doen` writer - The selected OEN signal for GPIO49. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO49_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO49_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo50_doen` reader - The selected OEN signal for GPIO50. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO50_DOEN_R = crate::FieldReader; #[doc = "Field `gpo50_doen` writer - The selected OEN signal for GPIO50. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO50_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO50_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo51_doen` reader - The selected OEN signal for GPIO51. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO51_DOEN_R = crate::FieldReader; #[doc = "Field `gpo51_doen` writer - The selected OEN signal for GPIO51. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO51_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO51_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO48. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO48. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo48_doen(&mut self) -> GPO48_DOEN_W { - GPO48_DOEN_W::new(self) + pub fn gpo48_doen(&mut self) -> GPO48_DOEN_W { + GPO48_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO49. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo49_doen(&mut self) -> GPO49_DOEN_W { - GPO49_DOEN_W::new(self) + pub fn gpo49_doen(&mut self) -> GPO49_DOEN_W { + GPO49_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO50. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo50_doen(&mut self) -> GPO50_DOEN_W { - GPO50_DOEN_W::new(self) + pub fn gpo50_doen(&mut self) -> GPO50_DOEN_W { + GPO50_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO51. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo51_doen(&mut self) -> GPO51_DOEN_W { - GPO51_DOEN_W::new(self) + pub fn gpo51_doen(&mut self) -> GPO51_DOEN_W { + GPO51_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen13.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen13.rs index b8ff102..c068311 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen13.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen13.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo52_doen` reader - The selected OEN signal for GPIO52. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO52_DOEN_R = crate::FieldReader; #[doc = "Field `gpo52_doen` writer - The selected OEN signal for GPIO52. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO52_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO52_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo53_doen` reader - The selected OEN signal for GPIO53. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO53_DOEN_R = crate::FieldReader; #[doc = "Field `gpo53_doen` writer - The selected OEN signal for GPIO53. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO53_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO53_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo54_doen` reader - The selected OEN signal for GPIO54. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO54_DOEN_R = crate::FieldReader; #[doc = "Field `gpo54_doen` writer - The selected OEN signal for GPIO54. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO54_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO54_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo55_doen` reader - The selected OEN signal for GPIO55. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO55_DOEN_R = crate::FieldReader; #[doc = "Field `gpo55_doen` writer - The selected OEN signal for GPIO55. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO55_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO55_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO52. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO52. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo52_doen(&mut self) -> GPO52_DOEN_W { - GPO52_DOEN_W::new(self) + pub fn gpo52_doen(&mut self) -> GPO52_DOEN_W { + GPO52_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO53. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo53_doen(&mut self) -> GPO53_DOEN_W { - GPO53_DOEN_W::new(self) + pub fn gpo53_doen(&mut self) -> GPO53_DOEN_W { + GPO53_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO54. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo54_doen(&mut self) -> GPO54_DOEN_W { - GPO54_DOEN_W::new(self) + pub fn gpo54_doen(&mut self) -> GPO54_DOEN_W { + GPO54_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO55. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo55_doen(&mut self) -> GPO55_DOEN_W { - GPO55_DOEN_W::new(self) + pub fn gpo55_doen(&mut self) -> GPO55_DOEN_W { + GPO55_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen14.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen14.rs index a188c89..e77e208 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen14.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen14.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo56_doen` reader - The selected OEN signal for GPIO56. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO56_DOEN_R = crate::FieldReader; #[doc = "Field `gpo56_doen` writer - The selected OEN signal for GPIO56. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO56_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO56_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo57_doen` reader - The selected OEN signal for GPIO57. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO57_DOEN_R = crate::FieldReader; #[doc = "Field `gpo57_doen` writer - The selected OEN signal for GPIO57. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO57_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO57_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo58_doen` reader - The selected OEN signal for GPIO58. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO58_DOEN_R = crate::FieldReader; #[doc = "Field `gpo58_doen` writer - The selected OEN signal for GPIO58. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO58_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO58_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo59_doen` reader - The selected OEN signal for GPIO59. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO59_DOEN_R = crate::FieldReader; #[doc = "Field `gpo59_doen` writer - The selected OEN signal for GPIO59. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO59_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO59_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO56. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO56. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo56_doen(&mut self) -> GPO56_DOEN_W { - GPO56_DOEN_W::new(self) + pub fn gpo56_doen(&mut self) -> GPO56_DOEN_W { + GPO56_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO57. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo57_doen(&mut self) -> GPO57_DOEN_W { - GPO57_DOEN_W::new(self) + pub fn gpo57_doen(&mut self) -> GPO57_DOEN_W { + GPO57_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO58. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo58_doen(&mut self) -> GPO58_DOEN_W { - GPO58_DOEN_W::new(self) + pub fn gpo58_doen(&mut self) -> GPO58_DOEN_W { + GPO58_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO59. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo59_doen(&mut self) -> GPO59_DOEN_W { - GPO59_DOEN_W::new(self) + pub fn gpo59_doen(&mut self) -> GPO59_DOEN_W { + GPO59_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen15.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen15.rs index cbb8548..72c085a 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen15.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen15.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo60_doen` reader - The selected OEN signal for GPIO60. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO60_DOEN_R = crate::FieldReader; #[doc = "Field `gpo60_doen` writer - The selected OEN signal for GPIO60. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO60_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO60_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo61_doen` reader - The selected OEN signal for GPIO61. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO61_DOEN_R = crate::FieldReader; #[doc = "Field `gpo61_doen` writer - The selected OEN signal for GPIO61. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO61_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO61_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo62_doen` reader - The selected OEN signal for GPIO62. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO62_DOEN_R = crate::FieldReader; #[doc = "Field `gpo62_doen` writer - The selected OEN signal for GPIO62. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO62_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO62_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo63_doen` reader - The selected OEN signal for GPIO63. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO63_DOEN_R = crate::FieldReader; #[doc = "Field `gpo63_doen` writer - The selected OEN signal for GPIO63. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO63_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO63_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO60. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO60. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo60_doen(&mut self) -> GPO60_DOEN_W { - GPO60_DOEN_W::new(self) + pub fn gpo60_doen(&mut self) -> GPO60_DOEN_W { + GPO60_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO61. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo61_doen(&mut self) -> GPO61_DOEN_W { - GPO61_DOEN_W::new(self) + pub fn gpo61_doen(&mut self) -> GPO61_DOEN_W { + GPO61_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO62. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo62_doen(&mut self) -> GPO62_DOEN_W { - GPO62_DOEN_W::new(self) + pub fn gpo62_doen(&mut self) -> GPO62_DOEN_W { + GPO62_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO63. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo63_doen(&mut self) -> GPO63_DOEN_W { - GPO63_DOEN_W::new(self) + pub fn gpo63_doen(&mut self) -> GPO63_DOEN_W { + GPO63_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen2.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen2.rs index 0ed4ed6..9d72adf 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen2.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen2.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo8_doen` reader - The selected OEN signal for GPIO8. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO8_DOEN_R = crate::FieldReader; #[doc = "Field `gpo8_doen` writer - The selected OEN signal for GPIO8. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO8_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO8_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo9_doen` reader - The selected OEN signal for GPIO9. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO9_DOEN_R = crate::FieldReader; #[doc = "Field `gpo9_doen` writer - The selected OEN signal for GPIO9. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO9_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO9_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo10_doen` reader - The selected OEN signal for GPIO10. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO10_DOEN_R = crate::FieldReader; #[doc = "Field `gpo10_doen` writer - The selected OEN signal for GPIO10. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO10_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO10_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo11_doen` reader - The selected OEN signal for GPIO11. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO11_DOEN_R = crate::FieldReader; #[doc = "Field `gpo11_doen` writer - The selected OEN signal for GPIO11. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO11_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO11_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO8. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO8. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo8_doen(&mut self) -> GPO8_DOEN_W { - GPO8_DOEN_W::new(self) + pub fn gpo8_doen(&mut self) -> GPO8_DOEN_W { + GPO8_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO9. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo9_doen(&mut self) -> GPO9_DOEN_W { - GPO9_DOEN_W::new(self) + pub fn gpo9_doen(&mut self) -> GPO9_DOEN_W { + GPO9_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO10. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo10_doen(&mut self) -> GPO10_DOEN_W { - GPO10_DOEN_W::new(self) + pub fn gpo10_doen(&mut self) -> GPO10_DOEN_W { + GPO10_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO11. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo11_doen(&mut self) -> GPO11_DOEN_W { - GPO11_DOEN_W::new(self) + pub fn gpo11_doen(&mut self) -> GPO11_DOEN_W { + GPO11_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen3.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen3.rs index 2042885..1d666a6 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen3.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen3.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo12_doen` reader - The selected OEN signal for GPIO12. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO12_DOEN_R = crate::FieldReader; #[doc = "Field `gpo12_doen` writer - The selected OEN signal for GPIO12. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO12_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO12_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo13_doen` reader - The selected OEN signal for GPIO13. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO13_DOEN_R = crate::FieldReader; #[doc = "Field `gpo13_doen` writer - The selected OEN signal for GPIO13. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO13_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO13_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo14_doen` reader - The selected OEN signal for GPIO14. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO14_DOEN_R = crate::FieldReader; #[doc = "Field `gpo14_doen` writer - The selected OEN signal for GPIO14. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO14_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO14_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo15_doen` reader - The selected OEN signal for GPIO15. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO15_DOEN_R = crate::FieldReader; #[doc = "Field `gpo15_doen` writer - The selected OEN signal for GPIO15. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO15_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO15_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO12. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO12. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo12_doen(&mut self) -> GPO12_DOEN_W { - GPO12_DOEN_W::new(self) + pub fn gpo12_doen(&mut self) -> GPO12_DOEN_W { + GPO12_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO13. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo13_doen(&mut self) -> GPO13_DOEN_W { - GPO13_DOEN_W::new(self) + pub fn gpo13_doen(&mut self) -> GPO13_DOEN_W { + GPO13_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO14. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo14_doen(&mut self) -> GPO14_DOEN_W { - GPO14_DOEN_W::new(self) + pub fn gpo14_doen(&mut self) -> GPO14_DOEN_W { + GPO14_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO15. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo15_doen(&mut self) -> GPO15_DOEN_W { - GPO15_DOEN_W::new(self) + pub fn gpo15_doen(&mut self) -> GPO15_DOEN_W { + GPO15_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen4.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen4.rs index fd8736f..f34eff2 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen4.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen4.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo16_doen` reader - The selected OEN signal for GPIO16. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO16_DOEN_R = crate::FieldReader; #[doc = "Field `gpo16_doen` writer - The selected OEN signal for GPIO16. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO16_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO16_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo17_doen` reader - The selected OEN signal for GPIO17. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO17_DOEN_R = crate::FieldReader; #[doc = "Field `gpo17_doen` writer - The selected OEN signal for GPIO17. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO17_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO17_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo18_doen` reader - The selected OEN signal for GPIO18. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO18_DOEN_R = crate::FieldReader; #[doc = "Field `gpo18_doen` writer - The selected OEN signal for GPIO18. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO18_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO18_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo19_doen` reader - The selected OEN signal for GPIO19. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO19_DOEN_R = crate::FieldReader; #[doc = "Field `gpo19_doen` writer - The selected OEN signal for GPIO19. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO19_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO19_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO16. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO16. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo16_doen(&mut self) -> GPO16_DOEN_W { - GPO16_DOEN_W::new(self) + pub fn gpo16_doen(&mut self) -> GPO16_DOEN_W { + GPO16_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO17. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo17_doen(&mut self) -> GPO17_DOEN_W { - GPO17_DOEN_W::new(self) + pub fn gpo17_doen(&mut self) -> GPO17_DOEN_W { + GPO17_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO18. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo18_doen(&mut self) -> GPO18_DOEN_W { - GPO18_DOEN_W::new(self) + pub fn gpo18_doen(&mut self) -> GPO18_DOEN_W { + GPO18_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO19. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo19_doen(&mut self) -> GPO19_DOEN_W { - GPO19_DOEN_W::new(self) + pub fn gpo19_doen(&mut self) -> GPO19_DOEN_W { + GPO19_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen5.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen5.rs index d43811a..d7c5e2d 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen5.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen5.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo20_doen` reader - The selected OEN signal for GPIO20. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO20_DOEN_R = crate::FieldReader; #[doc = "Field `gpo20_doen` writer - The selected OEN signal for GPIO20. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO20_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO20_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo21_doen` reader - The selected OEN signal for GPIO21. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO21_DOEN_R = crate::FieldReader; #[doc = "Field `gpo21_doen` writer - The selected OEN signal for GPIO21. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO21_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO21_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo22_doen` reader - The selected OEN signal for GPIO22. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO22_DOEN_R = crate::FieldReader; #[doc = "Field `gpo22_doen` writer - The selected OEN signal for GPIO22. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO22_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO22_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo23_doen` reader - The selected OEN signal for GPIO23. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO23_DOEN_R = crate::FieldReader; #[doc = "Field `gpo23_doen` writer - The selected OEN signal for GPIO23. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO23_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO23_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO20. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO20. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo20_doen(&mut self) -> GPO20_DOEN_W { - GPO20_DOEN_W::new(self) + pub fn gpo20_doen(&mut self) -> GPO20_DOEN_W { + GPO20_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO21. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo21_doen(&mut self) -> GPO21_DOEN_W { - GPO21_DOEN_W::new(self) + pub fn gpo21_doen(&mut self) -> GPO21_DOEN_W { + GPO21_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO22. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo22_doen(&mut self) -> GPO22_DOEN_W { - GPO22_DOEN_W::new(self) + pub fn gpo22_doen(&mut self) -> GPO22_DOEN_W { + GPO22_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO23. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo23_doen(&mut self) -> GPO23_DOEN_W { - GPO23_DOEN_W::new(self) + pub fn gpo23_doen(&mut self) -> GPO23_DOEN_W { + GPO23_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen6.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen6.rs index 268132c..4d11af1 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen6.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen6.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo24_doen` reader - The selected OEN signal for GPIO24. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO24_DOEN_R = crate::FieldReader; #[doc = "Field `gpo24_doen` writer - The selected OEN signal for GPIO24. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO24_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO24_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo25_doen` reader - The selected OEN signal for GPIO25. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO25_DOEN_R = crate::FieldReader; #[doc = "Field `gpo25_doen` writer - The selected OEN signal for GPIO25. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO25_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO25_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo26_doen` reader - The selected OEN signal for GPIO26. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO26_DOEN_R = crate::FieldReader; #[doc = "Field `gpo26_doen` writer - The selected OEN signal for GPIO26. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO26_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO26_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo27_doen` reader - The selected OEN signal for GPIO27. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO27_DOEN_R = crate::FieldReader; #[doc = "Field `gpo27_doen` writer - The selected OEN signal for GPIO27. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO27_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO27_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO24. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO24. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo24_doen(&mut self) -> GPO24_DOEN_W { - GPO24_DOEN_W::new(self) + pub fn gpo24_doen(&mut self) -> GPO24_DOEN_W { + GPO24_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO25. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo25_doen(&mut self) -> GPO25_DOEN_W { - GPO25_DOEN_W::new(self) + pub fn gpo25_doen(&mut self) -> GPO25_DOEN_W { + GPO25_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO26. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo26_doen(&mut self) -> GPO26_DOEN_W { - GPO26_DOEN_W::new(self) + pub fn gpo26_doen(&mut self) -> GPO26_DOEN_W { + GPO26_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO27. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo27_doen(&mut self) -> GPO27_DOEN_W { - GPO27_DOEN_W::new(self) + pub fn gpo27_doen(&mut self) -> GPO27_DOEN_W { + GPO27_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen7.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen7.rs index aba3198..daf7d4b 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen7.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen7.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo28_doen` reader - The selected OEN signal for GPIO28. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO28_DOEN_R = crate::FieldReader; #[doc = "Field `gpo28_doen` writer - The selected OEN signal for GPIO28. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO28_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO28_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo29_doen` reader - The selected OEN signal for GPIO29. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO29_DOEN_R = crate::FieldReader; #[doc = "Field `gpo29_doen` writer - The selected OEN signal for GPIO29. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO29_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO29_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo30_doen` reader - The selected OEN signal for GPIO30. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO30_DOEN_R = crate::FieldReader; #[doc = "Field `gpo30_doen` writer - The selected OEN signal for GPIO30. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO30_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO30_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo31_doen` reader - The selected OEN signal for GPIO31. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO31_DOEN_R = crate::FieldReader; #[doc = "Field `gpo31_doen` writer - The selected OEN signal for GPIO31. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO31_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO31_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO28. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO28. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo28_doen(&mut self) -> GPO28_DOEN_W { - GPO28_DOEN_W::new(self) + pub fn gpo28_doen(&mut self) -> GPO28_DOEN_W { + GPO28_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO29. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo29_doen(&mut self) -> GPO29_DOEN_W { - GPO29_DOEN_W::new(self) + pub fn gpo29_doen(&mut self) -> GPO29_DOEN_W { + GPO29_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO30. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo30_doen(&mut self) -> GPO30_DOEN_W { - GPO30_DOEN_W::new(self) + pub fn gpo30_doen(&mut self) -> GPO30_DOEN_W { + GPO30_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO31. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo31_doen(&mut self) -> GPO31_DOEN_W { - GPO31_DOEN_W::new(self) + pub fn gpo31_doen(&mut self) -> GPO31_DOEN_W { + GPO31_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen8.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen8.rs index 18a42cc..4699ba1 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen8.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen8.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo32_doen` reader - The selected OEN signal for GPIO32. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO32_DOEN_R = crate::FieldReader; #[doc = "Field `gpo32_doen` writer - The selected OEN signal for GPIO32. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO32_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO32_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo33_doen` reader - The selected OEN signal for GPIO33. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO33_DOEN_R = crate::FieldReader; #[doc = "Field `gpo33_doen` writer - The selected OEN signal for GPIO33. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO33_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO33_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo34_doen` reader - The selected OEN signal for GPIO34. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO34_DOEN_R = crate::FieldReader; #[doc = "Field `gpo34_doen` writer - The selected OEN signal for GPIO34. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO34_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO34_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo35_doen` reader - The selected OEN signal for GPIO35. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO35_DOEN_R = crate::FieldReader; #[doc = "Field `gpo35_doen` writer - The selected OEN signal for GPIO35. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO35_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO35_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO32. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO32. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo32_doen(&mut self) -> GPO32_DOEN_W { - GPO32_DOEN_W::new(self) + pub fn gpo32_doen(&mut self) -> GPO32_DOEN_W { + GPO32_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO33. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo33_doen(&mut self) -> GPO33_DOEN_W { - GPO33_DOEN_W::new(self) + pub fn gpo33_doen(&mut self) -> GPO33_DOEN_W { + GPO33_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO34. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo34_doen(&mut self) -> GPO34_DOEN_W { - GPO34_DOEN_W::new(self) + pub fn gpo34_doen(&mut self) -> GPO34_DOEN_W { + GPO34_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO35. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo35_doen(&mut self) -> GPO35_DOEN_W { - GPO35_DOEN_W::new(self) + pub fn gpo35_doen(&mut self) -> GPO35_DOEN_W { + GPO35_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen9.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen9.rs index 79e1f7c..bdf06c9 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen9.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_doen9.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo36_doen` reader - The selected OEN signal for GPIO36. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO36_DOEN_R = crate::FieldReader; #[doc = "Field `gpo36_doen` writer - The selected OEN signal for GPIO36. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO36_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO36_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo37_doen` reader - The selected OEN signal for GPIO37. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO37_DOEN_R = crate::FieldReader; #[doc = "Field `gpo37_doen` writer - The selected OEN signal for GPIO37. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO37_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO37_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo38_doen` reader - The selected OEN signal for GPIO38. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO38_DOEN_R = crate::FieldReader; #[doc = "Field `gpo38_doen` writer - The selected OEN signal for GPIO38. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO38_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO38_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `gpo39_doen` reader - The selected OEN signal for GPIO39. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO39_DOEN_R = crate::FieldReader; #[doc = "Field `gpo39_doen` writer - The selected OEN signal for GPIO39. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO39_DOEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type GPO39_DOEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:5 - The selected OEN signal for GPIO36. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:5 - The selected OEN signal for GPIO36. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo36_doen(&mut self) -> GPO36_DOEN_W { - GPO36_DOEN_W::new(self) + pub fn gpo36_doen(&mut self) -> GPO36_DOEN_W { + GPO36_DOEN_W::new(self, 0) } #[doc = "Bits 8:13 - The selected OEN signal for GPIO37. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo37_doen(&mut self) -> GPO37_DOEN_W { - GPO37_DOEN_W::new(self) + pub fn gpo37_doen(&mut self) -> GPO37_DOEN_W { + GPO37_DOEN_W::new(self, 8) } #[doc = "Bits 16:21 - The selected OEN signal for GPIO38. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo38_doen(&mut self) -> GPO38_DOEN_W { - GPO38_DOEN_W::new(self) + pub fn gpo38_doen(&mut self) -> GPO38_DOEN_W { + GPO38_DOEN_W::new(self, 16) } #[doc = "Bits 24:29 - The selected OEN signal for GPIO39. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo39_doen(&mut self) -> GPO39_DOEN_W { - GPO39_DOEN_W::new(self) + pub fn gpo39_doen(&mut self) -> GPO39_DOEN_W { + GPO39_DOEN_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout0_3.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout0_3.rs index c2c0374..d5e6dcc 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout0_3.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout0_3.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo0_dout` reader - The selected output signal for GPIO0. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO0_DOUT_R = crate::FieldReader; #[doc = "Field `gpo0_dout` writer - The selected output signal for GPIO0. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO0_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO0_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo1_dout` reader - The selected output signal for GPIO1. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO1_DOUT_R = crate::FieldReader; #[doc = "Field `gpo1_dout` writer - The selected output signal for GPIO1. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO1_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO1_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo2_dout` reader - The selected output signal for GPIO2. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO2_DOUT_R = crate::FieldReader; #[doc = "Field `gpo2_dout` writer - The selected output signal for GPIO2. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO2_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO2_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo3_dout` reader - The selected output signal for GPIO3. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO3_DOUT_R = crate::FieldReader; #[doc = "Field `gpo3_dout` writer - The selected output signal for GPIO3. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO3_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO3_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO0. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO0. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo0_dout(&mut self) -> GPO0_DOUT_W { - GPO0_DOUT_W::new(self) + pub fn gpo0_dout(&mut self) -> GPO0_DOUT_W { + GPO0_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO1. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo1_dout(&mut self) -> GPO1_DOUT_W { - GPO1_DOUT_W::new(self) + pub fn gpo1_dout(&mut self) -> GPO1_DOUT_W { + GPO1_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO2. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo2_dout(&mut self) -> GPO2_DOUT_W { - GPO2_DOUT_W::new(self) + pub fn gpo2_dout(&mut self) -> GPO2_DOUT_W { + GPO2_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO3. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo3_dout(&mut self) -> GPO3_DOUT_W { - GPO3_DOUT_W::new(self) + pub fn gpo3_dout(&mut self) -> GPO3_DOUT_W { + GPO3_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout12_15.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout12_15.rs index 69aeb9d..14a34aa 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout12_15.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout12_15.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo12_dout` reader - The selected output signal for GPIO12. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO12_DOUT_R = crate::FieldReader; #[doc = "Field `gpo12_dout` writer - The selected output signal for GPIO12. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO12_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO12_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo13_dout` reader - The selected output signal for GPIO13. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO13_DOUT_R = crate::FieldReader; #[doc = "Field `gpo13_dout` writer - The selected output signal for GPIO13. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO13_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO13_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo14_dout` reader - The selected output signal for GPIO14. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO14_DOUT_R = crate::FieldReader; #[doc = "Field `gpo14_dout` writer - The selected output signal for GPIO14. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO14_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO14_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo15_dout` reader - The selected output signal for GPIO15. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO15_DOUT_R = crate::FieldReader; #[doc = "Field `gpo15_dout` writer - The selected output signal for GPIO15. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO15_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO15_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO12. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO12. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo12_dout(&mut self) -> GPO12_DOUT_W { - GPO12_DOUT_W::new(self) + pub fn gpo12_dout(&mut self) -> GPO12_DOUT_W { + GPO12_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO13. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo13_dout(&mut self) -> GPO13_DOUT_W { - GPO13_DOUT_W::new(self) + pub fn gpo13_dout(&mut self) -> GPO13_DOUT_W { + GPO13_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO14. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo14_dout(&mut self) -> GPO14_DOUT_W { - GPO14_DOUT_W::new(self) + pub fn gpo14_dout(&mut self) -> GPO14_DOUT_W { + GPO14_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO15. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo15_dout(&mut self) -> GPO15_DOUT_W { - GPO15_DOUT_W::new(self) + pub fn gpo15_dout(&mut self) -> GPO15_DOUT_W { + GPO15_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout16_19.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout16_19.rs index 135d213..f1ed52a 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout16_19.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout16_19.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo16_dout` reader - The selected output signal for GPIO16. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO16_DOUT_R = crate::FieldReader; #[doc = "Field `gpo16_dout` writer - The selected output signal for GPIO16. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO16_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO16_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo17_dout` reader - The selected output signal for GPIO17. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO17_DOUT_R = crate::FieldReader; #[doc = "Field `gpo17_dout` writer - The selected output signal for GPIO17. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO17_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO17_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo18_dout` reader - The selected output signal for GPIO18. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO18_DOUT_R = crate::FieldReader; #[doc = "Field `gpo18_dout` writer - The selected output signal for GPIO18. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO18_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO18_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo19_dout` reader - The selected output signal for GPIO19. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO19_DOUT_R = crate::FieldReader; #[doc = "Field `gpo19_dout` writer - The selected output signal for GPIO19. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO19_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO19_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO16. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO16. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo16_dout(&mut self) -> GPO16_DOUT_W { - GPO16_DOUT_W::new(self) + pub fn gpo16_dout(&mut self) -> GPO16_DOUT_W { + GPO16_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO17. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo17_dout(&mut self) -> GPO17_DOUT_W { - GPO17_DOUT_W::new(self) + pub fn gpo17_dout(&mut self) -> GPO17_DOUT_W { + GPO17_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO18. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo18_dout(&mut self) -> GPO18_DOUT_W { - GPO18_DOUT_W::new(self) + pub fn gpo18_dout(&mut self) -> GPO18_DOUT_W { + GPO18_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO19. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo19_dout(&mut self) -> GPO19_DOUT_W { - GPO19_DOUT_W::new(self) + pub fn gpo19_dout(&mut self) -> GPO19_DOUT_W { + GPO19_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout20_23.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout20_23.rs index f25d49f..934ce6d 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout20_23.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout20_23.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo20_dout` reader - The selected output signal for GPIO20. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO20_DOUT_R = crate::FieldReader; #[doc = "Field `gpo20_dout` writer - The selected output signal for GPIO20. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO20_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO20_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo21_dout` reader - The selected output signal for GPIO21. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO21_DOUT_R = crate::FieldReader; #[doc = "Field `gpo21_dout` writer - The selected output signal for GPIO21. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO21_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO21_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo22_dout` reader - The selected output signal for GPIO22. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO22_DOUT_R = crate::FieldReader; #[doc = "Field `gpo22_dout` writer - The selected output signal for GPIO22. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO22_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO22_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo23_dout` reader - The selected output signal for GPIO23. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO23_DOUT_R = crate::FieldReader; #[doc = "Field `gpo23_dout` writer - The selected output signal for GPIO23. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO23_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO23_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO20. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO20. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo20_dout(&mut self) -> GPO20_DOUT_W { - GPO20_DOUT_W::new(self) + pub fn gpo20_dout(&mut self) -> GPO20_DOUT_W { + GPO20_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO21. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo21_dout(&mut self) -> GPO21_DOUT_W { - GPO21_DOUT_W::new(self) + pub fn gpo21_dout(&mut self) -> GPO21_DOUT_W { + GPO21_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO22. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo22_dout(&mut self) -> GPO22_DOUT_W { - GPO22_DOUT_W::new(self) + pub fn gpo22_dout(&mut self) -> GPO22_DOUT_W { + GPO22_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO23. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo23_dout(&mut self) -> GPO23_DOUT_W { - GPO23_DOUT_W::new(self) + pub fn gpo23_dout(&mut self) -> GPO23_DOUT_W { + GPO23_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout24_27.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout24_27.rs index 53f5b77..c726dc4 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout24_27.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout24_27.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo24_dout` reader - The selected output signal for GPIO24. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO24_DOUT_R = crate::FieldReader; #[doc = "Field `gpo24_dout` writer - The selected output signal for GPIO24. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO24_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO24_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo25_dout` reader - The selected output signal for GPIO25. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO25_DOUT_R = crate::FieldReader; #[doc = "Field `gpo25_dout` writer - The selected output signal for GPIO25. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO25_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO25_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo26_dout` reader - The selected output signal for GPIO26. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO26_DOUT_R = crate::FieldReader; #[doc = "Field `gpo26_dout` writer - The selected output signal for GPIO26. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO26_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO26_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo27_dout` reader - The selected output signal for GPIO27. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO27_DOUT_R = crate::FieldReader; #[doc = "Field `gpo27_dout` writer - The selected output signal for GPIO27. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO27_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO27_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO24. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO24. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo24_dout(&mut self) -> GPO24_DOUT_W { - GPO24_DOUT_W::new(self) + pub fn gpo24_dout(&mut self) -> GPO24_DOUT_W { + GPO24_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO25. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo25_dout(&mut self) -> GPO25_DOUT_W { - GPO25_DOUT_W::new(self) + pub fn gpo25_dout(&mut self) -> GPO25_DOUT_W { + GPO25_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO26. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo26_dout(&mut self) -> GPO26_DOUT_W { - GPO26_DOUT_W::new(self) + pub fn gpo26_dout(&mut self) -> GPO26_DOUT_W { + GPO26_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO27. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo27_dout(&mut self) -> GPO27_DOUT_W { - GPO27_DOUT_W::new(self) + pub fn gpo27_dout(&mut self) -> GPO27_DOUT_W { + GPO27_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout28_31.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout28_31.rs index 9a9ce42..a7602a2 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout28_31.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout28_31.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo28_dout` reader - The selected output signal for GPIO28. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO28_DOUT_R = crate::FieldReader; #[doc = "Field `gpo28_dout` writer - The selected output signal for GPIO28. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO28_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO28_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo29_dout` reader - The selected output signal for GPIO29. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO29_DOUT_R = crate::FieldReader; #[doc = "Field `gpo29_dout` writer - The selected output signal for GPIO29. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO29_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO29_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo30_dout` reader - The selected output signal for GPIO30. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO30_DOUT_R = crate::FieldReader; #[doc = "Field `gpo30_dout` writer - The selected output signal for GPIO30. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO30_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO30_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo31_dout` reader - The selected output signal for GPIO31. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO31_DOUT_R = crate::FieldReader; #[doc = "Field `gpo31_dout` writer - The selected output signal for GPIO31. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO31_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO31_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO28. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO28. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo28_dout(&mut self) -> GPO28_DOUT_W { - GPO28_DOUT_W::new(self) + pub fn gpo28_dout(&mut self) -> GPO28_DOUT_W { + GPO28_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO29. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo29_dout(&mut self) -> GPO29_DOUT_W { - GPO29_DOUT_W::new(self) + pub fn gpo29_dout(&mut self) -> GPO29_DOUT_W { + GPO29_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO30. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo30_dout(&mut self) -> GPO30_DOUT_W { - GPO30_DOUT_W::new(self) + pub fn gpo30_dout(&mut self) -> GPO30_DOUT_W { + GPO30_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO31. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo31_dout(&mut self) -> GPO31_DOUT_W { - GPO31_DOUT_W::new(self) + pub fn gpo31_dout(&mut self) -> GPO31_DOUT_W { + GPO31_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout32_35.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout32_35.rs index 9394568..fc44c0c 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout32_35.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout32_35.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo32_dout` reader - The selected output signal for GPIO32. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO32_DOUT_R = crate::FieldReader; #[doc = "Field `gpo32_dout` writer - The selected output signal for GPIO32. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO32_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO32_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo33_dout` reader - The selected output signal for GPIO33. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO33_DOUT_R = crate::FieldReader; #[doc = "Field `gpo33_dout` writer - The selected output signal for GPIO33. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO33_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO33_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo34_dout` reader - The selected output signal for GPIO34. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO34_DOUT_R = crate::FieldReader; #[doc = "Field `gpo34_dout` writer - The selected output signal for GPIO34. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO34_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO34_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo35_dout` reader - The selected output signal for GPIO35. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO35_DOUT_R = crate::FieldReader; #[doc = "Field `gpo35_dout` writer - The selected output signal for GPIO35. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO35_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO35_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO32. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO32. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo32_dout(&mut self) -> GPO32_DOUT_W { - GPO32_DOUT_W::new(self) + pub fn gpo32_dout(&mut self) -> GPO32_DOUT_W { + GPO32_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO33. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo33_dout(&mut self) -> GPO33_DOUT_W { - GPO33_DOUT_W::new(self) + pub fn gpo33_dout(&mut self) -> GPO33_DOUT_W { + GPO33_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO34. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo34_dout(&mut self) -> GPO34_DOUT_W { - GPO34_DOUT_W::new(self) + pub fn gpo34_dout(&mut self) -> GPO34_DOUT_W { + GPO34_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO35. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo35_dout(&mut self) -> GPO35_DOUT_W { - GPO35_DOUT_W::new(self) + pub fn gpo35_dout(&mut self) -> GPO35_DOUT_W { + GPO35_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout36_39.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout36_39.rs index 3559b5b..2680766 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout36_39.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout36_39.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo36_dout` reader - The selected output signal for GPIO36. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO36_DOUT_R = crate::FieldReader; #[doc = "Field `gpo36_dout` writer - The selected output signal for GPIO36. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO36_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO36_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo37_dout` reader - The selected output signal for GPIO37. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO37_DOUT_R = crate::FieldReader; #[doc = "Field `gpo37_dout` writer - The selected output signal for GPIO37. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO37_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO37_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo38_dout` reader - The selected output signal for GPIO38. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO38_DOUT_R = crate::FieldReader; #[doc = "Field `gpo38_dout` writer - The selected output signal for GPIO38. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO38_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO38_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo39_dout` reader - The selected output signal for GPIO39. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO39_DOUT_R = crate::FieldReader; #[doc = "Field `gpo39_dout` writer - The selected output signal for GPIO39. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO39_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO39_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO36. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO36. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo36_dout(&mut self) -> GPO36_DOUT_W { - GPO36_DOUT_W::new(self) + pub fn gpo36_dout(&mut self) -> GPO36_DOUT_W { + GPO36_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO37. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo37_dout(&mut self) -> GPO37_DOUT_W { - GPO37_DOUT_W::new(self) + pub fn gpo37_dout(&mut self) -> GPO37_DOUT_W { + GPO37_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO38. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo38_dout(&mut self) -> GPO38_DOUT_W { - GPO38_DOUT_W::new(self) + pub fn gpo38_dout(&mut self) -> GPO38_DOUT_W { + GPO38_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO39. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo39_dout(&mut self) -> GPO39_DOUT_W { - GPO39_DOUT_W::new(self) + pub fn gpo39_dout(&mut self) -> GPO39_DOUT_W { + GPO39_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout40_43.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout40_43.rs index 1327fa5..319a8f3 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout40_43.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout40_43.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo40_dout` reader - The selected output signal for GPIO40. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO40_DOUT_R = crate::FieldReader; #[doc = "Field `gpo40_dout` writer - The selected output signal for GPIO40. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO40_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO40_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo41_dout` reader - The selected output signal for GPIO41. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO41_DOUT_R = crate::FieldReader; #[doc = "Field `gpo41_dout` writer - The selected output signal for GPIO41. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO41_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO41_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo42_dout` reader - The selected output signal for GPIO42. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO42_DOUT_R = crate::FieldReader; #[doc = "Field `gpo42_dout` writer - The selected output signal for GPIO42. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO42_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO42_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo43_dout` reader - The selected output signal for GPIO43. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO43_DOUT_R = crate::FieldReader; #[doc = "Field `gpo43_dout` writer - The selected output signal for GPIO43. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO43_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO43_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO40. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO40. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo40_dout(&mut self) -> GPO40_DOUT_W { - GPO40_DOUT_W::new(self) + pub fn gpo40_dout(&mut self) -> GPO40_DOUT_W { + GPO40_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO41. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo41_dout(&mut self) -> GPO41_DOUT_W { - GPO41_DOUT_W::new(self) + pub fn gpo41_dout(&mut self) -> GPO41_DOUT_W { + GPO41_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO42. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo42_dout(&mut self) -> GPO42_DOUT_W { - GPO42_DOUT_W::new(self) + pub fn gpo42_dout(&mut self) -> GPO42_DOUT_W { + GPO42_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO43. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo43_dout(&mut self) -> GPO43_DOUT_W { - GPO43_DOUT_W::new(self) + pub fn gpo43_dout(&mut self) -> GPO43_DOUT_W { + GPO43_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout44_47.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout44_47.rs index 1c11381..c1e605b 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout44_47.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout44_47.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo44_dout` reader - The selected output signal for GPIO44. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO44_DOUT_R = crate::FieldReader; #[doc = "Field `gpo44_dout` writer - The selected output signal for GPIO44. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO44_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO44_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo45_dout` reader - The selected output signal for GPIO45. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO45_DOUT_R = crate::FieldReader; #[doc = "Field `gpo45_dout` writer - The selected output signal for GPIO45. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO45_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO45_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo46_dout` reader - The selected output signal for GPIO46. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO46_DOUT_R = crate::FieldReader; #[doc = "Field `gpo46_dout` writer - The selected output signal for GPIO46. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO46_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO46_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo47_dout` reader - The selected output signal for GPIO47. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO47_DOUT_R = crate::FieldReader; #[doc = "Field `gpo47_dout` writer - The selected output signal for GPIO47. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO47_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO47_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO44. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO44. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo44_dout(&mut self) -> GPO44_DOUT_W { - GPO44_DOUT_W::new(self) + pub fn gpo44_dout(&mut self) -> GPO44_DOUT_W { + GPO44_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO45. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo45_dout(&mut self) -> GPO45_DOUT_W { - GPO45_DOUT_W::new(self) + pub fn gpo45_dout(&mut self) -> GPO45_DOUT_W { + GPO45_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO46. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo46_dout(&mut self) -> GPO46_DOUT_W { - GPO46_DOUT_W::new(self) + pub fn gpo46_dout(&mut self) -> GPO46_DOUT_W { + GPO46_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO47. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo47_dout(&mut self) -> GPO47_DOUT_W { - GPO47_DOUT_W::new(self) + pub fn gpo47_dout(&mut self) -> GPO47_DOUT_W { + GPO47_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout48_51.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout48_51.rs index 4bfcc12..968917b 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout48_51.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout48_51.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo48_dout` reader - The selected output signal for GPIO48. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO48_DOUT_R = crate::FieldReader; #[doc = "Field `gpo48_dout` writer - The selected output signal for GPIO48. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO48_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO48_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo49_dout` reader - The selected output signal for GPIO49. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO49_DOUT_R = crate::FieldReader; #[doc = "Field `gpo49_dout` writer - The selected output signal for GPIO49. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO49_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO49_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo50_dout` reader - The selected output signal for GPIO50. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO50_DOUT_R = crate::FieldReader; #[doc = "Field `gpo50_dout` writer - The selected output signal for GPIO50. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO50_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO50_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo51_dout` reader - The selected output signal for GPIO51. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO51_DOUT_R = crate::FieldReader; #[doc = "Field `gpo51_dout` writer - The selected output signal for GPIO51. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO51_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO51_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO48. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO48. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo48_dout(&mut self) -> GPO48_DOUT_W { - GPO48_DOUT_W::new(self) + pub fn gpo48_dout(&mut self) -> GPO48_DOUT_W { + GPO48_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO49. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo49_dout(&mut self) -> GPO49_DOUT_W { - GPO49_DOUT_W::new(self) + pub fn gpo49_dout(&mut self) -> GPO49_DOUT_W { + GPO49_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO50. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo50_dout(&mut self) -> GPO50_DOUT_W { - GPO50_DOUT_W::new(self) + pub fn gpo50_dout(&mut self) -> GPO50_DOUT_W { + GPO50_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO51. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo51_dout(&mut self) -> GPO51_DOUT_W { - GPO51_DOUT_W::new(self) + pub fn gpo51_dout(&mut self) -> GPO51_DOUT_W { + GPO51_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout4_7.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout4_7.rs index aa20f2c..4b551a6 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout4_7.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout4_7.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo4_dout` reader - The selected output signal for GPIO4. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO4_DOUT_R = crate::FieldReader; #[doc = "Field `gpo4_dout` writer - The selected output signal for GPIO4. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO4_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO4_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo5_dout` reader - The selected output signal for GPIO5. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO5_DOUT_R = crate::FieldReader; #[doc = "Field `gpo5_dout` writer - The selected output signal for GPIO5. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO5_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO5_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo6_dout` reader - The selected output signal for GPIO6. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO6_DOUT_R = crate::FieldReader; #[doc = "Field `gpo6_dout` writer - The selected output signal for GPIO6. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO6_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO6_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo7_dout` reader - The selected output signal for GPIO7. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO7_DOUT_R = crate::FieldReader; #[doc = "Field `gpo7_dout` writer - The selected output signal for GPIO7. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO7_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO7_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO4. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO4. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo4_dout(&mut self) -> GPO4_DOUT_W { - GPO4_DOUT_W::new(self) + pub fn gpo4_dout(&mut self) -> GPO4_DOUT_W { + GPO4_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO5. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo5_dout(&mut self) -> GPO5_DOUT_W { - GPO5_DOUT_W::new(self) + pub fn gpo5_dout(&mut self) -> GPO5_DOUT_W { + GPO5_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO6. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo6_dout(&mut self) -> GPO6_DOUT_W { - GPO6_DOUT_W::new(self) + pub fn gpo6_dout(&mut self) -> GPO6_DOUT_W { + GPO6_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO7. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo7_dout(&mut self) -> GPO7_DOUT_W { - GPO7_DOUT_W::new(self) + pub fn gpo7_dout(&mut self) -> GPO7_DOUT_W { + GPO7_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout52_55.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout52_55.rs index 82a7b94..7c19921 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout52_55.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout52_55.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo52_dout` reader - The selected output signal for GPIO52. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO52_DOUT_R = crate::FieldReader; #[doc = "Field `gpo52_dout` writer - The selected output signal for GPIO52. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO52_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO52_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo53_dout` reader - The selected output signal for GPIO53. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO53_DOUT_R = crate::FieldReader; #[doc = "Field `gpo53_dout` writer - The selected output signal for GPIO53. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO53_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO53_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo54_dout` reader - The selected output signal for GPIO54. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO54_DOUT_R = crate::FieldReader; #[doc = "Field `gpo54_dout` writer - The selected output signal for GPIO54. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO54_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO54_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo55_dout` reader - The selected output signal for GPIO55. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO55_DOUT_R = crate::FieldReader; #[doc = "Field `gpo55_dout` writer - The selected output signal for GPIO55. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO55_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO55_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO52. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO52. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo52_dout(&mut self) -> GPO52_DOUT_W { - GPO52_DOUT_W::new(self) + pub fn gpo52_dout(&mut self) -> GPO52_DOUT_W { + GPO52_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO53. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo53_dout(&mut self) -> GPO53_DOUT_W { - GPO53_DOUT_W::new(self) + pub fn gpo53_dout(&mut self) -> GPO53_DOUT_W { + GPO53_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO54. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo54_dout(&mut self) -> GPO54_DOUT_W { - GPO54_DOUT_W::new(self) + pub fn gpo54_dout(&mut self) -> GPO54_DOUT_W { + GPO54_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO55. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo55_dout(&mut self) -> GPO55_DOUT_W { - GPO55_DOUT_W::new(self) + pub fn gpo55_dout(&mut self) -> GPO55_DOUT_W { + GPO55_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout56_59.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout56_59.rs index 3d26174..c5f9a92 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout56_59.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout56_59.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo56_dout` reader - The selected output signal for GPIO56. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO56_DOUT_R = crate::FieldReader; #[doc = "Field `gpo56_dout` writer - The selected output signal for GPIO56. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO56_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO56_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo57_dout` reader - The selected output signal for GPIO57. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO57_DOUT_R = crate::FieldReader; #[doc = "Field `gpo57_dout` writer - The selected output signal for GPIO57. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO57_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO57_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo58_dout` reader - The selected output signal for GPIO58. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO58_DOUT_R = crate::FieldReader; #[doc = "Field `gpo58_dout` writer - The selected output signal for GPIO58. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO58_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO58_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo59_dout` reader - The selected output signal for GPIO59. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO59_DOUT_R = crate::FieldReader; #[doc = "Field `gpo59_dout` writer - The selected output signal for GPIO59. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO59_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO59_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO56. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO56. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo56_dout(&mut self) -> GPO56_DOUT_W { - GPO56_DOUT_W::new(self) + pub fn gpo56_dout(&mut self) -> GPO56_DOUT_W { + GPO56_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO57. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo57_dout(&mut self) -> GPO57_DOUT_W { - GPO57_DOUT_W::new(self) + pub fn gpo57_dout(&mut self) -> GPO57_DOUT_W { + GPO57_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO58. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo58_dout(&mut self) -> GPO58_DOUT_W { - GPO58_DOUT_W::new(self) + pub fn gpo58_dout(&mut self) -> GPO58_DOUT_W { + GPO58_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO59. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo59_dout(&mut self) -> GPO59_DOUT_W { - GPO59_DOUT_W::new(self) + pub fn gpo59_dout(&mut self) -> GPO59_DOUT_W { + GPO59_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout60_63.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout60_63.rs index a194de2..ceccb90 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout60_63.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout60_63.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo60_dout` reader - The selected output signal for GPIO60. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO60_DOUT_R = crate::FieldReader; #[doc = "Field `gpo60_dout` writer - The selected output signal for GPIO60. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO60_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO60_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo61_dout` reader - The selected output signal for GPIO61. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO61_DOUT_R = crate::FieldReader; #[doc = "Field `gpo61_dout` writer - The selected output signal for GPIO61. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO61_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO61_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo62_dout` reader - The selected output signal for GPIO62. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO62_DOUT_R = crate::FieldReader; #[doc = "Field `gpo62_dout` writer - The selected output signal for GPIO62. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO62_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO62_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo63_dout` reader - The selected output signal for GPIO63. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO63_DOUT_R = crate::FieldReader; #[doc = "Field `gpo63_dout` writer - The selected output signal for GPIO63. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO63_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO63_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO60. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO60. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo60_dout(&mut self) -> GPO60_DOUT_W { - GPO60_DOUT_W::new(self) + pub fn gpo60_dout(&mut self) -> GPO60_DOUT_W { + GPO60_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO61. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo61_dout(&mut self) -> GPO61_DOUT_W { - GPO61_DOUT_W::new(self) + pub fn gpo61_dout(&mut self) -> GPO61_DOUT_W { + GPO61_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO62. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo62_dout(&mut self) -> GPO62_DOUT_W { - GPO62_DOUT_W::new(self) + pub fn gpo62_dout(&mut self) -> GPO62_DOUT_W { + GPO62_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO63. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo63_dout(&mut self) -> GPO63_DOUT_W { - GPO63_DOUT_W::new(self) + pub fn gpo63_dout(&mut self) -> GPO63_DOUT_W { + GPO63_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout8_11.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout8_11.rs index 88c763e..c03d2cb 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout8_11.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/gpo_dout8_11.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `gpo8_dout` reader - The selected output signal for GPIO8. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO8_DOUT_R = crate::FieldReader; #[doc = "Field `gpo8_dout` writer - The selected output signal for GPIO8. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO8_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO8_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo9_dout` reader - The selected output signal for GPIO9. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO9_DOUT_R = crate::FieldReader; #[doc = "Field `gpo9_dout` writer - The selected output signal for GPIO9. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO9_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO9_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo10_dout` reader - The selected output signal for GPIO10. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO10_DOUT_R = crate::FieldReader; #[doc = "Field `gpo10_dout` writer - The selected output signal for GPIO10. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO10_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO10_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; #[doc = "Field `gpo11_dout` reader - The selected output signal for GPIO11. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] pub type GPO11_DOUT_R = crate::FieldReader; #[doc = "Field `gpo11_dout` writer - The selected output signal for GPIO11. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] -pub type GPO11_DOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; +pub type GPO11_DOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; impl R { #[doc = "Bits 0:6 - The selected output signal for GPIO8. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bits 0:6 - The selected output signal for GPIO8. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo8_dout(&mut self) -> GPO8_DOUT_W { - GPO8_DOUT_W::new(self) + pub fn gpo8_dout(&mut self) -> GPO8_DOUT_W { + GPO8_DOUT_W::new(self, 0) } #[doc = "Bits 8:14 - The selected output signal for GPIO9. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo9_dout(&mut self) -> GPO9_DOUT_W { - GPO9_DOUT_W::new(self) + pub fn gpo9_dout(&mut self) -> GPO9_DOUT_W { + GPO9_DOUT_W::new(self, 8) } #[doc = "Bits 16:22 - The selected output signal for GPIO10. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo10_dout(&mut self) -> GPO10_DOUT_W { - GPO10_DOUT_W::new(self) + pub fn gpo10_dout(&mut self) -> GPO10_DOUT_W { + GPO10_DOUT_W::new(self, 16) } #[doc = "Bits 24:30 - The selected output signal for GPIO11. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information."] #[inline(always)] #[must_use] - pub fn gpo11_dout(&mut self) -> GPO11_DOUT_W { - GPO11_DOUT_W::new(self) + pub fn gpo11_dout(&mut self) -> GPO11_DOUT_W { + GPO11_DOUT_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq0.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq0.rs index 5dabb1a..9c32a14 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq0.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioen0` reader - 1: Enable, 0: Disable"] pub type GPIOEN0_R = crate::BitReader; #[doc = "Field `gpioen0` writer - 1: Enable, 0: Disable"] -pub type GPIOEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GPIOEN0_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Enable, 0: Disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - 1: Enable, 0: Disable"] #[inline(always)] #[must_use] - pub fn gpioen0(&mut self) -> GPIOEN0_W { - GPIOEN0_W::new(self) + pub fn gpioen0(&mut self) -> GPIOEN0_W { + GPIOEN0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq1.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq1.rs index c4125fc..21e7c76 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq1.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq1.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpiois0` reader - 1: Edge trigger, 0: Level trigger"] pub type GPIOIS0_R = crate::FieldReader; #[doc = "Field `gpiois0` writer - 1: Edge trigger, 0: Level trigger"] -pub type GPIOIS0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIS0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Edge trigger, 0: Level trigger"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Edge trigger, 0: Level trigger"] #[inline(always)] #[must_use] - pub fn gpiois0(&mut self) -> GPIOIS0_W { - GPIOIS0_W::new(self) + pub fn gpiois0(&mut self) -> GPIOIS0_W { + GPIOIS0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq10.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq10.rs index 6d92d98..f7d0b50 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq10.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq10.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioie1` reader - 1: Unmask, 0: Mask"] pub type GPIOIE1_R = crate::FieldReader; #[doc = "Field `gpioie1` writer - 1: Unmask, 0: Mask"] -pub type GPIOIE1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIE1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Unmask, 0: Mask"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Unmask, 0: Mask"] #[inline(always)] #[must_use] - pub fn gpioie1(&mut self) -> GPIOIE1_W { - GPIOIE1_W::new(self) + pub fn gpioie1(&mut self) -> GPIOIE1_W { + GPIOIE1_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq11.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq11.rs index a803bb2..630d5ce 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq11.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq11.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq12.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq12.rs index aff6604..573a724 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq12.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq12.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq13.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq13.rs index 15ae39d..54fd284 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq13.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq13.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq14.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq14.rs index e7a78ea..282a5d5 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq14.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq14.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq15.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq15.rs index fa51ba0..37a81b6 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq15.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq15.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq16.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq16.rs index 96972ea..8702079 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq16.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq16.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq2.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq2.rs index ae2e69c..f9c0d5b 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq2.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq2.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpiois1` reader - 1: Edge trigger, 0: Level trigger"] pub type GPIOIS1_R = crate::FieldReader; #[doc = "Field `gpiois1` writer - 1: Edge trigger, 0: Level trigger"] -pub type GPIOIS1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIS1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Edge trigger, 0: Level trigger"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Edge trigger, 0: Level trigger"] #[inline(always)] #[must_use] - pub fn gpiois1(&mut self) -> GPIOIS1_W { - GPIOIS1_W::new(self) + pub fn gpiois1(&mut self) -> GPIOIS1_W { + GPIOIS1_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq3.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq3.rs index 0570e0f..66b771c 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq3.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq3.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioic0` reader - 1: Do not clear the register, 0: Clear the register"] pub type GPIOIC0_R = crate::FieldReader; #[doc = "Field `gpioic0` writer - 1: Do not clear the register, 0: Clear the register"] -pub type GPIOIC0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIC0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Do not clear the register, 0: Clear the register"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Do not clear the register, 0: Clear the register"] #[inline(always)] #[must_use] - pub fn gpioic0(&mut self) -> GPIOIC0_W { - GPIOIC0_W::new(self) + pub fn gpioic0(&mut self) -> GPIOIC0_W { + GPIOIC0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq4.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq4.rs index 117401a..3c70b23 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq4.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq4.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioic1` reader - 1: Do not clear the register, 0: Clear the register"] pub type GPIOIC1_R = crate::FieldReader; #[doc = "Field `gpioic1` writer - 1: Do not clear the register, 0: Clear the register"] -pub type GPIOIC1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIC1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Do not clear the register, 0: Clear the register"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Do not clear the register, 0: Clear the register"] #[inline(always)] #[must_use] - pub fn gpioic1(&mut self) -> GPIOIC1_W { - GPIOIC1_W::new(self) + pub fn gpioic1(&mut self) -> GPIOIC1_W { + GPIOIC1_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq5.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq5.rs index 2c4f469..c84f6be 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq5.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq5.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioibe0` reader - 1: Trigger on both edges, 0: Trigger on a single edge"] pub type GPIOIBE0_R = crate::FieldReader; #[doc = "Field `gpioibe0` writer - 1: Trigger on both edges, 0: Trigger on a single edge"] -pub type GPIOIBE0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIBE0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Trigger on both edges, 0: Trigger on a single edge"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Trigger on both edges, 0: Trigger on a single edge"] #[inline(always)] #[must_use] - pub fn gpioibe0(&mut self) -> GPIOIBE0_W { - GPIOIBE0_W::new(self) + pub fn gpioibe0(&mut self) -> GPIOIBE0_W { + GPIOIBE0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq6.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq6.rs index 35cdfc0..e819d84 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq6.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq6.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioibe1` reader - 1: Trigger on both edges, 0: Trigger on a single edge"] pub type GPIOIBE1_R = crate::FieldReader; #[doc = "Field `gpioibe1` writer - 1: Trigger on both edges, 0: Trigger on a single edge"] -pub type GPIOIBE1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIBE1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Trigger on both edges, 0: Trigger on a single edge"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Trigger on both edges, 0: Trigger on a single edge"] #[inline(always)] #[must_use] - pub fn gpioibe1(&mut self) -> GPIOIBE1_W { - GPIOIBE1_W::new(self) + pub fn gpioibe1(&mut self) -> GPIOIBE1_W { + GPIOIBE1_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq7.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq7.rs index d20e458..1457ca7 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq7.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq7.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioiev0` reader - 1: Positive/Low, 0: Negative/High"] pub type GPIOIEV0_R = crate::FieldReader; #[doc = "Field `gpioiev0` writer - 1: Positive/Low, 0: Negative/High"] -pub type GPIOIEV0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIEV0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Positive/Low, 0: Negative/High"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Positive/Low, 0: Negative/High"] #[inline(always)] #[must_use] - pub fn gpioiev0(&mut self) -> GPIOIEV0_W { - GPIOIEV0_W::new(self) + pub fn gpioiev0(&mut self) -> GPIOIEV0_W { + GPIOIEV0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq8.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq8.rs index 74f6862..d9affb5 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq8.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq8.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioiev1` reader - 1: Positive/Low, 0: Negative/High"] pub type GPIOIEV1_R = crate::FieldReader; #[doc = "Field `gpioiev1` writer - 1: Positive/Low, 0: Negative/High"] -pub type GPIOIEV1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIEV1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Positive/Low, 0: Negative/High"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Positive/Low, 0: Negative/High"] #[inline(always)] #[must_use] - pub fn gpioiev1(&mut self) -> GPIOIEV1_W { - GPIOIEV1_W::new(self) + pub fn gpioiev1(&mut self) -> GPIOIEV1_W { + GPIOIEV1_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq9.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq9.rs index 48825b8..0bd97f9 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq9.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/ioirq9.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `gpioie0` reader - 1: Unmask, 0: Mask"] pub type GPIOIE0_R = crate::FieldReader; #[doc = "Field `gpioie0` writer - 1: Unmask, 0: Mask"] -pub type GPIOIE0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type GPIOIE0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - 1: Unmask, 0: Mask"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - 1: Unmask, 0: Mask"] #[inline(always)] #[must_use] - pub fn gpioie0(&mut self) -> GPIOIE0_W { - GPIOIE0_W::new(self) + pub fn gpioie0(&mut self) -> GPIOIE0_W { + GPIOIE0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_mdc_syscon.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_mdc_syscon.rs index 3a9dede..a7811d1 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_mdc_syscon.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_mdc_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_mdc_syscon` reader - padcfg_pad_gmac1_mdc_syscon"] pub type PADCFG_PAD_GMAC1_MDC_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_mdc_syscon` writer - padcfg_pad_gmac1_mdc_syscon"] -pub type PADCFG_PAD_GMAC1_MDC_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_MDC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_mdc_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_mdc_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_MDC_SYSCON_W { - PADCFG_PAD_GMAC1_MDC_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_MDC_SYSCON_W { + PADCFG_PAD_GMAC1_MDC_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_mdio_syscon.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_mdio_syscon.rs index eb9b718..4af4342 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_mdio_syscon.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_mdio_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_mdio_syscon` reader - padcfg_pad_gmac1_mdio_syscon"] pub type PADCFG_PAD_GMAC1_MDIO_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_mdio_syscon` writer - padcfg_pad_gmac1_mdio_syscon"] -pub type PADCFG_PAD_GMAC1_MDIO_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_MDIO_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_mdio_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_mdio_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_MDIO_SYSCON_W { - PADCFG_PAD_GMAC1_MDIO_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_MDIO_SYSCON_W { + PADCFG_PAD_GMAC1_MDIO_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxc_syscon.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxc_syscon.rs index 0017a23..83d7c93 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxc_syscon.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxc_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_rxc_syscon` reader - padcfg_pad_gmac1_rxc_syscon"] pub type PADCFG_PAD_GMAC1_RXC_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_rxc_syscon` writer - padcfg_pad_gmac1_rxc_syscon"] -pub type PADCFG_PAD_GMAC1_RXC_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_RXC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_rxc_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_rxc_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_RXC_SYSCON_W { - PADCFG_PAD_GMAC1_RXC_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_RXC_SYSCON_W { + PADCFG_PAD_GMAC1_RXC_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxd0_syscon.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxd0_syscon.rs index abe22a6..f614bf5 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxd0_syscon.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxd0_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_rxd0_syscon` reader - padcfg_pad_gmac1_rxd0_syscon"] pub type PADCFG_PAD_GMAC1_RXD0_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_rxd0_syscon` writer - padcfg_pad_gmac1_rxd0_syscon"] -pub type PADCFG_PAD_GMAC1_RXD0_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_RXD0_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_rxd0_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_rxd0_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_RXD0_SYSCON_W { - PADCFG_PAD_GMAC1_RXD0_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_RXD0_SYSCON_W { + PADCFG_PAD_GMAC1_RXD0_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxd1_syscon.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxd1_syscon.rs index 8d2ac5b..0075b2e 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxd1_syscon.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxd1_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_rxd1_syscon` reader - padcfg_pad_gmac1_rxd1_syscon"] pub type PADCFG_PAD_GMAC1_RXD1_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_rxd1_syscon` writer - padcfg_pad_gmac1_rxd1_syscon"] -pub type PADCFG_PAD_GMAC1_RXD1_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_RXD1_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_rxd1_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_rxd1_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_RXD1_SYSCON_W { - PADCFG_PAD_GMAC1_RXD1_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_RXD1_SYSCON_W { + PADCFG_PAD_GMAC1_RXD1_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxd2_syscon.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxd2_syscon.rs index 9459921..ff441db 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxd2_syscon.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxd2_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_rxd2_syscon` reader - padcfg_pad_gmac1_rxd2_syscon"] pub type PADCFG_PAD_GMAC1_RXD2_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_rxd2_syscon` writer - padcfg_pad_gmac1_rxd2_syscon"] -pub type PADCFG_PAD_GMAC1_RXD2_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_RXD2_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_rxd2_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_rxd2_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_RXD2_SYSCON_W { - PADCFG_PAD_GMAC1_RXD2_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_RXD2_SYSCON_W { + PADCFG_PAD_GMAC1_RXD2_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxd3_syscon.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxd3_syscon.rs index 8b282dc..a9c8c83 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxd3_syscon.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxd3_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_rxd3_syscon` reader - padcfg_pad_gmac1_rxd3_syscon"] pub type PADCFG_PAD_GMAC1_RXD3_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_rxd3_syscon` writer - padcfg_pad_gmac1_rxd3_syscon"] -pub type PADCFG_PAD_GMAC1_RXD3_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_RXD3_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_rxd3_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_rxd3_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_RXD3_SYSCON_W { - PADCFG_PAD_GMAC1_RXD3_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_RXD3_SYSCON_W { + PADCFG_PAD_GMAC1_RXD3_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxdv_syscon.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxdv_syscon.rs index 7fac45f..e963403 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxdv_syscon.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_rxdv_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_rxdv_syscon` reader - padcfg_pad_gmac1_rxdv_syscon"] pub type PADCFG_PAD_GMAC1_RXDV_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_rxdv_syscon` writer - padcfg_pad_gmac1_rxdv_syscon"] -pub type PADCFG_PAD_GMAC1_RXDV_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_RXDV_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_rxdv_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_rxdv_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_RXDV_SYSCON_W { - PADCFG_PAD_GMAC1_RXDV_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_RXDV_SYSCON_W { + PADCFG_PAD_GMAC1_RXDV_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txc_syscon.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txc_syscon.rs index d90bd72..8154358 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txc_syscon.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txc_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_txc_syscon` reader - padcfg_pad_gmac1_txc_syscon"] pub type PADCFG_PAD_GMAC1_TXC_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_txc_syscon` writer - padcfg_pad_gmac1_txc_syscon"] -pub type PADCFG_PAD_GMAC1_TXC_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_TXC_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_txc_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_txc_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_TXC_SYSCON_W { - PADCFG_PAD_GMAC1_TXC_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_TXC_SYSCON_W { + PADCFG_PAD_GMAC1_TXC_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txd0_syscon.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txd0_syscon.rs index 20f961f..0a1af38 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txd0_syscon.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txd0_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_txd0_syscon` reader - padcfg_pad_gmac1_txd0_syscon"] pub type PADCFG_PAD_GMAC1_TXD0_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_txd0_syscon` writer - padcfg_pad_gmac1_txd0_syscon"] -pub type PADCFG_PAD_GMAC1_TXD0_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_TXD0_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_txd0_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_txd0_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_TXD0_SYSCON_W { - PADCFG_PAD_GMAC1_TXD0_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_TXD0_SYSCON_W { + PADCFG_PAD_GMAC1_TXD0_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txd1_syscon.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txd1_syscon.rs index 74e37e5..b432eb5 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txd1_syscon.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txd1_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_txd1_syscon` reader - padcfg_pad_gmac1_txd1_syscon"] pub type PADCFG_PAD_GMAC1_TXD1_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_txd1_syscon` writer - padcfg_pad_gmac1_txd1_syscon"] -pub type PADCFG_PAD_GMAC1_TXD1_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_TXD1_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_txd1_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_txd1_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_TXD1_SYSCON_W { - PADCFG_PAD_GMAC1_TXD1_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_TXD1_SYSCON_W { + PADCFG_PAD_GMAC1_TXD1_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txd2_syscon.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txd2_syscon.rs index 945e0f8..346ec45 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txd2_syscon.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txd2_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_txd2_syscon` reader - padcfg_pad_gmac1_txd2_syscon"] pub type PADCFG_PAD_GMAC1_TXD2_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_txd2_syscon` writer - padcfg_pad_gmac1_txd2_syscon"] -pub type PADCFG_PAD_GMAC1_TXD2_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_TXD2_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_txd2_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_txd2_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_TXD2_SYSCON_W { - PADCFG_PAD_GMAC1_TXD2_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_TXD2_SYSCON_W { + PADCFG_PAD_GMAC1_TXD2_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txd3_syscon.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txd3_syscon.rs index f00aa6d..22946a5 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txd3_syscon.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txd3_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_txd3_syscon` reader - padcfg_pad_gmac1_txd3_syscon"] pub type PADCFG_PAD_GMAC1_TXD3_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_txd3_syscon` writer - padcfg_pad_gmac1_txd3_syscon"] -pub type PADCFG_PAD_GMAC1_TXD3_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_TXD3_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_txd3_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_txd3_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_TXD3_SYSCON_W { - PADCFG_PAD_GMAC1_TXD3_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_TXD3_SYSCON_W { + PADCFG_PAD_GMAC1_TXD3_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txen_syscon.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txen_syscon.rs index 2450d44..7855805 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txen_syscon.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gmac1_txen_syscon.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `padcfg_pad_gmac1_txen_syscon` reader - padcfg_pad_gmac1_txen_syscon"] pub type PADCFG_PAD_GMAC1_TXEN_SYSCON_R = crate::FieldReader; #[doc = "Field `padcfg_pad_gmac1_txen_syscon` writer - padcfg_pad_gmac1_txen_syscon"] -pub type PADCFG_PAD_GMAC1_TXEN_SYSCON_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type PADCFG_PAD_GMAC1_TXEN_SYSCON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - padcfg_pad_gmac1_txen_syscon"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn padcfg_pad_gmac1_txen_syscon( &mut self, - ) -> PADCFG_PAD_GMAC1_TXEN_SYSCON_W { - PADCFG_PAD_GMAC1_TXEN_SYSCON_W::new(self) + ) -> PADCFG_PAD_GMAC1_TXEN_SYSCON_W { + PADCFG_PAD_GMAC1_TXEN_SYSCON_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio0.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio0.rs index 96076c9..4fecea6 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio0.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio0.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio1.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio1.rs index 398124f..9dbb01e 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio1.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio1.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio10.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio10.rs index b4fe960..fada139 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio10.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio10.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio11.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio11.rs index f56fbe4..02676fe 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio11.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio11.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio12.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio12.rs index 530d06b..e70fcd3 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio12.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio12.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio13.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio13.rs index 264a66c..fb0c35a 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio13.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio13.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio14.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio14.rs index 95ba366..9b2e934 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio14.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio14.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio15.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio15.rs index 2e5014b..6b0bb17 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio15.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio15.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio16.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio16.rs index 917ae16..37b50b5 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio16.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio16.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio17.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio17.rs index 5c82ccc..6f52966 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio17.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio17.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio18.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio18.rs index 4856b14..ec88659 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio18.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio18.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio19.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio19.rs index 351dbde..3db4d43 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio19.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio19.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio2.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio2.rs index e0465f5..5e1dbd2 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio2.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio2.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio20.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio20.rs index cf5193c..ddd4039 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio20.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio20.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio21.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio21.rs index 417a861..45b58a6 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio21.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio21.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio22.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio22.rs index 3530238..cd81baa 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio22.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio22.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio23.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio23.rs index df9538b..6cd4d91 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio23.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio23.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio24.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio24.rs index 296d226..04893c0 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio24.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio24.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio25.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio25.rs index ade1493..52b9f8e 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio25.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio25.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio26.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio26.rs index 0f65f13..3d549bb 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio26.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio26.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio27.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio27.rs index 5fd7afb..a1f5441 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio27.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio27.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio28.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio28.rs index 18d687a..ec47f89 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio28.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio28.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio29.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio29.rs index 4dce15d..d4fbd43 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio29.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio29.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio3.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio3.rs index 0d6a2e2..d3504cc 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio3.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio3.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio30.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio30.rs index 0e192ff..903469d 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio30.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio30.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio31.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio31.rs index 4d9fce4..723cdae 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio31.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio31.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio32.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio32.rs index 2d304c0..6256178 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio32.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio32.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio33.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio33.rs index 7ba538f..15eb258 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio33.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio33.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio34.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio34.rs index cceb3ad..1d07aca 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio34.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio34.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio35.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio35.rs index 0d98ca3..e56e9c9 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio35.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio35.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio36.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio36.rs index 1802e23..222502f 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio36.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio36.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio37.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio37.rs index c674048..854f6bb 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio37.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio37.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio38.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio38.rs index 6259fac..01a3fa9 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio38.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio38.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio39.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio39.rs index 1d3b2dd..b45f291 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio39.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio39.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio4.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio4.rs index 6c3affc..ef51bec 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio4.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio4.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio40.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio40.rs index e739f38..af75995 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio40.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio40.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio41.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio41.rs index 21c345b..c9ed8ff 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio41.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio41.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio42.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio42.rs index dc402ba..c7bb4a7 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio42.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio42.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio43.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio43.rs index 70b48c4..bf61028 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio43.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio43.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio44.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio44.rs index d5de7b4..c98d823 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio44.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio44.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio45.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio45.rs index e25d49a..d6e5fc5 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio45.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio45.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio46.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio46.rs index ec4932c..a61ac4c 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio46.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio46.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio47.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio47.rs index 828e367..9482c04 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio47.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio47.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio48.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio48.rs index eedde59..16c6476 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio48.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio48.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio49.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio49.rs index b26f90a..95c23d1 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio49.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio49.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio5.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio5.rs index b5eb292..2395cea 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio5.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio5.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio50.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio50.rs index d7623f9..9e529ac 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio50.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio50.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio51.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio51.rs index e95fe49..989cda1 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio51.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio51.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio52.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio52.rs index 72a4c16..6b1dabb 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio52.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio52.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio53.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio53.rs index a3a0e2d..8ce1fd9 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio53.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio53.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio54.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio54.rs index 120852b..dcfdaa3 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio54.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio54.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio55.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio55.rs index 312caad..e56274f 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio55.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio55.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio56.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio56.rs index bc0e03b..9017da7 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio56.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio56.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio57.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio57.rs index 40fab1c..f1eaf55 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio57.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio57.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio58.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio58.rs index 9c56c39..46ffb54 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio58.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio58.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio59.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio59.rs index 1a9fb9d..475b711 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio59.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio59.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio6.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio6.rs index ee9de74..63fb99e 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio6.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio6.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio60.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio60.rs index 43ae2c3..3ed25bb 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio60.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio60.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio61.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio61.rs index 647d02d..bb7f31a 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio61.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio61.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio62.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio62.rs index d79cb93..9a0f5f9 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio62.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio62.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio63.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio63.rs index 422617f..999b142 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio63.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio63.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio7.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio7.rs index 02a90b4..41e3f3f 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio7.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio7.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio8.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio8.rs index e658599..9203dc3 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio8.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio8.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio9.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio9.rs index 426dad5..fc26681 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio9.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_gpio9.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_csn0.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_csn0.rs index d9febf2..1b00d56 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_csn0.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_csn0.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_data0.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_data0.rs index 95eb993..e6f00d5 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_data0.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_data0.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_data1.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_data1.rs index 6308875..d63b3e7 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_data1.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_data1.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_data2.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_data2.rs index f1000f7..2e5d58e 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_data2.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_data2.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_data3.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_data3.rs index d7adcd3..bf123f2 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_data3.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_data3.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_sclk.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_sclk.rs index 3ec3d57..14c49b8 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_sclk.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_qspi_sclk.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_clk.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_clk.rs index deb1be9..3cb752d 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_clk.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_clk.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_cmd.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_cmd.rs index aead87c..cb98e59 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_cmd.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_cmd.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data0.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data0.rs index 98bdcc0..77e4f5f 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data0.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data0.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data1.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data1.rs index f24d28a..1c0deae 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data1.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data1.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data2.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data2.rs index a687ed6..1e17981 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data2.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data2.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data3.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data3.rs index e2730ca..9b226ae 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data3.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data3.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data4.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data4.rs index f345187..a1cf301 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data4.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data4.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data5.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data5.rs index c9f3533..5cb5401 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data5.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data5.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data6.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data6.rs index 5c75958..8d7f00b 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data6.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data6.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data7.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data7.rs index b296372..46685b9 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data7.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_data7.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_strb.rs b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_strb.rs index fca4587..745ed13 100644 --- a/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_strb.rs +++ b/jh7110-vf2-13b-pac/src/sys_pinctrl/padcfg_sd0_strb.rs @@ -5,31 +5,31 @@ pub type W = crate::W; #[doc = "Field `ie` reader - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] pub type IE_R = crate::BitReader; #[doc = "Field `ie` writer - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] -pub type IE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ds` reader - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] pub type DS_R = crate::FieldReader; #[doc = "Field `ds` writer - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] -pub type DS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `pu` reader - Pull-Up (PU) settings - 1: Yes, 0: No"] pub type PU_R = crate::BitReader; #[doc = "Field `pu` writer - Pull-Up (PU) settings - 1: Yes, 0: No"] -pub type PU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pd` reader - Pull-Down (PD) settings - 1: Yes, 0: No"] pub type PD_R = crate::BitReader; #[doc = "Field `pd` writer - Pull-Down (PD) settings - 1: Yes, 0: No"] -pub type PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `slew` reader - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] pub type SLEW_R = crate::BitReader; #[doc = "Field `slew` writer - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] -pub type SLEW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SLEW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `smt` reader - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] pub type SMT_R = crate::BitReader; #[doc = "Field `smt` writer - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] -pub type SMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SMT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pos` reader - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] pub type POS_R = crate::BitReader; #[doc = "Field `pos` writer - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] -pub type POS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type POS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] @@ -71,46 +71,50 @@ impl W { #[doc = "Bit 0 - Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver"] #[inline(always)] #[must_use] - pub fn ie(&mut self) -> IE_W { - IE_W::new(self) + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 0) } #[doc = "Bits 1:2 - Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA"] #[inline(always)] #[must_use] - pub fn ds(&mut self) -> DS_W { - DS_W::new(self) + pub fn ds(&mut self) -> DS_W { + DS_W::new(self, 1) } #[doc = "Bit 3 - Pull-Up (PU) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pu(&mut self) -> PU_W { - PU_W::new(self) + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) } #[doc = "Bit 4 - Pull-Down (PD) settings - 1: Yes, 0: No"] #[inline(always)] #[must_use] - pub fn pd(&mut self) -> PD_W { - PD_W::new(self) + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) } #[doc = "Bit 5 - Slew Rate Control - 0: Slow (Half frequency), 1: Fast"] #[inline(always)] #[must_use] - pub fn slew(&mut self) -> SLEW_W { - SLEW_W::new(self) + pub fn slew(&mut self) -> SLEW_W { + SLEW_W::new(self, 5) } #[doc = "Bit 6 - Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled"] #[inline(always)] #[must_use] - pub fn smt(&mut self) -> SMT_W { - SMT_W::new(self) + pub fn smt(&mut self) -> SMT_W { + SMT_W::new(self, 6) } #[doc = "Bit 7 - Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled"] #[inline(always)] #[must_use] - pub fn pos(&mut self) -> POS_W { - POS_W::new(self) + pub fn pos(&mut self) -> POS_W { + POS_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon.rs b/jh7110-vf2-13b-pac/src/sys_syscon.rs index ac776c1..5d5a4a1 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon.rs @@ -1,312 +1,470 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + sys_sysconsaif_syscfg0: SYS_SYSCONSAIF_SYSCFG0, + sys_sysconsaif_syscfg4: SYS_SYSCONSAIF_SYSCFG4, + sys_sysconsaif_syscfg8: SYS_SYSCONSAIF_SYSCFG8, + sys_sysconsaif_syscfg12: SYS_SYSCONSAIF_SYSCFG12, + sys_sysconsaif_syscfg16: SYS_SYSCONSAIF_SYSCFG16, + sys_sysconsaif_syscfg20: SYS_SYSCONSAIF_SYSCFG20, + sys_sysconsaif_syscfg24: SYS_SYSCONSAIF_SYSCFG24, + sys_sysconsaif_syscfg28: SYS_SYSCONSAIF_SYSCFG28, + sys_sysconsaif_syscfg32: SYS_SYSCONSAIF_SYSCFG32, + sys_sysconsaif_syscfg36: SYS_SYSCONSAIF_SYSCFG36, + sys_sysconsaif_syscfg40: SYS_SYSCONSAIF_SYSCFG40, + sys_sysconsaif_syscfg44: SYS_SYSCONSAIF_SYSCFG44, + sys_sysconsaif_syscfg48: SYS_SYSCONSAIF_SYSCFG48, + sys_sysconsaif_syscfg52: SYS_SYSCONSAIF_SYSCFG52, + sys_sysconsaif_syscfg56: SYS_SYSCONSAIF_SYSCFG56, + sys_sysconsaif_syscfg60: SYS_SYSCONSAIF_SYSCFG60, + sys_sysconsaif_syscfg64: SYS_SYSCONSAIF_SYSCFG64, + sys_sysconsaif_syscfg68: SYS_SYSCONSAIF_SYSCFG68, + sys_sysconsaif_syscfg72: SYS_SYSCONSAIF_SYSCFG72, + sys_sysconsaif_syscfg76: SYS_SYSCONSAIF_SYSCFG76, + sys_sysconsaif_syscfg80: SYS_SYSCONSAIF_SYSCFG80, + sys_sysconsaif_syscfg84: SYS_SYSCONSAIF_SYSCFG84, + sys_sysconsaif_syscfg88: SYS_SYSCONSAIF_SYSCFG88, + sys_sysconsaif_syscfg92: SYS_SYSCONSAIF_SYSCFG92, + sys_sysconsaif_syscfg96: SYS_SYSCONSAIF_SYSCFG96, + sys_sysconsaif_syscfg100: SYS_SYSCONSAIF_SYSCFG100, + sys_sysconsaif_syscfg104: SYS_SYSCONSAIF_SYSCFG104, + sys_sysconsaif_syscfg108: SYS_SYSCONSAIF_SYSCFG108, + sys_sysconsaif_syscfg112: SYS_SYSCONSAIF_SYSCFG112, + sys_sysconsaif_syscfg116: SYS_SYSCONSAIF_SYSCFG116, + sys_sysconsaif_syscfg120: SYS_SYSCONSAIF_SYSCFG120, + sys_sysconsaif_syscfg124: SYS_SYSCONSAIF_SYSCFG124, + sys_sysconsaif_syscfg128: SYS_SYSCONSAIF_SYSCFG128, + _reserved33: [u8; 0x04], + sys_sysconsaif_syscfg136: SYS_SYSCONSAIF_SYSCFG136, + sys_sysconsaif_syscfg140: SYS_SYSCONSAIF_SYSCFG140, + sys_sysconsaif_syscfg144: SYS_SYSCONSAIF_SYSCFG144, + sys_sysconsaif_syscfg148: SYS_SYSCONSAIF_SYSCFG148, + sys_sysconsaif_syscfg152: SYS_SYSCONSAIF_SYSCFG152, + sys_sysconsaif_syscfg156: SYS_SYSCONSAIF_SYSCFG156, +} +impl RegisterBlock { #[doc = "0x00 - SYS SYSCONSAIF SYSCFG 0"] - pub sys_sysconsaif_syscfg0: SYS_SYSCONSAIF_SYSCFG0, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg0(&self) -> &SYS_SYSCONSAIF_SYSCFG0 { + &self.sys_sysconsaif_syscfg0 + } #[doc = "0x04 - SYS SYSCONSAIF SYSCFG 4"] - pub sys_sysconsaif_syscfg4: SYS_SYSCONSAIF_SYSCFG4, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg4(&self) -> &SYS_SYSCONSAIF_SYSCFG4 { + &self.sys_sysconsaif_syscfg4 + } #[doc = "0x08 - SYS SYSCONSAIF SYSCFG 8"] - pub sys_sysconsaif_syscfg8: SYS_SYSCONSAIF_SYSCFG8, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg8(&self) -> &SYS_SYSCONSAIF_SYSCFG8 { + &self.sys_sysconsaif_syscfg8 + } #[doc = "0x0c - SYS SYSCONSAIF SYSCFG 12: Set the GPIO voltage of all the 4 GPIO groups in this register"] - pub sys_sysconsaif_syscfg12: SYS_SYSCONSAIF_SYSCFG12, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg12(&self) -> &SYS_SYSCONSAIF_SYSCFG12 { + &self.sys_sysconsaif_syscfg12 + } #[doc = "0x10 - SYS SYSCONSAIF SYSCFG 16"] - pub sys_sysconsaif_syscfg16: SYS_SYSCONSAIF_SYSCFG16, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg16(&self) -> &SYS_SYSCONSAIF_SYSCFG16 { + &self.sys_sysconsaif_syscfg16 + } #[doc = "0x14 - SYS SYSCONSAIF SYSCFG 20"] - pub sys_sysconsaif_syscfg20: SYS_SYSCONSAIF_SYSCFG20, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg20(&self) -> &SYS_SYSCONSAIF_SYSCFG20 { + &self.sys_sysconsaif_syscfg20 + } #[doc = "0x18 - SYS SYSCONSAIF SYSCFG 24"] - pub sys_sysconsaif_syscfg24: SYS_SYSCONSAIF_SYSCFG24, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg24(&self) -> &SYS_SYSCONSAIF_SYSCFG24 { + &self.sys_sysconsaif_syscfg24 + } #[doc = "0x1c - SYS SYSCONSAIF SYSCFG 28"] - pub sys_sysconsaif_syscfg28: SYS_SYSCONSAIF_SYSCFG28, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg28(&self) -> &SYS_SYSCONSAIF_SYSCFG28 { + &self.sys_sysconsaif_syscfg28 + } #[doc = "0x20 - SYS SYSCONSAIF SYSCFG 32"] - pub sys_sysconsaif_syscfg32: SYS_SYSCONSAIF_SYSCFG32, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg32(&self) -> &SYS_SYSCONSAIF_SYSCFG32 { + &self.sys_sysconsaif_syscfg32 + } #[doc = "0x24 - SYS SYSCONSAIF SYSCFG 36"] - pub sys_sysconsaif_syscfg36: SYS_SYSCONSAIF_SYSCFG36, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg36(&self) -> &SYS_SYSCONSAIF_SYSCFG36 { + &self.sys_sysconsaif_syscfg36 + } #[doc = "0x28 - SYS SYSCONSAIF SYSCFG 40"] - pub sys_sysconsaif_syscfg40: SYS_SYSCONSAIF_SYSCFG40, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg40(&self) -> &SYS_SYSCONSAIF_SYSCFG40 { + &self.sys_sysconsaif_syscfg40 + } #[doc = "0x2c - SYS SYSCONSAIF SYSCFG 44"] - pub sys_sysconsaif_syscfg44: SYS_SYSCONSAIF_SYSCFG44, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg44(&self) -> &SYS_SYSCONSAIF_SYSCFG44 { + &self.sys_sysconsaif_syscfg44 + } #[doc = "0x30 - SYS SYSCONSAIF SYSCFG 48"] - pub sys_sysconsaif_syscfg48: SYS_SYSCONSAIF_SYSCFG48, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg48(&self) -> &SYS_SYSCONSAIF_SYSCFG48 { + &self.sys_sysconsaif_syscfg48 + } #[doc = "0x34 - SYS SYSCONSAIF SYSCFG 52"] - pub sys_sysconsaif_syscfg52: SYS_SYSCONSAIF_SYSCFG52, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg52(&self) -> &SYS_SYSCONSAIF_SYSCFG52 { + &self.sys_sysconsaif_syscfg52 + } #[doc = "0x38 - SYS SYSCONSAIF SYSCFG 56"] - pub sys_sysconsaif_syscfg56: SYS_SYSCONSAIF_SYSCFG56, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg56(&self) -> &SYS_SYSCONSAIF_SYSCFG56 { + &self.sys_sysconsaif_syscfg56 + } #[doc = "0x3c - SYS SYSCONSAIF SYSCFG 60"] - pub sys_sysconsaif_syscfg60: SYS_SYSCONSAIF_SYSCFG60, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg60(&self) -> &SYS_SYSCONSAIF_SYSCFG60 { + &self.sys_sysconsaif_syscfg60 + } #[doc = "0x40 - SYS SYSCONSAIF SYSCFG 64"] - pub sys_sysconsaif_syscfg64: SYS_SYSCONSAIF_SYSCFG64, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg64(&self) -> &SYS_SYSCONSAIF_SYSCFG64 { + &self.sys_sysconsaif_syscfg64 + } #[doc = "0x44 - SYS SYSCONSAIF SYSCFG 68"] - pub sys_sysconsaif_syscfg68: SYS_SYSCONSAIF_SYSCFG68, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg68(&self) -> &SYS_SYSCONSAIF_SYSCFG68 { + &self.sys_sysconsaif_syscfg68 + } #[doc = "0x48 - SYS SYSCONSAIF SYSCFG 72"] - pub sys_sysconsaif_syscfg72: SYS_SYSCONSAIF_SYSCFG72, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg72(&self) -> &SYS_SYSCONSAIF_SYSCFG72 { + &self.sys_sysconsaif_syscfg72 + } #[doc = "0x4c - SYS SYSCONSAIF SYSCFG 76"] - pub sys_sysconsaif_syscfg76: SYS_SYSCONSAIF_SYSCFG76, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg76(&self) -> &SYS_SYSCONSAIF_SYSCFG76 { + &self.sys_sysconsaif_syscfg76 + } #[doc = "0x50 - SYS SYSCONSAIF SYSCFG 80"] - pub sys_sysconsaif_syscfg80: SYS_SYSCONSAIF_SYSCFG80, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg80(&self) -> &SYS_SYSCONSAIF_SYSCFG80 { + &self.sys_sysconsaif_syscfg80 + } #[doc = "0x54 - SYS SYSCONSAIF SYSCFG 84"] - pub sys_sysconsaif_syscfg84: SYS_SYSCONSAIF_SYSCFG84, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg84(&self) -> &SYS_SYSCONSAIF_SYSCFG84 { + &self.sys_sysconsaif_syscfg84 + } #[doc = "0x58 - SYS SYSCONSAIF SYSCFG 88"] - pub sys_sysconsaif_syscfg88: SYS_SYSCONSAIF_SYSCFG88, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg88(&self) -> &SYS_SYSCONSAIF_SYSCFG88 { + &self.sys_sysconsaif_syscfg88 + } #[doc = "0x5c - SYS SYSCONSAIF SYSCFG 92"] - pub sys_sysconsaif_syscfg92: SYS_SYSCONSAIF_SYSCFG92, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg92(&self) -> &SYS_SYSCONSAIF_SYSCFG92 { + &self.sys_sysconsaif_syscfg92 + } #[doc = "0x60 - SYS SYSCONSAIF SYSCFG 96"] - pub sys_sysconsaif_syscfg96: SYS_SYSCONSAIF_SYSCFG96, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg96(&self) -> &SYS_SYSCONSAIF_SYSCFG96 { + &self.sys_sysconsaif_syscfg96 + } #[doc = "0x64 - SYS SYSCONSAIF SYSCFG 100"] - pub sys_sysconsaif_syscfg100: SYS_SYSCONSAIF_SYSCFG100, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg100(&self) -> &SYS_SYSCONSAIF_SYSCFG100 { + &self.sys_sysconsaif_syscfg100 + } #[doc = "0x68 - SYS SYSCONSAIF SYSCFG 104"] - pub sys_sysconsaif_syscfg104: SYS_SYSCONSAIF_SYSCFG104, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg104(&self) -> &SYS_SYSCONSAIF_SYSCFG104 { + &self.sys_sysconsaif_syscfg104 + } #[doc = "0x6c - SYS SYSCONSAIF SYSCFG 108"] - pub sys_sysconsaif_syscfg108: SYS_SYSCONSAIF_SYSCFG108, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg108(&self) -> &SYS_SYSCONSAIF_SYSCFG108 { + &self.sys_sysconsaif_syscfg108 + } #[doc = "0x70 - SYS SYSCONSAIF SYSCFG 112"] - pub sys_sysconsaif_syscfg112: SYS_SYSCONSAIF_SYSCFG112, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg112(&self) -> &SYS_SYSCONSAIF_SYSCFG112 { + &self.sys_sysconsaif_syscfg112 + } #[doc = "0x74 - SYS SYSCONSAIF SYSCFG 116"] - pub sys_sysconsaif_syscfg116: SYS_SYSCONSAIF_SYSCFG116, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg116(&self) -> &SYS_SYSCONSAIF_SYSCFG116 { + &self.sys_sysconsaif_syscfg116 + } #[doc = "0x78 - SYS SYSCONSAIF SYSCFG 120"] - pub sys_sysconsaif_syscfg120: SYS_SYSCONSAIF_SYSCFG120, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg120(&self) -> &SYS_SYSCONSAIF_SYSCFG120 { + &self.sys_sysconsaif_syscfg120 + } #[doc = "0x7c - SYS SYSCONSAIF SYSCFG 124"] - pub sys_sysconsaif_syscfg124: SYS_SYSCONSAIF_SYSCFG124, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg124(&self) -> &SYS_SYSCONSAIF_SYSCFG124 { + &self.sys_sysconsaif_syscfg124 + } #[doc = "0x80 - SYS SYSCONSAIF SYSCFG 128"] - pub sys_sysconsaif_syscfg128: SYS_SYSCONSAIF_SYSCFG128, - _reserved33: [u8; 0x04], + #[inline(always)] + pub const fn sys_sysconsaif_syscfg128(&self) -> &SYS_SYSCONSAIF_SYSCFG128 { + &self.sys_sysconsaif_syscfg128 + } #[doc = "0x88 - SYS SYSCONSAIF SYSCFG 136"] - pub sys_sysconsaif_syscfg136: SYS_SYSCONSAIF_SYSCFG136, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg136(&self) -> &SYS_SYSCONSAIF_SYSCFG136 { + &self.sys_sysconsaif_syscfg136 + } #[doc = "0x8c - SYS SYSCONSAIF SYSCFG 140"] - pub sys_sysconsaif_syscfg140: SYS_SYSCONSAIF_SYSCFG140, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg140(&self) -> &SYS_SYSCONSAIF_SYSCFG140 { + &self.sys_sysconsaif_syscfg140 + } #[doc = "0x90 - SYS SYSCONSAIF SYSCFG 144"] - pub sys_sysconsaif_syscfg144: SYS_SYSCONSAIF_SYSCFG144, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg144(&self) -> &SYS_SYSCONSAIF_SYSCFG144 { + &self.sys_sysconsaif_syscfg144 + } #[doc = "0x94 - SYS SYSCONSAIF SYSCFG 148"] - pub sys_sysconsaif_syscfg148: SYS_SYSCONSAIF_SYSCFG148, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg148(&self) -> &SYS_SYSCONSAIF_SYSCFG148 { + &self.sys_sysconsaif_syscfg148 + } #[doc = "0x98 - SYS SYSCONSAIF SYSCFG 152"] - pub sys_sysconsaif_syscfg152: SYS_SYSCONSAIF_SYSCFG152, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg152(&self) -> &SYS_SYSCONSAIF_SYSCFG152 { + &self.sys_sysconsaif_syscfg152 + } #[doc = "0x9c - SYS SYSCONSAIF SYSCFG 156"] - pub sys_sysconsaif_syscfg156: SYS_SYSCONSAIF_SYSCFG156, + #[inline(always)] + pub const fn sys_sysconsaif_syscfg156(&self) -> &SYS_SYSCONSAIF_SYSCFG156 { + &self.sys_sysconsaif_syscfg156 + } } -#[doc = "sys_sysconsaif_syscfg0 (rw) register accessor: SYS SYSCONSAIF SYSCFG 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg0`] +#[doc = "sys_sysconsaif_syscfg0 (rw) register accessor: SYS SYSCONSAIF SYSCFG 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg0`] module"] pub type SYS_SYSCONSAIF_SYSCFG0 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 0"] pub mod sys_sysconsaif_syscfg0; -#[doc = "sys_sysconsaif_syscfg4 (rw) register accessor: SYS SYSCONSAIF SYSCFG 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg4`] +#[doc = "sys_sysconsaif_syscfg4 (rw) register accessor: SYS SYSCONSAIF SYSCFG 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg4`] module"] pub type SYS_SYSCONSAIF_SYSCFG4 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 4"] pub mod sys_sysconsaif_syscfg4; -#[doc = "sys_sysconsaif_syscfg8 (rw) register accessor: SYS SYSCONSAIF SYSCFG 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg8`] +#[doc = "sys_sysconsaif_syscfg8 (rw) register accessor: SYS SYSCONSAIF SYSCFG 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg8`] module"] pub type SYS_SYSCONSAIF_SYSCFG8 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 8"] pub mod sys_sysconsaif_syscfg8; -#[doc = "sys_sysconsaif_syscfg12 (rw) register accessor: SYS SYSCONSAIF SYSCFG 12: Set the GPIO voltage of all the 4 GPIO groups in this register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg12::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg12`] +#[doc = "sys_sysconsaif_syscfg12 (rw) register accessor: SYS SYSCONSAIF SYSCFG 12: Set the GPIO voltage of all the 4 GPIO groups in this register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg12::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg12`] module"] pub type SYS_SYSCONSAIF_SYSCFG12 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 12: Set the GPIO voltage of all the 4 GPIO groups in this register"] pub mod sys_sysconsaif_syscfg12; -#[doc = "sys_sysconsaif_syscfg16 (rw) register accessor: SYS SYSCONSAIF SYSCFG 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg16::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg16`] +#[doc = "sys_sysconsaif_syscfg16 (rw) register accessor: SYS SYSCONSAIF SYSCFG 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg16::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg16`] module"] pub type SYS_SYSCONSAIF_SYSCFG16 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 16"] pub mod sys_sysconsaif_syscfg16; -#[doc = "sys_sysconsaif_syscfg20 (rw) register accessor: SYS SYSCONSAIF SYSCFG 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg20::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg20`] +#[doc = "sys_sysconsaif_syscfg20 (rw) register accessor: SYS SYSCONSAIF SYSCFG 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg20::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg20`] module"] pub type SYS_SYSCONSAIF_SYSCFG20 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 20"] pub mod sys_sysconsaif_syscfg20; -#[doc = "sys_sysconsaif_syscfg24 (rw) register accessor: SYS SYSCONSAIF SYSCFG 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg24::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg24`] +#[doc = "sys_sysconsaif_syscfg24 (rw) register accessor: SYS SYSCONSAIF SYSCFG 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg24::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg24`] module"] pub type SYS_SYSCONSAIF_SYSCFG24 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 24"] pub mod sys_sysconsaif_syscfg24; -#[doc = "sys_sysconsaif_syscfg28 (rw) register accessor: SYS SYSCONSAIF SYSCFG 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg28::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg28`] +#[doc = "sys_sysconsaif_syscfg28 (rw) register accessor: SYS SYSCONSAIF SYSCFG 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg28::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg28`] module"] pub type SYS_SYSCONSAIF_SYSCFG28 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 28"] pub mod sys_sysconsaif_syscfg28; -#[doc = "sys_sysconsaif_syscfg32 (rw) register accessor: SYS SYSCONSAIF SYSCFG 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg32::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg32`] +#[doc = "sys_sysconsaif_syscfg32 (rw) register accessor: SYS SYSCONSAIF SYSCFG 32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg32::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg32`] module"] pub type SYS_SYSCONSAIF_SYSCFG32 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 32"] pub mod sys_sysconsaif_syscfg32; -#[doc = "sys_sysconsaif_syscfg36 (rw) register accessor: SYS SYSCONSAIF SYSCFG 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg36::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg36`] +#[doc = "sys_sysconsaif_syscfg36 (rw) register accessor: SYS SYSCONSAIF SYSCFG 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg36::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg36`] module"] pub type SYS_SYSCONSAIF_SYSCFG36 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 36"] pub mod sys_sysconsaif_syscfg36; -#[doc = "sys_sysconsaif_syscfg40 (rw) register accessor: SYS SYSCONSAIF SYSCFG 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg40::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg40`] +#[doc = "sys_sysconsaif_syscfg40 (rw) register accessor: SYS SYSCONSAIF SYSCFG 40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg40::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg40`] module"] pub type SYS_SYSCONSAIF_SYSCFG40 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 40"] pub mod sys_sysconsaif_syscfg40; -#[doc = "sys_sysconsaif_syscfg44 (rw) register accessor: SYS SYSCONSAIF SYSCFG 44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg44::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg44`] +#[doc = "sys_sysconsaif_syscfg44 (rw) register accessor: SYS SYSCONSAIF SYSCFG 44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg44::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg44`] module"] pub type SYS_SYSCONSAIF_SYSCFG44 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 44"] pub mod sys_sysconsaif_syscfg44; -#[doc = "sys_sysconsaif_syscfg48 (rw) register accessor: SYS SYSCONSAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg48`] +#[doc = "sys_sysconsaif_syscfg48 (rw) register accessor: SYS SYSCONSAIF SYSCFG 48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg48::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg48`] module"] pub type SYS_SYSCONSAIF_SYSCFG48 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 48"] pub mod sys_sysconsaif_syscfg48; -#[doc = "sys_sysconsaif_syscfg52 (rw) register accessor: SYS SYSCONSAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg52`] +#[doc = "sys_sysconsaif_syscfg52 (rw) register accessor: SYS SYSCONSAIF SYSCFG 52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg52::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg52`] module"] pub type SYS_SYSCONSAIF_SYSCFG52 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 52"] pub mod sys_sysconsaif_syscfg52; -#[doc = "sys_sysconsaif_syscfg56 (rw) register accessor: SYS SYSCONSAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg56`] +#[doc = "sys_sysconsaif_syscfg56 (rw) register accessor: SYS SYSCONSAIF SYSCFG 56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg56::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg56`] module"] pub type SYS_SYSCONSAIF_SYSCFG56 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 56"] pub mod sys_sysconsaif_syscfg56; -#[doc = "sys_sysconsaif_syscfg60 (rw) register accessor: SYS SYSCONSAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg60`] +#[doc = "sys_sysconsaif_syscfg60 (rw) register accessor: SYS SYSCONSAIF SYSCFG 60\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg60::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg60::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg60`] module"] pub type SYS_SYSCONSAIF_SYSCFG60 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 60"] pub mod sys_sysconsaif_syscfg60; -#[doc = "sys_sysconsaif_syscfg64 (rw) register accessor: SYS SYSCONSAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg64`] +#[doc = "sys_sysconsaif_syscfg64 (rw) register accessor: SYS SYSCONSAIF SYSCFG 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg64::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg64::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg64`] module"] pub type SYS_SYSCONSAIF_SYSCFG64 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 64"] pub mod sys_sysconsaif_syscfg64; -#[doc = "sys_sysconsaif_syscfg68 (rw) register accessor: SYS SYSCONSAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg68`] +#[doc = "sys_sysconsaif_syscfg68 (rw) register accessor: SYS SYSCONSAIF SYSCFG 68\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg68::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg68::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg68`] module"] pub type SYS_SYSCONSAIF_SYSCFG68 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 68"] pub mod sys_sysconsaif_syscfg68; -#[doc = "sys_sysconsaif_syscfg72 (rw) register accessor: SYS SYSCONSAIF SYSCFG 72\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg72::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg72::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg72`] +#[doc = "sys_sysconsaif_syscfg72 (rw) register accessor: SYS SYSCONSAIF SYSCFG 72\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg72::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg72::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg72`] module"] pub type SYS_SYSCONSAIF_SYSCFG72 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 72"] pub mod sys_sysconsaif_syscfg72; -#[doc = "sys_sysconsaif_syscfg76 (rw) register accessor: SYS SYSCONSAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg76`] +#[doc = "sys_sysconsaif_syscfg76 (rw) register accessor: SYS SYSCONSAIF SYSCFG 76\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg76::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg76::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg76`] module"] pub type SYS_SYSCONSAIF_SYSCFG76 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 76"] pub mod sys_sysconsaif_syscfg76; -#[doc = "sys_sysconsaif_syscfg80 (rw) register accessor: SYS SYSCONSAIF SYSCFG 80\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg80::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg80::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg80`] +#[doc = "sys_sysconsaif_syscfg80 (rw) register accessor: SYS SYSCONSAIF SYSCFG 80\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg80::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg80::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg80`] module"] pub type SYS_SYSCONSAIF_SYSCFG80 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 80"] pub mod sys_sysconsaif_syscfg80; -#[doc = "sys_sysconsaif_syscfg84 (rw) register accessor: SYS SYSCONSAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg84`] +#[doc = "sys_sysconsaif_syscfg84 (rw) register accessor: SYS SYSCONSAIF SYSCFG 84\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg84::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg84::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg84`] module"] pub type SYS_SYSCONSAIF_SYSCFG84 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 84"] pub mod sys_sysconsaif_syscfg84; -#[doc = "sys_sysconsaif_syscfg88 (rw) register accessor: SYS SYSCONSAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg88`] +#[doc = "sys_sysconsaif_syscfg88 (rw) register accessor: SYS SYSCONSAIF SYSCFG 88\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg88::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg88::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg88`] module"] pub type SYS_SYSCONSAIF_SYSCFG88 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 88"] pub mod sys_sysconsaif_syscfg88; -#[doc = "sys_sysconsaif_syscfg92 (rw) register accessor: SYS SYSCONSAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg92`] +#[doc = "sys_sysconsaif_syscfg92 (rw) register accessor: SYS SYSCONSAIF SYSCFG 92\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg92::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg92::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg92`] module"] pub type SYS_SYSCONSAIF_SYSCFG92 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 92"] pub mod sys_sysconsaif_syscfg92; -#[doc = "sys_sysconsaif_syscfg96 (rw) register accessor: SYS SYSCONSAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg96`] +#[doc = "sys_sysconsaif_syscfg96 (rw) register accessor: SYS SYSCONSAIF SYSCFG 96\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg96::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg96::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg96`] module"] pub type SYS_SYSCONSAIF_SYSCFG96 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 96"] pub mod sys_sysconsaif_syscfg96; -#[doc = "sys_sysconsaif_syscfg100 (rw) register accessor: SYS SYSCONSAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg100`] +#[doc = "sys_sysconsaif_syscfg100 (rw) register accessor: SYS SYSCONSAIF SYSCFG 100\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg100::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg100::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg100`] module"] pub type SYS_SYSCONSAIF_SYSCFG100 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 100"] pub mod sys_sysconsaif_syscfg100; -#[doc = "sys_sysconsaif_syscfg104 (rw) register accessor: SYS SYSCONSAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg104`] +#[doc = "sys_sysconsaif_syscfg104 (rw) register accessor: SYS SYSCONSAIF SYSCFG 104\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg104::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg104::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg104`] module"] pub type SYS_SYSCONSAIF_SYSCFG104 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 104"] pub mod sys_sysconsaif_syscfg104; -#[doc = "sys_sysconsaif_syscfg108 (rw) register accessor: SYS SYSCONSAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg108`] +#[doc = "sys_sysconsaif_syscfg108 (rw) register accessor: SYS SYSCONSAIF SYSCFG 108\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg108::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg108::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg108`] module"] pub type SYS_SYSCONSAIF_SYSCFG108 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 108"] pub mod sys_sysconsaif_syscfg108; -#[doc = "sys_sysconsaif_syscfg112 (rw) register accessor: SYS SYSCONSAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg112`] +#[doc = "sys_sysconsaif_syscfg112 (rw) register accessor: SYS SYSCONSAIF SYSCFG 112\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg112::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg112`] module"] pub type SYS_SYSCONSAIF_SYSCFG112 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 112"] pub mod sys_sysconsaif_syscfg112; -#[doc = "sys_sysconsaif_syscfg116 (rw) register accessor: SYS SYSCONSAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg116`] +#[doc = "sys_sysconsaif_syscfg116 (rw) register accessor: SYS SYSCONSAIF SYSCFG 116\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg116::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg116`] module"] pub type SYS_SYSCONSAIF_SYSCFG116 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 116"] pub mod sys_sysconsaif_syscfg116; -#[doc = "sys_sysconsaif_syscfg120 (rw) register accessor: SYS SYSCONSAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg120`] +#[doc = "sys_sysconsaif_syscfg120 (rw) register accessor: SYS SYSCONSAIF SYSCFG 120\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg120::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg120`] module"] pub type SYS_SYSCONSAIF_SYSCFG120 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 120"] pub mod sys_sysconsaif_syscfg120; -#[doc = "sys_sysconsaif_syscfg124 (rw) register accessor: SYS SYSCONSAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg124`] +#[doc = "sys_sysconsaif_syscfg124 (rw) register accessor: SYS SYSCONSAIF SYSCFG 124\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg124::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg124::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg124`] module"] pub type SYS_SYSCONSAIF_SYSCFG124 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 124"] pub mod sys_sysconsaif_syscfg124; -#[doc = "sys_sysconsaif_syscfg128 (rw) register accessor: SYS SYSCONSAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg128`] +#[doc = "sys_sysconsaif_syscfg128 (rw) register accessor: SYS SYSCONSAIF SYSCFG 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg128::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg128::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg128`] module"] pub type SYS_SYSCONSAIF_SYSCFG128 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 128"] pub mod sys_sysconsaif_syscfg128; -#[doc = "sys_sysconsaif_syscfg136 (rw) register accessor: SYS SYSCONSAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg136`] +#[doc = "sys_sysconsaif_syscfg136 (rw) register accessor: SYS SYSCONSAIF SYSCFG 136\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg136::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg136::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg136`] module"] pub type SYS_SYSCONSAIF_SYSCFG136 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 136"] pub mod sys_sysconsaif_syscfg136; -#[doc = "sys_sysconsaif_syscfg140 (rw) register accessor: SYS SYSCONSAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg140::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg140::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg140`] +#[doc = "sys_sysconsaif_syscfg140 (rw) register accessor: SYS SYSCONSAIF SYSCFG 140\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg140::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg140::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg140`] module"] pub type SYS_SYSCONSAIF_SYSCFG140 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 140"] pub mod sys_sysconsaif_syscfg140; -#[doc = "sys_sysconsaif_syscfg144 (rw) register accessor: SYS SYSCONSAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg144::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg144::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg144`] +#[doc = "sys_sysconsaif_syscfg144 (rw) register accessor: SYS SYSCONSAIF SYSCFG 144\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg144::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg144::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg144`] module"] pub type SYS_SYSCONSAIF_SYSCFG144 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 144"] pub mod sys_sysconsaif_syscfg144; -#[doc = "sys_sysconsaif_syscfg148 (rw) register accessor: SYS SYSCONSAIF SYSCFG 148\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg148::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg148::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg148`] +#[doc = "sys_sysconsaif_syscfg148 (rw) register accessor: SYS SYSCONSAIF SYSCFG 148\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg148::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg148::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg148`] module"] pub type SYS_SYSCONSAIF_SYSCFG148 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 148"] pub mod sys_sysconsaif_syscfg148; -#[doc = "sys_sysconsaif_syscfg152 (rw) register accessor: SYS SYSCONSAIF SYSCFG 152\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg152::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg152::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg152`] +#[doc = "sys_sysconsaif_syscfg152 (rw) register accessor: SYS SYSCONSAIF SYSCFG 152\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg152::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg152::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg152`] module"] pub type SYS_SYSCONSAIF_SYSCFG152 = crate::Reg; #[doc = "SYS SYSCONSAIF SYSCFG 152"] pub mod sys_sysconsaif_syscfg152; -#[doc = "sys_sysconsaif_syscfg156 (rw) register accessor: SYS SYSCONSAIF SYSCFG 156\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg156::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg156::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_sysconsaif_syscfg156`] +#[doc = "sys_sysconsaif_syscfg156 (rw) register accessor: SYS SYSCONSAIF SYSCFG 156\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_sysconsaif_syscfg156::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_sysconsaif_syscfg156::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_sysconsaif_syscfg156`] module"] pub type SYS_SYSCONSAIF_SYSCFG156 = crate::Reg; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg0.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg0.rs index d6622af..aee6cd6 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg0.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg0.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `scfg_e24_remap_haddr` reader - scfg_e24_remap_haddr"] pub type SCFG_E24_REMAP_HADDR_R = crate::FieldReader; #[doc = "Field `scfg_e24_remap_haddr` writer - scfg_e24_remap_haddr"] -pub type SCFG_E24_REMAP_HADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_E24_REMAP_HADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_hifi4_idma_remap_araddr` reader - scfg_hifi4_idma_remap_araddr"] pub type SCFG_HIFI4_IDMA_REMAP_ARADDR_R = crate::FieldReader; #[doc = "Field `scfg_hifi4_idma_remap_araddr` writer - scfg_hifi4_idma_remap_araddr"] -pub type SCFG_HIFI4_IDMA_REMAP_ARADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_HIFI4_IDMA_REMAP_ARADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_hifi4_idma_remap_awaddr` reader - scfg_hifi4_idma_remap_awaddr"] pub type SCFG_HIFI4_IDMA_REMAP_AWADDR_R = crate::FieldReader; #[doc = "Field `scfg_hifi4_idma_remap_awaddr` writer - scfg_hifi4_idma_remap_awaddr"] -pub type SCFG_HIFI4_IDMA_REMAP_AWADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_HIFI4_IDMA_REMAP_AWADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_hifi4_sys_remap_araddr` reader - scfg_hifi4_sys_remap_araddr"] pub type SCFG_HIFI4_SYS_REMAP_ARADDR_R = crate::FieldReader; #[doc = "Field `scfg_hifi4_sys_remap_araddr` writer - scfg_hifi4_sys_remap_araddr"] -pub type SCFG_HIFI4_SYS_REMAP_ARADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_HIFI4_SYS_REMAP_ARADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_hifi4_sys_remap_awaddr` reader - scfg_hifi4_sys_remap_awaddr"] pub type SCFG_HIFI4_SYS_REMAP_AWADDR_R = crate::FieldReader; #[doc = "Field `scfg_hifi4_sys_remap_awaddr` writer - scfg_hifi4_sys_remap_awaddr"] -pub type SCFG_HIFI4_SYS_REMAP_AWADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_HIFI4_SYS_REMAP_AWADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_jpg_remap_araddr` reader - scfg_jpg_remap_araddr"] pub type SCFG_JPG_REMAP_ARADDR_R = crate::FieldReader; #[doc = "Field `scfg_jpg_remap_araddr` writer - scfg_jpg_remap_araddr"] -pub type SCFG_JPG_REMAP_ARADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_JPG_REMAP_ARADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_jpg_remap_awaddr` reader - scfg_jpg_remap_awaddr"] pub type SCFG_JPG_REMAP_AWADDR_R = crate::FieldReader; #[doc = "Field `scfg_jpg_remap_awaddr` writer - scfg_jpg_remap_awaddr"] -pub type SCFG_JPG_REMAP_AWADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_JPG_REMAP_AWADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_sd0_remap_araddr` reader - scfg_sd0_remap_araddr"] pub type SCFG_SD0_REMAP_ARADDR_R = crate::FieldReader; #[doc = "Field `scfg_sd0_remap_araddr` writer - scfg_sd0_remap_araddr"] -pub type SCFG_SD0_REMAP_ARADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_SD0_REMAP_ARADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - scfg_e24_remap_haddr"] #[inline(always)] @@ -80,68 +80,70 @@ impl W { #[doc = "Bits 0:3 - scfg_e24_remap_haddr"] #[inline(always)] #[must_use] - pub fn scfg_e24_remap_haddr( - &mut self, - ) -> SCFG_E24_REMAP_HADDR_W { - SCFG_E24_REMAP_HADDR_W::new(self) + pub fn scfg_e24_remap_haddr(&mut self) -> SCFG_E24_REMAP_HADDR_W { + SCFG_E24_REMAP_HADDR_W::new(self, 0) } #[doc = "Bits 4:7 - scfg_hifi4_idma_remap_araddr"] #[inline(always)] #[must_use] pub fn scfg_hifi4_idma_remap_araddr( &mut self, - ) -> SCFG_HIFI4_IDMA_REMAP_ARADDR_W { - SCFG_HIFI4_IDMA_REMAP_ARADDR_W::new(self) + ) -> SCFG_HIFI4_IDMA_REMAP_ARADDR_W { + SCFG_HIFI4_IDMA_REMAP_ARADDR_W::new(self, 4) } #[doc = "Bits 8:11 - scfg_hifi4_idma_remap_awaddr"] #[inline(always)] #[must_use] pub fn scfg_hifi4_idma_remap_awaddr( &mut self, - ) -> SCFG_HIFI4_IDMA_REMAP_AWADDR_W { - SCFG_HIFI4_IDMA_REMAP_AWADDR_W::new(self) + ) -> SCFG_HIFI4_IDMA_REMAP_AWADDR_W { + SCFG_HIFI4_IDMA_REMAP_AWADDR_W::new(self, 8) } #[doc = "Bits 12:15 - scfg_hifi4_sys_remap_araddr"] #[inline(always)] #[must_use] pub fn scfg_hifi4_sys_remap_araddr( &mut self, - ) -> SCFG_HIFI4_SYS_REMAP_ARADDR_W { - SCFG_HIFI4_SYS_REMAP_ARADDR_W::new(self) + ) -> SCFG_HIFI4_SYS_REMAP_ARADDR_W { + SCFG_HIFI4_SYS_REMAP_ARADDR_W::new(self, 12) } #[doc = "Bits 16:19 - scfg_hifi4_sys_remap_awaddr"] #[inline(always)] #[must_use] pub fn scfg_hifi4_sys_remap_awaddr( &mut self, - ) -> SCFG_HIFI4_SYS_REMAP_AWADDR_W { - SCFG_HIFI4_SYS_REMAP_AWADDR_W::new(self) + ) -> SCFG_HIFI4_SYS_REMAP_AWADDR_W { + SCFG_HIFI4_SYS_REMAP_AWADDR_W::new(self, 16) } #[doc = "Bits 20:23 - scfg_jpg_remap_araddr"] #[inline(always)] #[must_use] pub fn scfg_jpg_remap_araddr( &mut self, - ) -> SCFG_JPG_REMAP_ARADDR_W { - SCFG_JPG_REMAP_ARADDR_W::new(self) + ) -> SCFG_JPG_REMAP_ARADDR_W { + SCFG_JPG_REMAP_ARADDR_W::new(self, 20) } #[doc = "Bits 24:27 - scfg_jpg_remap_awaddr"] #[inline(always)] #[must_use] pub fn scfg_jpg_remap_awaddr( &mut self, - ) -> SCFG_JPG_REMAP_AWADDR_W { - SCFG_JPG_REMAP_AWADDR_W::new(self) + ) -> SCFG_JPG_REMAP_AWADDR_W { + SCFG_JPG_REMAP_AWADDR_W::new(self, 24) } #[doc = "Bits 28:31 - scfg_sd0_remap_araddr"] #[inline(always)] #[must_use] pub fn scfg_sd0_remap_araddr( &mut self, - ) -> SCFG_SD0_REMAP_ARADDR_W { - SCFG_SD0_REMAP_ARADDR_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> SCFG_SD0_REMAP_ARADDR_W { + SCFG_SD0_REMAP_ARADDR_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg100.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg100.rs index 7c1d8e1..952c6cb 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg100.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg100.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `u0_trace_mtx_scfg_c3_in0_ctl` reader - u0_trace_mtx_scfg_c3_in0_ctl"] pub type U0_TRACE_MTX_SCFG_C3_IN0_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c3_in0_ctl` writer - u0_trace_mtx_scfg_c3_in0_ctl"] -pub type U0_TRACE_MTX_SCFG_C3_IN0_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C3_IN0_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_trace_mtx_scfg_c3_in1_ctl` reader - u0_trace_mtx_scfg_c3_in1_ctl"] pub type U0_TRACE_MTX_SCFG_C3_IN1_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c3_in1_ctl` writer - u0_trace_mtx_scfg_c3_in1_ctl"] -pub type U0_TRACE_MTX_SCFG_C3_IN1_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C3_IN1_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_trace_mtx_scfg_c4_in0_ctl` reader - u0_trace_mtx_scfg_c4_in0_ctl"] pub type U0_TRACE_MTX_SCFG_C4_IN0_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c4_in0_ctl` writer - u0_trace_mtx_scfg_c4_in0_ctl"] -pub type U0_TRACE_MTX_SCFG_C4_IN0_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C4_IN0_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_trace_mtx_scfg_c4_in1_ctl` reader - u0_trace_mtx_scfg_c4_in1_ctl"] pub type U0_TRACE_MTX_SCFG_C4_IN1_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c4_in1_ctl` writer - u0_trace_mtx_scfg_c4_in1_ctl"] -pub type U0_TRACE_MTX_SCFG_C4_IN1_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C4_IN1_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_u7mc_sft7110_cease_from_tile_0` reader - u0_u7mc_sft7110_cease_from_tile_0"] pub type U0_U7MC_SFT7110_CEASE_FROM_TILE_0_R = crate::BitReader; #[doc = "Field `u0_u7mc_sft7110_cease_from_tile_1` reader - u0_u7mc_sft7110_cease_from_tile_1"] @@ -116,34 +116,38 @@ impl W { #[must_use] pub fn u0_trace_mtx_scfg_c3_in0_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C3_IN0_CTL_W { - U0_TRACE_MTX_SCFG_C3_IN0_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C3_IN0_CTL_W { + U0_TRACE_MTX_SCFG_C3_IN0_CTL_W::new(self, 0) } #[doc = "Bits 5:9 - u0_trace_mtx_scfg_c3_in1_ctl"] #[inline(always)] #[must_use] pub fn u0_trace_mtx_scfg_c3_in1_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C3_IN1_CTL_W { - U0_TRACE_MTX_SCFG_C3_IN1_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C3_IN1_CTL_W { + U0_TRACE_MTX_SCFG_C3_IN1_CTL_W::new(self, 5) } #[doc = "Bits 10:14 - u0_trace_mtx_scfg_c4_in0_ctl"] #[inline(always)] #[must_use] pub fn u0_trace_mtx_scfg_c4_in0_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C4_IN0_CTL_W { - U0_TRACE_MTX_SCFG_C4_IN0_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C4_IN0_CTL_W { + U0_TRACE_MTX_SCFG_C4_IN0_CTL_W::new(self, 10) } #[doc = "Bits 15:19 - u0_trace_mtx_scfg_c4_in1_ctl"] #[inline(always)] #[must_use] pub fn u0_trace_mtx_scfg_c4_in1_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C4_IN1_CTL_W { - U0_TRACE_MTX_SCFG_C4_IN1_CTL_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_TRACE_MTX_SCFG_C4_IN1_CTL_W { + U0_TRACE_MTX_SCFG_C4_IN1_CTL_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg104.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg104.rs index ab51c02..c2a5313 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg104.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg104.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_u7mc_sft7110_reset_vector_1_31_0` reader - u0_u7mc_sft7110_reset_vector_1_31_0"] pub type U0_U7MC_SFT7110_RESET_VECTOR_1_31_0_R = crate::FieldReader; #[doc = "Field `u0_u7mc_sft7110_reset_vector_1_31_0` writer - u0_u7mc_sft7110_reset_vector_1_31_0"] -pub type U0_U7MC_SFT7110_RESET_VECTOR_1_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_U7MC_SFT7110_RESET_VECTOR_1_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_u7mc_sft7110_reset_vector_1_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_u7mc_sft7110_reset_vector_1_31_0( &mut self, - ) -> U0_U7MC_SFT7110_RESET_VECTOR_1_31_0_W { - U0_U7MC_SFT7110_RESET_VECTOR_1_31_0_W::new(self) + ) -> U0_U7MC_SFT7110_RESET_VECTOR_1_31_0_W { + U0_U7MC_SFT7110_RESET_VECTOR_1_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg108.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg108.rs index 9056432..8c92258 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg108.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg108.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_u7mc_sft7110_reset_vector_1_35_32` reader - u0_u7mc_sft7110_reset_vector_1_35_32"] pub type U0_U7MC_SFT7110_RESET_VECTOR_1_35_32_R = crate::FieldReader; #[doc = "Field `u0_u7mc_sft7110_reset_vector_1_35_32` writer - u0_u7mc_sft7110_reset_vector_1_35_32"] -pub type U0_U7MC_SFT7110_RESET_VECTOR_1_35_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 4, O>; +pub type U0_U7MC_SFT7110_RESET_VECTOR_1_35_32_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - u0_u7mc_sft7110_reset_vector_1_35_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_u7mc_sft7110_reset_vector_1_35_32( &mut self, - ) -> U0_U7MC_SFT7110_RESET_VECTOR_1_35_32_W { - U0_U7MC_SFT7110_RESET_VECTOR_1_35_32_W::new(self) + ) -> U0_U7MC_SFT7110_RESET_VECTOR_1_35_32_W { + U0_U7MC_SFT7110_RESET_VECTOR_1_35_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg112.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg112.rs index 50c53b1..ebc4521 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg112.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg112.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_u7mc_sft7110_reset_vector_2_31_0` reader - u0_u7mc_sft7110_reset_vector_2_31_0"] pub type U0_U7MC_SFT7110_RESET_VECTOR_2_31_0_R = crate::FieldReader; #[doc = "Field `u0_u7mc_sft7110_reset_vector_2_31_0` writer - u0_u7mc_sft7110_reset_vector_2_31_0"] -pub type U0_U7MC_SFT7110_RESET_VECTOR_2_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_U7MC_SFT7110_RESET_VECTOR_2_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_u7mc_sft7110_reset_vector_2_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_u7mc_sft7110_reset_vector_2_31_0( &mut self, - ) -> U0_U7MC_SFT7110_RESET_VECTOR_2_31_0_W { - U0_U7MC_SFT7110_RESET_VECTOR_2_31_0_W::new(self) + ) -> U0_U7MC_SFT7110_RESET_VECTOR_2_31_0_W { + U0_U7MC_SFT7110_RESET_VECTOR_2_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg116.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg116.rs index a86dffc..0005df5 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg116.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg116.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_u7mc_sft7110_reset_vector_2_35_32` reader - u0_u7mc_sft7110_reset_vector_2_35_32"] pub type U0_U7MC_SFT7110_RESET_VECTOR_2_35_32_R = crate::FieldReader; #[doc = "Field `u0_u7mc_sft7110_reset_vector_2_35_32` writer - u0_u7mc_sft7110_reset_vector_2_35_32"] -pub type U0_U7MC_SFT7110_RESET_VECTOR_2_35_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 4, O>; +pub type U0_U7MC_SFT7110_RESET_VECTOR_2_35_32_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - u0_u7mc_sft7110_reset_vector_2_35_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_u7mc_sft7110_reset_vector_2_35_32( &mut self, - ) -> U0_U7MC_SFT7110_RESET_VECTOR_2_35_32_W { - U0_U7MC_SFT7110_RESET_VECTOR_2_35_32_W::new(self) + ) -> U0_U7MC_SFT7110_RESET_VECTOR_2_35_32_W { + U0_U7MC_SFT7110_RESET_VECTOR_2_35_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg12.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg12.rs index 5c95c93..58ab4be 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg12.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg12.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `scfg_vout0_remap_awaddr_gpio0` reader - 0: GPIO Group 0 (GPIO21-35) voltage select 3.3V, 1: GPIO Group 0 (GPIO21-35) voltage select 1.8V"] pub type SCFG_VOUT0_REMAP_AWADDR_GPIO0_R = crate::BitReader; #[doc = "Field `scfg_vout0_remap_awaddr_gpio0` writer - 0: GPIO Group 0 (GPIO21-35) voltage select 3.3V, 1: GPIO Group 0 (GPIO21-35) voltage select 1.8V"] -pub type SCFG_VOUT0_REMAP_AWADDR_GPIO0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SCFG_VOUT0_REMAP_AWADDR_GPIO0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scfg_vout0_remap_awaddr_gpio1` reader - 0: GPIO Group 1 (GPIO36-63) voltage select 3.3V, 1: GPIO Group 1 (GPIO36-63) voltage select 1.8V"] pub type SCFG_VOUT0_REMAP_AWADDR_GPIO1_R = crate::BitReader; #[doc = "Field `scfg_vout0_remap_awaddr_gpio1` writer - 0: GPIO Group 1 (GPIO36-63) voltage select 3.3V, 1: GPIO Group 1 (GPIO36-63) voltage select 1.8V"] -pub type SCFG_VOUT0_REMAP_AWADDR_GPIO1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SCFG_VOUT0_REMAP_AWADDR_GPIO1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scfg_vout0_remap_awaddr_gpio2` reader - 0: GPIO Group 2 (GPIO0-6) voltage select 3.3V, 1: GPIO Group 2 (GPIO0-6) voltage select 1.8V"] pub type SCFG_VOUT0_REMAP_AWADDR_GPIO2_R = crate::BitReader; #[doc = "Field `scfg_vout0_remap_awaddr_gpio2` writer - 0: GPIO Group 2 (GPIO0-6) voltage select 3.3V, 1: GPIO Group 2 (GPIO0-6) voltage select 1.8V"] -pub type SCFG_VOUT0_REMAP_AWADDR_GPIO2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SCFG_VOUT0_REMAP_AWADDR_GPIO2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `scfg_vout0_remap_awaddr_gpio3` reader - 0: GPIO Group 3 (GPIO7-20) voltage select 3.3V, 1: GPIO Group 3 (GPIO7-20) voltage select 1.8V"] pub type SCFG_VOUT0_REMAP_AWADDR_GPIO3_R = crate::BitReader; #[doc = "Field `scfg_vout0_remap_awaddr_gpio3` writer - 0: GPIO Group 3 (GPIO7-20) voltage select 3.3V, 1: GPIO Group 3 (GPIO7-20) voltage select 1.8V"] -pub type SCFG_VOUT0_REMAP_AWADDR_GPIO3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SCFG_VOUT0_REMAP_AWADDR_GPIO3_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 0: GPIO Group 0 (GPIO21-35) voltage select 3.3V, 1: GPIO Group 0 (GPIO21-35) voltage select 1.8V"] #[inline(always)] @@ -46,34 +46,38 @@ impl W { #[must_use] pub fn scfg_vout0_remap_awaddr_gpio0( &mut self, - ) -> SCFG_VOUT0_REMAP_AWADDR_GPIO0_W { - SCFG_VOUT0_REMAP_AWADDR_GPIO0_W::new(self) + ) -> SCFG_VOUT0_REMAP_AWADDR_GPIO0_W { + SCFG_VOUT0_REMAP_AWADDR_GPIO0_W::new(self, 0) } #[doc = "Bit 1 - 0: GPIO Group 1 (GPIO36-63) voltage select 3.3V, 1: GPIO Group 1 (GPIO36-63) voltage select 1.8V"] #[inline(always)] #[must_use] pub fn scfg_vout0_remap_awaddr_gpio1( &mut self, - ) -> SCFG_VOUT0_REMAP_AWADDR_GPIO1_W { - SCFG_VOUT0_REMAP_AWADDR_GPIO1_W::new(self) + ) -> SCFG_VOUT0_REMAP_AWADDR_GPIO1_W { + SCFG_VOUT0_REMAP_AWADDR_GPIO1_W::new(self, 1) } #[doc = "Bit 2 - 0: GPIO Group 2 (GPIO0-6) voltage select 3.3V, 1: GPIO Group 2 (GPIO0-6) voltage select 1.8V"] #[inline(always)] #[must_use] pub fn scfg_vout0_remap_awaddr_gpio2( &mut self, - ) -> SCFG_VOUT0_REMAP_AWADDR_GPIO2_W { - SCFG_VOUT0_REMAP_AWADDR_GPIO2_W::new(self) + ) -> SCFG_VOUT0_REMAP_AWADDR_GPIO2_W { + SCFG_VOUT0_REMAP_AWADDR_GPIO2_W::new(self, 2) } #[doc = "Bit 3 - 0: GPIO Group 3 (GPIO7-20) voltage select 3.3V, 1: GPIO Group 3 (GPIO7-20) voltage select 1.8V"] #[inline(always)] #[must_use] pub fn scfg_vout0_remap_awaddr_gpio3( &mut self, - ) -> SCFG_VOUT0_REMAP_AWADDR_GPIO3_W { - SCFG_VOUT0_REMAP_AWADDR_GPIO3_W::new(self) + ) -> SCFG_VOUT0_REMAP_AWADDR_GPIO3_W { + SCFG_VOUT0_REMAP_AWADDR_GPIO3_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg120.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg120.rs index 0854306..653b656 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg120.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg120.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_u7mc_sft7110_reset_vector_3_31_0` reader - u0_u7mc_sft7110_reset_vector_3_31_0"] pub type U0_U7MC_SFT7110_RESET_VECTOR_3_31_0_R = crate::FieldReader; #[doc = "Field `u0_u7mc_sft7110_reset_vector_3_31_0` writer - u0_u7mc_sft7110_reset_vector_3_31_0"] -pub type U0_U7MC_SFT7110_RESET_VECTOR_3_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_U7MC_SFT7110_RESET_VECTOR_3_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_u7mc_sft7110_reset_vector_3_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_u7mc_sft7110_reset_vector_3_31_0( &mut self, - ) -> U0_U7MC_SFT7110_RESET_VECTOR_3_31_0_W { - U0_U7MC_SFT7110_RESET_VECTOR_3_31_0_W::new(self) + ) -> U0_U7MC_SFT7110_RESET_VECTOR_3_31_0_W { + U0_U7MC_SFT7110_RESET_VECTOR_3_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg124.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg124.rs index dacd7e6..0356df5 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg124.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg124.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_u7mc_sft7110_reset_vector_3_35_32` reader - u0_u7mc_sft7110_reset_vector_3_35_32"] pub type U0_U7MC_SFT7110_RESET_VECTOR_3_35_32_R = crate::FieldReader; #[doc = "Field `u0_u7mc_sft7110_reset_vector_3_35_32` writer - u0_u7mc_sft7110_reset_vector_3_35_32"] -pub type U0_U7MC_SFT7110_RESET_VECTOR_3_35_32_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 4, O>; +pub type U0_U7MC_SFT7110_RESET_VECTOR_3_35_32_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - u0_u7mc_sft7110_reset_vector_3_35_32"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_u7mc_sft7110_reset_vector_3_35_32( &mut self, - ) -> U0_U7MC_SFT7110_RESET_VECTOR_3_35_32_W { - U0_U7MC_SFT7110_RESET_VECTOR_3_35_32_W::new(self) + ) -> U0_U7MC_SFT7110_RESET_VECTOR_3_35_32_W { + U0_U7MC_SFT7110_RESET_VECTOR_3_35_32_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg128.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg128.rs index da52f0c..369726c 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg128.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg128.rs @@ -5,8 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_u7mc_sft7110_reset_vector_4_31_0` reader - u0_u7mc_sft7110_reset_vector_4_31_0"] pub type U0_U7MC_SFT7110_RESET_VECTOR_4_31_0_R = crate::FieldReader; #[doc = "Field `u0_u7mc_sft7110_reset_vector_4_31_0` writer - u0_u7mc_sft7110_reset_vector_4_31_0"] -pub type U0_U7MC_SFT7110_RESET_VECTOR_4_31_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_U7MC_SFT7110_RESET_VECTOR_4_31_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_u7mc_sft7110_reset_vector_4_31_0"] #[inline(always)] @@ -20,10 +19,14 @@ impl W { #[must_use] pub fn u0_u7mc_sft7110_reset_vector_4_31_0( &mut self, - ) -> U0_U7MC_SFT7110_RESET_VECTOR_4_31_0_W { - U0_U7MC_SFT7110_RESET_VECTOR_4_31_0_W::new(self) + ) -> U0_U7MC_SFT7110_RESET_VECTOR_4_31_0_W { + U0_U7MC_SFT7110_RESET_VECTOR_4_31_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg136.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg136.rs index 3a367e8..d7bd89f 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg136.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg136.rs @@ -5,63 +5,57 @@ pub type W = crate::W; #[doc = "Field `u0_venc_intsram_sram_config_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] pub type U0_VENC_INTSRAM_SRAM_CONFIG_SLP_R = crate::BitReader; #[doc = "Field `u0_venc_intsram_sram_config_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] -pub type U0_VENC_INTSRAM_SRAM_CONFIG_SLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_VENC_INTSRAM_SRAM_CONFIG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_venc_intsram_sram_config_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] pub type U0_VENC_INTSRAM_SRAM_CONFIG_SRAM_CONFIG_SD_R = crate::BitReader; #[doc = "Field `u0_venc_intsram_sram_config_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] -pub type U0_VENC_INTSRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_VENC_INTSRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_venc_intsram_sram_config_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_VENC_INTSRAM_SRAM_CONFIG_RTSEL_R = crate::FieldReader; #[doc = "Field `u0_venc_intsram_sram_config_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_VENC_INTSRAM_SRAM_CONFIG_RTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_VENC_INTSRAM_SRAM_CONFIG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_venc_intsram_sram_config_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_VENC_INTSRAM_SRAM_CONFIG_PTSEL_R = crate::FieldReader; #[doc = "Field `u0_venc_intsram_sram_config_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_VENC_INTSRAM_SRAM_CONFIG_PTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_VENC_INTSRAM_SRAM_CONFIG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_venc_intsram_sram_config_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] pub type U0_VENC_INTSRAM_SRAM_CONFIG_TRB_R = crate::FieldReader; #[doc = "Field `u0_venc_intsram_sram_config_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] -pub type U0_VENC_INTSRAM_SRAM_CONFIG_TRB_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_VENC_INTSRAM_SRAM_CONFIG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_venc_intsram_sram_config_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_VENC_INTSRAM_SRAM_CONFIG_WTSEL_R = crate::FieldReader; #[doc = "Field `u0_venc_intsram_sram_config_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_VENC_INTSRAM_SRAM_CONFIG_WTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_VENC_INTSRAM_SRAM_CONFIG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_venc_intsram_sram_config_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] pub type U0_VENC_INTSRAM_SRAM_CONFIG_VS_R = crate::BitReader; #[doc = "Field `u0_venc_intsram_sram_config_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] -pub type U0_VENC_INTSRAM_SRAM_CONFIG_VS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_VENC_INTSRAM_SRAM_CONFIG_VS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_venc_intsram_sram_config_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] pub type U0_VENC_INTSRAM_SRAM_CONFIG_VG_R = crate::BitReader; #[doc = "Field `u0_venc_intsram_sram_config_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] -pub type U0_VENC_INTSRAM_SRAM_CONFIG_VG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_VENC_INTSRAM_SRAM_CONFIG_VG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_wave420l_i_ipu_current_buffer` reader - This signal indicates which buffer is currently active so that the VPU can correctly use the ipu_end_of_row signal for row counter."] pub type U0_WAVE420L_I_IPU_CURRENT_BUFFER_R = crate::FieldReader; #[doc = "Field `u0_wave420l_i_ipu_current_buffer` writer - This signal indicates which buffer is currently active so that the VPU can correctly use the ipu_end_of_row signal for row counter."] -pub type U0_WAVE420L_I_IPU_CURRENT_BUFFER_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 3, O>; +pub type U0_WAVE420L_I_IPU_CURRENT_BUFFER_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_wave420l_i_ipu_end_of_row` reader - This signal is flipped every time when the IPU completes writing a row."] pub type U0_WAVE420L_I_IPU_END_OF_ROW_R = crate::BitReader; #[doc = "Field `u0_wave420l_i_ipu_end_of_row` writer - This signal is flipped every time when the IPU completes writing a row."] -pub type U0_WAVE420L_I_IPU_END_OF_ROW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_WAVE420L_I_IPU_END_OF_ROW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_wave420l_i_ipu_new_frame` reader - This signal is flipped every time when the IPU completes writing a new frame."] pub type U0_WAVE420L_I_IPU_NEW_FRAME_R = crate::BitReader; #[doc = "Field `u0_wave420l_i_ipu_new_frame` writer - This signal is flipped every time when the IPU completes writing a new frame."] -pub type U0_WAVE420L_I_IPU_NEW_FRAME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_WAVE420L_I_IPU_NEW_FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_wave420l_o_vpu_idle` reader - VPU monitoring signal. This signal gives out an opposite value of VPU_BUSY register."] pub type U0_WAVE420L_O_VPU_IDLE_R = crate::BitReader; #[doc = "Field `u1_can_ctrl_can_fd_enable` reader - u1_can_ctrl_can_fd_enable"] pub type U1_CAN_CTRL_CAN_FD_ENABLE_R = crate::BitReader; #[doc = "Field `u1_can_ctrl_can_fd_enable` writer - u1_can_ctrl_can_fd_enable"] -pub type U1_CAN_CTRL_CAN_FD_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_CAN_CTRL_CAN_FD_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_can_ctrl_host_ecc_disable` reader - u1_can_ctrl_host_ecc_disable"] pub type U1_CAN_CTRL_HOST_ECC_DISABLE_R = crate::BitReader; #[doc = "Field `u1_can_ctrl_host_ecc_disable` writer - u1_can_ctrl_host_ecc_disable"] -pub type U1_CAN_CTRL_HOST_ECC_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_CAN_CTRL_HOST_ECC_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] #[inline(always)] @@ -142,106 +136,110 @@ impl W { #[must_use] pub fn u0_venc_intsram_sram_config_slp( &mut self, - ) -> U0_VENC_INTSRAM_SRAM_CONFIG_SLP_W { - U0_VENC_INTSRAM_SRAM_CONFIG_SLP_W::new(self) + ) -> U0_VENC_INTSRAM_SRAM_CONFIG_SLP_W { + U0_VENC_INTSRAM_SRAM_CONFIG_SLP_W::new(self, 0) } #[doc = "Bit 1 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_venc_intsram_sram_config_sram_config_sd( &mut self, - ) -> U0_VENC_INTSRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W { - U0_VENC_INTSRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self) + ) -> U0_VENC_INTSRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W { + U0_VENC_INTSRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self, 1) } #[doc = "Bits 2:3 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_venc_intsram_sram_config_rtsel( &mut self, - ) -> U0_VENC_INTSRAM_SRAM_CONFIG_RTSEL_W { - U0_VENC_INTSRAM_SRAM_CONFIG_RTSEL_W::new(self) + ) -> U0_VENC_INTSRAM_SRAM_CONFIG_RTSEL_W { + U0_VENC_INTSRAM_SRAM_CONFIG_RTSEL_W::new(self, 2) } #[doc = "Bits 4:5 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_venc_intsram_sram_config_ptsel( &mut self, - ) -> U0_VENC_INTSRAM_SRAM_CONFIG_PTSEL_W { - U0_VENC_INTSRAM_SRAM_CONFIG_PTSEL_W::new(self) + ) -> U0_VENC_INTSRAM_SRAM_CONFIG_PTSEL_W { + U0_VENC_INTSRAM_SRAM_CONFIG_PTSEL_W::new(self, 4) } #[doc = "Bits 6:7 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_venc_intsram_sram_config_trb( &mut self, - ) -> U0_VENC_INTSRAM_SRAM_CONFIG_TRB_W { - U0_VENC_INTSRAM_SRAM_CONFIG_TRB_W::new(self) + ) -> U0_VENC_INTSRAM_SRAM_CONFIG_TRB_W { + U0_VENC_INTSRAM_SRAM_CONFIG_TRB_W::new(self, 6) } #[doc = "Bits 8:9 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_venc_intsram_sram_config_wtsel( &mut self, - ) -> U0_VENC_INTSRAM_SRAM_CONFIG_WTSEL_W { - U0_VENC_INTSRAM_SRAM_CONFIG_WTSEL_W::new(self) + ) -> U0_VENC_INTSRAM_SRAM_CONFIG_WTSEL_W { + U0_VENC_INTSRAM_SRAM_CONFIG_WTSEL_W::new(self, 8) } #[doc = "Bit 10 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_venc_intsram_sram_config_vs( &mut self, - ) -> U0_VENC_INTSRAM_SRAM_CONFIG_VS_W { - U0_VENC_INTSRAM_SRAM_CONFIG_VS_W::new(self) + ) -> U0_VENC_INTSRAM_SRAM_CONFIG_VS_W { + U0_VENC_INTSRAM_SRAM_CONFIG_VS_W::new(self, 10) } #[doc = "Bit 11 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_venc_intsram_sram_config_vg( &mut self, - ) -> U0_VENC_INTSRAM_SRAM_CONFIG_VG_W { - U0_VENC_INTSRAM_SRAM_CONFIG_VG_W::new(self) + ) -> U0_VENC_INTSRAM_SRAM_CONFIG_VG_W { + U0_VENC_INTSRAM_SRAM_CONFIG_VG_W::new(self, 11) } #[doc = "Bits 12:14 - This signal indicates which buffer is currently active so that the VPU can correctly use the ipu_end_of_row signal for row counter."] #[inline(always)] #[must_use] pub fn u0_wave420l_i_ipu_current_buffer( &mut self, - ) -> U0_WAVE420L_I_IPU_CURRENT_BUFFER_W { - U0_WAVE420L_I_IPU_CURRENT_BUFFER_W::new(self) + ) -> U0_WAVE420L_I_IPU_CURRENT_BUFFER_W { + U0_WAVE420L_I_IPU_CURRENT_BUFFER_W::new(self, 12) } #[doc = "Bit 15 - This signal is flipped every time when the IPU completes writing a row."] #[inline(always)] #[must_use] pub fn u0_wave420l_i_ipu_end_of_row( &mut self, - ) -> U0_WAVE420L_I_IPU_END_OF_ROW_W { - U0_WAVE420L_I_IPU_END_OF_ROW_W::new(self) + ) -> U0_WAVE420L_I_IPU_END_OF_ROW_W { + U0_WAVE420L_I_IPU_END_OF_ROW_W::new(self, 15) } #[doc = "Bit 16 - This signal is flipped every time when the IPU completes writing a new frame."] #[inline(always)] #[must_use] pub fn u0_wave420l_i_ipu_new_frame( &mut self, - ) -> U0_WAVE420L_I_IPU_NEW_FRAME_W { - U0_WAVE420L_I_IPU_NEW_FRAME_W::new(self) + ) -> U0_WAVE420L_I_IPU_NEW_FRAME_W { + U0_WAVE420L_I_IPU_NEW_FRAME_W::new(self, 16) } #[doc = "Bit 18 - u1_can_ctrl_can_fd_enable"] #[inline(always)] #[must_use] pub fn u1_can_ctrl_can_fd_enable( &mut self, - ) -> U1_CAN_CTRL_CAN_FD_ENABLE_W { - U1_CAN_CTRL_CAN_FD_ENABLE_W::new(self) + ) -> U1_CAN_CTRL_CAN_FD_ENABLE_W { + U1_CAN_CTRL_CAN_FD_ENABLE_W::new(self, 18) } #[doc = "Bit 19 - u1_can_ctrl_host_ecc_disable"] #[inline(always)] #[must_use] pub fn u1_can_ctrl_host_ecc_disable( &mut self, - ) -> U1_CAN_CTRL_HOST_ECC_DISABLE_W { - U1_CAN_CTRL_HOST_ECC_DISABLE_W::new(self) + ) -> U1_CAN_CTRL_HOST_ECC_DISABLE_W { + U1_CAN_CTRL_HOST_ECC_DISABLE_W::new(self, 19) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg140.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg140.rs index 53acc9c..93c9a11 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg140.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg140.rs @@ -7,40 +7,35 @@ pub type U1_CAN_CTRL_HOST_IF_R = crate::FieldReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_SLP_R = crate::BitReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] -pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_SLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_R = crate::BitReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] -pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_R = crate::FieldReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_R = crate::FieldReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_TRB_R = crate::FieldReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] -pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_TRB_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_R = crate::FieldReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_VS_R = crate::BitReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] -pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_VS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_VS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_VG_R = crate::BitReader; #[doc = "Field `u1_gmac5_axi64_scfg_ram_cfg_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] -pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_VG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_GMAC5_AXI64_SCFG_RAM_CFG_VG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:18 - u1_can_ctrl_host_if"] #[inline(always)] @@ -96,66 +91,70 @@ impl W { #[must_use] pub fn u1_gmac5_axi64_scfg_ram_cfg_slp( &mut self, - ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_SLP_W { - U1_GMAC5_AXI64_SCFG_RAM_CFG_SLP_W::new(self) + ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_SLP_W { + U1_GMAC5_AXI64_SCFG_RAM_CFG_SLP_W::new(self, 19) } #[doc = "Bit 20 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u1_gmac5_axi64_scfg_ram_cfg_sram_config_sd( &mut self, - ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W { - U1_GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W::new(self) + ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W { + U1_GMAC5_AXI64_SCFG_RAM_CFG_SRAM_CONFIG_SD_W::new(self, 20) } #[doc = "Bits 21:22 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u1_gmac5_axi64_scfg_ram_cfg_rtsel( &mut self, - ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W { - U1_GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W::new(self) + ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W { + U1_GMAC5_AXI64_SCFG_RAM_CFG_RTSEL_W::new(self, 21) } #[doc = "Bits 23:24 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u1_gmac5_axi64_scfg_ram_cfg_ptsel( &mut self, - ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W { - U1_GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W::new(self) + ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W { + U1_GMAC5_AXI64_SCFG_RAM_CFG_PTSEL_W::new(self, 23) } #[doc = "Bits 25:26 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u1_gmac5_axi64_scfg_ram_cfg_trb( &mut self, - ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_TRB_W { - U1_GMAC5_AXI64_SCFG_RAM_CFG_TRB_W::new(self) + ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_TRB_W { + U1_GMAC5_AXI64_SCFG_RAM_CFG_TRB_W::new(self, 25) } #[doc = "Bits 27:28 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u1_gmac5_axi64_scfg_ram_cfg_wtsel( &mut self, - ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W { - U1_GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W::new(self) + ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W { + U1_GMAC5_AXI64_SCFG_RAM_CFG_WTSEL_W::new(self, 27) } #[doc = "Bit 29 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u1_gmac5_axi64_scfg_ram_cfg_vs( &mut self, - ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_VS_W { - U1_GMAC5_AXI64_SCFG_RAM_CFG_VS_W::new(self) + ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_VS_W { + U1_GMAC5_AXI64_SCFG_RAM_CFG_VS_W::new(self, 29) } #[doc = "Bit 30 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u1_gmac5_axi64_scfg_ram_cfg_vg( &mut self, - ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_VG_W { - U1_GMAC5_AXI64_SCFG_RAM_CFG_VG_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U1_GMAC5_AXI64_SCFG_RAM_CFG_VG_W { + U1_GMAC5_AXI64_SCFG_RAM_CFG_VG_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg144.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg144.rs index 9d929e0..f2ea1a5 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg144.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg144.rs @@ -7,7 +7,7 @@ pub type U1_GMAC5_AXI64_MAC_SPEED_0_R = crate::FieldReader; #[doc = "Field `u1_gmac5_axi64_phy_intf_sel_i` reader - Active PHY Selected | When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. | Values: 0x0:(GMII or MII), 0x01:RGMII, 0x2:SGMII, 0x3:TBI, 0x4:RMII, 0x5:RTBI, 0x6:SMII, 0x7:REVMII"] pub type U1_GMAC5_AXI64_PHY_INTF_SEL_I_R = crate::FieldReader; #[doc = "Field `u1_gmac5_axi64_phy_intf_sel_i` writer - Active PHY Selected | When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. | Values: 0x0:(GMII or MII), 0x01:RGMII, 0x2:SGMII, 0x3:TBI, 0x4:RMII, 0x5:RTBI, 0x6:SMII, 0x7:REVMII"] -pub type U1_GMAC5_AXI64_PHY_INTF_SEL_I_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U1_GMAC5_AXI64_PHY_INTF_SEL_I_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; impl R { #[doc = "Bits 0:1 - u1_gmac5_axi64_mac_speed_0"] #[inline(always)] @@ -26,10 +26,14 @@ impl W { #[must_use] pub fn u1_gmac5_axi64_phy_intf_sel_i( &mut self, - ) -> U1_GMAC5_AXI64_PHY_INTF_SEL_I_W { - U1_GMAC5_AXI64_PHY_INTF_SEL_I_W::new(self) + ) -> U1_GMAC5_AXI64_PHY_INTF_SEL_I_W { + U1_GMAC5_AXI64_PHY_INTF_SEL_I_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg148.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg148.rs index 8066569..db39868 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg148.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg148.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg152.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg152.rs index 7a1a21a..4e5bf6c 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg152.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg152.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg156.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg156.rs index 1dcfd12..d5ac3c2 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg156.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg156.rs @@ -7,25 +7,25 @@ pub type U1_I2C_IC_EN_R = crate::BitReader; #[doc = "Field `u1_sdio_data_strobe_phase_ctrl` reader - Data strobe delay chain select."] pub type U1_SDIO_DATA_STROBE_PHASE_CTRL_R = crate::FieldReader; #[doc = "Field `u1_sdio_data_strobe_phase_ctrl` writer - Data strobe delay chain select."] -pub type U1_SDIO_DATA_STROBE_PHASE_CTRL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U1_SDIO_DATA_STROBE_PHASE_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u1_sdio_hbig_endian` reader - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] pub type U1_SDIO_HBIG_ENDIAN_R = crate::BitReader; #[doc = "Field `u1_sdio_hbig_endian` writer - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] -pub type U1_SDIO_HBIG_ENDIAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_SDIO_HBIG_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_sdio_m_hbig_endian` reader - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] pub type U1_SDIO_M_HBIG_ENDIAN_R = crate::BitReader; #[doc = "Field `u1_sdio_m_hbig_endian` writer - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] -pub type U1_SDIO_M_HBIG_ENDIAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_SDIO_M_HBIG_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_reset_ctrl_clr_reset_status` reader - u1_reset_ctrl_clr_reset_status"] pub type U1_RESET_CTRL_CLR_RESET_STATUS_R = crate::BitReader; #[doc = "Field `u1_reset_ctrl_clr_reset_status` writer - u1_reset_ctrl_clr_reset_status"] -pub type U1_RESET_CTRL_CLR_RESET_STATUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_RESET_CTRL_CLR_RESET_STATUS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_reset_ctrl_pll_timecnt_finish` reader - u1_reset_ctrl_pll_timecnt_finish"] pub type U1_RESET_CTRL_PLL_TIMECNT_FINISH_R = crate::BitReader; #[doc = "Field `u1_reset_ctrl_rstn_sw` reader - u1_reset_ctrl_rstn_sw"] pub type U1_RESET_CTRL_RSTN_SW_R = crate::BitReader; #[doc = "Field `u1_reset_ctrl_rstn_sw` writer - u1_reset_ctrl_rstn_sw"] -pub type U1_RESET_CTRL_RSTN_SW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U1_RESET_CTRL_RSTN_SW_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u1_reset_ctrl_sys_reset_status` reader - u1_reset_ctrl_sys_reset_status"] pub type U1_RESET_CTRL_SYS_RESET_STATUS_R = crate::FieldReader; #[doc = "Field `u2_i2c_ic_en` reader - I2C interface enable."] @@ -111,42 +111,44 @@ impl W { #[must_use] pub fn u1_sdio_data_strobe_phase_ctrl( &mut self, - ) -> U1_SDIO_DATA_STROBE_PHASE_CTRL_W { - U1_SDIO_DATA_STROBE_PHASE_CTRL_W::new(self) + ) -> U1_SDIO_DATA_STROBE_PHASE_CTRL_W { + U1_SDIO_DATA_STROBE_PHASE_CTRL_W::new(self, 1) } #[doc = "Bit 6 - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] #[inline(always)] #[must_use] - pub fn u1_sdio_hbig_endian( - &mut self, - ) -> U1_SDIO_HBIG_ENDIAN_W { - U1_SDIO_HBIG_ENDIAN_W::new(self) + pub fn u1_sdio_hbig_endian(&mut self) -> U1_SDIO_HBIG_ENDIAN_W { + U1_SDIO_HBIG_ENDIAN_W::new(self, 6) } #[doc = "Bit 7 - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] #[inline(always)] #[must_use] pub fn u1_sdio_m_hbig_endian( &mut self, - ) -> U1_SDIO_M_HBIG_ENDIAN_W { - U1_SDIO_M_HBIG_ENDIAN_W::new(self) + ) -> U1_SDIO_M_HBIG_ENDIAN_W { + U1_SDIO_M_HBIG_ENDIAN_W::new(self, 7) } #[doc = "Bit 8 - u1_reset_ctrl_clr_reset_status"] #[inline(always)] #[must_use] pub fn u1_reset_ctrl_clr_reset_status( &mut self, - ) -> U1_RESET_CTRL_CLR_RESET_STATUS_W { - U1_RESET_CTRL_CLR_RESET_STATUS_W::new(self) + ) -> U1_RESET_CTRL_CLR_RESET_STATUS_W { + U1_RESET_CTRL_CLR_RESET_STATUS_W::new(self, 8) } #[doc = "Bit 10 - u1_reset_ctrl_rstn_sw"] #[inline(always)] #[must_use] pub fn u1_reset_ctrl_rstn_sw( &mut self, - ) -> U1_RESET_CTRL_RSTN_SW_W { - U1_RESET_CTRL_RSTN_SW_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U1_RESET_CTRL_RSTN_SW_W { + U1_RESET_CTRL_RSTN_SW_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg16.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg16.rs index 4b51d61..462d45a 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg16.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg16.rs @@ -9,11 +9,11 @@ pub type U0_WAVE511_O_VPU_IDLE_R = crate::BitReader; #[doc = "Field `u0_can_ctrl_can_fd_enable` reader - u0_can_ctrl_can_fd_enable"] pub type U0_CAN_CTRL_CAN_FD_ENABLE_R = crate::BitReader; #[doc = "Field `u0_can_ctrl_can_fd_enable` writer - u0_can_ctrl_can_fd_enable"] -pub type U0_CAN_CTRL_CAN_FD_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CAN_CTRL_CAN_FD_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_can_ctrl_host_ecc_disable` reader - u0_can_ctrl_host_ecc_disable"] pub type U0_CAN_CTRL_HOST_ECC_DISABLE_R = crate::BitReader; #[doc = "Field `u0_can_ctrl_host_ecc_disable` writer - u0_can_ctrl_host_ecc_disable"] -pub type U0_CAN_CTRL_HOST_ECC_DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CAN_CTRL_HOST_ECC_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_can_ctrl_host_if` reader - u0_can_ctrl_host_if"] pub type U0_CAN_CTRL_HOST_IF_R = crate::FieldReader; #[doc = "Field `u0_cdns_qspi_scfg_qspi_sclk_dlychain_sel` reader - des_qspi_sclk_dla: clock delay"] @@ -58,18 +58,22 @@ impl W { #[must_use] pub fn u0_can_ctrl_can_fd_enable( &mut self, - ) -> U0_CAN_CTRL_CAN_FD_ENABLE_W { - U0_CAN_CTRL_CAN_FD_ENABLE_W::new(self) + ) -> U0_CAN_CTRL_CAN_FD_ENABLE_W { + U0_CAN_CTRL_CAN_FD_ENABLE_W::new(self, 3) } #[doc = "Bit 4 - u0_can_ctrl_host_ecc_disable"] #[inline(always)] #[must_use] pub fn u0_can_ctrl_host_ecc_disable( &mut self, - ) -> U0_CAN_CTRL_HOST_ECC_DISABLE_W { - U0_CAN_CTRL_HOST_ECC_DISABLE_W::new(self) + ) -> U0_CAN_CTRL_HOST_ECC_DISABLE_W { + U0_CAN_CTRL_HOST_ECC_DISABLE_W::new(self, 4) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg20.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg20.rs index 7978cba..834cd83 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg20.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg20.rs @@ -5,77 +5,67 @@ pub type W = crate::W; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SLP_R = crate::BitReader; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] -pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_R = crate::BitReader; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] -pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_RTSEL_R = crate::FieldReader; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_RTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_PTSEL_R = crate::FieldReader; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_PTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_TRB_R = crate::FieldReader; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] -pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_TRB_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_WTSEL_R = crate::FieldReader; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_WTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VS_R = crate::BitReader; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] -pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VG_R = crate::BitReader; #[doc = "Field `u0_cdns_qspi_scfg_sram_config_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] -pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SLP_R = crate::BitReader; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] -pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_R = crate::BitReader; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] -pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_RTSEL_R = crate::FieldReader; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_RTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_PTSEL_R = crate::FieldReader; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_PTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_TRB_R = crate::FieldReader; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] -pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_TRB_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_WTSEL_R = crate::FieldReader; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_WTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VS_R = crate::BitReader; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] -pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VG_R = crate::BitReader; #[doc = "Field `u0_cdns_spdif_scfg_sram_config_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] -pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_cdns_spdif_trmodeo` reader - 1 for transmitter 0 for receiver"] pub type U0_CDNS_SPDIF_TRMODEO_R = crate::BitReader; #[doc = "Field `u0_i2c_ic_en` reader - I2C interface enable"] @@ -83,11 +73,11 @@ pub type U0_I2C_IC_EN_R = crate::BitReader; #[doc = "Field `u0_sdio_data_strobe_phase_ctrl` reader - Data strobe delay chain select"] pub type U0_SDIO_DATA_STROBE_PHASE_CTRL_R = crate::FieldReader; #[doc = "Field `u0_sdio_data_strobe_phase_ctrl` writer - Data strobe delay chain select"] -pub type U0_SDIO_DATA_STROBE_PHASE_CTRL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_SDIO_DATA_STROBE_PHASE_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_sdio_hbig_endian` reader - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] pub type U0_SDIO_HBIG_ENDIAN_R = crate::BitReader; #[doc = "Field `u0_sdio_hbig_endian` writer - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] -pub type U0_SDIO_HBIG_ENDIAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_SDIO_HBIG_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] #[inline(always)] @@ -200,146 +190,148 @@ impl W { #[must_use] pub fn u0_cdns_qspi_scfg_sram_config_slp( &mut self, - ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SLP_W { - U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SLP_W::new(self) + ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SLP_W { + U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SLP_W::new(self, 0) } #[doc = "Bit 1 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_cdns_qspi_scfg_sram_config_sram_config_sd( &mut self, - ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W { - U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self) + ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W { + U0_CDNS_QSPI_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self, 1) } #[doc = "Bits 2:3 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_cdns_qspi_scfg_sram_config_rtsel( &mut self, - ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_RTSEL_W { - U0_CDNS_QSPI_SCFG_SRAM_CONFIG_RTSEL_W::new(self) + ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_RTSEL_W { + U0_CDNS_QSPI_SCFG_SRAM_CONFIG_RTSEL_W::new(self, 2) } #[doc = "Bits 4:5 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_cdns_qspi_scfg_sram_config_ptsel( &mut self, - ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_PTSEL_W { - U0_CDNS_QSPI_SCFG_SRAM_CONFIG_PTSEL_W::new(self) + ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_PTSEL_W { + U0_CDNS_QSPI_SCFG_SRAM_CONFIG_PTSEL_W::new(self, 4) } #[doc = "Bits 6:7 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_cdns_qspi_scfg_sram_config_trb( &mut self, - ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_TRB_W { - U0_CDNS_QSPI_SCFG_SRAM_CONFIG_TRB_W::new(self) + ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_TRB_W { + U0_CDNS_QSPI_SCFG_SRAM_CONFIG_TRB_W::new(self, 6) } #[doc = "Bits 8:9 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_cdns_qspi_scfg_sram_config_wtsel( &mut self, - ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_WTSEL_W { - U0_CDNS_QSPI_SCFG_SRAM_CONFIG_WTSEL_W::new(self) + ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_WTSEL_W { + U0_CDNS_QSPI_SCFG_SRAM_CONFIG_WTSEL_W::new(self, 8) } #[doc = "Bit 10 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_cdns_qspi_scfg_sram_config_vs( &mut self, - ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VS_W { - U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VS_W::new(self) + ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VS_W { + U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VS_W::new(self, 10) } #[doc = "Bit 11 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_cdns_qspi_scfg_sram_config_vg( &mut self, - ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VG_W { - U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VG_W::new(self) + ) -> U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VG_W { + U0_CDNS_QSPI_SCFG_SRAM_CONFIG_VG_W::new(self, 11) } #[doc = "Bit 12 - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_cdns_spdif_scfg_sram_config_slp( &mut self, - ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SLP_W { - U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SLP_W::new(self) + ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SLP_W { + U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SLP_W::new(self, 12) } #[doc = "Bit 13 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_cdns_spdif_scfg_sram_config_sram_config_sd( &mut self, - ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W { - U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self) + ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W { + U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self, 13) } #[doc = "Bits 14:15 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_cdns_spdif_scfg_sram_config_rtsel( &mut self, - ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_RTSEL_W { - U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_RTSEL_W::new(self) + ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_RTSEL_W { + U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_RTSEL_W::new(self, 14) } #[doc = "Bits 16:17 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_cdns_spdif_scfg_sram_config_ptsel( &mut self, - ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_PTSEL_W { - U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_PTSEL_W::new(self) + ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_PTSEL_W { + U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_PTSEL_W::new(self, 16) } #[doc = "Bits 18:19 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_cdns_spdif_scfg_sram_config_trb( &mut self, - ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_TRB_W { - U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_TRB_W::new(self) + ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_TRB_W { + U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_TRB_W::new(self, 18) } #[doc = "Bits 20:21 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_cdns_spdif_scfg_sram_config_wtsel( &mut self, - ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_WTSEL_W { - U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_WTSEL_W::new(self) + ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_WTSEL_W { + U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_WTSEL_W::new(self, 20) } #[doc = "Bit 22 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_cdns_spdif_scfg_sram_config_vs( &mut self, - ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VS_W { - U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VS_W::new(self) + ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VS_W { + U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VS_W::new(self, 22) } #[doc = "Bit 23 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_cdns_spdif_scfg_sram_config_vg( &mut self, - ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VG_W { - U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VG_W::new(self) + ) -> U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VG_W { + U0_CDNS_SPDIF_SCFG_SRAM_CONFIG_VG_W::new(self, 23) } #[doc = "Bits 26:30 - Data strobe delay chain select"] #[inline(always)] #[must_use] pub fn u0_sdio_data_strobe_phase_ctrl( &mut self, - ) -> U0_SDIO_DATA_STROBE_PHASE_CTRL_W { - U0_SDIO_DATA_STROBE_PHASE_CTRL_W::new(self) + ) -> U0_SDIO_DATA_STROBE_PHASE_CTRL_W { + U0_SDIO_DATA_STROBE_PHASE_CTRL_W::new(self, 26) } #[doc = "Bit 31 - AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] #[inline(always)] #[must_use] - pub fn u0_sdio_hbig_endian( - &mut self, - ) -> U0_SDIO_HBIG_ENDIAN_W { - U0_SDIO_HBIG_ENDIAN_W::new(self) - } - #[doc = "Writes raw bits to the register."] + pub fn u0_sdio_hbig_endian(&mut self) -> U0_SDIO_HBIG_ENDIAN_W { + U0_SDIO_HBIG_ENDIAN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg24.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg24.rs index a290cdf..5cc5c44 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg24.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg24.rs @@ -5,80 +5,75 @@ pub type W = crate::W; #[doc = "Field `u0_sdio_m_hbig_endian` reader - AHB master bus interface endianess: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] pub type U0_SDIO_M_HBIG_ENDIAN_R = crate::BitReader; #[doc = "Field `u0_sdio_m_hbig_endian` writer - AHB master bus interface endianess: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] -pub type U0_SDIO_M_HBIG_ENDIAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_SDIO_M_HBIG_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_i2srx_3ch_adc_ena` reader - u0_i2srx_3ch_adc_ena"] pub type U0_I2SRX_3CH_ADC_ENA_R = crate::BitReader; #[doc = "Field `u0_i2srx_3ch_adc_ena` writer - u0_i2srx_3ch_adc_ena"] -pub type U0_I2SRX_3CH_ADC_ENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_I2SRX_3CH_ADC_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_intmem_rom_sram_scfg_disable_rom` reader - u0_intmem_rom_sram_scfg_disable_rom"] pub type U0_INTMEM_ROM_SRAM_SCFG_DISABLE_ROM_R = crate::BitReader; #[doc = "Field `u0_intmem_rom_sram_scfg_disable_rom` writer - u0_intmem_rom_sram_scfg_disable_rom"] -pub type U0_INTMEM_ROM_SRAM_SCFG_DISABLE_ROM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_INTMEM_ROM_SRAM_SCFG_DISABLE_ROM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_intmem_rom_sram_sram_config_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SLP_R = crate::BitReader; #[doc = "Field `u0_intmem_rom_sram_sram_config_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] -pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_intmem_rom_sram_sram_config_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SRAM_CONFIG_SD_R = crate::BitReader; #[doc = "Field `u0_intmem_rom_sram_sram_config_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] -pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_intmem_rom_sram_sram_config_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_RTSEL_R = crate::FieldReader; #[doc = "Field `u0_intmem_rom_sram_sram_config_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_RTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_intmem_rom_sram_sram_config_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_PTSEL_R = crate::FieldReader; #[doc = "Field `u0_intmem_rom_sram_sram_config_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_PTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_intmem_rom_sram_sram_config_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_TRB_R = crate::FieldReader; #[doc = "Field `u0_intmem_rom_sram_sram_config_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] -pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_TRB_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_intmem_rom_sram_sram_config_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_WTSEL_R = crate::FieldReader; #[doc = "Field `u0_intmem_rom_sram_sram_config_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] -pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_WTSEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 2, O>; +pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_intmem_rom_sram_sram_config_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VS_R = crate::BitReader; #[doc = "Field `u0_intmem_rom_sram_sram_config_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] -pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_intmem_rom_sram_sram_config_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VG_R = crate::BitReader; #[doc = "Field `u0_intmem_rom_sram_sram_config_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] -pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VG_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_jtag_daisy_chain_jtag_en_0` reader - u0_jtag_daisy_chain_jtag_en_0"] pub type U0_JTAG_DAISY_CHAIN_JTAG_EN_0_R = crate::BitReader; #[doc = "Field `u0_jtag_daisy_chain_jtag_en_0` writer - u0_jtag_daisy_chain_jtag_en_0"] -pub type U0_JTAG_DAISY_CHAIN_JTAG_EN_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_JTAG_DAISY_CHAIN_JTAG_EN_0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_jtag_daisy_chain_jtag_en_1` reader - u0_jtag_daisy_chain_jtag_en_1"] pub type U0_JTAG_DAISY_CHAIN_JTAG_EN_1_R = crate::BitReader; #[doc = "Field `u0_jtag_daisy_chain_jtag_en_1` writer - u0_jtag_daisy_chain_jtag_en_1"] -pub type U0_JTAG_DAISY_CHAIN_JTAG_EN_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_JTAG_DAISY_CHAIN_JTAG_EN_1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pdrstn_split_sw_usbpipe_plugen` reader - u0_pdrstn_split_sw_usbpipe_plugen"] pub type U0_PDRSTN_SPLIT_SW_USBPIPE_PLUGEN_R = crate::BitReader; #[doc = "Field `u0_pdrstn_split_sw_usbpipe_plugen` writer - u0_pdrstn_split_sw_usbpipe_plugen"] -pub type U0_PDRSTN_SPLIT_SW_USBPIPE_PLUGEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PDRSTN_SPLIT_SW_USBPIPE_PLUGEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll0_cpi_bias` reader - u0_pll_wrap_pll0_cpi_bias"] pub type U0_PLL_WRAP_PLL0_CPI_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_cpi_bias` writer - u0_pll_wrap_pll0_cpi_bias"] -pub type U0_PLL_WRAP_PLL0_CPI_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U0_PLL_WRAP_PLL0_CPI_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_pll_wrap_pll0_cpp_bias` reader - u0_pll_wrap_pll0_cpp_bias"] pub type U0_PLL_WRAP_PLL0_CPP_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_cpp_bias` writer - u0_pll_wrap_pll0_cpp_bias"] -pub type U0_PLL_WRAP_PLL0_CPP_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U0_PLL_WRAP_PLL0_CPP_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_pll_wrap_pll0_dacpd` reader - u0_pll_wrap_pll0_dacpd"] pub type U0_PLL_WRAP_PLL0_DACPD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll0_dacpd` writer - u0_pll_wrap_pll0_dacpd"] -pub type U0_PLL_WRAP_PLL0_DACPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL0_DACPD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll0_dsmpd` reader - u0_pll_wrap_pll0_dsmpd"] pub type U0_PLL_WRAP_PLL0_DSMPD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll0_dsmpd` writer - u0_pll_wrap_pll0_dsmpd"] -pub type U0_PLL_WRAP_PLL0_DSMPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL0_DSMPD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - AHB master bus interface endianess: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface"] #[inline(always)] @@ -179,146 +174,148 @@ impl W { #[must_use] pub fn u0_sdio_m_hbig_endian( &mut self, - ) -> U0_SDIO_M_HBIG_ENDIAN_W { - U0_SDIO_M_HBIG_ENDIAN_W::new(self) + ) -> U0_SDIO_M_HBIG_ENDIAN_W { + U0_SDIO_M_HBIG_ENDIAN_W::new(self, 0) } #[doc = "Bit 1 - u0_i2srx_3ch_adc_ena"] #[inline(always)] #[must_use] - pub fn u0_i2srx_3ch_adc_ena( - &mut self, - ) -> U0_I2SRX_3CH_ADC_ENA_W { - U0_I2SRX_3CH_ADC_ENA_W::new(self) + pub fn u0_i2srx_3ch_adc_ena(&mut self) -> U0_I2SRX_3CH_ADC_ENA_W { + U0_I2SRX_3CH_ADC_ENA_W::new(self, 1) } #[doc = "Bit 2 - u0_intmem_rom_sram_scfg_disable_rom"] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_scfg_disable_rom( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SCFG_DISABLE_ROM_W { - U0_INTMEM_ROM_SRAM_SCFG_DISABLE_ROM_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SCFG_DISABLE_ROM_W { + U0_INTMEM_ROM_SRAM_SCFG_DISABLE_ROM_W::new(self, 2) } #[doc = "Bit 3 - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_sram_config_slp( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SLP_W { - U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SLP_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SLP_W { + U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SLP_W::new(self, 3) } #[doc = "Bit 4 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_sram_config_sram_config_sd( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W { - U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W { + U0_INTMEM_ROM_SRAM_SRAM_CONFIG_SRAM_CONFIG_SD_W::new(self, 4) } #[doc = "Bits 5:6 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_sram_config_rtsel( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_RTSEL_W { - U0_INTMEM_ROM_SRAM_SRAM_CONFIG_RTSEL_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_RTSEL_W { + U0_INTMEM_ROM_SRAM_SRAM_CONFIG_RTSEL_W::new(self, 5) } #[doc = "Bits 7:8 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_sram_config_ptsel( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_PTSEL_W { - U0_INTMEM_ROM_SRAM_SRAM_CONFIG_PTSEL_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_PTSEL_W { + U0_INTMEM_ROM_SRAM_SRAM_CONFIG_PTSEL_W::new(self, 7) } #[doc = "Bits 9:10 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_sram_config_trb( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_TRB_W { - U0_INTMEM_ROM_SRAM_SRAM_CONFIG_TRB_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_TRB_W { + U0_INTMEM_ROM_SRAM_SRAM_CONFIG_TRB_W::new(self, 9) } #[doc = "Bits 11:12 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_sram_config_wtsel( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_WTSEL_W { - U0_INTMEM_ROM_SRAM_SRAM_CONFIG_WTSEL_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_WTSEL_W { + U0_INTMEM_ROM_SRAM_SRAM_CONFIG_WTSEL_W::new(self, 11) } #[doc = "Bit 13 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_sram_config_vs( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VS_W { - U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VS_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VS_W { + U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VS_W::new(self, 13) } #[doc = "Bit 14 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."] #[inline(always)] #[must_use] pub fn u0_intmem_rom_sram_sram_config_vg( &mut self, - ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VG_W { - U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VG_W::new(self) + ) -> U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VG_W { + U0_INTMEM_ROM_SRAM_SRAM_CONFIG_VG_W::new(self, 14) } #[doc = "Bit 15 - u0_jtag_daisy_chain_jtag_en_0"] #[inline(always)] #[must_use] pub fn u0_jtag_daisy_chain_jtag_en_0( &mut self, - ) -> U0_JTAG_DAISY_CHAIN_JTAG_EN_0_W { - U0_JTAG_DAISY_CHAIN_JTAG_EN_0_W::new(self) + ) -> U0_JTAG_DAISY_CHAIN_JTAG_EN_0_W { + U0_JTAG_DAISY_CHAIN_JTAG_EN_0_W::new(self, 15) } #[doc = "Bit 16 - u0_jtag_daisy_chain_jtag_en_1"] #[inline(always)] #[must_use] pub fn u0_jtag_daisy_chain_jtag_en_1( &mut self, - ) -> U0_JTAG_DAISY_CHAIN_JTAG_EN_1_W { - U0_JTAG_DAISY_CHAIN_JTAG_EN_1_W::new(self) + ) -> U0_JTAG_DAISY_CHAIN_JTAG_EN_1_W { + U0_JTAG_DAISY_CHAIN_JTAG_EN_1_W::new(self, 16) } #[doc = "Bit 17 - u0_pdrstn_split_sw_usbpipe_plugen"] #[inline(always)] #[must_use] pub fn u0_pdrstn_split_sw_usbpipe_plugen( &mut self, - ) -> U0_PDRSTN_SPLIT_SW_USBPIPE_PLUGEN_W { - U0_PDRSTN_SPLIT_SW_USBPIPE_PLUGEN_W::new(self) + ) -> U0_PDRSTN_SPLIT_SW_USBPIPE_PLUGEN_W { + U0_PDRSTN_SPLIT_SW_USBPIPE_PLUGEN_W::new(self, 17) } #[doc = "Bits 18:20 - u0_pll_wrap_pll0_cpi_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_cpi_bias( &mut self, - ) -> U0_PLL_WRAP_PLL0_CPI_BIAS_W { - U0_PLL_WRAP_PLL0_CPI_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL0_CPI_BIAS_W { + U0_PLL_WRAP_PLL0_CPI_BIAS_W::new(self, 18) } #[doc = "Bits 21:23 - u0_pll_wrap_pll0_cpp_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_cpp_bias( &mut self, - ) -> U0_PLL_WRAP_PLL0_CPP_BIAS_W { - U0_PLL_WRAP_PLL0_CPP_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL0_CPP_BIAS_W { + U0_PLL_WRAP_PLL0_CPP_BIAS_W::new(self, 21) } #[doc = "Bit 24 - u0_pll_wrap_pll0_dacpd"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_dacpd( &mut self, - ) -> U0_PLL_WRAP_PLL0_DACPD_W { - U0_PLL_WRAP_PLL0_DACPD_W::new(self) + ) -> U0_PLL_WRAP_PLL0_DACPD_W { + U0_PLL_WRAP_PLL0_DACPD_W::new(self, 24) } #[doc = "Bit 25 - u0_pll_wrap_pll0_dsmpd"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_dsmpd( &mut self, - ) -> U0_PLL_WRAP_PLL0_DSMPD_W { - U0_PLL_WRAP_PLL0_DSMPD_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_PLL_WRAP_PLL0_DSMPD_W { + U0_PLL_WRAP_PLL0_DSMPD_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg28.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg28.rs index 8506aef..e1ca1b3 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg28.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg28.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `u0_pll_wrap_pll0_fbdiv` reader - u0_pll_wrap_pll0_fbdiv"] pub type U0_PLL_WRAP_PLL0_FBDIV_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_fbdiv` writer - u0_pll_wrap_pll0_fbdiv"] -pub type U0_PLL_WRAP_PLL0_FBDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; +pub type U0_PLL_WRAP_PLL0_FBDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; impl R { #[doc = "Bits 0:11 - u0_pll_wrap_pll0_fbdiv"] #[inline(always)] @@ -19,10 +19,14 @@ impl W { #[must_use] pub fn u0_pll_wrap_pll0_fbdiv( &mut self, - ) -> U0_PLL_WRAP_PLL0_FBDIV_W { - U0_PLL_WRAP_PLL0_FBDIV_W::new(self) + ) -> U0_PLL_WRAP_PLL0_FBDIV_W { + U0_PLL_WRAP_PLL0_FBDIV_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg32.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg32.rs index 016cbee..9866f9c 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg32.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg32.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `u0_pll_wrap_pll0_frac` reader - u0_pll_wrap_pll0_frac"] pub type U0_PLL_WRAP_PLL0_FRAC_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_frac` writer - u0_pll_wrap_pll0_frac"] -pub type U0_PLL_WRAP_PLL0_FRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type U0_PLL_WRAP_PLL0_FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `u0_pll_wrap_pll0_gvco_bias` reader - u0_pll_wrap_pll0_gvco_bias"] pub type U0_PLL_WRAP_PLL0_GVCO_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_gvco_bias` writer - u0_pll_wrap_pll0_gvco_bias"] -pub type U0_PLL_WRAP_PLL0_GVCO_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL0_GVCO_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_pll0_lock` reader - u0_pll_wrap_pll0_lock"] pub type U0_PLL_WRAP_PLL0_LOCK_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll0_pd` reader - u0_pll_wrap_pll0_pd"] pub type U0_PLL_WRAP_PLL0_PD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll0_pd` writer - u0_pll_wrap_pll0_pd"] -pub type U0_PLL_WRAP_PLL0_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL0_PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll0_postdiv1` reader - u0_pll_wrap_pll0_postdiv1"] pub type U0_PLL_WRAP_PLL0_POSTDIV1_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_postdiv1` writer - u0_pll_wrap_pll0_postdiv1"] -pub type U0_PLL_WRAP_PLL0_POSTDIV1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL0_POSTDIV1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_pll0_postdiv2` reader - u0_pll_wrap_pll0_postdiv2"] pub type U0_PLL_WRAP_PLL0_POSTDIV2_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_postdiv2` writer - u0_pll_wrap_pll0_postdiv2"] -pub type U0_PLL_WRAP_PLL0_POSTDIV2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL0_POSTDIV2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:23 - u0_pll_wrap_pll0_frac"] #[inline(always)] @@ -62,42 +62,44 @@ impl W { #[must_use] pub fn u0_pll_wrap_pll0_frac( &mut self, - ) -> U0_PLL_WRAP_PLL0_FRAC_W { - U0_PLL_WRAP_PLL0_FRAC_W::new(self) + ) -> U0_PLL_WRAP_PLL0_FRAC_W { + U0_PLL_WRAP_PLL0_FRAC_W::new(self, 0) } #[doc = "Bits 24:25 - u0_pll_wrap_pll0_gvco_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_gvco_bias( &mut self, - ) -> U0_PLL_WRAP_PLL0_GVCO_BIAS_W { - U0_PLL_WRAP_PLL0_GVCO_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL0_GVCO_BIAS_W { + U0_PLL_WRAP_PLL0_GVCO_BIAS_W::new(self, 24) } #[doc = "Bit 27 - u0_pll_wrap_pll0_pd"] #[inline(always)] #[must_use] - pub fn u0_pll_wrap_pll0_pd( - &mut self, - ) -> U0_PLL_WRAP_PLL0_PD_W { - U0_PLL_WRAP_PLL0_PD_W::new(self) + pub fn u0_pll_wrap_pll0_pd(&mut self) -> U0_PLL_WRAP_PLL0_PD_W { + U0_PLL_WRAP_PLL0_PD_W::new(self, 27) } #[doc = "Bits 28:29 - u0_pll_wrap_pll0_postdiv1"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_postdiv1( &mut self, - ) -> U0_PLL_WRAP_PLL0_POSTDIV1_W { - U0_PLL_WRAP_PLL0_POSTDIV1_W::new(self) + ) -> U0_PLL_WRAP_PLL0_POSTDIV1_W { + U0_PLL_WRAP_PLL0_POSTDIV1_W::new(self, 28) } #[doc = "Bits 30:31 - u0_pll_wrap_pll0_postdiv2"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_postdiv2( &mut self, - ) -> U0_PLL_WRAP_PLL0_POSTDIV2_W { - U0_PLL_WRAP_PLL0_POSTDIV2_W::new(self) + ) -> U0_PLL_WRAP_PLL0_POSTDIV2_W { + U0_PLL_WRAP_PLL0_POSTDIV2_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg36.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg36.rs index 0cafa85..3a46591 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg36.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg36.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `u0_pll_wrap_pll0_prediv` reader - u0_pll_wrap_pll0_prediv"] pub type U0_PLL_WRAP_PLL0_PREDIV_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_prediv` writer - u0_pll_wrap_pll0_prediv"] -pub type U0_PLL_WRAP_PLL0_PREDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type U0_PLL_WRAP_PLL0_PREDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `u0_pll_wrap_pll0_testen` reader - u0_pll_wrap_pll0_testen"] pub type U0_PLL_WRAP_PLL0_TESTEN_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll0_testen` writer - u0_pll_wrap_pll0_testen"] -pub type U0_PLL_WRAP_PLL0_TESTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL0_TESTEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll0_testsel` reader - u0_pll_wrap_pll0_testsel"] pub type U0_PLL_WRAP_PLL0_TESTSEL_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll0_testsel` writer - u0_pll_wrap_pll0_testsel"] -pub type U0_PLL_WRAP_PLL0_TESTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL0_TESTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_pll1_cpi_bias` reader - u0_pll_wrap_pll1_cpi_bias"] pub type U0_PLL_WRAP_PLL1_CPI_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_cpi_bias` writer - u0_pll_wrap_pll1_cpi_bias"] -pub type U0_PLL_WRAP_PLL1_CPI_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U0_PLL_WRAP_PLL1_CPI_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_pll_wrap_pll1_cpp_bias` reader - u0_pll_wrap_pll1_cpp_bias"] pub type U0_PLL_WRAP_PLL1_CPP_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_cpp_bias` writer - u0_pll_wrap_pll1_cpp_bias"] -pub type U0_PLL_WRAP_PLL1_CPP_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U0_PLL_WRAP_PLL1_CPP_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_pll_wrap_pll1_dacpd` reader - u0_pll_wrap_pll1_dacpd"] pub type U0_PLL_WRAP_PLL1_DACPD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll1_dacpd` writer - u0_pll_wrap_pll1_dacpd"] -pub type U0_PLL_WRAP_PLL1_DACPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL1_DACPD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll1_dsmpd` reader - u0_pll_wrap_pll1_dsmpd"] pub type U0_PLL_WRAP_PLL1_DSMPD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll1_dsmpd` writer - u0_pll_wrap_pll1_dsmpd"] -pub type U0_PLL_WRAP_PLL1_DSMPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL1_DSMPD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll1_fbdiv` reader - u0_pll_wrap_pll1_fbdiv"] pub type U0_PLL_WRAP_PLL1_FBDIV_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_fbdiv` writer - u0_pll_wrap_pll1_fbdiv"] -pub type U0_PLL_WRAP_PLL1_FBDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; +pub type U0_PLL_WRAP_PLL1_FBDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; impl R { #[doc = "Bits 0:5 - u0_pll_wrap_pll0_prediv"] #[inline(always)] @@ -82,66 +82,70 @@ impl W { #[must_use] pub fn u0_pll_wrap_pll0_prediv( &mut self, - ) -> U0_PLL_WRAP_PLL0_PREDIV_W { - U0_PLL_WRAP_PLL0_PREDIV_W::new(self) + ) -> U0_PLL_WRAP_PLL0_PREDIV_W { + U0_PLL_WRAP_PLL0_PREDIV_W::new(self, 0) } #[doc = "Bit 6 - u0_pll_wrap_pll0_testen"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_testen( &mut self, - ) -> U0_PLL_WRAP_PLL0_TESTEN_W { - U0_PLL_WRAP_PLL0_TESTEN_W::new(self) + ) -> U0_PLL_WRAP_PLL0_TESTEN_W { + U0_PLL_WRAP_PLL0_TESTEN_W::new(self, 6) } #[doc = "Bits 7:8 - u0_pll_wrap_pll0_testsel"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll0_testsel( &mut self, - ) -> U0_PLL_WRAP_PLL0_TESTSEL_W { - U0_PLL_WRAP_PLL0_TESTSEL_W::new(self) + ) -> U0_PLL_WRAP_PLL0_TESTSEL_W { + U0_PLL_WRAP_PLL0_TESTSEL_W::new(self, 7) } #[doc = "Bits 9:11 - u0_pll_wrap_pll1_cpi_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_cpi_bias( &mut self, - ) -> U0_PLL_WRAP_PLL1_CPI_BIAS_W { - U0_PLL_WRAP_PLL1_CPI_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL1_CPI_BIAS_W { + U0_PLL_WRAP_PLL1_CPI_BIAS_W::new(self, 9) } #[doc = "Bits 12:14 - u0_pll_wrap_pll1_cpp_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_cpp_bias( &mut self, - ) -> U0_PLL_WRAP_PLL1_CPP_BIAS_W { - U0_PLL_WRAP_PLL1_CPP_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL1_CPP_BIAS_W { + U0_PLL_WRAP_PLL1_CPP_BIAS_W::new(self, 12) } #[doc = "Bit 15 - u0_pll_wrap_pll1_dacpd"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_dacpd( &mut self, - ) -> U0_PLL_WRAP_PLL1_DACPD_W { - U0_PLL_WRAP_PLL1_DACPD_W::new(self) + ) -> U0_PLL_WRAP_PLL1_DACPD_W { + U0_PLL_WRAP_PLL1_DACPD_W::new(self, 15) } #[doc = "Bit 16 - u0_pll_wrap_pll1_dsmpd"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_dsmpd( &mut self, - ) -> U0_PLL_WRAP_PLL1_DSMPD_W { - U0_PLL_WRAP_PLL1_DSMPD_W::new(self) + ) -> U0_PLL_WRAP_PLL1_DSMPD_W { + U0_PLL_WRAP_PLL1_DSMPD_W::new(self, 16) } #[doc = "Bits 17:28 - u0_pll_wrap_pll1_fbdiv"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_fbdiv( &mut self, - ) -> U0_PLL_WRAP_PLL1_FBDIV_W { - U0_PLL_WRAP_PLL1_FBDIV_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_PLL_WRAP_PLL1_FBDIV_W { + U0_PLL_WRAP_PLL1_FBDIV_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg4.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg4.rs index ec469be..6b0c18f 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg4.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg4.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `scfg_sd1_remap_awaddr` reader - scfg_sd1_remap_awaddr"] pub type SCFG_SD1_REMAP_AWADDR_R = crate::FieldReader; #[doc = "Field `scfg_sd1_remap_awaddr` writer - scfg_sd1_remap_awaddr"] -pub type SCFG_SD1_REMAP_AWADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_SD1_REMAP_AWADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_sec_haddr_remap` reader - scfg_sec_haddr_remap"] pub type SCFG_SEC_HADDR_REMAP_R = crate::FieldReader; #[doc = "Field `scfg_sec_haddr_remap` writer - scfg_sec_haddr_remap"] -pub type SCFG_SEC_HADDR_REMAP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_SEC_HADDR_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_usb_araddr_remap` reader - scfg_usb_araddr_remap"] pub type SCFG_USB_ARADDR_REMAP_R = crate::FieldReader; #[doc = "Field `scfg_usb_araddr_remap` writer - scfg_usb_araddr_remap"] -pub type SCFG_USB_ARADDR_REMAP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_USB_ARADDR_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_usb_awaddr_remap` reader - scfg_usb_awaddr_remap"] pub type SCFG_USB_AWADDR_REMAP_R = crate::FieldReader; #[doc = "Field `scfg_usb_awaddr_remap` writer - scfg_usb_awaddr_remap"] -pub type SCFG_USB_AWADDR_REMAP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_USB_AWADDR_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_vdec_remap_awaddr` reader - scfg_vdec_remap_awaddr"] pub type SCFG_VDEC_REMAP_AWADDR_R = crate::FieldReader; #[doc = "Field `scfg_vdec_remap_awaddr` writer - scfg_vdec_remap_awaddr"] -pub type SCFG_VDEC_REMAP_AWADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_VDEC_REMAP_AWADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_venc_remap_araddr` reader - scfg_venc_remap_araddr"] pub type SCFG_VENC_REMAP_ARADDR_R = crate::FieldReader; #[doc = "Field `scfg_venc_remap_araddr` writer - scfg_venc_remap_araddr"] -pub type SCFG_VENC_REMAP_ARADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_VENC_REMAP_ARADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_venc_remap_awaddr` reader - scfg_venc_remap_awaddr"] pub type SCFG_VENC_REMAP_AWADDR_R = crate::FieldReader; #[doc = "Field `scfg_venc_remap_awaddr` writer - scfg_venc_remap_awaddr"] -pub type SCFG_VENC_REMAP_AWADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_VENC_REMAP_AWADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_vout0_remap_araddr` reader - scfg_vout0_remap_araddr"] pub type SCFG_VOUT0_REMAP_ARADDR_R = crate::FieldReader; #[doc = "Field `scfg_vout0_remap_araddr` writer - scfg_vout0_remap_araddr"] -pub type SCFG_VOUT0_REMAP_ARADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_VOUT0_REMAP_ARADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - scfg_sd1_remap_awaddr"] #[inline(always)] @@ -82,66 +82,68 @@ impl W { #[must_use] pub fn scfg_sd1_remap_awaddr( &mut self, - ) -> SCFG_SD1_REMAP_AWADDR_W { - SCFG_SD1_REMAP_AWADDR_W::new(self) + ) -> SCFG_SD1_REMAP_AWADDR_W { + SCFG_SD1_REMAP_AWADDR_W::new(self, 0) } #[doc = "Bits 4:7 - scfg_sec_haddr_remap"] #[inline(always)] #[must_use] - pub fn scfg_sec_haddr_remap( - &mut self, - ) -> SCFG_SEC_HADDR_REMAP_W { - SCFG_SEC_HADDR_REMAP_W::new(self) + pub fn scfg_sec_haddr_remap(&mut self) -> SCFG_SEC_HADDR_REMAP_W { + SCFG_SEC_HADDR_REMAP_W::new(self, 4) } #[doc = "Bits 8:11 - scfg_usb_araddr_remap"] #[inline(always)] #[must_use] pub fn scfg_usb_araddr_remap( &mut self, - ) -> SCFG_USB_ARADDR_REMAP_W { - SCFG_USB_ARADDR_REMAP_W::new(self) + ) -> SCFG_USB_ARADDR_REMAP_W { + SCFG_USB_ARADDR_REMAP_W::new(self, 8) } #[doc = "Bits 12:15 - scfg_usb_awaddr_remap"] #[inline(always)] #[must_use] pub fn scfg_usb_awaddr_remap( &mut self, - ) -> SCFG_USB_AWADDR_REMAP_W { - SCFG_USB_AWADDR_REMAP_W::new(self) + ) -> SCFG_USB_AWADDR_REMAP_W { + SCFG_USB_AWADDR_REMAP_W::new(self, 12) } #[doc = "Bits 16:19 - scfg_vdec_remap_awaddr"] #[inline(always)] #[must_use] pub fn scfg_vdec_remap_awaddr( &mut self, - ) -> SCFG_VDEC_REMAP_AWADDR_W { - SCFG_VDEC_REMAP_AWADDR_W::new(self) + ) -> SCFG_VDEC_REMAP_AWADDR_W { + SCFG_VDEC_REMAP_AWADDR_W::new(self, 16) } #[doc = "Bits 20:23 - scfg_venc_remap_araddr"] #[inline(always)] #[must_use] pub fn scfg_venc_remap_araddr( &mut self, - ) -> SCFG_VENC_REMAP_ARADDR_W { - SCFG_VENC_REMAP_ARADDR_W::new(self) + ) -> SCFG_VENC_REMAP_ARADDR_W { + SCFG_VENC_REMAP_ARADDR_W::new(self, 20) } #[doc = "Bits 24:27 - scfg_venc_remap_awaddr"] #[inline(always)] #[must_use] pub fn scfg_venc_remap_awaddr( &mut self, - ) -> SCFG_VENC_REMAP_AWADDR_W { - SCFG_VENC_REMAP_AWADDR_W::new(self) + ) -> SCFG_VENC_REMAP_AWADDR_W { + SCFG_VENC_REMAP_AWADDR_W::new(self, 24) } #[doc = "Bits 28:31 - scfg_vout0_remap_araddr"] #[inline(always)] #[must_use] pub fn scfg_vout0_remap_araddr( &mut self, - ) -> SCFG_VOUT0_REMAP_ARADDR_W { - SCFG_VOUT0_REMAP_ARADDR_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> SCFG_VOUT0_REMAP_ARADDR_W { + SCFG_VOUT0_REMAP_ARADDR_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg40.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg40.rs index 94aa69a..d8a16eb 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg40.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg40.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `u0_pll_wrap_pll1_frac` reader - u0_pll_wrap_pll1_frac"] pub type U0_PLL_WRAP_PLL1_FRAC_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_frac` writer - u0_pll_wrap_pll1_frac"] -pub type U0_PLL_WRAP_PLL1_FRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type U0_PLL_WRAP_PLL1_FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `u0_pll_wrap_pll1_gvco_bias` reader - u0_pll_wrap_pll1_gvco_bias"] pub type U0_PLL_WRAP_PLL1_GVCO_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_gvco_bias` writer - u0_pll_wrap_pll1_gvco_bias"] -pub type U0_PLL_WRAP_PLL1_GVCO_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL1_GVCO_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_pll1_lock` reader - u0_pll_wrap_pll1_lock"] pub type U0_PLL_WRAP_PLL1_LOCK_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll1_pd` reader - u0_pll_wrap_pll1_pd"] pub type U0_PLL_WRAP_PLL1_PD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll1_pd` writer - u0_pll_wrap_pll1_pd"] -pub type U0_PLL_WRAP_PLL1_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL1_PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll1_postdiv1` reader - u0_pll_wrap_pll1_postdiv1"] pub type U0_PLL_WRAP_PLL1_POSTDIV1_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_postdiv1` writer - u0_pll_wrap_pll1_postdiv1"] -pub type U0_PLL_WRAP_PLL1_POSTDIV1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL1_POSTDIV1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_pll1_postdiv2` reader - u0_pll_wrap_pll1_postdiv2"] pub type U0_PLL_WRAP_PLL1_POSTDIV2_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_postdiv2` writer - u0_pll_wrap_pll1_postdiv2"] -pub type U0_PLL_WRAP_PLL1_POSTDIV2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL1_POSTDIV2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:23 - u0_pll_wrap_pll1_frac"] #[inline(always)] @@ -62,42 +62,44 @@ impl W { #[must_use] pub fn u0_pll_wrap_pll1_frac( &mut self, - ) -> U0_PLL_WRAP_PLL1_FRAC_W { - U0_PLL_WRAP_PLL1_FRAC_W::new(self) + ) -> U0_PLL_WRAP_PLL1_FRAC_W { + U0_PLL_WRAP_PLL1_FRAC_W::new(self, 0) } #[doc = "Bits 24:25 - u0_pll_wrap_pll1_gvco_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_gvco_bias( &mut self, - ) -> U0_PLL_WRAP_PLL1_GVCO_BIAS_W { - U0_PLL_WRAP_PLL1_GVCO_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL1_GVCO_BIAS_W { + U0_PLL_WRAP_PLL1_GVCO_BIAS_W::new(self, 24) } #[doc = "Bit 27 - u0_pll_wrap_pll1_pd"] #[inline(always)] #[must_use] - pub fn u0_pll_wrap_pll1_pd( - &mut self, - ) -> U0_PLL_WRAP_PLL1_PD_W { - U0_PLL_WRAP_PLL1_PD_W::new(self) + pub fn u0_pll_wrap_pll1_pd(&mut self) -> U0_PLL_WRAP_PLL1_PD_W { + U0_PLL_WRAP_PLL1_PD_W::new(self, 27) } #[doc = "Bits 28:29 - u0_pll_wrap_pll1_postdiv1"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_postdiv1( &mut self, - ) -> U0_PLL_WRAP_PLL1_POSTDIV1_W { - U0_PLL_WRAP_PLL1_POSTDIV1_W::new(self) + ) -> U0_PLL_WRAP_PLL1_POSTDIV1_W { + U0_PLL_WRAP_PLL1_POSTDIV1_W::new(self, 28) } #[doc = "Bits 30:31 - u0_pll_wrap_pll1_postdiv2"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_postdiv2( &mut self, - ) -> U0_PLL_WRAP_PLL1_POSTDIV2_W { - U0_PLL_WRAP_PLL1_POSTDIV2_W::new(self) + ) -> U0_PLL_WRAP_PLL1_POSTDIV2_W { + U0_PLL_WRAP_PLL1_POSTDIV2_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg44.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg44.rs index fec59da..b921ff3 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg44.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg44.rs @@ -5,35 +5,35 @@ pub type W = crate::W; #[doc = "Field `u0_pll_wrap_pll1_prediv` reader - u0_pll_wrap_pll1_prediv"] pub type U0_PLL_WRAP_PLL1_PREDIV_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_prediv` writer - u0_pll_wrap_pll1_prediv"] -pub type U0_PLL_WRAP_PLL1_PREDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type U0_PLL_WRAP_PLL1_PREDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `u0_pll_wrap_pll1_testen` reader - u0_pll_wrap_pll1_testen"] pub type U0_PLL_WRAP_PLL1_TESTEN_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll1_testen` writer - u0_pll_wrap_pll1_testen"] -pub type U0_PLL_WRAP_PLL1_TESTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL1_TESTEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll1_testsel` reader - u0_pll_wrap_pll1_testsel"] pub type U0_PLL_WRAP_PLL1_TESTSEL_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll1_testsel` writer - u0_pll_wrap_pll1_testsel"] -pub type U0_PLL_WRAP_PLL1_TESTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL1_TESTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_pll2_cpi_bias` reader - u0_pll_wrap_pll2_cpi_bias"] pub type U0_PLL_WRAP_PLL2_CPI_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_cpi_bias` writer - u0_pll_wrap_pll2_cpi_bias"] -pub type U0_PLL_WRAP_PLL2_CPI_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U0_PLL_WRAP_PLL2_CPI_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_pll_wrap_pll2_cpp_bias` reader - u0_pll_wrap_pll2_cpp_bias"] pub type U0_PLL_WRAP_PLL2_CPP_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_cpp_bias` writer - u0_pll_wrap_pll2_cpp_bias"] -pub type U0_PLL_WRAP_PLL2_CPP_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +pub type U0_PLL_WRAP_PLL2_CPP_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; #[doc = "Field `u0_pll_wrap_pll2_dacpd` reader - u0_pll_wrap_pll2_dacpd"] pub type U0_PLL_WRAP_PLL2_DACPD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll2_dacpd` writer - u0_pll_wrap_pll2_dacpd"] -pub type U0_PLL_WRAP_PLL2_DACPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL2_DACPD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll2_dsmpd` reader - u0_pll_wrap_pll2_dsmpd"] pub type U0_PLL_WRAP_PLL2_DSMPD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll2_dsmpd` writer - u0_pll_wrap_pll2_dsmpd"] -pub type U0_PLL_WRAP_PLL2_DSMPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL2_DSMPD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll2_fbdiv` reader - u0_pll_wrap_pll2_fbdiv"] pub type U0_PLL_WRAP_PLL2_FBDIV_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_fbdiv` writer - u0_pll_wrap_pll2_fbdiv"] -pub type U0_PLL_WRAP_PLL2_FBDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; +pub type U0_PLL_WRAP_PLL2_FBDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; impl R { #[doc = "Bits 0:5 - u0_pll_wrap_pll1_prediv"] #[inline(always)] @@ -82,66 +82,70 @@ impl W { #[must_use] pub fn u0_pll_wrap_pll1_prediv( &mut self, - ) -> U0_PLL_WRAP_PLL1_PREDIV_W { - U0_PLL_WRAP_PLL1_PREDIV_W::new(self) + ) -> U0_PLL_WRAP_PLL1_PREDIV_W { + U0_PLL_WRAP_PLL1_PREDIV_W::new(self, 0) } #[doc = "Bit 6 - u0_pll_wrap_pll1_testen"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_testen( &mut self, - ) -> U0_PLL_WRAP_PLL1_TESTEN_W { - U0_PLL_WRAP_PLL1_TESTEN_W::new(self) + ) -> U0_PLL_WRAP_PLL1_TESTEN_W { + U0_PLL_WRAP_PLL1_TESTEN_W::new(self, 6) } #[doc = "Bits 7:8 - u0_pll_wrap_pll1_testsel"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll1_testsel( &mut self, - ) -> U0_PLL_WRAP_PLL1_TESTSEL_W { - U0_PLL_WRAP_PLL1_TESTSEL_W::new(self) + ) -> U0_PLL_WRAP_PLL1_TESTSEL_W { + U0_PLL_WRAP_PLL1_TESTSEL_W::new(self, 7) } #[doc = "Bits 9:11 - u0_pll_wrap_pll2_cpi_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_cpi_bias( &mut self, - ) -> U0_PLL_WRAP_PLL2_CPI_BIAS_W { - U0_PLL_WRAP_PLL2_CPI_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL2_CPI_BIAS_W { + U0_PLL_WRAP_PLL2_CPI_BIAS_W::new(self, 9) } #[doc = "Bits 12:14 - u0_pll_wrap_pll2_cpp_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_cpp_bias( &mut self, - ) -> U0_PLL_WRAP_PLL2_CPP_BIAS_W { - U0_PLL_WRAP_PLL2_CPP_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL2_CPP_BIAS_W { + U0_PLL_WRAP_PLL2_CPP_BIAS_W::new(self, 12) } #[doc = "Bit 15 - u0_pll_wrap_pll2_dacpd"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_dacpd( &mut self, - ) -> U0_PLL_WRAP_PLL2_DACPD_W { - U0_PLL_WRAP_PLL2_DACPD_W::new(self) + ) -> U0_PLL_WRAP_PLL2_DACPD_W { + U0_PLL_WRAP_PLL2_DACPD_W::new(self, 15) } #[doc = "Bit 16 - u0_pll_wrap_pll2_dsmpd"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_dsmpd( &mut self, - ) -> U0_PLL_WRAP_PLL2_DSMPD_W { - U0_PLL_WRAP_PLL2_DSMPD_W::new(self) + ) -> U0_PLL_WRAP_PLL2_DSMPD_W { + U0_PLL_WRAP_PLL2_DSMPD_W::new(self, 16) } #[doc = "Bits 17:28 - u0_pll_wrap_pll2_fbdiv"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_fbdiv( &mut self, - ) -> U0_PLL_WRAP_PLL2_FBDIV_W { - U0_PLL_WRAP_PLL2_FBDIV_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_PLL_WRAP_PLL2_FBDIV_W { + U0_PLL_WRAP_PLL2_FBDIV_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg48.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg48.rs index afbc5f1..5f098de 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg48.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg48.rs @@ -5,25 +5,25 @@ pub type W = crate::W; #[doc = "Field `u0_pll_wrap_pll2_frac` reader - u0_pll_wrap_pll2_frac"] pub type U0_PLL_WRAP_PLL2_FRAC_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_frac` writer - u0_pll_wrap_pll2_frac"] -pub type U0_PLL_WRAP_PLL2_FRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type U0_PLL_WRAP_PLL2_FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `u0_pll_wrap_pll2_gvco_bias` reader - u0_pll_wrap_pll2_gvco_bias"] pub type U0_PLL_WRAP_PLL2_GVCO_BIAS_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_gvco_bias` writer - u0_pll_wrap_pll2_gvco_bias"] -pub type U0_PLL_WRAP_PLL2_GVCO_BIAS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL2_GVCO_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_pll2_lock` reader - u0_pll_wrap_pll2_lock"] pub type U0_PLL_WRAP_PLL2_LOCK_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll2_pd` reader - u0_pll_wrap_pll2_pd"] pub type U0_PLL_WRAP_PLL2_PD_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll2_pd` writer - u0_pll_wrap_pll2_pd"] -pub type U0_PLL_WRAP_PLL2_PD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL2_PD_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll2_postdiv1` reader - u0_pll_wrap_pll2_postdiv1"] pub type U0_PLL_WRAP_PLL2_POSTDIV1_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_postdiv1` writer - u0_pll_wrap_pll2_postdiv1"] -pub type U0_PLL_WRAP_PLL2_POSTDIV1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL2_POSTDIV1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_pll2_postdiv2` reader - u0_pll_wrap_pll2_postdiv2"] pub type U0_PLL_WRAP_PLL2_POSTDIV2_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_postdiv2` writer - u0_pll_wrap_pll2_postdiv2"] -pub type U0_PLL_WRAP_PLL2_POSTDIV2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL2_POSTDIV2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:23 - u0_pll_wrap_pll2_frac"] #[inline(always)] @@ -62,42 +62,44 @@ impl W { #[must_use] pub fn u0_pll_wrap_pll2_frac( &mut self, - ) -> U0_PLL_WRAP_PLL2_FRAC_W { - U0_PLL_WRAP_PLL2_FRAC_W::new(self) + ) -> U0_PLL_WRAP_PLL2_FRAC_W { + U0_PLL_WRAP_PLL2_FRAC_W::new(self, 0) } #[doc = "Bits 24:25 - u0_pll_wrap_pll2_gvco_bias"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_gvco_bias( &mut self, - ) -> U0_PLL_WRAP_PLL2_GVCO_BIAS_W { - U0_PLL_WRAP_PLL2_GVCO_BIAS_W::new(self) + ) -> U0_PLL_WRAP_PLL2_GVCO_BIAS_W { + U0_PLL_WRAP_PLL2_GVCO_BIAS_W::new(self, 24) } #[doc = "Bit 27 - u0_pll_wrap_pll2_pd"] #[inline(always)] #[must_use] - pub fn u0_pll_wrap_pll2_pd( - &mut self, - ) -> U0_PLL_WRAP_PLL2_PD_W { - U0_PLL_WRAP_PLL2_PD_W::new(self) + pub fn u0_pll_wrap_pll2_pd(&mut self) -> U0_PLL_WRAP_PLL2_PD_W { + U0_PLL_WRAP_PLL2_PD_W::new(self, 27) } #[doc = "Bits 28:29 - u0_pll_wrap_pll2_postdiv1"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_postdiv1( &mut self, - ) -> U0_PLL_WRAP_PLL2_POSTDIV1_W { - U0_PLL_WRAP_PLL2_POSTDIV1_W::new(self) + ) -> U0_PLL_WRAP_PLL2_POSTDIV1_W { + U0_PLL_WRAP_PLL2_POSTDIV1_W::new(self, 28) } #[doc = "Bits 30:31 - u0_pll_wrap_pll2_postdiv2"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_postdiv2( &mut self, - ) -> U0_PLL_WRAP_PLL2_POSTDIV2_W { - U0_PLL_WRAP_PLL2_POSTDIV2_W::new(self) + ) -> U0_PLL_WRAP_PLL2_POSTDIV2_W { + U0_PLL_WRAP_PLL2_POSTDIV2_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg52.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg52.rs index ed93b66..a542c31 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg52.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg52.rs @@ -5,75 +5,67 @@ pub type W = crate::W; #[doc = "Field `u0_pll_wrap_pll2_prediv` reader - u0_pll_wrap_pll2_prediv"] pub type U0_PLL_WRAP_PLL2_PREDIV_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_prediv` writer - u0_pll_wrap_pll2_prediv"] -pub type U0_PLL_WRAP_PLL2_PREDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type U0_PLL_WRAP_PLL2_PREDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `u0_pll_wrap_pll2_testen` reader - u0_pll_wrap_pll2_testen"] pub type U0_PLL_WRAP_PLL2_TESTEN_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_pll2_testen` writer - u0_pll_wrap_pll2_testen"] -pub type U0_PLL_WRAP_PLL2_TESTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_PLL2_TESTEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_pll_wrap_pll2_testsel` reader - u0_pll_wrap_pll2_testsel"] pub type U0_PLL_WRAP_PLL2_TESTSEL_R = crate::FieldReader; #[doc = "Field `u0_pll_wrap_pll2_testsel` writer - u0_pll_wrap_pll2_testsel"] -pub type U0_PLL_WRAP_PLL2_TESTSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type U0_PLL_WRAP_PLL2_TESTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `u0_pll_wrap_syscfg_test_pll_mode` reader - PLL test mode, only used for PLL BIST through jtag2apb"] pub type U0_PLL_WRAP_SYSCFG_TEST_PLL_MODE_R = crate::BitReader; #[doc = "Field `u0_pll_wrap_syscfg_test_pll_mode` writer - PLL test mode, only used for PLL BIST through jtag2apb"] -pub type U0_PLL_WRAP_SYSCFG_TEST_PLL_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_PLL_WRAP_SYSCFG_TEST_PLL_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_saif_audio_sdin_mux_scfg_i2sdin_sel` reader - u0_saif_audio_sdin_mux_scfg_i2sdin_sel"] pub type U0_SAIF_AUDIO_SDIN_MUX_SCFG_I2SDIN_SEL_R = crate::FieldReader; #[doc = "Field `u0_saif_audio_sdin_mux_scfg_i2sdin_sel` writer - u0_saif_audio_sdin_mux_scfg_i2sdin_sel"] -pub type U0_SAIF_AUDIO_SDIN_MUX_SCFG_I2SDIN_SEL_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 8, O>; +pub type U0_SAIF_AUDIO_SDIN_MUX_SCFG_I2SDIN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `u0_sft7110_noc_bus_clock_gating_off` reader - u0_sft7110_noc_bus_clock_gating_off"] pub type U0_SFT7110_NOC_BUS_CLOCK_GATING_OFF_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_clock_gating_off` writer - u0_sft7110_noc_bus_clock_gating_off"] -pub type U0_SFT7110_NOC_BUS_CLOCK_GATING_OFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_CLOCK_GATING_OFF_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_0_start` reader - u0_sft7110_noc_bus_oic_evemon_0_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_0_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_0_start` writer - u0_sft7110_noc_bus_oic_evemon_0_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_0_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_0_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_0_trigger` reader - u0_sft7110_noc_bus_oic_evemon_0_trigger"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_0_TRIGGER_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_1_start` reader - u0_sft7110_noc_bus_oic_evemon_1_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_1_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_1_start` writer - u0_sft7110_noc_bus_oic_evemon_1_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_1_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_1_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_1_trigger` reader - u0_sft7110_noc_bus_oic_evemon_1_trigger"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_1_TRIGGER_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_2_start` reader - u0_sft7110_noc_bus_oic_evemon_2_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_2_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_2_start` writer - u0_sft7110_noc_bus_oic_evemon_2_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_2_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_2_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_2_trigger` reader - u0_sft7110_noc_bus_oic_evemon_2_trigger"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_2_TRIGGER_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_3_start` reader - u0_sft7110_noc_bus_oic_evemon_3_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_3_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_3_start` writer - u0_sft7110_noc_bus_oic_evemon_3_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_3_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_3_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_3_trigger` reader - u0_sft7110_noc_bus_oic_evemon_3_trigger"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_3_TRIGGER_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_4_start` reader - u0_sft7110_noc_bus_oic_evemon_4_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_4_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_4_start` writer - u0_sft7110_noc_bus_oic_evemon_4_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_4_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_4_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_4_trigger` reader - u0_sft7110_noc_bus_oic_evemon_4_trigger"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_4_TRIGGER_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_5_start` reader - u0_sft7110_noc_bus_oic_evemon_5_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_5_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_5_start` writer - u0_sft7110_noc_bus_oic_evemon_5_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_5_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_5_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_5_trigger` reader - u0_sft7110_noc_bus_oic_evemon_5_trigger"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_5_TRIGGER_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_6_start` reader - u0_sft7110_noc_bus_oic_evemon_6_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_6_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_6_start` writer - u0_sft7110_noc_bus_oic_evemon_6_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_6_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_6_START_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:5 - u0_pll_wrap_pll2_prediv"] #[inline(always)] @@ -191,106 +183,110 @@ impl W { #[must_use] pub fn u0_pll_wrap_pll2_prediv( &mut self, - ) -> U0_PLL_WRAP_PLL2_PREDIV_W { - U0_PLL_WRAP_PLL2_PREDIV_W::new(self) + ) -> U0_PLL_WRAP_PLL2_PREDIV_W { + U0_PLL_WRAP_PLL2_PREDIV_W::new(self, 0) } #[doc = "Bit 6 - u0_pll_wrap_pll2_testen"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_testen( &mut self, - ) -> U0_PLL_WRAP_PLL2_TESTEN_W { - U0_PLL_WRAP_PLL2_TESTEN_W::new(self) + ) -> U0_PLL_WRAP_PLL2_TESTEN_W { + U0_PLL_WRAP_PLL2_TESTEN_W::new(self, 6) } #[doc = "Bits 7:8 - u0_pll_wrap_pll2_testsel"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_pll2_testsel( &mut self, - ) -> U0_PLL_WRAP_PLL2_TESTSEL_W { - U0_PLL_WRAP_PLL2_TESTSEL_W::new(self) + ) -> U0_PLL_WRAP_PLL2_TESTSEL_W { + U0_PLL_WRAP_PLL2_TESTSEL_W::new(self, 7) } #[doc = "Bit 9 - PLL test mode, only used for PLL BIST through jtag2apb"] #[inline(always)] #[must_use] pub fn u0_pll_wrap_syscfg_test_pll_mode( &mut self, - ) -> U0_PLL_WRAP_SYSCFG_TEST_PLL_MODE_W { - U0_PLL_WRAP_SYSCFG_TEST_PLL_MODE_W::new(self) + ) -> U0_PLL_WRAP_SYSCFG_TEST_PLL_MODE_W { + U0_PLL_WRAP_SYSCFG_TEST_PLL_MODE_W::new(self, 9) } #[doc = "Bits 10:17 - u0_saif_audio_sdin_mux_scfg_i2sdin_sel"] #[inline(always)] #[must_use] pub fn u0_saif_audio_sdin_mux_scfg_i2sdin_sel( &mut self, - ) -> U0_SAIF_AUDIO_SDIN_MUX_SCFG_I2SDIN_SEL_W { - U0_SAIF_AUDIO_SDIN_MUX_SCFG_I2SDIN_SEL_W::new(self) + ) -> U0_SAIF_AUDIO_SDIN_MUX_SCFG_I2SDIN_SEL_W { + U0_SAIF_AUDIO_SDIN_MUX_SCFG_I2SDIN_SEL_W::new(self, 10) } #[doc = "Bit 18 - u0_sft7110_noc_bus_clock_gating_off"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_clock_gating_off( &mut self, - ) -> U0_SFT7110_NOC_BUS_CLOCK_GATING_OFF_W { - U0_SFT7110_NOC_BUS_CLOCK_GATING_OFF_W::new(self) + ) -> U0_SFT7110_NOC_BUS_CLOCK_GATING_OFF_W { + U0_SFT7110_NOC_BUS_CLOCK_GATING_OFF_W::new(self, 18) } #[doc = "Bit 19 - u0_sft7110_noc_bus_oic_evemon_0_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_0_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_0_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_0_START_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_0_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_0_START_W::new(self, 19) } #[doc = "Bit 21 - u0_sft7110_noc_bus_oic_evemon_1_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_1_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_1_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_1_START_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_1_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_1_START_W::new(self, 21) } #[doc = "Bit 23 - u0_sft7110_noc_bus_oic_evemon_2_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_2_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_2_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_2_START_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_2_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_2_START_W::new(self, 23) } #[doc = "Bit 25 - u0_sft7110_noc_bus_oic_evemon_3_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_3_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_3_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_3_START_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_3_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_3_START_W::new(self, 25) } #[doc = "Bit 27 - u0_sft7110_noc_bus_oic_evemon_4_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_4_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_4_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_4_START_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_4_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_4_START_W::new(self, 27) } #[doc = "Bit 29 - u0_sft7110_noc_bus_oic_evemon_5_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_5_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_5_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_5_START_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_5_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_5_START_W::new(self, 29) } #[doc = "Bit 31 - u0_sft7110_noc_bus_oic_evemon_6_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_6_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_6_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_6_START_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_6_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_6_START_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg56.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg56.rs index a1ceebe..f637eb8 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg56.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg56.rs @@ -7,40 +7,33 @@ pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_6_TRIGGER_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_0` reader - u0_sft7110_noc_bus_oic_ignore_modifiable_0"] pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_0_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_0` writer - u0_sft7110_noc_bus_oic_ignore_modifiable_0"] -pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_0_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_1` reader - u0_sft7110_noc_bus_oic_ignore_modifiable_1"] pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_1_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_1` writer - u0_sft7110_noc_bus_oic_ignore_modifiable_1"] -pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_1_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_2` reader - u0_sft7110_noc_bus_oic_ignore_modifiable_2"] pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_2_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_2` writer - u0_sft7110_noc_bus_oic_ignore_modifiable_2"] -pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_2_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_3` reader - u0_sft7110_noc_bus_oic_ignore_modifiable_3"] pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_3_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_3` writer - u0_sft7110_noc_bus_oic_ignore_modifiable_3"] -pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_3_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_3_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_4` reader - u0_sft7110_noc_bus_oic_ignore_modifiable_4"] pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_4_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_ignore_modifiable_4` writer - u0_sft7110_noc_bus_oic_ignore_modifiable_4"] -pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_4_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_4_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_7_start` reader - u0_sft7110_noc_bus_oic_evemon_7_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_7_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_7_start` writer - u0_sft7110_noc_bus_oic_evemon_7_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_7_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_7_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_7_trigger` reader - u0_sft7110_noc_bus_oic_evemon_7_trigger"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_7_TRIGGER_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_8_start` reader - u0_sft7110_noc_bus_oic_evemon_8_start"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_8_START_R = crate::BitReader; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_8_start` writer - u0_sft7110_noc_bus_oic_evemon_8_start"] -pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_8_START_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_8_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `u0_sft7110_noc_bus_oic_evemon_8_trigger` reader - u0_sft7110_noc_bus_oic_evemon_8_trigger"] pub type U0_SFT7110_NOC_BUS_OIC_EVEMON_8_TRIGGER_R = crate::BitReader; impl R { @@ -117,58 +110,62 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_ignore_modifiable_0( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_0_W { - U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_0_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_0_W { + U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_0_W::new(self, 5) } #[doc = "Bit 6 - u0_sft7110_noc_bus_oic_ignore_modifiable_1"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_ignore_modifiable_1( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_1_W { - U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_1_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_1_W { + U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_1_W::new(self, 6) } #[doc = "Bit 7 - u0_sft7110_noc_bus_oic_ignore_modifiable_2"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_ignore_modifiable_2( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_2_W { - U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_2_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_2_W { + U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_2_W::new(self, 7) } #[doc = "Bit 8 - u0_sft7110_noc_bus_oic_ignore_modifiable_3"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_ignore_modifiable_3( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_3_W { - U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_3_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_3_W { + U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_3_W::new(self, 8) } #[doc = "Bit 9 - u0_sft7110_noc_bus_oic_ignore_modifiable_4"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_ignore_modifiable_4( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_4_W { - U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_4_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_4_W { + U0_SFT7110_NOC_BUS_OIC_IGNORE_MODIFIABLE_4_W::new(self, 9) } #[doc = "Bit 15 - u0_sft7110_noc_bus_oic_evemon_7_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_7_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_7_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_7_START_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_7_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_7_START_W::new(self, 15) } #[doc = "Bit 17 - u0_sft7110_noc_bus_oic_evemon_8_start"] #[inline(always)] #[must_use] pub fn u0_sft7110_noc_bus_oic_evemon_8_start( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_8_START_W { - U0_SFT7110_NOC_BUS_OIC_EVEMON_8_START_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> U0_SFT7110_NOC_BUS_OIC_EVEMON_8_START_W { + U0_SFT7110_NOC_BUS_OIC_EVEMON_8_START_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg60.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg60.rs index 39b1d8b..b97b06c 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg60.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg60.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_0_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_0_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_0_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_0( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_0_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_0_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_0_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_0_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg64.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg64.rs index 49420eb..94c764c 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg64.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg64.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_1_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_1_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_1_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_1( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_1_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_1_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_1_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_1_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg68.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg68.rs index cc52112..81fd95e 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg68.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg68.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_2_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_2_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_2_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_2( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_2_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_2_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_2_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_2_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg72.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg72.rs index f09b603..ddcbe13 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg72.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg72.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_3_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_3_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_3_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_3( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_3_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_3_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_3_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_3_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg76.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg76.rs index 271084e..1f33d71 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg76.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg76.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_4_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_4_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_4_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_4( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_4_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_4_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_4_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_4_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg8.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg8.rs index 4d8c810..a7e4743 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg8.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg8.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `scfg_vout0_remap_awaddr` reader - scfg_vout0_remap_awaddr"] pub type SCFG_VOUT0_REMAP_AWADDR_R = crate::FieldReader; #[doc = "Field `scfg_vout0_remap_awaddr` writer - scfg_vout0_remap_awaddr"] -pub type SCFG_VOUT0_REMAP_AWADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_VOUT0_REMAP_AWADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_vout1_remap_araddr` reader - scfg_vout1_remap_araddr"] pub type SCFG_VOUT1_REMAP_ARADDR_R = crate::FieldReader; #[doc = "Field `scfg_vout1_remap_araddr` writer - scfg_vout1_remap_araddr"] -pub type SCFG_VOUT1_REMAP_ARADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_VOUT1_REMAP_ARADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `scfg_vout1_remap_awaddr` reader - scfg_vout1_remap_awaddr"] pub type SCFG_VOUT1_REMAP_AWADDR_R = crate::FieldReader; #[doc = "Field `scfg_vout1_remap_awaddr` writer - scfg_vout1_remap_awaddr"] -pub type SCFG_VOUT1_REMAP_AWADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; +pub type SCFG_VOUT1_REMAP_AWADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - scfg_vout0_remap_awaddr"] #[inline(always)] @@ -37,26 +37,30 @@ impl W { #[must_use] pub fn scfg_vout0_remap_awaddr( &mut self, - ) -> SCFG_VOUT0_REMAP_AWADDR_W { - SCFG_VOUT0_REMAP_AWADDR_W::new(self) + ) -> SCFG_VOUT0_REMAP_AWADDR_W { + SCFG_VOUT0_REMAP_AWADDR_W::new(self, 0) } #[doc = "Bits 4:7 - scfg_vout1_remap_araddr"] #[inline(always)] #[must_use] pub fn scfg_vout1_remap_araddr( &mut self, - ) -> SCFG_VOUT1_REMAP_ARADDR_W { - SCFG_VOUT1_REMAP_ARADDR_W::new(self) + ) -> SCFG_VOUT1_REMAP_ARADDR_W { + SCFG_VOUT1_REMAP_ARADDR_W::new(self, 4) } #[doc = "Bits 8:11 - scfg_vout1_remap_awaddr"] #[inline(always)] #[must_use] pub fn scfg_vout1_remap_awaddr( &mut self, - ) -> SCFG_VOUT1_REMAP_AWADDR_W { - SCFG_VOUT1_REMAP_AWADDR_W::new(self) + ) -> SCFG_VOUT1_REMAP_AWADDR_W { + SCFG_VOUT1_REMAP_AWADDR_W::new(self, 8) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg80.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg80.rs index c029f58..4e441f1 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg80.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg80.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_5_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_5_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_5_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_5( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_5_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_5_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_5_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_5_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg84.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg84.rs index 36eb861..e2bb714 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg84.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg84.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_6_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_6_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_6_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_6( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_6_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_6_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_6_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_6_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg88.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg88.rs index 432ab5e..0dd9ee1 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg88.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg88.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_7_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_7_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_7_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_7( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_7_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_7_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_7_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_7_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg92.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg92.rs index 99964b1..0f09a22 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg92.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg92.rs @@ -5,8 +5,8 @@ pub type W = crate::W; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8` reader - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8"] pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_8_R = crate::FieldReader; #[doc = "Field `u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8` writer - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8"] -pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_8_W<'a, REG, const O: u8> = - crate::FieldWriter<'a, REG, 32, O, u32>; +pub type U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_8_W<'a, REG> = + crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8"] #[inline(always)] @@ -22,10 +22,14 @@ impl W { #[must_use] pub fn u0_sft7110_noc_bus_oic_qch_clock_stop_threshold_8( &mut self, - ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_8_W { - U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_8_W::new(self) + ) -> U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_8_W { + U0_SFT7110_NOC_BUS_OIC_QCH_CLOCK_STOP_THRESHOLD_8_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg96.rs b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg96.rs index 305193e..a20fe51 100644 --- a/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg96.rs +++ b/jh7110-vf2-13b-pac/src/sys_syscon/sys_sysconsaif_syscfg96.rs @@ -9,27 +9,27 @@ pub type U0_TDM16SLOT_PCM_MS_R = crate::BitReader; #[doc = "Field `u0_trace_mtx_scfg_c0_in0_ctl` reader - u0_trace_mtx_scfg_c0_in0_ctl"] pub type U0_TRACE_MTX_SCFG_C0_IN0_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c0_in0_ctl` writer - u0_trace_mtx_scfg_c0_in0_ctl"] -pub type U0_TRACE_MTX_SCFG_C0_IN0_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C0_IN0_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_trace_mtx_scfg_c0_in1_ctl` reader - u0_trace_mtx_scfg_c0_in1_ctl"] pub type U0_TRACE_MTX_SCFG_C0_IN1_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c0_in1_ctl` writer - u0_trace_mtx_scfg_c0_in1_ctl"] -pub type U0_TRACE_MTX_SCFG_C0_IN1_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C0_IN1_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_trace_mtx_scfg_c1_in0_ctl` reader - u0_trace_mtx_scfg_c1_in0_ctl"] pub type U0_TRACE_MTX_SCFG_C1_IN0_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c1_in0_ctl` writer - u0_trace_mtx_scfg_c1_in0_ctl"] -pub type U0_TRACE_MTX_SCFG_C1_IN0_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C1_IN0_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_trace_mtx_scfg_c1_in1_ctl` reader - u0_trace_mtx_scfg_c1_in1_ctl"] pub type U0_TRACE_MTX_SCFG_C1_IN1_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c1_in1_ctl` writer - u0_trace_mtx_scfg_c1_in1_ctl"] -pub type U0_TRACE_MTX_SCFG_C1_IN1_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C1_IN1_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_trace_mtx_scfg_c2_in0_ctl` reader - u0_trace_mtx_scfg_c2_in0_ctl"] pub type U0_TRACE_MTX_SCFG_C2_IN0_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c2_in0_ctl` writer - u0_trace_mtx_scfg_c2_in0_ctl"] -pub type U0_TRACE_MTX_SCFG_C2_IN0_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C2_IN0_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `u0_trace_mtx_scfg_c2_in1_ctl` reader - u0_trace_mtx_scfg_c2_in1_ctl"] pub type U0_TRACE_MTX_SCFG_C2_IN1_CTL_R = crate::FieldReader; #[doc = "Field `u0_trace_mtx_scfg_c2_in1_ctl` writer - u0_trace_mtx_scfg_c2_in1_ctl"] -pub type U0_TRACE_MTX_SCFG_C2_IN1_CTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; +pub type U0_TRACE_MTX_SCFG_C2_IN1_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; impl R { #[doc = "Bit 0 - u0_tdm16slot_clkpol"] #[inline(always)] @@ -78,50 +78,54 @@ impl W { #[must_use] pub fn u0_trace_mtx_scfg_c0_in0_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C0_IN0_CTL_W { - U0_TRACE_MTX_SCFG_C0_IN0_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C0_IN0_CTL_W { + U0_TRACE_MTX_SCFG_C0_IN0_CTL_W::new(self, 2) } #[doc = "Bits 7:11 - u0_trace_mtx_scfg_c0_in1_ctl"] #[inline(always)] #[must_use] pub fn u0_trace_mtx_scfg_c0_in1_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C0_IN1_CTL_W { - U0_TRACE_MTX_SCFG_C0_IN1_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C0_IN1_CTL_W { + U0_TRACE_MTX_SCFG_C0_IN1_CTL_W::new(self, 7) } #[doc = "Bits 12:16 - u0_trace_mtx_scfg_c1_in0_ctl"] #[inline(always)] #[must_use] pub fn u0_trace_mtx_scfg_c1_in0_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C1_IN0_CTL_W { - U0_TRACE_MTX_SCFG_C1_IN0_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C1_IN0_CTL_W { + U0_TRACE_MTX_SCFG_C1_IN0_CTL_W::new(self, 12) } #[doc = "Bits 17:21 - u0_trace_mtx_scfg_c1_in1_ctl"] #[inline(always)] #[must_use] pub fn u0_trace_mtx_scfg_c1_in1_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C1_IN1_CTL_W { - U0_TRACE_MTX_SCFG_C1_IN1_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C1_IN1_CTL_W { + U0_TRACE_MTX_SCFG_C1_IN1_CTL_W::new(self, 17) } #[doc = "Bits 22:26 - u0_trace_mtx_scfg_c2_in0_ctl"] #[inline(always)] #[must_use] pub fn u0_trace_mtx_scfg_c2_in0_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C2_IN0_CTL_W { - U0_TRACE_MTX_SCFG_C2_IN0_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C2_IN0_CTL_W { + U0_TRACE_MTX_SCFG_C2_IN0_CTL_W::new(self, 22) } #[doc = "Bits 27:31 - u0_trace_mtx_scfg_c2_in1_ctl"] #[inline(always)] #[must_use] pub fn u0_trace_mtx_scfg_c2_in1_ctl( &mut self, - ) -> U0_TRACE_MTX_SCFG_C2_IN1_CTL_W { - U0_TRACE_MTX_SCFG_C2_IN1_CTL_W::new(self) + ) -> U0_TRACE_MTX_SCFG_C2_IN1_CTL_W { + U0_TRACE_MTX_SCFG_C2_IN1_CTL_W::new(self, 27) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg.rs b/jh7110-vf2-13b-pac/src/syscrg.rs index 7c82f4a..8ff6910 100644 --- a/jh7110-vf2-13b-pac/src/syscrg.rs +++ b/jh7110-vf2-13b-pac/src/syscrg.rs @@ -1,1405 +1,2206 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + clk_cpu_root: CLK_CPU_ROOT, + clk_cpu_core: CLK_CPU_CORE, + clk_cpu_bus: CLK_CPU_BUS, + clk_gpu_root: CLK_GPU_ROOT, + clk_peripheral_root: CLK_PERIPHERAL_ROOT, + clk_bus_root: CLK_BUS_ROOT, + clk_nocstg_bus: CLK_NOCSTG_BUS, + clk_axi_cfg0: CLK_AXI_CFG0, + clk_stg_axiahb: CLK_STG_AXIAHB, + clk_ahb0: CLK_AHB0, + clk_ahb1: CLK_AHB1, + clk_apb_bus: CLK_APB_BUS, + clk_apb0: CLK_APB0, + clk_pll0_div2: CLK_PLL0_DIV2, + clk_pll1_div2: CLK_PLL1_DIV2, + clk_pll2_div2: CLK_PLL2_DIV2, + clk_audio_root: CLK_AUDIO_ROOT, + clk_mclk_inner: CLK_MCLK_INNER, + clk_mclk: CLK_MCLK, + clk_mclk_out: CLK_MCLK_OUT, + clk_isp_2x: CLK_ISP_2X, + clk_isp_axi: CLK_ISP_AXI, + clk_gclk0: CLK_GCLK0, + clk_gclk1: CLK_GCLK1, + clk_gclk2: CLK_GCLK2, + clk_u7mc_core0: CLK_U7MC_CORE0, + clk_u7mc_core1: CLK_U7MC_CORE1, + clk_u7mc_core2: CLK_U7MC_CORE2, + clk_u7mc_core3: CLK_U7MC_CORE3, + clk_u7mc_core4: CLK_U7MC_CORE4, + clk_u7mc_debug: CLK_U7MC_DEBUG, + u7mc_rtc_toggle: U7MC_RTC_TOGGLE, + clk_u7mc_trace0: CLK_U7MC_TRACE0, + clk_u7mc_trace1: CLK_U7MC_TRACE1, + clk_u7mc_trace2: CLK_U7MC_TRACE2, + clk_u7mc_trace3: CLK_U7MC_TRACE3, + clk_u7mc_trace4: CLK_U7MC_TRACE4, + clk_u7mc_trace_com: CLK_U7MC_TRACE_COM, + clk_u0_sft7110_noc_bus_clk_cpu_axi: CLK_U0_SFT7110_NOC_BUS_CLK_CPU_AXI, + clk_u0_sft7110_noc_bus_clk_axicfg0_axi: CLK_U0_SFT7110_NOC_BUS_CLK_AXICFG0_AXI, + clk_osc_div2: CLK_OSC_DIV2, + clk_pll1_div4: CLK_PLL1_DIV4, + clk_pll1_div8: CLK_PLL1_DIV8, + clk_ddr_bus: CLK_DDR_BUS, + clk_u0_ddr_sft7110_clk_axi: CLK_U0_DDR_SFT7110_CLK_AXI, + clk_gpu_core: CLK_GPU_CORE, + clk_u0_img_gpu_core_clk: CLK_U0_IMG_GPU_CORE_CLK, + clk_u0_img_gpu_sys_clk: CLK_U0_IMG_GPU_SYS_CLK, + clk_u0_img_gpu_clk_apb: CLK_U0_IMG_GPU_CLK_APB, + clk_u0_gpu_rtc_toggle: CLK_U0_GPU_RTC_TOGGLE, + clk_u0_sft7110_noc_bus_clk_gpu_axi: CLK_U0_SFT7110_NOC_BUS_CLK_GPU_AXI, + clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x: + CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISPCORE_2X, + clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi: CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISP_AXI, + clk_u0_sft7110_noc_bux_clk_isp_axi: CLK_U0_SFT7110_NOC_BUX_CLK_ISP_AXI, + clk_hifi4_core: CLK_HIFI4_CORE, + clk_hifi4_axi: CLK_HIFI4_AXI, + clk_u0_axi_cfg1_dec_clk_main: CLK_U0_AXI_CFG1_DEC_CLK_MAIN, + clk_u0_axi_cfg1_dec_clk_ahb: CLK_U0_AXI_CFG1_DEC_CLK_AHB, + clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src: + CLK_U0_DOM_VOUT_TOP_CLK_DOM_VOUT_TOP_CLK_VOUT_SRC, + clk_vout_axi_divcfg: CLK_VOUT_AXI_DIVCFG, + clk_noc_display_axi: CLK_NOC_DISPLAY_AXI, + clk_vout_ahb: CLK_VOUT_AHB, + clk_vout_axi_icg: CLK_VOUT_AXI_ICG, + clk_vout_hdmi_tx0_mclk: CLK_VOUT_HDMI_TX0_MCLK, + clk_vout_mipi_phy: CLK_VOUT_MIPI_PHY, + clk_jpeg_codec_axi: CLK_JPEG_CODEC_AXI, + clk_codaj12_axi: CLK_CODAJ12_AXI, + clk_codaj12_core: CLK_CODAJ12_CORE, + clk_codaj12_apb: CLK_CODAJ12_APB, + clk_vdec_axi: CLK_VDEC_AXI, + clk_wave511_axi: CLK_WAVE511_AXI, + clk_wave511_bpu: CLK_WAVE511_BPU, + clk_wave511_vce: CLK_WAVE511_VCE, + clk_wave511_apb: CLK_WAVE511_APB, + clk_wave511_jpg_arb: CLK_WAVE511_JPG_ARB, + clk_wave511_jpg_main: CLK_WAVE511_JPG_MAIN, + clk_noc_vdec_axi: CLK_NOC_VDEC_AXI, + clk_venc_axi: CLK_VENC_AXI, + clk_wave420l_axi: CLK_WAVE420L_AXI, + clk_wave420l_bpu: CLK_WAVE420L_BPU, + clk_wave420l_vce: CLK_WAVE420L_VCE, + clk_wave420l_apb: CLK_WAVE420L_APB, + clk_noc_venc_axi: CLK_NOC_VENC_AXI, + clk_axi_cfg0_dec_main_div: CLK_AXI_CFG0_DEC_MAIN_DIV, + clk_axi_cfg0_dec_main: CLK_AXI_CFG0_DEC_MAIN, + clk_axi_cfg0_dec_hifi4: CLK_AXI_CFG0_DEC_HIFI4, + clk_aximem_128b_axi: CLK_AXIMEM_128B_AXI, + clk_qspi_ahb: CLK_QSPI_AHB, + clk_qspi_apb: CLK_QSPI_APB, + clk_qspi_ref_src: CLK_QSPI_REF_SRC, + clk_qspi_ref: CLK_QSPI_REF, + clk_u0_sd_ahb: CLK_U0_SD_AHB, + clk_u1_sd_ahb: CLK_U1_SD_AHB, + clk_u0_sd_card: CLK_U0_SD_CARD, + clk_u1_sd_card: CLK_U1_SD_CARD, + clk_usb_125m: CLK_USB_125M, + clk_noc_stg_axi: CLK_NOC_STG_AXI, + clk_gmac5_axi64_ahb: CLK_GMAC5_AXI64_AHB, + clk_gmac5_axi64_axi: CLK_GMAC5_AXI64_AXI, + clk_gmac_src: CLK_GMAC_SRC, + clk_gmac1_gtx: CLK_GMAC1_GTX, + clk_gmac1_rmii_rtx: CLK_GMAC1_RMII_RTX, + clk_gmac5_axi64_ptp: CLK_GMAC5_AXI64_PTP, + clk_gmac5_axi64_rx: CLK_GMAC5_AXI64_RX, + clk_gmac5_axi64_rxi: CLK_GMAC5_AXI64_RXI, + clk_gmac5_axi64_tx: CLK_GMAC5_AXI64_TX, + clk_gmac5_axi64_txi: CLK_GMAC5_AXI64_TXI, + clk_gmac1_gtxclk: CLK_GMAC1_GTXCLK, + clk_gmac0_gtx: CLK_GMAC0_GTX, + clk_gmac0_ptp: CLK_GMAC0_PTP, + clk_gmac_phy: CLK_GMAC_PHY, + clk_gmac0_gtxclk: CLK_GMAC0_GTXCLK, + clk_sys_iomux_pclk: CLK_SYS_IOMUX_PCLK, + clk_mbox_apb: CLK_MBOX_APB, + clk_internal_ctrl_apb: CLK_INTERNAL_CTRL_APB, + clk_u0_can_ctrl_apb: CLK_U0_CAN_CTRL_APB, + clk_u0_can_ctrl_tim: CLK_U0_CAN_CTRL_TIM, + clk_u0_can_ctrl_can: CLK_U0_CAN_CTRL_CAN, + clk_u1_can_ctrl_apb: CLK_U1_CAN_CTRL_APB, + clk_u1_can_ctrl_tim: CLK_U1_CAN_CTRL_TIM, + clk_u1_can_ctrl_can: CLK_U1_CAN_CTRL_CAN, + clk_pwm_apb: CLK_PWM_APB, + clk_wdt_apb: CLK_WDT_APB, + clk_wdt: CLK_WDT, + clk_tim_apb: CLK_TIM_APB, + clk_tim0: CLK_TIM0, + clk_tim1: CLK_TIM1, + clk_tim2: CLK_TIM2, + clk_tim3: CLK_TIM3, + clk_temp_sensor_apb: CLK_TEMP_SENSOR_APB, + clk_temp_sensor: CLK_TEMP_SENSOR, + clk_u0_spi_apb: CLK_U0_SPI_APB, + clk_u1_spi_apb: CLK_U1_SPI_APB, + clk_u2_spi_apb: CLK_U2_SPI_APB, + clk_u3_spi_apb: CLK_U3_SPI_APB, + clk_u4_spi_apb: CLK_U4_SPI_APB, + clk_u5_spi_apb: CLK_U5_SPI_APB, + clk_u6_spi_apb: CLK_U6_SPI_APB, + clk_u0_i2c_apb: CLK_U0_I2C_APB, + clk_u1_i2c_apb: CLK_U1_I2C_APB, + clk_u2_i2c_apb: CLK_U2_I2C_APB, + clk_u3_i2c_apb: CLK_U3_I2C_APB, + clk_u4_i2c_apb: CLK_U4_I2C_APB, + clk_u5_i2c_apb: CLK_U5_I2C_APB, + clk_u6_i2c_apb: CLK_U6_I2C_APB, + clk_u0_uart_apb: CLK_U0_UART_APB, + clk_u0_uart_core: CLK_U0_UART_CORE, + clk_u1_uart_apb: CLK_U1_UART_APB, + clk_u1_uart_core: CLK_U1_UART_CORE, + clk_u2_uart_apb: CLK_U2_UART_APB, + clk_u2_uart_core: CLK_U2_UART_CORE, + clk_u3_uart_apb: CLK_U3_UART_APB, + clk_u3_uart_core: CLK_U3_UART_CORE, + clk_u4_uart_apb: CLK_U4_UART_APB, + clk_u4_uart_core: CLK_U4_UART_CORE, + clk_u5_uart_apb: CLK_U5_UART_APB, + clk_u5_uart_core: CLK_U5_UART_CORE, + clk_pwmdac_apb: CLK_PWMDAC_APB, + clk_pwmdac_core: CLK_PWMDAC_CORE, + clk_spdif_apb: CLK_SPDIF_APB, + clk_spdif_core: CLK_SPDIF_CORE, + clk_u0_i2s_tx_apb: CLK_U0_I2S_TX_APB, + clk_u0_i2stx_4ch0_bclk_mst: CLK_U0_I2STX_4CH0_BCLK_MST, + clk_u0_i2stx_4ch0_bclk_mst_inv: CLK_U0_I2STX_4CH0_BCLK_MST_INV, + clk_i2stx0_lrck_mst: CLK_I2STX0_LRCK_MST, + clk_u0_i2stx_bclk: CLK_U0_I2STX_BCLK, + clk_u0_i2stx_bclk_neg: CLK_U0_I2STX_BCLK_NEG, + clk_u0_i2stx_lrck: CLK_U0_I2STX_LRCK, + clk_u1_i2s_tx_apb: CLK_U1_I2S_TX_APB, + clk_u1_i2stx_4ch1_bclk_mst: CLK_U1_I2STX_4CH1_BCLK_MST, + clk_u1_i2stx_4ch1_bclk_mst_inv: CLK_U1_I2STX_4CH1_BCLK_MST_INV, + clk_i2stx1_lrck_mst: CLK_I2STX1_LRCK_MST, + clk_u1_i2stx_bclk: CLK_U1_I2STX_BCLK, + clk_u1_i2stx_bclk_neg: CLK_U1_I2STX_BCLK_NEG, + clk_u1_i2stx_lrck: CLK_U1_I2STX_LRCK, + clk_i2s_apb: CLK_I2S_APB, + clk_i2s_bclk_mst: CLK_I2S_BCLK_MST, + clk_i2s_bclk_mst_inv: CLK_I2S_BCLK_MST_INV, + clk_i2s_lrck_mst: CLK_I2S_LRCK_MST, + clk_i2s_bclk: CLK_I2S_BCLK, + clk_i2s_bclk_neg: CLK_I2S_BCLK_NEG, + clk_i2s_lrck: CLK_I2S_LRCK, + clk_pdm_dmic: CLK_PDM_DMIC, + clk_pdm_apb: CLK_PDM_APB, + clk_tdm_ahb: CLK_TDM_AHB, + clk_tdm_apb: CLK_TDM_APB, + clk_tdm_internal: CLK_TDM_INTERNAL, + clk_tdm: CLK_TDM, + clk_tdm_neg: CLK_TDM_NEG, + clk_jtag_cert_trng: CLK_JTAG_CERT_TRNG, + soft_rst0_addr_sel: SOFT_RST0_ADDR_SEL, + soft_rst1_addr_sel: SOFT_RST1_ADDR_SEL, + soft_rst2_addr_sel: SOFT_RST2_ADDR_SEL, + soft_rst3_addr_sel: SOFT_RST3_ADDR_SEL, + syscrg_rst0_status: SYSCRG_RST0_STATUS, + syscrg_rst1_status: SYSCRG_RST1_STATUS, + syscrg_rst2_status: SYSCRG_RST2_STATUS, + syscrg_rst3_status: SYSCRG_RST3_STATUS, +} +impl RegisterBlock { #[doc = "0x00 - Clock CPU Root"] - pub clk_cpu_root: CLK_CPU_ROOT, + #[inline(always)] + pub const fn clk_cpu_root(&self) -> &CLK_CPU_ROOT { + &self.clk_cpu_root + } #[doc = "0x04 - Clock CPU Core"] - pub clk_cpu_core: CLK_CPU_CORE, + #[inline(always)] + pub const fn clk_cpu_core(&self) -> &CLK_CPU_CORE { + &self.clk_cpu_core + } #[doc = "0x08 - Clock CPU Bus"] - pub clk_cpu_bus: CLK_CPU_BUS, + #[inline(always)] + pub const fn clk_cpu_bus(&self) -> &CLK_CPU_BUS { + &self.clk_cpu_bus + } #[doc = "0x0c - Clock GPU Root"] - pub clk_gpu_root: CLK_GPU_ROOT, + #[inline(always)] + pub const fn clk_gpu_root(&self) -> &CLK_GPU_ROOT { + &self.clk_gpu_root + } #[doc = "0x10 - Clock Peripheral Root"] - pub clk_peripheral_root: CLK_PERIPHERAL_ROOT, + #[inline(always)] + pub const fn clk_peripheral_root(&self) -> &CLK_PERIPHERAL_ROOT { + &self.clk_peripheral_root + } #[doc = "0x14 - Clock Bus Root"] - pub clk_bus_root: CLK_BUS_ROOT, + #[inline(always)] + pub const fn clk_bus_root(&self) -> &CLK_BUS_ROOT { + &self.clk_bus_root + } #[doc = "0x18 - Clock NOCSTG Bus"] - pub clk_nocstg_bus: CLK_NOCSTG_BUS, + #[inline(always)] + pub const fn clk_nocstg_bus(&self) -> &CLK_NOCSTG_BUS { + &self.clk_nocstg_bus + } #[doc = "0x1c - Clock AXI Configuration 0"] - pub clk_axi_cfg0: CLK_AXI_CFG0, + #[inline(always)] + pub const fn clk_axi_cfg0(&self) -> &CLK_AXI_CFG0 { + &self.clk_axi_cfg0 + } #[doc = "0x20 - Clock STG AXI AHB"] - pub clk_stg_axiahb: CLK_STG_AXIAHB, + #[inline(always)] + pub const fn clk_stg_axiahb(&self) -> &CLK_STG_AXIAHB { + &self.clk_stg_axiahb + } #[doc = "0x24 - Clock AHB 0"] - pub clk_ahb0: CLK_AHB0, + #[inline(always)] + pub const fn clk_ahb0(&self) -> &CLK_AHB0 { + &self.clk_ahb0 + } #[doc = "0x28 - Clock AHB 1"] - pub clk_ahb1: CLK_AHB1, + #[inline(always)] + pub const fn clk_ahb1(&self) -> &CLK_AHB1 { + &self.clk_ahb1 + } #[doc = "0x2c - Clock APB Bus"] - pub clk_apb_bus: CLK_APB_BUS, + #[inline(always)] + pub const fn clk_apb_bus(&self) -> &CLK_APB_BUS { + &self.clk_apb_bus + } #[doc = "0x30 - Clock APB 0"] - pub clk_apb0: CLK_APB0, + #[inline(always)] + pub const fn clk_apb0(&self) -> &CLK_APB0 { + &self.clk_apb0 + } #[doc = "0x34 - Clock PLL 0 Divider 2"] - pub clk_pll0_div2: CLK_PLL0_DIV2, + #[inline(always)] + pub const fn clk_pll0_div2(&self) -> &CLK_PLL0_DIV2 { + &self.clk_pll0_div2 + } #[doc = "0x38 - Clock PLL 1 Divider 2"] - pub clk_pll1_div2: CLK_PLL1_DIV2, + #[inline(always)] + pub const fn clk_pll1_div2(&self) -> &CLK_PLL1_DIV2 { + &self.clk_pll1_div2 + } #[doc = "0x3c - Clock PLL 2 Divider 2"] - pub clk_pll2_div2: CLK_PLL2_DIV2, + #[inline(always)] + pub const fn clk_pll2_div2(&self) -> &CLK_PLL2_DIV2 { + &self.clk_pll2_div2 + } #[doc = "0x40 - Clock Audio Root"] - pub clk_audio_root: CLK_AUDIO_ROOT, + #[inline(always)] + pub const fn clk_audio_root(&self) -> &CLK_AUDIO_ROOT { + &self.clk_audio_root + } #[doc = "0x44 - Clock MCLK Inner"] - pub clk_mclk_inner: CLK_MCLK_INNER, + #[inline(always)] + pub const fn clk_mclk_inner(&self) -> &CLK_MCLK_INNER { + &self.clk_mclk_inner + } #[doc = "0x48 - Clock MCLK"] - pub clk_mclk: CLK_MCLK, + #[inline(always)] + pub const fn clk_mclk(&self) -> &CLK_MCLK { + &self.clk_mclk + } #[doc = "0x4c - Clock MCLK Out"] - pub clk_mclk_out: CLK_MCLK_OUT, + #[inline(always)] + pub const fn clk_mclk_out(&self) -> &CLK_MCLK_OUT { + &self.clk_mclk_out + } #[doc = "0x50 - Clock ISP 2x"] - pub clk_isp_2x: CLK_ISP_2X, + #[inline(always)] + pub const fn clk_isp_2x(&self) -> &CLK_ISP_2X { + &self.clk_isp_2x + } #[doc = "0x54 - Clock ISP AXI"] - pub clk_isp_axi: CLK_ISP_AXI, + #[inline(always)] + pub const fn clk_isp_axi(&self) -> &CLK_ISP_AXI { + &self.clk_isp_axi + } #[doc = "0x58 - Clock GCLK 0"] - pub clk_gclk0: CLK_GCLK0, + #[inline(always)] + pub const fn clk_gclk0(&self) -> &CLK_GCLK0 { + &self.clk_gclk0 + } #[doc = "0x5c - Clock GCLK 1"] - pub clk_gclk1: CLK_GCLK1, + #[inline(always)] + pub const fn clk_gclk1(&self) -> &CLK_GCLK1 { + &self.clk_gclk1 + } #[doc = "0x60 - Clock GCLK 2"] - pub clk_gclk2: CLK_GCLK2, + #[inline(always)] + pub const fn clk_gclk2(&self) -> &CLK_GCLK2 { + &self.clk_gclk2 + } #[doc = "0x64 - U7MC Core Clock 0"] - pub clk_u7mc_core0: CLK_U7MC_CORE0, + #[inline(always)] + pub const fn clk_u7mc_core0(&self) -> &CLK_U7MC_CORE0 { + &self.clk_u7mc_core0 + } #[doc = "0x68 - U7MC Core Clock 1"] - pub clk_u7mc_core1: CLK_U7MC_CORE1, + #[inline(always)] + pub const fn clk_u7mc_core1(&self) -> &CLK_U7MC_CORE1 { + &self.clk_u7mc_core1 + } #[doc = "0x6c - U7MC Core Clock 2"] - pub clk_u7mc_core2: CLK_U7MC_CORE2, + #[inline(always)] + pub const fn clk_u7mc_core2(&self) -> &CLK_U7MC_CORE2 { + &self.clk_u7mc_core2 + } #[doc = "0x70 - U7MC Core Clock 3"] - pub clk_u7mc_core3: CLK_U7MC_CORE3, + #[inline(always)] + pub const fn clk_u7mc_core3(&self) -> &CLK_U7MC_CORE3 { + &self.clk_u7mc_core3 + } #[doc = "0x74 - U7MC Core Clock 4"] - pub clk_u7mc_core4: CLK_U7MC_CORE4, + #[inline(always)] + pub const fn clk_u7mc_core4(&self) -> &CLK_U7MC_CORE4 { + &self.clk_u7mc_core4 + } #[doc = "0x78 - U7MC Debug Clock"] - pub clk_u7mc_debug: CLK_U7MC_DEBUG, + #[inline(always)] + pub const fn clk_u7mc_debug(&self) -> &CLK_U7MC_DEBUG { + &self.clk_u7mc_debug + } #[doc = "0x7c - U7MC RTC Toggle"] - pub u7mc_rtc_toggle: U7MC_RTC_TOGGLE, + #[inline(always)] + pub const fn u7mc_rtc_toggle(&self) -> &U7MC_RTC_TOGGLE { + &self.u7mc_rtc_toggle + } #[doc = "0x80 - U7MC Trace Clock 0"] - pub clk_u7mc_trace0: CLK_U7MC_TRACE0, + #[inline(always)] + pub const fn clk_u7mc_trace0(&self) -> &CLK_U7MC_TRACE0 { + &self.clk_u7mc_trace0 + } #[doc = "0x84 - U7MC Trace Clock 1"] - pub clk_u7mc_trace1: CLK_U7MC_TRACE1, + #[inline(always)] + pub const fn clk_u7mc_trace1(&self) -> &CLK_U7MC_TRACE1 { + &self.clk_u7mc_trace1 + } #[doc = "0x88 - U7MC Trace Clock 2"] - pub clk_u7mc_trace2: CLK_U7MC_TRACE2, + #[inline(always)] + pub const fn clk_u7mc_trace2(&self) -> &CLK_U7MC_TRACE2 { + &self.clk_u7mc_trace2 + } #[doc = "0x8c - U7MC Trace Clock 3"] - pub clk_u7mc_trace3: CLK_U7MC_TRACE3, + #[inline(always)] + pub const fn clk_u7mc_trace3(&self) -> &CLK_U7MC_TRACE3 { + &self.clk_u7mc_trace3 + } #[doc = "0x90 - U7MC Trace Clock 4"] - pub clk_u7mc_trace4: CLK_U7MC_TRACE4, + #[inline(always)] + pub const fn clk_u7mc_trace4(&self) -> &CLK_U7MC_TRACE4 { + &self.clk_u7mc_trace4 + } #[doc = "0x94 - U7MC Trace Clock COM"] - pub clk_u7mc_trace_com: CLK_U7MC_TRACE_COM, + #[inline(always)] + pub const fn clk_u7mc_trace_com(&self) -> &CLK_U7MC_TRACE_COM { + &self.clk_u7mc_trace_com + } #[doc = "0x98 - clk_u0_sft7110_noc_bus_clk_cpu_axi"] - pub clk_u0_sft7110_noc_bus_clk_cpu_axi: CLK_U0_SFT7110_NOC_BUS_CLK_CPU_AXI, + #[inline(always)] + pub const fn clk_u0_sft7110_noc_bus_clk_cpu_axi(&self) -> &CLK_U0_SFT7110_NOC_BUS_CLK_CPU_AXI { + &self.clk_u0_sft7110_noc_bus_clk_cpu_axi + } #[doc = "0x9c - clk_u0_sft7110_noc_bus_clk_axicfg0_axi"] - pub clk_u0_sft7110_noc_bus_clk_axicfg0_axi: CLK_U0_SFT7110_NOC_BUS_CLK_AXICFG0_AXI, + #[inline(always)] + pub const fn clk_u0_sft7110_noc_bus_clk_axicfg0_axi( + &self, + ) -> &CLK_U0_SFT7110_NOC_BUS_CLK_AXICFG0_AXI { + &self.clk_u0_sft7110_noc_bus_clk_axicfg0_axi + } #[doc = "0xa0 - clk_osc_div2"] - pub clk_osc_div2: CLK_OSC_DIV2, + #[inline(always)] + pub const fn clk_osc_div2(&self) -> &CLK_OSC_DIV2 { + &self.clk_osc_div2 + } #[doc = "0xa4 - clk_pll1_div4"] - pub clk_pll1_div4: CLK_PLL1_DIV4, + #[inline(always)] + pub const fn clk_pll1_div4(&self) -> &CLK_PLL1_DIV4 { + &self.clk_pll1_div4 + } #[doc = "0xa8 - clk_pll1_div8"] - pub clk_pll1_div8: CLK_PLL1_DIV8, + #[inline(always)] + pub const fn clk_pll1_div8(&self) -> &CLK_PLL1_DIV8 { + &self.clk_pll1_div8 + } #[doc = "0xac - clk_ddr_bus"] - pub clk_ddr_bus: CLK_DDR_BUS, + #[inline(always)] + pub const fn clk_ddr_bus(&self) -> &CLK_DDR_BUS { + &self.clk_ddr_bus + } #[doc = "0xb0 - clk_u0_ddr_sfft7110_clk_axi"] - pub clk_u0_ddr_sft7110_clk_axi: CLK_U0_DDR_SFT7110_CLK_AXI, + #[inline(always)] + pub const fn clk_u0_ddr_sft7110_clk_axi(&self) -> &CLK_U0_DDR_SFT7110_CLK_AXI { + &self.clk_u0_ddr_sft7110_clk_axi + } #[doc = "0xb4 - clk_gpu_core"] - pub clk_gpu_core: CLK_GPU_CORE, + #[inline(always)] + pub const fn clk_gpu_core(&self) -> &CLK_GPU_CORE { + &self.clk_gpu_core + } #[doc = "0xb8 - clk_u0_img_gpu_core_clk"] - pub clk_u0_img_gpu_core_clk: CLK_U0_IMG_GPU_CORE_CLK, + #[inline(always)] + pub const fn clk_u0_img_gpu_core_clk(&self) -> &CLK_U0_IMG_GPU_CORE_CLK { + &self.clk_u0_img_gpu_core_clk + } #[doc = "0xbc - clk_u0_img_gpu_sys_clk"] - pub clk_u0_img_gpu_sys_clk: CLK_U0_IMG_GPU_SYS_CLK, + #[inline(always)] + pub const fn clk_u0_img_gpu_sys_clk(&self) -> &CLK_U0_IMG_GPU_SYS_CLK { + &self.clk_u0_img_gpu_sys_clk + } #[doc = "0xc0 - clk_u0_img_gpu_clk_apb"] - pub clk_u0_img_gpu_clk_apb: CLK_U0_IMG_GPU_CLK_APB, + #[inline(always)] + pub const fn clk_u0_img_gpu_clk_apb(&self) -> &CLK_U0_IMG_GPU_CLK_APB { + &self.clk_u0_img_gpu_clk_apb + } #[doc = "0xc4 - clk_u0_gpu_rtc_toggle"] - pub clk_u0_gpu_rtc_toggle: CLK_U0_GPU_RTC_TOGGLE, + #[inline(always)] + pub const fn clk_u0_gpu_rtc_toggle(&self) -> &CLK_U0_GPU_RTC_TOGGLE { + &self.clk_u0_gpu_rtc_toggle + } #[doc = "0xc8 - clk_u0_sft7110_noc_bus_clk_gpu_axi"] - pub clk_u0_sft7110_noc_bus_clk_gpu_axi: CLK_U0_SFT7110_NOC_BUS_CLK_GPU_AXI, + #[inline(always)] + pub const fn clk_u0_sft7110_noc_bus_clk_gpu_axi(&self) -> &CLK_U0_SFT7110_NOC_BUS_CLK_GPU_AXI { + &self.clk_u0_sft7110_noc_bus_clk_gpu_axi + } #[doc = "0xcc - clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x"] - pub clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x: - CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISPCORE_2X, + #[inline(always)] + pub const fn clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x( + &self, + ) -> &CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISPCORE_2X { + &self.clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x + } #[doc = "0xd0 - clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi"] - pub clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi: - CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISP_AXI, + #[inline(always)] + pub const fn clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi( + &self, + ) -> &CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISP_AXI { + &self.clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi + } #[doc = "0xd4 - clk_u0_sft7110_noc_bux_clk_isp_axi"] - pub clk_u0_sft7110_noc_bux_clk_isp_axi: CLK_U0_SFT7110_NOC_BUX_CLK_ISP_AXI, + #[inline(always)] + pub const fn clk_u0_sft7110_noc_bux_clk_isp_axi(&self) -> &CLK_U0_SFT7110_NOC_BUX_CLK_ISP_AXI { + &self.clk_u0_sft7110_noc_bux_clk_isp_axi + } #[doc = "0xd8 - clk_hifi4_core"] - pub clk_hifi4_core: CLK_HIFI4_CORE, + #[inline(always)] + pub const fn clk_hifi4_core(&self) -> &CLK_HIFI4_CORE { + &self.clk_hifi4_core + } #[doc = "0xdc - clk_hifi4_axi"] - pub clk_hifi4_axi: CLK_HIFI4_AXI, + #[inline(always)] + pub const fn clk_hifi4_axi(&self) -> &CLK_HIFI4_AXI { + &self.clk_hifi4_axi + } #[doc = "0xe0 - clk_u0_axi_cfg1_dec_clk_main"] - pub clk_u0_axi_cfg1_dec_clk_main: CLK_U0_AXI_CFG1_DEC_CLK_MAIN, + #[inline(always)] + pub const fn clk_u0_axi_cfg1_dec_clk_main(&self) -> &CLK_U0_AXI_CFG1_DEC_CLK_MAIN { + &self.clk_u0_axi_cfg1_dec_clk_main + } #[doc = "0xe4 - clk_u0_axi_cfg1_dec_clk_ahb"] - pub clk_u0_axi_cfg1_dec_clk_ahb: CLK_U0_AXI_CFG1_DEC_CLK_AHB, + #[inline(always)] + pub const fn clk_u0_axi_cfg1_dec_clk_ahb(&self) -> &CLK_U0_AXI_CFG1_DEC_CLK_AHB { + &self.clk_u0_axi_cfg1_dec_clk_ahb + } #[doc = "0xe8 - clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src"] - pub clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src: - CLK_U0_DOM_VOUT_TOP_CLK_DOM_VOUT_TOP_CLK_VOUT_SRC, + #[inline(always)] + pub const fn clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src( + &self, + ) -> &CLK_U0_DOM_VOUT_TOP_CLK_DOM_VOUT_TOP_CLK_VOUT_SRC { + &self.clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src + } #[doc = "0xec - Clock Video Output AXI DIVCFG"] - pub clk_vout_axi_divcfg: CLK_VOUT_AXI_DIVCFG, + #[inline(always)] + pub const fn clk_vout_axi_divcfg(&self) -> &CLK_VOUT_AXI_DIVCFG { + &self.clk_vout_axi_divcfg + } #[doc = "0xf0 - Clock NOC Display AXI"] - pub clk_noc_display_axi: CLK_NOC_DISPLAY_AXI, + #[inline(always)] + pub const fn clk_noc_display_axi(&self) -> &CLK_NOC_DISPLAY_AXI { + &self.clk_noc_display_axi + } #[doc = "0xf4 - Clock Video Output AHB"] - pub clk_vout_ahb: CLK_VOUT_AHB, + #[inline(always)] + pub const fn clk_vout_ahb(&self) -> &CLK_VOUT_AHB { + &self.clk_vout_ahb + } #[doc = "0xf8 - Clock Video Output AXI ICG"] - pub clk_vout_axi_icg: CLK_VOUT_AXI_ICG, + #[inline(always)] + pub const fn clk_vout_axi_icg(&self) -> &CLK_VOUT_AXI_ICG { + &self.clk_vout_axi_icg + } #[doc = "0xfc - Clock Video Output HDMI TX0 MCLK"] - pub clk_vout_hdmi_tx0_mclk: CLK_VOUT_HDMI_TX0_MCLK, + #[inline(always)] + pub const fn clk_vout_hdmi_tx0_mclk(&self) -> &CLK_VOUT_HDMI_TX0_MCLK { + &self.clk_vout_hdmi_tx0_mclk + } #[doc = "0x100 - Clock Video Output MIPI PHY Reference"] - pub clk_vout_mipi_phy: CLK_VOUT_MIPI_PHY, + #[inline(always)] + pub const fn clk_vout_mipi_phy(&self) -> &CLK_VOUT_MIPI_PHY { + &self.clk_vout_mipi_phy + } #[doc = "0x104 - Clock JPEG Codec AXI"] - pub clk_jpeg_codec_axi: CLK_JPEG_CODEC_AXI, + #[inline(always)] + pub const fn clk_jpeg_codec_axi(&self) -> &CLK_JPEG_CODEC_AXI { + &self.clk_jpeg_codec_axi + } #[doc = "0x108 - CODAJ12 Clock AXI"] - pub clk_codaj12_axi: CLK_CODAJ12_AXI, + #[inline(always)] + pub const fn clk_codaj12_axi(&self) -> &CLK_CODAJ12_AXI { + &self.clk_codaj12_axi + } #[doc = "0x10c - CODAJ12 Clock Core"] - pub clk_codaj12_core: CLK_CODAJ12_CORE, + #[inline(always)] + pub const fn clk_codaj12_core(&self) -> &CLK_CODAJ12_CORE { + &self.clk_codaj12_core + } #[doc = "0x110 - CODAJ12 Clock APB"] - pub clk_codaj12_apb: CLK_CODAJ12_APB, + #[inline(always)] + pub const fn clk_codaj12_apb(&self) -> &CLK_CODAJ12_APB { + &self.clk_codaj12_apb + } #[doc = "0x114 - Clock Video Decoder AXI"] - pub clk_vdec_axi: CLK_VDEC_AXI, + #[inline(always)] + pub const fn clk_vdec_axi(&self) -> &CLK_VDEC_AXI { + &self.clk_vdec_axi + } #[doc = "0x118 - Clock WAVE511 AXI"] - pub clk_wave511_axi: CLK_WAVE511_AXI, + #[inline(always)] + pub const fn clk_wave511_axi(&self) -> &CLK_WAVE511_AXI { + &self.clk_wave511_axi + } #[doc = "0x11c - Clock WAVE511 BPU"] - pub clk_wave511_bpu: CLK_WAVE511_BPU, + #[inline(always)] + pub const fn clk_wave511_bpu(&self) -> &CLK_WAVE511_BPU { + &self.clk_wave511_bpu + } #[doc = "0x120 - Clock WAVE511 VCE"] - pub clk_wave511_vce: CLK_WAVE511_VCE, + #[inline(always)] + pub const fn clk_wave511_vce(&self) -> &CLK_WAVE511_VCE { + &self.clk_wave511_vce + } #[doc = "0x124 - Clock WAVE511 APB"] - pub clk_wave511_apb: CLK_WAVE511_APB, + #[inline(always)] + pub const fn clk_wave511_apb(&self) -> &CLK_WAVE511_APB { + &self.clk_wave511_apb + } #[doc = "0x128 - Clock WAVE511 JPG ARB"] - pub clk_wave511_jpg_arb: CLK_WAVE511_JPG_ARB, + #[inline(always)] + pub const fn clk_wave511_jpg_arb(&self) -> &CLK_WAVE511_JPG_ARB { + &self.clk_wave511_jpg_arb + } #[doc = "0x12c - Clock WAVE511 JPG Main"] - pub clk_wave511_jpg_main: CLK_WAVE511_JPG_MAIN, + #[inline(always)] + pub const fn clk_wave511_jpg_main(&self) -> &CLK_WAVE511_JPG_MAIN { + &self.clk_wave511_jpg_main + } #[doc = "0x130 - Clock NOC Video Decoder AXI"] - pub clk_noc_vdec_axi: CLK_NOC_VDEC_AXI, + #[inline(always)] + pub const fn clk_noc_vdec_axi(&self) -> &CLK_NOC_VDEC_AXI { + &self.clk_noc_vdec_axi + } #[doc = "0x134 - Clock Video Encoder AXI"] - pub clk_venc_axi: CLK_VENC_AXI, + #[inline(always)] + pub const fn clk_venc_axi(&self) -> &CLK_VENC_AXI { + &self.clk_venc_axi + } #[doc = "0x138 - Clock WAVE420L AXI"] - pub clk_wave420l_axi: CLK_WAVE420L_AXI, + #[inline(always)] + pub const fn clk_wave420l_axi(&self) -> &CLK_WAVE420L_AXI { + &self.clk_wave420l_axi + } #[doc = "0x13c - Clock WAVE420L BPU"] - pub clk_wave420l_bpu: CLK_WAVE420L_BPU, + #[inline(always)] + pub const fn clk_wave420l_bpu(&self) -> &CLK_WAVE420L_BPU { + &self.clk_wave420l_bpu + } #[doc = "0x140 - Clock WAVE420L VCE"] - pub clk_wave420l_vce: CLK_WAVE420L_VCE, + #[inline(always)] + pub const fn clk_wave420l_vce(&self) -> &CLK_WAVE420L_VCE { + &self.clk_wave420l_vce + } #[doc = "0x144 - Clock WAVE420L APB"] - pub clk_wave420l_apb: CLK_WAVE420L_APB, + #[inline(always)] + pub const fn clk_wave420l_apb(&self) -> &CLK_WAVE420L_APB { + &self.clk_wave420l_apb + } #[doc = "0x148 - Clock NOC Video Encoder AXI"] - pub clk_noc_venc_axi: CLK_NOC_VENC_AXI, + #[inline(always)] + pub const fn clk_noc_venc_axi(&self) -> &CLK_NOC_VENC_AXI { + &self.clk_noc_venc_axi + } #[doc = "0x14c - Clock AXI Config 0 DEC Main Divider"] - pub clk_axi_cfg0_dec_main_div: CLK_AXI_CFG0_DEC_MAIN_DIV, + #[inline(always)] + pub const fn clk_axi_cfg0_dec_main_div(&self) -> &CLK_AXI_CFG0_DEC_MAIN_DIV { + &self.clk_axi_cfg0_dec_main_div + } #[doc = "0x150 - Clock AXI Config 0 DEC Main"] - pub clk_axi_cfg0_dec_main: CLK_AXI_CFG0_DEC_MAIN, + #[inline(always)] + pub const fn clk_axi_cfg0_dec_main(&self) -> &CLK_AXI_CFG0_DEC_MAIN { + &self.clk_axi_cfg0_dec_main + } #[doc = "0x154 - Clock AXI Config 0 DEC HIFI4"] - pub clk_axi_cfg0_dec_hifi4: CLK_AXI_CFG0_DEC_HIFI4, + #[inline(always)] + pub const fn clk_axi_cfg0_dec_hifi4(&self) -> &CLK_AXI_CFG0_DEC_HIFI4 { + &self.clk_axi_cfg0_dec_hifi4 + } #[doc = "0x158 - Clock AXIMEM 128B AXI"] - pub clk_aximem_128b_axi: CLK_AXIMEM_128B_AXI, + #[inline(always)] + pub const fn clk_aximem_128b_axi(&self) -> &CLK_AXIMEM_128B_AXI { + &self.clk_aximem_128b_axi + } #[doc = "0x15c - Clock QSPI AHB"] - pub clk_qspi_ahb: CLK_QSPI_AHB, + #[inline(always)] + pub const fn clk_qspi_ahb(&self) -> &CLK_QSPI_AHB { + &self.clk_qspi_ahb + } #[doc = "0x160 - Clock QSPI APB"] - pub clk_qspi_apb: CLK_QSPI_APB, + #[inline(always)] + pub const fn clk_qspi_apb(&self) -> &CLK_QSPI_APB { + &self.clk_qspi_apb + } #[doc = "0x164 - Clock QSPI Reference Source"] - pub clk_qspi_ref_src: CLK_QSPI_REF_SRC, + #[inline(always)] + pub const fn clk_qspi_ref_src(&self) -> &CLK_QSPI_REF_SRC { + &self.clk_qspi_ref_src + } #[doc = "0x168 - Clock QSPI Reference"] - pub clk_qspi_ref: CLK_QSPI_REF, + #[inline(always)] + pub const fn clk_qspi_ref(&self) -> &CLK_QSPI_REF { + &self.clk_qspi_ref + } #[doc = "0x16c - U0 SD Clock AHB"] - pub clk_u0_sd_ahb: CLK_U0_SD_AHB, + #[inline(always)] + pub const fn clk_u0_sd_ahb(&self) -> &CLK_U0_SD_AHB { + &self.clk_u0_sd_ahb + } #[doc = "0x170 - U1 SD Clock AHB"] - pub clk_u1_sd_ahb: CLK_U1_SD_AHB, + #[inline(always)] + pub const fn clk_u1_sd_ahb(&self) -> &CLK_U1_SD_AHB { + &self.clk_u1_sd_ahb + } #[doc = "0x174 - U0 SD Card Clock"] - pub clk_u0_sd_card: CLK_U0_SD_CARD, + #[inline(always)] + pub const fn clk_u0_sd_card(&self) -> &CLK_U0_SD_CARD { + &self.clk_u0_sd_card + } #[doc = "0x178 - U1 SD Card Clock"] - pub clk_u1_sd_card: CLK_U1_SD_CARD, + #[inline(always)] + pub const fn clk_u1_sd_card(&self) -> &CLK_U1_SD_CARD { + &self.clk_u1_sd_card + } #[doc = "0x17c - Clock USB 125M"] - pub clk_usb_125m: CLK_USB_125M, + #[inline(always)] + pub const fn clk_usb_125m(&self) -> &CLK_USB_125M { + &self.clk_usb_125m + } #[doc = "0x180 - Clock NOC STG AXI"] - pub clk_noc_stg_axi: CLK_NOC_STG_AXI, + #[inline(always)] + pub const fn clk_noc_stg_axi(&self) -> &CLK_NOC_STG_AXI { + &self.clk_noc_stg_axi + } #[doc = "0x184 - Clock GMAC 5 AXI 64 AHB"] - pub clk_gmac5_axi64_ahb: CLK_GMAC5_AXI64_AHB, + #[inline(always)] + pub const fn clk_gmac5_axi64_ahb(&self) -> &CLK_GMAC5_AXI64_AHB { + &self.clk_gmac5_axi64_ahb + } #[doc = "0x188 - Clock GMAC 5 AXI 64 AXI"] - pub clk_gmac5_axi64_axi: CLK_GMAC5_AXI64_AXI, + #[inline(always)] + pub const fn clk_gmac5_axi64_axi(&self) -> &CLK_GMAC5_AXI64_AXI { + &self.clk_gmac5_axi64_axi + } #[doc = "0x18c - Clock GMAC Source"] - pub clk_gmac_src: CLK_GMAC_SRC, + #[inline(always)] + pub const fn clk_gmac_src(&self) -> &CLK_GMAC_SRC { + &self.clk_gmac_src + } #[doc = "0x190 - Clock GMAC 1 GTX"] - pub clk_gmac1_gtx: CLK_GMAC1_GTX, + #[inline(always)] + pub const fn clk_gmac1_gtx(&self) -> &CLK_GMAC1_GTX { + &self.clk_gmac1_gtx + } #[doc = "0x194 - Clock GMAC 1 RMII RTX"] - pub clk_gmac1_rmii_rtx: CLK_GMAC1_RMII_RTX, + #[inline(always)] + pub const fn clk_gmac1_rmii_rtx(&self) -> &CLK_GMAC1_RMII_RTX { + &self.clk_gmac1_rmii_rtx + } #[doc = "0x198 - Clock GMAC 5 AXI 64 PTP"] - pub clk_gmac5_axi64_ptp: CLK_GMAC5_AXI64_PTP, + #[inline(always)] + pub const fn clk_gmac5_axi64_ptp(&self) -> &CLK_GMAC5_AXI64_PTP { + &self.clk_gmac5_axi64_ptp + } #[doc = "0x19c - Clock GMAC 5 AXI 64 RX"] - pub clk_gmac5_axi64_rx: CLK_GMAC5_AXI64_RX, + #[inline(always)] + pub const fn clk_gmac5_axi64_rx(&self) -> &CLK_GMAC5_AXI64_RX { + &self.clk_gmac5_axi64_rx + } #[doc = "0x1a0 - Clock GMAC 5 AXI 64 RX Inverter"] - pub clk_gmac5_axi64_rxi: CLK_GMAC5_AXI64_RXI, + #[inline(always)] + pub const fn clk_gmac5_axi64_rxi(&self) -> &CLK_GMAC5_AXI64_RXI { + &self.clk_gmac5_axi64_rxi + } #[doc = "0x1a4 - Clock GMAC 5 AXI 64 TX"] - pub clk_gmac5_axi64_tx: CLK_GMAC5_AXI64_TX, + #[inline(always)] + pub const fn clk_gmac5_axi64_tx(&self) -> &CLK_GMAC5_AXI64_TX { + &self.clk_gmac5_axi64_tx + } #[doc = "0x1a8 - Clock GMAC 5 AXI 64 TX Inverter"] - pub clk_gmac5_axi64_txi: CLK_GMAC5_AXI64_TXI, + #[inline(always)] + pub const fn clk_gmac5_axi64_txi(&self) -> &CLK_GMAC5_AXI64_TXI { + &self.clk_gmac5_axi64_txi + } #[doc = "0x1ac - Clock GMAC 1 GTXC"] - pub clk_gmac1_gtxclk: CLK_GMAC1_GTXCLK, + #[inline(always)] + pub const fn clk_gmac1_gtxclk(&self) -> &CLK_GMAC1_GTXCLK { + &self.clk_gmac1_gtxclk + } #[doc = "0x1b0 - Clock GMAC 0 GTX"] - pub clk_gmac0_gtx: CLK_GMAC0_GTX, + #[inline(always)] + pub const fn clk_gmac0_gtx(&self) -> &CLK_GMAC0_GTX { + &self.clk_gmac0_gtx + } #[doc = "0x1b4 - Clock GMAC 0 PTP"] - pub clk_gmac0_ptp: CLK_GMAC0_PTP, + #[inline(always)] + pub const fn clk_gmac0_ptp(&self) -> &CLK_GMAC0_PTP { + &self.clk_gmac0_ptp + } #[doc = "0x1b8 - Clock GMAC PHY"] - pub clk_gmac_phy: CLK_GMAC_PHY, + #[inline(always)] + pub const fn clk_gmac_phy(&self) -> &CLK_GMAC_PHY { + &self.clk_gmac_phy + } #[doc = "0x1bc - Clock GMAC 0 GTXC"] - pub clk_gmac0_gtxclk: CLK_GMAC0_GTXCLK, + #[inline(always)] + pub const fn clk_gmac0_gtxclk(&self) -> &CLK_GMAC0_GTXCLK { + &self.clk_gmac0_gtxclk + } #[doc = "0x1c0 - Clock SYS IOMUX PCLK"] - pub clk_sys_iomux_pclk: CLK_SYS_IOMUX_PCLK, + #[inline(always)] + pub const fn clk_sys_iomux_pclk(&self) -> &CLK_SYS_IOMUX_PCLK { + &self.clk_sys_iomux_pclk + } #[doc = "0x1c4 - Clock Mailbox APB"] - pub clk_mbox_apb: CLK_MBOX_APB, + #[inline(always)] + pub const fn clk_mbox_apb(&self) -> &CLK_MBOX_APB { + &self.clk_mbox_apb + } #[doc = "0x1c8 - Clock Internal Controller APB"] - pub clk_internal_ctrl_apb: CLK_INTERNAL_CTRL_APB, + #[inline(always)] + pub const fn clk_internal_ctrl_apb(&self) -> &CLK_INTERNAL_CTRL_APB { + &self.clk_internal_ctrl_apb + } #[doc = "0x1cc - U0 Clock CAN Controller APB"] - pub clk_u0_can_ctrl_apb: CLK_U0_CAN_CTRL_APB, + #[inline(always)] + pub const fn clk_u0_can_ctrl_apb(&self) -> &CLK_U0_CAN_CTRL_APB { + &self.clk_u0_can_ctrl_apb + } #[doc = "0x1d0 - U0 Clock CAN Controller Timer"] - pub clk_u0_can_ctrl_tim: CLK_U0_CAN_CTRL_TIM, + #[inline(always)] + pub const fn clk_u0_can_ctrl_tim(&self) -> &CLK_U0_CAN_CTRL_TIM { + &self.clk_u0_can_ctrl_tim + } #[doc = "0x1d4 - U0 Clock CAN Controller CAN"] - pub clk_u0_can_ctrl_can: CLK_U0_CAN_CTRL_CAN, + #[inline(always)] + pub const fn clk_u0_can_ctrl_can(&self) -> &CLK_U0_CAN_CTRL_CAN { + &self.clk_u0_can_ctrl_can + } #[doc = "0x1d8 - U1 Clock CAN Controller APB"] - pub clk_u1_can_ctrl_apb: CLK_U1_CAN_CTRL_APB, + #[inline(always)] + pub const fn clk_u1_can_ctrl_apb(&self) -> &CLK_U1_CAN_CTRL_APB { + &self.clk_u1_can_ctrl_apb + } #[doc = "0x1dc - U1 Clock CAN Controller Timer"] - pub clk_u1_can_ctrl_tim: CLK_U1_CAN_CTRL_TIM, + #[inline(always)] + pub const fn clk_u1_can_ctrl_tim(&self) -> &CLK_U1_CAN_CTRL_TIM { + &self.clk_u1_can_ctrl_tim + } #[doc = "0x1e0 - U1 Clock CAN Controller CAN"] - pub clk_u1_can_ctrl_can: CLK_U1_CAN_CTRL_CAN, + #[inline(always)] + pub const fn clk_u1_can_ctrl_can(&self) -> &CLK_U1_CAN_CTRL_CAN { + &self.clk_u1_can_ctrl_can + } #[doc = "0x1e4 - Clock PWM APB"] - pub clk_pwm_apb: CLK_PWM_APB, + #[inline(always)] + pub const fn clk_pwm_apb(&self) -> &CLK_PWM_APB { + &self.clk_pwm_apb + } #[doc = "0x1e8 - Clock WDT APB"] - pub clk_wdt_apb: CLK_WDT_APB, + #[inline(always)] + pub const fn clk_wdt_apb(&self) -> &CLK_WDT_APB { + &self.clk_wdt_apb + } #[doc = "0x1ec - Clock WDT"] - pub clk_wdt: CLK_WDT, + #[inline(always)] + pub const fn clk_wdt(&self) -> &CLK_WDT { + &self.clk_wdt + } #[doc = "0x1f0 - Clock Timer APB"] - pub clk_tim_apb: CLK_TIM_APB, + #[inline(always)] + pub const fn clk_tim_apb(&self) -> &CLK_TIM_APB { + &self.clk_tim_apb + } #[doc = "0x1f4 - Clock Timer 0"] - pub clk_tim0: CLK_TIM0, + #[inline(always)] + pub const fn clk_tim0(&self) -> &CLK_TIM0 { + &self.clk_tim0 + } #[doc = "0x1f8 - Clock Timer 1"] - pub clk_tim1: CLK_TIM1, + #[inline(always)] + pub const fn clk_tim1(&self) -> &CLK_TIM1 { + &self.clk_tim1 + } #[doc = "0x1fc - Clock Timer 2"] - pub clk_tim2: CLK_TIM2, + #[inline(always)] + pub const fn clk_tim2(&self) -> &CLK_TIM2 { + &self.clk_tim2 + } #[doc = "0x200 - Clock Timer 3"] - pub clk_tim3: CLK_TIM3, + #[inline(always)] + pub const fn clk_tim3(&self) -> &CLK_TIM3 { + &self.clk_tim3 + } #[doc = "0x204 - Clock Temperature Sensor APB"] - pub clk_temp_sensor_apb: CLK_TEMP_SENSOR_APB, + #[inline(always)] + pub const fn clk_temp_sensor_apb(&self) -> &CLK_TEMP_SENSOR_APB { + &self.clk_temp_sensor_apb + } #[doc = "0x208 - Clock Temperature Sensor"] - pub clk_temp_sensor: CLK_TEMP_SENSOR, + #[inline(always)] + pub const fn clk_temp_sensor(&self) -> &CLK_TEMP_SENSOR { + &self.clk_temp_sensor + } #[doc = "0x20c - U0 Clock SPI APB"] - pub clk_u0_spi_apb: CLK_U0_SPI_APB, + #[inline(always)] + pub const fn clk_u0_spi_apb(&self) -> &CLK_U0_SPI_APB { + &self.clk_u0_spi_apb + } #[doc = "0x210 - U1 Clock SPI APB"] - pub clk_u1_spi_apb: CLK_U1_SPI_APB, + #[inline(always)] + pub const fn clk_u1_spi_apb(&self) -> &CLK_U1_SPI_APB { + &self.clk_u1_spi_apb + } #[doc = "0x214 - U2 Clock SPI APB"] - pub clk_u2_spi_apb: CLK_U2_SPI_APB, + #[inline(always)] + pub const fn clk_u2_spi_apb(&self) -> &CLK_U2_SPI_APB { + &self.clk_u2_spi_apb + } #[doc = "0x218 - U3 Clock SPI APB"] - pub clk_u3_spi_apb: CLK_U3_SPI_APB, + #[inline(always)] + pub const fn clk_u3_spi_apb(&self) -> &CLK_U3_SPI_APB { + &self.clk_u3_spi_apb + } #[doc = "0x21c - U4 Clock SPI APB"] - pub clk_u4_spi_apb: CLK_U4_SPI_APB, + #[inline(always)] + pub const fn clk_u4_spi_apb(&self) -> &CLK_U4_SPI_APB { + &self.clk_u4_spi_apb + } #[doc = "0x220 - U5 Clock SPI APB"] - pub clk_u5_spi_apb: CLK_U5_SPI_APB, + #[inline(always)] + pub const fn clk_u5_spi_apb(&self) -> &CLK_U5_SPI_APB { + &self.clk_u5_spi_apb + } #[doc = "0x224 - U6 Clock SPI APB"] - pub clk_u6_spi_apb: CLK_U6_SPI_APB, + #[inline(always)] + pub const fn clk_u6_spi_apb(&self) -> &CLK_U6_SPI_APB { + &self.clk_u6_spi_apb + } #[doc = "0x228 - U0 Clock I2C APB"] - pub clk_u0_i2c_apb: CLK_U0_I2C_APB, + #[inline(always)] + pub const fn clk_u0_i2c_apb(&self) -> &CLK_U0_I2C_APB { + &self.clk_u0_i2c_apb + } #[doc = "0x22c - U1 Clock I2C APB"] - pub clk_u1_i2c_apb: CLK_U1_I2C_APB, + #[inline(always)] + pub const fn clk_u1_i2c_apb(&self) -> &CLK_U1_I2C_APB { + &self.clk_u1_i2c_apb + } #[doc = "0x230 - U2 Clock I2C APB"] - pub clk_u2_i2c_apb: CLK_U2_I2C_APB, + #[inline(always)] + pub const fn clk_u2_i2c_apb(&self) -> &CLK_U2_I2C_APB { + &self.clk_u2_i2c_apb + } #[doc = "0x234 - U3 Clock I2C APB"] - pub clk_u3_i2c_apb: CLK_U3_I2C_APB, + #[inline(always)] + pub const fn clk_u3_i2c_apb(&self) -> &CLK_U3_I2C_APB { + &self.clk_u3_i2c_apb + } #[doc = "0x238 - U4 Clock I2C APB"] - pub clk_u4_i2c_apb: CLK_U4_I2C_APB, + #[inline(always)] + pub const fn clk_u4_i2c_apb(&self) -> &CLK_U4_I2C_APB { + &self.clk_u4_i2c_apb + } #[doc = "0x23c - U5 Clock I2C APB"] - pub clk_u5_i2c_apb: CLK_U5_I2C_APB, + #[inline(always)] + pub const fn clk_u5_i2c_apb(&self) -> &CLK_U5_I2C_APB { + &self.clk_u5_i2c_apb + } #[doc = "0x240 - U6 Clock I2C APB"] - pub clk_u6_i2c_apb: CLK_U6_I2C_APB, + #[inline(always)] + pub const fn clk_u6_i2c_apb(&self) -> &CLK_U6_I2C_APB { + &self.clk_u6_i2c_apb + } #[doc = "0x244 - U0 Clock UART APB"] - pub clk_u0_uart_apb: CLK_U0_UART_APB, + #[inline(always)] + pub const fn clk_u0_uart_apb(&self) -> &CLK_U0_UART_APB { + &self.clk_u0_uart_apb + } #[doc = "0x248 - U0 Clock UART Core"] - pub clk_u0_uart_core: CLK_U0_UART_CORE, + #[inline(always)] + pub const fn clk_u0_uart_core(&self) -> &CLK_U0_UART_CORE { + &self.clk_u0_uart_core + } #[doc = "0x24c - U1 Clock UART APB"] - pub clk_u1_uart_apb: CLK_U1_UART_APB, + #[inline(always)] + pub const fn clk_u1_uart_apb(&self) -> &CLK_U1_UART_APB { + &self.clk_u1_uart_apb + } #[doc = "0x250 - U1 Clock UART Core"] - pub clk_u1_uart_core: CLK_U1_UART_CORE, + #[inline(always)] + pub const fn clk_u1_uart_core(&self) -> &CLK_U1_UART_CORE { + &self.clk_u1_uart_core + } #[doc = "0x254 - U2 Clock UART APB"] - pub clk_u2_uart_apb: CLK_U2_UART_APB, + #[inline(always)] + pub const fn clk_u2_uart_apb(&self) -> &CLK_U2_UART_APB { + &self.clk_u2_uart_apb + } #[doc = "0x258 - U2 Clock UART Core"] - pub clk_u2_uart_core: CLK_U2_UART_CORE, + #[inline(always)] + pub const fn clk_u2_uart_core(&self) -> &CLK_U2_UART_CORE { + &self.clk_u2_uart_core + } #[doc = "0x25c - U3 Clock UART APB"] - pub clk_u3_uart_apb: CLK_U3_UART_APB, + #[inline(always)] + pub const fn clk_u3_uart_apb(&self) -> &CLK_U3_UART_APB { + &self.clk_u3_uart_apb + } #[doc = "0x260 - U3 Clock UART Core"] - pub clk_u3_uart_core: CLK_U3_UART_CORE, + #[inline(always)] + pub const fn clk_u3_uart_core(&self) -> &CLK_U3_UART_CORE { + &self.clk_u3_uart_core + } #[doc = "0x264 - U4 Clock UART APB"] - pub clk_u4_uart_apb: CLK_U4_UART_APB, + #[inline(always)] + pub const fn clk_u4_uart_apb(&self) -> &CLK_U4_UART_APB { + &self.clk_u4_uart_apb + } #[doc = "0x268 - U4 Clock UART Core"] - pub clk_u4_uart_core: CLK_U4_UART_CORE, + #[inline(always)] + pub const fn clk_u4_uart_core(&self) -> &CLK_U4_UART_CORE { + &self.clk_u4_uart_core + } #[doc = "0x26c - U5 Clock UART APB"] - pub clk_u5_uart_apb: CLK_U5_UART_APB, + #[inline(always)] + pub const fn clk_u5_uart_apb(&self) -> &CLK_U5_UART_APB { + &self.clk_u5_uart_apb + } #[doc = "0x270 - U5 Clock UART Core"] - pub clk_u5_uart_core: CLK_U5_UART_CORE, + #[inline(always)] + pub const fn clk_u5_uart_core(&self) -> &CLK_U5_UART_CORE { + &self.clk_u5_uart_core + } #[doc = "0x274 - Clock PWMDAC APB"] - pub clk_pwmdac_apb: CLK_PWMDAC_APB, + #[inline(always)] + pub const fn clk_pwmdac_apb(&self) -> &CLK_PWMDAC_APB { + &self.clk_pwmdac_apb + } #[doc = "0x278 - Clock PWMDAC Core"] - pub clk_pwmdac_core: CLK_PWMDAC_CORE, + #[inline(always)] + pub const fn clk_pwmdac_core(&self) -> &CLK_PWMDAC_CORE { + &self.clk_pwmdac_core + } #[doc = "0x27c - Clock SPDIF APB"] - pub clk_spdif_apb: CLK_SPDIF_APB, + #[inline(always)] + pub const fn clk_spdif_apb(&self) -> &CLK_SPDIF_APB { + &self.clk_spdif_apb + } #[doc = "0x280 - Clock SPDIF Core"] - pub clk_spdif_core: CLK_SPDIF_CORE, + #[inline(always)] + pub const fn clk_spdif_core(&self) -> &CLK_SPDIF_CORE { + &self.clk_spdif_core + } #[doc = "0x284 - U0 Clock I2S TX APB"] - pub clk_u0_i2s_tx_apb: CLK_U0_I2S_TX_APB, + #[inline(always)] + pub const fn clk_u0_i2s_tx_apb(&self) -> &CLK_U0_I2S_TX_APB { + &self.clk_u0_i2s_tx_apb + } #[doc = "0x288 - U0 Clock I2S TX 0 BCLK MST"] - pub clk_u0_i2stx_4ch0_bclk_mst: CLK_U0_I2STX_4CH0_BCLK_MST, + #[inline(always)] + pub const fn clk_u0_i2stx_4ch0_bclk_mst(&self) -> &CLK_U0_I2STX_4CH0_BCLK_MST { + &self.clk_u0_i2stx_4ch0_bclk_mst + } #[doc = "0x28c - U0 Clock I2S TX 0 BCLK MST Inverter"] - pub clk_u0_i2stx_4ch0_bclk_mst_inv: CLK_U0_I2STX_4CH0_BCLK_MST_INV, + #[inline(always)] + pub const fn clk_u0_i2stx_4ch0_bclk_mst_inv(&self) -> &CLK_U0_I2STX_4CH0_BCLK_MST_INV { + &self.clk_u0_i2stx_4ch0_bclk_mst_inv + } #[doc = "0x290 - Clock I2S TX 0 LRCK MST"] - pub clk_i2stx0_lrck_mst: CLK_I2STX0_LRCK_MST, + #[inline(always)] + pub const fn clk_i2stx0_lrck_mst(&self) -> &CLK_I2STX0_LRCK_MST { + &self.clk_i2stx0_lrck_mst + } #[doc = "0x294 - U0 Clock I2S TX BCLK"] - pub clk_u0_i2stx_bclk: CLK_U0_I2STX_BCLK, + #[inline(always)] + pub const fn clk_u0_i2stx_bclk(&self) -> &CLK_U0_I2STX_BCLK { + &self.clk_u0_i2stx_bclk + } #[doc = "0x298 - U0 Clock I2S TX BCLK Negative"] - pub clk_u0_i2stx_bclk_neg: CLK_U0_I2STX_BCLK_NEG, + #[inline(always)] + pub const fn clk_u0_i2stx_bclk_neg(&self) -> &CLK_U0_I2STX_BCLK_NEG { + &self.clk_u0_i2stx_bclk_neg + } #[doc = "0x29c - U0 Clock I2S TX LRCK"] - pub clk_u0_i2stx_lrck: CLK_U0_I2STX_LRCK, + #[inline(always)] + pub const fn clk_u0_i2stx_lrck(&self) -> &CLK_U0_I2STX_LRCK { + &self.clk_u0_i2stx_lrck + } #[doc = "0x2a0 - U1 Clock I2S TX APB"] - pub clk_u1_i2s_tx_apb: CLK_U1_I2S_TX_APB, + #[inline(always)] + pub const fn clk_u1_i2s_tx_apb(&self) -> &CLK_U1_I2S_TX_APB { + &self.clk_u1_i2s_tx_apb + } #[doc = "0x2a4 - U1 Clock I2S TX 1 BCLK MST"] - pub clk_u1_i2stx_4ch1_bclk_mst: CLK_U1_I2STX_4CH1_BCLK_MST, + #[inline(always)] + pub const fn clk_u1_i2stx_4ch1_bclk_mst(&self) -> &CLK_U1_I2STX_4CH1_BCLK_MST { + &self.clk_u1_i2stx_4ch1_bclk_mst + } #[doc = "0x2a8 - U1 Clock I2S TX 1 BCLK MST Inverter"] - pub clk_u1_i2stx_4ch1_bclk_mst_inv: CLK_U1_I2STX_4CH1_BCLK_MST_INV, + #[inline(always)] + pub const fn clk_u1_i2stx_4ch1_bclk_mst_inv(&self) -> &CLK_U1_I2STX_4CH1_BCLK_MST_INV { + &self.clk_u1_i2stx_4ch1_bclk_mst_inv + } #[doc = "0x2ac - Clock I2S TX 1 LRCK MST"] - pub clk_i2stx1_lrck_mst: CLK_I2STX1_LRCK_MST, + #[inline(always)] + pub const fn clk_i2stx1_lrck_mst(&self) -> &CLK_I2STX1_LRCK_MST { + &self.clk_i2stx1_lrck_mst + } #[doc = "0x2b0 - U1 Clock I2S TX BCLK"] - pub clk_u1_i2stx_bclk: CLK_U1_I2STX_BCLK, + #[inline(always)] + pub const fn clk_u1_i2stx_bclk(&self) -> &CLK_U1_I2STX_BCLK { + &self.clk_u1_i2stx_bclk + } #[doc = "0x2b4 - U1 Clock I2S TX BCLK Negative"] - pub clk_u1_i2stx_bclk_neg: CLK_U1_I2STX_BCLK_NEG, + #[inline(always)] + pub const fn clk_u1_i2stx_bclk_neg(&self) -> &CLK_U1_I2STX_BCLK_NEG { + &self.clk_u1_i2stx_bclk_neg + } #[doc = "0x2b8 - U1 Clock I2S TX LRCK"] - pub clk_u1_i2stx_lrck: CLK_U1_I2STX_LRCK, + #[inline(always)] + pub const fn clk_u1_i2stx_lrck(&self) -> &CLK_U1_I2STX_LRCK { + &self.clk_u1_i2stx_lrck + } #[doc = "0x2bc - Clock I2S APB"] - pub clk_i2s_apb: CLK_I2S_APB, + #[inline(always)] + pub const fn clk_i2s_apb(&self) -> &CLK_I2S_APB { + &self.clk_i2s_apb + } #[doc = "0x2c0 - Clock I2S BCLK MST"] - pub clk_i2s_bclk_mst: CLK_I2S_BCLK_MST, + #[inline(always)] + pub const fn clk_i2s_bclk_mst(&self) -> &CLK_I2S_BCLK_MST { + &self.clk_i2s_bclk_mst + } #[doc = "0x2c4 - Clock I2S BCLK MST Inverter"] - pub clk_i2s_bclk_mst_inv: CLK_I2S_BCLK_MST_INV, + #[inline(always)] + pub const fn clk_i2s_bclk_mst_inv(&self) -> &CLK_I2S_BCLK_MST_INV { + &self.clk_i2s_bclk_mst_inv + } #[doc = "0x2c8 - Clock I2S LRCK MST"] - pub clk_i2s_lrck_mst: CLK_I2S_LRCK_MST, + #[inline(always)] + pub const fn clk_i2s_lrck_mst(&self) -> &CLK_I2S_LRCK_MST { + &self.clk_i2s_lrck_mst + } #[doc = "0x2cc - Clock I2S BCLK"] - pub clk_i2s_bclk: CLK_I2S_BCLK, + #[inline(always)] + pub const fn clk_i2s_bclk(&self) -> &CLK_I2S_BCLK { + &self.clk_i2s_bclk + } #[doc = "0x2d0 - Clock I2S BCLK Negative"] - pub clk_i2s_bclk_neg: CLK_I2S_BCLK_NEG, + #[inline(always)] + pub const fn clk_i2s_bclk_neg(&self) -> &CLK_I2S_BCLK_NEG { + &self.clk_i2s_bclk_neg + } #[doc = "0x2d4 - Clock I2S LRCK"] - pub clk_i2s_lrck: CLK_I2S_LRCK, + #[inline(always)] + pub const fn clk_i2s_lrck(&self) -> &CLK_I2S_LRCK { + &self.clk_i2s_lrck + } #[doc = "0x2d8 - Clock PDM DMIC"] - pub clk_pdm_dmic: CLK_PDM_DMIC, + #[inline(always)] + pub const fn clk_pdm_dmic(&self) -> &CLK_PDM_DMIC { + &self.clk_pdm_dmic + } #[doc = "0x2dc - Clock PDM APB"] - pub clk_pdm_apb: CLK_PDM_APB, + #[inline(always)] + pub const fn clk_pdm_apb(&self) -> &CLK_PDM_APB { + &self.clk_pdm_apb + } #[doc = "0x2e0 - Clock TDM AHB"] - pub clk_tdm_ahb: CLK_TDM_AHB, + #[inline(always)] + pub const fn clk_tdm_ahb(&self) -> &CLK_TDM_AHB { + &self.clk_tdm_ahb + } #[doc = "0x2e4 - Clock TDM APB"] - pub clk_tdm_apb: CLK_TDM_APB, + #[inline(always)] + pub const fn clk_tdm_apb(&self) -> &CLK_TDM_APB { + &self.clk_tdm_apb + } #[doc = "0x2e8 - Clock TDM Internal"] - pub clk_tdm_internal: CLK_TDM_INTERNAL, + #[inline(always)] + pub const fn clk_tdm_internal(&self) -> &CLK_TDM_INTERNAL { + &self.clk_tdm_internal + } #[doc = "0x2ec - Clock TDM"] - pub clk_tdm: CLK_TDM, + #[inline(always)] + pub const fn clk_tdm(&self) -> &CLK_TDM { + &self.clk_tdm + } #[doc = "0x2f0 - Clock TDM Negative"] - pub clk_tdm_neg: CLK_TDM_NEG, + #[inline(always)] + pub const fn clk_tdm_neg(&self) -> &CLK_TDM_NEG { + &self.clk_tdm_neg + } #[doc = "0x2f4 - Clock JTAG Certification TRNG"] - pub clk_jtag_cert_trng: CLK_JTAG_CERT_TRNG, + #[inline(always)] + pub const fn clk_jtag_cert_trng(&self) -> &CLK_JTAG_CERT_TRNG { + &self.clk_jtag_cert_trng + } #[doc = "0x2f8 - Software RESET 0 Address Selector"] - pub soft_rst0_addr_sel: SOFT_RST0_ADDR_SEL, + #[inline(always)] + pub const fn soft_rst0_addr_sel(&self) -> &SOFT_RST0_ADDR_SEL { + &self.soft_rst0_addr_sel + } #[doc = "0x2fc - Software RESET 1 Address Selector"] - pub soft_rst1_addr_sel: SOFT_RST1_ADDR_SEL, + #[inline(always)] + pub const fn soft_rst1_addr_sel(&self) -> &SOFT_RST1_ADDR_SEL { + &self.soft_rst1_addr_sel + } #[doc = "0x300 - Software RESET 2 Address Selector"] - pub soft_rst2_addr_sel: SOFT_RST2_ADDR_SEL, + #[inline(always)] + pub const fn soft_rst2_addr_sel(&self) -> &SOFT_RST2_ADDR_SEL { + &self.soft_rst2_addr_sel + } #[doc = "0x304 - Software RESET 3 Address Selector"] - pub soft_rst3_addr_sel: SOFT_RST3_ADDR_SEL, + #[inline(always)] + pub const fn soft_rst3_addr_sel(&self) -> &SOFT_RST3_ADDR_SEL { + &self.soft_rst3_addr_sel + } #[doc = "0x308 - SYSCRG RESET Status 0"] - pub syscrg_rst0_status: SYSCRG_RST0_STATUS, + #[inline(always)] + pub const fn syscrg_rst0_status(&self) -> &SYSCRG_RST0_STATUS { + &self.syscrg_rst0_status + } #[doc = "0x30c - SYSCRG RESET Status 1"] - pub syscrg_rst1_status: SYSCRG_RST1_STATUS, + #[inline(always)] + pub const fn syscrg_rst1_status(&self) -> &SYSCRG_RST1_STATUS { + &self.syscrg_rst1_status + } #[doc = "0x310 - SYSCRG RESET Status 2"] - pub syscrg_rst2_status: SYSCRG_RST2_STATUS, + #[inline(always)] + pub const fn syscrg_rst2_status(&self) -> &SYSCRG_RST2_STATUS { + &self.syscrg_rst2_status + } #[doc = "0x314 - SYSCRG RESET Status 3"] - pub syscrg_rst3_status: SYSCRG_RST3_STATUS, + #[inline(always)] + pub const fn syscrg_rst3_status(&self) -> &SYSCRG_RST3_STATUS { + &self.syscrg_rst3_status + } } -#[doc = "clk_cpu_root (rw) register accessor: Clock CPU Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cpu_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cpu_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_cpu_root`] +#[doc = "clk_cpu_root (rw) register accessor: Clock CPU Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cpu_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cpu_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_cpu_root`] module"] pub type CLK_CPU_ROOT = crate::Reg; #[doc = "Clock CPU Root"] pub mod clk_cpu_root; -#[doc = "clk_cpu_core (rw) register accessor: Clock CPU Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cpu_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cpu_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_cpu_core`] +#[doc = "clk_cpu_core (rw) register accessor: Clock CPU Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cpu_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cpu_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_cpu_core`] module"] pub type CLK_CPU_CORE = crate::Reg; #[doc = "Clock CPU Core"] pub mod clk_cpu_core; -#[doc = "clk_cpu_bus (rw) register accessor: Clock CPU Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cpu_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cpu_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_cpu_bus`] +#[doc = "clk_cpu_bus (rw) register accessor: Clock CPU Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cpu_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cpu_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_cpu_bus`] module"] pub type CLK_CPU_BUS = crate::Reg; #[doc = "Clock CPU Bus"] pub mod clk_cpu_bus; -#[doc = "clk_gpu_root (rw) register accessor: Clock GPU Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gpu_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpu_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gpu_root`] +#[doc = "clk_gpu_root (rw) register accessor: Clock GPU Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gpu_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpu_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gpu_root`] module"] pub type CLK_GPU_ROOT = crate::Reg; #[doc = "Clock GPU Root"] pub mod clk_gpu_root; -#[doc = "clk_peripheral_root (rw) register accessor: Clock Peripheral Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_peripheral_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_peripheral_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_peripheral_root`] +#[doc = "clk_peripheral_root (rw) register accessor: Clock Peripheral Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_peripheral_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_peripheral_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_peripheral_root`] module"] pub type CLK_PERIPHERAL_ROOT = crate::Reg; #[doc = "Clock Peripheral Root"] pub mod clk_peripheral_root; -#[doc = "clk_bus_root (rw) register accessor: Clock Bus Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_bus_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_bus_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_bus_root`] +#[doc = "clk_bus_root (rw) register accessor: Clock Bus Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_bus_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_bus_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_bus_root`] module"] pub type CLK_BUS_ROOT = crate::Reg; #[doc = "Clock Bus Root"] pub mod clk_bus_root; -#[doc = "clk_nocstg_bus (rw) register accessor: Clock NOCSTG Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_nocstg_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_nocstg_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_nocstg_bus`] +#[doc = "clk_nocstg_bus (rw) register accessor: Clock NOCSTG Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_nocstg_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_nocstg_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_nocstg_bus`] module"] pub type CLK_NOCSTG_BUS = crate::Reg; #[doc = "Clock NOCSTG Bus"] pub mod clk_nocstg_bus; -#[doc = "clk_axi_cfg0 (rw) register accessor: Clock AXI Configuration 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_cfg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_axi_cfg0`] +#[doc = "clk_axi_cfg0 (rw) register accessor: Clock AXI Configuration 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_cfg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_axi_cfg0`] module"] pub type CLK_AXI_CFG0 = crate::Reg; #[doc = "Clock AXI Configuration 0"] pub mod clk_axi_cfg0; -#[doc = "clk_stg_axiahb (rw) register accessor: Clock STG AXI AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_axiahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_axiahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_stg_axiahb`] +#[doc = "clk_stg_axiahb (rw) register accessor: Clock STG AXI AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_stg_axiahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_stg_axiahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_stg_axiahb`] module"] pub type CLK_STG_AXIAHB = crate::Reg; #[doc = "Clock STG AXI AHB"] pub mod clk_stg_axiahb; -#[doc = "clk_ahb0 (rw) register accessor: Clock AHB 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ahb0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ahb0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_ahb0`] +#[doc = "clk_ahb0 (rw) register accessor: Clock AHB 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ahb0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ahb0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_ahb0`] module"] pub type CLK_AHB0 = crate::Reg; #[doc = "Clock AHB 0"] pub mod clk_ahb0; -#[doc = "clk_ahb1 (rw) register accessor: Clock AHB 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ahb1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ahb1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_ahb1`] +#[doc = "clk_ahb1 (rw) register accessor: Clock AHB 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ahb1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ahb1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_ahb1`] module"] pub type CLK_AHB1 = crate::Reg; #[doc = "Clock AHB 1"] pub mod clk_ahb1; -#[doc = "clk_apb_bus (rw) register accessor: Clock APB Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_apb_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_apb_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_apb_bus`] +#[doc = "clk_apb_bus (rw) register accessor: Clock APB Bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_apb_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_apb_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_apb_bus`] module"] pub type CLK_APB_BUS = crate::Reg; #[doc = "Clock APB Bus"] pub mod clk_apb_bus; -#[doc = "clk_apb0 (rw) register accessor: Clock APB 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_apb0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_apb0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_apb0`] +#[doc = "clk_apb0 (rw) register accessor: Clock APB 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_apb0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_apb0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_apb0`] module"] pub type CLK_APB0 = crate::Reg; #[doc = "Clock APB 0"] pub mod clk_apb0; -#[doc = "clk_pll0_div2 (rw) register accessor: Clock PLL 0 Divider 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll0_div2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll0_div2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pll0_div2`] +#[doc = "clk_pll0_div2 (rw) register accessor: Clock PLL 0 Divider 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll0_div2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll0_div2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pll0_div2`] module"] pub type CLK_PLL0_DIV2 = crate::Reg; #[doc = "Clock PLL 0 Divider 2"] pub mod clk_pll0_div2; -#[doc = "clk_pll1_div2 (rw) register accessor: Clock PLL 1 Divider 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll1_div2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll1_div2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pll1_div2`] +#[doc = "clk_pll1_div2 (rw) register accessor: Clock PLL 1 Divider 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll1_div2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll1_div2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pll1_div2`] module"] pub type CLK_PLL1_DIV2 = crate::Reg; #[doc = "Clock PLL 1 Divider 2"] pub mod clk_pll1_div2; -#[doc = "clk_pll2_div2 (rw) register accessor: Clock PLL 2 Divider 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll2_div2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll2_div2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pll2_div2`] +#[doc = "clk_pll2_div2 (rw) register accessor: Clock PLL 2 Divider 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll2_div2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll2_div2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pll2_div2`] module"] pub type CLK_PLL2_DIV2 = crate::Reg; #[doc = "Clock PLL 2 Divider 2"] pub mod clk_pll2_div2; -#[doc = "clk_audio_root (rw) register accessor: Clock Audio Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_audio_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_audio_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_audio_root`] +#[doc = "clk_audio_root (rw) register accessor: Clock Audio Root\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_audio_root::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_audio_root::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_audio_root`] module"] pub type CLK_AUDIO_ROOT = crate::Reg; #[doc = "Clock Audio Root"] pub mod clk_audio_root; -#[doc = "clk_mclk_inner (rw) register accessor: Clock MCLK Inner\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_mclk_inner::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_mclk_inner::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_mclk_inner`] +#[doc = "clk_mclk_inner (rw) register accessor: Clock MCLK Inner\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_mclk_inner::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_mclk_inner::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_mclk_inner`] module"] pub type CLK_MCLK_INNER = crate::Reg; #[doc = "Clock MCLK Inner"] pub mod clk_mclk_inner; -#[doc = "clk_mclk (rw) register accessor: Clock MCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_mclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_mclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_mclk`] +#[doc = "clk_mclk (rw) register accessor: Clock MCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_mclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_mclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_mclk`] module"] pub type CLK_MCLK = crate::Reg; #[doc = "Clock MCLK"] pub mod clk_mclk; -#[doc = "clk_mclk_out (rw) register accessor: Clock MCLK Out\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_mclk_out::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_mclk_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_mclk_out`] +#[doc = "clk_mclk_out (rw) register accessor: Clock MCLK Out\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_mclk_out::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_mclk_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_mclk_out`] module"] pub type CLK_MCLK_OUT = crate::Reg; #[doc = "Clock MCLK Out"] pub mod clk_mclk_out; -#[doc = "clk_isp_2x (rw) register accessor: Clock ISP 2x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_isp_2x::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_isp_2x::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_isp_2x`] +#[doc = "clk_isp_2x (rw) register accessor: Clock ISP 2x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_isp_2x::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_isp_2x::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_isp_2x`] module"] pub type CLK_ISP_2X = crate::Reg; #[doc = "Clock ISP 2x"] pub mod clk_isp_2x; -#[doc = "clk_isp_axi (rw) register accessor: Clock ISP AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_isp_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_isp_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_isp_axi`] +#[doc = "clk_isp_axi (rw) register accessor: Clock ISP AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_isp_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_isp_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_isp_axi`] module"] pub type CLK_ISP_AXI = crate::Reg; #[doc = "Clock ISP AXI"] pub mod clk_isp_axi; -#[doc = "clk_gclk0 (rw) register accessor: Clock GCLK 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gclk0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gclk0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gclk0`] +#[doc = "clk_gclk0 (rw) register accessor: Clock GCLK 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gclk0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gclk0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gclk0`] module"] pub type CLK_GCLK0 = crate::Reg; #[doc = "Clock GCLK 0"] pub mod clk_gclk0; -#[doc = "clk_gclk1 (rw) register accessor: Clock GCLK 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gclk1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gclk1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gclk1`] +#[doc = "clk_gclk1 (rw) register accessor: Clock GCLK 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gclk1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gclk1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gclk1`] module"] pub type CLK_GCLK1 = crate::Reg; #[doc = "Clock GCLK 1"] pub mod clk_gclk1; -#[doc = "clk_gclk2 (rw) register accessor: Clock GCLK 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gclk2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gclk2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gclk2`] +#[doc = "clk_gclk2 (rw) register accessor: Clock GCLK 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gclk2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gclk2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gclk2`] module"] pub type CLK_GCLK2 = crate::Reg; #[doc = "Clock GCLK 2"] pub mod clk_gclk2; -#[doc = "clk_u7mc_core0 (rw) register accessor: U7MC Core Clock 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_core0`] +#[doc = "clk_u7mc_core0 (rw) register accessor: U7MC Core Clock 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_core0`] module"] pub type CLK_U7MC_CORE0 = crate::Reg; #[doc = "U7MC Core Clock 0"] pub mod clk_u7mc_core0; -#[doc = "clk_u7mc_core1 (rw) register accessor: U7MC Core Clock 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_core1`] +#[doc = "clk_u7mc_core1 (rw) register accessor: U7MC Core Clock 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_core1`] module"] pub type CLK_U7MC_CORE1 = crate::Reg; #[doc = "U7MC Core Clock 1"] pub mod clk_u7mc_core1; -#[doc = "clk_u7mc_core2 (rw) register accessor: U7MC Core Clock 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_core2`] +#[doc = "clk_u7mc_core2 (rw) register accessor: U7MC Core Clock 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_core2`] module"] pub type CLK_U7MC_CORE2 = crate::Reg; #[doc = "U7MC Core Clock 2"] pub mod clk_u7mc_core2; -#[doc = "clk_u7mc_core3 (rw) register accessor: U7MC Core Clock 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_core3`] +#[doc = "clk_u7mc_core3 (rw) register accessor: U7MC Core Clock 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_core3`] module"] pub type CLK_U7MC_CORE3 = crate::Reg; #[doc = "U7MC Core Clock 3"] pub mod clk_u7mc_core3; -#[doc = "clk_u7mc_core4 (rw) register accessor: U7MC Core Clock 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_core4`] +#[doc = "clk_u7mc_core4 (rw) register accessor: U7MC Core Clock 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_core4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_core4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_core4`] module"] pub type CLK_U7MC_CORE4 = crate::Reg; #[doc = "U7MC Core Clock 4"] pub mod clk_u7mc_core4; -#[doc = "clk_u7mc_debug (rw) register accessor: U7MC Debug Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_debug::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_debug::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_debug`] +#[doc = "clk_u7mc_debug (rw) register accessor: U7MC Debug Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_debug::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_debug::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_debug`] module"] pub type CLK_U7MC_DEBUG = crate::Reg; #[doc = "U7MC Debug Clock"] pub mod clk_u7mc_debug; -#[doc = "u7mc_rtc_toggle (rw) register accessor: U7MC RTC Toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u7mc_rtc_toggle::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u7mc_rtc_toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`u7mc_rtc_toggle`] +#[doc = "u7mc_rtc_toggle (rw) register accessor: U7MC RTC Toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u7mc_rtc_toggle::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u7mc_rtc_toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@u7mc_rtc_toggle`] module"] pub type U7MC_RTC_TOGGLE = crate::Reg; #[doc = "U7MC RTC Toggle"] pub mod u7mc_rtc_toggle; -#[doc = "clk_u7mc_trace0 (rw) register accessor: U7MC Trace Clock 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_trace0`] +#[doc = "clk_u7mc_trace0 (rw) register accessor: U7MC Trace Clock 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_trace0`] module"] pub type CLK_U7MC_TRACE0 = crate::Reg; #[doc = "U7MC Trace Clock 0"] pub mod clk_u7mc_trace0; -#[doc = "clk_u7mc_trace1 (rw) register accessor: U7MC Trace Clock 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_trace1`] +#[doc = "clk_u7mc_trace1 (rw) register accessor: U7MC Trace Clock 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_trace1`] module"] pub type CLK_U7MC_TRACE1 = crate::Reg; #[doc = "U7MC Trace Clock 1"] pub mod clk_u7mc_trace1; -#[doc = "clk_u7mc_trace2 (rw) register accessor: U7MC Trace Clock 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_trace2`] +#[doc = "clk_u7mc_trace2 (rw) register accessor: U7MC Trace Clock 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_trace2`] module"] pub type CLK_U7MC_TRACE2 = crate::Reg; #[doc = "U7MC Trace Clock 2"] pub mod clk_u7mc_trace2; -#[doc = "clk_u7mc_trace3 (rw) register accessor: U7MC Trace Clock 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_trace3`] +#[doc = "clk_u7mc_trace3 (rw) register accessor: U7MC Trace Clock 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_trace3`] module"] pub type CLK_U7MC_TRACE3 = crate::Reg; #[doc = "U7MC Trace Clock 3"] pub mod clk_u7mc_trace3; -#[doc = "clk_u7mc_trace4 (rw) register accessor: U7MC Trace Clock 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_trace4`] +#[doc = "clk_u7mc_trace4 (rw) register accessor: U7MC Trace Clock 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_trace4`] module"] pub type CLK_U7MC_TRACE4 = crate::Reg; #[doc = "U7MC Trace Clock 4"] pub mod clk_u7mc_trace4; -#[doc = "clk_u7mc_trace_com (rw) register accessor: U7MC Trace Clock COM\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace_com::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace_com::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u7mc_trace_com`] +#[doc = "clk_u7mc_trace_com (rw) register accessor: U7MC Trace Clock COM\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u7mc_trace_com::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u7mc_trace_com::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u7mc_trace_com`] module"] pub type CLK_U7MC_TRACE_COM = crate::Reg; #[doc = "U7MC Trace Clock COM"] pub mod clk_u7mc_trace_com; -#[doc = "clk_u0_sft7110_noc_bus_clk_cpu_axi (rw) register accessor: clk_u0_sft7110_noc_bus_clk_cpu_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sft7110_noc_bus_clk_cpu_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sft7110_noc_bus_clk_cpu_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_sft7110_noc_bus_clk_cpu_axi`] +#[doc = "clk_u0_sft7110_noc_bus_clk_cpu_axi (rw) register accessor: clk_u0_sft7110_noc_bus_clk_cpu_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sft7110_noc_bus_clk_cpu_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sft7110_noc_bus_clk_cpu_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_sft7110_noc_bus_clk_cpu_axi`] module"] pub type CLK_U0_SFT7110_NOC_BUS_CLK_CPU_AXI = crate::Reg; #[doc = "clk_u0_sft7110_noc_bus_clk_cpu_axi"] pub mod clk_u0_sft7110_noc_bus_clk_cpu_axi; -#[doc = "clk_u0_sft7110_noc_bus_clk_axicfg0_axi (rw) register accessor: clk_u0_sft7110_noc_bus_clk_axicfg0_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sft7110_noc_bus_clk_axicfg0_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sft7110_noc_bus_clk_axicfg0_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_sft7110_noc_bus_clk_axicfg0_axi`] +#[doc = "clk_u0_sft7110_noc_bus_clk_axicfg0_axi (rw) register accessor: clk_u0_sft7110_noc_bus_clk_axicfg0_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sft7110_noc_bus_clk_axicfg0_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sft7110_noc_bus_clk_axicfg0_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_sft7110_noc_bus_clk_axicfg0_axi`] module"] pub type CLK_U0_SFT7110_NOC_BUS_CLK_AXICFG0_AXI = crate::Reg; #[doc = "clk_u0_sft7110_noc_bus_clk_axicfg0_axi"] pub mod clk_u0_sft7110_noc_bus_clk_axicfg0_axi; -#[doc = "clk_osc_div2 (rw) register accessor: clk_osc_div2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_osc_div2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_osc_div2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_osc_div2`] +#[doc = "clk_osc_div2 (rw) register accessor: clk_osc_div2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_osc_div2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_osc_div2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_osc_div2`] module"] pub type CLK_OSC_DIV2 = crate::Reg; #[doc = "clk_osc_div2"] pub mod clk_osc_div2; -#[doc = "clk_pll1_div4 (rw) register accessor: clk_pll1_div4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll1_div4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll1_div4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pll1_div4`] +#[doc = "clk_pll1_div4 (rw) register accessor: clk_pll1_div4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll1_div4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll1_div4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pll1_div4`] module"] pub type CLK_PLL1_DIV4 = crate::Reg; #[doc = "clk_pll1_div4"] pub mod clk_pll1_div4; -#[doc = "clk_pll1_div8 (rw) register accessor: clk_pll1_div8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll1_div8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll1_div8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pll1_div8`] +#[doc = "clk_pll1_div8 (rw) register accessor: clk_pll1_div8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pll1_div8::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pll1_div8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pll1_div8`] module"] pub type CLK_PLL1_DIV8 = crate::Reg; #[doc = "clk_pll1_div8"] pub mod clk_pll1_div8; -#[doc = "clk_ddr_bus (rw) register accessor: clk_ddr_bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ddr_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ddr_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_ddr_bus`] +#[doc = "clk_ddr_bus (rw) register accessor: clk_ddr_bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ddr_bus::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ddr_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_ddr_bus`] module"] pub type CLK_DDR_BUS = crate::Reg; #[doc = "clk_ddr_bus"] pub mod clk_ddr_bus; -#[doc = "clk_u0_ddr_sft7110_clk_axi (rw) register accessor: clk_u0_ddr_sfft7110_clk_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_ddr_sft7110_clk_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_ddr_sft7110_clk_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_ddr_sft7110_clk_axi`] +#[doc = "clk_u0_ddr_sft7110_clk_axi (rw) register accessor: clk_u0_ddr_sfft7110_clk_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_ddr_sft7110_clk_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_ddr_sft7110_clk_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_ddr_sft7110_clk_axi`] module"] pub type CLK_U0_DDR_SFT7110_CLK_AXI = crate::Reg; #[doc = "clk_u0_ddr_sfft7110_clk_axi"] pub mod clk_u0_ddr_sft7110_clk_axi; -#[doc = "clk_gpu_core (rw) register accessor: clk_gpu_core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gpu_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpu_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gpu_core`] +#[doc = "clk_gpu_core (rw) register accessor: clk_gpu_core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gpu_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpu_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gpu_core`] module"] pub type CLK_GPU_CORE = crate::Reg; #[doc = "clk_gpu_core"] pub mod clk_gpu_core; -#[doc = "clk_u0_img_gpu_core_clk (rw) register accessor: clk_u0_img_gpu_core_clk\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_img_gpu_core_clk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_img_gpu_core_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_img_gpu_core_clk`] +#[doc = "clk_u0_img_gpu_core_clk (rw) register accessor: clk_u0_img_gpu_core_clk\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_img_gpu_core_clk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_img_gpu_core_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_img_gpu_core_clk`] module"] pub type CLK_U0_IMG_GPU_CORE_CLK = crate::Reg; #[doc = "clk_u0_img_gpu_core_clk"] pub mod clk_u0_img_gpu_core_clk; -#[doc = "clk_u0_img_gpu_sys_clk (rw) register accessor: clk_u0_img_gpu_sys_clk\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_img_gpu_sys_clk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_img_gpu_sys_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_img_gpu_sys_clk`] +#[doc = "clk_u0_img_gpu_sys_clk (rw) register accessor: clk_u0_img_gpu_sys_clk\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_img_gpu_sys_clk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_img_gpu_sys_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_img_gpu_sys_clk`] module"] pub type CLK_U0_IMG_GPU_SYS_CLK = crate::Reg; #[doc = "clk_u0_img_gpu_sys_clk"] pub mod clk_u0_img_gpu_sys_clk; -#[doc = "clk_u0_img_gpu_clk_apb (rw) register accessor: clk_u0_img_gpu_clk_apb\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_img_gpu_clk_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_img_gpu_clk_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_img_gpu_clk_apb`] +#[doc = "clk_u0_img_gpu_clk_apb (rw) register accessor: clk_u0_img_gpu_clk_apb\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_img_gpu_clk_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_img_gpu_clk_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_img_gpu_clk_apb`] module"] pub type CLK_U0_IMG_GPU_CLK_APB = crate::Reg; #[doc = "clk_u0_img_gpu_clk_apb"] pub mod clk_u0_img_gpu_clk_apb; -#[doc = "clk_u0_gpu_rtc_toggle (rw) register accessor: clk_u0_gpu_rtc_toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_gpu_rtc_toggle::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_gpu_rtc_toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_gpu_rtc_toggle`] +#[doc = "clk_u0_gpu_rtc_toggle (rw) register accessor: clk_u0_gpu_rtc_toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_gpu_rtc_toggle::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_gpu_rtc_toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_gpu_rtc_toggle`] module"] pub type CLK_U0_GPU_RTC_TOGGLE = crate::Reg; #[doc = "clk_u0_gpu_rtc_toggle"] pub mod clk_u0_gpu_rtc_toggle; -#[doc = "clk_u0_sft7110_noc_bus_clk_gpu_axi (rw) register accessor: clk_u0_sft7110_noc_bus_clk_gpu_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sft7110_noc_bus_clk_gpu_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sft7110_noc_bus_clk_gpu_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_sft7110_noc_bus_clk_gpu_axi`] +#[doc = "clk_u0_sft7110_noc_bus_clk_gpu_axi (rw) register accessor: clk_u0_sft7110_noc_bus_clk_gpu_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sft7110_noc_bus_clk_gpu_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sft7110_noc_bus_clk_gpu_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_sft7110_noc_bus_clk_gpu_axi`] module"] pub type CLK_U0_SFT7110_NOC_BUS_CLK_GPU_AXI = crate::Reg; #[doc = "clk_u0_sft7110_noc_bus_clk_gpu_axi"] pub mod clk_u0_sft7110_noc_bus_clk_gpu_axi; -#[doc = "clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x (rw) register accessor: clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x`] +#[doc = "clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x (rw) register accessor: clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x`] module"] pub type CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISPCORE_2X = crate :: Reg < clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x :: CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISPCORE_2X_SPEC > ; #[doc = "clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x"] pub mod clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x; -#[doc = "clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi (rw) register accessor: clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi`] +#[doc = "clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi (rw) register accessor: clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi`] module"] pub type CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISP_AXI = crate :: Reg < clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi :: CLK_U0_DOM_ISP_TOP_CLK_DOM_ISP_TOP_CLK_ISP_AXI_SPEC > ; #[doc = "clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi"] pub mod clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi; -#[doc = "clk_u0_sft7110_noc_bux_clk_isp_axi (rw) register accessor: clk_u0_sft7110_noc_bux_clk_isp_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sft7110_noc_bux_clk_isp_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sft7110_noc_bux_clk_isp_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_sft7110_noc_bux_clk_isp_axi`] +#[doc = "clk_u0_sft7110_noc_bux_clk_isp_axi (rw) register accessor: clk_u0_sft7110_noc_bux_clk_isp_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sft7110_noc_bux_clk_isp_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sft7110_noc_bux_clk_isp_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_sft7110_noc_bux_clk_isp_axi`] module"] pub type CLK_U0_SFT7110_NOC_BUX_CLK_ISP_AXI = crate::Reg; #[doc = "clk_u0_sft7110_noc_bux_clk_isp_axi"] pub mod clk_u0_sft7110_noc_bux_clk_isp_axi; -#[doc = "clk_hifi4_core (rw) register accessor: clk_hifi4_core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_hifi4_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_hifi4_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_hifi4_core`] +#[doc = "clk_hifi4_core (rw) register accessor: clk_hifi4_core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_hifi4_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_hifi4_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_hifi4_core`] module"] pub type CLK_HIFI4_CORE = crate::Reg; #[doc = "clk_hifi4_core"] pub mod clk_hifi4_core; -#[doc = "clk_hifi4_axi (rw) register accessor: clk_hifi4_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_hifi4_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_hifi4_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_hifi4_axi`] +#[doc = "clk_hifi4_axi (rw) register accessor: clk_hifi4_axi\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_hifi4_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_hifi4_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_hifi4_axi`] module"] pub type CLK_HIFI4_AXI = crate::Reg; #[doc = "clk_hifi4_axi"] pub mod clk_hifi4_axi; -#[doc = "clk_u0_axi_cfg1_dec_clk_main (rw) register accessor: clk_u0_axi_cfg1_dec_clk_main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_axi_cfg1_dec_clk_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_axi_cfg1_dec_clk_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_axi_cfg1_dec_clk_main`] +#[doc = "clk_u0_axi_cfg1_dec_clk_main (rw) register accessor: clk_u0_axi_cfg1_dec_clk_main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_axi_cfg1_dec_clk_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_axi_cfg1_dec_clk_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_axi_cfg1_dec_clk_main`] module"] pub type CLK_U0_AXI_CFG1_DEC_CLK_MAIN = crate::Reg; #[doc = "clk_u0_axi_cfg1_dec_clk_main"] pub mod clk_u0_axi_cfg1_dec_clk_main; -#[doc = "clk_u0_axi_cfg1_dec_clk_ahb (rw) register accessor: clk_u0_axi_cfg1_dec_clk_ahb\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_axi_cfg1_dec_clk_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_axi_cfg1_dec_clk_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_axi_cfg1_dec_clk_ahb`] +#[doc = "clk_u0_axi_cfg1_dec_clk_ahb (rw) register accessor: clk_u0_axi_cfg1_dec_clk_ahb\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_axi_cfg1_dec_clk_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_axi_cfg1_dec_clk_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_axi_cfg1_dec_clk_ahb`] module"] pub type CLK_U0_AXI_CFG1_DEC_CLK_AHB = crate::Reg; #[doc = "clk_u0_axi_cfg1_dec_clk_ahb"] pub mod clk_u0_axi_cfg1_dec_clk_ahb; -#[doc = "clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src (rw) register accessor: clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src`] +#[doc = "clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src (rw) register accessor: clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src`] module"] pub type CLK_U0_DOM_VOUT_TOP_CLK_DOM_VOUT_TOP_CLK_VOUT_SRC = crate :: Reg < clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src :: CLK_U0_DOM_VOUT_TOP_CLK_DOM_VOUT_TOP_CLK_VOUT_SRC_SPEC > ; #[doc = "clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src"] pub mod clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src; -#[doc = "clk_vout_axi_divcfg (rw) register accessor: Clock Video Output AXI DIVCFG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_axi_divcfg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_axi_divcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_vout_axi_divcfg`] +#[doc = "clk_vout_axi_divcfg (rw) register accessor: Clock Video Output AXI DIVCFG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_axi_divcfg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_axi_divcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_vout_axi_divcfg`] module"] pub type CLK_VOUT_AXI_DIVCFG = crate::Reg; #[doc = "Clock Video Output AXI DIVCFG"] pub mod clk_vout_axi_divcfg; -#[doc = "clk_noc_display_axi (rw) register accessor: Clock NOC Display AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_noc_display_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_noc_display_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_noc_display_axi`] +#[doc = "clk_noc_display_axi (rw) register accessor: Clock NOC Display AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_noc_display_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_noc_display_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_noc_display_axi`] module"] pub type CLK_NOC_DISPLAY_AXI = crate::Reg; #[doc = "Clock NOC Display AXI"] pub mod clk_noc_display_axi; -#[doc = "clk_vout_ahb (rw) register accessor: Clock Video Output AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_vout_ahb`] +#[doc = "clk_vout_ahb (rw) register accessor: Clock Video Output AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_vout_ahb`] module"] pub type CLK_VOUT_AHB = crate::Reg; #[doc = "Clock Video Output AHB"] pub mod clk_vout_ahb; -#[doc = "clk_vout_axi_icg (rw) register accessor: Clock Video Output AXI ICG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_axi_icg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_axi_icg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_vout_axi_icg`] +#[doc = "clk_vout_axi_icg (rw) register accessor: Clock Video Output AXI ICG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_axi_icg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_axi_icg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_vout_axi_icg`] module"] pub type CLK_VOUT_AXI_ICG = crate::Reg; #[doc = "Clock Video Output AXI ICG"] pub mod clk_vout_axi_icg; -#[doc = "clk_vout_hdmi_tx0_mclk (rw) register accessor: Clock Video Output HDMI TX0 MCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_hdmi_tx0_mclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_hdmi_tx0_mclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_vout_hdmi_tx0_mclk`] +#[doc = "clk_vout_hdmi_tx0_mclk (rw) register accessor: Clock Video Output HDMI TX0 MCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_hdmi_tx0_mclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_hdmi_tx0_mclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_vout_hdmi_tx0_mclk`] module"] pub type CLK_VOUT_HDMI_TX0_MCLK = crate::Reg; #[doc = "Clock Video Output HDMI TX0 MCLK"] pub mod clk_vout_hdmi_tx0_mclk; -#[doc = "clk_vout_mipi_phy (rw) register accessor: Clock Video Output MIPI PHY Reference\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_mipi_phy::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_mipi_phy::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_vout_mipi_phy`] +#[doc = "clk_vout_mipi_phy (rw) register accessor: Clock Video Output MIPI PHY Reference\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vout_mipi_phy::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vout_mipi_phy::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_vout_mipi_phy`] module"] pub type CLK_VOUT_MIPI_PHY = crate::Reg; #[doc = "Clock Video Output MIPI PHY Reference"] pub mod clk_vout_mipi_phy; -#[doc = "clk_jpeg_codec_axi (rw) register accessor: Clock JPEG Codec AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_jpeg_codec_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_jpeg_codec_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_jpeg_codec_axi`] +#[doc = "clk_jpeg_codec_axi (rw) register accessor: Clock JPEG Codec AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_jpeg_codec_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_jpeg_codec_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_jpeg_codec_axi`] module"] pub type CLK_JPEG_CODEC_AXI = crate::Reg; #[doc = "Clock JPEG Codec AXI"] pub mod clk_jpeg_codec_axi; -#[doc = "clk_codaj12_axi (rw) register accessor: CODAJ12 Clock AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_codaj12_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_codaj12_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_codaj12_axi`] +#[doc = "clk_codaj12_axi (rw) register accessor: CODAJ12 Clock AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_codaj12_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_codaj12_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_codaj12_axi`] module"] pub type CLK_CODAJ12_AXI = crate::Reg; #[doc = "CODAJ12 Clock AXI"] pub mod clk_codaj12_axi; -#[doc = "clk_codaj12_core (rw) register accessor: CODAJ12 Clock Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_codaj12_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_codaj12_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_codaj12_core`] +#[doc = "clk_codaj12_core (rw) register accessor: CODAJ12 Clock Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_codaj12_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_codaj12_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_codaj12_core`] module"] pub type CLK_CODAJ12_CORE = crate::Reg; #[doc = "CODAJ12 Clock Core"] pub mod clk_codaj12_core; -#[doc = "clk_codaj12_apb (rw) register accessor: CODAJ12 Clock APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_codaj12_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_codaj12_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_codaj12_apb`] +#[doc = "clk_codaj12_apb (rw) register accessor: CODAJ12 Clock APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_codaj12_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_codaj12_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_codaj12_apb`] module"] pub type CLK_CODAJ12_APB = crate::Reg; #[doc = "CODAJ12 Clock APB"] pub mod clk_codaj12_apb; -#[doc = "clk_vdec_axi (rw) register accessor: Clock Video Decoder AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vdec_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vdec_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_vdec_axi`] +#[doc = "clk_vdec_axi (rw) register accessor: Clock Video Decoder AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_vdec_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_vdec_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_vdec_axi`] module"] pub type CLK_VDEC_AXI = crate::Reg; #[doc = "Clock Video Decoder AXI"] pub mod clk_vdec_axi; -#[doc = "clk_wave511_axi (rw) register accessor: Clock WAVE511 AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave511_axi`] +#[doc = "clk_wave511_axi (rw) register accessor: Clock WAVE511 AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave511_axi`] module"] pub type CLK_WAVE511_AXI = crate::Reg; #[doc = "Clock WAVE511 AXI"] pub mod clk_wave511_axi; -#[doc = "clk_wave511_bpu (rw) register accessor: Clock WAVE511 BPU\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_bpu::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_bpu::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave511_bpu`] +#[doc = "clk_wave511_bpu (rw) register accessor: Clock WAVE511 BPU\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_bpu::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_bpu::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave511_bpu`] module"] pub type CLK_WAVE511_BPU = crate::Reg; #[doc = "Clock WAVE511 BPU"] pub mod clk_wave511_bpu; -#[doc = "clk_wave511_vce (rw) register accessor: Clock WAVE511 VCE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_vce::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_vce::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave511_vce`] +#[doc = "clk_wave511_vce (rw) register accessor: Clock WAVE511 VCE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_vce::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_vce::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave511_vce`] module"] pub type CLK_WAVE511_VCE = crate::Reg; #[doc = "Clock WAVE511 VCE"] pub mod clk_wave511_vce; -#[doc = "clk_wave511_apb (rw) register accessor: Clock WAVE511 APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave511_apb`] +#[doc = "clk_wave511_apb (rw) register accessor: Clock WAVE511 APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave511_apb`] module"] pub type CLK_WAVE511_APB = crate::Reg; #[doc = "Clock WAVE511 APB"] pub mod clk_wave511_apb; -#[doc = "clk_wave511_jpg_arb (rw) register accessor: Clock WAVE511 JPG ARB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_jpg_arb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_jpg_arb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave511_jpg_arb`] +#[doc = "clk_wave511_jpg_arb (rw) register accessor: Clock WAVE511 JPG ARB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_jpg_arb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_jpg_arb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave511_jpg_arb`] module"] pub type CLK_WAVE511_JPG_ARB = crate::Reg; #[doc = "Clock WAVE511 JPG ARB"] pub mod clk_wave511_jpg_arb; -#[doc = "clk_wave511_jpg_main (rw) register accessor: Clock WAVE511 JPG Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_jpg_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_jpg_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave511_jpg_main`] +#[doc = "clk_wave511_jpg_main (rw) register accessor: Clock WAVE511 JPG Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave511_jpg_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave511_jpg_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave511_jpg_main`] module"] pub type CLK_WAVE511_JPG_MAIN = crate::Reg; #[doc = "Clock WAVE511 JPG Main"] pub mod clk_wave511_jpg_main; -#[doc = "clk_noc_vdec_axi (rw) register accessor: Clock NOC Video Decoder AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_noc_vdec_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_noc_vdec_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_noc_vdec_axi`] +#[doc = "clk_noc_vdec_axi (rw) register accessor: Clock NOC Video Decoder AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_noc_vdec_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_noc_vdec_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_noc_vdec_axi`] module"] pub type CLK_NOC_VDEC_AXI = crate::Reg; #[doc = "Clock NOC Video Decoder AXI"] pub mod clk_noc_vdec_axi; -#[doc = "clk_venc_axi (rw) register accessor: Clock Video Encoder AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_venc_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_venc_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_venc_axi`] +#[doc = "clk_venc_axi (rw) register accessor: Clock Video Encoder AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_venc_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_venc_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_venc_axi`] module"] pub type CLK_VENC_AXI = crate::Reg; #[doc = "Clock Video Encoder AXI"] pub mod clk_venc_axi; -#[doc = "clk_wave420l_axi (rw) register accessor: Clock WAVE420L AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave420l_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave420l_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave420l_axi`] +#[doc = "clk_wave420l_axi (rw) register accessor: Clock WAVE420L AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave420l_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave420l_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave420l_axi`] module"] pub type CLK_WAVE420L_AXI = crate::Reg; #[doc = "Clock WAVE420L AXI"] pub mod clk_wave420l_axi; -#[doc = "clk_wave420l_bpu (rw) register accessor: Clock WAVE420L BPU\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave420l_bpu::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave420l_bpu::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave420l_bpu`] +#[doc = "clk_wave420l_bpu (rw) register accessor: Clock WAVE420L BPU\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave420l_bpu::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave420l_bpu::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave420l_bpu`] module"] pub type CLK_WAVE420L_BPU = crate::Reg; #[doc = "Clock WAVE420L BPU"] pub mod clk_wave420l_bpu; -#[doc = "clk_wave420l_vce (rw) register accessor: Clock WAVE420L VCE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave420l_vce::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave420l_vce::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave420l_vce`] +#[doc = "clk_wave420l_vce (rw) register accessor: Clock WAVE420L VCE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave420l_vce::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave420l_vce::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave420l_vce`] module"] pub type CLK_WAVE420L_VCE = crate::Reg; #[doc = "Clock WAVE420L VCE"] pub mod clk_wave420l_vce; -#[doc = "clk_wave420l_apb (rw) register accessor: Clock WAVE420L APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave420l_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave420l_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wave420l_apb`] +#[doc = "clk_wave420l_apb (rw) register accessor: Clock WAVE420L APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wave420l_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wave420l_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wave420l_apb`] module"] pub type CLK_WAVE420L_APB = crate::Reg; #[doc = "Clock WAVE420L APB"] pub mod clk_wave420l_apb; -#[doc = "clk_noc_venc_axi (rw) register accessor: Clock NOC Video Encoder AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_noc_venc_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_noc_venc_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_noc_venc_axi`] +#[doc = "clk_noc_venc_axi (rw) register accessor: Clock NOC Video Encoder AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_noc_venc_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_noc_venc_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_noc_venc_axi`] module"] pub type CLK_NOC_VENC_AXI = crate::Reg; #[doc = "Clock NOC Video Encoder AXI"] pub mod clk_noc_venc_axi; -#[doc = "clk_axi_cfg0_dec_main_div (rw) register accessor: Clock AXI Config 0 DEC Main Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_cfg0_dec_main_div::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_cfg0_dec_main_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_axi_cfg0_dec_main_div`] +#[doc = "clk_axi_cfg0_dec_main_div (rw) register accessor: Clock AXI Config 0 DEC Main Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_cfg0_dec_main_div::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_cfg0_dec_main_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_axi_cfg0_dec_main_div`] module"] pub type CLK_AXI_CFG0_DEC_MAIN_DIV = crate::Reg; #[doc = "Clock AXI Config 0 DEC Main Divider"] pub mod clk_axi_cfg0_dec_main_div; -#[doc = "clk_axi_cfg0_dec_main (rw) register accessor: Clock AXI Config 0 DEC Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_cfg0_dec_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_cfg0_dec_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_axi_cfg0_dec_main`] +#[doc = "clk_axi_cfg0_dec_main (rw) register accessor: Clock AXI Config 0 DEC Main\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_cfg0_dec_main::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_cfg0_dec_main::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_axi_cfg0_dec_main`] module"] pub type CLK_AXI_CFG0_DEC_MAIN = crate::Reg; #[doc = "Clock AXI Config 0 DEC Main"] pub mod clk_axi_cfg0_dec_main; -#[doc = "clk_axi_cfg0_dec_hifi4 (rw) register accessor: Clock AXI Config 0 DEC HIFI4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_cfg0_dec_hifi4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_cfg0_dec_hifi4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_axi_cfg0_dec_hifi4`] +#[doc = "clk_axi_cfg0_dec_hifi4 (rw) register accessor: Clock AXI Config 0 DEC HIFI4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_axi_cfg0_dec_hifi4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_axi_cfg0_dec_hifi4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_axi_cfg0_dec_hifi4`] module"] pub type CLK_AXI_CFG0_DEC_HIFI4 = crate::Reg; #[doc = "Clock AXI Config 0 DEC HIFI4"] pub mod clk_axi_cfg0_dec_hifi4; -#[doc = "clk_aximem_128b_axi (rw) register accessor: Clock AXIMEM 128B AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_aximem_128b_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_aximem_128b_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_aximem_128b_axi`] +#[doc = "clk_aximem_128b_axi (rw) register accessor: Clock AXIMEM 128B AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_aximem_128b_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_aximem_128b_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_aximem_128b_axi`] module"] pub type CLK_AXIMEM_128B_AXI = crate::Reg; #[doc = "Clock AXIMEM 128B AXI"] pub mod clk_aximem_128b_axi; -#[doc = "clk_qspi_ahb (rw) register accessor: Clock QSPI AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_qspi_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_qspi_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_qspi_ahb`] +#[doc = "clk_qspi_ahb (rw) register accessor: Clock QSPI AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_qspi_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_qspi_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_qspi_ahb`] module"] pub type CLK_QSPI_AHB = crate::Reg; #[doc = "Clock QSPI AHB"] pub mod clk_qspi_ahb; -#[doc = "clk_qspi_apb (rw) register accessor: Clock QSPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_qspi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_qspi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_qspi_apb`] +#[doc = "clk_qspi_apb (rw) register accessor: Clock QSPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_qspi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_qspi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_qspi_apb`] module"] pub type CLK_QSPI_APB = crate::Reg; #[doc = "Clock QSPI APB"] pub mod clk_qspi_apb; -#[doc = "clk_qspi_ref_src (rw) register accessor: Clock QSPI Reference Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_qspi_ref_src::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_qspi_ref_src::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_qspi_ref_src`] +#[doc = "clk_qspi_ref_src (rw) register accessor: Clock QSPI Reference Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_qspi_ref_src::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_qspi_ref_src::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_qspi_ref_src`] module"] pub type CLK_QSPI_REF_SRC = crate::Reg; #[doc = "Clock QSPI Reference Source"] pub mod clk_qspi_ref_src; -#[doc = "clk_qspi_ref (rw) register accessor: Clock QSPI Reference\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_qspi_ref::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_qspi_ref::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_qspi_ref`] +#[doc = "clk_qspi_ref (rw) register accessor: Clock QSPI Reference\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_qspi_ref::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_qspi_ref::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_qspi_ref`] module"] pub type CLK_QSPI_REF = crate::Reg; #[doc = "Clock QSPI Reference"] pub mod clk_qspi_ref; -#[doc = "clk_u0_sd_ahb (rw) register accessor: U0 SD Clock AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sd_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sd_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_sd_ahb`] +#[doc = "clk_u0_sd_ahb (rw) register accessor: U0 SD Clock AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sd_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sd_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_sd_ahb`] module"] pub type CLK_U0_SD_AHB = crate::Reg; #[doc = "U0 SD Clock AHB"] pub mod clk_u0_sd_ahb; -#[doc = "clk_u1_sd_ahb (rw) register accessor: U1 SD Clock AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_sd_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_sd_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_sd_ahb`] +#[doc = "clk_u1_sd_ahb (rw) register accessor: U1 SD Clock AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_sd_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_sd_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_sd_ahb`] module"] pub type CLK_U1_SD_AHB = crate::Reg; #[doc = "U1 SD Clock AHB"] pub mod clk_u1_sd_ahb; -#[doc = "clk_u0_sd_card (rw) register accessor: U0 SD Card Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sd_card::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sd_card::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_sd_card`] +#[doc = "clk_u0_sd_card (rw) register accessor: U0 SD Card Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_sd_card::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_sd_card::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_sd_card`] module"] pub type CLK_U0_SD_CARD = crate::Reg; #[doc = "U0 SD Card Clock"] pub mod clk_u0_sd_card; -#[doc = "clk_u1_sd_card (rw) register accessor: U1 SD Card Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_sd_card::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_sd_card::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_sd_card`] +#[doc = "clk_u1_sd_card (rw) register accessor: U1 SD Card Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_sd_card::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_sd_card::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_sd_card`] module"] pub type CLK_U1_SD_CARD = crate::Reg; #[doc = "U1 SD Card Clock"] pub mod clk_u1_sd_card; -#[doc = "clk_usb_125m (rw) register accessor: Clock USB 125M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_125m::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_125m::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_usb_125m`] +#[doc = "clk_usb_125m (rw) register accessor: Clock USB 125M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_125m::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_125m::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_usb_125m`] module"] pub type CLK_USB_125M = crate::Reg; #[doc = "Clock USB 125M"] pub mod clk_usb_125m; -#[doc = "clk_noc_stg_axi (rw) register accessor: Clock NOC STG AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_noc_stg_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_noc_stg_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_noc_stg_axi`] +#[doc = "clk_noc_stg_axi (rw) register accessor: Clock NOC STG AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_noc_stg_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_noc_stg_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_noc_stg_axi`] module"] pub type CLK_NOC_STG_AXI = crate::Reg; #[doc = "Clock NOC STG AXI"] pub mod clk_noc_stg_axi; -#[doc = "clk_gmac5_axi64_ahb (rw) register accessor: Clock GMAC 5 AXI 64 AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_ahb`] +#[doc = "clk_gmac5_axi64_ahb (rw) register accessor: Clock GMAC 5 AXI 64 AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_ahb`] module"] pub type CLK_GMAC5_AXI64_AHB = crate::Reg; #[doc = "Clock GMAC 5 AXI 64 AHB"] pub mod clk_gmac5_axi64_ahb; -#[doc = "clk_gmac5_axi64_axi (rw) register accessor: Clock GMAC 5 AXI 64 AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_axi`] +#[doc = "clk_gmac5_axi64_axi (rw) register accessor: Clock GMAC 5 AXI 64 AXI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_axi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_axi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_axi`] module"] pub type CLK_GMAC5_AXI64_AXI = crate::Reg; #[doc = "Clock GMAC 5 AXI 64 AXI"] pub mod clk_gmac5_axi64_axi; -#[doc = "clk_gmac_src (rw) register accessor: Clock GMAC Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac_src::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac_src::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac_src`] +#[doc = "clk_gmac_src (rw) register accessor: Clock GMAC Source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac_src::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac_src::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac_src`] module"] pub type CLK_GMAC_SRC = crate::Reg; #[doc = "Clock GMAC Source"] pub mod clk_gmac_src; -#[doc = "clk_gmac1_gtx (rw) register accessor: Clock GMAC 1 GTX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac1_gtx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac1_gtx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac1_gtx`] +#[doc = "clk_gmac1_gtx (rw) register accessor: Clock GMAC 1 GTX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac1_gtx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac1_gtx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac1_gtx`] module"] pub type CLK_GMAC1_GTX = crate::Reg; #[doc = "Clock GMAC 1 GTX"] pub mod clk_gmac1_gtx; -#[doc = "clk_gmac1_rmii_rtx (rw) register accessor: Clock GMAC 1 RMII RTX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac1_rmii_rtx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac1_rmii_rtx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac1_rmii_rtx`] +#[doc = "clk_gmac1_rmii_rtx (rw) register accessor: Clock GMAC 1 RMII RTX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac1_rmii_rtx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac1_rmii_rtx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac1_rmii_rtx`] module"] pub type CLK_GMAC1_RMII_RTX = crate::Reg; #[doc = "Clock GMAC 1 RMII RTX"] pub mod clk_gmac1_rmii_rtx; -#[doc = "clk_gmac5_axi64_ptp (rw) register accessor: Clock GMAC 5 AXI 64 PTP\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_ptp::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_ptp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_ptp`] +#[doc = "clk_gmac5_axi64_ptp (rw) register accessor: Clock GMAC 5 AXI 64 PTP\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_ptp::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_ptp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_ptp`] module"] pub type CLK_GMAC5_AXI64_PTP = crate::Reg; #[doc = "Clock GMAC 5 AXI 64 PTP"] pub mod clk_gmac5_axi64_ptp; -#[doc = "clk_gmac5_axi64_rx (rw) register accessor: Clock GMAC 5 AXI 64 RX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_rx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_rx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_rx`] +#[doc = "clk_gmac5_axi64_rx (rw) register accessor: Clock GMAC 5 AXI 64 RX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_rx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_rx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_rx`] module"] pub type CLK_GMAC5_AXI64_RX = crate::Reg; #[doc = "Clock GMAC 5 AXI 64 RX"] pub mod clk_gmac5_axi64_rx; -#[doc = "clk_gmac5_axi64_rxi (rw) register accessor: Clock GMAC 5 AXI 64 RX Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_rxi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_rxi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_rxi`] +#[doc = "clk_gmac5_axi64_rxi (rw) register accessor: Clock GMAC 5 AXI 64 RX Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_rxi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_rxi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_rxi`] module"] pub type CLK_GMAC5_AXI64_RXI = crate::Reg; #[doc = "Clock GMAC 5 AXI 64 RX Inverter"] pub mod clk_gmac5_axi64_rxi; -#[doc = "clk_gmac5_axi64_tx (rw) register accessor: Clock GMAC 5 AXI 64 TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_tx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_tx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_tx`] +#[doc = "clk_gmac5_axi64_tx (rw) register accessor: Clock GMAC 5 AXI 64 TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_tx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_tx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_tx`] module"] pub type CLK_GMAC5_AXI64_TX = crate::Reg; #[doc = "Clock GMAC 5 AXI 64 TX"] pub mod clk_gmac5_axi64_tx; -#[doc = "clk_gmac5_axi64_txi (rw) register accessor: Clock GMAC 5 AXI 64 TX Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_txi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_txi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac5_axi64_txi`] +#[doc = "clk_gmac5_axi64_txi (rw) register accessor: Clock GMAC 5 AXI 64 TX Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac5_axi64_txi::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac5_axi64_txi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac5_axi64_txi`] module"] pub type CLK_GMAC5_AXI64_TXI = crate::Reg; #[doc = "Clock GMAC 5 AXI 64 TX Inverter"] pub mod clk_gmac5_axi64_txi; -#[doc = "clk_gmac1_gtxclk (rw) register accessor: Clock GMAC 1 GTXC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac1_gtxclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac1_gtxclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac1_gtxclk`] +#[doc = "clk_gmac1_gtxclk (rw) register accessor: Clock GMAC 1 GTXC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac1_gtxclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac1_gtxclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac1_gtxclk`] module"] pub type CLK_GMAC1_GTXCLK = crate::Reg; #[doc = "Clock GMAC 1 GTXC"] pub mod clk_gmac1_gtxclk; -#[doc = "clk_gmac0_gtx (rw) register accessor: Clock GMAC 0 GTX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac0_gtx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac0_gtx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac0_gtx`] +#[doc = "clk_gmac0_gtx (rw) register accessor: Clock GMAC 0 GTX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac0_gtx::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac0_gtx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac0_gtx`] module"] pub type CLK_GMAC0_GTX = crate::Reg; #[doc = "Clock GMAC 0 GTX"] pub mod clk_gmac0_gtx; -#[doc = "clk_gmac0_ptp (rw) register accessor: Clock GMAC 0 PTP\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac0_ptp::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac0_ptp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac0_ptp`] +#[doc = "clk_gmac0_ptp (rw) register accessor: Clock GMAC 0 PTP\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac0_ptp::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac0_ptp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac0_ptp`] module"] pub type CLK_GMAC0_PTP = crate::Reg; #[doc = "Clock GMAC 0 PTP"] pub mod clk_gmac0_ptp; -#[doc = "clk_gmac_phy (rw) register accessor: Clock GMAC PHY\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac_phy::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac_phy::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac_phy`] +#[doc = "clk_gmac_phy (rw) register accessor: Clock GMAC PHY\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac_phy::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac_phy::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac_phy`] module"] pub type CLK_GMAC_PHY = crate::Reg; #[doc = "Clock GMAC PHY"] pub mod clk_gmac_phy; -#[doc = "clk_gmac0_gtxclk (rw) register accessor: Clock GMAC 0 GTXC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac0_gtxclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac0_gtxclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_gmac0_gtxclk`] +#[doc = "clk_gmac0_gtxclk (rw) register accessor: Clock GMAC 0 GTXC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gmac0_gtxclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gmac0_gtxclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gmac0_gtxclk`] module"] pub type CLK_GMAC0_GTXCLK = crate::Reg; #[doc = "Clock GMAC 0 GTXC"] pub mod clk_gmac0_gtxclk; -#[doc = "clk_sys_iomux_pclk (rw) register accessor: Clock SYS IOMUX PCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_iomux_pclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_iomux_pclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_sys_iomux_pclk`] +#[doc = "clk_sys_iomux_pclk (rw) register accessor: Clock SYS IOMUX PCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_iomux_pclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_iomux_pclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_sys_iomux_pclk`] module"] pub type CLK_SYS_IOMUX_PCLK = crate::Reg; #[doc = "Clock SYS IOMUX PCLK"] pub mod clk_sys_iomux_pclk; -#[doc = "clk_mbox_apb (rw) register accessor: Clock Mailbox APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_mbox_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_mbox_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_mbox_apb`] +#[doc = "clk_mbox_apb (rw) register accessor: Clock Mailbox APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_mbox_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_mbox_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_mbox_apb`] module"] pub type CLK_MBOX_APB = crate::Reg; #[doc = "Clock Mailbox APB"] pub mod clk_mbox_apb; -#[doc = "clk_internal_ctrl_apb (rw) register accessor: Clock Internal Controller APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_internal_ctrl_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_internal_ctrl_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_internal_ctrl_apb`] +#[doc = "clk_internal_ctrl_apb (rw) register accessor: Clock Internal Controller APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_internal_ctrl_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_internal_ctrl_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_internal_ctrl_apb`] module"] pub type CLK_INTERNAL_CTRL_APB = crate::Reg; #[doc = "Clock Internal Controller APB"] pub mod clk_internal_ctrl_apb; -#[doc = "clk_u0_can_ctrl_apb (rw) register accessor: U0 Clock CAN Controller APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_can_ctrl_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_can_ctrl_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_can_ctrl_apb`] +#[doc = "clk_u0_can_ctrl_apb (rw) register accessor: U0 Clock CAN Controller APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_can_ctrl_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_can_ctrl_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_can_ctrl_apb`] module"] pub type CLK_U0_CAN_CTRL_APB = crate::Reg; #[doc = "U0 Clock CAN Controller APB"] pub mod clk_u0_can_ctrl_apb; -#[doc = "clk_u0_can_ctrl_tim (rw) register accessor: U0 Clock CAN Controller Timer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_can_ctrl_tim::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_can_ctrl_tim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_can_ctrl_tim`] +#[doc = "clk_u0_can_ctrl_tim (rw) register accessor: U0 Clock CAN Controller Timer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_can_ctrl_tim::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_can_ctrl_tim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_can_ctrl_tim`] module"] pub type CLK_U0_CAN_CTRL_TIM = crate::Reg; #[doc = "U0 Clock CAN Controller Timer"] pub mod clk_u0_can_ctrl_tim; -#[doc = "clk_u0_can_ctrl_can (rw) register accessor: U0 Clock CAN Controller CAN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_can_ctrl_can::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_can_ctrl_can::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_can_ctrl_can`] +#[doc = "clk_u0_can_ctrl_can (rw) register accessor: U0 Clock CAN Controller CAN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_can_ctrl_can::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_can_ctrl_can::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_can_ctrl_can`] module"] pub type CLK_U0_CAN_CTRL_CAN = crate::Reg; #[doc = "U0 Clock CAN Controller CAN"] pub mod clk_u0_can_ctrl_can; -#[doc = "clk_u1_can_ctrl_apb (rw) register accessor: U1 Clock CAN Controller APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_can_ctrl_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_can_ctrl_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_can_ctrl_apb`] +#[doc = "clk_u1_can_ctrl_apb (rw) register accessor: U1 Clock CAN Controller APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_can_ctrl_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_can_ctrl_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_can_ctrl_apb`] module"] pub type CLK_U1_CAN_CTRL_APB = crate::Reg; #[doc = "U1 Clock CAN Controller APB"] pub mod clk_u1_can_ctrl_apb; -#[doc = "clk_u1_can_ctrl_tim (rw) register accessor: U1 Clock CAN Controller Timer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_can_ctrl_tim::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_can_ctrl_tim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_can_ctrl_tim`] +#[doc = "clk_u1_can_ctrl_tim (rw) register accessor: U1 Clock CAN Controller Timer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_can_ctrl_tim::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_can_ctrl_tim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_can_ctrl_tim`] module"] pub type CLK_U1_CAN_CTRL_TIM = crate::Reg; #[doc = "U1 Clock CAN Controller Timer"] pub mod clk_u1_can_ctrl_tim; -#[doc = "clk_u1_can_ctrl_can (rw) register accessor: U1 Clock CAN Controller CAN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_can_ctrl_can::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_can_ctrl_can::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_can_ctrl_can`] +#[doc = "clk_u1_can_ctrl_can (rw) register accessor: U1 Clock CAN Controller CAN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_can_ctrl_can::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_can_ctrl_can::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_can_ctrl_can`] module"] pub type CLK_U1_CAN_CTRL_CAN = crate::Reg; #[doc = "U1 Clock CAN Controller CAN"] pub mod clk_u1_can_ctrl_can; -#[doc = "clk_pwm_apb (rw) register accessor: Clock PWM APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pwm_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pwm_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pwm_apb`] +#[doc = "clk_pwm_apb (rw) register accessor: Clock PWM APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pwm_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pwm_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pwm_apb`] module"] pub type CLK_PWM_APB = crate::Reg; #[doc = "Clock PWM APB"] pub mod clk_pwm_apb; -#[doc = "clk_wdt_apb (rw) register accessor: Clock WDT APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wdt_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wdt_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wdt_apb`] +#[doc = "clk_wdt_apb (rw) register accessor: Clock WDT APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wdt_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wdt_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wdt_apb`] module"] pub type CLK_WDT_APB = crate::Reg; #[doc = "Clock WDT APB"] pub mod clk_wdt_apb; -#[doc = "clk_wdt (rw) register accessor: Clock WDT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wdt::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wdt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_wdt`] +#[doc = "clk_wdt (rw) register accessor: Clock WDT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_wdt::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_wdt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_wdt`] module"] pub type CLK_WDT = crate::Reg; #[doc = "Clock WDT"] pub mod clk_wdt; -#[doc = "clk_tim_apb (rw) register accessor: Clock Timer APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tim_apb`] +#[doc = "clk_tim_apb (rw) register accessor: Clock Timer APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tim_apb`] module"] pub type CLK_TIM_APB = crate::Reg; #[doc = "Clock Timer APB"] pub mod clk_tim_apb; -#[doc = "clk_tim0 (rw) register accessor: Clock Timer 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tim0`] +#[doc = "clk_tim0 (rw) register accessor: Clock Timer 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tim0`] module"] pub type CLK_TIM0 = crate::Reg; #[doc = "Clock Timer 0"] pub mod clk_tim0; -#[doc = "clk_tim1 (rw) register accessor: Clock Timer 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tim1`] +#[doc = "clk_tim1 (rw) register accessor: Clock Timer 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tim1`] module"] pub type CLK_TIM1 = crate::Reg; #[doc = "Clock Timer 1"] pub mod clk_tim1; -#[doc = "clk_tim2 (rw) register accessor: Clock Timer 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tim2`] +#[doc = "clk_tim2 (rw) register accessor: Clock Timer 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tim2`] module"] pub type CLK_TIM2 = crate::Reg; #[doc = "Clock Timer 2"] pub mod clk_tim2; -#[doc = "clk_tim3 (rw) register accessor: Clock Timer 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tim3`] +#[doc = "clk_tim3 (rw) register accessor: Clock Timer 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tim3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tim3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tim3`] module"] pub type CLK_TIM3 = crate::Reg; #[doc = "Clock Timer 3"] pub mod clk_tim3; -#[doc = "clk_temp_sensor_apb (rw) register accessor: Clock Temperature Sensor APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_temp_sensor_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_temp_sensor_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_temp_sensor_apb`] +#[doc = "clk_temp_sensor_apb (rw) register accessor: Clock Temperature Sensor APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_temp_sensor_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_temp_sensor_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_temp_sensor_apb`] module"] pub type CLK_TEMP_SENSOR_APB = crate::Reg; #[doc = "Clock Temperature Sensor APB"] pub mod clk_temp_sensor_apb; -#[doc = "clk_temp_sensor (rw) register accessor: Clock Temperature Sensor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_temp_sensor::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_temp_sensor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_temp_sensor`] +#[doc = "clk_temp_sensor (rw) register accessor: Clock Temperature Sensor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_temp_sensor::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_temp_sensor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_temp_sensor`] module"] pub type CLK_TEMP_SENSOR = crate::Reg; #[doc = "Clock Temperature Sensor"] pub mod clk_temp_sensor; -#[doc = "clk_u0_spi_apb (rw) register accessor: U0 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_spi_apb`] +#[doc = "clk_u0_spi_apb (rw) register accessor: U0 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_spi_apb`] module"] pub type CLK_U0_SPI_APB = crate::Reg; #[doc = "U0 Clock SPI APB"] pub mod clk_u0_spi_apb; -#[doc = "clk_u1_spi_apb (rw) register accessor: U1 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_spi_apb`] +#[doc = "clk_u1_spi_apb (rw) register accessor: U1 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_spi_apb`] module"] pub type CLK_U1_SPI_APB = crate::Reg; #[doc = "U1 Clock SPI APB"] pub mod clk_u1_spi_apb; -#[doc = "clk_u2_spi_apb (rw) register accessor: U2 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u2_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u2_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u2_spi_apb`] +#[doc = "clk_u2_spi_apb (rw) register accessor: U2 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u2_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u2_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u2_spi_apb`] module"] pub type CLK_U2_SPI_APB = crate::Reg; #[doc = "U2 Clock SPI APB"] pub mod clk_u2_spi_apb; -#[doc = "clk_u3_spi_apb (rw) register accessor: U3 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u3_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u3_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u3_spi_apb`] +#[doc = "clk_u3_spi_apb (rw) register accessor: U3 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u3_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u3_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u3_spi_apb`] module"] pub type CLK_U3_SPI_APB = crate::Reg; #[doc = "U3 Clock SPI APB"] pub mod clk_u3_spi_apb; -#[doc = "clk_u4_spi_apb (rw) register accessor: U4 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u4_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u4_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u4_spi_apb`] +#[doc = "clk_u4_spi_apb (rw) register accessor: U4 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u4_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u4_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u4_spi_apb`] module"] pub type CLK_U4_SPI_APB = crate::Reg; #[doc = "U4 Clock SPI APB"] pub mod clk_u4_spi_apb; -#[doc = "clk_u5_spi_apb (rw) register accessor: U5 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u5_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u5_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u5_spi_apb`] +#[doc = "clk_u5_spi_apb (rw) register accessor: U5 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u5_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u5_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u5_spi_apb`] module"] pub type CLK_U5_SPI_APB = crate::Reg; #[doc = "U5 Clock SPI APB"] pub mod clk_u5_spi_apb; -#[doc = "clk_u6_spi_apb (rw) register accessor: U6 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u6_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u6_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u6_spi_apb`] +#[doc = "clk_u6_spi_apb (rw) register accessor: U6 Clock SPI APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u6_spi_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u6_spi_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u6_spi_apb`] module"] pub type CLK_U6_SPI_APB = crate::Reg; #[doc = "U6 Clock SPI APB"] pub mod clk_u6_spi_apb; -#[doc = "clk_u0_i2c_apb (rw) register accessor: U0 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_i2c_apb`] +#[doc = "clk_u0_i2c_apb (rw) register accessor: U0 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_i2c_apb`] module"] pub type CLK_U0_I2C_APB = crate::Reg; #[doc = "U0 Clock I2C APB"] pub mod clk_u0_i2c_apb; -#[doc = "clk_u1_i2c_apb (rw) register accessor: U1 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_i2c_apb`] +#[doc = "clk_u1_i2c_apb (rw) register accessor: U1 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_i2c_apb`] module"] pub type CLK_U1_I2C_APB = crate::Reg; #[doc = "U1 Clock I2C APB"] pub mod clk_u1_i2c_apb; -#[doc = "clk_u2_i2c_apb (rw) register accessor: U2 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u2_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u2_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u2_i2c_apb`] +#[doc = "clk_u2_i2c_apb (rw) register accessor: U2 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u2_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u2_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u2_i2c_apb`] module"] pub type CLK_U2_I2C_APB = crate::Reg; #[doc = "U2 Clock I2C APB"] pub mod clk_u2_i2c_apb; -#[doc = "clk_u3_i2c_apb (rw) register accessor: U3 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u3_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u3_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u3_i2c_apb`] +#[doc = "clk_u3_i2c_apb (rw) register accessor: U3 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u3_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u3_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u3_i2c_apb`] module"] pub type CLK_U3_I2C_APB = crate::Reg; #[doc = "U3 Clock I2C APB"] pub mod clk_u3_i2c_apb; -#[doc = "clk_u4_i2c_apb (rw) register accessor: U4 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u4_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u4_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u4_i2c_apb`] +#[doc = "clk_u4_i2c_apb (rw) register accessor: U4 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u4_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u4_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u4_i2c_apb`] module"] pub type CLK_U4_I2C_APB = crate::Reg; #[doc = "U4 Clock I2C APB"] pub mod clk_u4_i2c_apb; -#[doc = "clk_u5_i2c_apb (rw) register accessor: U5 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u5_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u5_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u5_i2c_apb`] +#[doc = "clk_u5_i2c_apb (rw) register accessor: U5 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u5_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u5_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u5_i2c_apb`] module"] pub type CLK_U5_I2C_APB = crate::Reg; #[doc = "U5 Clock I2C APB"] pub mod clk_u5_i2c_apb; -#[doc = "clk_u6_i2c_apb (rw) register accessor: U6 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u6_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u6_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u6_i2c_apb`] +#[doc = "clk_u6_i2c_apb (rw) register accessor: U6 Clock I2C APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u6_i2c_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u6_i2c_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u6_i2c_apb`] module"] pub type CLK_U6_I2C_APB = crate::Reg; #[doc = "U6 Clock I2C APB"] pub mod clk_u6_i2c_apb; -#[doc = "clk_u0_uart_apb (rw) register accessor: U0 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_uart_apb`] +#[doc = "clk_u0_uart_apb (rw) register accessor: U0 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_uart_apb`] module"] pub type CLK_U0_UART_APB = crate::Reg; #[doc = "U0 Clock UART APB"] pub mod clk_u0_uart_apb; -#[doc = "clk_u0_uart_core (rw) register accessor: U0 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_uart_core`] +#[doc = "clk_u0_uart_core (rw) register accessor: U0 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_uart_core`] module"] pub type CLK_U0_UART_CORE = crate::Reg; #[doc = "U0 Clock UART Core"] pub mod clk_u0_uart_core; -#[doc = "clk_u1_uart_apb (rw) register accessor: U1 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_uart_apb`] +#[doc = "clk_u1_uart_apb (rw) register accessor: U1 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_uart_apb`] module"] pub type CLK_U1_UART_APB = crate::Reg; #[doc = "U1 Clock UART APB"] pub mod clk_u1_uart_apb; -#[doc = "clk_u1_uart_core (rw) register accessor: U1 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_uart_core`] +#[doc = "clk_u1_uart_core (rw) register accessor: U1 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_uart_core`] module"] pub type CLK_U1_UART_CORE = crate::Reg; #[doc = "U1 Clock UART Core"] pub mod clk_u1_uart_core; -#[doc = "clk_u2_uart_apb (rw) register accessor: U2 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u2_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u2_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u2_uart_apb`] +#[doc = "clk_u2_uart_apb (rw) register accessor: U2 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u2_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u2_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u2_uart_apb`] module"] pub type CLK_U2_UART_APB = crate::Reg; #[doc = "U2 Clock UART APB"] pub mod clk_u2_uart_apb; -#[doc = "clk_u2_uart_core (rw) register accessor: U2 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u2_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u2_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u2_uart_core`] +#[doc = "clk_u2_uart_core (rw) register accessor: U2 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u2_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u2_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u2_uart_core`] module"] pub type CLK_U2_UART_CORE = crate::Reg; #[doc = "U2 Clock UART Core"] pub mod clk_u2_uart_core; -#[doc = "clk_u3_uart_apb (rw) register accessor: U3 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u3_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u3_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u3_uart_apb`] +#[doc = "clk_u3_uart_apb (rw) register accessor: U3 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u3_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u3_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u3_uart_apb`] module"] pub type CLK_U3_UART_APB = crate::Reg; #[doc = "U3 Clock UART APB"] pub mod clk_u3_uart_apb; -#[doc = "clk_u3_uart_core (rw) register accessor: U3 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u3_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u3_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u3_uart_core`] +#[doc = "clk_u3_uart_core (rw) register accessor: U3 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u3_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u3_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u3_uart_core`] module"] pub type CLK_U3_UART_CORE = crate::Reg; #[doc = "U3 Clock UART Core"] pub mod clk_u3_uart_core; -#[doc = "clk_u4_uart_apb (rw) register accessor: U4 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u4_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u4_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u4_uart_apb`] +#[doc = "clk_u4_uart_apb (rw) register accessor: U4 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u4_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u4_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u4_uart_apb`] module"] pub type CLK_U4_UART_APB = crate::Reg; #[doc = "U4 Clock UART APB"] pub mod clk_u4_uart_apb; -#[doc = "clk_u4_uart_core (rw) register accessor: U4 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u4_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u4_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u4_uart_core`] +#[doc = "clk_u4_uart_core (rw) register accessor: U4 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u4_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u4_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u4_uart_core`] module"] pub type CLK_U4_UART_CORE = crate::Reg; #[doc = "U4 Clock UART Core"] pub mod clk_u4_uart_core; -#[doc = "clk_u5_uart_apb (rw) register accessor: U5 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u5_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u5_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u5_uart_apb`] +#[doc = "clk_u5_uart_apb (rw) register accessor: U5 Clock UART APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u5_uart_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u5_uart_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u5_uart_apb`] module"] pub type CLK_U5_UART_APB = crate::Reg; #[doc = "U5 Clock UART APB"] pub mod clk_u5_uart_apb; -#[doc = "clk_u5_uart_core (rw) register accessor: U5 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u5_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u5_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u5_uart_core`] +#[doc = "clk_u5_uart_core (rw) register accessor: U5 Clock UART Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u5_uart_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u5_uart_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u5_uart_core`] module"] pub type CLK_U5_UART_CORE = crate::Reg; #[doc = "U5 Clock UART Core"] pub mod clk_u5_uart_core; -#[doc = "clk_pwmdac_apb (rw) register accessor: Clock PWMDAC APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pwmdac_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pwmdac_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pwmdac_apb`] +#[doc = "clk_pwmdac_apb (rw) register accessor: Clock PWMDAC APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pwmdac_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pwmdac_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pwmdac_apb`] module"] pub type CLK_PWMDAC_APB = crate::Reg; #[doc = "Clock PWMDAC APB"] pub mod clk_pwmdac_apb; -#[doc = "clk_pwmdac_core (rw) register accessor: Clock PWMDAC Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pwmdac_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pwmdac_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pwmdac_core`] +#[doc = "clk_pwmdac_core (rw) register accessor: Clock PWMDAC Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pwmdac_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pwmdac_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pwmdac_core`] module"] pub type CLK_PWMDAC_CORE = crate::Reg; #[doc = "Clock PWMDAC Core"] pub mod clk_pwmdac_core; -#[doc = "clk_spdif_apb (rw) register accessor: Clock SPDIF APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_spdif_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_spdif_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_spdif_apb`] +#[doc = "clk_spdif_apb (rw) register accessor: Clock SPDIF APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_spdif_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_spdif_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_spdif_apb`] module"] pub type CLK_SPDIF_APB = crate::Reg; #[doc = "Clock SPDIF APB"] pub mod clk_spdif_apb; -#[doc = "clk_spdif_core (rw) register accessor: Clock SPDIF Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_spdif_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_spdif_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_spdif_core`] +#[doc = "clk_spdif_core (rw) register accessor: Clock SPDIF Core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_spdif_core::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_spdif_core::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_spdif_core`] module"] pub type CLK_SPDIF_CORE = crate::Reg; #[doc = "Clock SPDIF Core"] pub mod clk_spdif_core; -#[doc = "clk_u0_i2s_tx_apb (rw) register accessor: U0 Clock I2S TX APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2s_tx_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2s_tx_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_i2s_tx_apb`] +#[doc = "clk_u0_i2s_tx_apb (rw) register accessor: U0 Clock I2S TX APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2s_tx_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2s_tx_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_i2s_tx_apb`] module"] pub type CLK_U0_I2S_TX_APB = crate::Reg; #[doc = "U0 Clock I2S TX APB"] pub mod clk_u0_i2s_tx_apb; -#[doc = "clk_u0_i2stx_4ch0_bclk_mst (rw) register accessor: U0 Clock I2S TX 0 BCLK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_4ch0_bclk_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_4ch0_bclk_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_i2stx_4ch0_bclk_mst`] +#[doc = "clk_u0_i2stx_4ch0_bclk_mst (rw) register accessor: U0 Clock I2S TX 0 BCLK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_4ch0_bclk_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_4ch0_bclk_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_i2stx_4ch0_bclk_mst`] module"] pub type CLK_U0_I2STX_4CH0_BCLK_MST = crate::Reg; #[doc = "U0 Clock I2S TX 0 BCLK MST"] pub mod clk_u0_i2stx_4ch0_bclk_mst; -#[doc = "clk_u0_i2stx_4ch0_bclk_mst_inv (rw) register accessor: U0 Clock I2S TX 0 BCLK MST Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_4ch0_bclk_mst_inv::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_4ch0_bclk_mst_inv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_i2stx_4ch0_bclk_mst_inv`] +#[doc = "clk_u0_i2stx_4ch0_bclk_mst_inv (rw) register accessor: U0 Clock I2S TX 0 BCLK MST Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_4ch0_bclk_mst_inv::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_4ch0_bclk_mst_inv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_i2stx_4ch0_bclk_mst_inv`] module"] pub type CLK_U0_I2STX_4CH0_BCLK_MST_INV = crate::Reg; #[doc = "U0 Clock I2S TX 0 BCLK MST Inverter"] pub mod clk_u0_i2stx_4ch0_bclk_mst_inv; -#[doc = "clk_i2stx0_lrck_mst (rw) register accessor: Clock I2S TX 0 LRCK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2stx0_lrck_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2stx0_lrck_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2stx0_lrck_mst`] +#[doc = "clk_i2stx0_lrck_mst (rw) register accessor: Clock I2S TX 0 LRCK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2stx0_lrck_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2stx0_lrck_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2stx0_lrck_mst`] module"] pub type CLK_I2STX0_LRCK_MST = crate::Reg; #[doc = "Clock I2S TX 0 LRCK MST"] pub mod clk_i2stx0_lrck_mst; -#[doc = "clk_u0_i2stx_bclk (rw) register accessor: U0 Clock I2S TX BCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_bclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_bclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_i2stx_bclk`] +#[doc = "clk_u0_i2stx_bclk (rw) register accessor: U0 Clock I2S TX BCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_bclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_bclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_i2stx_bclk`] module"] pub type CLK_U0_I2STX_BCLK = crate::Reg; #[doc = "U0 Clock I2S TX BCLK"] pub mod clk_u0_i2stx_bclk; -#[doc = "clk_u0_i2stx_bclk_neg (rw) register accessor: U0 Clock I2S TX BCLK Negative\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_bclk_neg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_bclk_neg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_i2stx_bclk_neg`] +#[doc = "clk_u0_i2stx_bclk_neg (rw) register accessor: U0 Clock I2S TX BCLK Negative\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_bclk_neg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_bclk_neg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_i2stx_bclk_neg`] module"] pub type CLK_U0_I2STX_BCLK_NEG = crate::Reg; #[doc = "U0 Clock I2S TX BCLK Negative"] pub mod clk_u0_i2stx_bclk_neg; -#[doc = "clk_u0_i2stx_lrck (rw) register accessor: U0 Clock I2S TX LRCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_lrck::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_lrck::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u0_i2stx_lrck`] +#[doc = "clk_u0_i2stx_lrck (rw) register accessor: U0 Clock I2S TX LRCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u0_i2stx_lrck::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u0_i2stx_lrck::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u0_i2stx_lrck`] module"] pub type CLK_U0_I2STX_LRCK = crate::Reg; #[doc = "U0 Clock I2S TX LRCK"] pub mod clk_u0_i2stx_lrck; -#[doc = "clk_u1_i2s_tx_apb (rw) register accessor: U1 Clock I2S TX APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2s_tx_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2s_tx_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_i2s_tx_apb`] +#[doc = "clk_u1_i2s_tx_apb (rw) register accessor: U1 Clock I2S TX APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2s_tx_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2s_tx_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_i2s_tx_apb`] module"] pub type CLK_U1_I2S_TX_APB = crate::Reg; #[doc = "U1 Clock I2S TX APB"] pub mod clk_u1_i2s_tx_apb; -#[doc = "clk_u1_i2stx_4ch1_bclk_mst (rw) register accessor: U1 Clock I2S TX 1 BCLK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_4ch1_bclk_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_4ch1_bclk_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_i2stx_4ch1_bclk_mst`] +#[doc = "clk_u1_i2stx_4ch1_bclk_mst (rw) register accessor: U1 Clock I2S TX 1 BCLK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_4ch1_bclk_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_4ch1_bclk_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_i2stx_4ch1_bclk_mst`] module"] pub type CLK_U1_I2STX_4CH1_BCLK_MST = crate::Reg; #[doc = "U1 Clock I2S TX 1 BCLK MST"] pub mod clk_u1_i2stx_4ch1_bclk_mst; -#[doc = "clk_u1_i2stx_4ch1_bclk_mst_inv (rw) register accessor: U1 Clock I2S TX 1 BCLK MST Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_4ch1_bclk_mst_inv::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_4ch1_bclk_mst_inv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_i2stx_4ch1_bclk_mst_inv`] +#[doc = "clk_u1_i2stx_4ch1_bclk_mst_inv (rw) register accessor: U1 Clock I2S TX 1 BCLK MST Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_4ch1_bclk_mst_inv::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_4ch1_bclk_mst_inv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_i2stx_4ch1_bclk_mst_inv`] module"] pub type CLK_U1_I2STX_4CH1_BCLK_MST_INV = crate::Reg; #[doc = "U1 Clock I2S TX 1 BCLK MST Inverter"] pub mod clk_u1_i2stx_4ch1_bclk_mst_inv; -#[doc = "clk_i2stx1_lrck_mst (rw) register accessor: Clock I2S TX 1 LRCK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2stx1_lrck_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2stx1_lrck_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2stx1_lrck_mst`] +#[doc = "clk_i2stx1_lrck_mst (rw) register accessor: Clock I2S TX 1 LRCK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2stx1_lrck_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2stx1_lrck_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2stx1_lrck_mst`] module"] pub type CLK_I2STX1_LRCK_MST = crate::Reg; #[doc = "Clock I2S TX 1 LRCK MST"] pub mod clk_i2stx1_lrck_mst; -#[doc = "clk_u1_i2stx_bclk (rw) register accessor: U1 Clock I2S TX BCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_bclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_bclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_i2stx_bclk`] +#[doc = "clk_u1_i2stx_bclk (rw) register accessor: U1 Clock I2S TX BCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_bclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_bclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_i2stx_bclk`] module"] pub type CLK_U1_I2STX_BCLK = crate::Reg; #[doc = "U1 Clock I2S TX BCLK"] pub mod clk_u1_i2stx_bclk; -#[doc = "clk_u1_i2stx_bclk_neg (rw) register accessor: U1 Clock I2S TX BCLK Negative\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_bclk_neg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_bclk_neg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_i2stx_bclk_neg`] +#[doc = "clk_u1_i2stx_bclk_neg (rw) register accessor: U1 Clock I2S TX BCLK Negative\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_bclk_neg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_bclk_neg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_i2stx_bclk_neg`] module"] pub type CLK_U1_I2STX_BCLK_NEG = crate::Reg; #[doc = "U1 Clock I2S TX BCLK Negative"] pub mod clk_u1_i2stx_bclk_neg; -#[doc = "clk_u1_i2stx_lrck (rw) register accessor: U1 Clock I2S TX LRCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_lrck::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_lrck::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_u1_i2stx_lrck`] +#[doc = "clk_u1_i2stx_lrck (rw) register accessor: U1 Clock I2S TX LRCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_lrck::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_lrck::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_u1_i2stx_lrck`] module"] pub type CLK_U1_I2STX_LRCK = crate::Reg; #[doc = "U1 Clock I2S TX LRCK"] pub mod clk_u1_i2stx_lrck; -#[doc = "clk_i2s_apb (rw) register accessor: Clock I2S APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2s_apb`] +#[doc = "clk_i2s_apb (rw) register accessor: Clock I2S APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2s_apb`] module"] pub type CLK_I2S_APB = crate::Reg; #[doc = "Clock I2S APB"] pub mod clk_i2s_apb; -#[doc = "clk_i2s_bclk_mst (rw) register accessor: Clock I2S BCLK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_bclk_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_bclk_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2s_bclk_mst`] +#[doc = "clk_i2s_bclk_mst (rw) register accessor: Clock I2S BCLK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_bclk_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_bclk_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2s_bclk_mst`] module"] pub type CLK_I2S_BCLK_MST = crate::Reg; #[doc = "Clock I2S BCLK MST"] pub mod clk_i2s_bclk_mst; -#[doc = "clk_i2s_bclk_mst_inv (rw) register accessor: Clock I2S BCLK MST Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_bclk_mst_inv::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_bclk_mst_inv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2s_bclk_mst_inv`] +#[doc = "clk_i2s_bclk_mst_inv (rw) register accessor: Clock I2S BCLK MST Inverter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_bclk_mst_inv::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_bclk_mst_inv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2s_bclk_mst_inv`] module"] pub type CLK_I2S_BCLK_MST_INV = crate::Reg; #[doc = "Clock I2S BCLK MST Inverter"] pub mod clk_i2s_bclk_mst_inv; -#[doc = "clk_i2s_lrck_mst (rw) register accessor: Clock I2S LRCK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_lrck_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_lrck_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2s_lrck_mst`] +#[doc = "clk_i2s_lrck_mst (rw) register accessor: Clock I2S LRCK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_lrck_mst::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_lrck_mst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2s_lrck_mst`] module"] pub type CLK_I2S_LRCK_MST = crate::Reg; #[doc = "Clock I2S LRCK MST"] pub mod clk_i2s_lrck_mst; -#[doc = "clk_i2s_bclk (rw) register accessor: Clock I2S BCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_bclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_bclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2s_bclk`] +#[doc = "clk_i2s_bclk (rw) register accessor: Clock I2S BCLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_bclk::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_bclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2s_bclk`] module"] pub type CLK_I2S_BCLK = crate::Reg; #[doc = "Clock I2S BCLK"] pub mod clk_i2s_bclk; -#[doc = "clk_i2s_bclk_neg (rw) register accessor: Clock I2S BCLK Negative\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_bclk_neg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_bclk_neg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2s_bclk_neg`] +#[doc = "clk_i2s_bclk_neg (rw) register accessor: Clock I2S BCLK Negative\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_bclk_neg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_bclk_neg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2s_bclk_neg`] module"] pub type CLK_I2S_BCLK_NEG = crate::Reg; #[doc = "Clock I2S BCLK Negative"] pub mod clk_i2s_bclk_neg; -#[doc = "clk_i2s_lrck (rw) register accessor: Clock I2S LRCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_lrck::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_lrck::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_i2s_lrck`] +#[doc = "clk_i2s_lrck (rw) register accessor: Clock I2S LRCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_i2s_lrck::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_i2s_lrck::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_i2s_lrck`] module"] pub type CLK_I2S_LRCK = crate::Reg; #[doc = "Clock I2S LRCK"] pub mod clk_i2s_lrck; -#[doc = "clk_pdm_dmic (rw) register accessor: Clock PDM DMIC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pdm_dmic::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pdm_dmic::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pdm_dmic`] +#[doc = "clk_pdm_dmic (rw) register accessor: Clock PDM DMIC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pdm_dmic::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pdm_dmic::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pdm_dmic`] module"] pub type CLK_PDM_DMIC = crate::Reg; #[doc = "Clock PDM DMIC"] pub mod clk_pdm_dmic; -#[doc = "clk_pdm_apb (rw) register accessor: Clock PDM APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pdm_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pdm_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_pdm_apb`] +#[doc = "clk_pdm_apb (rw) register accessor: Clock PDM APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_pdm_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_pdm_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_pdm_apb`] module"] pub type CLK_PDM_APB = crate::Reg; #[doc = "Clock PDM APB"] pub mod clk_pdm_apb; -#[doc = "clk_tdm_ahb (rw) register accessor: Clock TDM AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tdm_ahb`] +#[doc = "clk_tdm_ahb (rw) register accessor: Clock TDM AHB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm_ahb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm_ahb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tdm_ahb`] module"] pub type CLK_TDM_AHB = crate::Reg; #[doc = "Clock TDM AHB"] pub mod clk_tdm_ahb; -#[doc = "clk_tdm_apb (rw) register accessor: Clock TDM APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tdm_apb`] +#[doc = "clk_tdm_apb (rw) register accessor: Clock TDM APB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm_apb::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tdm_apb`] module"] pub type CLK_TDM_APB = crate::Reg; #[doc = "Clock TDM APB"] pub mod clk_tdm_apb; -#[doc = "clk_tdm_internal (rw) register accessor: Clock TDM Internal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm_internal::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm_internal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tdm_internal`] +#[doc = "clk_tdm_internal (rw) register accessor: Clock TDM Internal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm_internal::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm_internal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tdm_internal`] module"] pub type CLK_TDM_INTERNAL = crate::Reg; #[doc = "Clock TDM Internal"] pub mod clk_tdm_internal; -#[doc = "clk_tdm (rw) register accessor: Clock TDM\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tdm`] +#[doc = "clk_tdm (rw) register accessor: Clock TDM\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tdm`] module"] pub type CLK_TDM = crate::Reg; #[doc = "Clock TDM"] pub mod clk_tdm; -#[doc = "clk_tdm_neg (rw) register accessor: Clock TDM Negative\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm_neg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm_neg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_tdm_neg`] +#[doc = "clk_tdm_neg (rw) register accessor: Clock TDM Negative\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_tdm_neg::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_tdm_neg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_tdm_neg`] module"] pub type CLK_TDM_NEG = crate::Reg; #[doc = "Clock TDM Negative"] pub mod clk_tdm_neg; -#[doc = "clk_jtag_cert_trng (rw) register accessor: Clock JTAG Certification TRNG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_jtag_cert_trng::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_jtag_cert_trng::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk_jtag_cert_trng`] +#[doc = "clk_jtag_cert_trng (rw) register accessor: Clock JTAG Certification TRNG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_jtag_cert_trng::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_jtag_cert_trng::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_jtag_cert_trng`] module"] pub type CLK_JTAG_CERT_TRNG = crate::Reg; #[doc = "Clock JTAG Certification TRNG"] pub mod clk_jtag_cert_trng; -#[doc = "soft_rst0_addr_sel (rw) register accessor: Software RESET 0 Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst0_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst0_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_rst0_addr_sel`] +#[doc = "soft_rst0_addr_sel (rw) register accessor: Software RESET 0 Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst0_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst0_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_rst0_addr_sel`] module"] pub type SOFT_RST0_ADDR_SEL = crate::Reg; #[doc = "Software RESET 0 Address Selector"] pub mod soft_rst0_addr_sel; -#[doc = "soft_rst1_addr_sel (rw) register accessor: Software RESET 1 Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst1_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst1_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_rst1_addr_sel`] +#[doc = "soft_rst1_addr_sel (rw) register accessor: Software RESET 1 Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst1_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst1_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_rst1_addr_sel`] module"] pub type SOFT_RST1_ADDR_SEL = crate::Reg; #[doc = "Software RESET 1 Address Selector"] pub mod soft_rst1_addr_sel; -#[doc = "soft_rst2_addr_sel (rw) register accessor: Software RESET 2 Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst2_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst2_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_rst2_addr_sel`] +#[doc = "soft_rst2_addr_sel (rw) register accessor: Software RESET 2 Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst2_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst2_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_rst2_addr_sel`] module"] pub type SOFT_RST2_ADDR_SEL = crate::Reg; #[doc = "Software RESET 2 Address Selector"] pub mod soft_rst2_addr_sel; -#[doc = "soft_rst3_addr_sel (rw) register accessor: Software RESET 3 Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst3_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst3_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`soft_rst3_addr_sel`] +#[doc = "soft_rst3_addr_sel (rw) register accessor: Software RESET 3 Address Selector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soft_rst3_addr_sel::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_rst3_addr_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_rst3_addr_sel`] module"] pub type SOFT_RST3_ADDR_SEL = crate::Reg; #[doc = "Software RESET 3 Address Selector"] pub mod soft_rst3_addr_sel; -#[doc = "syscrg_rst0_status (rw) register accessor: SYSCRG RESET Status 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscrg_rst0_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscrg_rst0_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`syscrg_rst0_status`] +#[doc = "syscrg_rst0_status (rw) register accessor: SYSCRG RESET Status 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscrg_rst0_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscrg_rst0_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syscrg_rst0_status`] module"] pub type SYSCRG_RST0_STATUS = crate::Reg; #[doc = "SYSCRG RESET Status 0"] pub mod syscrg_rst0_status; -#[doc = "syscrg_rst1_status (rw) register accessor: SYSCRG RESET Status 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscrg_rst1_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscrg_rst1_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`syscrg_rst1_status`] +#[doc = "syscrg_rst1_status (rw) register accessor: SYSCRG RESET Status 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscrg_rst1_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscrg_rst1_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syscrg_rst1_status`] module"] pub type SYSCRG_RST1_STATUS = crate::Reg; #[doc = "SYSCRG RESET Status 1"] pub mod syscrg_rst1_status; -#[doc = "syscrg_rst2_status (rw) register accessor: SYSCRG RESET Status 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscrg_rst2_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscrg_rst2_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`syscrg_rst2_status`] +#[doc = "syscrg_rst2_status (rw) register accessor: SYSCRG RESET Status 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscrg_rst2_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscrg_rst2_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syscrg_rst2_status`] module"] pub type SYSCRG_RST2_STATUS = crate::Reg; #[doc = "SYSCRG RESET Status 2"] pub mod syscrg_rst2_status; -#[doc = "syscrg_rst3_status (rw) register accessor: SYSCRG RESET Status 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscrg_rst3_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscrg_rst3_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`syscrg_rst3_status`] +#[doc = "syscrg_rst3_status (rw) register accessor: SYSCRG RESET Status 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscrg_rst3_status::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscrg_rst3_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syscrg_rst3_status`] module"] pub type SYSCRG_RST3_STATUS = crate::Reg; #[doc = "SYSCRG RESET Status 3"] diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_ahb0.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_ahb0.rs index 91788fe..a85782e 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_ahb0.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_ahb0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_ahb1.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_ahb1.rs index ad10aff..bcca7f9 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_ahb1.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_ahb1.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_apb0.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_apb0.rs index 9c05437..78dba35 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_apb0.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_apb0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_apb_bus.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_apb_bus.rs index e966b6f..a9cba95 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_apb_bus.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_apb_bus.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=8, Default=4, Min=4, Typical=4"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=8, Default=4, Min=4, Typical=4"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=8, Default=4, Min=4, Typical=4"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=8, Default=4, Min=4, Typical=4"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_audio_root.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_audio_root.rs index 75c8d95..9125669 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_audio_root.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_audio_root.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0.rs index 4dce62b..6c54140 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0_dec_hifi4.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0_dec_hifi4.rs index c890675..373d243 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0_dec_hifi4.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0_dec_hifi4.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0_dec_main.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0_dec_main.rs index 76e506a..f0065f2 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0_dec_main.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0_dec_main.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0_dec_main_div.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0_dec_main_div.rs index 6f8f14f..863b387 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0_dec_main_div.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_axi_cfg0_dec_main_div.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_aximem_128b_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_aximem_128b_axi.rs index 47a418f..6e444cb 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_aximem_128b_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_aximem_128b_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_bus_root.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_bus_root.rs index 86e92ad..2d6e4b1 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_bus_root.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_bus_root.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_osc, clk_pll2"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_osc, clk_pll2"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc, clk_pll2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc, clk_pll2"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_codaj12_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_codaj12_apb.rs index 2a4af22..600ba47 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_codaj12_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_codaj12_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_codaj12_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_codaj12_axi.rs index c580dd2..6606a92 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_codaj12_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_codaj12_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_codaj12_core.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_codaj12_core.rs index f89dfcd..3357d7f 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_codaj12_core.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_codaj12_core.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_cpu_bus.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_cpu_bus.rs index 26be7e4..7a7d6eb 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_cpu_bus.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_cpu_bus.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_cpu_core.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_cpu_core.rs index 384f907..9c38337 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_cpu_core.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_cpu_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=7, Default=1, Min=1, Typical=1"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=7, Default=1, Min=1, Typical=1"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=1, Min=1, Typical=1"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=1, Min=1, Typical=1"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_cpu_root.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_cpu_root.rs index 82bc559..266f212 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_cpu_root.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_cpu_root.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_osc, clk_pll0"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_osc, clk_pll0"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc, clk_pll0"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc, clk_pll0"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_ddr_bus.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_ddr_bus.rs index 137a83a..2e27aa6 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_ddr_bus.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_ddr_bus.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_osc_div2, clk_pll1_div4, clk_pll1_div8"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_osc_div2, clk_pll1_div4, clk_pll1_div8"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc_div2, clk_pll1_div4, clk_pll1_div8"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc_div2, clk_pll1_div4, clk_pll1_div8"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gclk0.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gclk0.rs index 75b6bb8..72b3b30 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gclk0.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gclk0.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=62, Default=20, Min=16, Typical=20"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=62, Default=20, Min=16, Typical=20"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=62, Default=20, Min=16, Typical=20"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=62, Default=20, Min=16, Typical=20"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gclk1.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gclk1.rs index 5a6bb9a..15bdaa3 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gclk1.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gclk1.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=62, Default=16, Min=16, Typical=16"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=62, Default=16, Min=16, Typical=16"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=62, Default=16, Min=16, Typical=16"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=62, Default=16, Min=16, Typical=16"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gclk2.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gclk2.rs index a8d8c4f..117e6fc 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gclk2.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gclk2.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=62, Default=12, Min=12, Typical=12"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=62, Default=12, Min=12, Typical=12"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=62, Default=12, Min=12, Typical=12"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=62, Default=12, Min=12, Typical=12"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac0_gtx.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac0_gtx.rs index 34c7c0b..d82deb0 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac0_gtx.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac0_gtx.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac0_gtxclk.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac0_gtxclk.rs index 97b4fb7..ac2076f 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac0_gtxclk.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac0_gtxclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `dly_chain_sel` reader - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] pub type DLY_CHAIN_SEL_R = crate::FieldReader; #[doc = "Field `dly_chain_sel` writer - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] -pub type DLY_CHAIN_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type DLY_CHAIN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] #[inline(always)] #[must_use] - pub fn dly_chain_sel(&mut self) -> DLY_CHAIN_SEL_W { - DLY_CHAIN_SEL_W::new(self) + pub fn dly_chain_sel(&mut self) -> DLY_CHAIN_SEL_W { + DLY_CHAIN_SEL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac0_ptp.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac0_ptp.rs index 88a3a57..b187a1a 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac0_ptp.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac0_ptp.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac1_gtx.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac1_gtx.rs index 6a5b29a..b68f2f3 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac1_gtx.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac1_gtx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac1_gtxclk.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac1_gtxclk.rs index 0f9d180..b9d1c17 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac1_gtxclk.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac1_gtxclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `dly_chain_sel` reader - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] pub type DLY_CHAIN_SEL_R = crate::FieldReader; #[doc = "Field `dly_chain_sel` writer - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] -pub type DLY_CHAIN_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type DLY_CHAIN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] #[inline(always)] #[must_use] - pub fn dly_chain_sel(&mut self) -> DLY_CHAIN_SEL_W { - DLY_CHAIN_SEL_W::new(self) + pub fn dly_chain_sel(&mut self) -> DLY_CHAIN_SEL_W { + DLY_CHAIN_SEL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac1_rmii_rtx.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac1_rmii_rtx.rs index 70b2160..e3dc263 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac1_rmii_rtx.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac1_rmii_rtx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_ahb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_ahb.rs index 862dd40..fbadb98 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_ahb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_axi.rs index e651602..f0d4aea 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_ptp.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_ptp.rs index fb3b1d1..9b633b1 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_ptp.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_ptp.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=10"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=10"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=10"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=10"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_rx.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_rx.rs index 93a41ff..c855d81 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_rx.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_rx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `dly_chain_sel` reader - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] pub type DLY_CHAIN_SEL_R = crate::FieldReader; #[doc = "Field `dly_chain_sel` writer - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] -pub type DLY_CHAIN_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type DLY_CHAIN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage."] #[inline(always)] #[must_use] - pub fn dly_chain_sel(&mut self) -> DLY_CHAIN_SEL_W { - DLY_CHAIN_SEL_W::new(self) + pub fn dly_chain_sel(&mut self) -> DLY_CHAIN_SEL_W { + DLY_CHAIN_SEL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_rxi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_rxi.rs index d6319fd..c25f010 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_rxi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_rxi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_tx.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_tx.rs index 2c32863..3a26f2e 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_tx.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_tx.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_gmac1_gtxclk, clk_gmac1_rmii_rtx"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_gmac1_gtxclk, clk_gmac1_rmii_rtx"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_gmac1_gtxclk, clk_gmac1_rmii_rtx"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_gmac1_gtxclk, clk_gmac1_rmii_rtx"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_txi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_txi.rs index cdf4136..644dbbf 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_txi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac5_axi64_txi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac_phy.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac_phy.rs index 2ec54ad..fb7d26b 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac_phy.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac_phy.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac_src.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac_src.rs index d6c5f28..84f0e8a 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gmac_src.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gmac_src.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gpu_core.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gpu_core.rs index 66e7b9c..eaed536 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gpu_core.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gpu_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_gpu_root.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_gpu_root.rs index bdf56a7..1fd5f7d 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_gpu_root.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_gpu_root.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_pll2, clk_pll1"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_pll2, clk_pll1"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_pll2, clk_pll1"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_pll2, clk_pll1"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_hifi4_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_hifi4_axi.rs index 2365a5a..924caf4 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_hifi4_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_hifi4_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_hifi4_core.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_hifi4_core.rs index f50cf93..1d615cb 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_hifi4_core.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_hifi4_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=3, Min=3, Typical=3"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=3, Min=3, Typical=3"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=3, Min=3, Typical=3"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=3, Min=3, Typical=3"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_apb.rs index c45c6ba..8a79cd7 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk.rs index b110e16..96f3475 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2srx_3ch_bclk_mst, clk_i2srx_3ch_bclk_ext"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2srx_3ch_bclk_mst, clk_i2srx_3ch_bclk_ext"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2srx_3ch_bclk_mst, clk_i2srx_3ch_bclk_ext"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2srx_3ch_bclk_mst, clk_i2srx_3ch_bclk_ext"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk_mst.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk_mst.rs index c3e862f..e153a25 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk_mst.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk_mst.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk_mst_inv.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk_mst_inv.rs index fff0423..cfe8e93 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk_mst_inv.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk_mst_inv.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk_neg.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk_neg.rs index 161efa0..dc75f6a 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk_neg.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_bclk_neg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_lrck.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_lrck.rs index 3ba9dcc..665875a 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_lrck.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_lrck.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2srx_3ch_lrck_mst, clk_i2srx_3ch_lrck_ext"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2srx_3ch_lrck_mst, clk_i2srx_3ch_lrck_ext"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2srx_3ch_lrck_mst, clk_i2srx_3ch_lrck_ext"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2srx_3ch_lrck_mst, clk_i2srx_3ch_lrck_ext"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_lrck_mst.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_lrck_mst.rs index 9acee21..f7f1804 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_lrck_mst.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_i2s_lrck_mst.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2srx_3ch_bclk_mst_inv, clk_i2srx_3ch_bclk_mst"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2srx_3ch_bclk_mst_inv, clk_i2srx_3ch_bclk_mst"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2srx_3ch_bclk_mst_inv, clk_i2srx_3ch_bclk_mst"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_i2stx0_lrck_mst.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_i2stx0_lrck_mst.rs index fb410b5..5c877fd 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_i2stx0_lrck_mst.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_i2stx0_lrck_mst.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_i2stx1_lrck_mst.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_i2stx1_lrck_mst.rs index 2c819c1..e5dbd15 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_i2stx1_lrck_mst.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_i2stx1_lrck_mst.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_internal_ctrl_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_internal_ctrl_apb.rs index dcc67ea..712100c 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_internal_ctrl_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_internal_ctrl_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_isp_2x.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_isp_2x.rs index 6fc6124..206776d 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_isp_2x.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_isp_2x.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_pll2, clk_pll1"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_pll2, clk_pll1"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bits 24:29 - Clock multiplexing selector: clk_pll2, clk_pll1"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_isp_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_isp_axi.rs index 7a88458..9d1b58b 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_isp_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_isp_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=4, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=4, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=4, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=4, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_jpeg_codec_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_jpeg_codec_axi.rs index e41037b..f76afb3 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_jpeg_codec_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_jpeg_codec_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_jtag_cert_trng.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_jtag_cert_trng.rs index 26aebd6..bfdcc02 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_jtag_cert_trng.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_jtag_cert_trng.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_mbox_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_mbox_apb.rs index 2941b9d..7c5f0d5 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_mbox_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_mbox_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_mclk.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_mclk.rs index 3929cc8..86cc786 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_mclk.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_mclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_mclk_inner, clk_mclk_ext"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_mclk_inner, clk_mclk_ext"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_mclk_inner, clk_mclk_ext"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_mclk_inner, clk_mclk_ext"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_mclk_inner.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_mclk_inner.rs index 20c8df0..62e7801 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_mclk_inner.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_mclk_inner.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=64, Default=12, Min=12, Typical=12"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=64, Default=12, Min=12, Typical=12"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=12, Min=12, Typical=12"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=12, Min=12, Typical=12"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_mclk_out.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_mclk_out.rs index 31e1208..acd5d99 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_mclk_out.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_mclk_out.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_noc_display_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_noc_display_axi.rs index a6af042..885c675 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_noc_display_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_noc_display_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_noc_stg_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_noc_stg_axi.rs index d3cfb48..1f39705 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_noc_stg_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_noc_stg_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_noc_vdec_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_noc_vdec_axi.rs index c01c84d..593406b 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_noc_vdec_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_noc_vdec_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_noc_venc_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_noc_venc_axi.rs index 247d421..92b6791 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_noc_venc_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_noc_venc_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_nocstg_bus.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_nocstg_bus.rs index ae169fe..a2c2324 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_nocstg_bus.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_nocstg_bus.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_osc_div2.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_osc_div2.rs index d444e83..3bff3e8 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_osc_div2.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_osc_div2.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_pdm_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_pdm_apb.rs index ecbe03c..cc6aa36 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_pdm_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_pdm_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_pdm_dmic.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_pdm_dmic.rs index 5146d36..639e7a2 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_pdm_dmic.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_pdm_dmic.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=64, Default=8, Min=8, Typical=8"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=64, Default=8, Min=8, Typical=8"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=8, Min=8, Typical=8"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=8, Min=8, Typical=8"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_peripheral_root.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_peripheral_root.rs index a827f45..b5240dc 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_peripheral_root.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_peripheral_root.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_pll0, clk_pll2"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_pll0, clk_pll2"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bits 24:29 - Clock multiplexing selector: clk_pll0, clk_pll2"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_pll0_div2.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_pll0_div2.rs index 7334a5d..18ce371 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_pll0_div2.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_pll0_div2.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_pll1_div2.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_pll1_div2.rs index 82cf36d..3a3e98f 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_pll1_div2.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_pll1_div2.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_pll1_div4.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_pll1_div4.rs index 2886366..8f89227 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_pll1_div4.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_pll1_div4.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_pll1_div8.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_pll1_div8.rs index fa50861..4772516 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_pll1_div8.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_pll1_div8.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_pll2_div2.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_pll2_div2.rs index 0821186..cba9c86 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_pll2_div2.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_pll2_div2.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_pwm_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_pwm_apb.rs index 0ae7144..1fb7ce7 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_pwm_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_pwm_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_pwmdac_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_pwmdac_apb.rs index c255e14..50b0199 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_pwmdac_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_pwmdac_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_pwmdac_core.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_pwmdac_core.rs index 645b7f9..7f98f4f 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_pwmdac_core.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_pwmdac_core.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=256, Default=12, Min=12, Typical=12"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=256, Default=12, Min=12, Typical=12"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=256, Default=12, Min=12, Typical=12"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=256, Default=12, Min=12, Typical=12"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_qspi_ahb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_qspi_ahb.rs index 7745b73..4a38f05 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_qspi_ahb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_qspi_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_qspi_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_qspi_apb.rs index d3e51fd..388a0e9 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_qspi_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_qspi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_qspi_ref.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_qspi_ref.rs index 7074e20..66dabfb 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_qspi_ref.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_qspi_ref.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_osc, clk_qspi_ref_src"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_osc, clk_qspi_ref_src"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc, clk_qspi_ref_src"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_osc, clk_qspi_ref_src"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_qspi_ref_src.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_qspi_ref_src.rs index 2c3d475..fa61839 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_qspi_ref_src.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_qspi_ref_src.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=16, Default=10, Min=10, Typical=10"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=16, Default=10, Min=10, Typical=10"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=16, Default=10, Min=10, Typical=10"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=16, Default=10, Min=10, Typical=10"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_spdif_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_spdif_apb.rs index f874dc9..3e085ec 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_spdif_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_spdif_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_spdif_core.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_spdif_core.rs index baa6b5b..908827f 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_spdif_core.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_spdif_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_stg_axiahb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_stg_axiahb.rs index cf74983..29d6a58 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_stg_axiahb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_stg_axiahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_sys_iomux_pclk.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_sys_iomux_pclk.rs index 4e5836b..e382eb1 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_sys_iomux_pclk.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_sys_iomux_pclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_tdm.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_tdm.rs index 8d1fe67..81c8d42 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_tdm.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_tdm.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_tdm_internal, clk_tdm_ext"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_tdm_internal, clk_tdm_ext"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_tdm_internal, clk_tdm_ext"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_tdm_internal, clk_tdm_ext"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_tdm_ahb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_tdm_ahb.rs index a2f9e3a..b19c0ff 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_tdm_ahb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_tdm_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_tdm_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_tdm_apb.rs index a5cd1f0..6c73d4f 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_tdm_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_tdm_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_tdm_internal.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_tdm_internal.rs index b873e2b..e9ece3d 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_tdm_internal.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_tdm_internal.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=64, Default=1, Min=1, Typical=1"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=64, Default=1, Min=1, Typical=1"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=1, Min=1, Typical=1"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=64, Default=1, Min=1, Typical=1"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_tdm_neg.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_tdm_neg.rs index 5174acf..439912c 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_tdm_neg.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_tdm_neg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_temp_sensor.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_temp_sensor.rs index 25bc858..b5c0cdd 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_temp_sensor.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_temp_sensor.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_temp_sensor_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_temp_sensor_apb.rs index bbabdca..2e83527 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_temp_sensor_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_temp_sensor_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_tim0.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_tim0.rs index 25d210d..5721d03 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_tim0.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_tim0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_tim1.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_tim1.rs index e8b9a9e..13d1e57 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_tim1.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_tim1.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_tim2.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_tim2.rs index f7e9121..6ecbe54 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_tim2.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_tim2.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_tim3.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_tim3.rs index 370f7c9..3488ff6 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_tim3.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_tim3.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_tim_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_tim_apb.rs index 9599c08..6e573c8 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_tim_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_tim_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_axi_cfg1_dec_clk_ahb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_axi_cfg1_dec_clk_ahb.rs index d3653f5..f721a34 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_axi_cfg1_dec_clk_ahb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_axi_cfg1_dec_clk_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_axi_cfg1_dec_clk_main.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_axi_cfg1_dec_clk_main.rs index 1411af5..fa92ab9 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_axi_cfg1_dec_clk_main.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_axi_cfg1_dec_clk_main.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_can_ctrl_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_can_ctrl_apb.rs index d0ebbc7..559c564 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_can_ctrl_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_can_ctrl_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_can_ctrl_can.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_can_ctrl_can.rs index 0d6e20b..bd42b8f 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_can_ctrl_can.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_can_ctrl_can.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_can_ctrl_tim.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_can_ctrl_tim.rs index 73074d0..db6bf3f 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_can_ctrl_tim.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_can_ctrl_tim.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_ddr_sft7110_clk_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_ddr_sft7110_clk_axi.rs index c628428..26f2529 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_ddr_sft7110_clk_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_ddr_sft7110_clk_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi.rs index 9beca33..267dffb 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,12 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg( - &mut self, - ) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x.rs index bec791a..244ea1b 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,12 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg( - &mut self, - ) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src.rs index 264349f..f60e500 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,12 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg( - &mut self, - ) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_gpu_rtc_toggle.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_gpu_rtc_toggle.rs index 853225e..5a49875 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_gpu_rtc_toggle.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_gpu_rtc_toggle.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=12, Default=12, Min=12, Typical=12"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=12, Default=12, Min=12, Typical=12"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=12, Default=12, Min=12, Typical=12"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=12, Default=12, Min=12, Typical=12"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2c_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2c_apb.rs index 9adb97c..551c406 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2c_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2c_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2s_tx_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2s_tx_apb.rs index 040b2d5..1afffd0 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2s_tx_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2s_tx_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_4ch0_bclk_mst.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_4ch0_bclk_mst.rs index d987243..4607fac 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_4ch0_bclk_mst.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_4ch0_bclk_mst.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_4ch0_bclk_mst_inv.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_4ch0_bclk_mst_inv.rs index 63baebd..7a7f775 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_4ch0_bclk_mst_inv.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_4ch0_bclk_mst_inv.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_bclk.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_bclk.rs index f23af1e..ee403e4 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_bclk.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_bclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst, clk_i2stx_bclk_ext"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst, clk_i2stx_bclk_ext"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst, clk_i2stx_bclk_ext"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst, clk_i2stx_bclk_ext"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_bclk_neg.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_bclk_neg.rs index 612bd4a..84eec10 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_bclk_neg.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_bclk_neg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_lrck.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_lrck.rs index 0c6a39f..c0e3740 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_lrck.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_i2stx_lrck.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2stx_4ch0_lrck_mst, clk_i2stx_lrck_ext"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2stx_4ch0_lrck_mst, clk_i2stx_lrck_ext"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch0_lrck_mst, clk_i2stx_lrck_ext"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch0_lrck_mst, clk_i2stx_lrck_ext"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_img_gpu_clk_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_img_gpu_clk_apb.rs index 837ea93..f7ed7bc 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_img_gpu_clk_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_img_gpu_clk_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_img_gpu_core_clk.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_img_gpu_core_clk.rs index ca73d06..2f382ce 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_img_gpu_core_clk.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_img_gpu_core_clk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_img_gpu_sys_clk.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_img_gpu_sys_clk.rs index e8ac3ae..9519339 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_img_gpu_sys_clk.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_img_gpu_sys_clk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sd_ahb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sd_ahb.rs index ffbc74f..3beb073 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sd_ahb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sd_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sd_card.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sd_card.rs index 913e591..214fe35 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sd_card.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sd_card.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_axicfg0_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_axicfg0_axi.rs index 14ec464..5576c9b 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_axicfg0_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_axicfg0_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_cpu_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_cpu_axi.rs index e9ffd14..06eac91 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_cpu_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_cpu_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_gpu_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_gpu_axi.rs index eecfbf6..d87b04e 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_gpu_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sft7110_noc_bus_clk_gpu_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sft7110_noc_bux_clk_isp_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sft7110_noc_bux_clk_isp_axi.rs index 97bda8c..f8da2c3 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sft7110_noc_bux_clk_isp_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_sft7110_noc_bux_clk_isp_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_spi_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_spi_apb.rs index f629ac4..c8a8c3d 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_spi_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_spi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_uart_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_uart_apb.rs index 14f94d3..b6254b1 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_uart_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_uart_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_uart_core.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_uart_core.rs index d03321e..af24d86 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u0_uart_core.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u0_uart_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_can_ctrl_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_can_ctrl_apb.rs index 2d3ddc1..91bb2df 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_can_ctrl_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_can_ctrl_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_can_ctrl_can.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_can_ctrl_can.rs index f3ef999..1d6597c 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_can_ctrl_can.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_can_ctrl_can.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_can_ctrl_tim.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_can_ctrl_tim.rs index 59fda4d..baa9a9d 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_can_ctrl_tim.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_can_ctrl_tim.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2c_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2c_apb.rs index b109d7b..7eacf9c 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2c_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2c_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2s_tx_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2s_tx_apb.rs index 08fb166..2c64a0e 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2s_tx_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2s_tx_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_4ch1_bclk_mst.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_4ch1_bclk_mst.rs index 3311c15..8bb7661 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_4ch1_bclk_mst.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_4ch1_bclk_mst.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_4ch1_bclk_mst_inv.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_4ch1_bclk_mst_inv.rs index 6f33044..34a7fdf 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_4ch1_bclk_mst_inv.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_4ch1_bclk_mst_inv.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_bclk.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_bclk.rs index 2b90c32..751c872 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_bclk.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_bclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2stx_4ch1_bclk_mst, clk_i2stx_bclk_ext"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2stx_4ch1_bclk_mst, clk_i2stx_bclk_ext"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch1_bclk_mst, clk_i2stx_bclk_ext"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch1_bclk_mst, clk_i2stx_bclk_ext"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_bclk_neg.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_bclk_neg.rs index c69854f..52a542b 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_bclk_neg.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_bclk_neg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_polarity` reader - 1: Clock inverter, 0: Clock buffer"] pub type CLK_POLARITY_R = crate::BitReader; #[doc = "Field `clk_polarity` writer - 1: Clock inverter, 0: Clock buffer"] -pub type CLK_POLARITY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 30 - 1: Clock inverter, 0: Clock buffer"] #[inline(always)] #[must_use] - pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { - CLK_POLARITY_W::new(self) + pub fn clk_polarity(&mut self) -> CLK_POLARITY_W { + CLK_POLARITY_W::new(self, 30) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_lrck.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_lrck.rs index 1296825..c699878 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_lrck.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_i2stx_lrck.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_mux_sel` reader - Clock multiplexing selector: clk_i2stx_4ch1_lrck_mst, clk_i2stx_lrck_ext"] pub type CLK_MUX_SEL_R = crate::FieldReader; #[doc = "Field `clk_mux_sel` writer - Clock multiplexing selector: clk_i2stx_4ch1_lrck_mst, clk_i2stx_lrck_ext"] -pub type CLK_MUX_SEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; +pub type CLK_MUX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch1_lrck_mst, clk_i2stx_lrck_ext"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 24:29 - Clock multiplexing selector: clk_i2stx_4ch1_lrck_mst, clk_i2stx_lrck_ext"] #[inline(always)] #[must_use] - pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { - CLK_MUX_SEL_W::new(self) + pub fn clk_mux_sel(&mut self) -> CLK_MUX_SEL_W { + CLK_MUX_SEL_W::new(self, 24) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_sd_ahb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_sd_ahb.rs index db57421..721548e 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_sd_ahb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_sd_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_sd_card.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_sd_card.rs index 381ffaf..99c4303 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_sd_card.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_sd_card.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_spi_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_spi_apb.rs index be9e4ee..79c5d4d 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_spi_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_spi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_uart_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_uart_apb.rs index 41da55e..a0dba7b 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_uart_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_uart_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_uart_core.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_uart_core.rs index be0fea1..84b7e7e 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u1_uart_core.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u1_uart_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u2_i2c_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u2_i2c_apb.rs index 844d1ee..ba1619e 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u2_i2c_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u2_i2c_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u2_spi_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u2_spi_apb.rs index 8e02071..5678f49 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u2_spi_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u2_spi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u2_uart_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u2_uart_apb.rs index 3def501..8ffe72c 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u2_uart_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u2_uart_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u2_uart_core.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u2_uart_core.rs index 1651273..558493f 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u2_uart_core.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u2_uart_core.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u3_i2c_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u3_i2c_apb.rs index 358bfe5..0c7fbe7 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u3_i2c_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u3_i2c_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u3_spi_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u3_spi_apb.rs index e88cbe1..e6ae423 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u3_spi_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u3_spi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u3_uart_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u3_uart_apb.rs index 79be0b1..09f186a 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u3_uart_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u3_uart_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u3_uart_core.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u3_uart_core.rs index 1f6c1fd..c7b7e79 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u3_uart_core.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u3_uart_core.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u4_i2c_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u4_i2c_apb.rs index 06c8bea..c276ad5 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u4_i2c_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u4_i2c_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u4_spi_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u4_spi_apb.rs index 9ea42ec..a597aa8 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u4_spi_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u4_spi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u4_uart_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u4_uart_apb.rs index 0897ec6..8f3aae2 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u4_uart_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u4_uart_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u4_uart_core.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u4_uart_core.rs index 39c3884..8a40590 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u4_uart_core.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u4_uart_core.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u5_i2c_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u5_i2c_apb.rs index 7c427b4..f33be86 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u5_i2c_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u5_i2c_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u5_spi_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u5_spi_apb.rs index bf7775c..cdab8dc 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u5_spi_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u5_spi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u5_uart_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u5_uart_apb.rs index 6692b1e..35f37a4 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u5_uart_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u5_uart_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u5_uart_core.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u5_uart_core.rs index bcbddb6..61d5279 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u5_uart_core.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u5_uart_core.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u6_i2c_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u6_i2c_apb.rs index 0e59082..ba496ed 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u6_i2c_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u6_i2c_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u6_spi_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u6_spi_apb.rs index 6fc3721..150f5f4 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u6_spi_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u6_spi_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core0.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core0.rs index eda1657..3d1a8b0 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core0.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core1.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core1.rs index bca30e8..37797ad 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core1.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core1.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core2.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core2.rs index 58a976e..2051161 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core2.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core2.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core3.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core3.rs index acfefac..7f225e6 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core3.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core3.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core4.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core4.rs index ad29b28..1fc5258 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core4.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_core4.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_debug.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_debug.rs index 2cc9043..550262b 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_debug.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_debug.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace0.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace0.rs index 4745687..f7e648d 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace0.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace0.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace1.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace1.rs index 2eb77fa..6633efe 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace1.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace1.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace2.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace2.rs index 3768a89..1803426 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace2.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace2.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace3.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace3.rs index 8407a97..a7766ea 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace3.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace3.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace4.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace4.rs index fb02b26..1089592 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace4.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace4.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace_com.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace_com.rs index 48f2b75..106673f 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace_com.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_u7mc_trace_com.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_usb_125m.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_usb_125m.rs index cf1b913..3add98d 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_usb_125m.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_usb_125m.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_vdec_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_vdec_axi.rs index 8e3dc27..d3e92d5 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_vdec_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_vdec_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_venc_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_venc_axi.rs index d6daec4..6ba93e4 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_venc_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_venc_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_vout_ahb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_vout_ahb.rs index 4928864..f908152 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_vout_ahb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_vout_ahb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_vout_axi_divcfg.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_vout_axi_divcfg.rs index 24e0339..0470524 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_vout_axi_divcfg.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_vout_axi_divcfg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_vout_axi_icg.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_vout_axi_icg.rs index d6c6b97..c79dccb 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_vout_axi_icg.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_vout_axi_icg.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_vout_hdmi_tx0_mclk.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_vout_hdmi_tx0_mclk.rs index afe7731..de966b9 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_vout_hdmi_tx0_mclk.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_vout_hdmi_tx0_mclk.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_vout_mipi_phy.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_vout_mipi_phy.rs index 6b66d29..0eea4b3 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_vout_mipi_phy.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_vout_mipi_phy.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_wave420l_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_wave420l_apb.rs index 04791a2..321eb6f 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_wave420l_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_wave420l_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_wave420l_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_wave420l_axi.rs index 634fc09..bbc3254 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_wave420l_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_wave420l_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_wave420l_bpu.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_wave420l_bpu.rs index 88776c7..36ed24b 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_wave420l_bpu.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_wave420l_bpu.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_wave420l_vce.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_wave420l_vce.rs index 38f4298..28baaf9 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_wave420l_vce.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_wave420l_vce.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_apb.rs index 2f1e92d..ca4a7ec 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_axi.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_axi.rs index 7d01fe2..1eb107c 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_axi.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_axi.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_bpu.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_bpu.rs index 4b1344d..aff7c45 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_bpu.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_bpu.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_jpg_arb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_jpg_arb.rs index da0bce6..18aaf68 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_jpg_arb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_jpg_arb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_jpg_main.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_jpg_main.rs index d54a5cd..2d6395d 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_jpg_main.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_jpg_main.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_vce.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_vce.rs index 2c1957b..6bb2382 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_vce.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_wave511_vce.rs @@ -5,11 +5,11 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=7, Default=2, Min=3, Typical=2"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=7, Default=2, Min=3, Typical=2"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=2, Min=3, Typical=2"] #[inline(always)] @@ -26,16 +26,20 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=7, Default=2, Min=3, Typical=2"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_wdt.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_wdt.rs index 416a9cd..dfd64d0 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_wdt.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_wdt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/clk_wdt_apb.rs b/jh7110-vf2-13b-pac/src/syscrg/clk_wdt_apb.rs index 558e6b7..4b63ed5 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/clk_wdt_apb.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/clk_wdt_apb.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"] pub type CLK_ICG_R = crate::BitReader; #[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"] -pub type CLK_ICG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"] #[inline(always)] #[must_use] - pub fn clk_icg(&mut self) -> CLK_ICG_W { - CLK_ICG_W::new(self) + pub fn clk_icg(&mut self) -> CLK_ICG_W { + CLK_ICG_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/soft_rst0_addr_sel.rs b/jh7110-vf2-13b-pac/src/syscrg/soft_rst0_addr_sel.rs index 05e5c2a..1690ed5 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/soft_rst0_addr_sel.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/soft_rst0_addr_sel.rs @@ -5,140 +5,131 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_jtag2apb_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_JTAG2APB_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_jtag2apb_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_JTAG2APB_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_JTAG2APB_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_sys_syscon_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SYS_SYSCON_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_sys_syscon_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SYS_SYSCON_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SYS_SYSCON_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_sys_iomux_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SYS_IOMUX_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_sys_iomux_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SYS_IOMUX_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SYS_IOMUX_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_bus` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_BUS_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_bus` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_BUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_BUS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_debug_reset` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_DEBUG_RESET_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_debug_reset` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_DEBUG_RESET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_DEBUG_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core0` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE0_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core1` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE1_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core1` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core2` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE2_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core2` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core3` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE3_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core3` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE3_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core4` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE4_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core4` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE4_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core0_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE0_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core0_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE0_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core1_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE1_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core1_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE1_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core2_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE2_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core2_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE2_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core3_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE3_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core3_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE3_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE3_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core4_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE4_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core4_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE4_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE4_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst0` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST0_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst1` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST1_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst1` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst2` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST2_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst2` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst3` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST3_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst3` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST3_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst4` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST4_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst4` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST4_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_com_rst` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_COM_RST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_com_rst` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_COM_RST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_COM_RST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_img_gpu_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_IMG_GPU_RSTN_APB_R = crate::BitReader; #[doc = "Field `rst_u0_img_gpu_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_IMG_GPU_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_IMG_GPU_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_img_gpu_rstn_doma` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_IMG_GPU_RSTN_DOMA_R = crate::BitReader; #[doc = "Field `rst_u0_img_gpu_rstn_doma` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_IMG_GPU_RSTN_DOMA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_IMG_GPU_RSTN_DOMA_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_apb_bus_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_apb_bus_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_axicfg0_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_axicfg0_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_cpu_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_cpu_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_disp_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_disp_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_gpu_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_gpu_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_isp_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_isp_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_ddrc_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_ddrc_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_stg_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_stg_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_vdec_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_vdec_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -325,258 +316,262 @@ impl W { #[must_use] pub fn rstn_u0_jtag2apb_presetn( &mut self, - ) -> RSTN_U0_JTAG2APB_PRESETN_W { - RSTN_U0_JTAG2APB_PRESETN_W::new(self) + ) -> RSTN_U0_JTAG2APB_PRESETN_W { + RSTN_U0_JTAG2APB_PRESETN_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_sys_syscon_presetn( &mut self, - ) -> RSTN_U0_SYS_SYSCON_PRESETN_W { - RSTN_U0_SYS_SYSCON_PRESETN_W::new(self) + ) -> RSTN_U0_SYS_SYSCON_PRESETN_W { + RSTN_U0_SYS_SYSCON_PRESETN_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_sys_iomux_presetn( &mut self, - ) -> RSTN_U0_SYS_IOMUX_PRESETN_W { - RSTN_U0_SYS_IOMUX_PRESETN_W::new(self) + ) -> RSTN_U0_SYS_IOMUX_PRESETN_W { + RSTN_U0_SYS_IOMUX_PRESETN_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_bus( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_BUS_W { - RST_U0_U7MC_SFT7110_RST_BUS_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_BUS_W { + RST_U0_U7MC_SFT7110_RST_BUS_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_debug_reset( &mut self, - ) -> RST_U0_U7MC_SFT7110_DEBUG_RESET_W { - RST_U0_U7MC_SFT7110_DEBUG_RESET_W::new(self) + ) -> RST_U0_U7MC_SFT7110_DEBUG_RESET_W { + RST_U0_U7MC_SFT7110_DEBUG_RESET_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core0( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE0_W { - RST_U0_U7MC_SFT7110_RST_CORE0_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE0_W { + RST_U0_U7MC_SFT7110_RST_CORE0_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core1( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE1_W { - RST_U0_U7MC_SFT7110_RST_CORE1_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE1_W { + RST_U0_U7MC_SFT7110_RST_CORE1_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core2( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE2_W { - RST_U0_U7MC_SFT7110_RST_CORE2_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE2_W { + RST_U0_U7MC_SFT7110_RST_CORE2_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core3( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE3_W { - RST_U0_U7MC_SFT7110_RST_CORE3_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE3_W { + RST_U0_U7MC_SFT7110_RST_CORE3_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core4( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE4_W { - RST_U0_U7MC_SFT7110_RST_CORE4_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE4_W { + RST_U0_U7MC_SFT7110_RST_CORE4_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core0_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE0_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE0_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE0_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE0_ST_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core1_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE1_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE1_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE1_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE1_ST_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core2_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE2_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE2_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE2_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE2_ST_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core3_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE3_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE3_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE3_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE3_ST_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core4_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE4_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE4_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE4_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE4_ST_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst0( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST0_W { - RST_U0_U7MC_SFT7110_TRACE_RST0_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST0_W { + RST_U0_U7MC_SFT7110_TRACE_RST0_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst1( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST1_W { - RST_U0_U7MC_SFT7110_TRACE_RST1_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST1_W { + RST_U0_U7MC_SFT7110_TRACE_RST1_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst2( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST2_W { - RST_U0_U7MC_SFT7110_TRACE_RST2_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST2_W { + RST_U0_U7MC_SFT7110_TRACE_RST2_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst3( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST3_W { - RST_U0_U7MC_SFT7110_TRACE_RST3_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST3_W { + RST_U0_U7MC_SFT7110_TRACE_RST3_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst4( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST4_W { - RST_U0_U7MC_SFT7110_TRACE_RST4_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST4_W { + RST_U0_U7MC_SFT7110_TRACE_RST4_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_com_rst( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_COM_RST_W { - RST_U0_U7MC_SFT7110_TRACE_COM_RST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_COM_RST_W { + RST_U0_U7MC_SFT7110_TRACE_COM_RST_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_img_gpu_rstn_apb( &mut self, - ) -> RST_U0_IMG_GPU_RSTN_APB_W { - RST_U0_IMG_GPU_RSTN_APB_W::new(self) + ) -> RST_U0_IMG_GPU_RSTN_APB_W { + RST_U0_IMG_GPU_RSTN_APB_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_img_gpu_rstn_doma( &mut self, - ) -> RST_U0_IMG_GPU_RSTN_DOMA_W { - RST_U0_IMG_GPU_RSTN_DOMA_W::new(self) + ) -> RST_U0_IMG_GPU_RSTN_DOMA_W { + RST_U0_IMG_GPU_RSTN_DOMA_W::new(self, 22) } #[doc = "Bit 23 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_apb_bus_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W::new(self, 23) } #[doc = "Bit 24 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_axicfg0_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W::new(self, 24) } #[doc = "Bit 25 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_cpu_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W::new(self, 25) } #[doc = "Bit 26 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_disp_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W::new(self, 26) } #[doc = "Bit 27 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_gpu_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W::new(self, 27) } #[doc = "Bit 28 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_isp_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W::new(self, 28) } #[doc = "Bit 29 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_ddrc_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W::new(self, 29) } #[doc = "Bit 30 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_stg_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W::new(self, 30) } #[doc = "Bit 31 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_vdec_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/soft_rst1_addr_sel.rs b/jh7110-vf2-13b-pac/src/syscrg/soft_rst1_addr_sel.rs index d3a8ec9..704da18 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/soft_rst1_addr_sel.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/soft_rst1_addr_sel.rs @@ -5,135 +5,132 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_sft7100_noc_bus_reset_venc_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_R = crate::BitReader; #[doc = "Field `rstn_u0_sft7100_noc_bus_reset_venc_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg1_dec_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg1_dec_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg1_dec_rstn_main` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg1_dec_rstn_main` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_main` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_main` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_main_div` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_main_div` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_hifi4` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_hifi4` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DDR_SFT7110_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DDR_SFT7110_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DDR_SFT7110_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_osc` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DDR_SFT7110_RSTN_OSC_R = crate::BitReader; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_osc` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DDR_SFT7110_RSTN_OSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DDR_SFT7110_RSTN_OSC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DDR_SFT7110_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DDR_SFT7110_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DDR_SFT7110_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dom_isp_top_rstn_dom_isp_top_ip_top_reset_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_R = crate::BitReader; #[doc = "Field `rstn_u0_dom_isp_top_rstn_dom_isp_top_ip_top_reset_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dom_isp_top_rstn_dom_isp_top_rstn_isp_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_dom_isp_top_rstn_dom_isp_top_rstn_isp_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_R = crate::BitReader; #[doc = "Field `rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W<'a, REG> = + crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_codaj12_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CODAJ12_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_codaj12_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CODAJ12_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CODAJ12_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_codaj12_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CODAJ12_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u0_codaj12_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CODAJ12_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CODAJ12_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_codaj12_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CODAJ12_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_codaj12_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CODAJ12_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CODAJ12_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave511_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE511_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_wave511_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE511_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE511_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave511_rstn_bpu` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE511_RSTN_BPU_R = crate::BitReader; #[doc = "Field `rstn_u0_wave511_rstn_bpu` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE511_RSTN_BPU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE511_RSTN_BPU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave511_rstn_vce` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE511_RSTN_VCE_R = crate::BitReader; #[doc = "Field `rstn_u0_wave511_rstn_vce` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE511_RSTN_VCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE511_RSTN_VCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave511_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE511_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_wave511_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE511_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE511_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_vdec_jpg_arb_jpgresetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_VDEC_JPG_ARB_JPGRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_vdec_jpg_arb_jpgresetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_vdec_jpg_arb_mainresetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_VDEC_JPG_ARB_MAINRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_vdec_jpg_arb_mainresetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_aximem_128b_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXIMEM_128B_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_aximem_128b_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXIMEM_128B_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXIMEM_128B_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave420l_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE420L_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_wave420l_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE420L_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE420L_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave420l_rstn_bpu` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE420L_RSTN_BPU_R = crate::BitReader; #[doc = "Field `rstn_u0_wave420l_rstn_bpu` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE420L_RSTN_BPU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE420L_RSTN_BPU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave420l_rstn_vce` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE420L_RSTN_VCE_R = crate::BitReader; #[doc = "Field `rstn_u0_wave420l_rstn_vce` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE420L_RSTN_VCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE420L_RSTN_VCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave420l_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE420L_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_wave420l_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE420L_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE420L_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_aximem_128b_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_AXIMEM_128B_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u1_aximem_128b_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_AXIMEM_128B_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_AXIMEM_128B_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_aximem_128b_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_AXIMEM_128B_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u2_aximem_128b_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_AXIMEM_128B_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_AXIMEM_128B_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_intmem_rom_sram_rstn_rom` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_R = crate::BitReader; #[doc = "Field `rstn_u0_intmem_rom_sram_rstn_rom` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdns_qspi_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDNS_QSPI_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdns_qspi_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDNS_QSPI_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDNS_QSPI_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdns_qspi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDNS_QSPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdns_qspi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDNS_QSPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDNS_QSPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdns_qspi_rstn_ref` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDNS_QSPI_RSTN_REF_R = crate::BitReader; #[doc = "Field `rstn_u0_cdns_qspi_rstn_ref` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDNS_QSPI_RSTN_REF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDNS_QSPI_RSTN_REF_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -310,258 +307,262 @@ impl W { #[must_use] pub fn rstn_u0_sft7100_noc_bus_reset_venc_axi_n( &mut self, - ) -> RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W { - RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W::new(self) + ) -> RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W { + RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg1_dec_rstn_ahb( &mut self, - ) -> RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W { - RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W::new(self) + ) -> RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W { + RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg1_dec_rstn_main( &mut self, - ) -> RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W { - RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W::new(self) + ) -> RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W { + RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg0_dec_rstn_main( &mut self, - ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W { - RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W::new(self) + ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W { + RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg0_dec_rstn_main_div( &mut self, - ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W { - RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W::new(self) + ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W { + RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg0_dec_rstn_hifi4( &mut self, - ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W { - RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W::new(self) + ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W { + RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_ddr_sft7110_rstn_axi( &mut self, - ) -> RSTN_U0_DDR_SFT7110_RSTN_AXI_W { - RSTN_U0_DDR_SFT7110_RSTN_AXI_W::new(self) + ) -> RSTN_U0_DDR_SFT7110_RSTN_AXI_W { + RSTN_U0_DDR_SFT7110_RSTN_AXI_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_ddr_sft7110_rstn_osc( &mut self, - ) -> RSTN_U0_DDR_SFT7110_RSTN_OSC_W { - RSTN_U0_DDR_SFT7110_RSTN_OSC_W::new(self) + ) -> RSTN_U0_DDR_SFT7110_RSTN_OSC_W { + RSTN_U0_DDR_SFT7110_RSTN_OSC_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_ddr_sft7110_rstn_apb( &mut self, - ) -> RSTN_U0_DDR_SFT7110_RSTN_APB_W { - RSTN_U0_DDR_SFT7110_RSTN_APB_W::new(self) + ) -> RSTN_U0_DDR_SFT7110_RSTN_APB_W { + RSTN_U0_DDR_SFT7110_RSTN_APB_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dom_isp_top_rstn_dom_isp_top_ip_top_reset_n( &mut self, - ) -> RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W { - RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W::new(self) + ) -> RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W { + RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dom_isp_top_rstn_dom_isp_top_rstn_isp_axi( &mut self, - ) -> RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W { - RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W::new(self) + ) -> RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W { + RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src( &mut self, - ) -> RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W { - RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W::new(self) + ) -> RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W { + RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_codaj12_rstn_axi( &mut self, - ) -> RSTN_U0_CODAJ12_RSTN_AXI_W { - RSTN_U0_CODAJ12_RSTN_AXI_W::new(self) + ) -> RSTN_U0_CODAJ12_RSTN_AXI_W { + RSTN_U0_CODAJ12_RSTN_AXI_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_codaj12_rstn_core( &mut self, - ) -> RSTN_U0_CODAJ12_RSTN_CORE_W { - RSTN_U0_CODAJ12_RSTN_CORE_W::new(self) + ) -> RSTN_U0_CODAJ12_RSTN_CORE_W { + RSTN_U0_CODAJ12_RSTN_CORE_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_codaj12_rstn_apb( &mut self, - ) -> RSTN_U0_CODAJ12_RSTN_APB_W { - RSTN_U0_CODAJ12_RSTN_APB_W::new(self) + ) -> RSTN_U0_CODAJ12_RSTN_APB_W { + RSTN_U0_CODAJ12_RSTN_APB_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave511_rstn_axi( &mut self, - ) -> RSTN_U0_WAVE511_RSTN_AXI_W { - RSTN_U0_WAVE511_RSTN_AXI_W::new(self) + ) -> RSTN_U0_WAVE511_RSTN_AXI_W { + RSTN_U0_WAVE511_RSTN_AXI_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave511_rstn_bpu( &mut self, - ) -> RSTN_U0_WAVE511_RSTN_BPU_W { - RSTN_U0_WAVE511_RSTN_BPU_W::new(self) + ) -> RSTN_U0_WAVE511_RSTN_BPU_W { + RSTN_U0_WAVE511_RSTN_BPU_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave511_rstn_vce( &mut self, - ) -> RSTN_U0_WAVE511_RSTN_VCE_W { - RSTN_U0_WAVE511_RSTN_VCE_W::new(self) + ) -> RSTN_U0_WAVE511_RSTN_VCE_W { + RSTN_U0_WAVE511_RSTN_VCE_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave511_rstn_apb( &mut self, - ) -> RSTN_U0_WAVE511_RSTN_APB_W { - RSTN_U0_WAVE511_RSTN_APB_W::new(self) + ) -> RSTN_U0_WAVE511_RSTN_APB_W { + RSTN_U0_WAVE511_RSTN_APB_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_vdec_jpg_arb_jpgresetn( &mut self, - ) -> RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W { - RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W::new(self) + ) -> RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W { + RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_vdec_jpg_arb_mainresetn( &mut self, - ) -> RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W { - RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W::new(self) + ) -> RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W { + RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_aximem_128b_rstn_axi( &mut self, - ) -> RSTN_U0_AXIMEM_128B_RSTN_AXI_W { - RSTN_U0_AXIMEM_128B_RSTN_AXI_W::new(self) + ) -> RSTN_U0_AXIMEM_128B_RSTN_AXI_W { + RSTN_U0_AXIMEM_128B_RSTN_AXI_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave420l_rstn_axi( &mut self, - ) -> RSTN_U0_WAVE420L_RSTN_AXI_W { - RSTN_U0_WAVE420L_RSTN_AXI_W::new(self) + ) -> RSTN_U0_WAVE420L_RSTN_AXI_W { + RSTN_U0_WAVE420L_RSTN_AXI_W::new(self, 22) } #[doc = "Bit 23 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave420l_rstn_bpu( &mut self, - ) -> RSTN_U0_WAVE420L_RSTN_BPU_W { - RSTN_U0_WAVE420L_RSTN_BPU_W::new(self) + ) -> RSTN_U0_WAVE420L_RSTN_BPU_W { + RSTN_U0_WAVE420L_RSTN_BPU_W::new(self, 23) } #[doc = "Bit 24 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave420l_rstn_vce( &mut self, - ) -> RSTN_U0_WAVE420L_RSTN_VCE_W { - RSTN_U0_WAVE420L_RSTN_VCE_W::new(self) + ) -> RSTN_U0_WAVE420L_RSTN_VCE_W { + RSTN_U0_WAVE420L_RSTN_VCE_W::new(self, 24) } #[doc = "Bit 25 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave420l_rstn_apb( &mut self, - ) -> RSTN_U0_WAVE420L_RSTN_APB_W { - RSTN_U0_WAVE420L_RSTN_APB_W::new(self) + ) -> RSTN_U0_WAVE420L_RSTN_APB_W { + RSTN_U0_WAVE420L_RSTN_APB_W::new(self, 25) } #[doc = "Bit 26 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_aximem_128b_rstn_axi( &mut self, - ) -> RSTN_U1_AXIMEM_128B_RSTN_AXI_W { - RSTN_U1_AXIMEM_128B_RSTN_AXI_W::new(self) + ) -> RSTN_U1_AXIMEM_128B_RSTN_AXI_W { + RSTN_U1_AXIMEM_128B_RSTN_AXI_W::new(self, 26) } #[doc = "Bit 27 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u2_aximem_128b_rstn_axi( &mut self, - ) -> RSTN_U2_AXIMEM_128B_RSTN_AXI_W { - RSTN_U2_AXIMEM_128B_RSTN_AXI_W::new(self) + ) -> RSTN_U2_AXIMEM_128B_RSTN_AXI_W { + RSTN_U2_AXIMEM_128B_RSTN_AXI_W::new(self, 27) } #[doc = "Bit 28 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_intmem_rom_sram_rstn_rom( &mut self, - ) -> RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W { - RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W::new(self) + ) -> RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W { + RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W::new(self, 28) } #[doc = "Bit 29 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdns_qspi_rstn_ahb( &mut self, - ) -> RSTN_U0_CDNS_QSPI_RSTN_AHB_W { - RSTN_U0_CDNS_QSPI_RSTN_AHB_W::new(self) + ) -> RSTN_U0_CDNS_QSPI_RSTN_AHB_W { + RSTN_U0_CDNS_QSPI_RSTN_AHB_W::new(self, 29) } #[doc = "Bit 30 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdns_qspi_rstn_apb( &mut self, - ) -> RSTN_U0_CDNS_QSPI_RSTN_APB_W { - RSTN_U0_CDNS_QSPI_RSTN_APB_W::new(self) + ) -> RSTN_U0_CDNS_QSPI_RSTN_APB_W { + RSTN_U0_CDNS_QSPI_RSTN_APB_W::new(self, 30) } #[doc = "Bit 31 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdns_qspi_rstn_ref( &mut self, - ) -> RSTN_U0_CDNS_QSPI_RSTN_REF_W { - RSTN_U0_CDNS_QSPI_RSTN_REF_W::new(self) + ) -> RSTN_U0_CDNS_QSPI_RSTN_REF_W { + RSTN_U0_CDNS_QSPI_RSTN_REF_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/soft_rst2_addr_sel.rs b/jh7110-vf2-13b-pac/src/syscrg/soft_rst2_addr_sel.rs index a9a2df4..28f2199 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/soft_rst2_addr_sel.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/soft_rst2_addr_sel.rs @@ -5,131 +5,131 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_sdio_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SDIO_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_sdio_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SDIO_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SDIO_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_sdi_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_SDI_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u1_sdi_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_SDI_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_SDI_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_gmac5_axi64_aresetn_i` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_GMAC5_AXI64_ARESETN_I_R = crate::BitReader; #[doc = "Field `rstn_u1_gmac5_axi64_aresetn_i` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_GMAC5_AXI64_ARESETN_I_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_GMAC5_AXI64_ARESETN_I_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_gmac5_axi64_hresetn_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_GMAC5_AXI64_HRESETN_N_R = crate::BitReader; #[doc = "Field `rstn_u1_gmac5_axi64_hresetn_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_GMAC5_AXI64_HRESETN_N_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_GMAC5_AXI64_HRESETN_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_mailbox_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_MAILBOX_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_mailbox_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_MAILBOX_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_MAILBOX_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u2_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u3_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U3_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u3_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U3_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U3_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u4_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U4_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u4_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U4_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U4_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u5_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U5_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u5_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U5_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U5_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u6_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U6_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u6_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U6_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U6_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u2_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u3_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U3_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u3_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U3_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U3_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u4_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U4_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u4_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U4_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U4_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u5_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U5_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u5_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U5_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U5_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u6_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U6_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u6_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U6_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U6_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u0_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u1_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u2_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u2_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u3_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U3_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u3_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U3_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U3_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u3_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U3_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u3_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U3_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U3_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u4_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U4_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u4_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U4_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U4_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u4_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U4_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u4_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U4_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U4_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u5_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U5_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u5_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U5_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U5_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u6_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U6_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u6_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U6_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U6_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdns_spdif_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDNS_SPDIF_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdns_spdif_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDNS_SPDIF_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDNS_SPDIF_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -296,242 +296,222 @@ impl W { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_sdio_rstn_ahb(&mut self) -> RSTN_U0_SDIO_RSTN_AHB_W { - RSTN_U0_SDIO_RSTN_AHB_W::new(self) + pub fn rstn_u0_sdio_rstn_ahb(&mut self) -> RSTN_U0_SDIO_RSTN_AHB_W { + RSTN_U0_SDIO_RSTN_AHB_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u1_sdi_rstn_ahb(&mut self) -> RSTN_U1_SDI_RSTN_AHB_W { - RSTN_U1_SDI_RSTN_AHB_W::new(self) + pub fn rstn_u1_sdi_rstn_ahb(&mut self) -> RSTN_U1_SDI_RSTN_AHB_W { + RSTN_U1_SDI_RSTN_AHB_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_gmac5_axi64_aresetn_i( &mut self, - ) -> RSTN_U1_GMAC5_AXI64_ARESETN_I_W { - RSTN_U1_GMAC5_AXI64_ARESETN_I_W::new(self) + ) -> RSTN_U1_GMAC5_AXI64_ARESETN_I_W { + RSTN_U1_GMAC5_AXI64_ARESETN_I_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_gmac5_axi64_hresetn_n( &mut self, - ) -> RSTN_U1_GMAC5_AXI64_HRESETN_N_W { - RSTN_U1_GMAC5_AXI64_HRESETN_N_W::new(self) + ) -> RSTN_U1_GMAC5_AXI64_HRESETN_N_W { + RSTN_U1_GMAC5_AXI64_HRESETN_N_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_mailbox_presetn( &mut self, - ) -> RSTN_U0_MAILBOX_PRESETN_W { - RSTN_U0_MAILBOX_PRESETN_W::new(self) + ) -> RSTN_U0_MAILBOX_PRESETN_W { + RSTN_U0_MAILBOX_PRESETN_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U0_SSP_SPI_RSTN_APB_W { - RSTN_U0_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U0_SSP_SPI_RSTN_APB_W { + RSTN_U0_SSP_SPI_RSTN_APB_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U1_SSP_SPI_RSTN_APB_W { - RSTN_U1_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U1_SSP_SPI_RSTN_APB_W { + RSTN_U1_SSP_SPI_RSTN_APB_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u2_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U2_SSP_SPI_RSTN_APB_W { - RSTN_U2_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U2_SSP_SPI_RSTN_APB_W { + RSTN_U2_SSP_SPI_RSTN_APB_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u3_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U3_SSP_SPI_RSTN_APB_W { - RSTN_U3_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U3_SSP_SPI_RSTN_APB_W { + RSTN_U3_SSP_SPI_RSTN_APB_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u4_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U4_SSP_SPI_RSTN_APB_W { - RSTN_U4_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U4_SSP_SPI_RSTN_APB_W { + RSTN_U4_SSP_SPI_RSTN_APB_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u5_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U5_SSP_SPI_RSTN_APB_W { - RSTN_U5_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U5_SSP_SPI_RSTN_APB_W { + RSTN_U5_SSP_SPI_RSTN_APB_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u6_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U6_SSP_SPI_RSTN_APB_W { - RSTN_U6_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U6_SSP_SPI_RSTN_APB_W { + RSTN_U6_SSP_SPI_RSTN_APB_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_i2c_rstn_apb(&mut self) -> RSTN_U0_I2C_RSTN_APB_W { - RSTN_U0_I2C_RSTN_APB_W::new(self) + pub fn rstn_u0_i2c_rstn_apb(&mut self) -> RSTN_U0_I2C_RSTN_APB_W { + RSTN_U0_I2C_RSTN_APB_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u1_i2c_rstn_apb(&mut self) -> RSTN_U1_I2C_RSTN_APB_W { - RSTN_U1_I2C_RSTN_APB_W::new(self) + pub fn rstn_u1_i2c_rstn_apb(&mut self) -> RSTN_U1_I2C_RSTN_APB_W { + RSTN_U1_I2C_RSTN_APB_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u2_i2c_rstn_apb(&mut self) -> RSTN_U2_I2C_RSTN_APB_W { - RSTN_U2_I2C_RSTN_APB_W::new(self) + pub fn rstn_u2_i2c_rstn_apb(&mut self) -> RSTN_U2_I2C_RSTN_APB_W { + RSTN_U2_I2C_RSTN_APB_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u3_i2c_rstn_apb(&mut self) -> RSTN_U3_I2C_RSTN_APB_W { - RSTN_U3_I2C_RSTN_APB_W::new(self) + pub fn rstn_u3_i2c_rstn_apb(&mut self) -> RSTN_U3_I2C_RSTN_APB_W { + RSTN_U3_I2C_RSTN_APB_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u4_i2c_rstn_apb(&mut self) -> RSTN_U4_I2C_RSTN_APB_W { - RSTN_U4_I2C_RSTN_APB_W::new(self) + pub fn rstn_u4_i2c_rstn_apb(&mut self) -> RSTN_U4_I2C_RSTN_APB_W { + RSTN_U4_I2C_RSTN_APB_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u5_i2c_rstn_apb(&mut self) -> RSTN_U5_I2C_RSTN_APB_W { - RSTN_U5_I2C_RSTN_APB_W::new(self) + pub fn rstn_u5_i2c_rstn_apb(&mut self) -> RSTN_U5_I2C_RSTN_APB_W { + RSTN_U5_I2C_RSTN_APB_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u6_i2c_rstn_apb(&mut self) -> RSTN_U6_I2C_RSTN_APB_W { - RSTN_U6_I2C_RSTN_APB_W::new(self) + pub fn rstn_u6_i2c_rstn_apb(&mut self) -> RSTN_U6_I2C_RSTN_APB_W { + RSTN_U6_I2C_RSTN_APB_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_uart_rstn_apb( - &mut self, - ) -> RSTN_U0_UART_RSTN_APB_W { - RSTN_U0_UART_RSTN_APB_W::new(self) + pub fn rstn_u0_uart_rstn_apb(&mut self) -> RSTN_U0_UART_RSTN_APB_W { + RSTN_U0_UART_RSTN_APB_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_uart_rstn_core( - &mut self, - ) -> RSTN_U0_UART_RSTN_CORE_W { - RSTN_U0_UART_RSTN_CORE_W::new(self) + pub fn rstn_u0_uart_rstn_core(&mut self) -> RSTN_U0_UART_RSTN_CORE_W { + RSTN_U0_UART_RSTN_CORE_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u1_uart_rstn_apb( - &mut self, - ) -> RSTN_U1_UART_RSTN_APB_W { - RSTN_U1_UART_RSTN_APB_W::new(self) + pub fn rstn_u1_uart_rstn_apb(&mut self) -> RSTN_U1_UART_RSTN_APB_W { + RSTN_U1_UART_RSTN_APB_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u1_uart_rstn_core( - &mut self, - ) -> RSTN_U1_UART_RSTN_CORE_W { - RSTN_U1_UART_RSTN_CORE_W::new(self) + pub fn rstn_u1_uart_rstn_core(&mut self) -> RSTN_U1_UART_RSTN_CORE_W { + RSTN_U1_UART_RSTN_CORE_W::new(self, 22) } #[doc = "Bit 23 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u2_uart_rstn_apb( - &mut self, - ) -> RSTN_U2_UART_RSTN_APB_W { - RSTN_U2_UART_RSTN_APB_W::new(self) + pub fn rstn_u2_uart_rstn_apb(&mut self) -> RSTN_U2_UART_RSTN_APB_W { + RSTN_U2_UART_RSTN_APB_W::new(self, 23) } #[doc = "Bit 24 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u2_uart_rstn_core( - &mut self, - ) -> RSTN_U2_UART_RSTN_CORE_W { - RSTN_U2_UART_RSTN_CORE_W::new(self) + pub fn rstn_u2_uart_rstn_core(&mut self) -> RSTN_U2_UART_RSTN_CORE_W { + RSTN_U2_UART_RSTN_CORE_W::new(self, 24) } #[doc = "Bit 25 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u3_uart_rstn_apb( - &mut self, - ) -> RSTN_U3_UART_RSTN_APB_W { - RSTN_U3_UART_RSTN_APB_W::new(self) + pub fn rstn_u3_uart_rstn_apb(&mut self) -> RSTN_U3_UART_RSTN_APB_W { + RSTN_U3_UART_RSTN_APB_W::new(self, 25) } #[doc = "Bit 26 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u3_uart_rstn_core( - &mut self, - ) -> RSTN_U3_UART_RSTN_CORE_W { - RSTN_U3_UART_RSTN_CORE_W::new(self) + pub fn rstn_u3_uart_rstn_core(&mut self) -> RSTN_U3_UART_RSTN_CORE_W { + RSTN_U3_UART_RSTN_CORE_W::new(self, 26) } #[doc = "Bit 27 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u4_uart_rstn_apb( - &mut self, - ) -> RSTN_U4_UART_RSTN_APB_W { - RSTN_U4_UART_RSTN_APB_W::new(self) + pub fn rstn_u4_uart_rstn_apb(&mut self) -> RSTN_U4_UART_RSTN_APB_W { + RSTN_U4_UART_RSTN_APB_W::new(self, 27) } #[doc = "Bit 28 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u4_uart_rstn_core( - &mut self, - ) -> RSTN_U4_UART_RSTN_CORE_W { - RSTN_U4_UART_RSTN_CORE_W::new(self) + pub fn rstn_u4_uart_rstn_core(&mut self) -> RSTN_U4_UART_RSTN_CORE_W { + RSTN_U4_UART_RSTN_CORE_W::new(self, 28) } #[doc = "Bit 29 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u5_uart_rstn_apb( - &mut self, - ) -> RSTN_U5_UART_RSTN_APB_W { - RSTN_U5_UART_RSTN_APB_W::new(self) + pub fn rstn_u5_uart_rstn_apb(&mut self) -> RSTN_U5_UART_RSTN_APB_W { + RSTN_U5_UART_RSTN_APB_W::new(self, 29) } #[doc = "Bit 30 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u6_uart_rstn_core( - &mut self, - ) -> RSTN_U6_UART_RSTN_CORE_W { - RSTN_U6_UART_RSTN_CORE_W::new(self) + pub fn rstn_u6_uart_rstn_core(&mut self) -> RSTN_U6_UART_RSTN_CORE_W { + RSTN_U6_UART_RSTN_CORE_W::new(self, 30) } #[doc = "Bit 31 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdns_spdif_rstn_apb( &mut self, - ) -> RSTN_U0_CDNS_SPDIF_RSTN_APB_W { - RSTN_U0_CDNS_SPDIF_RSTN_APB_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> RSTN_U0_CDNS_SPDIF_RSTN_APB_W { + RSTN_U0_CDNS_SPDIF_RSTN_APB_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/soft_rst3_addr_sel.rs b/jh7110-vf2-13b-pac/src/syscrg/soft_rst3_addr_sel.rs index bd0d372..2127cd6 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/soft_rst3_addr_sel.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/soft_rst3_addr_sel.rs @@ -5,123 +5,123 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_pwmdac_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PWMDAC_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_pwmdac_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PWMDAC_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PWMDAC_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_pdm_4mic_rstn_dmic` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PDM_4MIC_RSTN_DMIC_R = crate::BitReader; #[doc = "Field `rstn_u0_pdm_4mic_rstn_dmic` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PDM_4MIC_RSTN_DMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PDM_4MIC_RSTN_DMIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_pdm_4mic_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PDM_4MIC_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_pdm_4mic_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PDM_4MIC_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PDM_4MIC_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2srx_3ch_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2SRX_3CH_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_i2srx_3ch_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2SRX_3CH_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2SRX_3CH_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2srx_3ch_rstn_bclk` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2SRX_3CH_RSTN_BCLK_R = crate::BitReader; #[doc = "Field `rstn_u0_i2srx_3ch_rstn_bclk` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2SRX_3CH_RSTN_BCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2SRX_3CH_RSTN_BCLK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2stx_4ch_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2STX_4CH_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_i2stx_4ch_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2STX_4CH_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2STX_4CH_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2stx_4ch_rstn_bclk` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2STX_4CH_RSTN_BCLK_R = crate::BitReader; #[doc = "Field `rstn_u0_i2stx_4ch_rstn_bclk` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2STX_4CH_RSTN_BCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2STX_4CH_RSTN_BCLK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_i2stx_4ch_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_I2STX_4CH_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_i2stx_4ch_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_I2STX_4CH_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_I2STX_4CH_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_i2stx_4ch_rstn_bclk` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_I2STX_4CH_RSTN_BCLK_R = crate::BitReader; #[doc = "Field `rstn_u1_i2stx_4ch_rstn_bclk` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_I2STX_4CH_RSTN_BCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_I2STX_4CH_RSTN_BCLK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_tdm16slot_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TDM16SLOT_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_tdm16slot_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TDM16SLOT_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TDM16SLOT_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_tdm16slot_rstn_tdm` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TDM16SLOT_RSTN_TDM_R = crate::BitReader; #[doc = "Field `rstn_u0_tdm16slot_rstn_tdm` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TDM16SLOT_RSTN_TDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TDM16SLOT_RSTN_TDM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_tdm16slot_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TDM16SLOT_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_tdm16slot_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TDM16SLOT_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TDM16SLOT_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_pwm_8ch_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PWM_8CH_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_pwm_8ch_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PWM_8CH_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PWM_8CH_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dskit_wdt_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DSKIT_WDT_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_dskit_wdt_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DSKIT_WDT_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DSKIT_WDT_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dskit_wdt_rstn_wdt` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DSKIT_WDT_RSTN_WDT_R = crate::BitReader; #[doc = "Field `rstn_u0_dskit_wdt_rstn_wdt` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DSKIT_WDT_RSTN_WDT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DSKIT_WDT_RSTN_WDT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_can_ctrl_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CAN_CTRL_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_can_ctrl_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CAN_CTRL_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CAN_CTRL_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_can_ctrl_rstn_can` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CAN_CTRL_RSTN_CAN_R = crate::BitReader; #[doc = "Field `rstn_u0_can_ctrl_rstn_can` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CAN_CTRL_RSTN_CAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CAN_CTRL_RSTN_CAN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_can_ctrl_rstn_timer` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CAN_CTRL_RSTN_TIMER_R = crate::BitReader; #[doc = "Field `rstn_u0_can_ctrl_rstn_timer` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CAN_CTRL_RSTN_TIMER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CAN_CTRL_RSTN_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_can_ctrl_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_CAN_CTRL_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_can_ctrl_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_CAN_CTRL_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_CAN_CTRL_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_can_ctrl_rstn_can` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_CAN_CTRL_RSTN_CAN_R = crate::BitReader; #[doc = "Field `rstn_u1_can_ctrl_rstn_can` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_CAN_CTRL_RSTN_CAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_CAN_CTRL_RSTN_CAN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_can_ctrl_rstn_timer` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_CAN_CTRL_RSTN_TIMER_R = crate::BitReader; #[doc = "Field `rstn_u1_can_ctrl_rstn_timer` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_CAN_CTRL_RSTN_TIMER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_CAN_CTRL_RSTN_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_timer0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_TIMER0_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_timer0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_TIMER0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_TIMER0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_time10` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_TIME10_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_time10` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_TIME10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_TIME10_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_timer2` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_TIMER2_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_timer2` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_TIMER2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_TIMER2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_timer3` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_TIMER3_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_timer3` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_TIMER3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_TIMER3_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_int_ctrl_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_INT_CTRL_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_int_ctrl_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_INT_CTRL_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_INT_CTRL_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_temp_sensor_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TEMP_SENSOR_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_temp_sensor_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TEMP_SENSOR_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TEMP_SENSOR_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_temp_sensor_rstn_temp` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TEMP_SENSOR_RSTN_TEMP_R = crate::BitReader; #[doc = "Field `rstn_u0_temp_sensor_rstn_temp` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_jtag_certification_rst_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_JTAG_CERTIFICATION_RST_N_R = crate::BitReader; #[doc = "Field `rstn_u0_jtag_certification_rst_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_JTAG_CERTIFICATION_RST_N_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_JTAG_CERTIFICATION_RST_N_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -280,242 +280,246 @@ impl W { #[must_use] pub fn rstn_u0_pwmdac_rstn_apb( &mut self, - ) -> RSTN_U0_PWMDAC_RSTN_APB_W { - RSTN_U0_PWMDAC_RSTN_APB_W::new(self) + ) -> RSTN_U0_PWMDAC_RSTN_APB_W { + RSTN_U0_PWMDAC_RSTN_APB_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_pdm_4mic_rstn_dmic( &mut self, - ) -> RSTN_U0_PDM_4MIC_RSTN_DMIC_W { - RSTN_U0_PDM_4MIC_RSTN_DMIC_W::new(self) + ) -> RSTN_U0_PDM_4MIC_RSTN_DMIC_W { + RSTN_U0_PDM_4MIC_RSTN_DMIC_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_pdm_4mic_rstn_apb( &mut self, - ) -> RSTN_U0_PDM_4MIC_RSTN_APB_W { - RSTN_U0_PDM_4MIC_RSTN_APB_W::new(self) + ) -> RSTN_U0_PDM_4MIC_RSTN_APB_W { + RSTN_U0_PDM_4MIC_RSTN_APB_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_i2srx_3ch_rstn_apb( &mut self, - ) -> RSTN_U0_I2SRX_3CH_RSTN_APB_W { - RSTN_U0_I2SRX_3CH_RSTN_APB_W::new(self) + ) -> RSTN_U0_I2SRX_3CH_RSTN_APB_W { + RSTN_U0_I2SRX_3CH_RSTN_APB_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_i2srx_3ch_rstn_bclk( &mut self, - ) -> RSTN_U0_I2SRX_3CH_RSTN_BCLK_W { - RSTN_U0_I2SRX_3CH_RSTN_BCLK_W::new(self) + ) -> RSTN_U0_I2SRX_3CH_RSTN_BCLK_W { + RSTN_U0_I2SRX_3CH_RSTN_BCLK_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_i2stx_4ch_rstn_apb( &mut self, - ) -> RSTN_U0_I2STX_4CH_RSTN_APB_W { - RSTN_U0_I2STX_4CH_RSTN_APB_W::new(self) + ) -> RSTN_U0_I2STX_4CH_RSTN_APB_W { + RSTN_U0_I2STX_4CH_RSTN_APB_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_i2stx_4ch_rstn_bclk( &mut self, - ) -> RSTN_U0_I2STX_4CH_RSTN_BCLK_W { - RSTN_U0_I2STX_4CH_RSTN_BCLK_W::new(self) + ) -> RSTN_U0_I2STX_4CH_RSTN_BCLK_W { + RSTN_U0_I2STX_4CH_RSTN_BCLK_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_i2stx_4ch_rstn_apb( &mut self, - ) -> RSTN_U1_I2STX_4CH_RSTN_APB_W { - RSTN_U1_I2STX_4CH_RSTN_APB_W::new(self) + ) -> RSTN_U1_I2STX_4CH_RSTN_APB_W { + RSTN_U1_I2STX_4CH_RSTN_APB_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_i2stx_4ch_rstn_bclk( &mut self, - ) -> RSTN_U1_I2STX_4CH_RSTN_BCLK_W { - RSTN_U1_I2STX_4CH_RSTN_BCLK_W::new(self) + ) -> RSTN_U1_I2STX_4CH_RSTN_BCLK_W { + RSTN_U1_I2STX_4CH_RSTN_BCLK_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_tdm16slot_rstn_ahb( &mut self, - ) -> RSTN_U0_TDM16SLOT_RSTN_AHB_W { - RSTN_U0_TDM16SLOT_RSTN_AHB_W::new(self) + ) -> RSTN_U0_TDM16SLOT_RSTN_AHB_W { + RSTN_U0_TDM16SLOT_RSTN_AHB_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_tdm16slot_rstn_tdm( &mut self, - ) -> RSTN_U0_TDM16SLOT_RSTN_TDM_W { - RSTN_U0_TDM16SLOT_RSTN_TDM_W::new(self) + ) -> RSTN_U0_TDM16SLOT_RSTN_TDM_W { + RSTN_U0_TDM16SLOT_RSTN_TDM_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_tdm16slot_rstn_apb( &mut self, - ) -> RSTN_U0_TDM16SLOT_RSTN_APB_W { - RSTN_U0_TDM16SLOT_RSTN_APB_W::new(self) + ) -> RSTN_U0_TDM16SLOT_RSTN_APB_W { + RSTN_U0_TDM16SLOT_RSTN_APB_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_pwm_8ch_rstn_apb( &mut self, - ) -> RSTN_U0_PWM_8CH_RSTN_APB_W { - RSTN_U0_PWM_8CH_RSTN_APB_W::new(self) + ) -> RSTN_U0_PWM_8CH_RSTN_APB_W { + RSTN_U0_PWM_8CH_RSTN_APB_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dskit_wdt_rstn_apb( &mut self, - ) -> RSTN_U0_DSKIT_WDT_RSTN_APB_W { - RSTN_U0_DSKIT_WDT_RSTN_APB_W::new(self) + ) -> RSTN_U0_DSKIT_WDT_RSTN_APB_W { + RSTN_U0_DSKIT_WDT_RSTN_APB_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dskit_wdt_rstn_wdt( &mut self, - ) -> RSTN_U0_DSKIT_WDT_RSTN_WDT_W { - RSTN_U0_DSKIT_WDT_RSTN_WDT_W::new(self) + ) -> RSTN_U0_DSKIT_WDT_RSTN_WDT_W { + RSTN_U0_DSKIT_WDT_RSTN_WDT_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_can_ctrl_rstn_apb( &mut self, - ) -> RSTN_U0_CAN_CTRL_RSTN_APB_W { - RSTN_U0_CAN_CTRL_RSTN_APB_W::new(self) + ) -> RSTN_U0_CAN_CTRL_RSTN_APB_W { + RSTN_U0_CAN_CTRL_RSTN_APB_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_can_ctrl_rstn_can( &mut self, - ) -> RSTN_U0_CAN_CTRL_RSTN_CAN_W { - RSTN_U0_CAN_CTRL_RSTN_CAN_W::new(self) + ) -> RSTN_U0_CAN_CTRL_RSTN_CAN_W { + RSTN_U0_CAN_CTRL_RSTN_CAN_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_can_ctrl_rstn_timer( &mut self, - ) -> RSTN_U0_CAN_CTRL_RSTN_TIMER_W { - RSTN_U0_CAN_CTRL_RSTN_TIMER_W::new(self) + ) -> RSTN_U0_CAN_CTRL_RSTN_TIMER_W { + RSTN_U0_CAN_CTRL_RSTN_TIMER_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_can_ctrl_rstn_apb( &mut self, - ) -> RSTN_U1_CAN_CTRL_RSTN_APB_W { - RSTN_U1_CAN_CTRL_RSTN_APB_W::new(self) + ) -> RSTN_U1_CAN_CTRL_RSTN_APB_W { + RSTN_U1_CAN_CTRL_RSTN_APB_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_can_ctrl_rstn_can( &mut self, - ) -> RSTN_U1_CAN_CTRL_RSTN_CAN_W { - RSTN_U1_CAN_CTRL_RSTN_CAN_W::new(self) + ) -> RSTN_U1_CAN_CTRL_RSTN_CAN_W { + RSTN_U1_CAN_CTRL_RSTN_CAN_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_can_ctrl_rstn_timer( &mut self, - ) -> RSTN_U1_CAN_CTRL_RSTN_TIMER_W { - RSTN_U1_CAN_CTRL_RSTN_TIMER_W::new(self) + ) -> RSTN_U1_CAN_CTRL_RSTN_TIMER_W { + RSTN_U1_CAN_CTRL_RSTN_TIMER_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_apb( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_APB_W { - RSTN_U0_SI5_TIMER_RSTN_APB_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_APB_W { + RSTN_U0_SI5_TIMER_RSTN_APB_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_timer0( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER0_W { - RSTN_U0_SI5_TIMER_RSTN_TIMER0_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER0_W { + RSTN_U0_SI5_TIMER_RSTN_TIMER0_W::new(self, 22) } #[doc = "Bit 23 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_time10( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_TIME10_W { - RSTN_U0_SI5_TIMER_RSTN_TIME10_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_TIME10_W { + RSTN_U0_SI5_TIMER_RSTN_TIME10_W::new(self, 23) } #[doc = "Bit 24 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_timer2( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER2_W { - RSTN_U0_SI5_TIMER_RSTN_TIMER2_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER2_W { + RSTN_U0_SI5_TIMER_RSTN_TIMER2_W::new(self, 24) } #[doc = "Bit 25 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_timer3( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER3_W { - RSTN_U0_SI5_TIMER_RSTN_TIMER3_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER3_W { + RSTN_U0_SI5_TIMER_RSTN_TIMER3_W::new(self, 25) } #[doc = "Bit 26 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_int_ctrl_rstn_apb( &mut self, - ) -> RSTN_U0_INT_CTRL_RSTN_APB_W { - RSTN_U0_INT_CTRL_RSTN_APB_W::new(self) + ) -> RSTN_U0_INT_CTRL_RSTN_APB_W { + RSTN_U0_INT_CTRL_RSTN_APB_W::new(self, 26) } #[doc = "Bit 27 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_temp_sensor_rstn_apb( &mut self, - ) -> RSTN_U0_TEMP_SENSOR_RSTN_APB_W { - RSTN_U0_TEMP_SENSOR_RSTN_APB_W::new(self) + ) -> RSTN_U0_TEMP_SENSOR_RSTN_APB_W { + RSTN_U0_TEMP_SENSOR_RSTN_APB_W::new(self, 27) } #[doc = "Bit 28 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_temp_sensor_rstn_temp( &mut self, - ) -> RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W { - RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W::new(self) + ) -> RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W { + RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W::new(self, 28) } #[doc = "Bit 29 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_jtag_certification_rst_n( &mut self, - ) -> RSTN_U0_JTAG_CERTIFICATION_RST_N_W { - RSTN_U0_JTAG_CERTIFICATION_RST_N_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> RSTN_U0_JTAG_CERTIFICATION_RST_N_W { + RSTN_U0_JTAG_CERTIFICATION_RST_N_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/syscrg_rst0_status.rs b/jh7110-vf2-13b-pac/src/syscrg/syscrg_rst0_status.rs index 5fa6e96..4d11058 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/syscrg_rst0_status.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/syscrg_rst0_status.rs @@ -5,140 +5,131 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_jtag2apb_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_JTAG2APB_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_jtag2apb_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_JTAG2APB_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_JTAG2APB_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_sys_syscon_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SYS_SYSCON_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_sys_syscon_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SYS_SYSCON_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SYS_SYSCON_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_sys_iomux_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SYS_IOMUX_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_sys_iomux_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SYS_IOMUX_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SYS_IOMUX_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_bus` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_BUS_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_bus` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_BUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_BUS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_debug_reset` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_DEBUG_RESET_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_debug_reset` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_DEBUG_RESET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_DEBUG_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core0` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE0_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core1` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE1_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core1` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core2` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE2_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core2` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core3` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE3_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core3` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE3_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core4` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE4_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core4` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE4_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core0_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE0_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core0_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE0_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core1_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE1_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core1_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE1_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core2_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE2_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core2_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE2_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core3_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE3_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core3_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE3_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE3_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core4_st` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_RST_CORE4_ST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_rst_core4_st` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_RST_CORE4_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_RST_CORE4_ST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst0` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST0_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst1` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST1_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst1` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst2` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST2_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst2` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst3` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST3_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst3` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST3_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst4` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_RST4_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_rst4` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_RST4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_RST4_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_trace_com_rst` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_TRACE_COM_RST_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_trace_com_rst` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_TRACE_COM_RST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_TRACE_COM_RST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_img_gpu_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_IMG_GPU_RSTN_APB_R = crate::BitReader; #[doc = "Field `rst_u0_img_gpu_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_IMG_GPU_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_IMG_GPU_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_img_gpu_rstn_doma` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_IMG_GPU_RSTN_DOMA_R = crate::BitReader; #[doc = "Field `rst_u0_img_gpu_rstn_doma` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_IMG_GPU_RSTN_DOMA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RST_U0_IMG_GPU_RSTN_DOMA_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_apb_bus_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_apb_bus_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_axicfg0_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_axicfg0_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_cpu_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_cpu_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_disp_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_disp_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_gpu_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_gpu_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_isp_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_isp_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_ddrc_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_ddrc_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_stg_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_stg_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_vdec_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_R = crate::BitReader; #[doc = "Field `rst_u0_u7mc_sft7110_noc_bus_reset_vdec_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -325,258 +316,262 @@ impl W { #[must_use] pub fn rstn_u0_jtag2apb_presetn( &mut self, - ) -> RSTN_U0_JTAG2APB_PRESETN_W { - RSTN_U0_JTAG2APB_PRESETN_W::new(self) + ) -> RSTN_U0_JTAG2APB_PRESETN_W { + RSTN_U0_JTAG2APB_PRESETN_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_sys_syscon_presetn( &mut self, - ) -> RSTN_U0_SYS_SYSCON_PRESETN_W { - RSTN_U0_SYS_SYSCON_PRESETN_W::new(self) + ) -> RSTN_U0_SYS_SYSCON_PRESETN_W { + RSTN_U0_SYS_SYSCON_PRESETN_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_sys_iomux_presetn( &mut self, - ) -> RSTN_U0_SYS_IOMUX_PRESETN_W { - RSTN_U0_SYS_IOMUX_PRESETN_W::new(self) + ) -> RSTN_U0_SYS_IOMUX_PRESETN_W { + RSTN_U0_SYS_IOMUX_PRESETN_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_bus( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_BUS_W { - RST_U0_U7MC_SFT7110_RST_BUS_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_BUS_W { + RST_U0_U7MC_SFT7110_RST_BUS_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_debug_reset( &mut self, - ) -> RST_U0_U7MC_SFT7110_DEBUG_RESET_W { - RST_U0_U7MC_SFT7110_DEBUG_RESET_W::new(self) + ) -> RST_U0_U7MC_SFT7110_DEBUG_RESET_W { + RST_U0_U7MC_SFT7110_DEBUG_RESET_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core0( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE0_W { - RST_U0_U7MC_SFT7110_RST_CORE0_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE0_W { + RST_U0_U7MC_SFT7110_RST_CORE0_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core1( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE1_W { - RST_U0_U7MC_SFT7110_RST_CORE1_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE1_W { + RST_U0_U7MC_SFT7110_RST_CORE1_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core2( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE2_W { - RST_U0_U7MC_SFT7110_RST_CORE2_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE2_W { + RST_U0_U7MC_SFT7110_RST_CORE2_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core3( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE3_W { - RST_U0_U7MC_SFT7110_RST_CORE3_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE3_W { + RST_U0_U7MC_SFT7110_RST_CORE3_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core4( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE4_W { - RST_U0_U7MC_SFT7110_RST_CORE4_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE4_W { + RST_U0_U7MC_SFT7110_RST_CORE4_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core0_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE0_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE0_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE0_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE0_ST_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core1_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE1_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE1_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE1_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE1_ST_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core2_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE2_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE2_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE2_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE2_ST_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core3_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE3_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE3_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE3_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE3_ST_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_rst_core4_st( &mut self, - ) -> RST_U0_U7MC_SFT7110_RST_CORE4_ST_W { - RST_U0_U7MC_SFT7110_RST_CORE4_ST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_RST_CORE4_ST_W { + RST_U0_U7MC_SFT7110_RST_CORE4_ST_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst0( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST0_W { - RST_U0_U7MC_SFT7110_TRACE_RST0_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST0_W { + RST_U0_U7MC_SFT7110_TRACE_RST0_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst1( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST1_W { - RST_U0_U7MC_SFT7110_TRACE_RST1_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST1_W { + RST_U0_U7MC_SFT7110_TRACE_RST1_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst2( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST2_W { - RST_U0_U7MC_SFT7110_TRACE_RST2_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST2_W { + RST_U0_U7MC_SFT7110_TRACE_RST2_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst3( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST3_W { - RST_U0_U7MC_SFT7110_TRACE_RST3_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST3_W { + RST_U0_U7MC_SFT7110_TRACE_RST3_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_rst4( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_RST4_W { - RST_U0_U7MC_SFT7110_TRACE_RST4_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_RST4_W { + RST_U0_U7MC_SFT7110_TRACE_RST4_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_trace_com_rst( &mut self, - ) -> RST_U0_U7MC_SFT7110_TRACE_COM_RST_W { - RST_U0_U7MC_SFT7110_TRACE_COM_RST_W::new(self) + ) -> RST_U0_U7MC_SFT7110_TRACE_COM_RST_W { + RST_U0_U7MC_SFT7110_TRACE_COM_RST_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_img_gpu_rstn_apb( &mut self, - ) -> RST_U0_IMG_GPU_RSTN_APB_W { - RST_U0_IMG_GPU_RSTN_APB_W::new(self) + ) -> RST_U0_IMG_GPU_RSTN_APB_W { + RST_U0_IMG_GPU_RSTN_APB_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_img_gpu_rstn_doma( &mut self, - ) -> RST_U0_IMG_GPU_RSTN_DOMA_W { - RST_U0_IMG_GPU_RSTN_DOMA_W::new(self) + ) -> RST_U0_IMG_GPU_RSTN_DOMA_W { + RST_U0_IMG_GPU_RSTN_DOMA_W::new(self, 22) } #[doc = "Bit 23 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_apb_bus_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_APB_BUS_N_W::new(self, 23) } #[doc = "Bit 24 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_axicfg0_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_AXICFG0_AXI_N_W::new(self, 24) } #[doc = "Bit 25 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_cpu_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_CPU_AXI_N_W::new(self, 25) } #[doc = "Bit 26 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_disp_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DISP_AXI_N_W::new(self, 26) } #[doc = "Bit 27 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_gpu_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_GPU_AXI_N_W::new(self, 27) } #[doc = "Bit 28 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_isp_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_ISP_AXI_N_W::new(self, 28) } #[doc = "Bit 29 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_ddrc_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_DDRC_N_W::new(self, 29) } #[doc = "Bit 30 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_stg_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_STG_AXI_N_W::new(self, 30) } #[doc = "Bit 31 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rst_u0_u7mc_sft7110_noc_bus_reset_vdec_axi_n( &mut self, - ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W { - RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W::new(self) + ) -> RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W { + RST_U0_U7MC_SFT7110_NOC_BUS_RESET_VDEC_AXI_N_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/syscrg_rst1_status.rs b/jh7110-vf2-13b-pac/src/syscrg/syscrg_rst1_status.rs index 5eabcc1..8c45e48 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/syscrg_rst1_status.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/syscrg_rst1_status.rs @@ -5,135 +5,132 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_sft7100_noc_bus_reset_venc_axi_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_R = crate::BitReader; #[doc = "Field `rstn_u0_sft7100_noc_bus_reset_venc_axi_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg1_dec_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg1_dec_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg1_dec_rstn_main` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg1_dec_rstn_main` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_main` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_main` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_main_div` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_main_div` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_hifi4` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_R = crate::BitReader; #[doc = "Field `rstn_u0_axi_cfg0_dec_rstn_hifi4` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DDR_SFT7110_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DDR_SFT7110_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DDR_SFT7110_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_osc` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DDR_SFT7110_RSTN_OSC_R = crate::BitReader; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_osc` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DDR_SFT7110_RSTN_OSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DDR_SFT7110_RSTN_OSC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DDR_SFT7110_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_ddr_sft7110_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DDR_SFT7110_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DDR_SFT7110_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dom_isp_top_rstn_dom_isp_top_ip_top_reset_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_R = crate::BitReader; #[doc = "Field `rstn_u0_dom_isp_top_rstn_dom_isp_top_ip_top_reset_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dom_isp_top_rstn_dom_isp_top_rstn_isp_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_dom_isp_top_rstn_dom_isp_top_rstn_isp_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_R = crate::BitReader; #[doc = "Field `rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W<'a, REG, const O: u8> = - crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W<'a, REG> = + crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_codaj12_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CODAJ12_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_codaj12_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CODAJ12_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CODAJ12_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_codaj12_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CODAJ12_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u0_codaj12_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CODAJ12_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CODAJ12_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_codaj12_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CODAJ12_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_codaj12_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CODAJ12_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CODAJ12_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave511_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE511_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_wave511_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE511_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE511_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave511_rstn_bpu` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE511_RSTN_BPU_R = crate::BitReader; #[doc = "Field `rstn_u0_wave511_rstn_bpu` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE511_RSTN_BPU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE511_RSTN_BPU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave511_rstn_vce` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE511_RSTN_VCE_R = crate::BitReader; #[doc = "Field `rstn_u0_wave511_rstn_vce` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE511_RSTN_VCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE511_RSTN_VCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave511_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE511_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_wave511_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE511_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE511_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_vdec_jpg_arb_jpgresetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_VDEC_JPG_ARB_JPGRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_vdec_jpg_arb_jpgresetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_vdec_jpg_arb_mainresetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_VDEC_JPG_ARB_MAINRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_vdec_jpg_arb_mainresetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_aximem_128b_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_AXIMEM_128B_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_aximem_128b_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_AXIMEM_128B_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_AXIMEM_128B_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave420l_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE420L_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u0_wave420l_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE420L_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE420L_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave420l_rstn_bpu` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE420L_RSTN_BPU_R = crate::BitReader; #[doc = "Field `rstn_u0_wave420l_rstn_bpu` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE420L_RSTN_BPU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE420L_RSTN_BPU_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave420l_rstn_vce` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE420L_RSTN_VCE_R = crate::BitReader; #[doc = "Field `rstn_u0_wave420l_rstn_vce` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE420L_RSTN_VCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE420L_RSTN_VCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_wave420l_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_WAVE420L_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_wave420l_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_WAVE420L_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_WAVE420L_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_aximem_128b_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_AXIMEM_128B_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u1_aximem_128b_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_AXIMEM_128B_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_AXIMEM_128B_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_aximem_128b_rstn_axi` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_AXIMEM_128B_RSTN_AXI_R = crate::BitReader; #[doc = "Field `rstn_u2_aximem_128b_rstn_axi` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_AXIMEM_128B_RSTN_AXI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_AXIMEM_128B_RSTN_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_intmem_rom_sram_rstn_rom` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_R = crate::BitReader; #[doc = "Field `rstn_u0_intmem_rom_sram_rstn_rom` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdns_qspi_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDNS_QSPI_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdns_qspi_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDNS_QSPI_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDNS_QSPI_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdns_qspi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDNS_QSPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdns_qspi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDNS_QSPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDNS_QSPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdns_qspi_rstn_ref` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDNS_QSPI_RSTN_REF_R = crate::BitReader; #[doc = "Field `rstn_u0_cdns_qspi_rstn_ref` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDNS_QSPI_RSTN_REF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDNS_QSPI_RSTN_REF_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -310,258 +307,262 @@ impl W { #[must_use] pub fn rstn_u0_sft7100_noc_bus_reset_venc_axi_n( &mut self, - ) -> RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W { - RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W::new(self) + ) -> RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W { + RSTN_U0_SFT7100_NOC_BUS_RESET_VENC_AXI_N_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg1_dec_rstn_ahb( &mut self, - ) -> RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W { - RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W::new(self) + ) -> RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W { + RSTN_U0_AXI_CFG1_DEC_RSTN_AHB_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg1_dec_rstn_main( &mut self, - ) -> RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W { - RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W::new(self) + ) -> RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W { + RSTN_U0_AXI_CFG1_DEC_RSTN_MAIN_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg0_dec_rstn_main( &mut self, - ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W { - RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W::new(self) + ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W { + RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg0_dec_rstn_main_div( &mut self, - ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W { - RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W::new(self) + ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W { + RSTN_U0_AXI_CFG0_DEC_RSTN_MAIN_DIV_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_axi_cfg0_dec_rstn_hifi4( &mut self, - ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W { - RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W::new(self) + ) -> RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W { + RSTN_U0_AXI_CFG0_DEC_RSTN_HIFI4_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_ddr_sft7110_rstn_axi( &mut self, - ) -> RSTN_U0_DDR_SFT7110_RSTN_AXI_W { - RSTN_U0_DDR_SFT7110_RSTN_AXI_W::new(self) + ) -> RSTN_U0_DDR_SFT7110_RSTN_AXI_W { + RSTN_U0_DDR_SFT7110_RSTN_AXI_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_ddr_sft7110_rstn_osc( &mut self, - ) -> RSTN_U0_DDR_SFT7110_RSTN_OSC_W { - RSTN_U0_DDR_SFT7110_RSTN_OSC_W::new(self) + ) -> RSTN_U0_DDR_SFT7110_RSTN_OSC_W { + RSTN_U0_DDR_SFT7110_RSTN_OSC_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_ddr_sft7110_rstn_apb( &mut self, - ) -> RSTN_U0_DDR_SFT7110_RSTN_APB_W { - RSTN_U0_DDR_SFT7110_RSTN_APB_W::new(self) + ) -> RSTN_U0_DDR_SFT7110_RSTN_APB_W { + RSTN_U0_DDR_SFT7110_RSTN_APB_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dom_isp_top_rstn_dom_isp_top_ip_top_reset_n( &mut self, - ) -> RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W { - RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W::new(self) + ) -> RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W { + RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_IP_TOP_RESET_N_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dom_isp_top_rstn_dom_isp_top_rstn_isp_axi( &mut self, - ) -> RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W { - RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W::new(self) + ) -> RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W { + RSTN_U0_DOM_ISP_TOP_RSTN_DOM_ISP_TOP_RSTN_ISP_AXI_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src( &mut self, - ) -> RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W { - RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W::new(self) + ) -> RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W { + RSTN_U0_DOM_VOUT_TOP_RSTN_DOM_VOUT_TOP_RSTN_VOUT_SRC_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_codaj12_rstn_axi( &mut self, - ) -> RSTN_U0_CODAJ12_RSTN_AXI_W { - RSTN_U0_CODAJ12_RSTN_AXI_W::new(self) + ) -> RSTN_U0_CODAJ12_RSTN_AXI_W { + RSTN_U0_CODAJ12_RSTN_AXI_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_codaj12_rstn_core( &mut self, - ) -> RSTN_U0_CODAJ12_RSTN_CORE_W { - RSTN_U0_CODAJ12_RSTN_CORE_W::new(self) + ) -> RSTN_U0_CODAJ12_RSTN_CORE_W { + RSTN_U0_CODAJ12_RSTN_CORE_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_codaj12_rstn_apb( &mut self, - ) -> RSTN_U0_CODAJ12_RSTN_APB_W { - RSTN_U0_CODAJ12_RSTN_APB_W::new(self) + ) -> RSTN_U0_CODAJ12_RSTN_APB_W { + RSTN_U0_CODAJ12_RSTN_APB_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave511_rstn_axi( &mut self, - ) -> RSTN_U0_WAVE511_RSTN_AXI_W { - RSTN_U0_WAVE511_RSTN_AXI_W::new(self) + ) -> RSTN_U0_WAVE511_RSTN_AXI_W { + RSTN_U0_WAVE511_RSTN_AXI_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave511_rstn_bpu( &mut self, - ) -> RSTN_U0_WAVE511_RSTN_BPU_W { - RSTN_U0_WAVE511_RSTN_BPU_W::new(self) + ) -> RSTN_U0_WAVE511_RSTN_BPU_W { + RSTN_U0_WAVE511_RSTN_BPU_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave511_rstn_vce( &mut self, - ) -> RSTN_U0_WAVE511_RSTN_VCE_W { - RSTN_U0_WAVE511_RSTN_VCE_W::new(self) + ) -> RSTN_U0_WAVE511_RSTN_VCE_W { + RSTN_U0_WAVE511_RSTN_VCE_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave511_rstn_apb( &mut self, - ) -> RSTN_U0_WAVE511_RSTN_APB_W { - RSTN_U0_WAVE511_RSTN_APB_W::new(self) + ) -> RSTN_U0_WAVE511_RSTN_APB_W { + RSTN_U0_WAVE511_RSTN_APB_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_vdec_jpg_arb_jpgresetn( &mut self, - ) -> RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W { - RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W::new(self) + ) -> RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W { + RSTN_U0_VDEC_JPG_ARB_JPGRESETN_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_vdec_jpg_arb_mainresetn( &mut self, - ) -> RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W { - RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W::new(self) + ) -> RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W { + RSTN_U0_VDEC_JPG_ARB_MAINRESETN_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_aximem_128b_rstn_axi( &mut self, - ) -> RSTN_U0_AXIMEM_128B_RSTN_AXI_W { - RSTN_U0_AXIMEM_128B_RSTN_AXI_W::new(self) + ) -> RSTN_U0_AXIMEM_128B_RSTN_AXI_W { + RSTN_U0_AXIMEM_128B_RSTN_AXI_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave420l_rstn_axi( &mut self, - ) -> RSTN_U0_WAVE420L_RSTN_AXI_W { - RSTN_U0_WAVE420L_RSTN_AXI_W::new(self) + ) -> RSTN_U0_WAVE420L_RSTN_AXI_W { + RSTN_U0_WAVE420L_RSTN_AXI_W::new(self, 22) } #[doc = "Bit 23 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave420l_rstn_bpu( &mut self, - ) -> RSTN_U0_WAVE420L_RSTN_BPU_W { - RSTN_U0_WAVE420L_RSTN_BPU_W::new(self) + ) -> RSTN_U0_WAVE420L_RSTN_BPU_W { + RSTN_U0_WAVE420L_RSTN_BPU_W::new(self, 23) } #[doc = "Bit 24 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave420l_rstn_vce( &mut self, - ) -> RSTN_U0_WAVE420L_RSTN_VCE_W { - RSTN_U0_WAVE420L_RSTN_VCE_W::new(self) + ) -> RSTN_U0_WAVE420L_RSTN_VCE_W { + RSTN_U0_WAVE420L_RSTN_VCE_W::new(self, 24) } #[doc = "Bit 25 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_wave420l_rstn_apb( &mut self, - ) -> RSTN_U0_WAVE420L_RSTN_APB_W { - RSTN_U0_WAVE420L_RSTN_APB_W::new(self) + ) -> RSTN_U0_WAVE420L_RSTN_APB_W { + RSTN_U0_WAVE420L_RSTN_APB_W::new(self, 25) } #[doc = "Bit 26 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_aximem_128b_rstn_axi( &mut self, - ) -> RSTN_U1_AXIMEM_128B_RSTN_AXI_W { - RSTN_U1_AXIMEM_128B_RSTN_AXI_W::new(self) + ) -> RSTN_U1_AXIMEM_128B_RSTN_AXI_W { + RSTN_U1_AXIMEM_128B_RSTN_AXI_W::new(self, 26) } #[doc = "Bit 27 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u2_aximem_128b_rstn_axi( &mut self, - ) -> RSTN_U2_AXIMEM_128B_RSTN_AXI_W { - RSTN_U2_AXIMEM_128B_RSTN_AXI_W::new(self) + ) -> RSTN_U2_AXIMEM_128B_RSTN_AXI_W { + RSTN_U2_AXIMEM_128B_RSTN_AXI_W::new(self, 27) } #[doc = "Bit 28 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_intmem_rom_sram_rstn_rom( &mut self, - ) -> RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W { - RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W::new(self) + ) -> RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W { + RSTN_U0_INTMEM_ROM_SRAM_RSTN_ROM_W::new(self, 28) } #[doc = "Bit 29 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdns_qspi_rstn_ahb( &mut self, - ) -> RSTN_U0_CDNS_QSPI_RSTN_AHB_W { - RSTN_U0_CDNS_QSPI_RSTN_AHB_W::new(self) + ) -> RSTN_U0_CDNS_QSPI_RSTN_AHB_W { + RSTN_U0_CDNS_QSPI_RSTN_AHB_W::new(self, 29) } #[doc = "Bit 30 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdns_qspi_rstn_apb( &mut self, - ) -> RSTN_U0_CDNS_QSPI_RSTN_APB_W { - RSTN_U0_CDNS_QSPI_RSTN_APB_W::new(self) + ) -> RSTN_U0_CDNS_QSPI_RSTN_APB_W { + RSTN_U0_CDNS_QSPI_RSTN_APB_W::new(self, 30) } #[doc = "Bit 31 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdns_qspi_rstn_ref( &mut self, - ) -> RSTN_U0_CDNS_QSPI_RSTN_REF_W { - RSTN_U0_CDNS_QSPI_RSTN_REF_W::new(self) + ) -> RSTN_U0_CDNS_QSPI_RSTN_REF_W { + RSTN_U0_CDNS_QSPI_RSTN_REF_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/syscrg_rst2_status.rs b/jh7110-vf2-13b-pac/src/syscrg/syscrg_rst2_status.rs index f224d7e..34bfc81 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/syscrg_rst2_status.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/syscrg_rst2_status.rs @@ -5,131 +5,131 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_sdio_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SDIO_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_sdio_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SDIO_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SDIO_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_sdi_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_SDI_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u1_sdi_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_SDI_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_SDI_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_gmac5_axi64_aresetn_i` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_GMAC5_AXI64_ARESETN_I_R = crate::BitReader; #[doc = "Field `rstn_u1_gmac5_axi64_aresetn_i` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_GMAC5_AXI64_ARESETN_I_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_GMAC5_AXI64_ARESETN_I_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_gmac5_axi64_hresetn_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_GMAC5_AXI64_HRESETN_N_R = crate::BitReader; #[doc = "Field `rstn_u1_gmac5_axi64_hresetn_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_GMAC5_AXI64_HRESETN_N_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_GMAC5_AXI64_HRESETN_N_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_mailbox_presetn` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_MAILBOX_PRESETN_R = crate::BitReader; #[doc = "Field `rstn_u0_mailbox_presetn` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_MAILBOX_PRESETN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_MAILBOX_PRESETN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u2_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u3_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U3_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u3_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U3_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U3_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u4_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U4_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u4_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U4_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U4_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u5_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U5_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u5_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U5_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U5_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u6_ssp_spi_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U6_SSP_SPI_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u6_ssp_spi_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U6_SSP_SPI_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U6_SSP_SPI_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u2_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u3_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U3_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u3_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U3_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U3_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u4_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U4_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u4_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U4_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U4_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u5_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U5_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u5_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U5_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U5_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u6_i2c_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U6_I2C_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u6_i2c_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U6_I2C_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U6_I2C_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u0_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u1_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u2_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u2_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U2_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u2_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U2_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U2_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u3_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U3_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u3_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U3_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U3_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u3_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U3_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u3_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U3_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U3_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u4_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U4_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u4_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U4_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U4_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u4_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U4_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u4_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U4_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U4_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u5_uart_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U5_UART_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u5_uart_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U5_UART_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U5_UART_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u6_uart_rstn_core` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U6_UART_RSTN_CORE_R = crate::BitReader; #[doc = "Field `rstn_u6_uart_rstn_core` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U6_UART_RSTN_CORE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U6_UART_RSTN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_cdns_spdif_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CDNS_SPDIF_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_cdns_spdif_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CDNS_SPDIF_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CDNS_SPDIF_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -296,242 +296,222 @@ impl W { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_sdio_rstn_ahb(&mut self) -> RSTN_U0_SDIO_RSTN_AHB_W { - RSTN_U0_SDIO_RSTN_AHB_W::new(self) + pub fn rstn_u0_sdio_rstn_ahb(&mut self) -> RSTN_U0_SDIO_RSTN_AHB_W { + RSTN_U0_SDIO_RSTN_AHB_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u1_sdi_rstn_ahb(&mut self) -> RSTN_U1_SDI_RSTN_AHB_W { - RSTN_U1_SDI_RSTN_AHB_W::new(self) + pub fn rstn_u1_sdi_rstn_ahb(&mut self) -> RSTN_U1_SDI_RSTN_AHB_W { + RSTN_U1_SDI_RSTN_AHB_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_gmac5_axi64_aresetn_i( &mut self, - ) -> RSTN_U1_GMAC5_AXI64_ARESETN_I_W { - RSTN_U1_GMAC5_AXI64_ARESETN_I_W::new(self) + ) -> RSTN_U1_GMAC5_AXI64_ARESETN_I_W { + RSTN_U1_GMAC5_AXI64_ARESETN_I_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_gmac5_axi64_hresetn_n( &mut self, - ) -> RSTN_U1_GMAC5_AXI64_HRESETN_N_W { - RSTN_U1_GMAC5_AXI64_HRESETN_N_W::new(self) + ) -> RSTN_U1_GMAC5_AXI64_HRESETN_N_W { + RSTN_U1_GMAC5_AXI64_HRESETN_N_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_mailbox_presetn( &mut self, - ) -> RSTN_U0_MAILBOX_PRESETN_W { - RSTN_U0_MAILBOX_PRESETN_W::new(self) + ) -> RSTN_U0_MAILBOX_PRESETN_W { + RSTN_U0_MAILBOX_PRESETN_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U0_SSP_SPI_RSTN_APB_W { - RSTN_U0_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U0_SSP_SPI_RSTN_APB_W { + RSTN_U0_SSP_SPI_RSTN_APB_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U1_SSP_SPI_RSTN_APB_W { - RSTN_U1_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U1_SSP_SPI_RSTN_APB_W { + RSTN_U1_SSP_SPI_RSTN_APB_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u2_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U2_SSP_SPI_RSTN_APB_W { - RSTN_U2_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U2_SSP_SPI_RSTN_APB_W { + RSTN_U2_SSP_SPI_RSTN_APB_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u3_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U3_SSP_SPI_RSTN_APB_W { - RSTN_U3_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U3_SSP_SPI_RSTN_APB_W { + RSTN_U3_SSP_SPI_RSTN_APB_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u4_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U4_SSP_SPI_RSTN_APB_W { - RSTN_U4_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U4_SSP_SPI_RSTN_APB_W { + RSTN_U4_SSP_SPI_RSTN_APB_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u5_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U5_SSP_SPI_RSTN_APB_W { - RSTN_U5_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U5_SSP_SPI_RSTN_APB_W { + RSTN_U5_SSP_SPI_RSTN_APB_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u6_ssp_spi_rstn_apb( &mut self, - ) -> RSTN_U6_SSP_SPI_RSTN_APB_W { - RSTN_U6_SSP_SPI_RSTN_APB_W::new(self) + ) -> RSTN_U6_SSP_SPI_RSTN_APB_W { + RSTN_U6_SSP_SPI_RSTN_APB_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_i2c_rstn_apb(&mut self) -> RSTN_U0_I2C_RSTN_APB_W { - RSTN_U0_I2C_RSTN_APB_W::new(self) + pub fn rstn_u0_i2c_rstn_apb(&mut self) -> RSTN_U0_I2C_RSTN_APB_W { + RSTN_U0_I2C_RSTN_APB_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u1_i2c_rstn_apb(&mut self) -> RSTN_U1_I2C_RSTN_APB_W { - RSTN_U1_I2C_RSTN_APB_W::new(self) + pub fn rstn_u1_i2c_rstn_apb(&mut self) -> RSTN_U1_I2C_RSTN_APB_W { + RSTN_U1_I2C_RSTN_APB_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u2_i2c_rstn_apb(&mut self) -> RSTN_U2_I2C_RSTN_APB_W { - RSTN_U2_I2C_RSTN_APB_W::new(self) + pub fn rstn_u2_i2c_rstn_apb(&mut self) -> RSTN_U2_I2C_RSTN_APB_W { + RSTN_U2_I2C_RSTN_APB_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u3_i2c_rstn_apb(&mut self) -> RSTN_U3_I2C_RSTN_APB_W { - RSTN_U3_I2C_RSTN_APB_W::new(self) + pub fn rstn_u3_i2c_rstn_apb(&mut self) -> RSTN_U3_I2C_RSTN_APB_W { + RSTN_U3_I2C_RSTN_APB_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u4_i2c_rstn_apb(&mut self) -> RSTN_U4_I2C_RSTN_APB_W { - RSTN_U4_I2C_RSTN_APB_W::new(self) + pub fn rstn_u4_i2c_rstn_apb(&mut self) -> RSTN_U4_I2C_RSTN_APB_W { + RSTN_U4_I2C_RSTN_APB_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u5_i2c_rstn_apb(&mut self) -> RSTN_U5_I2C_RSTN_APB_W { - RSTN_U5_I2C_RSTN_APB_W::new(self) + pub fn rstn_u5_i2c_rstn_apb(&mut self) -> RSTN_U5_I2C_RSTN_APB_W { + RSTN_U5_I2C_RSTN_APB_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u6_i2c_rstn_apb(&mut self) -> RSTN_U6_I2C_RSTN_APB_W { - RSTN_U6_I2C_RSTN_APB_W::new(self) + pub fn rstn_u6_i2c_rstn_apb(&mut self) -> RSTN_U6_I2C_RSTN_APB_W { + RSTN_U6_I2C_RSTN_APB_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_uart_rstn_apb( - &mut self, - ) -> RSTN_U0_UART_RSTN_APB_W { - RSTN_U0_UART_RSTN_APB_W::new(self) + pub fn rstn_u0_uart_rstn_apb(&mut self) -> RSTN_U0_UART_RSTN_APB_W { + RSTN_U0_UART_RSTN_APB_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u0_uart_rstn_core( - &mut self, - ) -> RSTN_U0_UART_RSTN_CORE_W { - RSTN_U0_UART_RSTN_CORE_W::new(self) + pub fn rstn_u0_uart_rstn_core(&mut self) -> RSTN_U0_UART_RSTN_CORE_W { + RSTN_U0_UART_RSTN_CORE_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u1_uart_rstn_apb( - &mut self, - ) -> RSTN_U1_UART_RSTN_APB_W { - RSTN_U1_UART_RSTN_APB_W::new(self) + pub fn rstn_u1_uart_rstn_apb(&mut self) -> RSTN_U1_UART_RSTN_APB_W { + RSTN_U1_UART_RSTN_APB_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u1_uart_rstn_core( - &mut self, - ) -> RSTN_U1_UART_RSTN_CORE_W { - RSTN_U1_UART_RSTN_CORE_W::new(self) + pub fn rstn_u1_uart_rstn_core(&mut self) -> RSTN_U1_UART_RSTN_CORE_W { + RSTN_U1_UART_RSTN_CORE_W::new(self, 22) } #[doc = "Bit 23 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u2_uart_rstn_apb( - &mut self, - ) -> RSTN_U2_UART_RSTN_APB_W { - RSTN_U2_UART_RSTN_APB_W::new(self) + pub fn rstn_u2_uart_rstn_apb(&mut self) -> RSTN_U2_UART_RSTN_APB_W { + RSTN_U2_UART_RSTN_APB_W::new(self, 23) } #[doc = "Bit 24 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u2_uart_rstn_core( - &mut self, - ) -> RSTN_U2_UART_RSTN_CORE_W { - RSTN_U2_UART_RSTN_CORE_W::new(self) + pub fn rstn_u2_uart_rstn_core(&mut self) -> RSTN_U2_UART_RSTN_CORE_W { + RSTN_U2_UART_RSTN_CORE_W::new(self, 24) } #[doc = "Bit 25 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u3_uart_rstn_apb( - &mut self, - ) -> RSTN_U3_UART_RSTN_APB_W { - RSTN_U3_UART_RSTN_APB_W::new(self) + pub fn rstn_u3_uart_rstn_apb(&mut self) -> RSTN_U3_UART_RSTN_APB_W { + RSTN_U3_UART_RSTN_APB_W::new(self, 25) } #[doc = "Bit 26 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u3_uart_rstn_core( - &mut self, - ) -> RSTN_U3_UART_RSTN_CORE_W { - RSTN_U3_UART_RSTN_CORE_W::new(self) + pub fn rstn_u3_uart_rstn_core(&mut self) -> RSTN_U3_UART_RSTN_CORE_W { + RSTN_U3_UART_RSTN_CORE_W::new(self, 26) } #[doc = "Bit 27 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u4_uart_rstn_apb( - &mut self, - ) -> RSTN_U4_UART_RSTN_APB_W { - RSTN_U4_UART_RSTN_APB_W::new(self) + pub fn rstn_u4_uart_rstn_apb(&mut self) -> RSTN_U4_UART_RSTN_APB_W { + RSTN_U4_UART_RSTN_APB_W::new(self, 27) } #[doc = "Bit 28 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u4_uart_rstn_core( - &mut self, - ) -> RSTN_U4_UART_RSTN_CORE_W { - RSTN_U4_UART_RSTN_CORE_W::new(self) + pub fn rstn_u4_uart_rstn_core(&mut self) -> RSTN_U4_UART_RSTN_CORE_W { + RSTN_U4_UART_RSTN_CORE_W::new(self, 28) } #[doc = "Bit 29 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u5_uart_rstn_apb( - &mut self, - ) -> RSTN_U5_UART_RSTN_APB_W { - RSTN_U5_UART_RSTN_APB_W::new(self) + pub fn rstn_u5_uart_rstn_apb(&mut self) -> RSTN_U5_UART_RSTN_APB_W { + RSTN_U5_UART_RSTN_APB_W::new(self, 29) } #[doc = "Bit 30 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] - pub fn rstn_u6_uart_rstn_core( - &mut self, - ) -> RSTN_U6_UART_RSTN_CORE_W { - RSTN_U6_UART_RSTN_CORE_W::new(self) + pub fn rstn_u6_uart_rstn_core(&mut self) -> RSTN_U6_UART_RSTN_CORE_W { + RSTN_U6_UART_RSTN_CORE_W::new(self, 30) } #[doc = "Bit 31 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_cdns_spdif_rstn_apb( &mut self, - ) -> RSTN_U0_CDNS_SPDIF_RSTN_APB_W { - RSTN_U0_CDNS_SPDIF_RSTN_APB_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> RSTN_U0_CDNS_SPDIF_RSTN_APB_W { + RSTN_U0_CDNS_SPDIF_RSTN_APB_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/syscrg_rst3_status.rs b/jh7110-vf2-13b-pac/src/syscrg/syscrg_rst3_status.rs index 1017bc5..30c9c71 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/syscrg_rst3_status.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/syscrg_rst3_status.rs @@ -5,123 +5,123 @@ pub type W = crate::W; #[doc = "Field `rstn_u0_pwmdac_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PWMDAC_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_pwmdac_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PWMDAC_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PWMDAC_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_pdm_4mic_rstn_dmic` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PDM_4MIC_RSTN_DMIC_R = crate::BitReader; #[doc = "Field `rstn_u0_pdm_4mic_rstn_dmic` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PDM_4MIC_RSTN_DMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PDM_4MIC_RSTN_DMIC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_pdm_4mic_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PDM_4MIC_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_pdm_4mic_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PDM_4MIC_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PDM_4MIC_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2srx_3ch_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2SRX_3CH_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_i2srx_3ch_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2SRX_3CH_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2SRX_3CH_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2srx_3ch_rstn_bclk` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2SRX_3CH_RSTN_BCLK_R = crate::BitReader; #[doc = "Field `rstn_u0_i2srx_3ch_rstn_bclk` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2SRX_3CH_RSTN_BCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2SRX_3CH_RSTN_BCLK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2stx_4ch_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2STX_4CH_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_i2stx_4ch_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2STX_4CH_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2STX_4CH_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_i2stx_4ch_rstn_bclk` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_I2STX_4CH_RSTN_BCLK_R = crate::BitReader; #[doc = "Field `rstn_u0_i2stx_4ch_rstn_bclk` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_I2STX_4CH_RSTN_BCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_I2STX_4CH_RSTN_BCLK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_i2stx_4ch_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_I2STX_4CH_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_i2stx_4ch_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_I2STX_4CH_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_I2STX_4CH_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_i2stx_4ch_rstn_bclk` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_I2STX_4CH_RSTN_BCLK_R = crate::BitReader; #[doc = "Field `rstn_u1_i2stx_4ch_rstn_bclk` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_I2STX_4CH_RSTN_BCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_I2STX_4CH_RSTN_BCLK_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_tdm16slot_rstn_ahb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TDM16SLOT_RSTN_AHB_R = crate::BitReader; #[doc = "Field `rstn_u0_tdm16slot_rstn_ahb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TDM16SLOT_RSTN_AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TDM16SLOT_RSTN_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_tdm16slot_rstn_tdm` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TDM16SLOT_RSTN_TDM_R = crate::BitReader; #[doc = "Field `rstn_u0_tdm16slot_rstn_tdm` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TDM16SLOT_RSTN_TDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TDM16SLOT_RSTN_TDM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_tdm16slot_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TDM16SLOT_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_tdm16slot_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TDM16SLOT_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TDM16SLOT_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_pwm_8ch_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_PWM_8CH_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_pwm_8ch_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_PWM_8CH_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_PWM_8CH_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dskit_wdt_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DSKIT_WDT_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_dskit_wdt_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DSKIT_WDT_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DSKIT_WDT_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_dskit_wdt_rstn_wdt` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_DSKIT_WDT_RSTN_WDT_R = crate::BitReader; #[doc = "Field `rstn_u0_dskit_wdt_rstn_wdt` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_DSKIT_WDT_RSTN_WDT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_DSKIT_WDT_RSTN_WDT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_can_ctrl_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CAN_CTRL_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_can_ctrl_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CAN_CTRL_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CAN_CTRL_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_can_ctrl_rstn_can` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CAN_CTRL_RSTN_CAN_R = crate::BitReader; #[doc = "Field `rstn_u0_can_ctrl_rstn_can` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CAN_CTRL_RSTN_CAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CAN_CTRL_RSTN_CAN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_can_ctrl_rstn_timer` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_CAN_CTRL_RSTN_TIMER_R = crate::BitReader; #[doc = "Field `rstn_u0_can_ctrl_rstn_timer` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_CAN_CTRL_RSTN_TIMER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_CAN_CTRL_RSTN_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_can_ctrl_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_CAN_CTRL_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u1_can_ctrl_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_CAN_CTRL_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_CAN_CTRL_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_can_ctrl_rstn_can` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_CAN_CTRL_RSTN_CAN_R = crate::BitReader; #[doc = "Field `rstn_u1_can_ctrl_rstn_can` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_CAN_CTRL_RSTN_CAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_CAN_CTRL_RSTN_CAN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u1_can_ctrl_rstn_timer` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U1_CAN_CTRL_RSTN_TIMER_R = crate::BitReader; #[doc = "Field `rstn_u1_can_ctrl_rstn_timer` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U1_CAN_CTRL_RSTN_TIMER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U1_CAN_CTRL_RSTN_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_timer0` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_TIMER0_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_timer0` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_TIMER0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_TIMER0_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_time10` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_TIME10_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_time10` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_TIME10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_TIME10_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_timer2` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_TIMER2_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_timer2` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_TIMER2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_TIMER2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_si5_timer_rstn_timer3` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_SI5_TIMER_RSTN_TIMER3_R = crate::BitReader; #[doc = "Field `rstn_u0_si5_timer_rstn_timer3` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_SI5_TIMER_RSTN_TIMER3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_SI5_TIMER_RSTN_TIMER3_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_int_ctrl_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_INT_CTRL_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_int_ctrl_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_INT_CTRL_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_INT_CTRL_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_temp_sensor_rstn_apb` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TEMP_SENSOR_RSTN_APB_R = crate::BitReader; #[doc = "Field `rstn_u0_temp_sensor_rstn_apb` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TEMP_SENSOR_RSTN_APB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TEMP_SENSOR_RSTN_APB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_temp_sensor_rstn_temp` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_TEMP_SENSOR_RSTN_TEMP_R = crate::BitReader; #[doc = "Field `rstn_u0_temp_sensor_rstn_temp` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rstn_u0_jtag_certification_rst_n` reader - 1: Assert reset, 0: De-assert reset"] pub type RSTN_U0_JTAG_CERTIFICATION_RST_N_R = crate::BitReader; #[doc = "Field `rstn_u0_jtag_certification_rst_n` writer - 1: Assert reset, 0: De-assert reset"] -pub type RSTN_U0_JTAG_CERTIFICATION_RST_N_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RSTN_U0_JTAG_CERTIFICATION_RST_N_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] @@ -280,242 +280,246 @@ impl W { #[must_use] pub fn rstn_u0_pwmdac_rstn_apb( &mut self, - ) -> RSTN_U0_PWMDAC_RSTN_APB_W { - RSTN_U0_PWMDAC_RSTN_APB_W::new(self) + ) -> RSTN_U0_PWMDAC_RSTN_APB_W { + RSTN_U0_PWMDAC_RSTN_APB_W::new(self, 0) } #[doc = "Bit 1 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_pdm_4mic_rstn_dmic( &mut self, - ) -> RSTN_U0_PDM_4MIC_RSTN_DMIC_W { - RSTN_U0_PDM_4MIC_RSTN_DMIC_W::new(self) + ) -> RSTN_U0_PDM_4MIC_RSTN_DMIC_W { + RSTN_U0_PDM_4MIC_RSTN_DMIC_W::new(self, 1) } #[doc = "Bit 2 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_pdm_4mic_rstn_apb( &mut self, - ) -> RSTN_U0_PDM_4MIC_RSTN_APB_W { - RSTN_U0_PDM_4MIC_RSTN_APB_W::new(self) + ) -> RSTN_U0_PDM_4MIC_RSTN_APB_W { + RSTN_U0_PDM_4MIC_RSTN_APB_W::new(self, 2) } #[doc = "Bit 3 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_i2srx_3ch_rstn_apb( &mut self, - ) -> RSTN_U0_I2SRX_3CH_RSTN_APB_W { - RSTN_U0_I2SRX_3CH_RSTN_APB_W::new(self) + ) -> RSTN_U0_I2SRX_3CH_RSTN_APB_W { + RSTN_U0_I2SRX_3CH_RSTN_APB_W::new(self, 3) } #[doc = "Bit 4 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_i2srx_3ch_rstn_bclk( &mut self, - ) -> RSTN_U0_I2SRX_3CH_RSTN_BCLK_W { - RSTN_U0_I2SRX_3CH_RSTN_BCLK_W::new(self) + ) -> RSTN_U0_I2SRX_3CH_RSTN_BCLK_W { + RSTN_U0_I2SRX_3CH_RSTN_BCLK_W::new(self, 4) } #[doc = "Bit 5 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_i2stx_4ch_rstn_apb( &mut self, - ) -> RSTN_U0_I2STX_4CH_RSTN_APB_W { - RSTN_U0_I2STX_4CH_RSTN_APB_W::new(self) + ) -> RSTN_U0_I2STX_4CH_RSTN_APB_W { + RSTN_U0_I2STX_4CH_RSTN_APB_W::new(self, 5) } #[doc = "Bit 6 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_i2stx_4ch_rstn_bclk( &mut self, - ) -> RSTN_U0_I2STX_4CH_RSTN_BCLK_W { - RSTN_U0_I2STX_4CH_RSTN_BCLK_W::new(self) + ) -> RSTN_U0_I2STX_4CH_RSTN_BCLK_W { + RSTN_U0_I2STX_4CH_RSTN_BCLK_W::new(self, 6) } #[doc = "Bit 7 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_i2stx_4ch_rstn_apb( &mut self, - ) -> RSTN_U1_I2STX_4CH_RSTN_APB_W { - RSTN_U1_I2STX_4CH_RSTN_APB_W::new(self) + ) -> RSTN_U1_I2STX_4CH_RSTN_APB_W { + RSTN_U1_I2STX_4CH_RSTN_APB_W::new(self, 7) } #[doc = "Bit 8 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_i2stx_4ch_rstn_bclk( &mut self, - ) -> RSTN_U1_I2STX_4CH_RSTN_BCLK_W { - RSTN_U1_I2STX_4CH_RSTN_BCLK_W::new(self) + ) -> RSTN_U1_I2STX_4CH_RSTN_BCLK_W { + RSTN_U1_I2STX_4CH_RSTN_BCLK_W::new(self, 8) } #[doc = "Bit 9 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_tdm16slot_rstn_ahb( &mut self, - ) -> RSTN_U0_TDM16SLOT_RSTN_AHB_W { - RSTN_U0_TDM16SLOT_RSTN_AHB_W::new(self) + ) -> RSTN_U0_TDM16SLOT_RSTN_AHB_W { + RSTN_U0_TDM16SLOT_RSTN_AHB_W::new(self, 9) } #[doc = "Bit 10 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_tdm16slot_rstn_tdm( &mut self, - ) -> RSTN_U0_TDM16SLOT_RSTN_TDM_W { - RSTN_U0_TDM16SLOT_RSTN_TDM_W::new(self) + ) -> RSTN_U0_TDM16SLOT_RSTN_TDM_W { + RSTN_U0_TDM16SLOT_RSTN_TDM_W::new(self, 10) } #[doc = "Bit 11 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_tdm16slot_rstn_apb( &mut self, - ) -> RSTN_U0_TDM16SLOT_RSTN_APB_W { - RSTN_U0_TDM16SLOT_RSTN_APB_W::new(self) + ) -> RSTN_U0_TDM16SLOT_RSTN_APB_W { + RSTN_U0_TDM16SLOT_RSTN_APB_W::new(self, 11) } #[doc = "Bit 12 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_pwm_8ch_rstn_apb( &mut self, - ) -> RSTN_U0_PWM_8CH_RSTN_APB_W { - RSTN_U0_PWM_8CH_RSTN_APB_W::new(self) + ) -> RSTN_U0_PWM_8CH_RSTN_APB_W { + RSTN_U0_PWM_8CH_RSTN_APB_W::new(self, 12) } #[doc = "Bit 13 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dskit_wdt_rstn_apb( &mut self, - ) -> RSTN_U0_DSKIT_WDT_RSTN_APB_W { - RSTN_U0_DSKIT_WDT_RSTN_APB_W::new(self) + ) -> RSTN_U0_DSKIT_WDT_RSTN_APB_W { + RSTN_U0_DSKIT_WDT_RSTN_APB_W::new(self, 13) } #[doc = "Bit 14 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_dskit_wdt_rstn_wdt( &mut self, - ) -> RSTN_U0_DSKIT_WDT_RSTN_WDT_W { - RSTN_U0_DSKIT_WDT_RSTN_WDT_W::new(self) + ) -> RSTN_U0_DSKIT_WDT_RSTN_WDT_W { + RSTN_U0_DSKIT_WDT_RSTN_WDT_W::new(self, 14) } #[doc = "Bit 15 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_can_ctrl_rstn_apb( &mut self, - ) -> RSTN_U0_CAN_CTRL_RSTN_APB_W { - RSTN_U0_CAN_CTRL_RSTN_APB_W::new(self) + ) -> RSTN_U0_CAN_CTRL_RSTN_APB_W { + RSTN_U0_CAN_CTRL_RSTN_APB_W::new(self, 15) } #[doc = "Bit 16 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_can_ctrl_rstn_can( &mut self, - ) -> RSTN_U0_CAN_CTRL_RSTN_CAN_W { - RSTN_U0_CAN_CTRL_RSTN_CAN_W::new(self) + ) -> RSTN_U0_CAN_CTRL_RSTN_CAN_W { + RSTN_U0_CAN_CTRL_RSTN_CAN_W::new(self, 16) } #[doc = "Bit 17 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_can_ctrl_rstn_timer( &mut self, - ) -> RSTN_U0_CAN_CTRL_RSTN_TIMER_W { - RSTN_U0_CAN_CTRL_RSTN_TIMER_W::new(self) + ) -> RSTN_U0_CAN_CTRL_RSTN_TIMER_W { + RSTN_U0_CAN_CTRL_RSTN_TIMER_W::new(self, 17) } #[doc = "Bit 18 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_can_ctrl_rstn_apb( &mut self, - ) -> RSTN_U1_CAN_CTRL_RSTN_APB_W { - RSTN_U1_CAN_CTRL_RSTN_APB_W::new(self) + ) -> RSTN_U1_CAN_CTRL_RSTN_APB_W { + RSTN_U1_CAN_CTRL_RSTN_APB_W::new(self, 18) } #[doc = "Bit 19 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_can_ctrl_rstn_can( &mut self, - ) -> RSTN_U1_CAN_CTRL_RSTN_CAN_W { - RSTN_U1_CAN_CTRL_RSTN_CAN_W::new(self) + ) -> RSTN_U1_CAN_CTRL_RSTN_CAN_W { + RSTN_U1_CAN_CTRL_RSTN_CAN_W::new(self, 19) } #[doc = "Bit 20 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u1_can_ctrl_rstn_timer( &mut self, - ) -> RSTN_U1_CAN_CTRL_RSTN_TIMER_W { - RSTN_U1_CAN_CTRL_RSTN_TIMER_W::new(self) + ) -> RSTN_U1_CAN_CTRL_RSTN_TIMER_W { + RSTN_U1_CAN_CTRL_RSTN_TIMER_W::new(self, 20) } #[doc = "Bit 21 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_apb( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_APB_W { - RSTN_U0_SI5_TIMER_RSTN_APB_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_APB_W { + RSTN_U0_SI5_TIMER_RSTN_APB_W::new(self, 21) } #[doc = "Bit 22 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_timer0( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER0_W { - RSTN_U0_SI5_TIMER_RSTN_TIMER0_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER0_W { + RSTN_U0_SI5_TIMER_RSTN_TIMER0_W::new(self, 22) } #[doc = "Bit 23 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_time10( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_TIME10_W { - RSTN_U0_SI5_TIMER_RSTN_TIME10_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_TIME10_W { + RSTN_U0_SI5_TIMER_RSTN_TIME10_W::new(self, 23) } #[doc = "Bit 24 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_timer2( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER2_W { - RSTN_U0_SI5_TIMER_RSTN_TIMER2_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER2_W { + RSTN_U0_SI5_TIMER_RSTN_TIMER2_W::new(self, 24) } #[doc = "Bit 25 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_si5_timer_rstn_timer3( &mut self, - ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER3_W { - RSTN_U0_SI5_TIMER_RSTN_TIMER3_W::new(self) + ) -> RSTN_U0_SI5_TIMER_RSTN_TIMER3_W { + RSTN_U0_SI5_TIMER_RSTN_TIMER3_W::new(self, 25) } #[doc = "Bit 26 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_int_ctrl_rstn_apb( &mut self, - ) -> RSTN_U0_INT_CTRL_RSTN_APB_W { - RSTN_U0_INT_CTRL_RSTN_APB_W::new(self) + ) -> RSTN_U0_INT_CTRL_RSTN_APB_W { + RSTN_U0_INT_CTRL_RSTN_APB_W::new(self, 26) } #[doc = "Bit 27 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_temp_sensor_rstn_apb( &mut self, - ) -> RSTN_U0_TEMP_SENSOR_RSTN_APB_W { - RSTN_U0_TEMP_SENSOR_RSTN_APB_W::new(self) + ) -> RSTN_U0_TEMP_SENSOR_RSTN_APB_W { + RSTN_U0_TEMP_SENSOR_RSTN_APB_W::new(self, 27) } #[doc = "Bit 28 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_temp_sensor_rstn_temp( &mut self, - ) -> RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W { - RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W::new(self) + ) -> RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W { + RSTN_U0_TEMP_SENSOR_RSTN_TEMP_W::new(self, 28) } #[doc = "Bit 29 - 1: Assert reset, 0: De-assert reset"] #[inline(always)] #[must_use] pub fn rstn_u0_jtag_certification_rst_n( &mut self, - ) -> RSTN_U0_JTAG_CERTIFICATION_RST_N_W { - RSTN_U0_JTAG_CERTIFICATION_RST_N_W::new(self) - } - #[doc = "Writes raw bits to the register."] + ) -> RSTN_U0_JTAG_CERTIFICATION_RST_N_W { + RSTN_U0_JTAG_CERTIFICATION_RST_N_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/syscrg/u7mc_rtc_toggle.rs b/jh7110-vf2-13b-pac/src/syscrg/u7mc_rtc_toggle.rs index 71fbc84..d031079 100644 --- a/jh7110-vf2-13b-pac/src/syscrg/u7mc_rtc_toggle.rs +++ b/jh7110-vf2-13b-pac/src/syscrg/u7mc_rtc_toggle.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=6, Default=6, Min=6, Typical=6"] pub type CLK_DIVCFG_R = crate::FieldReader; #[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=6, Default=6, Min=6, Typical=6"] -pub type CLK_DIVCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; +pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { #[doc = "Bits 0:23 - Clock divider coefficient: Max=6, Default=6, Min=6, Typical=6"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:23 - Clock divider coefficient: Max=6, Default=6, Min=6, Typical=6"] #[inline(always)] #[must_use] - pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { - CLK_DIVCFG_W::new(self) + pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W { + CLK_DIVCFG_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/trng.rs b/jh7110-vf2-13b-pac/src/trng.rs index c4fa9aa..3f9616e 100644 --- a/jh7110-vf2-13b-pac/src/trng.rs +++ b/jh7110-vf2-13b-pac/src/trng.rs @@ -1,117 +1,183 @@ #[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { + ctrl: CTRL, + stat: STAT, + mode: MODE, + smode: SMODE, + ie: IE, + istat: ISTAT, + _reserved6: [u8; 0x08], + rand0: RAND0, + rand1: RAND1, + rand2: RAND2, + rand3: RAND3, + rand4: RAND4, + rand5: RAND5, + rand6: RAND6, + rand7: RAND7, + _reserved14: [u8; 0x20], + auto_rqsts: AUTO_RQSTS, + auto_age: AUTO_AGE, +} +impl RegisterBlock { #[doc = "0x00 - TRNG CTRL Register"] - pub ctrl: CTRL, + #[inline(always)] + pub const fn ctrl(&self) -> &CTRL { + &self.ctrl + } #[doc = "0x04 - TRNG STAT Register"] - pub stat: STAT, + #[inline(always)] + pub const fn stat(&self) -> &STAT { + &self.stat + } #[doc = "0x08 - TRNG MODE Register"] - pub mode: MODE, + #[inline(always)] + pub const fn mode(&self) -> &MODE { + &self.mode + } #[doc = "0x0c - TRNG SMODE Register"] - pub smode: SMODE, + #[inline(always)] + pub const fn smode(&self) -> &SMODE { + &self.smode + } #[doc = "0x10 - TRNG Interrupt Enable Register"] - pub ie: IE, + #[inline(always)] + pub const fn ie(&self) -> &IE { + &self.ie + } #[doc = "0x14 - TRNG Interrupt Status Register"] - pub istat: ISTAT, - _reserved6: [u8; 0x08], + #[inline(always)] + pub const fn istat(&self) -> &ISTAT { + &self.istat + } #[doc = "0x20 - TRNG RAND 0 Status Register"] - pub rand0: RAND0, + #[inline(always)] + pub const fn rand0(&self) -> &RAND0 { + &self.rand0 + } #[doc = "0x24 - TRNG RAND 1 Status Register"] - pub rand1: RAND1, + #[inline(always)] + pub const fn rand1(&self) -> &RAND1 { + &self.rand1 + } #[doc = "0x28 - TRNG RAND 2 Status Register"] - pub rand2: RAND2, + #[inline(always)] + pub const fn rand2(&self) -> &RAND2 { + &self.rand2 + } #[doc = "0x2c - TRNG RAND 3 Status Register"] - pub rand3: RAND3, + #[inline(always)] + pub const fn rand3(&self) -> &RAND3 { + &self.rand3 + } #[doc = "0x30 - TRNG RAND 4 Status Register"] - pub rand4: RAND4, + #[inline(always)] + pub const fn rand4(&self) -> &RAND4 { + &self.rand4 + } #[doc = "0x34 - TRNG RAND 5 Status Register"] - pub rand5: RAND5, + #[inline(always)] + pub const fn rand5(&self) -> &RAND5 { + &self.rand5 + } #[doc = "0x38 - TRNG RAND 6 Status Register"] - pub rand6: RAND6, + #[inline(always)] + pub const fn rand6(&self) -> &RAND6 { + &self.rand6 + } #[doc = "0x3c - TRNG RAND 7 Status Register"] - pub rand7: RAND7, - _reserved14: [u8; 0x20], + #[inline(always)] + pub const fn rand7(&self) -> &RAND7 { + &self.rand7 + } #[doc = "0x60 - Auto-reseeding after random number requests by host reaches specified counter: 0 - disable counter, other - reload value for internal counter"] - pub auto_rqsts: AUTO_RQSTS, + #[inline(always)] + pub const fn auto_rqsts(&self) -> &AUTO_RQSTS { + &self.auto_rqsts + } #[doc = "0x64 - Auto-reseeding after specified timer countdowns to 0: 0 - disable timer, other - reload value for internal timer"] - pub auto_age: AUTO_AGE, + #[inline(always)] + pub const fn auto_age(&self) -> &AUTO_AGE { + &self.auto_age + } } -#[doc = "ctrl (rw) register accessor: TRNG CTRL Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctrl`] +#[doc = "ctrl (rw) register accessor: TRNG CTRL Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] pub type CTRL = crate::Reg; #[doc = "TRNG CTRL Register"] pub mod ctrl; -#[doc = "stat (rw) register accessor: TRNG STAT Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stat`] +#[doc = "stat (rw) register accessor: TRNG STAT Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] module"] pub type STAT = crate::Reg; #[doc = "TRNG STAT Register"] pub mod stat; -#[doc = "mode (rw) register accessor: TRNG MODE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mode`] +#[doc = "mode (rw) register accessor: TRNG MODE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode`] module"] pub type MODE = crate::Reg; #[doc = "TRNG MODE Register"] pub mod mode; -#[doc = "smode (rw) register accessor: TRNG SMODE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smode::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`smode`] +#[doc = "smode (rw) register accessor: TRNG SMODE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smode::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smode`] module"] pub type SMODE = crate::Reg; #[doc = "TRNG SMODE Register"] pub mod smode; -#[doc = "ie (rw) register accessor: TRNG Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ie::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ie::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ie`] +#[doc = "ie (rw) register accessor: TRNG Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ie::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ie::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ie`] module"] pub type IE = crate::Reg; #[doc = "TRNG Interrupt Enable Register"] pub mod ie; -#[doc = "istat (rw) register accessor: TRNG Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`istat::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`istat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`istat`] +#[doc = "istat (rw) register accessor: TRNG Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`istat::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`istat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@istat`] module"] pub type ISTAT = crate::Reg; #[doc = "TRNG Interrupt Status Register"] pub mod istat; -#[doc = "rand0 (rw) register accessor: TRNG RAND 0 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand0`] +#[doc = "rand0 (rw) register accessor: TRNG RAND 0 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rand0`] module"] pub type RAND0 = crate::Reg; #[doc = "TRNG RAND 0 Status Register"] pub mod rand0; -#[doc = "rand1 (rw) register accessor: TRNG RAND 1 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand1`] +#[doc = "rand1 (rw) register accessor: TRNG RAND 1 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rand1`] module"] pub type RAND1 = crate::Reg; #[doc = "TRNG RAND 1 Status Register"] pub mod rand1; -#[doc = "rand2 (rw) register accessor: TRNG RAND 2 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand2`] +#[doc = "rand2 (rw) register accessor: TRNG RAND 2 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rand2`] module"] pub type RAND2 = crate::Reg; #[doc = "TRNG RAND 2 Status Register"] pub mod rand2; -#[doc = "rand3 (rw) register accessor: TRNG RAND 3 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand3`] +#[doc = "rand3 (rw) register accessor: TRNG RAND 3 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rand3`] module"] pub type RAND3 = crate::Reg; #[doc = "TRNG RAND 3 Status Register"] pub mod rand3; -#[doc = "rand4 (rw) register accessor: TRNG RAND 4 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand4`] +#[doc = "rand4 (rw) register accessor: TRNG RAND 4 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rand4`] module"] pub type RAND4 = crate::Reg; #[doc = "TRNG RAND 4 Status Register"] pub mod rand4; -#[doc = "rand5 (rw) register accessor: TRNG RAND 5 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand5`] +#[doc = "rand5 (rw) register accessor: TRNG RAND 5 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rand5`] module"] pub type RAND5 = crate::Reg; #[doc = "TRNG RAND 5 Status Register"] pub mod rand5; -#[doc = "rand6 (rw) register accessor: TRNG RAND 6 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand6::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand6`] +#[doc = "rand6 (rw) register accessor: TRNG RAND 6 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand6::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rand6`] module"] pub type RAND6 = crate::Reg; #[doc = "TRNG RAND 6 Status Register"] pub mod rand6; -#[doc = "rand7 (rw) register accessor: TRNG RAND 7 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand7::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rand7`] +#[doc = "rand7 (rw) register accessor: TRNG RAND 7 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rand7::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rand7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rand7`] module"] pub type RAND7 = crate::Reg; #[doc = "TRNG RAND 7 Status Register"] pub mod rand7; -#[doc = "auto_rqsts (rw) register accessor: Auto-reseeding after random number requests by host reaches specified counter: 0 - disable counter, other - reload value for internal counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`auto_rqsts::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`auto_rqsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`auto_rqsts`] +#[doc = "auto_rqsts (rw) register accessor: Auto-reseeding after random number requests by host reaches specified counter: 0 - disable counter, other - reload value for internal counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`auto_rqsts::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`auto_rqsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@auto_rqsts`] module"] pub type AUTO_RQSTS = crate::Reg; #[doc = "Auto-reseeding after random number requests by host reaches specified counter: 0 - disable counter, other - reload value for internal counter"] pub mod auto_rqsts; -#[doc = "auto_age (rw) register accessor: Auto-reseeding after specified timer countdowns to 0: 0 - disable timer, other - reload value for internal timer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`auto_age::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`auto_age::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`auto_age`] +#[doc = "auto_age (rw) register accessor: Auto-reseeding after specified timer countdowns to 0: 0 - disable timer, other - reload value for internal timer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`auto_age::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`auto_age::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@auto_age`] module"] pub type AUTO_AGE = crate::Reg; #[doc = "Auto-reseeding after specified timer countdowns to 0: 0 - disable timer, other - reload value for internal timer"] diff --git a/jh7110-vf2-13b-pac/src/trng/auto_age.rs b/jh7110-vf2-13b-pac/src/trng/auto_age.rs index a711c39..3bd24b7 100644 --- a/jh7110-vf2-13b-pac/src/trng/auto_age.rs +++ b/jh7110-vf2-13b-pac/src/trng/auto_age.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `age` reader - Countdown value for auto-reseed timer"] pub type AGE_R = crate::FieldReader; #[doc = "Field `age` writer - Countdown value for auto-reseed timer"] -pub type AGE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type AGE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - Countdown value for auto-reseed timer"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - Countdown value for auto-reseed timer"] #[inline(always)] #[must_use] - pub fn age(&mut self) -> AGE_W { - AGE_W::new(self) + pub fn age(&mut self) -> AGE_W { + AGE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/trng/auto_rqsts.rs b/jh7110-vf2-13b-pac/src/trng/auto_rqsts.rs index d6bb092..eae5c89 100644 --- a/jh7110-vf2-13b-pac/src/trng/auto_rqsts.rs +++ b/jh7110-vf2-13b-pac/src/trng/auto_rqsts.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `rqsts` reader - Threshold number of reseed requests for auto-reseed counter"] pub type RQSTS_R = crate::FieldReader; #[doc = "Field `rqsts` writer - Threshold number of reseed requests for auto-reseed counter"] -pub type RQSTS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; +pub type RQSTS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { #[doc = "Bits 0:31 - Threshold number of reseed requests for auto-reseed counter"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:31 - Threshold number of reseed requests for auto-reseed counter"] #[inline(always)] #[must_use] - pub fn rqsts(&mut self) -> RQSTS_W { - RQSTS_W::new(self) + pub fn rqsts(&mut self) -> RQSTS_W { + RQSTS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/trng/ctrl.rs b/jh7110-vf2-13b-pac/src/trng/ctrl.rs index 17511a1..62dea09 100644 --- a/jh7110-vf2-13b-pac/src/trng/ctrl.rs +++ b/jh7110-vf2-13b-pac/src/trng/ctrl.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `exec_nop` reader - Execute a NOP instruction"] pub type EXEC_NOP_R = crate::BitReader; #[doc = "Field `exec_nop` writer - Execute a NOP instruction"] -pub type EXEC_NOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EXEC_NOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `gene_randnum` reader - Generate a random number"] pub type GENE_RANDNUM_R = crate::BitReader; #[doc = "Field `gene_randnum` writer - Generate a random number"] -pub type GENE_RANDNUM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GENE_RANDNUM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `exec_randreseed` reader - Reseed the TRNG from noise sources"] pub type EXEC_RANDRESEED_R = crate::BitReader; #[doc = "Field `exec_randreseed` writer - Reseed the TRNG from noise sources"] -pub type EXEC_RANDRESEED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EXEC_RANDRESEED_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Execute a NOP instruction"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bit 0 - Execute a NOP instruction"] #[inline(always)] #[must_use] - pub fn exec_nop(&mut self) -> EXEC_NOP_W { - EXEC_NOP_W::new(self) + pub fn exec_nop(&mut self) -> EXEC_NOP_W { + EXEC_NOP_W::new(self, 0) } #[doc = "Bit 1 - Generate a random number"] #[inline(always)] #[must_use] - pub fn gene_randnum(&mut self) -> GENE_RANDNUM_W { - GENE_RANDNUM_W::new(self) + pub fn gene_randnum(&mut self) -> GENE_RANDNUM_W { + GENE_RANDNUM_W::new(self, 1) } #[doc = "Bit 2 - Reseed the TRNG from noise sources"] #[inline(always)] #[must_use] - pub fn exec_randreseed(&mut self) -> EXEC_RANDRESEED_W { - EXEC_RANDRESEED_W::new(self) + pub fn exec_randreseed(&mut self) -> EXEC_RANDRESEED_W { + EXEC_RANDRESEED_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/trng/ie.rs b/jh7110-vf2-13b-pac/src/trng/ie.rs index dee70fe..8fdd65b 100644 --- a/jh7110-vf2-13b-pac/src/trng/ie.rs +++ b/jh7110-vf2-13b-pac/src/trng/ie.rs @@ -5,19 +5,19 @@ pub type W = crate::W; #[doc = "Field `rand_rdy_en` reader - RAND Ready Enable"] pub type RAND_RDY_EN_R = crate::BitReader; #[doc = "Field `rand_rdy_en` writer - RAND Ready Enable"] -pub type RAND_RDY_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RAND_RDY_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `seed_done_en` reader - Seed Done Enable"] pub type SEED_DONE_EN_R = crate::BitReader; #[doc = "Field `seed_done_en` writer - Seed Done Enable"] -pub type SEED_DONE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SEED_DONE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `lfsr_lockup_en` reader - LFSR Lockup Enable"] pub type LFSR_LOCKUP_EN_R = crate::BitReader; #[doc = "Field `lfsr_lockup_en` writer - LFSR Lockup Enable"] -pub type LFSR_LOCKUP_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LFSR_LOCKUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `glbl_en` reader - Global Enable"] pub type GLBL_EN_R = crate::BitReader; #[doc = "Field `glbl_en` writer - Global Enable"] -pub type GLBL_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type GLBL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - RAND Ready Enable"] #[inline(always)] @@ -44,28 +44,32 @@ impl W { #[doc = "Bit 0 - RAND Ready Enable"] #[inline(always)] #[must_use] - pub fn rand_rdy_en(&mut self) -> RAND_RDY_EN_W { - RAND_RDY_EN_W::new(self) + pub fn rand_rdy_en(&mut self) -> RAND_RDY_EN_W { + RAND_RDY_EN_W::new(self, 0) } #[doc = "Bit 1 - Seed Done Enable"] #[inline(always)] #[must_use] - pub fn seed_done_en(&mut self) -> SEED_DONE_EN_W { - SEED_DONE_EN_W::new(self) + pub fn seed_done_en(&mut self) -> SEED_DONE_EN_W { + SEED_DONE_EN_W::new(self, 1) } #[doc = "Bit 4 - LFSR Lockup Enable"] #[inline(always)] #[must_use] - pub fn lfsr_lockup_en(&mut self) -> LFSR_LOCKUP_EN_W { - LFSR_LOCKUP_EN_W::new(self) + pub fn lfsr_lockup_en(&mut self) -> LFSR_LOCKUP_EN_W { + LFSR_LOCKUP_EN_W::new(self, 4) } #[doc = "Bit 31 - Global Enable"] #[inline(always)] #[must_use] - pub fn glbl_en(&mut self) -> GLBL_EN_W { - GLBL_EN_W::new(self) + pub fn glbl_en(&mut self) -> GLBL_EN_W { + GLBL_EN_W::new(self, 31) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/trng/istat.rs b/jh7110-vf2-13b-pac/src/trng/istat.rs index d17bc57..a3c0bc6 100644 --- a/jh7110-vf2-13b-pac/src/trng/istat.rs +++ b/jh7110-vf2-13b-pac/src/trng/istat.rs @@ -26,7 +26,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/trng/mode.rs b/jh7110-vf2-13b-pac/src/trng/mode.rs index 0483fcb..2178579 100644 --- a/jh7110-vf2-13b-pac/src/trng/mode.rs +++ b/jh7110-vf2-13b-pac/src/trng/mode.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `r256` reader - 256-bit operation mode: 0 - 128-bit mode, 1 - 256-bit mode"] pub type R256_R = crate::BitReader; #[doc = "Field `r256` writer - 256-bit operation mode: 0 - 128-bit mode, 1 - 256-bit mode"] -pub type R256_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type R256_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 3 - 256-bit operation mode: 0 - 128-bit mode, 1 - 256-bit mode"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 3 - 256-bit operation mode: 0 - 128-bit mode, 1 - 256-bit mode"] #[inline(always)] #[must_use] - pub fn r256(&mut self) -> R256_W { - R256_W::new(self) + pub fn r256(&mut self) -> R256_W { + R256_W::new(self, 3) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/trng/rand0.rs b/jh7110-vf2-13b-pac/src/trng/rand0.rs index 8d640b8..a99f590 100644 --- a/jh7110-vf2-13b-pac/src/trng/rand0.rs +++ b/jh7110-vf2-13b-pac/src/trng/rand0.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/trng/rand1.rs b/jh7110-vf2-13b-pac/src/trng/rand1.rs index 02759fc..8779d7f 100644 --- a/jh7110-vf2-13b-pac/src/trng/rand1.rs +++ b/jh7110-vf2-13b-pac/src/trng/rand1.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/trng/rand2.rs b/jh7110-vf2-13b-pac/src/trng/rand2.rs index 9c12892..98e7722 100644 --- a/jh7110-vf2-13b-pac/src/trng/rand2.rs +++ b/jh7110-vf2-13b-pac/src/trng/rand2.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/trng/rand3.rs b/jh7110-vf2-13b-pac/src/trng/rand3.rs index 3cf673c..aa3cd17 100644 --- a/jh7110-vf2-13b-pac/src/trng/rand3.rs +++ b/jh7110-vf2-13b-pac/src/trng/rand3.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/trng/rand4.rs b/jh7110-vf2-13b-pac/src/trng/rand4.rs index 053c800..594d125 100644 --- a/jh7110-vf2-13b-pac/src/trng/rand4.rs +++ b/jh7110-vf2-13b-pac/src/trng/rand4.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/trng/rand5.rs b/jh7110-vf2-13b-pac/src/trng/rand5.rs index 2c3614a..2a30aee 100644 --- a/jh7110-vf2-13b-pac/src/trng/rand5.rs +++ b/jh7110-vf2-13b-pac/src/trng/rand5.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/trng/rand6.rs b/jh7110-vf2-13b-pac/src/trng/rand6.rs index 62ff145..a852096 100644 --- a/jh7110-vf2-13b-pac/src/trng/rand6.rs +++ b/jh7110-vf2-13b-pac/src/trng/rand6.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/trng/rand7.rs b/jh7110-vf2-13b-pac/src/trng/rand7.rs index ae12b01..2a3f62d 100644 --- a/jh7110-vf2-13b-pac/src/trng/rand7.rs +++ b/jh7110-vf2-13b-pac/src/trng/rand7.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/trng/smode.rs b/jh7110-vf2-13b-pac/src/trng/smode.rs index 23f0a12..35d99e4 100644 --- a/jh7110-vf2-13b-pac/src/trng/smode.rs +++ b/jh7110-vf2-13b-pac/src/trng/smode.rs @@ -5,15 +5,15 @@ pub type W = crate::W; #[doc = "Field `nonce_mode` reader - Nonce operation mode"] pub type NONCE_MODE_R = crate::BitReader; #[doc = "Field `nonce_mode` writer - Nonce operation mode"] -pub type NONCE_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type NONCE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `mission_mode` reader - Mission operation mode"] pub type MISSION_MODE_R = crate::BitReader; #[doc = "Field `mission_mode` writer - Mission operation mode"] -pub type MISSION_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type MISSION_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `max_rejects` reader - TRNG Maximum Rejects"] pub type MAX_REJECTS_R = crate::FieldReader; #[doc = "Field `max_rejects` writer - TRNG Maximum Rejects"] -pub type MAX_REJECTS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; +pub type MAX_REJECTS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bit 2 - Nonce operation mode"] #[inline(always)] @@ -35,22 +35,26 @@ impl W { #[doc = "Bit 2 - Nonce operation mode"] #[inline(always)] #[must_use] - pub fn nonce_mode(&mut self) -> NONCE_MODE_W { - NONCE_MODE_W::new(self) + pub fn nonce_mode(&mut self) -> NONCE_MODE_W { + NONCE_MODE_W::new(self, 2) } #[doc = "Bit 8 - Mission operation mode"] #[inline(always)] #[must_use] - pub fn mission_mode(&mut self) -> MISSION_MODE_W { - MISSION_MODE_W::new(self) + pub fn mission_mode(&mut self) -> MISSION_MODE_W { + MISSION_MODE_W::new(self, 8) } #[doc = "Bits 16:31 - TRNG Maximum Rejects"] #[inline(always)] #[must_use] - pub fn max_rejects(&mut self) -> MAX_REJECTS_W { - MAX_REJECTS_W::new(self) + pub fn max_rejects(&mut self) -> MAX_REJECTS_W { + MAX_REJECTS_W::new(self, 16) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/trng/stat.rs b/jh7110-vf2-13b-pac/src/trng/stat.rs index afc22a4..73ae28b 100644 --- a/jh7110-vf2-13b-pac/src/trng/stat.rs +++ b/jh7110-vf2-13b-pac/src/trng/stat.rs @@ -110,7 +110,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0.rs b/jh7110-vf2-13b-pac/src/uart0.rs index c462fbf..8a5f089 100644 --- a/jh7110-vf2-13b-pac/src/uart0.rs +++ b/jh7110-vf2-13b-pac/src/uart0.rs @@ -4,20 +4,13 @@ pub struct RegisterBlock { _reserved_0_dll: [u8; 0x04], _reserved_1_dlh: [u8; 0x04], _reserved_2_fcr: [u8; 0x04], - #[doc = "0x0c - Line Control Register"] - pub lcr: LCR, - #[doc = "0x10 - Modem Control Register"] - pub mcr: MCR, - #[doc = "0x14 - Line Status Register"] - pub lsr: LSR, - #[doc = "0x18 - Line Status Register"] - pub msr: MSR, - #[doc = "0x1c - Scratch Pad Register"] - pub scr: SCR, - #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdll: LPDLL, - #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdlh: LPDLH, + lcr: LCR, + mcr: MCR, + lsr: LSR, + msr: MSR, + scr: SCR, + lpdll: LPDLL, + lpdlh: LPDLH, _reserved10: [u8; 0x08], _reserved_10_srbr0: [u8; 0x04], _reserved_11_srbr1: [u8; 0x04], @@ -35,564 +28,663 @@ pub struct RegisterBlock { _reserved_23_srbr13: [u8; 0x04], _reserved_24_srbr14: [u8; 0x04], _reserved_25_srbr15: [u8; 0x04], - #[doc = "0x70 - FIFO Access Register"] - pub far: FAR, - #[doc = "0x74 - Transmit FIFO Read"] - pub tfr: TFR, - #[doc = "0x78 - Receive FIFO Write"] - pub rfw: RFW, - #[doc = "0x7c - UART Status Register"] - pub usr: USR, - #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub tfl: TFL, - #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub rfl: RFL, - #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srr: SRR, - #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srts: SRTS, - #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sbcr: SBCR, - #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sdmam: SDMAM, - #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sfe: SFE, - #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srt: SRT, - #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub stet: STET, - #[doc = "0xa4 - Halt TX"] - pub htx: HTX, - #[doc = "0xa8 - DMA Software Acknowledge"] - pub dmasa: DMASA, + far: FAR, + tfr: TFR, + rfw: RFW, + usr: USR, + tfl: TFL, + rfl: RFL, + srr: SRR, + srts: SRTS, + sbcr: SBCR, + sdmam: SDMAM, + sfe: SFE, + srt: SRT, + stet: STET, + htx: HTX, + dmasa: DMASA, _reserved41: [u8; 0x48], - #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] - pub cpr: CPR, + cpr: CPR, _reserved_42_ctr: [u8; 0x04], } impl RegisterBlock { #[doc = "0x00 - Divisor Latch Low"] #[inline(always)] pub const fn dll(&self) -> &DLL { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Transmit Holding Register"] #[inline(always)] pub const fn thr(&self) -> &THR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Receive Buffer Register"] #[inline(always)] pub const fn rbr(&self) -> &RBR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x04 - Interrupt Enable Register"] #[inline(always)] pub const fn ier(&self) -> &IER { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x04 - Divisor Latch High"] #[inline(always)] pub const fn dlh(&self) -> &DLH { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x08 - FIFO Control Register"] #[inline(always)] pub const fn fcr(&self) -> &FCR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } } #[doc = "0x08 - Interrupt Identity Register"] #[inline(always)] pub const fn iir(&self) -> &IIR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } + } + #[doc = "0x0c - Line Control Register"] + #[inline(always)] + pub const fn lcr(&self) -> &LCR { + &self.lcr + } + #[doc = "0x10 - Modem Control Register"] + #[inline(always)] + pub const fn mcr(&self) -> &MCR { + &self.mcr + } + #[doc = "0x14 - Line Status Register"] + #[inline(always)] + pub const fn lsr(&self) -> &LSR { + &self.lsr + } + #[doc = "0x18 - Line Status Register"] + #[inline(always)] + pub const fn msr(&self) -> &MSR { + &self.msr + } + #[doc = "0x1c - Scratch Pad Register"] + #[inline(always)] + pub const fn scr(&self) -> &SCR { + &self.scr + } + #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdll(&self) -> &LPDLL { + &self.lpdll + } + #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdlh(&self) -> &LPDLH { + &self.lpdlh } #[doc = "0x30 - Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr0(&self) -> &STHR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x30 - Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr0(&self) -> &SRBR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x34 - Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr1(&self) -> &STHR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x34 - Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr1(&self) -> &SRBR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x38 - Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr2(&self) -> &STHR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x38 - Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr2(&self) -> &SRBR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x3c - Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr3(&self) -> &STHR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x3c - Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr3(&self) -> &SRBR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x40 - Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr4(&self) -> &STHR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x40 - Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr4(&self) -> &SRBR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x44 - Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr5(&self) -> &STHR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x44 - Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr5(&self) -> &SRBR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x48 - Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr6(&self) -> &STHR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x48 - Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr6(&self) -> &SRBR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x4c - Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr7(&self) -> &STHR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x4c - Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr7(&self) -> &SRBR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x50 - Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr8(&self) -> &STHR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x50 - Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr8(&self) -> &SRBR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x54 - Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr9(&self) -> &STHR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x54 - Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr9(&self) -> &SRBR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x58 - Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr10(&self) -> &STHR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x58 - Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr10(&self) -> &SRBR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x5c - Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr11(&self) -> &STHR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x5c - Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr11(&self) -> &SRBR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x60 - Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr12(&self) -> &STHR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x60 - Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr12(&self) -> &SRBR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x64 - Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr13(&self) -> &STHR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x64 - Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr13(&self) -> &SRBR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x68 - Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr14(&self) -> &STHR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x68 - Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr14(&self) -> &SRBR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x6c - Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr15(&self) -> &STHR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } } #[doc = "0x6c - Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr15(&self) -> &SRBR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } + } + #[doc = "0x70 - FIFO Access Register"] + #[inline(always)] + pub const fn far(&self) -> &FAR { + &self.far + } + #[doc = "0x74 - Transmit FIFO Read"] + #[inline(always)] + pub const fn tfr(&self) -> &TFR { + &self.tfr + } + #[doc = "0x78 - Receive FIFO Write"] + #[inline(always)] + pub const fn rfw(&self) -> &RFW { + &self.rfw + } + #[doc = "0x7c - UART Status Register"] + #[inline(always)] + pub const fn usr(&self) -> &USR { + &self.usr + } + #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn tfl(&self) -> &TFL { + &self.tfl + } + #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn rfl(&self) -> &RFL { + &self.rfl + } + #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srr(&self) -> &SRR { + &self.srr + } + #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srts(&self) -> &SRTS { + &self.srts + } + #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sbcr(&self) -> &SBCR { + &self.sbcr + } + #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sdmam(&self) -> &SDMAM { + &self.sdmam + } + #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sfe(&self) -> &SFE { + &self.sfe + } + #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srt(&self) -> &SRT { + &self.srt + } + #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn stet(&self) -> &STET { + &self.stet + } + #[doc = "0xa4 - Halt TX"] + #[inline(always)] + pub const fn htx(&self) -> &HTX { + &self.htx + } + #[doc = "0xa8 - DMA Software Acknowledge"] + #[inline(always)] + pub const fn dmasa(&self) -> &DMASA { + &self.dmasa + } + #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn cpr(&self) -> &CPR { + &self.cpr } #[doc = "0xf8 - Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ctr(&self) -> &CTR { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } #[doc = "0xf8 - UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ucv(&self) -> &UCV { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } } -#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rbr`] +#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbr`] module"] pub type RBR = crate::Reg; #[doc = "Receive Buffer Register"] pub mod rbr; -#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`thr`] +#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thr`] module"] pub type THR = crate::Reg; #[doc = "Transmit Holding Register"] pub mod thr; -#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dll`] +#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll`] module"] pub type DLL = crate::Reg; #[doc = "Divisor Latch Low"] pub mod dll; -#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dlh`] +#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlh`] module"] pub type DLH = crate::Reg; #[doc = "Divisor Latch High"] pub mod dlh; -#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`iir`] +#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] module"] pub type IIR = crate::Reg; #[doc = "Interrupt Identity Register"] pub mod iir; -#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fcr`] +#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"] pub type FCR = crate::Reg; #[doc = "FIFO Control Register"] pub mod fcr; -#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lcr`] +#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] module"] pub type LCR = crate::Reg; #[doc = "Line Control Register"] pub mod lcr; -#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mcr`] +#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] pub type MCR = crate::Reg; #[doc = "Modem Control Register"] pub mod mcr; -#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lsr`] +#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] module"] pub type LSR = crate::Reg; #[doc = "Line Status Register"] pub mod lsr; -#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msr`] +#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"] pub type MSR = crate::Reg; #[doc = "Line Status Register"] pub mod msr; -#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scr`] +#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`] module"] pub type SCR = crate::Reg; #[doc = "Scratch Pad Register"] pub mod scr; -#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdll`] +#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdll`] module"] pub type LPDLL = crate::Reg; #[doc = "Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdll; -#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdlh`] +#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdlh`] module"] pub type LPDLH = crate::Reg; #[doc = "Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdlh; -#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr0`] +#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr0`] module"] pub type SRBR0 = crate::Reg; #[doc = "Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr0; -#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr0`] +#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr0`] module"] pub type STHR0 = crate::Reg; #[doc = "Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr0; -#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr1`] +#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr1`] module"] pub type SRBR1 = crate::Reg; #[doc = "Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr1; -#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr1`] +#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr1`] module"] pub type STHR1 = crate::Reg; #[doc = "Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr1; -#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr2`] +#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr2`] module"] pub type SRBR2 = crate::Reg; #[doc = "Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr2; -#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr2`] +#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr2`] module"] pub type STHR2 = crate::Reg; #[doc = "Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr2; -#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr3`] +#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr3`] module"] pub type SRBR3 = crate::Reg; #[doc = "Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr3; -#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr3`] +#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr3`] module"] pub type STHR3 = crate::Reg; #[doc = "Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr3; -#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr4`] +#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr4`] module"] pub type SRBR4 = crate::Reg; #[doc = "Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr4; -#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr4`] +#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr4`] module"] pub type STHR4 = crate::Reg; #[doc = "Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr4; -#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr5`] +#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr5`] module"] pub type SRBR5 = crate::Reg; #[doc = "Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr5; -#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr5`] +#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr5`] module"] pub type STHR5 = crate::Reg; #[doc = "Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr5; -#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr6`] +#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr6`] module"] pub type SRBR6 = crate::Reg; #[doc = "Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr6; -#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr6`] +#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr6`] module"] pub type STHR6 = crate::Reg; #[doc = "Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr6; -#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr7`] +#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr7`] module"] pub type SRBR7 = crate::Reg; #[doc = "Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr7; -#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr7`] +#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr7`] module"] pub type STHR7 = crate::Reg; #[doc = "Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr7; -#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr8`] +#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr8`] module"] pub type SRBR8 = crate::Reg; #[doc = "Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr8; -#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr8`] +#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr8`] module"] pub type STHR8 = crate::Reg; #[doc = "Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr8; -#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr9`] +#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr9`] module"] pub type SRBR9 = crate::Reg; #[doc = "Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr9; -#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr9`] +#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr9`] module"] pub type STHR9 = crate::Reg; #[doc = "Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr9; -#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr10`] +#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr10`] module"] pub type SRBR10 = crate::Reg; #[doc = "Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr10; -#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr10`] +#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr10`] module"] pub type STHR10 = crate::Reg; #[doc = "Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr10; -#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr11`] +#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr11`] module"] pub type SRBR11 = crate::Reg; #[doc = "Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr11; -#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr11`] +#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr11`] module"] pub type STHR11 = crate::Reg; #[doc = "Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr11; -#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr12`] +#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr12`] module"] pub type SRBR12 = crate::Reg; #[doc = "Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr12; -#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr12`] +#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr12`] module"] pub type STHR12 = crate::Reg; #[doc = "Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr12; -#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr13`] +#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr13`] module"] pub type SRBR13 = crate::Reg; #[doc = "Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr13; -#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr13`] +#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr13`] module"] pub type STHR13 = crate::Reg; #[doc = "Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr13; -#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr14`] +#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr14`] module"] pub type SRBR14 = crate::Reg; #[doc = "Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr14; -#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr14`] +#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr14`] module"] pub type STHR14 = crate::Reg; #[doc = "Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr14; -#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr15`] +#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr15`] module"] pub type SRBR15 = crate::Reg; #[doc = "Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr15; -#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr15`] +#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr15`] module"] pub type STHR15 = crate::Reg; #[doc = "Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr15; -#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`far`] +#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@far`] module"] pub type FAR = crate::Reg; #[doc = "FIFO Access Register"] pub mod far; -#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfr`] +#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfr`] module"] pub type TFR = crate::Reg; #[doc = "Transmit FIFO Read"] pub mod tfr; -#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfw`] +#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfw`] module"] pub type RFW = crate::Reg; #[doc = "Receive FIFO Write"] pub mod rfw; -#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`usr`] +#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usr`] module"] pub type USR = crate::Reg; #[doc = "UART Status Register"] pub mod usr; -#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfl`] +#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfl`] module"] pub type TFL = crate::Reg; #[doc = "Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod tfl; -#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfl`] +#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfl`] module"] pub type RFL = crate::Reg; #[doc = "Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod rfl; -#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srr`] +#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srr`] module"] pub type SRR = crate::Reg; #[doc = "Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srr; -#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srts`] +#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srts`] module"] pub type SRTS = crate::Reg; #[doc = "Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srts; -#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sbcr`] +#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sbcr`] module"] pub type SBCR = crate::Reg; #[doc = "Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sbcr; -#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sdmam`] +#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdmam`] module"] pub type SDMAM = crate::Reg; #[doc = "Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sdmam; -#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sfe`] +#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfe`] module"] pub type SFE = crate::Reg; #[doc = "Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sfe; -#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srt`] +#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srt`] module"] pub type SRT = crate::Reg; #[doc = "Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srt; -#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stet`] +#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stet`] module"] pub type STET = crate::Reg; #[doc = "Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod stet; -#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`htx`] +#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@htx`] module"] pub type HTX = crate::Reg; #[doc = "Halt TX"] pub mod htx; -#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dmasa`] +#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasa`] module"] pub type DMASA = crate::Reg; #[doc = "DMA Software Acknowledge"] pub mod dmasa; -#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cpr`] +#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpr`] module"] pub type CPR = crate::Reg; #[doc = "Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] pub mod cpr; -#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ucv`] +#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucv`] module"] pub type UCV = crate::Reg; #[doc = "UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] pub mod ucv; -#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctr`] +#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"] pub type CTR = crate::Reg; #[doc = "Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] diff --git a/jh7110-vf2-13b-pac/src/uart0/cpr.rs b/jh7110-vf2-13b-pac/src/uart0/cpr.rs index 4807519..332b584 100644 --- a/jh7110-vf2-13b-pac/src/uart0/cpr.rs +++ b/jh7110-vf2-13b-pac/src/uart0/cpr.rs @@ -89,7 +89,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/ctr.rs b/jh7110-vf2-13b-pac/src/uart0/ctr.rs index c3760d5..ac70194 100644 --- a/jh7110-vf2-13b-pac/src/uart0/ctr.rs +++ b/jh7110-vf2-13b-pac/src/uart0/ctr.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/dlh.rs b/jh7110-vf2-13b-pac/src/uart0/dlh.rs index 3257a2d..2a788c1 100644 --- a/jh7110-vf2-13b-pac/src/uart0/dlh.rs +++ b/jh7110-vf2-13b-pac/src/uart0/dlh.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLH_R = crate::FieldReader; #[doc = "Field `dlh` writer - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dlh(&mut self) -> DLH_W { - DLH_W::new(self) + pub fn dlh(&mut self) -> DLH_W { + DLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/dll.rs b/jh7110-vf2-13b-pac/src/uart0/dll.rs index 9c9daff..1c9d765 100644 --- a/jh7110-vf2-13b-pac/src/uart0/dll.rs +++ b/jh7110-vf2-13b-pac/src/uart0/dll.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLL_R = crate::FieldReader; #[doc = "Field `dll` writer - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dll(&mut self) -> DLL_W { - DLL_W::new(self) + pub fn dll(&mut self) -> DLL_W { + DLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/dmasa.rs b/jh7110-vf2-13b-pac/src/uart0/dmasa.rs index 7bcfb26..2fc4e6d 100644 --- a/jh7110-vf2-13b-pac/src/uart0/dmasa.rs +++ b/jh7110-vf2-13b-pac/src/uart0/dmasa.rs @@ -3,15 +3,19 @@ pub type R = crate::R; #[doc = "Register `dmasa` writer"] pub type W = crate::W; #[doc = "Field `dmasa` writer - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type DMASA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMASA_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn dmasa(&mut self) -> DMASA_W { - DMASA_W::new(self) + pub fn dmasa(&mut self) -> DMASA_W { + DMASA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/far.rs b/jh7110-vf2-13b-pac/src/uart0/far.rs index 3b3bcb1..d52059a 100644 --- a/jh7110-vf2-13b-pac/src/uart0/far.rs +++ b/jh7110-vf2-13b-pac/src/uart0/far.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `far` reader - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] pub type FAR_R = crate::BitReader; #[doc = "Field `far` writer - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] -pub type FAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FAR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] #[must_use] - pub fn far(&mut self) -> FAR_W { - FAR_W::new(self) + pub fn far(&mut self) -> FAR_W { + FAR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/fcr.rs b/jh7110-vf2-13b-pac/src/uart0/fcr.rs index 4fbb499..a64a60b 100644 --- a/jh7110-vf2-13b-pac/src/uart0/fcr.rs +++ b/jh7110-vf2-13b-pac/src/uart0/fcr.rs @@ -3,55 +3,59 @@ pub type R = crate::R; #[doc = "Register `fcr` writer"] pub type W = crate::W; #[doc = "Field `fifoe` writer - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] -pub type FIFOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIFOE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfifor` writer - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfifor` writer - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dmam` writer - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] -pub type DMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMAM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tet` writer - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type TET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `rt` writer - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type RT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type RT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl W { #[doc = "Bit 0 - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] #[inline(always)] #[must_use] - pub fn fifoe(&mut self) -> FIFOE_W { - FIFOE_W::new(self) + pub fn fifoe(&mut self) -> FIFOE_W { + FIFOE_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfifor(&mut self) -> RFIFOR_W { - RFIFOR_W::new(self) + pub fn rfifor(&mut self) -> RFIFOR_W { + RFIFOR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfifor(&mut self) -> XFIFOR_W { - XFIFOR_W::new(self) + pub fn xfifor(&mut self) -> XFIFOR_W { + XFIFOR_W::new(self, 2) } #[doc = "Bit 3 - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn dmam(&mut self) -> DMAM_W { - DMAM_W::new(self) + pub fn dmam(&mut self) -> DMAM_W { + DMAM_W::new(self, 3) } #[doc = "Bits 4:5 - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn tet(&mut self) -> TET_W { - TET_W::new(self) + pub fn tet(&mut self) -> TET_W { + TET_W::new(self, 4) } #[doc = "Bits 6:7 - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn rt(&mut self) -> RT_W { - RT_W::new(self) + pub fn rt(&mut self) -> RT_W { + RT_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/htx.rs b/jh7110-vf2-13b-pac/src/uart0/htx.rs index ad027bd..fc82325 100644 --- a/jh7110-vf2-13b-pac/src/uart0/htx.rs +++ b/jh7110-vf2-13b-pac/src/uart0/htx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `htx` reader - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] pub type HTX_R = crate::BitReader; #[doc = "Field `htx` writer - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] -pub type HTX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HTX_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] #[must_use] - pub fn htx(&mut self) -> HTX_W { - HTX_W::new(self) + pub fn htx(&mut self) -> HTX_W { + HTX_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/ier.rs b/jh7110-vf2-13b-pac/src/uart0/ier.rs index 006fbea..3cf3d7f 100644 --- a/jh7110-vf2-13b-pac/src/uart0/ier.rs +++ b/jh7110-vf2-13b-pac/src/uart0/ier.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `erbfi` reader - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] pub type ERBFI_R = crate::BitReader; #[doc = "Field `erbfi` writer - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] -pub type ERBFI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ERBFI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `etbei` reader - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] pub type ETBEI_R = crate::BitReader; #[doc = "Field `etbei` writer - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ETBEI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ETBEI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `elsi` reader - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] pub type ELSI_R = crate::BitReader; #[doc = "Field `elsi` writer - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ELSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ELSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `edssi` reader - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] pub type EDSSI_R = crate::BitReader; #[doc = "Field `edssi` writer - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] -pub type EDSSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EDSSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ptime` reader - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] pub type PTIME_R = crate::BitReader; #[doc = "Field `ptime` writer - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] -pub type PTIME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PTIME_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn erbfi(&mut self) -> ERBFI_W { - ERBFI_W::new(self) + pub fn erbfi(&mut self) -> ERBFI_W { + ERBFI_W::new(self, 0) } #[doc = "Bit 1 - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn etbei(&mut self) -> ETBEI_W { - ETBEI_W::new(self) + pub fn etbei(&mut self) -> ETBEI_W { + ETBEI_W::new(self, 1) } #[doc = "Bit 2 - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn elsi(&mut self) -> ELSI_W { - ELSI_W::new(self) + pub fn elsi(&mut self) -> ELSI_W { + ELSI_W::new(self, 2) } #[doc = "Bit 3 - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn edssi(&mut self) -> EDSSI_W { - EDSSI_W::new(self) + pub fn edssi(&mut self) -> EDSSI_W { + EDSSI_W::new(self, 3) } #[doc = "Bit 7 - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn ptime(&mut self) -> PTIME_W { - PTIME_W::new(self) + pub fn ptime(&mut self) -> PTIME_W { + PTIME_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/iir.rs b/jh7110-vf2-13b-pac/src/uart0/iir.rs index c90daa5..c949f03 100644 --- a/jh7110-vf2-13b-pac/src/uart0/iir.rs +++ b/jh7110-vf2-13b-pac/src/uart0/iir.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/lcr.rs b/jh7110-vf2-13b-pac/src/uart0/lcr.rs index acd83ee..3bc10c2 100644 --- a/jh7110-vf2-13b-pac/src/uart0/lcr.rs +++ b/jh7110-vf2-13b-pac/src/uart0/lcr.rs @@ -7,7 +7,7 @@ is zero), always readable. This is used to select the number of data bits per ch pub type DLS_R = crate::FieldReader; #[doc = "Field `dls` writer - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] -pub type DLS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DLS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `stop` reader - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] @@ -15,31 +15,31 @@ pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pen` reader - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] pub type PEN_R = crate::BitReader; #[doc = "Field `pen` writer - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] -pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `eps` reader - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] pub type EPS_R = crate::BitReader; #[doc = "Field `eps` writer - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] -pub type EPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EPS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bc` reader - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] pub type BC_R = crate::BitReader; #[doc = "Field `bc` writer - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] -pub type BC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dlab` reader - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] pub type DLAB_R = crate::BitReader; #[doc = "Field `dlab` writer - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] -pub type DLAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DLAB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:1 - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] @@ -84,46 +84,50 @@ impl W { is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] #[inline(always)] #[must_use] - pub fn dls(&mut self) -> DLS_W { - DLS_W::new(self) + pub fn dls(&mut self) -> DLS_W { + DLS_W::new(self, 0) } #[doc = "Bit 2 - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 2) } #[doc = "Bit 3 - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W { - PEN_W::new(self) + pub fn pen(&mut self) -> PEN_W { + PEN_W::new(self, 3) } #[doc = "Bit 4 - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] #[inline(always)] #[must_use] - pub fn eps(&mut self) -> EPS_W { - EPS_W::new(self) + pub fn eps(&mut self) -> EPS_W { + EPS_W::new(self, 4) } #[doc = "Bit 6 - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] #[inline(always)] #[must_use] - pub fn bc(&mut self) -> BC_W { - BC_W::new(self) + pub fn bc(&mut self) -> BC_W { + BC_W::new(self, 6) } #[doc = "Bit 7 - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] #[inline(always)] #[must_use] - pub fn dlab(&mut self) -> DLAB_W { - DLAB_W::new(self) + pub fn dlab(&mut self) -> DLAB_W { + DLAB_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/lpdlh.rs b/jh7110-vf2-13b-pac/src/uart0/lpdlh.rs index 8a910c8..095afa9 100644 --- a/jh7110-vf2-13b-pac/src/uart0/lpdlh.rs +++ b/jh7110-vf2-13b-pac/src/uart0/lpdlh.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdlh` reader - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] pub type LPDLH_R = crate::FieldReader; #[doc = "Field `lpdlh` writer - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] -pub type LPDLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] #[must_use] - pub fn lpdlh(&mut self) -> LPDLH_W { - LPDLH_W::new(self) + pub fn lpdlh(&mut self) -> LPDLH_W { + LPDLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/lpdll.rs b/jh7110-vf2-13b-pac/src/uart0/lpdll.rs index 7780651..21d0018 100644 --- a/jh7110-vf2-13b-pac/src/uart0/lpdll.rs +++ b/jh7110-vf2-13b-pac/src/uart0/lpdll.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdll` reader - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] pub type LPDLL_R = crate::FieldReader; #[doc = "Field `lpdll` writer - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type LPDLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn lpdll(&mut self) -> LPDLL_W { - LPDLL_W::new(self) + pub fn lpdll(&mut self) -> LPDLL_W { + LPDLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/lsr.rs b/jh7110-vf2-13b-pac/src/uart0/lsr.rs index f576c10..ff2ab48 100644 --- a/jh7110-vf2-13b-pac/src/uart0/lsr.rs +++ b/jh7110-vf2-13b-pac/src/uart0/lsr.rs @@ -73,7 +73,11 @@ set to one). This is used to indicate if there is at least one parity error, fra } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/mcr.rs b/jh7110-vf2-13b-pac/src/uart0/mcr.rs index 6932ee7..9c93108 100644 --- a/jh7110-vf2-13b-pac/src/uart0/mcr.rs +++ b/jh7110-vf2-13b-pac/src/uart0/mcr.rs @@ -7,7 +7,7 @@ set to one), the dtr_n output is held inactive high while the value of this loca pub type DTR_R = crate::BitReader; #[doc = "Field `dtr` writer - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type DTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rts` reader - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR\\[5\\] @@ -23,19 +23,19 @@ set to one) and FIFOs enable (FCR\\[0\\] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR\\[1\\] is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out1` reader - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT1_R = crate::BitReader; #[doc = "Field `out1` writer - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out2` reader - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT2_R = crate::BitReader; #[doc = "Field `out2` writer - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `lb` reader - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] @@ -43,15 +43,15 @@ pub type LB_R = crate::BitReader; #[doc = "Field `lb` writer - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] -pub type LB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `afce` reader - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] pub type AFCE_R = crate::BitReader; #[doc = "Field `afce` writer - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] -pub type AFCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AFCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sire` reader - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] pub type SIRE_R = crate::BitReader; #[doc = "Field `sire` writer - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] -pub type SIRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SIRE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] @@ -105,8 +105,8 @@ impl W { set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn dtr(&mut self) -> DTR_W { - DTR_W::new(self) + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 0) } #[doc = "Bit 1 - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] @@ -117,44 +117,48 @@ is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W { - RTS_W::new(self) + pub fn rts(&mut self) -> RTS_W { + RTS_W::new(self, 1) } #[doc = "Bit 2 - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out1(&mut self) -> OUT1_W { - OUT1_W::new(self) + pub fn out1(&mut self) -> OUT1_W { + OUT1_W::new(self, 2) } #[doc = "Bit 3 - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out2(&mut self) -> OUT2_W { - OUT2_W::new(self) + pub fn out2(&mut self) -> OUT2_W { + OUT2_W::new(self, 3) } #[doc = "Bit 4 - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] #[inline(always)] #[must_use] - pub fn lb(&mut self) -> LB_W { - LB_W::new(self) + pub fn lb(&mut self) -> LB_W { + LB_W::new(self, 4) } #[doc = "Bit 5 - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] #[inline(always)] #[must_use] - pub fn afce(&mut self) -> AFCE_W { - AFCE_W::new(self) + pub fn afce(&mut self) -> AFCE_W { + AFCE_W::new(self, 5) } #[doc = "Bit 6 - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] #[inline(always)] #[must_use] - pub fn sire(&mut self) -> SIRE_W { - SIRE_W::new(self) + pub fn sire(&mut self) -> SIRE_W { + SIRE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/msr.rs b/jh7110-vf2-13b-pac/src/uart0/msr.rs index 65c526b..b54fc38 100644 --- a/jh7110-vf2-13b-pac/src/uart0/msr.rs +++ b/jh7110-vf2-13b-pac/src/uart0/msr.rs @@ -93,7 +93,11 @@ set to one), DCD is the same as MCR\\[3\\] } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/rbr.rs b/jh7110-vf2-13b-pac/src/uart0/rbr.rs index 03003ed..403adcf 100644 --- a/jh7110-vf2-13b-pac/src/uart0/rbr.rs +++ b/jh7110-vf2-13b-pac/src/uart0/rbr.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/rfl.rs b/jh7110-vf2-13b-pac/src/uart0/rfl.rs index 2aea928..59355cb 100644 --- a/jh7110-vf2-13b-pac/src/uart0/rfl.rs +++ b/jh7110-vf2-13b-pac/src/uart0/rfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/rfw.rs b/jh7110-vf2-13b-pac/src/uart0/rfw.rs index 7b917de..490472d 100644 --- a/jh7110-vf2-13b-pac/src/uart0/rfw.rs +++ b/jh7110-vf2-13b-pac/src/uart0/rfw.rs @@ -4,36 +4,40 @@ pub type R = crate::R; pub type W = crate::W; #[doc = "Field `rfwd` writer - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] -pub type RFWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type RFWD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `rfpe` writer - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] -pub type RFPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFPE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rffe` writer - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] -pub type RFFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bits 0:7 - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] #[inline(always)] #[must_use] - pub fn rfwd(&mut self) -> RFWD_W { - RFWD_W::new(self) + pub fn rfwd(&mut self) -> RFWD_W { + RFWD_W::new(self, 0) } #[doc = "Bit 8 - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rfpe(&mut self) -> RFPE_W { - RFPE_W::new(self) + pub fn rfpe(&mut self) -> RFPE_W { + RFPE_W::new(self, 8) } #[doc = "Bit 9 - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rffe(&mut self) -> RFFE_W { - RFFE_W::new(self) + pub fn rffe(&mut self) -> RFFE_W { + RFFE_W::new(self, 9) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sbcr.rs b/jh7110-vf2-13b-pac/src/uart0/sbcr.rs index 73914e9..5a120c0 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sbcr.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sbcr.rs @@ -7,7 +7,7 @@ pub type W = crate::W; pub type SBCR_R = crate::BitReader; #[doc = "Field `sbcr` writer - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] -pub type SBCR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SBCR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] @@ -21,10 +21,14 @@ impl W { = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] #[inline(always)] #[must_use] - pub fn sbcr(&mut self) -> SBCR_W { - SBCR_W::new(self) + pub fn sbcr(&mut self) -> SBCR_W { + SBCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/scr.rs b/jh7110-vf2-13b-pac/src/uart0/scr.rs index 744352e..f46ba21 100644 --- a/jh7110-vf2-13b-pac/src/uart0/scr.rs +++ b/jh7110-vf2-13b-pac/src/uart0/scr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `scr` reader - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sdmam.rs b/jh7110-vf2-13b-pac/src/uart0/sdmam.rs index 684377c..4be4fa2 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sdmam.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sdmam.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sdmam` reader - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] pub type SDMAM_R = crate::BitReader; #[doc = "Field `sdmam` writer - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] -pub type SDMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SDMAM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn sdmam(&mut self) -> SDMAM_W { - SDMAM_W::new(self) + pub fn sdmam(&mut self) -> SDMAM_W { + SDMAM_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sfe.rs b/jh7110-vf2-13b-pac/src/uart0/sfe.rs index e68b088..ed26fee 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sfe.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sfe.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sfe` reader - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] pub type SFE_R = crate::BitReader; #[doc = "Field `sfe` writer - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] -pub type SFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] #[must_use] - pub fn sfe(&mut self) -> SFE_W { - SFE_W::new(self) + pub fn sfe(&mut self) -> SFE_W { + SFE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srbr0.rs b/jh7110-vf2-13b-pac/src/uart0/srbr0.rs index 4076661..4e44d1a 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srbr0.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srbr0.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srbr1.rs b/jh7110-vf2-13b-pac/src/uart0/srbr1.rs index 2f31b75..46bc479 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srbr1.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srbr1.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srbr10.rs b/jh7110-vf2-13b-pac/src/uart0/srbr10.rs index 3639d65..70297bf 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srbr10.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srbr10.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srbr11.rs b/jh7110-vf2-13b-pac/src/uart0/srbr11.rs index 92d29b1..28d0277 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srbr11.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srbr11.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srbr12.rs b/jh7110-vf2-13b-pac/src/uart0/srbr12.rs index 52e795e..3eccd9a 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srbr12.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srbr12.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srbr13.rs b/jh7110-vf2-13b-pac/src/uart0/srbr13.rs index 50aae40..e47e4e4 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srbr13.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srbr13.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srbr14.rs b/jh7110-vf2-13b-pac/src/uart0/srbr14.rs index cb25819..8f23662 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srbr14.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srbr14.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srbr15.rs b/jh7110-vf2-13b-pac/src/uart0/srbr15.rs index b25ae46..1dac092 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srbr15.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srbr15.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srbr2.rs b/jh7110-vf2-13b-pac/src/uart0/srbr2.rs index 9f3236c..afb0617 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srbr2.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srbr2.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srbr3.rs b/jh7110-vf2-13b-pac/src/uart0/srbr3.rs index 5c1edda..0ff3650 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srbr3.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srbr3.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srbr4.rs b/jh7110-vf2-13b-pac/src/uart0/srbr4.rs index e6bee93..59560c4 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srbr4.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srbr4.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srbr5.rs b/jh7110-vf2-13b-pac/src/uart0/srbr5.rs index e599009..763e341 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srbr5.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srbr5.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srbr6.rs b/jh7110-vf2-13b-pac/src/uart0/srbr6.rs index b0155b3..78e2a40 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srbr6.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srbr6.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srbr7.rs b/jh7110-vf2-13b-pac/src/uart0/srbr7.rs index b8f9b88..0723ff0 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srbr7.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srbr7.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srbr8.rs b/jh7110-vf2-13b-pac/src/uart0/srbr8.rs index f57b044..4702cd9 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srbr8.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srbr8.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srbr9.rs b/jh7110-vf2-13b-pac/src/uart0/srbr9.rs index 3a160aa..e1a262e 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srbr9.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srbr9.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srr.rs b/jh7110-vf2-13b-pac/src/uart0/srr.rs index 6671199..fdb0c0a 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srr.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srr.rs @@ -3,31 +3,35 @@ pub type R = crate::R; #[doc = "Register `srr` writer"] pub type W = crate::W; #[doc = "Field `ur` writer - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] -pub type UR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type UR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfr` writer - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfr` writer - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFR_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] #[inline(always)] #[must_use] - pub fn ur(&mut self) -> UR_W { - UR_W::new(self) + pub fn ur(&mut self) -> UR_W { + UR_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfr(&mut self) -> RFR_W { - RFR_W::new(self) + pub fn rfr(&mut self) -> RFR_W { + RFR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfr(&mut self) -> XFR_W { - XFR_W::new(self) + pub fn xfr(&mut self) -> XFR_W { + XFR_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srt.rs b/jh7110-vf2-13b-pac/src/uart0/srt.rs index fed4f1f..da909fd 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srt.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `srt` reader - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] pub type SRT_R = crate::FieldReader; #[doc = "Field `srt` writer - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type SRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SRT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn srt(&mut self) -> SRT_W { - SRT_W::new(self) + pub fn srt(&mut self) -> SRT_W { + SRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/srts.rs b/jh7110-vf2-13b-pac/src/uart0/srts.rs index ceb0ee4..cf1e2a9 100644 --- a/jh7110-vf2-13b-pac/src/uart0/srts.rs +++ b/jh7110-vf2-13b-pac/src/uart0/srts.rs @@ -15,7 +15,7 @@ pub type SRTS_R = crate::BitReader; = 1) and FIFOs enable (FCR\\[0\\] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR\\[4\\] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] -pub type SRTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SRTS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Request to Send. This is a shadow register for the RTS bit (MCR\\[1\\]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] = 0), the rts_n signal is set low by programming MCR\\[1\\] @@ -37,10 +37,14 @@ impl W { = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn srts(&mut self) -> SRTS_W { - SRTS_W::new(self) + pub fn srts(&mut self) -> SRTS_W { + SRTS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/stet.rs b/jh7110-vf2-13b-pac/src/uart0/stet.rs index acb8ba1..503dc8a 100644 --- a/jh7110-vf2-13b-pac/src/uart0/stet.rs +++ b/jh7110-vf2-13b-pac/src/uart0/stet.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `stet` reader - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] pub type STET_R = crate::FieldReader; #[doc = "Field `stet` writer - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type STET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type STET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn stet(&mut self) -> STET_W { - STET_W::new(self) + pub fn stet(&mut self) -> STET_W { + STET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sthr0.rs b/jh7110-vf2-13b-pac/src/uart0/sthr0.rs index bfd277a..764ff05 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sthr0.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sthr0.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sthr1.rs b/jh7110-vf2-13b-pac/src/uart0/sthr1.rs index cc79733..5d58855 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sthr1.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sthr1.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sthr10.rs b/jh7110-vf2-13b-pac/src/uart0/sthr10.rs index be2659d..ffc38ff 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sthr10.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sthr10.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sthr11.rs b/jh7110-vf2-13b-pac/src/uart0/sthr11.rs index 8613dd5..1f8147f 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sthr11.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sthr11.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sthr12.rs b/jh7110-vf2-13b-pac/src/uart0/sthr12.rs index b354b10..7d816f3 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sthr12.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sthr12.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sthr13.rs b/jh7110-vf2-13b-pac/src/uart0/sthr13.rs index 06df4bc..9283b6a 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sthr13.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sthr13.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sthr14.rs b/jh7110-vf2-13b-pac/src/uart0/sthr14.rs index e181dd0..2daf622 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sthr14.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sthr14.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sthr15.rs b/jh7110-vf2-13b-pac/src/uart0/sthr15.rs index 4825778..f70715e 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sthr15.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sthr15.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sthr2.rs b/jh7110-vf2-13b-pac/src/uart0/sthr2.rs index d390f10..f1a9c77 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sthr2.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sthr2.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sthr3.rs b/jh7110-vf2-13b-pac/src/uart0/sthr3.rs index a74fdf0..06aab9e 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sthr3.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sthr3.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sthr4.rs b/jh7110-vf2-13b-pac/src/uart0/sthr4.rs index 1ee6b87..f6e7944 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sthr4.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sthr4.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sthr5.rs b/jh7110-vf2-13b-pac/src/uart0/sthr5.rs index ca360fe..7873a53 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sthr5.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sthr5.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sthr6.rs b/jh7110-vf2-13b-pac/src/uart0/sthr6.rs index 18e6fac..87c81df 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sthr6.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sthr6.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sthr7.rs b/jh7110-vf2-13b-pac/src/uart0/sthr7.rs index 27072a3..9928b3d 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sthr7.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sthr7.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sthr8.rs b/jh7110-vf2-13b-pac/src/uart0/sthr8.rs index 15060b8..565cb1d 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sthr8.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sthr8.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/sthr9.rs b/jh7110-vf2-13b-pac/src/uart0/sthr9.rs index 58af642..e64fece 100644 --- a/jh7110-vf2-13b-pac/src/uart0/sthr9.rs +++ b/jh7110-vf2-13b-pac/src/uart0/sthr9.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/tfl.rs b/jh7110-vf2-13b-pac/src/uart0/tfl.rs index e1faba6..db09fe3 100644 --- a/jh7110-vf2-13b-pac/src/uart0/tfl.rs +++ b/jh7110-vf2-13b-pac/src/uart0/tfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/tfr.rs b/jh7110-vf2-13b-pac/src/uart0/tfr.rs index 8e9ad91..714deff 100644 --- a/jh7110-vf2-13b-pac/src/uart0/tfr.rs +++ b/jh7110-vf2-13b-pac/src/uart0/tfr.rs @@ -14,7 +14,11 @@ is set to one). When FIFOs are implemented and enabled, reading this register gi } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/thr.rs b/jh7110-vf2-13b-pac/src/uart0/thr.rs index f910bd8..7845232 100644 --- a/jh7110-vf2-13b-pac/src/uart0/thr.rs +++ b/jh7110-vf2-13b-pac/src/uart0/thr.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `thr` writer - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type THR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type THR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn thr(&mut self) -> THR_W { - THR_W::new(self) + pub fn thr(&mut self) -> THR_W { + THR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/ucv.rs b/jh7110-vf2-13b-pac/src/uart0/ucv.rs index 8a3be91..6497a08 100644 --- a/jh7110-vf2-13b-pac/src/uart0/ucv.rs +++ b/jh7110-vf2-13b-pac/src/uart0/ucv.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart0/usr.rs b/jh7110-vf2-13b-pac/src/uart0/usr.rs index 445a085..b96417d 100644 --- a/jh7110-vf2-13b-pac/src/uart0/usr.rs +++ b/jh7110-vf2-13b-pac/src/uart0/usr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1.rs b/jh7110-vf2-13b-pac/src/uart1.rs index c462fbf..8a5f089 100644 --- a/jh7110-vf2-13b-pac/src/uart1.rs +++ b/jh7110-vf2-13b-pac/src/uart1.rs @@ -4,20 +4,13 @@ pub struct RegisterBlock { _reserved_0_dll: [u8; 0x04], _reserved_1_dlh: [u8; 0x04], _reserved_2_fcr: [u8; 0x04], - #[doc = "0x0c - Line Control Register"] - pub lcr: LCR, - #[doc = "0x10 - Modem Control Register"] - pub mcr: MCR, - #[doc = "0x14 - Line Status Register"] - pub lsr: LSR, - #[doc = "0x18 - Line Status Register"] - pub msr: MSR, - #[doc = "0x1c - Scratch Pad Register"] - pub scr: SCR, - #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdll: LPDLL, - #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdlh: LPDLH, + lcr: LCR, + mcr: MCR, + lsr: LSR, + msr: MSR, + scr: SCR, + lpdll: LPDLL, + lpdlh: LPDLH, _reserved10: [u8; 0x08], _reserved_10_srbr0: [u8; 0x04], _reserved_11_srbr1: [u8; 0x04], @@ -35,564 +28,663 @@ pub struct RegisterBlock { _reserved_23_srbr13: [u8; 0x04], _reserved_24_srbr14: [u8; 0x04], _reserved_25_srbr15: [u8; 0x04], - #[doc = "0x70 - FIFO Access Register"] - pub far: FAR, - #[doc = "0x74 - Transmit FIFO Read"] - pub tfr: TFR, - #[doc = "0x78 - Receive FIFO Write"] - pub rfw: RFW, - #[doc = "0x7c - UART Status Register"] - pub usr: USR, - #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub tfl: TFL, - #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub rfl: RFL, - #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srr: SRR, - #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srts: SRTS, - #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sbcr: SBCR, - #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sdmam: SDMAM, - #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sfe: SFE, - #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srt: SRT, - #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub stet: STET, - #[doc = "0xa4 - Halt TX"] - pub htx: HTX, - #[doc = "0xa8 - DMA Software Acknowledge"] - pub dmasa: DMASA, + far: FAR, + tfr: TFR, + rfw: RFW, + usr: USR, + tfl: TFL, + rfl: RFL, + srr: SRR, + srts: SRTS, + sbcr: SBCR, + sdmam: SDMAM, + sfe: SFE, + srt: SRT, + stet: STET, + htx: HTX, + dmasa: DMASA, _reserved41: [u8; 0x48], - #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] - pub cpr: CPR, + cpr: CPR, _reserved_42_ctr: [u8; 0x04], } impl RegisterBlock { #[doc = "0x00 - Divisor Latch Low"] #[inline(always)] pub const fn dll(&self) -> &DLL { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Transmit Holding Register"] #[inline(always)] pub const fn thr(&self) -> &THR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Receive Buffer Register"] #[inline(always)] pub const fn rbr(&self) -> &RBR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x04 - Interrupt Enable Register"] #[inline(always)] pub const fn ier(&self) -> &IER { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x04 - Divisor Latch High"] #[inline(always)] pub const fn dlh(&self) -> &DLH { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x08 - FIFO Control Register"] #[inline(always)] pub const fn fcr(&self) -> &FCR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } } #[doc = "0x08 - Interrupt Identity Register"] #[inline(always)] pub const fn iir(&self) -> &IIR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } + } + #[doc = "0x0c - Line Control Register"] + #[inline(always)] + pub const fn lcr(&self) -> &LCR { + &self.lcr + } + #[doc = "0x10 - Modem Control Register"] + #[inline(always)] + pub const fn mcr(&self) -> &MCR { + &self.mcr + } + #[doc = "0x14 - Line Status Register"] + #[inline(always)] + pub const fn lsr(&self) -> &LSR { + &self.lsr + } + #[doc = "0x18 - Line Status Register"] + #[inline(always)] + pub const fn msr(&self) -> &MSR { + &self.msr + } + #[doc = "0x1c - Scratch Pad Register"] + #[inline(always)] + pub const fn scr(&self) -> &SCR { + &self.scr + } + #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdll(&self) -> &LPDLL { + &self.lpdll + } + #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdlh(&self) -> &LPDLH { + &self.lpdlh } #[doc = "0x30 - Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr0(&self) -> &STHR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x30 - Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr0(&self) -> &SRBR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x34 - Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr1(&self) -> &STHR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x34 - Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr1(&self) -> &SRBR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x38 - Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr2(&self) -> &STHR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x38 - Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr2(&self) -> &SRBR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x3c - Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr3(&self) -> &STHR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x3c - Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr3(&self) -> &SRBR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x40 - Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr4(&self) -> &STHR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x40 - Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr4(&self) -> &SRBR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x44 - Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr5(&self) -> &STHR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x44 - Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr5(&self) -> &SRBR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x48 - Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr6(&self) -> &STHR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x48 - Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr6(&self) -> &SRBR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x4c - Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr7(&self) -> &STHR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x4c - Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr7(&self) -> &SRBR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x50 - Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr8(&self) -> &STHR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x50 - Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr8(&self) -> &SRBR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x54 - Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr9(&self) -> &STHR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x54 - Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr9(&self) -> &SRBR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x58 - Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr10(&self) -> &STHR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x58 - Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr10(&self) -> &SRBR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x5c - Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr11(&self) -> &STHR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x5c - Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr11(&self) -> &SRBR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x60 - Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr12(&self) -> &STHR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x60 - Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr12(&self) -> &SRBR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x64 - Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr13(&self) -> &STHR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x64 - Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr13(&self) -> &SRBR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x68 - Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr14(&self) -> &STHR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x68 - Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr14(&self) -> &SRBR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x6c - Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr15(&self) -> &STHR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } } #[doc = "0x6c - Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr15(&self) -> &SRBR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } + } + #[doc = "0x70 - FIFO Access Register"] + #[inline(always)] + pub const fn far(&self) -> &FAR { + &self.far + } + #[doc = "0x74 - Transmit FIFO Read"] + #[inline(always)] + pub const fn tfr(&self) -> &TFR { + &self.tfr + } + #[doc = "0x78 - Receive FIFO Write"] + #[inline(always)] + pub const fn rfw(&self) -> &RFW { + &self.rfw + } + #[doc = "0x7c - UART Status Register"] + #[inline(always)] + pub const fn usr(&self) -> &USR { + &self.usr + } + #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn tfl(&self) -> &TFL { + &self.tfl + } + #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn rfl(&self) -> &RFL { + &self.rfl + } + #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srr(&self) -> &SRR { + &self.srr + } + #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srts(&self) -> &SRTS { + &self.srts + } + #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sbcr(&self) -> &SBCR { + &self.sbcr + } + #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sdmam(&self) -> &SDMAM { + &self.sdmam + } + #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sfe(&self) -> &SFE { + &self.sfe + } + #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srt(&self) -> &SRT { + &self.srt + } + #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn stet(&self) -> &STET { + &self.stet + } + #[doc = "0xa4 - Halt TX"] + #[inline(always)] + pub const fn htx(&self) -> &HTX { + &self.htx + } + #[doc = "0xa8 - DMA Software Acknowledge"] + #[inline(always)] + pub const fn dmasa(&self) -> &DMASA { + &self.dmasa + } + #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn cpr(&self) -> &CPR { + &self.cpr } #[doc = "0xf8 - Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ctr(&self) -> &CTR { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } #[doc = "0xf8 - UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ucv(&self) -> &UCV { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } } -#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rbr`] +#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbr`] module"] pub type RBR = crate::Reg; #[doc = "Receive Buffer Register"] pub mod rbr; -#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`thr`] +#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thr`] module"] pub type THR = crate::Reg; #[doc = "Transmit Holding Register"] pub mod thr; -#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dll`] +#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll`] module"] pub type DLL = crate::Reg; #[doc = "Divisor Latch Low"] pub mod dll; -#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dlh`] +#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlh`] module"] pub type DLH = crate::Reg; #[doc = "Divisor Latch High"] pub mod dlh; -#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`iir`] +#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] module"] pub type IIR = crate::Reg; #[doc = "Interrupt Identity Register"] pub mod iir; -#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fcr`] +#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"] pub type FCR = crate::Reg; #[doc = "FIFO Control Register"] pub mod fcr; -#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lcr`] +#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] module"] pub type LCR = crate::Reg; #[doc = "Line Control Register"] pub mod lcr; -#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mcr`] +#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] pub type MCR = crate::Reg; #[doc = "Modem Control Register"] pub mod mcr; -#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lsr`] +#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] module"] pub type LSR = crate::Reg; #[doc = "Line Status Register"] pub mod lsr; -#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msr`] +#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"] pub type MSR = crate::Reg; #[doc = "Line Status Register"] pub mod msr; -#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scr`] +#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`] module"] pub type SCR = crate::Reg; #[doc = "Scratch Pad Register"] pub mod scr; -#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdll`] +#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdll`] module"] pub type LPDLL = crate::Reg; #[doc = "Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdll; -#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdlh`] +#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdlh`] module"] pub type LPDLH = crate::Reg; #[doc = "Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdlh; -#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr0`] +#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr0`] module"] pub type SRBR0 = crate::Reg; #[doc = "Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr0; -#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr0`] +#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr0`] module"] pub type STHR0 = crate::Reg; #[doc = "Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr0; -#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr1`] +#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr1`] module"] pub type SRBR1 = crate::Reg; #[doc = "Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr1; -#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr1`] +#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr1`] module"] pub type STHR1 = crate::Reg; #[doc = "Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr1; -#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr2`] +#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr2`] module"] pub type SRBR2 = crate::Reg; #[doc = "Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr2; -#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr2`] +#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr2`] module"] pub type STHR2 = crate::Reg; #[doc = "Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr2; -#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr3`] +#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr3`] module"] pub type SRBR3 = crate::Reg; #[doc = "Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr3; -#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr3`] +#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr3`] module"] pub type STHR3 = crate::Reg; #[doc = "Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr3; -#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr4`] +#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr4`] module"] pub type SRBR4 = crate::Reg; #[doc = "Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr4; -#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr4`] +#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr4`] module"] pub type STHR4 = crate::Reg; #[doc = "Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr4; -#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr5`] +#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr5`] module"] pub type SRBR5 = crate::Reg; #[doc = "Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr5; -#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr5`] +#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr5`] module"] pub type STHR5 = crate::Reg; #[doc = "Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr5; -#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr6`] +#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr6`] module"] pub type SRBR6 = crate::Reg; #[doc = "Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr6; -#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr6`] +#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr6`] module"] pub type STHR6 = crate::Reg; #[doc = "Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr6; -#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr7`] +#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr7`] module"] pub type SRBR7 = crate::Reg; #[doc = "Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr7; -#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr7`] +#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr7`] module"] pub type STHR7 = crate::Reg; #[doc = "Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr7; -#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr8`] +#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr8`] module"] pub type SRBR8 = crate::Reg; #[doc = "Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr8; -#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr8`] +#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr8`] module"] pub type STHR8 = crate::Reg; #[doc = "Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr8; -#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr9`] +#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr9`] module"] pub type SRBR9 = crate::Reg; #[doc = "Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr9; -#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr9`] +#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr9`] module"] pub type STHR9 = crate::Reg; #[doc = "Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr9; -#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr10`] +#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr10`] module"] pub type SRBR10 = crate::Reg; #[doc = "Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr10; -#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr10`] +#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr10`] module"] pub type STHR10 = crate::Reg; #[doc = "Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr10; -#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr11`] +#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr11`] module"] pub type SRBR11 = crate::Reg; #[doc = "Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr11; -#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr11`] +#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr11`] module"] pub type STHR11 = crate::Reg; #[doc = "Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr11; -#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr12`] +#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr12`] module"] pub type SRBR12 = crate::Reg; #[doc = "Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr12; -#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr12`] +#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr12`] module"] pub type STHR12 = crate::Reg; #[doc = "Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr12; -#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr13`] +#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr13`] module"] pub type SRBR13 = crate::Reg; #[doc = "Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr13; -#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr13`] +#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr13`] module"] pub type STHR13 = crate::Reg; #[doc = "Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr13; -#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr14`] +#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr14`] module"] pub type SRBR14 = crate::Reg; #[doc = "Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr14; -#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr14`] +#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr14`] module"] pub type STHR14 = crate::Reg; #[doc = "Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr14; -#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr15`] +#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr15`] module"] pub type SRBR15 = crate::Reg; #[doc = "Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr15; -#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr15`] +#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr15`] module"] pub type STHR15 = crate::Reg; #[doc = "Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr15; -#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`far`] +#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@far`] module"] pub type FAR = crate::Reg; #[doc = "FIFO Access Register"] pub mod far; -#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfr`] +#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfr`] module"] pub type TFR = crate::Reg; #[doc = "Transmit FIFO Read"] pub mod tfr; -#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfw`] +#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfw`] module"] pub type RFW = crate::Reg; #[doc = "Receive FIFO Write"] pub mod rfw; -#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`usr`] +#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usr`] module"] pub type USR = crate::Reg; #[doc = "UART Status Register"] pub mod usr; -#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfl`] +#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfl`] module"] pub type TFL = crate::Reg; #[doc = "Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod tfl; -#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfl`] +#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfl`] module"] pub type RFL = crate::Reg; #[doc = "Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod rfl; -#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srr`] +#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srr`] module"] pub type SRR = crate::Reg; #[doc = "Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srr; -#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srts`] +#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srts`] module"] pub type SRTS = crate::Reg; #[doc = "Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srts; -#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sbcr`] +#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sbcr`] module"] pub type SBCR = crate::Reg; #[doc = "Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sbcr; -#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sdmam`] +#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdmam`] module"] pub type SDMAM = crate::Reg; #[doc = "Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sdmam; -#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sfe`] +#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfe`] module"] pub type SFE = crate::Reg; #[doc = "Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sfe; -#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srt`] +#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srt`] module"] pub type SRT = crate::Reg; #[doc = "Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srt; -#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stet`] +#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stet`] module"] pub type STET = crate::Reg; #[doc = "Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod stet; -#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`htx`] +#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@htx`] module"] pub type HTX = crate::Reg; #[doc = "Halt TX"] pub mod htx; -#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dmasa`] +#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasa`] module"] pub type DMASA = crate::Reg; #[doc = "DMA Software Acknowledge"] pub mod dmasa; -#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cpr`] +#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpr`] module"] pub type CPR = crate::Reg; #[doc = "Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] pub mod cpr; -#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ucv`] +#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucv`] module"] pub type UCV = crate::Reg; #[doc = "UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] pub mod ucv; -#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctr`] +#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"] pub type CTR = crate::Reg; #[doc = "Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] diff --git a/jh7110-vf2-13b-pac/src/uart1/cpr.rs b/jh7110-vf2-13b-pac/src/uart1/cpr.rs index 4807519..332b584 100644 --- a/jh7110-vf2-13b-pac/src/uart1/cpr.rs +++ b/jh7110-vf2-13b-pac/src/uart1/cpr.rs @@ -89,7 +89,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/ctr.rs b/jh7110-vf2-13b-pac/src/uart1/ctr.rs index c3760d5..ac70194 100644 --- a/jh7110-vf2-13b-pac/src/uart1/ctr.rs +++ b/jh7110-vf2-13b-pac/src/uart1/ctr.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/dlh.rs b/jh7110-vf2-13b-pac/src/uart1/dlh.rs index 3257a2d..2a788c1 100644 --- a/jh7110-vf2-13b-pac/src/uart1/dlh.rs +++ b/jh7110-vf2-13b-pac/src/uart1/dlh.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLH_R = crate::FieldReader; #[doc = "Field `dlh` writer - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dlh(&mut self) -> DLH_W { - DLH_W::new(self) + pub fn dlh(&mut self) -> DLH_W { + DLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/dll.rs b/jh7110-vf2-13b-pac/src/uart1/dll.rs index 9c9daff..1c9d765 100644 --- a/jh7110-vf2-13b-pac/src/uart1/dll.rs +++ b/jh7110-vf2-13b-pac/src/uart1/dll.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLL_R = crate::FieldReader; #[doc = "Field `dll` writer - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dll(&mut self) -> DLL_W { - DLL_W::new(self) + pub fn dll(&mut self) -> DLL_W { + DLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/dmasa.rs b/jh7110-vf2-13b-pac/src/uart1/dmasa.rs index 7bcfb26..2fc4e6d 100644 --- a/jh7110-vf2-13b-pac/src/uart1/dmasa.rs +++ b/jh7110-vf2-13b-pac/src/uart1/dmasa.rs @@ -3,15 +3,19 @@ pub type R = crate::R; #[doc = "Register `dmasa` writer"] pub type W = crate::W; #[doc = "Field `dmasa` writer - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type DMASA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMASA_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn dmasa(&mut self) -> DMASA_W { - DMASA_W::new(self) + pub fn dmasa(&mut self) -> DMASA_W { + DMASA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/far.rs b/jh7110-vf2-13b-pac/src/uart1/far.rs index 3b3bcb1..d52059a 100644 --- a/jh7110-vf2-13b-pac/src/uart1/far.rs +++ b/jh7110-vf2-13b-pac/src/uart1/far.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `far` reader - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] pub type FAR_R = crate::BitReader; #[doc = "Field `far` writer - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] -pub type FAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FAR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] #[must_use] - pub fn far(&mut self) -> FAR_W { - FAR_W::new(self) + pub fn far(&mut self) -> FAR_W { + FAR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/fcr.rs b/jh7110-vf2-13b-pac/src/uart1/fcr.rs index 4fbb499..a64a60b 100644 --- a/jh7110-vf2-13b-pac/src/uart1/fcr.rs +++ b/jh7110-vf2-13b-pac/src/uart1/fcr.rs @@ -3,55 +3,59 @@ pub type R = crate::R; #[doc = "Register `fcr` writer"] pub type W = crate::W; #[doc = "Field `fifoe` writer - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] -pub type FIFOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIFOE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfifor` writer - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfifor` writer - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dmam` writer - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] -pub type DMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMAM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tet` writer - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type TET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `rt` writer - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type RT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type RT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl W { #[doc = "Bit 0 - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] #[inline(always)] #[must_use] - pub fn fifoe(&mut self) -> FIFOE_W { - FIFOE_W::new(self) + pub fn fifoe(&mut self) -> FIFOE_W { + FIFOE_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfifor(&mut self) -> RFIFOR_W { - RFIFOR_W::new(self) + pub fn rfifor(&mut self) -> RFIFOR_W { + RFIFOR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfifor(&mut self) -> XFIFOR_W { - XFIFOR_W::new(self) + pub fn xfifor(&mut self) -> XFIFOR_W { + XFIFOR_W::new(self, 2) } #[doc = "Bit 3 - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn dmam(&mut self) -> DMAM_W { - DMAM_W::new(self) + pub fn dmam(&mut self) -> DMAM_W { + DMAM_W::new(self, 3) } #[doc = "Bits 4:5 - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn tet(&mut self) -> TET_W { - TET_W::new(self) + pub fn tet(&mut self) -> TET_W { + TET_W::new(self, 4) } #[doc = "Bits 6:7 - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn rt(&mut self) -> RT_W { - RT_W::new(self) + pub fn rt(&mut self) -> RT_W { + RT_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/htx.rs b/jh7110-vf2-13b-pac/src/uart1/htx.rs index ad027bd..fc82325 100644 --- a/jh7110-vf2-13b-pac/src/uart1/htx.rs +++ b/jh7110-vf2-13b-pac/src/uart1/htx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `htx` reader - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] pub type HTX_R = crate::BitReader; #[doc = "Field `htx` writer - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] -pub type HTX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HTX_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] #[must_use] - pub fn htx(&mut self) -> HTX_W { - HTX_W::new(self) + pub fn htx(&mut self) -> HTX_W { + HTX_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/ier.rs b/jh7110-vf2-13b-pac/src/uart1/ier.rs index 006fbea..3cf3d7f 100644 --- a/jh7110-vf2-13b-pac/src/uart1/ier.rs +++ b/jh7110-vf2-13b-pac/src/uart1/ier.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `erbfi` reader - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] pub type ERBFI_R = crate::BitReader; #[doc = "Field `erbfi` writer - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] -pub type ERBFI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ERBFI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `etbei` reader - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] pub type ETBEI_R = crate::BitReader; #[doc = "Field `etbei` writer - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ETBEI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ETBEI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `elsi` reader - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] pub type ELSI_R = crate::BitReader; #[doc = "Field `elsi` writer - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ELSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ELSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `edssi` reader - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] pub type EDSSI_R = crate::BitReader; #[doc = "Field `edssi` writer - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] -pub type EDSSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EDSSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ptime` reader - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] pub type PTIME_R = crate::BitReader; #[doc = "Field `ptime` writer - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] -pub type PTIME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PTIME_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn erbfi(&mut self) -> ERBFI_W { - ERBFI_W::new(self) + pub fn erbfi(&mut self) -> ERBFI_W { + ERBFI_W::new(self, 0) } #[doc = "Bit 1 - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn etbei(&mut self) -> ETBEI_W { - ETBEI_W::new(self) + pub fn etbei(&mut self) -> ETBEI_W { + ETBEI_W::new(self, 1) } #[doc = "Bit 2 - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn elsi(&mut self) -> ELSI_W { - ELSI_W::new(self) + pub fn elsi(&mut self) -> ELSI_W { + ELSI_W::new(self, 2) } #[doc = "Bit 3 - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn edssi(&mut self) -> EDSSI_W { - EDSSI_W::new(self) + pub fn edssi(&mut self) -> EDSSI_W { + EDSSI_W::new(self, 3) } #[doc = "Bit 7 - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn ptime(&mut self) -> PTIME_W { - PTIME_W::new(self) + pub fn ptime(&mut self) -> PTIME_W { + PTIME_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/iir.rs b/jh7110-vf2-13b-pac/src/uart1/iir.rs index c90daa5..c949f03 100644 --- a/jh7110-vf2-13b-pac/src/uart1/iir.rs +++ b/jh7110-vf2-13b-pac/src/uart1/iir.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/lcr.rs b/jh7110-vf2-13b-pac/src/uart1/lcr.rs index acd83ee..3bc10c2 100644 --- a/jh7110-vf2-13b-pac/src/uart1/lcr.rs +++ b/jh7110-vf2-13b-pac/src/uart1/lcr.rs @@ -7,7 +7,7 @@ is zero), always readable. This is used to select the number of data bits per ch pub type DLS_R = crate::FieldReader; #[doc = "Field `dls` writer - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] -pub type DLS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DLS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `stop` reader - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] @@ -15,31 +15,31 @@ pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pen` reader - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] pub type PEN_R = crate::BitReader; #[doc = "Field `pen` writer - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] -pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `eps` reader - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] pub type EPS_R = crate::BitReader; #[doc = "Field `eps` writer - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] -pub type EPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EPS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bc` reader - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] pub type BC_R = crate::BitReader; #[doc = "Field `bc` writer - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] -pub type BC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dlab` reader - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] pub type DLAB_R = crate::BitReader; #[doc = "Field `dlab` writer - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] -pub type DLAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DLAB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:1 - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] @@ -84,46 +84,50 @@ impl W { is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] #[inline(always)] #[must_use] - pub fn dls(&mut self) -> DLS_W { - DLS_W::new(self) + pub fn dls(&mut self) -> DLS_W { + DLS_W::new(self, 0) } #[doc = "Bit 2 - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 2) } #[doc = "Bit 3 - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W { - PEN_W::new(self) + pub fn pen(&mut self) -> PEN_W { + PEN_W::new(self, 3) } #[doc = "Bit 4 - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] #[inline(always)] #[must_use] - pub fn eps(&mut self) -> EPS_W { - EPS_W::new(self) + pub fn eps(&mut self) -> EPS_W { + EPS_W::new(self, 4) } #[doc = "Bit 6 - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] #[inline(always)] #[must_use] - pub fn bc(&mut self) -> BC_W { - BC_W::new(self) + pub fn bc(&mut self) -> BC_W { + BC_W::new(self, 6) } #[doc = "Bit 7 - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] #[inline(always)] #[must_use] - pub fn dlab(&mut self) -> DLAB_W { - DLAB_W::new(self) + pub fn dlab(&mut self) -> DLAB_W { + DLAB_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/lpdlh.rs b/jh7110-vf2-13b-pac/src/uart1/lpdlh.rs index 8a910c8..095afa9 100644 --- a/jh7110-vf2-13b-pac/src/uart1/lpdlh.rs +++ b/jh7110-vf2-13b-pac/src/uart1/lpdlh.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdlh` reader - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] pub type LPDLH_R = crate::FieldReader; #[doc = "Field `lpdlh` writer - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] -pub type LPDLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] #[must_use] - pub fn lpdlh(&mut self) -> LPDLH_W { - LPDLH_W::new(self) + pub fn lpdlh(&mut self) -> LPDLH_W { + LPDLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/lpdll.rs b/jh7110-vf2-13b-pac/src/uart1/lpdll.rs index 7780651..21d0018 100644 --- a/jh7110-vf2-13b-pac/src/uart1/lpdll.rs +++ b/jh7110-vf2-13b-pac/src/uart1/lpdll.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdll` reader - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] pub type LPDLL_R = crate::FieldReader; #[doc = "Field `lpdll` writer - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type LPDLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn lpdll(&mut self) -> LPDLL_W { - LPDLL_W::new(self) + pub fn lpdll(&mut self) -> LPDLL_W { + LPDLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/lsr.rs b/jh7110-vf2-13b-pac/src/uart1/lsr.rs index f576c10..ff2ab48 100644 --- a/jh7110-vf2-13b-pac/src/uart1/lsr.rs +++ b/jh7110-vf2-13b-pac/src/uart1/lsr.rs @@ -73,7 +73,11 @@ set to one). This is used to indicate if there is at least one parity error, fra } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/mcr.rs b/jh7110-vf2-13b-pac/src/uart1/mcr.rs index 6932ee7..9c93108 100644 --- a/jh7110-vf2-13b-pac/src/uart1/mcr.rs +++ b/jh7110-vf2-13b-pac/src/uart1/mcr.rs @@ -7,7 +7,7 @@ set to one), the dtr_n output is held inactive high while the value of this loca pub type DTR_R = crate::BitReader; #[doc = "Field `dtr` writer - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type DTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rts` reader - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR\\[5\\] @@ -23,19 +23,19 @@ set to one) and FIFOs enable (FCR\\[0\\] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR\\[1\\] is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out1` reader - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT1_R = crate::BitReader; #[doc = "Field `out1` writer - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out2` reader - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT2_R = crate::BitReader; #[doc = "Field `out2` writer - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `lb` reader - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] @@ -43,15 +43,15 @@ pub type LB_R = crate::BitReader; #[doc = "Field `lb` writer - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] -pub type LB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `afce` reader - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] pub type AFCE_R = crate::BitReader; #[doc = "Field `afce` writer - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] -pub type AFCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AFCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sire` reader - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] pub type SIRE_R = crate::BitReader; #[doc = "Field `sire` writer - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] -pub type SIRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SIRE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] @@ -105,8 +105,8 @@ impl W { set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn dtr(&mut self) -> DTR_W { - DTR_W::new(self) + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 0) } #[doc = "Bit 1 - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] @@ -117,44 +117,48 @@ is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W { - RTS_W::new(self) + pub fn rts(&mut self) -> RTS_W { + RTS_W::new(self, 1) } #[doc = "Bit 2 - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out1(&mut self) -> OUT1_W { - OUT1_W::new(self) + pub fn out1(&mut self) -> OUT1_W { + OUT1_W::new(self, 2) } #[doc = "Bit 3 - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out2(&mut self) -> OUT2_W { - OUT2_W::new(self) + pub fn out2(&mut self) -> OUT2_W { + OUT2_W::new(self, 3) } #[doc = "Bit 4 - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] #[inline(always)] #[must_use] - pub fn lb(&mut self) -> LB_W { - LB_W::new(self) + pub fn lb(&mut self) -> LB_W { + LB_W::new(self, 4) } #[doc = "Bit 5 - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] #[inline(always)] #[must_use] - pub fn afce(&mut self) -> AFCE_W { - AFCE_W::new(self) + pub fn afce(&mut self) -> AFCE_W { + AFCE_W::new(self, 5) } #[doc = "Bit 6 - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] #[inline(always)] #[must_use] - pub fn sire(&mut self) -> SIRE_W { - SIRE_W::new(self) + pub fn sire(&mut self) -> SIRE_W { + SIRE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/msr.rs b/jh7110-vf2-13b-pac/src/uart1/msr.rs index 65c526b..b54fc38 100644 --- a/jh7110-vf2-13b-pac/src/uart1/msr.rs +++ b/jh7110-vf2-13b-pac/src/uart1/msr.rs @@ -93,7 +93,11 @@ set to one), DCD is the same as MCR\\[3\\] } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/rbr.rs b/jh7110-vf2-13b-pac/src/uart1/rbr.rs index 03003ed..403adcf 100644 --- a/jh7110-vf2-13b-pac/src/uart1/rbr.rs +++ b/jh7110-vf2-13b-pac/src/uart1/rbr.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/rfl.rs b/jh7110-vf2-13b-pac/src/uart1/rfl.rs index 2aea928..59355cb 100644 --- a/jh7110-vf2-13b-pac/src/uart1/rfl.rs +++ b/jh7110-vf2-13b-pac/src/uart1/rfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/rfw.rs b/jh7110-vf2-13b-pac/src/uart1/rfw.rs index 7b917de..490472d 100644 --- a/jh7110-vf2-13b-pac/src/uart1/rfw.rs +++ b/jh7110-vf2-13b-pac/src/uart1/rfw.rs @@ -4,36 +4,40 @@ pub type R = crate::R; pub type W = crate::W; #[doc = "Field `rfwd` writer - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] -pub type RFWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type RFWD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `rfpe` writer - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] -pub type RFPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFPE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rffe` writer - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] -pub type RFFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bits 0:7 - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] #[inline(always)] #[must_use] - pub fn rfwd(&mut self) -> RFWD_W { - RFWD_W::new(self) + pub fn rfwd(&mut self) -> RFWD_W { + RFWD_W::new(self, 0) } #[doc = "Bit 8 - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rfpe(&mut self) -> RFPE_W { - RFPE_W::new(self) + pub fn rfpe(&mut self) -> RFPE_W { + RFPE_W::new(self, 8) } #[doc = "Bit 9 - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rffe(&mut self) -> RFFE_W { - RFFE_W::new(self) + pub fn rffe(&mut self) -> RFFE_W { + RFFE_W::new(self, 9) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sbcr.rs b/jh7110-vf2-13b-pac/src/uart1/sbcr.rs index 73914e9..5a120c0 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sbcr.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sbcr.rs @@ -7,7 +7,7 @@ pub type W = crate::W; pub type SBCR_R = crate::BitReader; #[doc = "Field `sbcr` writer - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] -pub type SBCR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SBCR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] @@ -21,10 +21,14 @@ impl W { = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] #[inline(always)] #[must_use] - pub fn sbcr(&mut self) -> SBCR_W { - SBCR_W::new(self) + pub fn sbcr(&mut self) -> SBCR_W { + SBCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/scr.rs b/jh7110-vf2-13b-pac/src/uart1/scr.rs index 744352e..f46ba21 100644 --- a/jh7110-vf2-13b-pac/src/uart1/scr.rs +++ b/jh7110-vf2-13b-pac/src/uart1/scr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `scr` reader - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sdmam.rs b/jh7110-vf2-13b-pac/src/uart1/sdmam.rs index 684377c..4be4fa2 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sdmam.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sdmam.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sdmam` reader - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] pub type SDMAM_R = crate::BitReader; #[doc = "Field `sdmam` writer - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] -pub type SDMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SDMAM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn sdmam(&mut self) -> SDMAM_W { - SDMAM_W::new(self) + pub fn sdmam(&mut self) -> SDMAM_W { + SDMAM_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sfe.rs b/jh7110-vf2-13b-pac/src/uart1/sfe.rs index e68b088..ed26fee 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sfe.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sfe.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sfe` reader - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] pub type SFE_R = crate::BitReader; #[doc = "Field `sfe` writer - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] -pub type SFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] #[must_use] - pub fn sfe(&mut self) -> SFE_W { - SFE_W::new(self) + pub fn sfe(&mut self) -> SFE_W { + SFE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srbr0.rs b/jh7110-vf2-13b-pac/src/uart1/srbr0.rs index 4076661..4e44d1a 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srbr0.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srbr0.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srbr1.rs b/jh7110-vf2-13b-pac/src/uart1/srbr1.rs index 2f31b75..46bc479 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srbr1.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srbr1.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srbr10.rs b/jh7110-vf2-13b-pac/src/uart1/srbr10.rs index 3639d65..70297bf 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srbr10.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srbr10.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srbr11.rs b/jh7110-vf2-13b-pac/src/uart1/srbr11.rs index 92d29b1..28d0277 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srbr11.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srbr11.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srbr12.rs b/jh7110-vf2-13b-pac/src/uart1/srbr12.rs index 52e795e..3eccd9a 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srbr12.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srbr12.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srbr13.rs b/jh7110-vf2-13b-pac/src/uart1/srbr13.rs index 50aae40..e47e4e4 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srbr13.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srbr13.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srbr14.rs b/jh7110-vf2-13b-pac/src/uart1/srbr14.rs index cb25819..8f23662 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srbr14.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srbr14.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srbr15.rs b/jh7110-vf2-13b-pac/src/uart1/srbr15.rs index b25ae46..1dac092 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srbr15.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srbr15.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srbr2.rs b/jh7110-vf2-13b-pac/src/uart1/srbr2.rs index 9f3236c..afb0617 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srbr2.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srbr2.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srbr3.rs b/jh7110-vf2-13b-pac/src/uart1/srbr3.rs index 5c1edda..0ff3650 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srbr3.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srbr3.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srbr4.rs b/jh7110-vf2-13b-pac/src/uart1/srbr4.rs index e6bee93..59560c4 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srbr4.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srbr4.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srbr5.rs b/jh7110-vf2-13b-pac/src/uart1/srbr5.rs index e599009..763e341 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srbr5.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srbr5.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srbr6.rs b/jh7110-vf2-13b-pac/src/uart1/srbr6.rs index b0155b3..78e2a40 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srbr6.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srbr6.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srbr7.rs b/jh7110-vf2-13b-pac/src/uart1/srbr7.rs index b8f9b88..0723ff0 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srbr7.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srbr7.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srbr8.rs b/jh7110-vf2-13b-pac/src/uart1/srbr8.rs index f57b044..4702cd9 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srbr8.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srbr8.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srbr9.rs b/jh7110-vf2-13b-pac/src/uart1/srbr9.rs index 3a160aa..e1a262e 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srbr9.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srbr9.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srr.rs b/jh7110-vf2-13b-pac/src/uart1/srr.rs index 6671199..fdb0c0a 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srr.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srr.rs @@ -3,31 +3,35 @@ pub type R = crate::R; #[doc = "Register `srr` writer"] pub type W = crate::W; #[doc = "Field `ur` writer - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] -pub type UR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type UR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfr` writer - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfr` writer - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFR_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] #[inline(always)] #[must_use] - pub fn ur(&mut self) -> UR_W { - UR_W::new(self) + pub fn ur(&mut self) -> UR_W { + UR_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfr(&mut self) -> RFR_W { - RFR_W::new(self) + pub fn rfr(&mut self) -> RFR_W { + RFR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfr(&mut self) -> XFR_W { - XFR_W::new(self) + pub fn xfr(&mut self) -> XFR_W { + XFR_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srt.rs b/jh7110-vf2-13b-pac/src/uart1/srt.rs index fed4f1f..da909fd 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srt.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `srt` reader - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] pub type SRT_R = crate::FieldReader; #[doc = "Field `srt` writer - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type SRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SRT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn srt(&mut self) -> SRT_W { - SRT_W::new(self) + pub fn srt(&mut self) -> SRT_W { + SRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/srts.rs b/jh7110-vf2-13b-pac/src/uart1/srts.rs index ceb0ee4..cf1e2a9 100644 --- a/jh7110-vf2-13b-pac/src/uart1/srts.rs +++ b/jh7110-vf2-13b-pac/src/uart1/srts.rs @@ -15,7 +15,7 @@ pub type SRTS_R = crate::BitReader; = 1) and FIFOs enable (FCR\\[0\\] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR\\[4\\] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] -pub type SRTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SRTS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Request to Send. This is a shadow register for the RTS bit (MCR\\[1\\]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] = 0), the rts_n signal is set low by programming MCR\\[1\\] @@ -37,10 +37,14 @@ impl W { = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn srts(&mut self) -> SRTS_W { - SRTS_W::new(self) + pub fn srts(&mut self) -> SRTS_W { + SRTS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/stet.rs b/jh7110-vf2-13b-pac/src/uart1/stet.rs index acb8ba1..503dc8a 100644 --- a/jh7110-vf2-13b-pac/src/uart1/stet.rs +++ b/jh7110-vf2-13b-pac/src/uart1/stet.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `stet` reader - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] pub type STET_R = crate::FieldReader; #[doc = "Field `stet` writer - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type STET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type STET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn stet(&mut self) -> STET_W { - STET_W::new(self) + pub fn stet(&mut self) -> STET_W { + STET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sthr0.rs b/jh7110-vf2-13b-pac/src/uart1/sthr0.rs index bfd277a..764ff05 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sthr0.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sthr0.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sthr1.rs b/jh7110-vf2-13b-pac/src/uart1/sthr1.rs index cc79733..5d58855 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sthr1.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sthr1.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sthr10.rs b/jh7110-vf2-13b-pac/src/uart1/sthr10.rs index be2659d..ffc38ff 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sthr10.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sthr10.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sthr11.rs b/jh7110-vf2-13b-pac/src/uart1/sthr11.rs index 8613dd5..1f8147f 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sthr11.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sthr11.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sthr12.rs b/jh7110-vf2-13b-pac/src/uart1/sthr12.rs index b354b10..7d816f3 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sthr12.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sthr12.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sthr13.rs b/jh7110-vf2-13b-pac/src/uart1/sthr13.rs index 06df4bc..9283b6a 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sthr13.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sthr13.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sthr14.rs b/jh7110-vf2-13b-pac/src/uart1/sthr14.rs index e181dd0..2daf622 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sthr14.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sthr14.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sthr15.rs b/jh7110-vf2-13b-pac/src/uart1/sthr15.rs index 4825778..f70715e 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sthr15.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sthr15.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sthr2.rs b/jh7110-vf2-13b-pac/src/uart1/sthr2.rs index d390f10..f1a9c77 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sthr2.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sthr2.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sthr3.rs b/jh7110-vf2-13b-pac/src/uart1/sthr3.rs index a74fdf0..06aab9e 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sthr3.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sthr3.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sthr4.rs b/jh7110-vf2-13b-pac/src/uart1/sthr4.rs index 1ee6b87..f6e7944 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sthr4.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sthr4.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sthr5.rs b/jh7110-vf2-13b-pac/src/uart1/sthr5.rs index ca360fe..7873a53 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sthr5.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sthr5.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sthr6.rs b/jh7110-vf2-13b-pac/src/uart1/sthr6.rs index 18e6fac..87c81df 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sthr6.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sthr6.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sthr7.rs b/jh7110-vf2-13b-pac/src/uart1/sthr7.rs index 27072a3..9928b3d 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sthr7.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sthr7.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sthr8.rs b/jh7110-vf2-13b-pac/src/uart1/sthr8.rs index 15060b8..565cb1d 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sthr8.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sthr8.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/sthr9.rs b/jh7110-vf2-13b-pac/src/uart1/sthr9.rs index 58af642..e64fece 100644 --- a/jh7110-vf2-13b-pac/src/uart1/sthr9.rs +++ b/jh7110-vf2-13b-pac/src/uart1/sthr9.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/tfl.rs b/jh7110-vf2-13b-pac/src/uart1/tfl.rs index e1faba6..db09fe3 100644 --- a/jh7110-vf2-13b-pac/src/uart1/tfl.rs +++ b/jh7110-vf2-13b-pac/src/uart1/tfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/tfr.rs b/jh7110-vf2-13b-pac/src/uart1/tfr.rs index 8e9ad91..714deff 100644 --- a/jh7110-vf2-13b-pac/src/uart1/tfr.rs +++ b/jh7110-vf2-13b-pac/src/uart1/tfr.rs @@ -14,7 +14,11 @@ is set to one). When FIFOs are implemented and enabled, reading this register gi } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/thr.rs b/jh7110-vf2-13b-pac/src/uart1/thr.rs index f910bd8..7845232 100644 --- a/jh7110-vf2-13b-pac/src/uart1/thr.rs +++ b/jh7110-vf2-13b-pac/src/uart1/thr.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `thr` writer - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type THR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type THR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn thr(&mut self) -> THR_W { - THR_W::new(self) + pub fn thr(&mut self) -> THR_W { + THR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/ucv.rs b/jh7110-vf2-13b-pac/src/uart1/ucv.rs index 8a3be91..6497a08 100644 --- a/jh7110-vf2-13b-pac/src/uart1/ucv.rs +++ b/jh7110-vf2-13b-pac/src/uart1/ucv.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart1/usr.rs b/jh7110-vf2-13b-pac/src/uart1/usr.rs index 445a085..b96417d 100644 --- a/jh7110-vf2-13b-pac/src/uart1/usr.rs +++ b/jh7110-vf2-13b-pac/src/uart1/usr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2.rs b/jh7110-vf2-13b-pac/src/uart2.rs index c462fbf..8a5f089 100644 --- a/jh7110-vf2-13b-pac/src/uart2.rs +++ b/jh7110-vf2-13b-pac/src/uart2.rs @@ -4,20 +4,13 @@ pub struct RegisterBlock { _reserved_0_dll: [u8; 0x04], _reserved_1_dlh: [u8; 0x04], _reserved_2_fcr: [u8; 0x04], - #[doc = "0x0c - Line Control Register"] - pub lcr: LCR, - #[doc = "0x10 - Modem Control Register"] - pub mcr: MCR, - #[doc = "0x14 - Line Status Register"] - pub lsr: LSR, - #[doc = "0x18 - Line Status Register"] - pub msr: MSR, - #[doc = "0x1c - Scratch Pad Register"] - pub scr: SCR, - #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdll: LPDLL, - #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdlh: LPDLH, + lcr: LCR, + mcr: MCR, + lsr: LSR, + msr: MSR, + scr: SCR, + lpdll: LPDLL, + lpdlh: LPDLH, _reserved10: [u8; 0x08], _reserved_10_srbr0: [u8; 0x04], _reserved_11_srbr1: [u8; 0x04], @@ -35,564 +28,663 @@ pub struct RegisterBlock { _reserved_23_srbr13: [u8; 0x04], _reserved_24_srbr14: [u8; 0x04], _reserved_25_srbr15: [u8; 0x04], - #[doc = "0x70 - FIFO Access Register"] - pub far: FAR, - #[doc = "0x74 - Transmit FIFO Read"] - pub tfr: TFR, - #[doc = "0x78 - Receive FIFO Write"] - pub rfw: RFW, - #[doc = "0x7c - UART Status Register"] - pub usr: USR, - #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub tfl: TFL, - #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub rfl: RFL, - #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srr: SRR, - #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srts: SRTS, - #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sbcr: SBCR, - #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sdmam: SDMAM, - #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sfe: SFE, - #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srt: SRT, - #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub stet: STET, - #[doc = "0xa4 - Halt TX"] - pub htx: HTX, - #[doc = "0xa8 - DMA Software Acknowledge"] - pub dmasa: DMASA, + far: FAR, + tfr: TFR, + rfw: RFW, + usr: USR, + tfl: TFL, + rfl: RFL, + srr: SRR, + srts: SRTS, + sbcr: SBCR, + sdmam: SDMAM, + sfe: SFE, + srt: SRT, + stet: STET, + htx: HTX, + dmasa: DMASA, _reserved41: [u8; 0x48], - #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] - pub cpr: CPR, + cpr: CPR, _reserved_42_ctr: [u8; 0x04], } impl RegisterBlock { #[doc = "0x00 - Divisor Latch Low"] #[inline(always)] pub const fn dll(&self) -> &DLL { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Transmit Holding Register"] #[inline(always)] pub const fn thr(&self) -> &THR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Receive Buffer Register"] #[inline(always)] pub const fn rbr(&self) -> &RBR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x04 - Interrupt Enable Register"] #[inline(always)] pub const fn ier(&self) -> &IER { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x04 - Divisor Latch High"] #[inline(always)] pub const fn dlh(&self) -> &DLH { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x08 - FIFO Control Register"] #[inline(always)] pub const fn fcr(&self) -> &FCR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } } #[doc = "0x08 - Interrupt Identity Register"] #[inline(always)] pub const fn iir(&self) -> &IIR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } + } + #[doc = "0x0c - Line Control Register"] + #[inline(always)] + pub const fn lcr(&self) -> &LCR { + &self.lcr + } + #[doc = "0x10 - Modem Control Register"] + #[inline(always)] + pub const fn mcr(&self) -> &MCR { + &self.mcr + } + #[doc = "0x14 - Line Status Register"] + #[inline(always)] + pub const fn lsr(&self) -> &LSR { + &self.lsr + } + #[doc = "0x18 - Line Status Register"] + #[inline(always)] + pub const fn msr(&self) -> &MSR { + &self.msr + } + #[doc = "0x1c - Scratch Pad Register"] + #[inline(always)] + pub const fn scr(&self) -> &SCR { + &self.scr + } + #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdll(&self) -> &LPDLL { + &self.lpdll + } + #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdlh(&self) -> &LPDLH { + &self.lpdlh } #[doc = "0x30 - Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr0(&self) -> &STHR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x30 - Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr0(&self) -> &SRBR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x34 - Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr1(&self) -> &STHR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x34 - Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr1(&self) -> &SRBR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x38 - Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr2(&self) -> &STHR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x38 - Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr2(&self) -> &SRBR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x3c - Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr3(&self) -> &STHR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x3c - Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr3(&self) -> &SRBR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x40 - Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr4(&self) -> &STHR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x40 - Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr4(&self) -> &SRBR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x44 - Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr5(&self) -> &STHR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x44 - Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr5(&self) -> &SRBR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x48 - Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr6(&self) -> &STHR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x48 - Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr6(&self) -> &SRBR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x4c - Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr7(&self) -> &STHR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x4c - Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr7(&self) -> &SRBR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x50 - Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr8(&self) -> &STHR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x50 - Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr8(&self) -> &SRBR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x54 - Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr9(&self) -> &STHR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x54 - Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr9(&self) -> &SRBR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x58 - Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr10(&self) -> &STHR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x58 - Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr10(&self) -> &SRBR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x5c - Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr11(&self) -> &STHR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x5c - Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr11(&self) -> &SRBR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x60 - Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr12(&self) -> &STHR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x60 - Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr12(&self) -> &SRBR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x64 - Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr13(&self) -> &STHR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x64 - Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr13(&self) -> &SRBR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x68 - Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr14(&self) -> &STHR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x68 - Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr14(&self) -> &SRBR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x6c - Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr15(&self) -> &STHR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } } #[doc = "0x6c - Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr15(&self) -> &SRBR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } + } + #[doc = "0x70 - FIFO Access Register"] + #[inline(always)] + pub const fn far(&self) -> &FAR { + &self.far + } + #[doc = "0x74 - Transmit FIFO Read"] + #[inline(always)] + pub const fn tfr(&self) -> &TFR { + &self.tfr + } + #[doc = "0x78 - Receive FIFO Write"] + #[inline(always)] + pub const fn rfw(&self) -> &RFW { + &self.rfw + } + #[doc = "0x7c - UART Status Register"] + #[inline(always)] + pub const fn usr(&self) -> &USR { + &self.usr + } + #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn tfl(&self) -> &TFL { + &self.tfl + } + #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn rfl(&self) -> &RFL { + &self.rfl + } + #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srr(&self) -> &SRR { + &self.srr + } + #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srts(&self) -> &SRTS { + &self.srts + } + #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sbcr(&self) -> &SBCR { + &self.sbcr + } + #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sdmam(&self) -> &SDMAM { + &self.sdmam + } + #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sfe(&self) -> &SFE { + &self.sfe + } + #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srt(&self) -> &SRT { + &self.srt + } + #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn stet(&self) -> &STET { + &self.stet + } + #[doc = "0xa4 - Halt TX"] + #[inline(always)] + pub const fn htx(&self) -> &HTX { + &self.htx + } + #[doc = "0xa8 - DMA Software Acknowledge"] + #[inline(always)] + pub const fn dmasa(&self) -> &DMASA { + &self.dmasa + } + #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn cpr(&self) -> &CPR { + &self.cpr } #[doc = "0xf8 - Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ctr(&self) -> &CTR { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } #[doc = "0xf8 - UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ucv(&self) -> &UCV { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } } -#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rbr`] +#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbr`] module"] pub type RBR = crate::Reg; #[doc = "Receive Buffer Register"] pub mod rbr; -#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`thr`] +#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thr`] module"] pub type THR = crate::Reg; #[doc = "Transmit Holding Register"] pub mod thr; -#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dll`] +#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll`] module"] pub type DLL = crate::Reg; #[doc = "Divisor Latch Low"] pub mod dll; -#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dlh`] +#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlh`] module"] pub type DLH = crate::Reg; #[doc = "Divisor Latch High"] pub mod dlh; -#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`iir`] +#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] module"] pub type IIR = crate::Reg; #[doc = "Interrupt Identity Register"] pub mod iir; -#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fcr`] +#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"] pub type FCR = crate::Reg; #[doc = "FIFO Control Register"] pub mod fcr; -#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lcr`] +#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] module"] pub type LCR = crate::Reg; #[doc = "Line Control Register"] pub mod lcr; -#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mcr`] +#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] pub type MCR = crate::Reg; #[doc = "Modem Control Register"] pub mod mcr; -#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lsr`] +#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] module"] pub type LSR = crate::Reg; #[doc = "Line Status Register"] pub mod lsr; -#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msr`] +#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"] pub type MSR = crate::Reg; #[doc = "Line Status Register"] pub mod msr; -#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scr`] +#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`] module"] pub type SCR = crate::Reg; #[doc = "Scratch Pad Register"] pub mod scr; -#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdll`] +#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdll`] module"] pub type LPDLL = crate::Reg; #[doc = "Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdll; -#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdlh`] +#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdlh`] module"] pub type LPDLH = crate::Reg; #[doc = "Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdlh; -#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr0`] +#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr0`] module"] pub type SRBR0 = crate::Reg; #[doc = "Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr0; -#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr0`] +#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr0`] module"] pub type STHR0 = crate::Reg; #[doc = "Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr0; -#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr1`] +#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr1`] module"] pub type SRBR1 = crate::Reg; #[doc = "Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr1; -#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr1`] +#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr1`] module"] pub type STHR1 = crate::Reg; #[doc = "Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr1; -#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr2`] +#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr2`] module"] pub type SRBR2 = crate::Reg; #[doc = "Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr2; -#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr2`] +#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr2`] module"] pub type STHR2 = crate::Reg; #[doc = "Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr2; -#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr3`] +#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr3`] module"] pub type SRBR3 = crate::Reg; #[doc = "Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr3; -#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr3`] +#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr3`] module"] pub type STHR3 = crate::Reg; #[doc = "Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr3; -#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr4`] +#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr4`] module"] pub type SRBR4 = crate::Reg; #[doc = "Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr4; -#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr4`] +#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr4`] module"] pub type STHR4 = crate::Reg; #[doc = "Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr4; -#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr5`] +#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr5`] module"] pub type SRBR5 = crate::Reg; #[doc = "Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr5; -#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr5`] +#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr5`] module"] pub type STHR5 = crate::Reg; #[doc = "Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr5; -#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr6`] +#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr6`] module"] pub type SRBR6 = crate::Reg; #[doc = "Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr6; -#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr6`] +#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr6`] module"] pub type STHR6 = crate::Reg; #[doc = "Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr6; -#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr7`] +#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr7`] module"] pub type SRBR7 = crate::Reg; #[doc = "Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr7; -#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr7`] +#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr7`] module"] pub type STHR7 = crate::Reg; #[doc = "Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr7; -#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr8`] +#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr8`] module"] pub type SRBR8 = crate::Reg; #[doc = "Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr8; -#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr8`] +#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr8`] module"] pub type STHR8 = crate::Reg; #[doc = "Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr8; -#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr9`] +#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr9`] module"] pub type SRBR9 = crate::Reg; #[doc = "Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr9; -#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr9`] +#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr9`] module"] pub type STHR9 = crate::Reg; #[doc = "Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr9; -#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr10`] +#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr10`] module"] pub type SRBR10 = crate::Reg; #[doc = "Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr10; -#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr10`] +#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr10`] module"] pub type STHR10 = crate::Reg; #[doc = "Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr10; -#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr11`] +#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr11`] module"] pub type SRBR11 = crate::Reg; #[doc = "Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr11; -#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr11`] +#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr11`] module"] pub type STHR11 = crate::Reg; #[doc = "Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr11; -#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr12`] +#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr12`] module"] pub type SRBR12 = crate::Reg; #[doc = "Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr12; -#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr12`] +#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr12`] module"] pub type STHR12 = crate::Reg; #[doc = "Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr12; -#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr13`] +#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr13`] module"] pub type SRBR13 = crate::Reg; #[doc = "Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr13; -#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr13`] +#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr13`] module"] pub type STHR13 = crate::Reg; #[doc = "Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr13; -#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr14`] +#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr14`] module"] pub type SRBR14 = crate::Reg; #[doc = "Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr14; -#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr14`] +#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr14`] module"] pub type STHR14 = crate::Reg; #[doc = "Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr14; -#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr15`] +#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr15`] module"] pub type SRBR15 = crate::Reg; #[doc = "Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr15; -#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr15`] +#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr15`] module"] pub type STHR15 = crate::Reg; #[doc = "Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr15; -#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`far`] +#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@far`] module"] pub type FAR = crate::Reg; #[doc = "FIFO Access Register"] pub mod far; -#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfr`] +#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfr`] module"] pub type TFR = crate::Reg; #[doc = "Transmit FIFO Read"] pub mod tfr; -#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfw`] +#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfw`] module"] pub type RFW = crate::Reg; #[doc = "Receive FIFO Write"] pub mod rfw; -#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`usr`] +#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usr`] module"] pub type USR = crate::Reg; #[doc = "UART Status Register"] pub mod usr; -#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfl`] +#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfl`] module"] pub type TFL = crate::Reg; #[doc = "Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod tfl; -#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfl`] +#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfl`] module"] pub type RFL = crate::Reg; #[doc = "Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod rfl; -#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srr`] +#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srr`] module"] pub type SRR = crate::Reg; #[doc = "Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srr; -#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srts`] +#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srts`] module"] pub type SRTS = crate::Reg; #[doc = "Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srts; -#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sbcr`] +#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sbcr`] module"] pub type SBCR = crate::Reg; #[doc = "Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sbcr; -#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sdmam`] +#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdmam`] module"] pub type SDMAM = crate::Reg; #[doc = "Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sdmam; -#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sfe`] +#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfe`] module"] pub type SFE = crate::Reg; #[doc = "Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sfe; -#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srt`] +#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srt`] module"] pub type SRT = crate::Reg; #[doc = "Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srt; -#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stet`] +#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stet`] module"] pub type STET = crate::Reg; #[doc = "Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod stet; -#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`htx`] +#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@htx`] module"] pub type HTX = crate::Reg; #[doc = "Halt TX"] pub mod htx; -#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dmasa`] +#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasa`] module"] pub type DMASA = crate::Reg; #[doc = "DMA Software Acknowledge"] pub mod dmasa; -#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cpr`] +#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpr`] module"] pub type CPR = crate::Reg; #[doc = "Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] pub mod cpr; -#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ucv`] +#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucv`] module"] pub type UCV = crate::Reg; #[doc = "UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] pub mod ucv; -#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctr`] +#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"] pub type CTR = crate::Reg; #[doc = "Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] diff --git a/jh7110-vf2-13b-pac/src/uart2/cpr.rs b/jh7110-vf2-13b-pac/src/uart2/cpr.rs index 4807519..332b584 100644 --- a/jh7110-vf2-13b-pac/src/uart2/cpr.rs +++ b/jh7110-vf2-13b-pac/src/uart2/cpr.rs @@ -89,7 +89,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/ctr.rs b/jh7110-vf2-13b-pac/src/uart2/ctr.rs index c3760d5..ac70194 100644 --- a/jh7110-vf2-13b-pac/src/uart2/ctr.rs +++ b/jh7110-vf2-13b-pac/src/uart2/ctr.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/dlh.rs b/jh7110-vf2-13b-pac/src/uart2/dlh.rs index 3257a2d..2a788c1 100644 --- a/jh7110-vf2-13b-pac/src/uart2/dlh.rs +++ b/jh7110-vf2-13b-pac/src/uart2/dlh.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLH_R = crate::FieldReader; #[doc = "Field `dlh` writer - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dlh(&mut self) -> DLH_W { - DLH_W::new(self) + pub fn dlh(&mut self) -> DLH_W { + DLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/dll.rs b/jh7110-vf2-13b-pac/src/uart2/dll.rs index 9c9daff..1c9d765 100644 --- a/jh7110-vf2-13b-pac/src/uart2/dll.rs +++ b/jh7110-vf2-13b-pac/src/uart2/dll.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLL_R = crate::FieldReader; #[doc = "Field `dll` writer - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dll(&mut self) -> DLL_W { - DLL_W::new(self) + pub fn dll(&mut self) -> DLL_W { + DLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/dmasa.rs b/jh7110-vf2-13b-pac/src/uart2/dmasa.rs index 7bcfb26..2fc4e6d 100644 --- a/jh7110-vf2-13b-pac/src/uart2/dmasa.rs +++ b/jh7110-vf2-13b-pac/src/uart2/dmasa.rs @@ -3,15 +3,19 @@ pub type R = crate::R; #[doc = "Register `dmasa` writer"] pub type W = crate::W; #[doc = "Field `dmasa` writer - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type DMASA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMASA_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn dmasa(&mut self) -> DMASA_W { - DMASA_W::new(self) + pub fn dmasa(&mut self) -> DMASA_W { + DMASA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/far.rs b/jh7110-vf2-13b-pac/src/uart2/far.rs index 3b3bcb1..d52059a 100644 --- a/jh7110-vf2-13b-pac/src/uart2/far.rs +++ b/jh7110-vf2-13b-pac/src/uart2/far.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `far` reader - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] pub type FAR_R = crate::BitReader; #[doc = "Field `far` writer - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] -pub type FAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FAR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] #[must_use] - pub fn far(&mut self) -> FAR_W { - FAR_W::new(self) + pub fn far(&mut self) -> FAR_W { + FAR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/fcr.rs b/jh7110-vf2-13b-pac/src/uart2/fcr.rs index 4fbb499..a64a60b 100644 --- a/jh7110-vf2-13b-pac/src/uart2/fcr.rs +++ b/jh7110-vf2-13b-pac/src/uart2/fcr.rs @@ -3,55 +3,59 @@ pub type R = crate::R; #[doc = "Register `fcr` writer"] pub type W = crate::W; #[doc = "Field `fifoe` writer - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] -pub type FIFOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIFOE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfifor` writer - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfifor` writer - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dmam` writer - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] -pub type DMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMAM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tet` writer - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type TET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `rt` writer - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type RT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type RT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl W { #[doc = "Bit 0 - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] #[inline(always)] #[must_use] - pub fn fifoe(&mut self) -> FIFOE_W { - FIFOE_W::new(self) + pub fn fifoe(&mut self) -> FIFOE_W { + FIFOE_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfifor(&mut self) -> RFIFOR_W { - RFIFOR_W::new(self) + pub fn rfifor(&mut self) -> RFIFOR_W { + RFIFOR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfifor(&mut self) -> XFIFOR_W { - XFIFOR_W::new(self) + pub fn xfifor(&mut self) -> XFIFOR_W { + XFIFOR_W::new(self, 2) } #[doc = "Bit 3 - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn dmam(&mut self) -> DMAM_W { - DMAM_W::new(self) + pub fn dmam(&mut self) -> DMAM_W { + DMAM_W::new(self, 3) } #[doc = "Bits 4:5 - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn tet(&mut self) -> TET_W { - TET_W::new(self) + pub fn tet(&mut self) -> TET_W { + TET_W::new(self, 4) } #[doc = "Bits 6:7 - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn rt(&mut self) -> RT_W { - RT_W::new(self) + pub fn rt(&mut self) -> RT_W { + RT_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/htx.rs b/jh7110-vf2-13b-pac/src/uart2/htx.rs index ad027bd..fc82325 100644 --- a/jh7110-vf2-13b-pac/src/uart2/htx.rs +++ b/jh7110-vf2-13b-pac/src/uart2/htx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `htx` reader - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] pub type HTX_R = crate::BitReader; #[doc = "Field `htx` writer - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] -pub type HTX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HTX_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] #[must_use] - pub fn htx(&mut self) -> HTX_W { - HTX_W::new(self) + pub fn htx(&mut self) -> HTX_W { + HTX_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/ier.rs b/jh7110-vf2-13b-pac/src/uart2/ier.rs index 006fbea..3cf3d7f 100644 --- a/jh7110-vf2-13b-pac/src/uart2/ier.rs +++ b/jh7110-vf2-13b-pac/src/uart2/ier.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `erbfi` reader - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] pub type ERBFI_R = crate::BitReader; #[doc = "Field `erbfi` writer - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] -pub type ERBFI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ERBFI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `etbei` reader - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] pub type ETBEI_R = crate::BitReader; #[doc = "Field `etbei` writer - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ETBEI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ETBEI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `elsi` reader - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] pub type ELSI_R = crate::BitReader; #[doc = "Field `elsi` writer - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ELSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ELSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `edssi` reader - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] pub type EDSSI_R = crate::BitReader; #[doc = "Field `edssi` writer - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] -pub type EDSSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EDSSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ptime` reader - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] pub type PTIME_R = crate::BitReader; #[doc = "Field `ptime` writer - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] -pub type PTIME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PTIME_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn erbfi(&mut self) -> ERBFI_W { - ERBFI_W::new(self) + pub fn erbfi(&mut self) -> ERBFI_W { + ERBFI_W::new(self, 0) } #[doc = "Bit 1 - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn etbei(&mut self) -> ETBEI_W { - ETBEI_W::new(self) + pub fn etbei(&mut self) -> ETBEI_W { + ETBEI_W::new(self, 1) } #[doc = "Bit 2 - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn elsi(&mut self) -> ELSI_W { - ELSI_W::new(self) + pub fn elsi(&mut self) -> ELSI_W { + ELSI_W::new(self, 2) } #[doc = "Bit 3 - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn edssi(&mut self) -> EDSSI_W { - EDSSI_W::new(self) + pub fn edssi(&mut self) -> EDSSI_W { + EDSSI_W::new(self, 3) } #[doc = "Bit 7 - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn ptime(&mut self) -> PTIME_W { - PTIME_W::new(self) + pub fn ptime(&mut self) -> PTIME_W { + PTIME_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/iir.rs b/jh7110-vf2-13b-pac/src/uart2/iir.rs index c90daa5..c949f03 100644 --- a/jh7110-vf2-13b-pac/src/uart2/iir.rs +++ b/jh7110-vf2-13b-pac/src/uart2/iir.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/lcr.rs b/jh7110-vf2-13b-pac/src/uart2/lcr.rs index acd83ee..3bc10c2 100644 --- a/jh7110-vf2-13b-pac/src/uart2/lcr.rs +++ b/jh7110-vf2-13b-pac/src/uart2/lcr.rs @@ -7,7 +7,7 @@ is zero), always readable. This is used to select the number of data bits per ch pub type DLS_R = crate::FieldReader; #[doc = "Field `dls` writer - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] -pub type DLS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DLS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `stop` reader - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] @@ -15,31 +15,31 @@ pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pen` reader - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] pub type PEN_R = crate::BitReader; #[doc = "Field `pen` writer - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] -pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `eps` reader - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] pub type EPS_R = crate::BitReader; #[doc = "Field `eps` writer - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] -pub type EPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EPS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bc` reader - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] pub type BC_R = crate::BitReader; #[doc = "Field `bc` writer - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] -pub type BC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dlab` reader - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] pub type DLAB_R = crate::BitReader; #[doc = "Field `dlab` writer - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] -pub type DLAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DLAB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:1 - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] @@ -84,46 +84,50 @@ impl W { is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] #[inline(always)] #[must_use] - pub fn dls(&mut self) -> DLS_W { - DLS_W::new(self) + pub fn dls(&mut self) -> DLS_W { + DLS_W::new(self, 0) } #[doc = "Bit 2 - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 2) } #[doc = "Bit 3 - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W { - PEN_W::new(self) + pub fn pen(&mut self) -> PEN_W { + PEN_W::new(self, 3) } #[doc = "Bit 4 - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] #[inline(always)] #[must_use] - pub fn eps(&mut self) -> EPS_W { - EPS_W::new(self) + pub fn eps(&mut self) -> EPS_W { + EPS_W::new(self, 4) } #[doc = "Bit 6 - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] #[inline(always)] #[must_use] - pub fn bc(&mut self) -> BC_W { - BC_W::new(self) + pub fn bc(&mut self) -> BC_W { + BC_W::new(self, 6) } #[doc = "Bit 7 - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] #[inline(always)] #[must_use] - pub fn dlab(&mut self) -> DLAB_W { - DLAB_W::new(self) + pub fn dlab(&mut self) -> DLAB_W { + DLAB_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/lpdlh.rs b/jh7110-vf2-13b-pac/src/uart2/lpdlh.rs index 8a910c8..095afa9 100644 --- a/jh7110-vf2-13b-pac/src/uart2/lpdlh.rs +++ b/jh7110-vf2-13b-pac/src/uart2/lpdlh.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdlh` reader - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] pub type LPDLH_R = crate::FieldReader; #[doc = "Field `lpdlh` writer - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] -pub type LPDLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] #[must_use] - pub fn lpdlh(&mut self) -> LPDLH_W { - LPDLH_W::new(self) + pub fn lpdlh(&mut self) -> LPDLH_W { + LPDLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/lpdll.rs b/jh7110-vf2-13b-pac/src/uart2/lpdll.rs index 7780651..21d0018 100644 --- a/jh7110-vf2-13b-pac/src/uart2/lpdll.rs +++ b/jh7110-vf2-13b-pac/src/uart2/lpdll.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdll` reader - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] pub type LPDLL_R = crate::FieldReader; #[doc = "Field `lpdll` writer - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type LPDLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn lpdll(&mut self) -> LPDLL_W { - LPDLL_W::new(self) + pub fn lpdll(&mut self) -> LPDLL_W { + LPDLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/lsr.rs b/jh7110-vf2-13b-pac/src/uart2/lsr.rs index f576c10..ff2ab48 100644 --- a/jh7110-vf2-13b-pac/src/uart2/lsr.rs +++ b/jh7110-vf2-13b-pac/src/uart2/lsr.rs @@ -73,7 +73,11 @@ set to one). This is used to indicate if there is at least one parity error, fra } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/mcr.rs b/jh7110-vf2-13b-pac/src/uart2/mcr.rs index 6932ee7..9c93108 100644 --- a/jh7110-vf2-13b-pac/src/uart2/mcr.rs +++ b/jh7110-vf2-13b-pac/src/uart2/mcr.rs @@ -7,7 +7,7 @@ set to one), the dtr_n output is held inactive high while the value of this loca pub type DTR_R = crate::BitReader; #[doc = "Field `dtr` writer - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type DTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rts` reader - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR\\[5\\] @@ -23,19 +23,19 @@ set to one) and FIFOs enable (FCR\\[0\\] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR\\[1\\] is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out1` reader - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT1_R = crate::BitReader; #[doc = "Field `out1` writer - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out2` reader - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT2_R = crate::BitReader; #[doc = "Field `out2` writer - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `lb` reader - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] @@ -43,15 +43,15 @@ pub type LB_R = crate::BitReader; #[doc = "Field `lb` writer - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] -pub type LB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `afce` reader - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] pub type AFCE_R = crate::BitReader; #[doc = "Field `afce` writer - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] -pub type AFCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AFCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sire` reader - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] pub type SIRE_R = crate::BitReader; #[doc = "Field `sire` writer - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] -pub type SIRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SIRE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] @@ -105,8 +105,8 @@ impl W { set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn dtr(&mut self) -> DTR_W { - DTR_W::new(self) + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 0) } #[doc = "Bit 1 - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] @@ -117,44 +117,48 @@ is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W { - RTS_W::new(self) + pub fn rts(&mut self) -> RTS_W { + RTS_W::new(self, 1) } #[doc = "Bit 2 - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out1(&mut self) -> OUT1_W { - OUT1_W::new(self) + pub fn out1(&mut self) -> OUT1_W { + OUT1_W::new(self, 2) } #[doc = "Bit 3 - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out2(&mut self) -> OUT2_W { - OUT2_W::new(self) + pub fn out2(&mut self) -> OUT2_W { + OUT2_W::new(self, 3) } #[doc = "Bit 4 - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] #[inline(always)] #[must_use] - pub fn lb(&mut self) -> LB_W { - LB_W::new(self) + pub fn lb(&mut self) -> LB_W { + LB_W::new(self, 4) } #[doc = "Bit 5 - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] #[inline(always)] #[must_use] - pub fn afce(&mut self) -> AFCE_W { - AFCE_W::new(self) + pub fn afce(&mut self) -> AFCE_W { + AFCE_W::new(self, 5) } #[doc = "Bit 6 - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] #[inline(always)] #[must_use] - pub fn sire(&mut self) -> SIRE_W { - SIRE_W::new(self) + pub fn sire(&mut self) -> SIRE_W { + SIRE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/msr.rs b/jh7110-vf2-13b-pac/src/uart2/msr.rs index 65c526b..b54fc38 100644 --- a/jh7110-vf2-13b-pac/src/uart2/msr.rs +++ b/jh7110-vf2-13b-pac/src/uart2/msr.rs @@ -93,7 +93,11 @@ set to one), DCD is the same as MCR\\[3\\] } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/rbr.rs b/jh7110-vf2-13b-pac/src/uart2/rbr.rs index 03003ed..403adcf 100644 --- a/jh7110-vf2-13b-pac/src/uart2/rbr.rs +++ b/jh7110-vf2-13b-pac/src/uart2/rbr.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/rfl.rs b/jh7110-vf2-13b-pac/src/uart2/rfl.rs index 2aea928..59355cb 100644 --- a/jh7110-vf2-13b-pac/src/uart2/rfl.rs +++ b/jh7110-vf2-13b-pac/src/uart2/rfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/rfw.rs b/jh7110-vf2-13b-pac/src/uart2/rfw.rs index 7b917de..490472d 100644 --- a/jh7110-vf2-13b-pac/src/uart2/rfw.rs +++ b/jh7110-vf2-13b-pac/src/uart2/rfw.rs @@ -4,36 +4,40 @@ pub type R = crate::R; pub type W = crate::W; #[doc = "Field `rfwd` writer - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] -pub type RFWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type RFWD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `rfpe` writer - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] -pub type RFPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFPE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rffe` writer - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] -pub type RFFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bits 0:7 - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] #[inline(always)] #[must_use] - pub fn rfwd(&mut self) -> RFWD_W { - RFWD_W::new(self) + pub fn rfwd(&mut self) -> RFWD_W { + RFWD_W::new(self, 0) } #[doc = "Bit 8 - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rfpe(&mut self) -> RFPE_W { - RFPE_W::new(self) + pub fn rfpe(&mut self) -> RFPE_W { + RFPE_W::new(self, 8) } #[doc = "Bit 9 - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rffe(&mut self) -> RFFE_W { - RFFE_W::new(self) + pub fn rffe(&mut self) -> RFFE_W { + RFFE_W::new(self, 9) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sbcr.rs b/jh7110-vf2-13b-pac/src/uart2/sbcr.rs index 73914e9..5a120c0 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sbcr.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sbcr.rs @@ -7,7 +7,7 @@ pub type W = crate::W; pub type SBCR_R = crate::BitReader; #[doc = "Field `sbcr` writer - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] -pub type SBCR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SBCR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] @@ -21,10 +21,14 @@ impl W { = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] #[inline(always)] #[must_use] - pub fn sbcr(&mut self) -> SBCR_W { - SBCR_W::new(self) + pub fn sbcr(&mut self) -> SBCR_W { + SBCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/scr.rs b/jh7110-vf2-13b-pac/src/uart2/scr.rs index 744352e..f46ba21 100644 --- a/jh7110-vf2-13b-pac/src/uart2/scr.rs +++ b/jh7110-vf2-13b-pac/src/uart2/scr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `scr` reader - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sdmam.rs b/jh7110-vf2-13b-pac/src/uart2/sdmam.rs index 684377c..4be4fa2 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sdmam.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sdmam.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sdmam` reader - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] pub type SDMAM_R = crate::BitReader; #[doc = "Field `sdmam` writer - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] -pub type SDMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SDMAM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn sdmam(&mut self) -> SDMAM_W { - SDMAM_W::new(self) + pub fn sdmam(&mut self) -> SDMAM_W { + SDMAM_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sfe.rs b/jh7110-vf2-13b-pac/src/uart2/sfe.rs index e68b088..ed26fee 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sfe.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sfe.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sfe` reader - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] pub type SFE_R = crate::BitReader; #[doc = "Field `sfe` writer - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] -pub type SFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] #[must_use] - pub fn sfe(&mut self) -> SFE_W { - SFE_W::new(self) + pub fn sfe(&mut self) -> SFE_W { + SFE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srbr0.rs b/jh7110-vf2-13b-pac/src/uart2/srbr0.rs index 4076661..4e44d1a 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srbr0.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srbr0.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srbr1.rs b/jh7110-vf2-13b-pac/src/uart2/srbr1.rs index 2f31b75..46bc479 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srbr1.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srbr1.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srbr10.rs b/jh7110-vf2-13b-pac/src/uart2/srbr10.rs index 3639d65..70297bf 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srbr10.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srbr10.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srbr11.rs b/jh7110-vf2-13b-pac/src/uart2/srbr11.rs index 92d29b1..28d0277 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srbr11.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srbr11.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srbr12.rs b/jh7110-vf2-13b-pac/src/uart2/srbr12.rs index 52e795e..3eccd9a 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srbr12.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srbr12.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srbr13.rs b/jh7110-vf2-13b-pac/src/uart2/srbr13.rs index 50aae40..e47e4e4 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srbr13.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srbr13.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srbr14.rs b/jh7110-vf2-13b-pac/src/uart2/srbr14.rs index cb25819..8f23662 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srbr14.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srbr14.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srbr15.rs b/jh7110-vf2-13b-pac/src/uart2/srbr15.rs index b25ae46..1dac092 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srbr15.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srbr15.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srbr2.rs b/jh7110-vf2-13b-pac/src/uart2/srbr2.rs index 9f3236c..afb0617 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srbr2.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srbr2.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srbr3.rs b/jh7110-vf2-13b-pac/src/uart2/srbr3.rs index 5c1edda..0ff3650 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srbr3.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srbr3.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srbr4.rs b/jh7110-vf2-13b-pac/src/uart2/srbr4.rs index e6bee93..59560c4 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srbr4.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srbr4.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srbr5.rs b/jh7110-vf2-13b-pac/src/uart2/srbr5.rs index e599009..763e341 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srbr5.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srbr5.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srbr6.rs b/jh7110-vf2-13b-pac/src/uart2/srbr6.rs index b0155b3..78e2a40 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srbr6.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srbr6.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srbr7.rs b/jh7110-vf2-13b-pac/src/uart2/srbr7.rs index b8f9b88..0723ff0 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srbr7.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srbr7.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srbr8.rs b/jh7110-vf2-13b-pac/src/uart2/srbr8.rs index f57b044..4702cd9 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srbr8.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srbr8.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srbr9.rs b/jh7110-vf2-13b-pac/src/uart2/srbr9.rs index 3a160aa..e1a262e 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srbr9.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srbr9.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srr.rs b/jh7110-vf2-13b-pac/src/uart2/srr.rs index 6671199..fdb0c0a 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srr.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srr.rs @@ -3,31 +3,35 @@ pub type R = crate::R; #[doc = "Register `srr` writer"] pub type W = crate::W; #[doc = "Field `ur` writer - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] -pub type UR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type UR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfr` writer - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfr` writer - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFR_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] #[inline(always)] #[must_use] - pub fn ur(&mut self) -> UR_W { - UR_W::new(self) + pub fn ur(&mut self) -> UR_W { + UR_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfr(&mut self) -> RFR_W { - RFR_W::new(self) + pub fn rfr(&mut self) -> RFR_W { + RFR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfr(&mut self) -> XFR_W { - XFR_W::new(self) + pub fn xfr(&mut self) -> XFR_W { + XFR_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srt.rs b/jh7110-vf2-13b-pac/src/uart2/srt.rs index fed4f1f..da909fd 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srt.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `srt` reader - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] pub type SRT_R = crate::FieldReader; #[doc = "Field `srt` writer - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type SRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SRT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn srt(&mut self) -> SRT_W { - SRT_W::new(self) + pub fn srt(&mut self) -> SRT_W { + SRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/srts.rs b/jh7110-vf2-13b-pac/src/uart2/srts.rs index ceb0ee4..cf1e2a9 100644 --- a/jh7110-vf2-13b-pac/src/uart2/srts.rs +++ b/jh7110-vf2-13b-pac/src/uart2/srts.rs @@ -15,7 +15,7 @@ pub type SRTS_R = crate::BitReader; = 1) and FIFOs enable (FCR\\[0\\] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR\\[4\\] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] -pub type SRTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SRTS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Request to Send. This is a shadow register for the RTS bit (MCR\\[1\\]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] = 0), the rts_n signal is set low by programming MCR\\[1\\] @@ -37,10 +37,14 @@ impl W { = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn srts(&mut self) -> SRTS_W { - SRTS_W::new(self) + pub fn srts(&mut self) -> SRTS_W { + SRTS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/stet.rs b/jh7110-vf2-13b-pac/src/uart2/stet.rs index acb8ba1..503dc8a 100644 --- a/jh7110-vf2-13b-pac/src/uart2/stet.rs +++ b/jh7110-vf2-13b-pac/src/uart2/stet.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `stet` reader - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] pub type STET_R = crate::FieldReader; #[doc = "Field `stet` writer - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type STET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type STET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn stet(&mut self) -> STET_W { - STET_W::new(self) + pub fn stet(&mut self) -> STET_W { + STET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sthr0.rs b/jh7110-vf2-13b-pac/src/uart2/sthr0.rs index bfd277a..764ff05 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sthr0.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sthr0.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sthr1.rs b/jh7110-vf2-13b-pac/src/uart2/sthr1.rs index cc79733..5d58855 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sthr1.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sthr1.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sthr10.rs b/jh7110-vf2-13b-pac/src/uart2/sthr10.rs index be2659d..ffc38ff 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sthr10.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sthr10.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sthr11.rs b/jh7110-vf2-13b-pac/src/uart2/sthr11.rs index 8613dd5..1f8147f 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sthr11.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sthr11.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sthr12.rs b/jh7110-vf2-13b-pac/src/uart2/sthr12.rs index b354b10..7d816f3 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sthr12.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sthr12.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sthr13.rs b/jh7110-vf2-13b-pac/src/uart2/sthr13.rs index 06df4bc..9283b6a 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sthr13.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sthr13.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sthr14.rs b/jh7110-vf2-13b-pac/src/uart2/sthr14.rs index e181dd0..2daf622 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sthr14.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sthr14.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sthr15.rs b/jh7110-vf2-13b-pac/src/uart2/sthr15.rs index 4825778..f70715e 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sthr15.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sthr15.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sthr2.rs b/jh7110-vf2-13b-pac/src/uart2/sthr2.rs index d390f10..f1a9c77 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sthr2.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sthr2.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sthr3.rs b/jh7110-vf2-13b-pac/src/uart2/sthr3.rs index a74fdf0..06aab9e 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sthr3.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sthr3.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sthr4.rs b/jh7110-vf2-13b-pac/src/uart2/sthr4.rs index 1ee6b87..f6e7944 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sthr4.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sthr4.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sthr5.rs b/jh7110-vf2-13b-pac/src/uart2/sthr5.rs index ca360fe..7873a53 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sthr5.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sthr5.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sthr6.rs b/jh7110-vf2-13b-pac/src/uart2/sthr6.rs index 18e6fac..87c81df 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sthr6.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sthr6.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sthr7.rs b/jh7110-vf2-13b-pac/src/uart2/sthr7.rs index 27072a3..9928b3d 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sthr7.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sthr7.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sthr8.rs b/jh7110-vf2-13b-pac/src/uart2/sthr8.rs index 15060b8..565cb1d 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sthr8.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sthr8.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/sthr9.rs b/jh7110-vf2-13b-pac/src/uart2/sthr9.rs index 58af642..e64fece 100644 --- a/jh7110-vf2-13b-pac/src/uart2/sthr9.rs +++ b/jh7110-vf2-13b-pac/src/uart2/sthr9.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/tfl.rs b/jh7110-vf2-13b-pac/src/uart2/tfl.rs index e1faba6..db09fe3 100644 --- a/jh7110-vf2-13b-pac/src/uart2/tfl.rs +++ b/jh7110-vf2-13b-pac/src/uart2/tfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/tfr.rs b/jh7110-vf2-13b-pac/src/uart2/tfr.rs index 8e9ad91..714deff 100644 --- a/jh7110-vf2-13b-pac/src/uart2/tfr.rs +++ b/jh7110-vf2-13b-pac/src/uart2/tfr.rs @@ -14,7 +14,11 @@ is set to one). When FIFOs are implemented and enabled, reading this register gi } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/thr.rs b/jh7110-vf2-13b-pac/src/uart2/thr.rs index f910bd8..7845232 100644 --- a/jh7110-vf2-13b-pac/src/uart2/thr.rs +++ b/jh7110-vf2-13b-pac/src/uart2/thr.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `thr` writer - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type THR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type THR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn thr(&mut self) -> THR_W { - THR_W::new(self) + pub fn thr(&mut self) -> THR_W { + THR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/ucv.rs b/jh7110-vf2-13b-pac/src/uart2/ucv.rs index 8a3be91..6497a08 100644 --- a/jh7110-vf2-13b-pac/src/uart2/ucv.rs +++ b/jh7110-vf2-13b-pac/src/uart2/ucv.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart2/usr.rs b/jh7110-vf2-13b-pac/src/uart2/usr.rs index 445a085..b96417d 100644 --- a/jh7110-vf2-13b-pac/src/uart2/usr.rs +++ b/jh7110-vf2-13b-pac/src/uart2/usr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3.rs b/jh7110-vf2-13b-pac/src/uart3.rs index c462fbf..8a5f089 100644 --- a/jh7110-vf2-13b-pac/src/uart3.rs +++ b/jh7110-vf2-13b-pac/src/uart3.rs @@ -4,20 +4,13 @@ pub struct RegisterBlock { _reserved_0_dll: [u8; 0x04], _reserved_1_dlh: [u8; 0x04], _reserved_2_fcr: [u8; 0x04], - #[doc = "0x0c - Line Control Register"] - pub lcr: LCR, - #[doc = "0x10 - Modem Control Register"] - pub mcr: MCR, - #[doc = "0x14 - Line Status Register"] - pub lsr: LSR, - #[doc = "0x18 - Line Status Register"] - pub msr: MSR, - #[doc = "0x1c - Scratch Pad Register"] - pub scr: SCR, - #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdll: LPDLL, - #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdlh: LPDLH, + lcr: LCR, + mcr: MCR, + lsr: LSR, + msr: MSR, + scr: SCR, + lpdll: LPDLL, + lpdlh: LPDLH, _reserved10: [u8; 0x08], _reserved_10_srbr0: [u8; 0x04], _reserved_11_srbr1: [u8; 0x04], @@ -35,564 +28,663 @@ pub struct RegisterBlock { _reserved_23_srbr13: [u8; 0x04], _reserved_24_srbr14: [u8; 0x04], _reserved_25_srbr15: [u8; 0x04], - #[doc = "0x70 - FIFO Access Register"] - pub far: FAR, - #[doc = "0x74 - Transmit FIFO Read"] - pub tfr: TFR, - #[doc = "0x78 - Receive FIFO Write"] - pub rfw: RFW, - #[doc = "0x7c - UART Status Register"] - pub usr: USR, - #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub tfl: TFL, - #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub rfl: RFL, - #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srr: SRR, - #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srts: SRTS, - #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sbcr: SBCR, - #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sdmam: SDMAM, - #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sfe: SFE, - #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srt: SRT, - #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub stet: STET, - #[doc = "0xa4 - Halt TX"] - pub htx: HTX, - #[doc = "0xa8 - DMA Software Acknowledge"] - pub dmasa: DMASA, + far: FAR, + tfr: TFR, + rfw: RFW, + usr: USR, + tfl: TFL, + rfl: RFL, + srr: SRR, + srts: SRTS, + sbcr: SBCR, + sdmam: SDMAM, + sfe: SFE, + srt: SRT, + stet: STET, + htx: HTX, + dmasa: DMASA, _reserved41: [u8; 0x48], - #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] - pub cpr: CPR, + cpr: CPR, _reserved_42_ctr: [u8; 0x04], } impl RegisterBlock { #[doc = "0x00 - Divisor Latch Low"] #[inline(always)] pub const fn dll(&self) -> &DLL { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Transmit Holding Register"] #[inline(always)] pub const fn thr(&self) -> &THR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Receive Buffer Register"] #[inline(always)] pub const fn rbr(&self) -> &RBR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x04 - Interrupt Enable Register"] #[inline(always)] pub const fn ier(&self) -> &IER { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x04 - Divisor Latch High"] #[inline(always)] pub const fn dlh(&self) -> &DLH { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x08 - FIFO Control Register"] #[inline(always)] pub const fn fcr(&self) -> &FCR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } } #[doc = "0x08 - Interrupt Identity Register"] #[inline(always)] pub const fn iir(&self) -> &IIR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } + } + #[doc = "0x0c - Line Control Register"] + #[inline(always)] + pub const fn lcr(&self) -> &LCR { + &self.lcr + } + #[doc = "0x10 - Modem Control Register"] + #[inline(always)] + pub const fn mcr(&self) -> &MCR { + &self.mcr + } + #[doc = "0x14 - Line Status Register"] + #[inline(always)] + pub const fn lsr(&self) -> &LSR { + &self.lsr + } + #[doc = "0x18 - Line Status Register"] + #[inline(always)] + pub const fn msr(&self) -> &MSR { + &self.msr + } + #[doc = "0x1c - Scratch Pad Register"] + #[inline(always)] + pub const fn scr(&self) -> &SCR { + &self.scr + } + #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdll(&self) -> &LPDLL { + &self.lpdll + } + #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdlh(&self) -> &LPDLH { + &self.lpdlh } #[doc = "0x30 - Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr0(&self) -> &STHR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x30 - Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr0(&self) -> &SRBR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x34 - Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr1(&self) -> &STHR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x34 - Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr1(&self) -> &SRBR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x38 - Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr2(&self) -> &STHR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x38 - Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr2(&self) -> &SRBR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x3c - Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr3(&self) -> &STHR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x3c - Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr3(&self) -> &SRBR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x40 - Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr4(&self) -> &STHR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x40 - Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr4(&self) -> &SRBR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x44 - Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr5(&self) -> &STHR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x44 - Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr5(&self) -> &SRBR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x48 - Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr6(&self) -> &STHR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x48 - Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr6(&self) -> &SRBR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x4c - Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr7(&self) -> &STHR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x4c - Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr7(&self) -> &SRBR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x50 - Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr8(&self) -> &STHR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x50 - Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr8(&self) -> &SRBR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x54 - Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr9(&self) -> &STHR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x54 - Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr9(&self) -> &SRBR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x58 - Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr10(&self) -> &STHR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x58 - Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr10(&self) -> &SRBR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x5c - Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr11(&self) -> &STHR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x5c - Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr11(&self) -> &SRBR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x60 - Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr12(&self) -> &STHR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x60 - Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr12(&self) -> &SRBR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x64 - Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr13(&self) -> &STHR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x64 - Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr13(&self) -> &SRBR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x68 - Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr14(&self) -> &STHR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x68 - Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr14(&self) -> &SRBR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x6c - Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr15(&self) -> &STHR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } } #[doc = "0x6c - Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr15(&self) -> &SRBR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } + } + #[doc = "0x70 - FIFO Access Register"] + #[inline(always)] + pub const fn far(&self) -> &FAR { + &self.far + } + #[doc = "0x74 - Transmit FIFO Read"] + #[inline(always)] + pub const fn tfr(&self) -> &TFR { + &self.tfr + } + #[doc = "0x78 - Receive FIFO Write"] + #[inline(always)] + pub const fn rfw(&self) -> &RFW { + &self.rfw + } + #[doc = "0x7c - UART Status Register"] + #[inline(always)] + pub const fn usr(&self) -> &USR { + &self.usr + } + #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn tfl(&self) -> &TFL { + &self.tfl + } + #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn rfl(&self) -> &RFL { + &self.rfl + } + #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srr(&self) -> &SRR { + &self.srr + } + #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srts(&self) -> &SRTS { + &self.srts + } + #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sbcr(&self) -> &SBCR { + &self.sbcr + } + #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sdmam(&self) -> &SDMAM { + &self.sdmam + } + #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sfe(&self) -> &SFE { + &self.sfe + } + #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srt(&self) -> &SRT { + &self.srt + } + #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn stet(&self) -> &STET { + &self.stet + } + #[doc = "0xa4 - Halt TX"] + #[inline(always)] + pub const fn htx(&self) -> &HTX { + &self.htx + } + #[doc = "0xa8 - DMA Software Acknowledge"] + #[inline(always)] + pub const fn dmasa(&self) -> &DMASA { + &self.dmasa + } + #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn cpr(&self) -> &CPR { + &self.cpr } #[doc = "0xf8 - Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ctr(&self) -> &CTR { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } #[doc = "0xf8 - UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ucv(&self) -> &UCV { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } } -#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rbr`] +#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbr`] module"] pub type RBR = crate::Reg; #[doc = "Receive Buffer Register"] pub mod rbr; -#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`thr`] +#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thr`] module"] pub type THR = crate::Reg; #[doc = "Transmit Holding Register"] pub mod thr; -#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dll`] +#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll`] module"] pub type DLL = crate::Reg; #[doc = "Divisor Latch Low"] pub mod dll; -#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dlh`] +#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlh`] module"] pub type DLH = crate::Reg; #[doc = "Divisor Latch High"] pub mod dlh; -#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`iir`] +#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] module"] pub type IIR = crate::Reg; #[doc = "Interrupt Identity Register"] pub mod iir; -#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fcr`] +#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"] pub type FCR = crate::Reg; #[doc = "FIFO Control Register"] pub mod fcr; -#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lcr`] +#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] module"] pub type LCR = crate::Reg; #[doc = "Line Control Register"] pub mod lcr; -#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mcr`] +#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] pub type MCR = crate::Reg; #[doc = "Modem Control Register"] pub mod mcr; -#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lsr`] +#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] module"] pub type LSR = crate::Reg; #[doc = "Line Status Register"] pub mod lsr; -#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msr`] +#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"] pub type MSR = crate::Reg; #[doc = "Line Status Register"] pub mod msr; -#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scr`] +#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`] module"] pub type SCR = crate::Reg; #[doc = "Scratch Pad Register"] pub mod scr; -#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdll`] +#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdll`] module"] pub type LPDLL = crate::Reg; #[doc = "Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdll; -#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdlh`] +#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdlh`] module"] pub type LPDLH = crate::Reg; #[doc = "Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdlh; -#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr0`] +#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr0`] module"] pub type SRBR0 = crate::Reg; #[doc = "Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr0; -#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr0`] +#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr0`] module"] pub type STHR0 = crate::Reg; #[doc = "Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr0; -#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr1`] +#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr1`] module"] pub type SRBR1 = crate::Reg; #[doc = "Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr1; -#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr1`] +#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr1`] module"] pub type STHR1 = crate::Reg; #[doc = "Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr1; -#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr2`] +#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr2`] module"] pub type SRBR2 = crate::Reg; #[doc = "Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr2; -#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr2`] +#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr2`] module"] pub type STHR2 = crate::Reg; #[doc = "Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr2; -#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr3`] +#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr3`] module"] pub type SRBR3 = crate::Reg; #[doc = "Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr3; -#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr3`] +#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr3`] module"] pub type STHR3 = crate::Reg; #[doc = "Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr3; -#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr4`] +#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr4`] module"] pub type SRBR4 = crate::Reg; #[doc = "Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr4; -#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr4`] +#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr4`] module"] pub type STHR4 = crate::Reg; #[doc = "Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr4; -#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr5`] +#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr5`] module"] pub type SRBR5 = crate::Reg; #[doc = "Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr5; -#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr5`] +#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr5`] module"] pub type STHR5 = crate::Reg; #[doc = "Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr5; -#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr6`] +#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr6`] module"] pub type SRBR6 = crate::Reg; #[doc = "Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr6; -#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr6`] +#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr6`] module"] pub type STHR6 = crate::Reg; #[doc = "Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr6; -#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr7`] +#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr7`] module"] pub type SRBR7 = crate::Reg; #[doc = "Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr7; -#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr7`] +#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr7`] module"] pub type STHR7 = crate::Reg; #[doc = "Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr7; -#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr8`] +#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr8`] module"] pub type SRBR8 = crate::Reg; #[doc = "Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr8; -#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr8`] +#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr8`] module"] pub type STHR8 = crate::Reg; #[doc = "Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr8; -#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr9`] +#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr9`] module"] pub type SRBR9 = crate::Reg; #[doc = "Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr9; -#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr9`] +#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr9`] module"] pub type STHR9 = crate::Reg; #[doc = "Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr9; -#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr10`] +#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr10`] module"] pub type SRBR10 = crate::Reg; #[doc = "Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr10; -#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr10`] +#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr10`] module"] pub type STHR10 = crate::Reg; #[doc = "Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr10; -#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr11`] +#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr11`] module"] pub type SRBR11 = crate::Reg; #[doc = "Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr11; -#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr11`] +#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr11`] module"] pub type STHR11 = crate::Reg; #[doc = "Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr11; -#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr12`] +#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr12`] module"] pub type SRBR12 = crate::Reg; #[doc = "Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr12; -#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr12`] +#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr12`] module"] pub type STHR12 = crate::Reg; #[doc = "Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr12; -#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr13`] +#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr13`] module"] pub type SRBR13 = crate::Reg; #[doc = "Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr13; -#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr13`] +#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr13`] module"] pub type STHR13 = crate::Reg; #[doc = "Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr13; -#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr14`] +#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr14`] module"] pub type SRBR14 = crate::Reg; #[doc = "Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr14; -#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr14`] +#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr14`] module"] pub type STHR14 = crate::Reg; #[doc = "Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr14; -#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr15`] +#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr15`] module"] pub type SRBR15 = crate::Reg; #[doc = "Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr15; -#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr15`] +#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr15`] module"] pub type STHR15 = crate::Reg; #[doc = "Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr15; -#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`far`] +#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@far`] module"] pub type FAR = crate::Reg; #[doc = "FIFO Access Register"] pub mod far; -#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfr`] +#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfr`] module"] pub type TFR = crate::Reg; #[doc = "Transmit FIFO Read"] pub mod tfr; -#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfw`] +#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfw`] module"] pub type RFW = crate::Reg; #[doc = "Receive FIFO Write"] pub mod rfw; -#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`usr`] +#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usr`] module"] pub type USR = crate::Reg; #[doc = "UART Status Register"] pub mod usr; -#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfl`] +#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfl`] module"] pub type TFL = crate::Reg; #[doc = "Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod tfl; -#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfl`] +#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfl`] module"] pub type RFL = crate::Reg; #[doc = "Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod rfl; -#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srr`] +#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srr`] module"] pub type SRR = crate::Reg; #[doc = "Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srr; -#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srts`] +#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srts`] module"] pub type SRTS = crate::Reg; #[doc = "Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srts; -#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sbcr`] +#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sbcr`] module"] pub type SBCR = crate::Reg; #[doc = "Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sbcr; -#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sdmam`] +#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdmam`] module"] pub type SDMAM = crate::Reg; #[doc = "Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sdmam; -#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sfe`] +#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfe`] module"] pub type SFE = crate::Reg; #[doc = "Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sfe; -#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srt`] +#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srt`] module"] pub type SRT = crate::Reg; #[doc = "Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srt; -#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stet`] +#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stet`] module"] pub type STET = crate::Reg; #[doc = "Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod stet; -#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`htx`] +#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@htx`] module"] pub type HTX = crate::Reg; #[doc = "Halt TX"] pub mod htx; -#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dmasa`] +#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasa`] module"] pub type DMASA = crate::Reg; #[doc = "DMA Software Acknowledge"] pub mod dmasa; -#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cpr`] +#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpr`] module"] pub type CPR = crate::Reg; #[doc = "Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] pub mod cpr; -#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ucv`] +#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucv`] module"] pub type UCV = crate::Reg; #[doc = "UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] pub mod ucv; -#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctr`] +#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"] pub type CTR = crate::Reg; #[doc = "Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] diff --git a/jh7110-vf2-13b-pac/src/uart3/cpr.rs b/jh7110-vf2-13b-pac/src/uart3/cpr.rs index 4807519..332b584 100644 --- a/jh7110-vf2-13b-pac/src/uart3/cpr.rs +++ b/jh7110-vf2-13b-pac/src/uart3/cpr.rs @@ -89,7 +89,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/ctr.rs b/jh7110-vf2-13b-pac/src/uart3/ctr.rs index c3760d5..ac70194 100644 --- a/jh7110-vf2-13b-pac/src/uart3/ctr.rs +++ b/jh7110-vf2-13b-pac/src/uart3/ctr.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/dlh.rs b/jh7110-vf2-13b-pac/src/uart3/dlh.rs index 3257a2d..2a788c1 100644 --- a/jh7110-vf2-13b-pac/src/uart3/dlh.rs +++ b/jh7110-vf2-13b-pac/src/uart3/dlh.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLH_R = crate::FieldReader; #[doc = "Field `dlh` writer - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dlh(&mut self) -> DLH_W { - DLH_W::new(self) + pub fn dlh(&mut self) -> DLH_W { + DLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/dll.rs b/jh7110-vf2-13b-pac/src/uart3/dll.rs index 9c9daff..1c9d765 100644 --- a/jh7110-vf2-13b-pac/src/uart3/dll.rs +++ b/jh7110-vf2-13b-pac/src/uart3/dll.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLL_R = crate::FieldReader; #[doc = "Field `dll` writer - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dll(&mut self) -> DLL_W { - DLL_W::new(self) + pub fn dll(&mut self) -> DLL_W { + DLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/dmasa.rs b/jh7110-vf2-13b-pac/src/uart3/dmasa.rs index 7bcfb26..2fc4e6d 100644 --- a/jh7110-vf2-13b-pac/src/uart3/dmasa.rs +++ b/jh7110-vf2-13b-pac/src/uart3/dmasa.rs @@ -3,15 +3,19 @@ pub type R = crate::R; #[doc = "Register `dmasa` writer"] pub type W = crate::W; #[doc = "Field `dmasa` writer - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type DMASA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMASA_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn dmasa(&mut self) -> DMASA_W { - DMASA_W::new(self) + pub fn dmasa(&mut self) -> DMASA_W { + DMASA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/far.rs b/jh7110-vf2-13b-pac/src/uart3/far.rs index 3b3bcb1..d52059a 100644 --- a/jh7110-vf2-13b-pac/src/uart3/far.rs +++ b/jh7110-vf2-13b-pac/src/uart3/far.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `far` reader - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] pub type FAR_R = crate::BitReader; #[doc = "Field `far` writer - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] -pub type FAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FAR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] #[must_use] - pub fn far(&mut self) -> FAR_W { - FAR_W::new(self) + pub fn far(&mut self) -> FAR_W { + FAR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/fcr.rs b/jh7110-vf2-13b-pac/src/uart3/fcr.rs index 4fbb499..a64a60b 100644 --- a/jh7110-vf2-13b-pac/src/uart3/fcr.rs +++ b/jh7110-vf2-13b-pac/src/uart3/fcr.rs @@ -3,55 +3,59 @@ pub type R = crate::R; #[doc = "Register `fcr` writer"] pub type W = crate::W; #[doc = "Field `fifoe` writer - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] -pub type FIFOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIFOE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfifor` writer - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfifor` writer - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dmam` writer - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] -pub type DMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMAM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tet` writer - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type TET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `rt` writer - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type RT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type RT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl W { #[doc = "Bit 0 - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] #[inline(always)] #[must_use] - pub fn fifoe(&mut self) -> FIFOE_W { - FIFOE_W::new(self) + pub fn fifoe(&mut self) -> FIFOE_W { + FIFOE_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfifor(&mut self) -> RFIFOR_W { - RFIFOR_W::new(self) + pub fn rfifor(&mut self) -> RFIFOR_W { + RFIFOR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfifor(&mut self) -> XFIFOR_W { - XFIFOR_W::new(self) + pub fn xfifor(&mut self) -> XFIFOR_W { + XFIFOR_W::new(self, 2) } #[doc = "Bit 3 - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn dmam(&mut self) -> DMAM_W { - DMAM_W::new(self) + pub fn dmam(&mut self) -> DMAM_W { + DMAM_W::new(self, 3) } #[doc = "Bits 4:5 - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn tet(&mut self) -> TET_W { - TET_W::new(self) + pub fn tet(&mut self) -> TET_W { + TET_W::new(self, 4) } #[doc = "Bits 6:7 - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn rt(&mut self) -> RT_W { - RT_W::new(self) + pub fn rt(&mut self) -> RT_W { + RT_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/htx.rs b/jh7110-vf2-13b-pac/src/uart3/htx.rs index ad027bd..fc82325 100644 --- a/jh7110-vf2-13b-pac/src/uart3/htx.rs +++ b/jh7110-vf2-13b-pac/src/uart3/htx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `htx` reader - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] pub type HTX_R = crate::BitReader; #[doc = "Field `htx` writer - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] -pub type HTX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HTX_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] #[must_use] - pub fn htx(&mut self) -> HTX_W { - HTX_W::new(self) + pub fn htx(&mut self) -> HTX_W { + HTX_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/ier.rs b/jh7110-vf2-13b-pac/src/uart3/ier.rs index 006fbea..3cf3d7f 100644 --- a/jh7110-vf2-13b-pac/src/uart3/ier.rs +++ b/jh7110-vf2-13b-pac/src/uart3/ier.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `erbfi` reader - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] pub type ERBFI_R = crate::BitReader; #[doc = "Field `erbfi` writer - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] -pub type ERBFI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ERBFI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `etbei` reader - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] pub type ETBEI_R = crate::BitReader; #[doc = "Field `etbei` writer - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ETBEI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ETBEI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `elsi` reader - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] pub type ELSI_R = crate::BitReader; #[doc = "Field `elsi` writer - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ELSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ELSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `edssi` reader - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] pub type EDSSI_R = crate::BitReader; #[doc = "Field `edssi` writer - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] -pub type EDSSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EDSSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ptime` reader - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] pub type PTIME_R = crate::BitReader; #[doc = "Field `ptime` writer - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] -pub type PTIME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PTIME_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn erbfi(&mut self) -> ERBFI_W { - ERBFI_W::new(self) + pub fn erbfi(&mut self) -> ERBFI_W { + ERBFI_W::new(self, 0) } #[doc = "Bit 1 - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn etbei(&mut self) -> ETBEI_W { - ETBEI_W::new(self) + pub fn etbei(&mut self) -> ETBEI_W { + ETBEI_W::new(self, 1) } #[doc = "Bit 2 - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn elsi(&mut self) -> ELSI_W { - ELSI_W::new(self) + pub fn elsi(&mut self) -> ELSI_W { + ELSI_W::new(self, 2) } #[doc = "Bit 3 - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn edssi(&mut self) -> EDSSI_W { - EDSSI_W::new(self) + pub fn edssi(&mut self) -> EDSSI_W { + EDSSI_W::new(self, 3) } #[doc = "Bit 7 - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn ptime(&mut self) -> PTIME_W { - PTIME_W::new(self) + pub fn ptime(&mut self) -> PTIME_W { + PTIME_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/iir.rs b/jh7110-vf2-13b-pac/src/uart3/iir.rs index c90daa5..c949f03 100644 --- a/jh7110-vf2-13b-pac/src/uart3/iir.rs +++ b/jh7110-vf2-13b-pac/src/uart3/iir.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/lcr.rs b/jh7110-vf2-13b-pac/src/uart3/lcr.rs index acd83ee..3bc10c2 100644 --- a/jh7110-vf2-13b-pac/src/uart3/lcr.rs +++ b/jh7110-vf2-13b-pac/src/uart3/lcr.rs @@ -7,7 +7,7 @@ is zero), always readable. This is used to select the number of data bits per ch pub type DLS_R = crate::FieldReader; #[doc = "Field `dls` writer - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] -pub type DLS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DLS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `stop` reader - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] @@ -15,31 +15,31 @@ pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pen` reader - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] pub type PEN_R = crate::BitReader; #[doc = "Field `pen` writer - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] -pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `eps` reader - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] pub type EPS_R = crate::BitReader; #[doc = "Field `eps` writer - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] -pub type EPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EPS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bc` reader - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] pub type BC_R = crate::BitReader; #[doc = "Field `bc` writer - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] -pub type BC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dlab` reader - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] pub type DLAB_R = crate::BitReader; #[doc = "Field `dlab` writer - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] -pub type DLAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DLAB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:1 - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] @@ -84,46 +84,50 @@ impl W { is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] #[inline(always)] #[must_use] - pub fn dls(&mut self) -> DLS_W { - DLS_W::new(self) + pub fn dls(&mut self) -> DLS_W { + DLS_W::new(self, 0) } #[doc = "Bit 2 - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 2) } #[doc = "Bit 3 - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W { - PEN_W::new(self) + pub fn pen(&mut self) -> PEN_W { + PEN_W::new(self, 3) } #[doc = "Bit 4 - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] #[inline(always)] #[must_use] - pub fn eps(&mut self) -> EPS_W { - EPS_W::new(self) + pub fn eps(&mut self) -> EPS_W { + EPS_W::new(self, 4) } #[doc = "Bit 6 - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] #[inline(always)] #[must_use] - pub fn bc(&mut self) -> BC_W { - BC_W::new(self) + pub fn bc(&mut self) -> BC_W { + BC_W::new(self, 6) } #[doc = "Bit 7 - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] #[inline(always)] #[must_use] - pub fn dlab(&mut self) -> DLAB_W { - DLAB_W::new(self) + pub fn dlab(&mut self) -> DLAB_W { + DLAB_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/lpdlh.rs b/jh7110-vf2-13b-pac/src/uart3/lpdlh.rs index 8a910c8..095afa9 100644 --- a/jh7110-vf2-13b-pac/src/uart3/lpdlh.rs +++ b/jh7110-vf2-13b-pac/src/uart3/lpdlh.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdlh` reader - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] pub type LPDLH_R = crate::FieldReader; #[doc = "Field `lpdlh` writer - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] -pub type LPDLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] #[must_use] - pub fn lpdlh(&mut self) -> LPDLH_W { - LPDLH_W::new(self) + pub fn lpdlh(&mut self) -> LPDLH_W { + LPDLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/lpdll.rs b/jh7110-vf2-13b-pac/src/uart3/lpdll.rs index 7780651..21d0018 100644 --- a/jh7110-vf2-13b-pac/src/uart3/lpdll.rs +++ b/jh7110-vf2-13b-pac/src/uart3/lpdll.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdll` reader - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] pub type LPDLL_R = crate::FieldReader; #[doc = "Field `lpdll` writer - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type LPDLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn lpdll(&mut self) -> LPDLL_W { - LPDLL_W::new(self) + pub fn lpdll(&mut self) -> LPDLL_W { + LPDLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/lsr.rs b/jh7110-vf2-13b-pac/src/uart3/lsr.rs index f576c10..ff2ab48 100644 --- a/jh7110-vf2-13b-pac/src/uart3/lsr.rs +++ b/jh7110-vf2-13b-pac/src/uart3/lsr.rs @@ -73,7 +73,11 @@ set to one). This is used to indicate if there is at least one parity error, fra } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/mcr.rs b/jh7110-vf2-13b-pac/src/uart3/mcr.rs index 6932ee7..9c93108 100644 --- a/jh7110-vf2-13b-pac/src/uart3/mcr.rs +++ b/jh7110-vf2-13b-pac/src/uart3/mcr.rs @@ -7,7 +7,7 @@ set to one), the dtr_n output is held inactive high while the value of this loca pub type DTR_R = crate::BitReader; #[doc = "Field `dtr` writer - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type DTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rts` reader - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR\\[5\\] @@ -23,19 +23,19 @@ set to one) and FIFOs enable (FCR\\[0\\] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR\\[1\\] is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out1` reader - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT1_R = crate::BitReader; #[doc = "Field `out1` writer - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out2` reader - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT2_R = crate::BitReader; #[doc = "Field `out2` writer - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `lb` reader - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] @@ -43,15 +43,15 @@ pub type LB_R = crate::BitReader; #[doc = "Field `lb` writer - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] -pub type LB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `afce` reader - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] pub type AFCE_R = crate::BitReader; #[doc = "Field `afce` writer - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] -pub type AFCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AFCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sire` reader - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] pub type SIRE_R = crate::BitReader; #[doc = "Field `sire` writer - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] -pub type SIRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SIRE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] @@ -105,8 +105,8 @@ impl W { set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn dtr(&mut self) -> DTR_W { - DTR_W::new(self) + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 0) } #[doc = "Bit 1 - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] @@ -117,44 +117,48 @@ is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W { - RTS_W::new(self) + pub fn rts(&mut self) -> RTS_W { + RTS_W::new(self, 1) } #[doc = "Bit 2 - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out1(&mut self) -> OUT1_W { - OUT1_W::new(self) + pub fn out1(&mut self) -> OUT1_W { + OUT1_W::new(self, 2) } #[doc = "Bit 3 - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out2(&mut self) -> OUT2_W { - OUT2_W::new(self) + pub fn out2(&mut self) -> OUT2_W { + OUT2_W::new(self, 3) } #[doc = "Bit 4 - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] #[inline(always)] #[must_use] - pub fn lb(&mut self) -> LB_W { - LB_W::new(self) + pub fn lb(&mut self) -> LB_W { + LB_W::new(self, 4) } #[doc = "Bit 5 - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] #[inline(always)] #[must_use] - pub fn afce(&mut self) -> AFCE_W { - AFCE_W::new(self) + pub fn afce(&mut self) -> AFCE_W { + AFCE_W::new(self, 5) } #[doc = "Bit 6 - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] #[inline(always)] #[must_use] - pub fn sire(&mut self) -> SIRE_W { - SIRE_W::new(self) + pub fn sire(&mut self) -> SIRE_W { + SIRE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/msr.rs b/jh7110-vf2-13b-pac/src/uart3/msr.rs index 65c526b..b54fc38 100644 --- a/jh7110-vf2-13b-pac/src/uart3/msr.rs +++ b/jh7110-vf2-13b-pac/src/uart3/msr.rs @@ -93,7 +93,11 @@ set to one), DCD is the same as MCR\\[3\\] } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/rbr.rs b/jh7110-vf2-13b-pac/src/uart3/rbr.rs index 03003ed..403adcf 100644 --- a/jh7110-vf2-13b-pac/src/uart3/rbr.rs +++ b/jh7110-vf2-13b-pac/src/uart3/rbr.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/rfl.rs b/jh7110-vf2-13b-pac/src/uart3/rfl.rs index 2aea928..59355cb 100644 --- a/jh7110-vf2-13b-pac/src/uart3/rfl.rs +++ b/jh7110-vf2-13b-pac/src/uart3/rfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/rfw.rs b/jh7110-vf2-13b-pac/src/uart3/rfw.rs index 7b917de..490472d 100644 --- a/jh7110-vf2-13b-pac/src/uart3/rfw.rs +++ b/jh7110-vf2-13b-pac/src/uart3/rfw.rs @@ -4,36 +4,40 @@ pub type R = crate::R; pub type W = crate::W; #[doc = "Field `rfwd` writer - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] -pub type RFWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type RFWD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `rfpe` writer - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] -pub type RFPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFPE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rffe` writer - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] -pub type RFFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bits 0:7 - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] #[inline(always)] #[must_use] - pub fn rfwd(&mut self) -> RFWD_W { - RFWD_W::new(self) + pub fn rfwd(&mut self) -> RFWD_W { + RFWD_W::new(self, 0) } #[doc = "Bit 8 - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rfpe(&mut self) -> RFPE_W { - RFPE_W::new(self) + pub fn rfpe(&mut self) -> RFPE_W { + RFPE_W::new(self, 8) } #[doc = "Bit 9 - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rffe(&mut self) -> RFFE_W { - RFFE_W::new(self) + pub fn rffe(&mut self) -> RFFE_W { + RFFE_W::new(self, 9) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sbcr.rs b/jh7110-vf2-13b-pac/src/uart3/sbcr.rs index 73914e9..5a120c0 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sbcr.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sbcr.rs @@ -7,7 +7,7 @@ pub type W = crate::W; pub type SBCR_R = crate::BitReader; #[doc = "Field `sbcr` writer - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] -pub type SBCR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SBCR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] @@ -21,10 +21,14 @@ impl W { = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] #[inline(always)] #[must_use] - pub fn sbcr(&mut self) -> SBCR_W { - SBCR_W::new(self) + pub fn sbcr(&mut self) -> SBCR_W { + SBCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/scr.rs b/jh7110-vf2-13b-pac/src/uart3/scr.rs index 744352e..f46ba21 100644 --- a/jh7110-vf2-13b-pac/src/uart3/scr.rs +++ b/jh7110-vf2-13b-pac/src/uart3/scr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `scr` reader - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sdmam.rs b/jh7110-vf2-13b-pac/src/uart3/sdmam.rs index 684377c..4be4fa2 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sdmam.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sdmam.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sdmam` reader - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] pub type SDMAM_R = crate::BitReader; #[doc = "Field `sdmam` writer - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] -pub type SDMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SDMAM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn sdmam(&mut self) -> SDMAM_W { - SDMAM_W::new(self) + pub fn sdmam(&mut self) -> SDMAM_W { + SDMAM_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sfe.rs b/jh7110-vf2-13b-pac/src/uart3/sfe.rs index e68b088..ed26fee 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sfe.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sfe.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sfe` reader - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] pub type SFE_R = crate::BitReader; #[doc = "Field `sfe` writer - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] -pub type SFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] #[must_use] - pub fn sfe(&mut self) -> SFE_W { - SFE_W::new(self) + pub fn sfe(&mut self) -> SFE_W { + SFE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srbr0.rs b/jh7110-vf2-13b-pac/src/uart3/srbr0.rs index 4076661..4e44d1a 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srbr0.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srbr0.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srbr1.rs b/jh7110-vf2-13b-pac/src/uart3/srbr1.rs index 2f31b75..46bc479 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srbr1.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srbr1.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srbr10.rs b/jh7110-vf2-13b-pac/src/uart3/srbr10.rs index 3639d65..70297bf 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srbr10.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srbr10.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srbr11.rs b/jh7110-vf2-13b-pac/src/uart3/srbr11.rs index 92d29b1..28d0277 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srbr11.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srbr11.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srbr12.rs b/jh7110-vf2-13b-pac/src/uart3/srbr12.rs index 52e795e..3eccd9a 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srbr12.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srbr12.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srbr13.rs b/jh7110-vf2-13b-pac/src/uart3/srbr13.rs index 50aae40..e47e4e4 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srbr13.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srbr13.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srbr14.rs b/jh7110-vf2-13b-pac/src/uart3/srbr14.rs index cb25819..8f23662 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srbr14.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srbr14.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srbr15.rs b/jh7110-vf2-13b-pac/src/uart3/srbr15.rs index b25ae46..1dac092 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srbr15.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srbr15.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srbr2.rs b/jh7110-vf2-13b-pac/src/uart3/srbr2.rs index 9f3236c..afb0617 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srbr2.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srbr2.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srbr3.rs b/jh7110-vf2-13b-pac/src/uart3/srbr3.rs index 5c1edda..0ff3650 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srbr3.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srbr3.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srbr4.rs b/jh7110-vf2-13b-pac/src/uart3/srbr4.rs index e6bee93..59560c4 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srbr4.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srbr4.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srbr5.rs b/jh7110-vf2-13b-pac/src/uart3/srbr5.rs index e599009..763e341 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srbr5.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srbr5.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srbr6.rs b/jh7110-vf2-13b-pac/src/uart3/srbr6.rs index b0155b3..78e2a40 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srbr6.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srbr6.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srbr7.rs b/jh7110-vf2-13b-pac/src/uart3/srbr7.rs index b8f9b88..0723ff0 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srbr7.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srbr7.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srbr8.rs b/jh7110-vf2-13b-pac/src/uart3/srbr8.rs index f57b044..4702cd9 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srbr8.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srbr8.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srbr9.rs b/jh7110-vf2-13b-pac/src/uart3/srbr9.rs index 3a160aa..e1a262e 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srbr9.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srbr9.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srr.rs b/jh7110-vf2-13b-pac/src/uart3/srr.rs index 6671199..fdb0c0a 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srr.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srr.rs @@ -3,31 +3,35 @@ pub type R = crate::R; #[doc = "Register `srr` writer"] pub type W = crate::W; #[doc = "Field `ur` writer - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] -pub type UR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type UR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfr` writer - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfr` writer - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFR_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] #[inline(always)] #[must_use] - pub fn ur(&mut self) -> UR_W { - UR_W::new(self) + pub fn ur(&mut self) -> UR_W { + UR_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfr(&mut self) -> RFR_W { - RFR_W::new(self) + pub fn rfr(&mut self) -> RFR_W { + RFR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfr(&mut self) -> XFR_W { - XFR_W::new(self) + pub fn xfr(&mut self) -> XFR_W { + XFR_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srt.rs b/jh7110-vf2-13b-pac/src/uart3/srt.rs index fed4f1f..da909fd 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srt.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `srt` reader - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] pub type SRT_R = crate::FieldReader; #[doc = "Field `srt` writer - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type SRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SRT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn srt(&mut self) -> SRT_W { - SRT_W::new(self) + pub fn srt(&mut self) -> SRT_W { + SRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/srts.rs b/jh7110-vf2-13b-pac/src/uart3/srts.rs index ceb0ee4..cf1e2a9 100644 --- a/jh7110-vf2-13b-pac/src/uart3/srts.rs +++ b/jh7110-vf2-13b-pac/src/uart3/srts.rs @@ -15,7 +15,7 @@ pub type SRTS_R = crate::BitReader; = 1) and FIFOs enable (FCR\\[0\\] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR\\[4\\] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] -pub type SRTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SRTS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Request to Send. This is a shadow register for the RTS bit (MCR\\[1\\]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] = 0), the rts_n signal is set low by programming MCR\\[1\\] @@ -37,10 +37,14 @@ impl W { = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn srts(&mut self) -> SRTS_W { - SRTS_W::new(self) + pub fn srts(&mut self) -> SRTS_W { + SRTS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/stet.rs b/jh7110-vf2-13b-pac/src/uart3/stet.rs index acb8ba1..503dc8a 100644 --- a/jh7110-vf2-13b-pac/src/uart3/stet.rs +++ b/jh7110-vf2-13b-pac/src/uart3/stet.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `stet` reader - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] pub type STET_R = crate::FieldReader; #[doc = "Field `stet` writer - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type STET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type STET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn stet(&mut self) -> STET_W { - STET_W::new(self) + pub fn stet(&mut self) -> STET_W { + STET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sthr0.rs b/jh7110-vf2-13b-pac/src/uart3/sthr0.rs index bfd277a..764ff05 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sthr0.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sthr0.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sthr1.rs b/jh7110-vf2-13b-pac/src/uart3/sthr1.rs index cc79733..5d58855 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sthr1.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sthr1.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sthr10.rs b/jh7110-vf2-13b-pac/src/uart3/sthr10.rs index be2659d..ffc38ff 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sthr10.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sthr10.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sthr11.rs b/jh7110-vf2-13b-pac/src/uart3/sthr11.rs index 8613dd5..1f8147f 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sthr11.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sthr11.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sthr12.rs b/jh7110-vf2-13b-pac/src/uart3/sthr12.rs index b354b10..7d816f3 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sthr12.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sthr12.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sthr13.rs b/jh7110-vf2-13b-pac/src/uart3/sthr13.rs index 06df4bc..9283b6a 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sthr13.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sthr13.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sthr14.rs b/jh7110-vf2-13b-pac/src/uart3/sthr14.rs index e181dd0..2daf622 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sthr14.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sthr14.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sthr15.rs b/jh7110-vf2-13b-pac/src/uart3/sthr15.rs index 4825778..f70715e 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sthr15.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sthr15.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sthr2.rs b/jh7110-vf2-13b-pac/src/uart3/sthr2.rs index d390f10..f1a9c77 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sthr2.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sthr2.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sthr3.rs b/jh7110-vf2-13b-pac/src/uart3/sthr3.rs index a74fdf0..06aab9e 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sthr3.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sthr3.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sthr4.rs b/jh7110-vf2-13b-pac/src/uart3/sthr4.rs index 1ee6b87..f6e7944 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sthr4.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sthr4.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sthr5.rs b/jh7110-vf2-13b-pac/src/uart3/sthr5.rs index ca360fe..7873a53 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sthr5.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sthr5.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sthr6.rs b/jh7110-vf2-13b-pac/src/uart3/sthr6.rs index 18e6fac..87c81df 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sthr6.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sthr6.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sthr7.rs b/jh7110-vf2-13b-pac/src/uart3/sthr7.rs index 27072a3..9928b3d 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sthr7.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sthr7.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sthr8.rs b/jh7110-vf2-13b-pac/src/uart3/sthr8.rs index 15060b8..565cb1d 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sthr8.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sthr8.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/sthr9.rs b/jh7110-vf2-13b-pac/src/uart3/sthr9.rs index 58af642..e64fece 100644 --- a/jh7110-vf2-13b-pac/src/uart3/sthr9.rs +++ b/jh7110-vf2-13b-pac/src/uart3/sthr9.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/tfl.rs b/jh7110-vf2-13b-pac/src/uart3/tfl.rs index e1faba6..db09fe3 100644 --- a/jh7110-vf2-13b-pac/src/uart3/tfl.rs +++ b/jh7110-vf2-13b-pac/src/uart3/tfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/tfr.rs b/jh7110-vf2-13b-pac/src/uart3/tfr.rs index 8e9ad91..714deff 100644 --- a/jh7110-vf2-13b-pac/src/uart3/tfr.rs +++ b/jh7110-vf2-13b-pac/src/uart3/tfr.rs @@ -14,7 +14,11 @@ is set to one). When FIFOs are implemented and enabled, reading this register gi } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/thr.rs b/jh7110-vf2-13b-pac/src/uart3/thr.rs index f910bd8..7845232 100644 --- a/jh7110-vf2-13b-pac/src/uart3/thr.rs +++ b/jh7110-vf2-13b-pac/src/uart3/thr.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `thr` writer - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type THR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type THR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn thr(&mut self) -> THR_W { - THR_W::new(self) + pub fn thr(&mut self) -> THR_W { + THR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/ucv.rs b/jh7110-vf2-13b-pac/src/uart3/ucv.rs index 8a3be91..6497a08 100644 --- a/jh7110-vf2-13b-pac/src/uart3/ucv.rs +++ b/jh7110-vf2-13b-pac/src/uart3/ucv.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart3/usr.rs b/jh7110-vf2-13b-pac/src/uart3/usr.rs index 445a085..b96417d 100644 --- a/jh7110-vf2-13b-pac/src/uart3/usr.rs +++ b/jh7110-vf2-13b-pac/src/uart3/usr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4.rs b/jh7110-vf2-13b-pac/src/uart4.rs index c462fbf..8a5f089 100644 --- a/jh7110-vf2-13b-pac/src/uart4.rs +++ b/jh7110-vf2-13b-pac/src/uart4.rs @@ -4,20 +4,13 @@ pub struct RegisterBlock { _reserved_0_dll: [u8; 0x04], _reserved_1_dlh: [u8; 0x04], _reserved_2_fcr: [u8; 0x04], - #[doc = "0x0c - Line Control Register"] - pub lcr: LCR, - #[doc = "0x10 - Modem Control Register"] - pub mcr: MCR, - #[doc = "0x14 - Line Status Register"] - pub lsr: LSR, - #[doc = "0x18 - Line Status Register"] - pub msr: MSR, - #[doc = "0x1c - Scratch Pad Register"] - pub scr: SCR, - #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdll: LPDLL, - #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdlh: LPDLH, + lcr: LCR, + mcr: MCR, + lsr: LSR, + msr: MSR, + scr: SCR, + lpdll: LPDLL, + lpdlh: LPDLH, _reserved10: [u8; 0x08], _reserved_10_srbr0: [u8; 0x04], _reserved_11_srbr1: [u8; 0x04], @@ -35,564 +28,663 @@ pub struct RegisterBlock { _reserved_23_srbr13: [u8; 0x04], _reserved_24_srbr14: [u8; 0x04], _reserved_25_srbr15: [u8; 0x04], - #[doc = "0x70 - FIFO Access Register"] - pub far: FAR, - #[doc = "0x74 - Transmit FIFO Read"] - pub tfr: TFR, - #[doc = "0x78 - Receive FIFO Write"] - pub rfw: RFW, - #[doc = "0x7c - UART Status Register"] - pub usr: USR, - #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub tfl: TFL, - #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub rfl: RFL, - #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srr: SRR, - #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srts: SRTS, - #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sbcr: SBCR, - #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sdmam: SDMAM, - #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sfe: SFE, - #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srt: SRT, - #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub stet: STET, - #[doc = "0xa4 - Halt TX"] - pub htx: HTX, - #[doc = "0xa8 - DMA Software Acknowledge"] - pub dmasa: DMASA, + far: FAR, + tfr: TFR, + rfw: RFW, + usr: USR, + tfl: TFL, + rfl: RFL, + srr: SRR, + srts: SRTS, + sbcr: SBCR, + sdmam: SDMAM, + sfe: SFE, + srt: SRT, + stet: STET, + htx: HTX, + dmasa: DMASA, _reserved41: [u8; 0x48], - #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] - pub cpr: CPR, + cpr: CPR, _reserved_42_ctr: [u8; 0x04], } impl RegisterBlock { #[doc = "0x00 - Divisor Latch Low"] #[inline(always)] pub const fn dll(&self) -> &DLL { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Transmit Holding Register"] #[inline(always)] pub const fn thr(&self) -> &THR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Receive Buffer Register"] #[inline(always)] pub const fn rbr(&self) -> &RBR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x04 - Interrupt Enable Register"] #[inline(always)] pub const fn ier(&self) -> &IER { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x04 - Divisor Latch High"] #[inline(always)] pub const fn dlh(&self) -> &DLH { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x08 - FIFO Control Register"] #[inline(always)] pub const fn fcr(&self) -> &FCR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } } #[doc = "0x08 - Interrupt Identity Register"] #[inline(always)] pub const fn iir(&self) -> &IIR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } + } + #[doc = "0x0c - Line Control Register"] + #[inline(always)] + pub const fn lcr(&self) -> &LCR { + &self.lcr + } + #[doc = "0x10 - Modem Control Register"] + #[inline(always)] + pub const fn mcr(&self) -> &MCR { + &self.mcr + } + #[doc = "0x14 - Line Status Register"] + #[inline(always)] + pub const fn lsr(&self) -> &LSR { + &self.lsr + } + #[doc = "0x18 - Line Status Register"] + #[inline(always)] + pub const fn msr(&self) -> &MSR { + &self.msr + } + #[doc = "0x1c - Scratch Pad Register"] + #[inline(always)] + pub const fn scr(&self) -> &SCR { + &self.scr + } + #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdll(&self) -> &LPDLL { + &self.lpdll + } + #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdlh(&self) -> &LPDLH { + &self.lpdlh } #[doc = "0x30 - Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr0(&self) -> &STHR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x30 - Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr0(&self) -> &SRBR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x34 - Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr1(&self) -> &STHR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x34 - Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr1(&self) -> &SRBR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x38 - Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr2(&self) -> &STHR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x38 - Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr2(&self) -> &SRBR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x3c - Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr3(&self) -> &STHR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x3c - Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr3(&self) -> &SRBR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x40 - Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr4(&self) -> &STHR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x40 - Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr4(&self) -> &SRBR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x44 - Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr5(&self) -> &STHR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x44 - Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr5(&self) -> &SRBR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x48 - Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr6(&self) -> &STHR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x48 - Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr6(&self) -> &SRBR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x4c - Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr7(&self) -> &STHR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x4c - Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr7(&self) -> &SRBR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x50 - Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr8(&self) -> &STHR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x50 - Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr8(&self) -> &SRBR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x54 - Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr9(&self) -> &STHR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x54 - Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr9(&self) -> &SRBR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x58 - Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr10(&self) -> &STHR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x58 - Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr10(&self) -> &SRBR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x5c - Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr11(&self) -> &STHR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x5c - Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr11(&self) -> &SRBR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x60 - Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr12(&self) -> &STHR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x60 - Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr12(&self) -> &SRBR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x64 - Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr13(&self) -> &STHR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x64 - Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr13(&self) -> &SRBR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x68 - Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr14(&self) -> &STHR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x68 - Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr14(&self) -> &SRBR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x6c - Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr15(&self) -> &STHR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } } #[doc = "0x6c - Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr15(&self) -> &SRBR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } + } + #[doc = "0x70 - FIFO Access Register"] + #[inline(always)] + pub const fn far(&self) -> &FAR { + &self.far + } + #[doc = "0x74 - Transmit FIFO Read"] + #[inline(always)] + pub const fn tfr(&self) -> &TFR { + &self.tfr + } + #[doc = "0x78 - Receive FIFO Write"] + #[inline(always)] + pub const fn rfw(&self) -> &RFW { + &self.rfw + } + #[doc = "0x7c - UART Status Register"] + #[inline(always)] + pub const fn usr(&self) -> &USR { + &self.usr + } + #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn tfl(&self) -> &TFL { + &self.tfl + } + #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn rfl(&self) -> &RFL { + &self.rfl + } + #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srr(&self) -> &SRR { + &self.srr + } + #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srts(&self) -> &SRTS { + &self.srts + } + #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sbcr(&self) -> &SBCR { + &self.sbcr + } + #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sdmam(&self) -> &SDMAM { + &self.sdmam + } + #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sfe(&self) -> &SFE { + &self.sfe + } + #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srt(&self) -> &SRT { + &self.srt + } + #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn stet(&self) -> &STET { + &self.stet + } + #[doc = "0xa4 - Halt TX"] + #[inline(always)] + pub const fn htx(&self) -> &HTX { + &self.htx + } + #[doc = "0xa8 - DMA Software Acknowledge"] + #[inline(always)] + pub const fn dmasa(&self) -> &DMASA { + &self.dmasa + } + #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn cpr(&self) -> &CPR { + &self.cpr } #[doc = "0xf8 - Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ctr(&self) -> &CTR { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } #[doc = "0xf8 - UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ucv(&self) -> &UCV { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } } -#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rbr`] +#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbr`] module"] pub type RBR = crate::Reg; #[doc = "Receive Buffer Register"] pub mod rbr; -#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`thr`] +#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thr`] module"] pub type THR = crate::Reg; #[doc = "Transmit Holding Register"] pub mod thr; -#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dll`] +#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll`] module"] pub type DLL = crate::Reg; #[doc = "Divisor Latch Low"] pub mod dll; -#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dlh`] +#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlh`] module"] pub type DLH = crate::Reg; #[doc = "Divisor Latch High"] pub mod dlh; -#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`iir`] +#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] module"] pub type IIR = crate::Reg; #[doc = "Interrupt Identity Register"] pub mod iir; -#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fcr`] +#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"] pub type FCR = crate::Reg; #[doc = "FIFO Control Register"] pub mod fcr; -#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lcr`] +#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] module"] pub type LCR = crate::Reg; #[doc = "Line Control Register"] pub mod lcr; -#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mcr`] +#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] pub type MCR = crate::Reg; #[doc = "Modem Control Register"] pub mod mcr; -#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lsr`] +#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] module"] pub type LSR = crate::Reg; #[doc = "Line Status Register"] pub mod lsr; -#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msr`] +#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"] pub type MSR = crate::Reg; #[doc = "Line Status Register"] pub mod msr; -#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scr`] +#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`] module"] pub type SCR = crate::Reg; #[doc = "Scratch Pad Register"] pub mod scr; -#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdll`] +#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdll`] module"] pub type LPDLL = crate::Reg; #[doc = "Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdll; -#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdlh`] +#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdlh`] module"] pub type LPDLH = crate::Reg; #[doc = "Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdlh; -#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr0`] +#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr0`] module"] pub type SRBR0 = crate::Reg; #[doc = "Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr0; -#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr0`] +#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr0`] module"] pub type STHR0 = crate::Reg; #[doc = "Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr0; -#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr1`] +#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr1`] module"] pub type SRBR1 = crate::Reg; #[doc = "Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr1; -#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr1`] +#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr1`] module"] pub type STHR1 = crate::Reg; #[doc = "Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr1; -#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr2`] +#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr2`] module"] pub type SRBR2 = crate::Reg; #[doc = "Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr2; -#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr2`] +#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr2`] module"] pub type STHR2 = crate::Reg; #[doc = "Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr2; -#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr3`] +#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr3`] module"] pub type SRBR3 = crate::Reg; #[doc = "Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr3; -#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr3`] +#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr3`] module"] pub type STHR3 = crate::Reg; #[doc = "Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr3; -#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr4`] +#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr4`] module"] pub type SRBR4 = crate::Reg; #[doc = "Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr4; -#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr4`] +#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr4`] module"] pub type STHR4 = crate::Reg; #[doc = "Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr4; -#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr5`] +#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr5`] module"] pub type SRBR5 = crate::Reg; #[doc = "Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr5; -#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr5`] +#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr5`] module"] pub type STHR5 = crate::Reg; #[doc = "Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr5; -#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr6`] +#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr6`] module"] pub type SRBR6 = crate::Reg; #[doc = "Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr6; -#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr6`] +#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr6`] module"] pub type STHR6 = crate::Reg; #[doc = "Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr6; -#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr7`] +#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr7`] module"] pub type SRBR7 = crate::Reg; #[doc = "Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr7; -#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr7`] +#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr7`] module"] pub type STHR7 = crate::Reg; #[doc = "Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr7; -#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr8`] +#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr8`] module"] pub type SRBR8 = crate::Reg; #[doc = "Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr8; -#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr8`] +#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr8`] module"] pub type STHR8 = crate::Reg; #[doc = "Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr8; -#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr9`] +#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr9`] module"] pub type SRBR9 = crate::Reg; #[doc = "Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr9; -#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr9`] +#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr9`] module"] pub type STHR9 = crate::Reg; #[doc = "Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr9; -#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr10`] +#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr10`] module"] pub type SRBR10 = crate::Reg; #[doc = "Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr10; -#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr10`] +#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr10`] module"] pub type STHR10 = crate::Reg; #[doc = "Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr10; -#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr11`] +#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr11`] module"] pub type SRBR11 = crate::Reg; #[doc = "Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr11; -#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr11`] +#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr11`] module"] pub type STHR11 = crate::Reg; #[doc = "Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr11; -#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr12`] +#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr12`] module"] pub type SRBR12 = crate::Reg; #[doc = "Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr12; -#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr12`] +#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr12`] module"] pub type STHR12 = crate::Reg; #[doc = "Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr12; -#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr13`] +#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr13`] module"] pub type SRBR13 = crate::Reg; #[doc = "Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr13; -#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr13`] +#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr13`] module"] pub type STHR13 = crate::Reg; #[doc = "Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr13; -#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr14`] +#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr14`] module"] pub type SRBR14 = crate::Reg; #[doc = "Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr14; -#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr14`] +#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr14`] module"] pub type STHR14 = crate::Reg; #[doc = "Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr14; -#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr15`] +#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr15`] module"] pub type SRBR15 = crate::Reg; #[doc = "Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr15; -#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr15`] +#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr15`] module"] pub type STHR15 = crate::Reg; #[doc = "Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr15; -#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`far`] +#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@far`] module"] pub type FAR = crate::Reg; #[doc = "FIFO Access Register"] pub mod far; -#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfr`] +#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfr`] module"] pub type TFR = crate::Reg; #[doc = "Transmit FIFO Read"] pub mod tfr; -#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfw`] +#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfw`] module"] pub type RFW = crate::Reg; #[doc = "Receive FIFO Write"] pub mod rfw; -#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`usr`] +#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usr`] module"] pub type USR = crate::Reg; #[doc = "UART Status Register"] pub mod usr; -#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfl`] +#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfl`] module"] pub type TFL = crate::Reg; #[doc = "Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod tfl; -#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfl`] +#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfl`] module"] pub type RFL = crate::Reg; #[doc = "Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod rfl; -#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srr`] +#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srr`] module"] pub type SRR = crate::Reg; #[doc = "Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srr; -#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srts`] +#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srts`] module"] pub type SRTS = crate::Reg; #[doc = "Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srts; -#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sbcr`] +#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sbcr`] module"] pub type SBCR = crate::Reg; #[doc = "Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sbcr; -#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sdmam`] +#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdmam`] module"] pub type SDMAM = crate::Reg; #[doc = "Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sdmam; -#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sfe`] +#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfe`] module"] pub type SFE = crate::Reg; #[doc = "Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sfe; -#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srt`] +#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srt`] module"] pub type SRT = crate::Reg; #[doc = "Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srt; -#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stet`] +#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stet`] module"] pub type STET = crate::Reg; #[doc = "Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod stet; -#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`htx`] +#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@htx`] module"] pub type HTX = crate::Reg; #[doc = "Halt TX"] pub mod htx; -#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dmasa`] +#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasa`] module"] pub type DMASA = crate::Reg; #[doc = "DMA Software Acknowledge"] pub mod dmasa; -#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cpr`] +#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpr`] module"] pub type CPR = crate::Reg; #[doc = "Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] pub mod cpr; -#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ucv`] +#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucv`] module"] pub type UCV = crate::Reg; #[doc = "UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] pub mod ucv; -#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctr`] +#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"] pub type CTR = crate::Reg; #[doc = "Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] diff --git a/jh7110-vf2-13b-pac/src/uart4/cpr.rs b/jh7110-vf2-13b-pac/src/uart4/cpr.rs index 4807519..332b584 100644 --- a/jh7110-vf2-13b-pac/src/uart4/cpr.rs +++ b/jh7110-vf2-13b-pac/src/uart4/cpr.rs @@ -89,7 +89,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/ctr.rs b/jh7110-vf2-13b-pac/src/uart4/ctr.rs index c3760d5..ac70194 100644 --- a/jh7110-vf2-13b-pac/src/uart4/ctr.rs +++ b/jh7110-vf2-13b-pac/src/uart4/ctr.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/dlh.rs b/jh7110-vf2-13b-pac/src/uart4/dlh.rs index 3257a2d..2a788c1 100644 --- a/jh7110-vf2-13b-pac/src/uart4/dlh.rs +++ b/jh7110-vf2-13b-pac/src/uart4/dlh.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLH_R = crate::FieldReader; #[doc = "Field `dlh` writer - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dlh(&mut self) -> DLH_W { - DLH_W::new(self) + pub fn dlh(&mut self) -> DLH_W { + DLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/dll.rs b/jh7110-vf2-13b-pac/src/uart4/dll.rs index 9c9daff..1c9d765 100644 --- a/jh7110-vf2-13b-pac/src/uart4/dll.rs +++ b/jh7110-vf2-13b-pac/src/uart4/dll.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLL_R = crate::FieldReader; #[doc = "Field `dll` writer - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dll(&mut self) -> DLL_W { - DLL_W::new(self) + pub fn dll(&mut self) -> DLL_W { + DLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/dmasa.rs b/jh7110-vf2-13b-pac/src/uart4/dmasa.rs index 7bcfb26..2fc4e6d 100644 --- a/jh7110-vf2-13b-pac/src/uart4/dmasa.rs +++ b/jh7110-vf2-13b-pac/src/uart4/dmasa.rs @@ -3,15 +3,19 @@ pub type R = crate::R; #[doc = "Register `dmasa` writer"] pub type W = crate::W; #[doc = "Field `dmasa` writer - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type DMASA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMASA_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn dmasa(&mut self) -> DMASA_W { - DMASA_W::new(self) + pub fn dmasa(&mut self) -> DMASA_W { + DMASA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/far.rs b/jh7110-vf2-13b-pac/src/uart4/far.rs index 3b3bcb1..d52059a 100644 --- a/jh7110-vf2-13b-pac/src/uart4/far.rs +++ b/jh7110-vf2-13b-pac/src/uart4/far.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `far` reader - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] pub type FAR_R = crate::BitReader; #[doc = "Field `far` writer - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] -pub type FAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FAR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] #[must_use] - pub fn far(&mut self) -> FAR_W { - FAR_W::new(self) + pub fn far(&mut self) -> FAR_W { + FAR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/fcr.rs b/jh7110-vf2-13b-pac/src/uart4/fcr.rs index 4fbb499..a64a60b 100644 --- a/jh7110-vf2-13b-pac/src/uart4/fcr.rs +++ b/jh7110-vf2-13b-pac/src/uart4/fcr.rs @@ -3,55 +3,59 @@ pub type R = crate::R; #[doc = "Register `fcr` writer"] pub type W = crate::W; #[doc = "Field `fifoe` writer - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] -pub type FIFOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIFOE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfifor` writer - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfifor` writer - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dmam` writer - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] -pub type DMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMAM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tet` writer - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type TET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `rt` writer - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type RT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type RT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl W { #[doc = "Bit 0 - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] #[inline(always)] #[must_use] - pub fn fifoe(&mut self) -> FIFOE_W { - FIFOE_W::new(self) + pub fn fifoe(&mut self) -> FIFOE_W { + FIFOE_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfifor(&mut self) -> RFIFOR_W { - RFIFOR_W::new(self) + pub fn rfifor(&mut self) -> RFIFOR_W { + RFIFOR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfifor(&mut self) -> XFIFOR_W { - XFIFOR_W::new(self) + pub fn xfifor(&mut self) -> XFIFOR_W { + XFIFOR_W::new(self, 2) } #[doc = "Bit 3 - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn dmam(&mut self) -> DMAM_W { - DMAM_W::new(self) + pub fn dmam(&mut self) -> DMAM_W { + DMAM_W::new(self, 3) } #[doc = "Bits 4:5 - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn tet(&mut self) -> TET_W { - TET_W::new(self) + pub fn tet(&mut self) -> TET_W { + TET_W::new(self, 4) } #[doc = "Bits 6:7 - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn rt(&mut self) -> RT_W { - RT_W::new(self) + pub fn rt(&mut self) -> RT_W { + RT_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/htx.rs b/jh7110-vf2-13b-pac/src/uart4/htx.rs index ad027bd..fc82325 100644 --- a/jh7110-vf2-13b-pac/src/uart4/htx.rs +++ b/jh7110-vf2-13b-pac/src/uart4/htx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `htx` reader - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] pub type HTX_R = crate::BitReader; #[doc = "Field `htx` writer - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] -pub type HTX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HTX_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] #[must_use] - pub fn htx(&mut self) -> HTX_W { - HTX_W::new(self) + pub fn htx(&mut self) -> HTX_W { + HTX_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/ier.rs b/jh7110-vf2-13b-pac/src/uart4/ier.rs index 006fbea..3cf3d7f 100644 --- a/jh7110-vf2-13b-pac/src/uart4/ier.rs +++ b/jh7110-vf2-13b-pac/src/uart4/ier.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `erbfi` reader - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] pub type ERBFI_R = crate::BitReader; #[doc = "Field `erbfi` writer - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] -pub type ERBFI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ERBFI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `etbei` reader - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] pub type ETBEI_R = crate::BitReader; #[doc = "Field `etbei` writer - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ETBEI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ETBEI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `elsi` reader - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] pub type ELSI_R = crate::BitReader; #[doc = "Field `elsi` writer - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ELSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ELSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `edssi` reader - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] pub type EDSSI_R = crate::BitReader; #[doc = "Field `edssi` writer - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] -pub type EDSSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EDSSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ptime` reader - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] pub type PTIME_R = crate::BitReader; #[doc = "Field `ptime` writer - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] -pub type PTIME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PTIME_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn erbfi(&mut self) -> ERBFI_W { - ERBFI_W::new(self) + pub fn erbfi(&mut self) -> ERBFI_W { + ERBFI_W::new(self, 0) } #[doc = "Bit 1 - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn etbei(&mut self) -> ETBEI_W { - ETBEI_W::new(self) + pub fn etbei(&mut self) -> ETBEI_W { + ETBEI_W::new(self, 1) } #[doc = "Bit 2 - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn elsi(&mut self) -> ELSI_W { - ELSI_W::new(self) + pub fn elsi(&mut self) -> ELSI_W { + ELSI_W::new(self, 2) } #[doc = "Bit 3 - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn edssi(&mut self) -> EDSSI_W { - EDSSI_W::new(self) + pub fn edssi(&mut self) -> EDSSI_W { + EDSSI_W::new(self, 3) } #[doc = "Bit 7 - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn ptime(&mut self) -> PTIME_W { - PTIME_W::new(self) + pub fn ptime(&mut self) -> PTIME_W { + PTIME_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/iir.rs b/jh7110-vf2-13b-pac/src/uart4/iir.rs index c90daa5..c949f03 100644 --- a/jh7110-vf2-13b-pac/src/uart4/iir.rs +++ b/jh7110-vf2-13b-pac/src/uart4/iir.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/lcr.rs b/jh7110-vf2-13b-pac/src/uart4/lcr.rs index acd83ee..3bc10c2 100644 --- a/jh7110-vf2-13b-pac/src/uart4/lcr.rs +++ b/jh7110-vf2-13b-pac/src/uart4/lcr.rs @@ -7,7 +7,7 @@ is zero), always readable. This is used to select the number of data bits per ch pub type DLS_R = crate::FieldReader; #[doc = "Field `dls` writer - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] -pub type DLS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DLS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `stop` reader - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] @@ -15,31 +15,31 @@ pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pen` reader - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] pub type PEN_R = crate::BitReader; #[doc = "Field `pen` writer - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] -pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `eps` reader - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] pub type EPS_R = crate::BitReader; #[doc = "Field `eps` writer - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] -pub type EPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EPS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bc` reader - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] pub type BC_R = crate::BitReader; #[doc = "Field `bc` writer - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] -pub type BC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dlab` reader - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] pub type DLAB_R = crate::BitReader; #[doc = "Field `dlab` writer - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] -pub type DLAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DLAB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:1 - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] @@ -84,46 +84,50 @@ impl W { is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] #[inline(always)] #[must_use] - pub fn dls(&mut self) -> DLS_W { - DLS_W::new(self) + pub fn dls(&mut self) -> DLS_W { + DLS_W::new(self, 0) } #[doc = "Bit 2 - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 2) } #[doc = "Bit 3 - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W { - PEN_W::new(self) + pub fn pen(&mut self) -> PEN_W { + PEN_W::new(self, 3) } #[doc = "Bit 4 - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] #[inline(always)] #[must_use] - pub fn eps(&mut self) -> EPS_W { - EPS_W::new(self) + pub fn eps(&mut self) -> EPS_W { + EPS_W::new(self, 4) } #[doc = "Bit 6 - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] #[inline(always)] #[must_use] - pub fn bc(&mut self) -> BC_W { - BC_W::new(self) + pub fn bc(&mut self) -> BC_W { + BC_W::new(self, 6) } #[doc = "Bit 7 - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] #[inline(always)] #[must_use] - pub fn dlab(&mut self) -> DLAB_W { - DLAB_W::new(self) + pub fn dlab(&mut self) -> DLAB_W { + DLAB_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/lpdlh.rs b/jh7110-vf2-13b-pac/src/uart4/lpdlh.rs index 8a910c8..095afa9 100644 --- a/jh7110-vf2-13b-pac/src/uart4/lpdlh.rs +++ b/jh7110-vf2-13b-pac/src/uart4/lpdlh.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdlh` reader - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] pub type LPDLH_R = crate::FieldReader; #[doc = "Field `lpdlh` writer - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] -pub type LPDLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] #[must_use] - pub fn lpdlh(&mut self) -> LPDLH_W { - LPDLH_W::new(self) + pub fn lpdlh(&mut self) -> LPDLH_W { + LPDLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/lpdll.rs b/jh7110-vf2-13b-pac/src/uart4/lpdll.rs index 7780651..21d0018 100644 --- a/jh7110-vf2-13b-pac/src/uart4/lpdll.rs +++ b/jh7110-vf2-13b-pac/src/uart4/lpdll.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdll` reader - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] pub type LPDLL_R = crate::FieldReader; #[doc = "Field `lpdll` writer - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type LPDLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn lpdll(&mut self) -> LPDLL_W { - LPDLL_W::new(self) + pub fn lpdll(&mut self) -> LPDLL_W { + LPDLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/lsr.rs b/jh7110-vf2-13b-pac/src/uart4/lsr.rs index f576c10..ff2ab48 100644 --- a/jh7110-vf2-13b-pac/src/uart4/lsr.rs +++ b/jh7110-vf2-13b-pac/src/uart4/lsr.rs @@ -73,7 +73,11 @@ set to one). This is used to indicate if there is at least one parity error, fra } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/mcr.rs b/jh7110-vf2-13b-pac/src/uart4/mcr.rs index 6932ee7..9c93108 100644 --- a/jh7110-vf2-13b-pac/src/uart4/mcr.rs +++ b/jh7110-vf2-13b-pac/src/uart4/mcr.rs @@ -7,7 +7,7 @@ set to one), the dtr_n output is held inactive high while the value of this loca pub type DTR_R = crate::BitReader; #[doc = "Field `dtr` writer - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type DTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rts` reader - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR\\[5\\] @@ -23,19 +23,19 @@ set to one) and FIFOs enable (FCR\\[0\\] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR\\[1\\] is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out1` reader - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT1_R = crate::BitReader; #[doc = "Field `out1` writer - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out2` reader - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT2_R = crate::BitReader; #[doc = "Field `out2` writer - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `lb` reader - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] @@ -43,15 +43,15 @@ pub type LB_R = crate::BitReader; #[doc = "Field `lb` writer - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] -pub type LB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `afce` reader - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] pub type AFCE_R = crate::BitReader; #[doc = "Field `afce` writer - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] -pub type AFCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AFCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sire` reader - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] pub type SIRE_R = crate::BitReader; #[doc = "Field `sire` writer - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] -pub type SIRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SIRE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] @@ -105,8 +105,8 @@ impl W { set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn dtr(&mut self) -> DTR_W { - DTR_W::new(self) + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 0) } #[doc = "Bit 1 - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] @@ -117,44 +117,48 @@ is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W { - RTS_W::new(self) + pub fn rts(&mut self) -> RTS_W { + RTS_W::new(self, 1) } #[doc = "Bit 2 - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out1(&mut self) -> OUT1_W { - OUT1_W::new(self) + pub fn out1(&mut self) -> OUT1_W { + OUT1_W::new(self, 2) } #[doc = "Bit 3 - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out2(&mut self) -> OUT2_W { - OUT2_W::new(self) + pub fn out2(&mut self) -> OUT2_W { + OUT2_W::new(self, 3) } #[doc = "Bit 4 - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] #[inline(always)] #[must_use] - pub fn lb(&mut self) -> LB_W { - LB_W::new(self) + pub fn lb(&mut self) -> LB_W { + LB_W::new(self, 4) } #[doc = "Bit 5 - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] #[inline(always)] #[must_use] - pub fn afce(&mut self) -> AFCE_W { - AFCE_W::new(self) + pub fn afce(&mut self) -> AFCE_W { + AFCE_W::new(self, 5) } #[doc = "Bit 6 - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] #[inline(always)] #[must_use] - pub fn sire(&mut self) -> SIRE_W { - SIRE_W::new(self) + pub fn sire(&mut self) -> SIRE_W { + SIRE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/msr.rs b/jh7110-vf2-13b-pac/src/uart4/msr.rs index 65c526b..b54fc38 100644 --- a/jh7110-vf2-13b-pac/src/uart4/msr.rs +++ b/jh7110-vf2-13b-pac/src/uart4/msr.rs @@ -93,7 +93,11 @@ set to one), DCD is the same as MCR\\[3\\] } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/rbr.rs b/jh7110-vf2-13b-pac/src/uart4/rbr.rs index 03003ed..403adcf 100644 --- a/jh7110-vf2-13b-pac/src/uart4/rbr.rs +++ b/jh7110-vf2-13b-pac/src/uart4/rbr.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/rfl.rs b/jh7110-vf2-13b-pac/src/uart4/rfl.rs index 2aea928..59355cb 100644 --- a/jh7110-vf2-13b-pac/src/uart4/rfl.rs +++ b/jh7110-vf2-13b-pac/src/uart4/rfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/rfw.rs b/jh7110-vf2-13b-pac/src/uart4/rfw.rs index 7b917de..490472d 100644 --- a/jh7110-vf2-13b-pac/src/uart4/rfw.rs +++ b/jh7110-vf2-13b-pac/src/uart4/rfw.rs @@ -4,36 +4,40 @@ pub type R = crate::R; pub type W = crate::W; #[doc = "Field `rfwd` writer - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] -pub type RFWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type RFWD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `rfpe` writer - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] -pub type RFPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFPE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rffe` writer - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] -pub type RFFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bits 0:7 - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] #[inline(always)] #[must_use] - pub fn rfwd(&mut self) -> RFWD_W { - RFWD_W::new(self) + pub fn rfwd(&mut self) -> RFWD_W { + RFWD_W::new(self, 0) } #[doc = "Bit 8 - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rfpe(&mut self) -> RFPE_W { - RFPE_W::new(self) + pub fn rfpe(&mut self) -> RFPE_W { + RFPE_W::new(self, 8) } #[doc = "Bit 9 - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rffe(&mut self) -> RFFE_W { - RFFE_W::new(self) + pub fn rffe(&mut self) -> RFFE_W { + RFFE_W::new(self, 9) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sbcr.rs b/jh7110-vf2-13b-pac/src/uart4/sbcr.rs index 73914e9..5a120c0 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sbcr.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sbcr.rs @@ -7,7 +7,7 @@ pub type W = crate::W; pub type SBCR_R = crate::BitReader; #[doc = "Field `sbcr` writer - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] -pub type SBCR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SBCR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] @@ -21,10 +21,14 @@ impl W { = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] #[inline(always)] #[must_use] - pub fn sbcr(&mut self) -> SBCR_W { - SBCR_W::new(self) + pub fn sbcr(&mut self) -> SBCR_W { + SBCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/scr.rs b/jh7110-vf2-13b-pac/src/uart4/scr.rs index 744352e..f46ba21 100644 --- a/jh7110-vf2-13b-pac/src/uart4/scr.rs +++ b/jh7110-vf2-13b-pac/src/uart4/scr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `scr` reader - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sdmam.rs b/jh7110-vf2-13b-pac/src/uart4/sdmam.rs index 684377c..4be4fa2 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sdmam.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sdmam.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sdmam` reader - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] pub type SDMAM_R = crate::BitReader; #[doc = "Field `sdmam` writer - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] -pub type SDMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SDMAM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn sdmam(&mut self) -> SDMAM_W { - SDMAM_W::new(self) + pub fn sdmam(&mut self) -> SDMAM_W { + SDMAM_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sfe.rs b/jh7110-vf2-13b-pac/src/uart4/sfe.rs index e68b088..ed26fee 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sfe.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sfe.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sfe` reader - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] pub type SFE_R = crate::BitReader; #[doc = "Field `sfe` writer - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] -pub type SFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] #[must_use] - pub fn sfe(&mut self) -> SFE_W { - SFE_W::new(self) + pub fn sfe(&mut self) -> SFE_W { + SFE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srbr0.rs b/jh7110-vf2-13b-pac/src/uart4/srbr0.rs index 4076661..4e44d1a 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srbr0.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srbr0.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srbr1.rs b/jh7110-vf2-13b-pac/src/uart4/srbr1.rs index 2f31b75..46bc479 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srbr1.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srbr1.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srbr10.rs b/jh7110-vf2-13b-pac/src/uart4/srbr10.rs index 3639d65..70297bf 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srbr10.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srbr10.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srbr11.rs b/jh7110-vf2-13b-pac/src/uart4/srbr11.rs index 92d29b1..28d0277 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srbr11.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srbr11.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srbr12.rs b/jh7110-vf2-13b-pac/src/uart4/srbr12.rs index 52e795e..3eccd9a 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srbr12.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srbr12.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srbr13.rs b/jh7110-vf2-13b-pac/src/uart4/srbr13.rs index 50aae40..e47e4e4 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srbr13.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srbr13.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srbr14.rs b/jh7110-vf2-13b-pac/src/uart4/srbr14.rs index cb25819..8f23662 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srbr14.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srbr14.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srbr15.rs b/jh7110-vf2-13b-pac/src/uart4/srbr15.rs index b25ae46..1dac092 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srbr15.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srbr15.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srbr2.rs b/jh7110-vf2-13b-pac/src/uart4/srbr2.rs index 9f3236c..afb0617 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srbr2.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srbr2.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srbr3.rs b/jh7110-vf2-13b-pac/src/uart4/srbr3.rs index 5c1edda..0ff3650 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srbr3.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srbr3.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srbr4.rs b/jh7110-vf2-13b-pac/src/uart4/srbr4.rs index e6bee93..59560c4 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srbr4.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srbr4.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srbr5.rs b/jh7110-vf2-13b-pac/src/uart4/srbr5.rs index e599009..763e341 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srbr5.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srbr5.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srbr6.rs b/jh7110-vf2-13b-pac/src/uart4/srbr6.rs index b0155b3..78e2a40 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srbr6.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srbr6.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srbr7.rs b/jh7110-vf2-13b-pac/src/uart4/srbr7.rs index b8f9b88..0723ff0 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srbr7.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srbr7.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srbr8.rs b/jh7110-vf2-13b-pac/src/uart4/srbr8.rs index f57b044..4702cd9 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srbr8.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srbr8.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srbr9.rs b/jh7110-vf2-13b-pac/src/uart4/srbr9.rs index 3a160aa..e1a262e 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srbr9.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srbr9.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srr.rs b/jh7110-vf2-13b-pac/src/uart4/srr.rs index 6671199..fdb0c0a 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srr.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srr.rs @@ -3,31 +3,35 @@ pub type R = crate::R; #[doc = "Register `srr` writer"] pub type W = crate::W; #[doc = "Field `ur` writer - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] -pub type UR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type UR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfr` writer - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfr` writer - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFR_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] #[inline(always)] #[must_use] - pub fn ur(&mut self) -> UR_W { - UR_W::new(self) + pub fn ur(&mut self) -> UR_W { + UR_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfr(&mut self) -> RFR_W { - RFR_W::new(self) + pub fn rfr(&mut self) -> RFR_W { + RFR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfr(&mut self) -> XFR_W { - XFR_W::new(self) + pub fn xfr(&mut self) -> XFR_W { + XFR_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srt.rs b/jh7110-vf2-13b-pac/src/uart4/srt.rs index fed4f1f..da909fd 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srt.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `srt` reader - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] pub type SRT_R = crate::FieldReader; #[doc = "Field `srt` writer - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type SRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SRT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn srt(&mut self) -> SRT_W { - SRT_W::new(self) + pub fn srt(&mut self) -> SRT_W { + SRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/srts.rs b/jh7110-vf2-13b-pac/src/uart4/srts.rs index ceb0ee4..cf1e2a9 100644 --- a/jh7110-vf2-13b-pac/src/uart4/srts.rs +++ b/jh7110-vf2-13b-pac/src/uart4/srts.rs @@ -15,7 +15,7 @@ pub type SRTS_R = crate::BitReader; = 1) and FIFOs enable (FCR\\[0\\] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR\\[4\\] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] -pub type SRTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SRTS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Request to Send. This is a shadow register for the RTS bit (MCR\\[1\\]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] = 0), the rts_n signal is set low by programming MCR\\[1\\] @@ -37,10 +37,14 @@ impl W { = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn srts(&mut self) -> SRTS_W { - SRTS_W::new(self) + pub fn srts(&mut self) -> SRTS_W { + SRTS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/stet.rs b/jh7110-vf2-13b-pac/src/uart4/stet.rs index acb8ba1..503dc8a 100644 --- a/jh7110-vf2-13b-pac/src/uart4/stet.rs +++ b/jh7110-vf2-13b-pac/src/uart4/stet.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `stet` reader - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] pub type STET_R = crate::FieldReader; #[doc = "Field `stet` writer - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type STET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type STET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn stet(&mut self) -> STET_W { - STET_W::new(self) + pub fn stet(&mut self) -> STET_W { + STET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sthr0.rs b/jh7110-vf2-13b-pac/src/uart4/sthr0.rs index bfd277a..764ff05 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sthr0.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sthr0.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sthr1.rs b/jh7110-vf2-13b-pac/src/uart4/sthr1.rs index cc79733..5d58855 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sthr1.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sthr1.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sthr10.rs b/jh7110-vf2-13b-pac/src/uart4/sthr10.rs index be2659d..ffc38ff 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sthr10.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sthr10.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sthr11.rs b/jh7110-vf2-13b-pac/src/uart4/sthr11.rs index 8613dd5..1f8147f 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sthr11.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sthr11.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sthr12.rs b/jh7110-vf2-13b-pac/src/uart4/sthr12.rs index b354b10..7d816f3 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sthr12.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sthr12.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sthr13.rs b/jh7110-vf2-13b-pac/src/uart4/sthr13.rs index 06df4bc..9283b6a 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sthr13.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sthr13.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sthr14.rs b/jh7110-vf2-13b-pac/src/uart4/sthr14.rs index e181dd0..2daf622 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sthr14.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sthr14.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sthr15.rs b/jh7110-vf2-13b-pac/src/uart4/sthr15.rs index 4825778..f70715e 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sthr15.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sthr15.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sthr2.rs b/jh7110-vf2-13b-pac/src/uart4/sthr2.rs index d390f10..f1a9c77 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sthr2.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sthr2.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sthr3.rs b/jh7110-vf2-13b-pac/src/uart4/sthr3.rs index a74fdf0..06aab9e 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sthr3.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sthr3.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sthr4.rs b/jh7110-vf2-13b-pac/src/uart4/sthr4.rs index 1ee6b87..f6e7944 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sthr4.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sthr4.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sthr5.rs b/jh7110-vf2-13b-pac/src/uart4/sthr5.rs index ca360fe..7873a53 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sthr5.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sthr5.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sthr6.rs b/jh7110-vf2-13b-pac/src/uart4/sthr6.rs index 18e6fac..87c81df 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sthr6.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sthr6.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sthr7.rs b/jh7110-vf2-13b-pac/src/uart4/sthr7.rs index 27072a3..9928b3d 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sthr7.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sthr7.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sthr8.rs b/jh7110-vf2-13b-pac/src/uart4/sthr8.rs index 15060b8..565cb1d 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sthr8.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sthr8.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/sthr9.rs b/jh7110-vf2-13b-pac/src/uart4/sthr9.rs index 58af642..e64fece 100644 --- a/jh7110-vf2-13b-pac/src/uart4/sthr9.rs +++ b/jh7110-vf2-13b-pac/src/uart4/sthr9.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/tfl.rs b/jh7110-vf2-13b-pac/src/uart4/tfl.rs index e1faba6..db09fe3 100644 --- a/jh7110-vf2-13b-pac/src/uart4/tfl.rs +++ b/jh7110-vf2-13b-pac/src/uart4/tfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/tfr.rs b/jh7110-vf2-13b-pac/src/uart4/tfr.rs index 8e9ad91..714deff 100644 --- a/jh7110-vf2-13b-pac/src/uart4/tfr.rs +++ b/jh7110-vf2-13b-pac/src/uart4/tfr.rs @@ -14,7 +14,11 @@ is set to one). When FIFOs are implemented and enabled, reading this register gi } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/thr.rs b/jh7110-vf2-13b-pac/src/uart4/thr.rs index f910bd8..7845232 100644 --- a/jh7110-vf2-13b-pac/src/uart4/thr.rs +++ b/jh7110-vf2-13b-pac/src/uart4/thr.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `thr` writer - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type THR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type THR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn thr(&mut self) -> THR_W { - THR_W::new(self) + pub fn thr(&mut self) -> THR_W { + THR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/ucv.rs b/jh7110-vf2-13b-pac/src/uart4/ucv.rs index 8a3be91..6497a08 100644 --- a/jh7110-vf2-13b-pac/src/uart4/ucv.rs +++ b/jh7110-vf2-13b-pac/src/uart4/ucv.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart4/usr.rs b/jh7110-vf2-13b-pac/src/uart4/usr.rs index 445a085..b96417d 100644 --- a/jh7110-vf2-13b-pac/src/uart4/usr.rs +++ b/jh7110-vf2-13b-pac/src/uart4/usr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5.rs b/jh7110-vf2-13b-pac/src/uart5.rs index c462fbf..8a5f089 100644 --- a/jh7110-vf2-13b-pac/src/uart5.rs +++ b/jh7110-vf2-13b-pac/src/uart5.rs @@ -4,20 +4,13 @@ pub struct RegisterBlock { _reserved_0_dll: [u8; 0x04], _reserved_1_dlh: [u8; 0x04], _reserved_2_fcr: [u8; 0x04], - #[doc = "0x0c - Line Control Register"] - pub lcr: LCR, - #[doc = "0x10 - Modem Control Register"] - pub mcr: MCR, - #[doc = "0x14 - Line Status Register"] - pub lsr: LSR, - #[doc = "0x18 - Line Status Register"] - pub msr: MSR, - #[doc = "0x1c - Scratch Pad Register"] - pub scr: SCR, - #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdll: LPDLL, - #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] - pub lpdlh: LPDLH, + lcr: LCR, + mcr: MCR, + lsr: LSR, + msr: MSR, + scr: SCR, + lpdll: LPDLL, + lpdlh: LPDLH, _reserved10: [u8; 0x08], _reserved_10_srbr0: [u8; 0x04], _reserved_11_srbr1: [u8; 0x04], @@ -35,564 +28,663 @@ pub struct RegisterBlock { _reserved_23_srbr13: [u8; 0x04], _reserved_24_srbr14: [u8; 0x04], _reserved_25_srbr15: [u8; 0x04], - #[doc = "0x70 - FIFO Access Register"] - pub far: FAR, - #[doc = "0x74 - Transmit FIFO Read"] - pub tfr: TFR, - #[doc = "0x78 - Receive FIFO Write"] - pub rfw: RFW, - #[doc = "0x7c - UART Status Register"] - pub usr: USR, - #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub tfl: TFL, - #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub rfl: RFL, - #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srr: SRR, - #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srts: SRTS, - #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sbcr: SBCR, - #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sdmam: SDMAM, - #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub sfe: SFE, - #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub srt: SRT, - #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] - pub stet: STET, - #[doc = "0xa4 - Halt TX"] - pub htx: HTX, - #[doc = "0xa8 - DMA Software Acknowledge"] - pub dmasa: DMASA, + far: FAR, + tfr: TFR, + rfw: RFW, + usr: USR, + tfl: TFL, + rfl: RFL, + srr: SRR, + srts: SRTS, + sbcr: SBCR, + sdmam: SDMAM, + sfe: SFE, + srt: SRT, + stet: STET, + htx: HTX, + dmasa: DMASA, _reserved41: [u8; 0x48], - #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] - pub cpr: CPR, + cpr: CPR, _reserved_42_ctr: [u8; 0x04], } impl RegisterBlock { #[doc = "0x00 - Divisor Latch Low"] #[inline(always)] pub const fn dll(&self) -> &DLL { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Transmit Holding Register"] #[inline(always)] pub const fn thr(&self) -> &THR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x00 - Receive Buffer Register"] #[inline(always)] pub const fn rbr(&self) -> &RBR { - unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + unsafe { &*(self as *const Self).cast::().add(0).cast() } } #[doc = "0x04 - Interrupt Enable Register"] #[inline(always)] pub const fn ier(&self) -> &IER { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x04 - Divisor Latch High"] #[inline(always)] pub const fn dlh(&self) -> &DLH { - unsafe { &*(self as *const Self).cast::().add(4usize).cast() } + unsafe { &*(self as *const Self).cast::().add(4).cast() } } #[doc = "0x08 - FIFO Control Register"] #[inline(always)] pub const fn fcr(&self) -> &FCR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } } #[doc = "0x08 - Interrupt Identity Register"] #[inline(always)] pub const fn iir(&self) -> &IIR { - unsafe { &*(self as *const Self).cast::().add(8usize).cast() } + unsafe { &*(self as *const Self).cast::().add(8).cast() } + } + #[doc = "0x0c - Line Control Register"] + #[inline(always)] + pub const fn lcr(&self) -> &LCR { + &self.lcr + } + #[doc = "0x10 - Modem Control Register"] + #[inline(always)] + pub const fn mcr(&self) -> &MCR { + &self.mcr + } + #[doc = "0x14 - Line Status Register"] + #[inline(always)] + pub const fn lsr(&self) -> &LSR { + &self.lsr + } + #[doc = "0x18 - Line Status Register"] + #[inline(always)] + pub const fn msr(&self) -> &MSR { + &self.msr + } + #[doc = "0x1c - Scratch Pad Register"] + #[inline(always)] + pub const fn scr(&self) -> &SCR { + &self.scr + } + #[doc = "0x20 - Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdll(&self) -> &LPDLL { + &self.lpdll + } + #[doc = "0x24 - Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] + #[inline(always)] + pub const fn lpdlh(&self) -> &LPDLH { + &self.lpdlh } #[doc = "0x30 - Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr0(&self) -> &STHR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x30 - Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr0(&self) -> &SRBR0 { - unsafe { &*(self as *const Self).cast::().add(48usize).cast() } + unsafe { &*(self as *const Self).cast::().add(48).cast() } } #[doc = "0x34 - Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr1(&self) -> &STHR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x34 - Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr1(&self) -> &SRBR1 { - unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + unsafe { &*(self as *const Self).cast::().add(52).cast() } } #[doc = "0x38 - Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr2(&self) -> &STHR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x38 - Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr2(&self) -> &SRBR2 { - unsafe { &*(self as *const Self).cast::().add(56usize).cast() } + unsafe { &*(self as *const Self).cast::().add(56).cast() } } #[doc = "0x3c - Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr3(&self) -> &STHR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x3c - Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr3(&self) -> &SRBR3 { - unsafe { &*(self as *const Self).cast::().add(60usize).cast() } + unsafe { &*(self as *const Self).cast::().add(60).cast() } } #[doc = "0x40 - Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr4(&self) -> &STHR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x40 - Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr4(&self) -> &SRBR4 { - unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + unsafe { &*(self as *const Self).cast::().add(64).cast() } } #[doc = "0x44 - Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr5(&self) -> &STHR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x44 - Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr5(&self) -> &SRBR5 { - unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + unsafe { &*(self as *const Self).cast::().add(68).cast() } } #[doc = "0x48 - Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr6(&self) -> &STHR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x48 - Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr6(&self) -> &SRBR6 { - unsafe { &*(self as *const Self).cast::().add(72usize).cast() } + unsafe { &*(self as *const Self).cast::().add(72).cast() } } #[doc = "0x4c - Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr7(&self) -> &STHR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x4c - Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr7(&self) -> &SRBR7 { - unsafe { &*(self as *const Self).cast::().add(76usize).cast() } + unsafe { &*(self as *const Self).cast::().add(76).cast() } } #[doc = "0x50 - Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr8(&self) -> &STHR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x50 - Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr8(&self) -> &SRBR8 { - unsafe { &*(self as *const Self).cast::().add(80usize).cast() } + unsafe { &*(self as *const Self).cast::().add(80).cast() } } #[doc = "0x54 - Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr9(&self) -> &STHR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x54 - Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr9(&self) -> &SRBR9 { - unsafe { &*(self as *const Self).cast::().add(84usize).cast() } + unsafe { &*(self as *const Self).cast::().add(84).cast() } } #[doc = "0x58 - Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr10(&self) -> &STHR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x58 - Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr10(&self) -> &SRBR10 { - unsafe { &*(self as *const Self).cast::().add(88usize).cast() } + unsafe { &*(self as *const Self).cast::().add(88).cast() } } #[doc = "0x5c - Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr11(&self) -> &STHR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x5c - Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr11(&self) -> &SRBR11 { - unsafe { &*(self as *const Self).cast::().add(92usize).cast() } + unsafe { &*(self as *const Self).cast::().add(92).cast() } } #[doc = "0x60 - Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr12(&self) -> &STHR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x60 - Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr12(&self) -> &SRBR12 { - unsafe { &*(self as *const Self).cast::().add(96usize).cast() } + unsafe { &*(self as *const Self).cast::().add(96).cast() } } #[doc = "0x64 - Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr13(&self) -> &STHR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x64 - Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr13(&self) -> &SRBR13 { - unsafe { &*(self as *const Self).cast::().add(100usize).cast() } + unsafe { &*(self as *const Self).cast::().add(100).cast() } } #[doc = "0x68 - Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr14(&self) -> &STHR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x68 - Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr14(&self) -> &SRBR14 { - unsafe { &*(self as *const Self).cast::().add(104usize).cast() } + unsafe { &*(self as *const Self).cast::().add(104).cast() } } #[doc = "0x6c - Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn sthr15(&self) -> &STHR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } } #[doc = "0x6c - Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn srbr15(&self) -> &SRBR15 { - unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + unsafe { &*(self as *const Self).cast::().add(108).cast() } + } + #[doc = "0x70 - FIFO Access Register"] + #[inline(always)] + pub const fn far(&self) -> &FAR { + &self.far + } + #[doc = "0x74 - Transmit FIFO Read"] + #[inline(always)] + pub const fn tfr(&self) -> &TFR { + &self.tfr + } + #[doc = "0x78 - Receive FIFO Write"] + #[inline(always)] + pub const fn rfw(&self) -> &RFW { + &self.rfw + } + #[doc = "0x7c - UART Status Register"] + #[inline(always)] + pub const fn usr(&self) -> &USR { + &self.usr + } + #[doc = "0x80 - Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn tfl(&self) -> &TFL { + &self.tfl + } + #[doc = "0x84 - Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn rfl(&self) -> &RFL { + &self.rfl + } + #[doc = "0x88 - Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srr(&self) -> &SRR { + &self.srr + } + #[doc = "0x8c - Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srts(&self) -> &SRTS { + &self.srts + } + #[doc = "0x90 - Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sbcr(&self) -> &SBCR { + &self.sbcr + } + #[doc = "0x94 - Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sdmam(&self) -> &SDMAM { + &self.sdmam + } + #[doc = "0x98 - Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn sfe(&self) -> &SFE { + &self.sfe + } + #[doc = "0x9c - Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn srt(&self) -> &SRT { + &self.srt + } + #[doc = "0xa0 - Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn stet(&self) -> &STET { + &self.stet + } + #[doc = "0xa4 - Halt TX"] + #[inline(always)] + pub const fn htx(&self) -> &HTX { + &self.htx + } + #[doc = "0xa8 - DMA Software Acknowledge"] + #[inline(always)] + pub const fn dmasa(&self) -> &DMASA { + &self.dmasa + } + #[doc = "0xf4 - Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] + #[inline(always)] + pub const fn cpr(&self) -> &CPR { + &self.cpr } #[doc = "0xf8 - Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ctr(&self) -> &CTR { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } #[doc = "0xf8 - UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] #[inline(always)] pub const fn ucv(&self) -> &UCV { - unsafe { &*(self as *const Self).cast::().add(248usize).cast() } + unsafe { &*(self as *const Self).cast::().add(248).cast() } } } -#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rbr`] +#[doc = "rbr (rw) register accessor: Receive Buffer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbr`] module"] pub type RBR = crate::Reg; #[doc = "Receive Buffer Register"] pub mod rbr; -#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`thr`] +#[doc = "thr (rw) register accessor: Transmit Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thr`] module"] pub type THR = crate::Reg; #[doc = "Transmit Holding Register"] pub mod thr; -#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dll`] +#[doc = "dll (rw) register accessor: Divisor Latch Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll`] module"] pub type DLL = crate::Reg; #[doc = "Divisor Latch Low"] pub mod dll; -#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dlh`] +#[doc = "dlh (rw) register accessor: Divisor Latch High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlh`] module"] pub type DLH = crate::Reg; #[doc = "Divisor Latch High"] pub mod dlh; -#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +#[doc = "ier (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`iir`] +#[doc = "iir (rw) register accessor: Interrupt Identity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] module"] pub type IIR = crate::Reg; #[doc = "Interrupt Identity Register"] pub mod iir; -#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fcr`] +#[doc = "fcr (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] module"] pub type FCR = crate::Reg; #[doc = "FIFO Control Register"] pub mod fcr; -#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lcr`] +#[doc = "lcr (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] module"] pub type LCR = crate::Reg; #[doc = "Line Control Register"] pub mod lcr; -#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mcr`] +#[doc = "mcr (rw) register accessor: Modem Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] module"] pub type MCR = crate::Reg; #[doc = "Modem Control Register"] pub mod mcr; -#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lsr`] +#[doc = "lsr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] module"] pub type LSR = crate::Reg; #[doc = "Line Status Register"] pub mod lsr; -#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msr`] +#[doc = "msr (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] module"] pub type MSR = crate::Reg; #[doc = "Line Status Register"] pub mod msr; -#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scr`] +#[doc = "scr (rw) register accessor: Scratch Pad Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`] module"] pub type SCR = crate::Reg; #[doc = "Scratch Pad Register"] pub mod scr; -#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdll`] +#[doc = "lpdll (rw) register accessor: Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdll`] module"] pub type LPDLL = crate::Reg; #[doc = "Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdll; -#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lpdlh`] +#[doc = "lpdlh (rw) register accessor: Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpdlh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpdlh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpdlh`] module"] pub type LPDLH = crate::Reg; #[doc = "Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero."] pub mod lpdlh; -#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr0`] +#[doc = "srbr0 (rw) register accessor: Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr0`] module"] pub type SRBR0 = crate::Reg; #[doc = "Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr0; -#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr0`] +#[doc = "sthr0 (rw) register accessor: Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr0`] module"] pub type STHR0 = crate::Reg; #[doc = "Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr0; -#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr1`] +#[doc = "srbr1 (rw) register accessor: Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr1`] module"] pub type SRBR1 = crate::Reg; #[doc = "Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr1; -#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr1`] +#[doc = "sthr1 (rw) register accessor: Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr1`] module"] pub type STHR1 = crate::Reg; #[doc = "Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr1; -#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr2`] +#[doc = "srbr2 (rw) register accessor: Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr2`] module"] pub type SRBR2 = crate::Reg; #[doc = "Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr2; -#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr2`] +#[doc = "sthr2 (rw) register accessor: Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr2`] module"] pub type STHR2 = crate::Reg; #[doc = "Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr2; -#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr3`] +#[doc = "srbr3 (rw) register accessor: Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr3`] module"] pub type SRBR3 = crate::Reg; #[doc = "Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr3; -#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr3`] +#[doc = "sthr3 (rw) register accessor: Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr3`] module"] pub type STHR3 = crate::Reg; #[doc = "Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr3; -#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr4`] +#[doc = "srbr4 (rw) register accessor: Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr4`] module"] pub type SRBR4 = crate::Reg; #[doc = "Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr4; -#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr4`] +#[doc = "sthr4 (rw) register accessor: Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr4`] module"] pub type STHR4 = crate::Reg; #[doc = "Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr4; -#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr5`] +#[doc = "srbr5 (rw) register accessor: Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr5`] module"] pub type SRBR5 = crate::Reg; #[doc = "Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr5; -#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr5`] +#[doc = "sthr5 (rw) register accessor: Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr5`] module"] pub type STHR5 = crate::Reg; #[doc = "Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr5; -#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr6`] +#[doc = "srbr6 (rw) register accessor: Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr6`] module"] pub type SRBR6 = crate::Reg; #[doc = "Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr6; -#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr6`] +#[doc = "sthr6 (rw) register accessor: Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr6`] module"] pub type STHR6 = crate::Reg; #[doc = "Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr6; -#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr7`] +#[doc = "srbr7 (rw) register accessor: Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr7`] module"] pub type SRBR7 = crate::Reg; #[doc = "Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr7; -#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr7`] +#[doc = "sthr7 (rw) register accessor: Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr7`] module"] pub type STHR7 = crate::Reg; #[doc = "Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr7; -#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr8`] +#[doc = "srbr8 (rw) register accessor: Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr8`] module"] pub type SRBR8 = crate::Reg; #[doc = "Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr8; -#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr8`] +#[doc = "sthr8 (rw) register accessor: Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr8`] module"] pub type STHR8 = crate::Reg; #[doc = "Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr8; -#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr9`] +#[doc = "srbr9 (rw) register accessor: Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr9`] module"] pub type SRBR9 = crate::Reg; #[doc = "Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr9; -#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr9`] +#[doc = "sthr9 (rw) register accessor: Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr9`] module"] pub type STHR9 = crate::Reg; #[doc = "Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr9; -#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr10`] +#[doc = "srbr10 (rw) register accessor: Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr10`] module"] pub type SRBR10 = crate::Reg; #[doc = "Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr10; -#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr10`] +#[doc = "sthr10 (rw) register accessor: Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr10`] module"] pub type STHR10 = crate::Reg; #[doc = "Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr10; -#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr11`] +#[doc = "srbr11 (rw) register accessor: Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr11`] module"] pub type SRBR11 = crate::Reg; #[doc = "Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr11; -#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr11`] +#[doc = "sthr11 (rw) register accessor: Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr11`] module"] pub type STHR11 = crate::Reg; #[doc = "Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr11; -#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr12`] +#[doc = "srbr12 (rw) register accessor: Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr12`] module"] pub type SRBR12 = crate::Reg; #[doc = "Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr12; -#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr12`] +#[doc = "sthr12 (rw) register accessor: Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr12`] module"] pub type STHR12 = crate::Reg; #[doc = "Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr12; -#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr13`] +#[doc = "srbr13 (rw) register accessor: Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr13`] module"] pub type SRBR13 = crate::Reg; #[doc = "Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr13; -#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr13`] +#[doc = "sthr13 (rw) register accessor: Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr13`] module"] pub type STHR13 = crate::Reg; #[doc = "Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr13; -#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr14`] +#[doc = "srbr14 (rw) register accessor: Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr14`] module"] pub type SRBR14 = crate::Reg; #[doc = "Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr14; -#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr14`] +#[doc = "sthr14 (rw) register accessor: Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr14`] module"] pub type STHR14 = crate::Reg; #[doc = "Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr14; -#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srbr15`] +#[doc = "srbr15 (rw) register accessor: Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srbr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srbr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srbr15`] module"] pub type SRBR15 = crate::Reg; #[doc = "Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srbr15; -#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sthr15`] +#[doc = "sthr15 (rw) register accessor: Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sthr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sthr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sthr15`] module"] pub type STHR15 = crate::Reg; #[doc = "Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sthr15; -#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`far`] +#[doc = "far (rw) register accessor: FIFO Access Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@far`] module"] pub type FAR = crate::Reg; #[doc = "FIFO Access Register"] pub mod far; -#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfr`] +#[doc = "tfr (rw) register accessor: Transmit FIFO Read\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfr`] module"] pub type TFR = crate::Reg; #[doc = "Transmit FIFO Read"] pub mod tfr; -#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfw`] +#[doc = "rfw (rw) register accessor: Receive FIFO Write\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfw`] module"] pub type RFW = crate::Reg; #[doc = "Receive FIFO Write"] pub mod rfw; -#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`usr`] +#[doc = "usr (rw) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usr`] module"] pub type USR = crate::Reg; #[doc = "UART Status Register"] pub mod usr; -#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfl`] +#[doc = "tfl (rw) register accessor: Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tfl`] module"] pub type TFL = crate::Reg; #[doc = "Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod tfl; -#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfl`] +#[doc = "rfl (rw) register accessor: Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rfl`] module"] pub type RFL = crate::Reg; #[doc = "Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod rfl; -#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srr`] +#[doc = "srr (rw) register accessor: Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srr`] module"] pub type SRR = crate::Reg; #[doc = "Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srr; -#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srts`] +#[doc = "srts (rw) register accessor: Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srts`] module"] pub type SRTS = crate::Reg; #[doc = "Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srts; -#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sbcr`] +#[doc = "sbcr (rw) register accessor: Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sbcr`] module"] pub type SBCR = crate::Reg; #[doc = "Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sbcr; -#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sdmam`] +#[doc = "sdmam (rw) register accessor: Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdmam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdmam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdmam`] module"] pub type SDMAM = crate::Reg; #[doc = "Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sdmam; -#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sfe`] +#[doc = "sfe (rw) register accessor: Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfe`] module"] pub type SFE = crate::Reg; #[doc = "Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod sfe; -#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`srt`] +#[doc = "srt (rw) register accessor: Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`srt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srt`] module"] pub type SRT = crate::Reg; #[doc = "Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod srt; -#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`stet`] +#[doc = "stet (rw) register accessor: Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stet::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stet::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stet`] module"] pub type STET = crate::Reg; #[doc = "Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero."] pub mod stet; -#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`htx`] +#[doc = "htx (rw) register accessor: Halt TX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`htx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`htx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@htx`] module"] pub type HTX = crate::Reg; #[doc = "Halt TX"] pub mod htx; -#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dmasa`] +#[doc = "dmasa (rw) register accessor: DMA Software Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasa`] module"] pub type DMASA = crate::Reg; #[doc = "DMA Software Acknowledge"] pub mod dmasa; -#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cpr`] +#[doc = "cpr (rw) register accessor: Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpr`] module"] pub type CPR = crate::Reg; #[doc = "Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero."] pub mod cpr; -#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ucv`] +#[doc = "ucv (rw) register accessor: UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ucv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ucv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucv`] module"] pub type UCV = crate::Reg; #[doc = "UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] pub mod ucv; -#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctr`] +#[doc = "ctr (rw) register accessor: Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"] pub type CTR = crate::Reg; #[doc = "Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero."] diff --git a/jh7110-vf2-13b-pac/src/uart5/cpr.rs b/jh7110-vf2-13b-pac/src/uart5/cpr.rs index 4807519..332b584 100644 --- a/jh7110-vf2-13b-pac/src/uart5/cpr.rs +++ b/jh7110-vf2-13b-pac/src/uart5/cpr.rs @@ -89,7 +89,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/ctr.rs b/jh7110-vf2-13b-pac/src/uart5/ctr.rs index c3760d5..ac70194 100644 --- a/jh7110-vf2-13b-pac/src/uart5/ctr.rs +++ b/jh7110-vf2-13b-pac/src/uart5/ctr.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/dlh.rs b/jh7110-vf2-13b-pac/src/uart5/dlh.rs index 3257a2d..2a788c1 100644 --- a/jh7110-vf2-13b-pac/src/uart5/dlh.rs +++ b/jh7110-vf2-13b-pac/src/uart5/dlh.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLH_R = crate::FieldReader; #[doc = "Field `dlh` writer - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dlh(&mut self) -> DLH_W { - DLH_W::new(self) + pub fn dlh(&mut self) -> DLH_W { + DLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/dll.rs b/jh7110-vf2-13b-pac/src/uart5/dll.rs index 9c9daff..1c9d765 100644 --- a/jh7110-vf2-13b-pac/src/uart5/dll.rs +++ b/jh7110-vf2-13b-pac/src/uart5/dll.rs @@ -7,7 +7,7 @@ is zero). The output baud rate is equal to the serial clock (pclk if one clock d pub type DLL_R = crate::FieldReader; #[doc = "Field `dll` writer - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type DLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type DLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] @@ -21,10 +21,14 @@ impl W { is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn dll(&mut self) -> DLL_W { - DLL_W::new(self) + pub fn dll(&mut self) -> DLL_W { + DLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/dmasa.rs b/jh7110-vf2-13b-pac/src/uart5/dmasa.rs index 7bcfb26..2fc4e6d 100644 --- a/jh7110-vf2-13b-pac/src/uart5/dmasa.rs +++ b/jh7110-vf2-13b-pac/src/uart5/dmasa.rs @@ -3,15 +3,19 @@ pub type R = crate::R; #[doc = "Register `dmasa` writer"] pub type W = crate::W; #[doc = "Field `dmasa` writer - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type DMASA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMASA_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn dmasa(&mut self) -> DMASA_W { - DMASA_W::new(self) + pub fn dmasa(&mut self) -> DMASA_W { + DMASA_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/far.rs b/jh7110-vf2-13b-pac/src/uart5/far.rs index 3b3bcb1..d52059a 100644 --- a/jh7110-vf2-13b-pac/src/uart5/far.rs +++ b/jh7110-vf2-13b-pac/src/uart5/far.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `far` reader - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] pub type FAR_R = crate::BitReader; #[doc = "Field `far` writer - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] -pub type FAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FAR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty."] #[inline(always)] #[must_use] - pub fn far(&mut self) -> FAR_W { - FAR_W::new(self) + pub fn far(&mut self) -> FAR_W { + FAR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/fcr.rs b/jh7110-vf2-13b-pac/src/uart5/fcr.rs index 4fbb499..a64a60b 100644 --- a/jh7110-vf2-13b-pac/src/uart5/fcr.rs +++ b/jh7110-vf2-13b-pac/src/uart5/fcr.rs @@ -3,55 +3,59 @@ pub type R = crate::R; #[doc = "Register `fcr` writer"] pub type W = crate::W; #[doc = "Field `fifoe` writer - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] -pub type FIFOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type FIFOE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfifor` writer - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfifor` writer - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFIFOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFIFOR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dmam` writer - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] -pub type DMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DMAM_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `tet` writer - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type TET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type TET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `rt` writer - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type RT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type RT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl W { #[doc = "Bit 0 - FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset."] #[inline(always)] #[must_use] - pub fn fifoe(&mut self) -> FIFOE_W { - FIFOE_W::new(self) + pub fn fifoe(&mut self) -> FIFOE_W { + FIFOE_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfifor(&mut self) -> RFIFOR_W { - RFIFOR_W::new(self) + pub fn rfifor(&mut self) -> RFIFOR_W { + RFIFOR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfifor(&mut self) -> XFIFOR_W { - XFIFOR_W::new(self) + pub fn xfifor(&mut self) -> XFIFOR_W { + XFIFOR_W::new(self, 2) } #[doc = "Bit 3 - DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn dmam(&mut self) -> DMAM_W { - DMAM_W::new(self) + pub fn dmam(&mut self) -> DMAM_W { + DMAM_W::new(self, 3) } #[doc = "Bits 4:5 - TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn tet(&mut self) -> TET_W { - TET_W::new(self) + pub fn tet(&mut self) -> TET_W { + TET_W::new(self, 4) } #[doc = "Bits 6:7 - RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn rt(&mut self) -> RT_W { - RT_W::new(self) + pub fn rt(&mut self) -> RT_W { + RT_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/htx.rs b/jh7110-vf2-13b-pac/src/uart5/htx.rs index ad027bd..fc82325 100644 --- a/jh7110-vf2-13b-pac/src/uart5/htx.rs +++ b/jh7110-vf2-13b-pac/src/uart5/htx.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `htx` reader - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] pub type HTX_R = crate::BitReader; #[doc = "Field `htx` writer - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] -pub type HTX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type HTX_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation."] #[inline(always)] #[must_use] - pub fn htx(&mut self) -> HTX_W { - HTX_W::new(self) + pub fn htx(&mut self) -> HTX_W { + HTX_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/ier.rs b/jh7110-vf2-13b-pac/src/uart5/ier.rs index 006fbea..3cf3d7f 100644 --- a/jh7110-vf2-13b-pac/src/uart5/ier.rs +++ b/jh7110-vf2-13b-pac/src/uart5/ier.rs @@ -5,23 +5,23 @@ pub type W = crate::W; #[doc = "Field `erbfi` reader - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] pub type ERBFI_R = crate::BitReader; #[doc = "Field `erbfi` writer - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] -pub type ERBFI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ERBFI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `etbei` reader - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] pub type ETBEI_R = crate::BitReader; #[doc = "Field `etbei` writer - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ETBEI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ETBEI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `elsi` reader - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] pub type ELSI_R = crate::BitReader; #[doc = "Field `elsi` writer - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] -pub type ELSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type ELSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `edssi` reader - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] pub type EDSSI_R = crate::BitReader; #[doc = "Field `edssi` writer - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] -pub type EDSSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EDSSI_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ptime` reader - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] pub type PTIME_R = crate::BitReader; #[doc = "Field `ptime` writer - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] -pub type PTIME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PTIME_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] @@ -53,34 +53,38 @@ impl W { #[doc = "Bit 0 - Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn erbfi(&mut self) -> ERBFI_W { - ERBFI_W::new(self) + pub fn erbfi(&mut self) -> ERBFI_W { + ERBFI_W::new(self, 0) } #[doc = "Bit 1 - Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn etbei(&mut self) -> ETBEI_W { - ETBEI_W::new(self) + pub fn etbei(&mut self) -> ETBEI_W { + ETBEI_W::new(self, 1) } #[doc = "Bit 2 - Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn elsi(&mut self) -> ELSI_W { - ELSI_W::new(self) + pub fn elsi(&mut self) -> ELSI_W { + ELSI_W::new(self, 2) } #[doc = "Bit 3 - Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn edssi(&mut self) -> EDSSI_W { - EDSSI_W::new(self) + pub fn edssi(&mut self) -> EDSSI_W { + EDSSI_W::new(self, 3) } #[doc = "Bit 7 - Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled"] #[inline(always)] #[must_use] - pub fn ptime(&mut self) -> PTIME_W { - PTIME_W::new(self) + pub fn ptime(&mut self) -> PTIME_W { + PTIME_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/iir.rs b/jh7110-vf2-13b-pac/src/uart5/iir.rs index c90daa5..c949f03 100644 --- a/jh7110-vf2-13b-pac/src/uart5/iir.rs +++ b/jh7110-vf2-13b-pac/src/uart5/iir.rs @@ -19,7 +19,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/lcr.rs b/jh7110-vf2-13b-pac/src/uart5/lcr.rs index acd83ee..3bc10c2 100644 --- a/jh7110-vf2-13b-pac/src/uart5/lcr.rs +++ b/jh7110-vf2-13b-pac/src/uart5/lcr.rs @@ -7,7 +7,7 @@ is zero), always readable. This is used to select the number of data bits per ch pub type DLS_R = crate::FieldReader; #[doc = "Field `dls` writer - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] -pub type DLS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type DLS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `stop` reader - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] @@ -15,31 +15,31 @@ pub type STOP_R = crate::BitReader; #[doc = "Field `stop` writer - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] -pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `pen` reader - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] pub type PEN_R = crate::BitReader; #[doc = "Field `pen` writer - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] -pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `eps` reader - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] pub type EPS_R = crate::BitReader; #[doc = "Field `eps` writer - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] -pub type EPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type EPS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `bc` reader - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] pub type BC_R = crate::BitReader; #[doc = "Field `bc` writer - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] -pub type BC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type BC_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `dlab` reader - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] pub type DLAB_R = crate::BitReader; #[doc = "Field `dlab` writer - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] -pub type DLAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DLAB_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:1 - Data Length Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] @@ -84,46 +84,50 @@ impl W { is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits"] #[inline(always)] #[must_use] - pub fn dls(&mut self) -> DLS_W { - DLS_W::new(self) + pub fn dls(&mut self) -> DLS_W { + DLS_W::new(self, 0) } #[doc = "Bit 2 - Number of stop bits. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR\\[1:0\\] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR\\[1:0\\]) is zero, else 2 stop bit"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W { - STOP_W::new(self) + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 2) } #[doc = "Bit 3 - Parity Enable. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled"] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W { - PEN_W::new(self) + pub fn pen(&mut self) -> PEN_W { + PEN_W::new(self, 3) } #[doc = "Bit 4 - Even Parity Select. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked."] #[inline(always)] #[must_use] - pub fn eps(&mut self) -> EPS_W { - EPS_W::new(self) + pub fn eps(&mut self) -> EPS_W { + EPS_W::new(self, 4) } #[doc = "Bit 6 - Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low."] #[inline(always)] #[must_use] - pub fn bc(&mut self) -> BC_W { - BC_W::new(self) + pub fn bc(&mut self) -> BC_W { + BC_W::new(self, 6) } #[doc = "Bit 7 - Divisor Latch Access Bit. Writeable only when UART is not busy (USR\\[0\\] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers."] #[inline(always)] #[must_use] - pub fn dlab(&mut self) -> DLAB_W { - DLAB_W::new(self) + pub fn dlab(&mut self) -> DLAB_W { + DLAB_W::new(self, 7) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/lpdlh.rs b/jh7110-vf2-13b-pac/src/uart5/lpdlh.rs index 8a910c8..095afa9 100644 --- a/jh7110-vf2-13b-pac/src/uart5/lpdlh.rs +++ b/jh7110-vf2-13b-pac/src/uart5/lpdlh.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdlh` reader - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] pub type LPDLH_R = crate::FieldReader; #[doc = "Field `lpdlh` writer - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] -pub type LPDLH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data"] #[inline(always)] #[must_use] - pub fn lpdlh(&mut self) -> LPDLH_W { - LPDLH_W::new(self) + pub fn lpdlh(&mut self) -> LPDLH_W { + LPDLH_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/lpdll.rs b/jh7110-vf2-13b-pac/src/uart5/lpdll.rs index 7780651..21d0018 100644 --- a/jh7110-vf2-13b-pac/src/uart5/lpdll.rs +++ b/jh7110-vf2-13b-pac/src/uart5/lpdll.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `lpdll` reader - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] pub type LPDLL_R = crate::FieldReader; #[doc = "Field `lpdll` writer - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] -pub type LPDLL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type LPDLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR\\[7\\]) is set and the UART is not busy (USR\\[0\\]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data."] #[inline(always)] #[must_use] - pub fn lpdll(&mut self) -> LPDLL_W { - LPDLL_W::new(self) + pub fn lpdll(&mut self) -> LPDLL_W { + LPDLL_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/lsr.rs b/jh7110-vf2-13b-pac/src/uart5/lsr.rs index f576c10..ff2ab48 100644 --- a/jh7110-vf2-13b-pac/src/uart5/lsr.rs +++ b/jh7110-vf2-13b-pac/src/uart5/lsr.rs @@ -73,7 +73,11 @@ set to one). This is used to indicate if there is at least one parity error, fra } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/mcr.rs b/jh7110-vf2-13b-pac/src/uart5/mcr.rs index 6932ee7..9c93108 100644 --- a/jh7110-vf2-13b-pac/src/uart5/mcr.rs +++ b/jh7110-vf2-13b-pac/src/uart5/mcr.rs @@ -7,7 +7,7 @@ set to one), the dtr_n output is held inactive high while the value of this loca pub type DTR_R = crate::BitReader; #[doc = "Field `dtr` writer - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type DTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rts` reader - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR\\[5\\] @@ -23,19 +23,19 @@ set to one) and FIFOs enable (FCR\\[0\\] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR\\[1\\] is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RTS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out1` reader - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT1_R = crate::BitReader; #[doc = "Field `out1` writer - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT1_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `out2` reader - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] pub type OUT2_R = crate::BitReader; #[doc = "Field `out2` writer - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] -pub type OUT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type OUT2_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `lb` reader - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] @@ -43,15 +43,15 @@ pub type LB_R = crate::BitReader; #[doc = "Field `lb` writer - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] -pub type LB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type LB_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `afce` reader - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] pub type AFCE_R = crate::BitReader; #[doc = "Field `afce` writer - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] -pub type AFCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type AFCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `sire` reader - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] pub type SIRE_R = crate::BitReader; #[doc = "Field `sire` writer - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] -pub type SIRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SIRE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR\\[4\\] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] @@ -105,8 +105,8 @@ impl W { set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn dtr(&mut self) -> DTR_W { - DTR_W::new(self) + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 0) } #[doc = "Bit 1 - Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] set to zero), the rts_n signal is set low by programming MCR\\[1\\] @@ -117,44 +117,48 @@ is set low. Note that in Loopback mode (MCR\\[4\\] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W { - RTS_W::new(self) + pub fn rts(&mut self) -> RTS_W { + RTS_W::new(self, 1) } #[doc = "Bit 2 - OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out1(&mut self) -> OUT1_W { - OUT1_W::new(self) + pub fn out1(&mut self) -> OUT1_W { + OUT1_W::new(self, 2) } #[doc = "Bit 3 - OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR\\[4\\] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn out2(&mut self) -> OUT2_W { - OUT2_W::new(self) + pub fn out2(&mut self) -> OUT2_W { + OUT2_W::new(self, 3) } #[doc = "Bit 4 - LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR\\[6\\] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR\\[6\\] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line"] #[inline(always)] #[must_use] - pub fn lb(&mut self) -> LB_W { - LB_W::new(self) + pub fn lb(&mut self) -> LB_W { + LB_W::new(self, 4) } #[doc = "Bit 5 - Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled"] #[inline(always)] #[must_use] - pub fn afce(&mut self) -> AFCE_W { - AFCE_W::new(self) + pub fn afce(&mut self) -> AFCE_W { + AFCE_W::new(self, 5) } #[doc = "Bit 6 - SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled"] #[inline(always)] #[must_use] - pub fn sire(&mut self) -> SIRE_W { - SIRE_W::new(self) + pub fn sire(&mut self) -> SIRE_W { + SIRE_W::new(self, 6) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/msr.rs b/jh7110-vf2-13b-pac/src/uart5/msr.rs index 65c526b..b54fc38 100644 --- a/jh7110-vf2-13b-pac/src/uart5/msr.rs +++ b/jh7110-vf2-13b-pac/src/uart5/msr.rs @@ -93,7 +93,11 @@ set to one), DCD is the same as MCR\\[3\\] } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/rbr.rs b/jh7110-vf2-13b-pac/src/uart5/rbr.rs index 03003ed..403adcf 100644 --- a/jh7110-vf2-13b-pac/src/uart5/rbr.rs +++ b/jh7110-vf2-13b-pac/src/uart5/rbr.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/rfl.rs b/jh7110-vf2-13b-pac/src/uart5/rfl.rs index 2aea928..59355cb 100644 --- a/jh7110-vf2-13b-pac/src/uart5/rfl.rs +++ b/jh7110-vf2-13b-pac/src/uart5/rfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/rfw.rs b/jh7110-vf2-13b-pac/src/uart5/rfw.rs index 7b917de..490472d 100644 --- a/jh7110-vf2-13b-pac/src/uart5/rfw.rs +++ b/jh7110-vf2-13b-pac/src/uart5/rfw.rs @@ -4,36 +4,40 @@ pub type R = crate::R; pub type W = crate::W; #[doc = "Field `rfwd` writer - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] -pub type RFWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type RFWD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `rfpe` writer - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] -pub type RFPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFPE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rffe` writer - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] -pub type RFFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bits 0:7 - Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR."] #[inline(always)] #[must_use] - pub fn rfwd(&mut self) -> RFWD_W { - RFWD_W::new(self) + pub fn rfwd(&mut self) -> RFWD_W { + RFWD_W::new(self, 0) } #[doc = "Bit 8 - Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rfpe(&mut self) -> RFPE_W { - RFPE_W::new(self) + pub fn rfpe(&mut self) -> RFPE_W { + RFPE_W::new(self, 8) } #[doc = "Bit 9 - Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR\\[0\\] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR."] #[inline(always)] #[must_use] - pub fn rffe(&mut self) -> RFFE_W { - RFFE_W::new(self) + pub fn rffe(&mut self) -> RFFE_W { + RFFE_W::new(self, 9) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sbcr.rs b/jh7110-vf2-13b-pac/src/uart5/sbcr.rs index 73914e9..5a120c0 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sbcr.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sbcr.rs @@ -7,7 +7,7 @@ pub type W = crate::W; pub type SBCR_R = crate::BitReader; #[doc = "Field `sbcr` writer - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] -pub type SBCR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SBCR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Break Control Bit. This is a shadow register for the Break bit (LCR\\[6\\]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR\\[4\\], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR\\[6\\] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] @@ -21,10 +21,14 @@ impl W { = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver."] #[inline(always)] #[must_use] - pub fn sbcr(&mut self) -> SBCR_W { - SBCR_W::new(self) + pub fn sbcr(&mut self) -> SBCR_W { + SBCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/scr.rs b/jh7110-vf2-13b-pac/src/uart5/scr.rs index 744352e..f46ba21 100644 --- a/jh7110-vf2-13b-pac/src/uart5/scr.rs +++ b/jh7110-vf2-13b-pac/src/uart5/scr.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `scr` reader - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] pub type SCR_R = crate::FieldReader; #[doc = "Field `scr` writer - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] -pub type SCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:7 - This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart."] #[inline(always)] #[must_use] - pub fn scr(&mut self) -> SCR_W { - SCR_W::new(self) + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sdmam.rs b/jh7110-vf2-13b-pac/src/uart5/sdmam.rs index 684377c..4be4fa2 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sdmam.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sdmam.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sdmam` reader - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] pub type SDMAM_R = crate::BitReader; #[doc = "Field `sdmam` writer - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] -pub type SDMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SDMAM_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR\\[3\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1"] #[inline(always)] #[must_use] - pub fn sdmam(&mut self) -> SDMAM_W { - SDMAM_W::new(self) + pub fn sdmam(&mut self) -> SDMAM_W { + SDMAM_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sfe.rs b/jh7110-vf2-13b-pac/src/uart5/sfe.rs index e68b088..ed26fee 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sfe.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sfe.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `sfe` reader - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] pub type SFE_R = crate::BitReader; #[doc = "Field `sfe` writer - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] -pub type SFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SFE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bit 0 - Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR\\[0\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset."] #[inline(always)] #[must_use] - pub fn sfe(&mut self) -> SFE_W { - SFE_W::new(self) + pub fn sfe(&mut self) -> SFE_W { + SFE_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srbr0.rs b/jh7110-vf2-13b-pac/src/uart5/srbr0.rs index 4076661..4e44d1a 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srbr0.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srbr0.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srbr1.rs b/jh7110-vf2-13b-pac/src/uart5/srbr1.rs index 2f31b75..46bc479 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srbr1.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srbr1.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srbr10.rs b/jh7110-vf2-13b-pac/src/uart5/srbr10.rs index 3639d65..70297bf 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srbr10.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srbr10.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srbr11.rs b/jh7110-vf2-13b-pac/src/uart5/srbr11.rs index 92d29b1..28d0277 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srbr11.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srbr11.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srbr12.rs b/jh7110-vf2-13b-pac/src/uart5/srbr12.rs index 52e795e..3eccd9a 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srbr12.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srbr12.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srbr13.rs b/jh7110-vf2-13b-pac/src/uart5/srbr13.rs index 50aae40..e47e4e4 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srbr13.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srbr13.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srbr14.rs b/jh7110-vf2-13b-pac/src/uart5/srbr14.rs index cb25819..8f23662 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srbr14.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srbr14.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srbr15.rs b/jh7110-vf2-13b-pac/src/uart5/srbr15.rs index b25ae46..1dac092 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srbr15.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srbr15.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srbr2.rs b/jh7110-vf2-13b-pac/src/uart5/srbr2.rs index 9f3236c..afb0617 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srbr2.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srbr2.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srbr3.rs b/jh7110-vf2-13b-pac/src/uart5/srbr3.rs index 5c1edda..0ff3650 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srbr3.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srbr3.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srbr4.rs b/jh7110-vf2-13b-pac/src/uart5/srbr4.rs index e6bee93..59560c4 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srbr4.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srbr4.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srbr5.rs b/jh7110-vf2-13b-pac/src/uart5/srbr5.rs index e599009..763e341 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srbr5.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srbr5.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srbr6.rs b/jh7110-vf2-13b-pac/src/uart5/srbr6.rs index b0155b3..78e2a40 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srbr6.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srbr6.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srbr7.rs b/jh7110-vf2-13b-pac/src/uart5/srbr7.rs index b8f9b88..0723ff0 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srbr7.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srbr7.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srbr8.rs b/jh7110-vf2-13b-pac/src/uart5/srbr8.rs index f57b044..4702cd9 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srbr8.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srbr8.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srbr9.rs b/jh7110-vf2-13b-pac/src/uart5/srbr9.rs index 3a160aa..e1a262e 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srbr9.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srbr9.rs @@ -16,7 +16,11 @@ set to one), this register accesses the head of the receive FIFO. If the receive } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srr.rs b/jh7110-vf2-13b-pac/src/uart5/srr.rs index 6671199..fdb0c0a 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srr.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srr.rs @@ -3,31 +3,35 @@ pub type R = crate::R; #[doc = "Register `srr` writer"] pub type W = crate::W; #[doc = "Field `ur` writer - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] -pub type UR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type UR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `rfr` writer - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type RFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type RFR_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `xfr` writer - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] -pub type XFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type XFR_W<'a, REG> = crate::BitWriter<'a, REG>; impl W { #[doc = "Bit 0 - UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset."] #[inline(always)] #[must_use] - pub fn ur(&mut self) -> UR_W { - UR_W::new(self) + pub fn ur(&mut self) -> UR_W { + UR_W::new(self, 0) } #[doc = "Bit 1 - RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR\\[1\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn rfr(&mut self) -> RFR_W { - RFR_W::new(self) + pub fn rfr(&mut self) -> RFR_W { + RFR_W::new(self, 1) } #[doc = "Bit 2 - XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR\\[2\\]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit."] #[inline(always)] #[must_use] - pub fn xfr(&mut self) -> XFR_W { - XFR_W::new(self) + pub fn xfr(&mut self) -> XFR_W { + XFR_W::new(self, 2) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srt.rs b/jh7110-vf2-13b-pac/src/uart5/srt.rs index fed4f1f..da909fd 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srt.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srt.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `srt` reader - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] pub type SRT_R = crate::FieldReader; #[doc = "Field `srt` writer - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] -pub type SRT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type SRT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR\\[7:6\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR\\[3\\]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full"] #[inline(always)] #[must_use] - pub fn srt(&mut self) -> SRT_W { - SRT_W::new(self) + pub fn srt(&mut self) -> SRT_W { + SRT_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/srts.rs b/jh7110-vf2-13b-pac/src/uart5/srts.rs index ceb0ee4..cf1e2a9 100644 --- a/jh7110-vf2-13b-pac/src/uart5/srts.rs +++ b/jh7110-vf2-13b-pac/src/uart5/srts.rs @@ -15,7 +15,7 @@ pub type SRTS_R = crate::BitReader; = 1) and FIFOs enable (FCR\\[0\\] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR\\[4\\] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] -pub type SRTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +pub type SRTS_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Shadow Request to Send. This is a shadow register for the RTS bit (MCR\\[1\\]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR\\[5\\] = 0), the rts_n signal is set low by programming MCR\\[1\\] @@ -37,10 +37,14 @@ impl W { = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input."] #[inline(always)] #[must_use] - pub fn srts(&mut self) -> SRTS_W { - SRTS_W::new(self) + pub fn srts(&mut self) -> SRTS_W { + SRTS_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/stet.rs b/jh7110-vf2-13b-pac/src/uart5/stet.rs index acb8ba1..503dc8a 100644 --- a/jh7110-vf2-13b-pac/src/uart5/stet.rs +++ b/jh7110-vf2-13b-pac/src/uart5/stet.rs @@ -5,7 +5,7 @@ pub type W = crate::W; #[doc = "Field `stet` reader - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] pub type STET_R = crate::FieldReader; #[doc = "Field `stet` writer - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] -pub type STET_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; +pub type STET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] @@ -17,10 +17,14 @@ impl W { #[doc = "Bits 0:1 - Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR\\[5:4\\]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full"] #[inline(always)] #[must_use] - pub fn stet(&mut self) -> STET_W { - STET_W::new(self) + pub fn stet(&mut self) -> STET_W { + STET_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sthr0.rs b/jh7110-vf2-13b-pac/src/uart5/sthr0.rs index bfd277a..764ff05 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sthr0.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sthr0.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sthr1.rs b/jh7110-vf2-13b-pac/src/uart5/sthr1.rs index cc79733..5d58855 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sthr1.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sthr1.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sthr10.rs b/jh7110-vf2-13b-pac/src/uart5/sthr10.rs index be2659d..ffc38ff 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sthr10.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sthr10.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sthr11.rs b/jh7110-vf2-13b-pac/src/uart5/sthr11.rs index 8613dd5..1f8147f 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sthr11.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sthr11.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sthr12.rs b/jh7110-vf2-13b-pac/src/uart5/sthr12.rs index b354b10..7d816f3 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sthr12.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sthr12.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sthr13.rs b/jh7110-vf2-13b-pac/src/uart5/sthr13.rs index 06df4bc..9283b6a 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sthr13.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sthr13.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sthr14.rs b/jh7110-vf2-13b-pac/src/uart5/sthr14.rs index e181dd0..2daf622 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sthr14.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sthr14.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sthr15.rs b/jh7110-vf2-13b-pac/src/uart5/sthr15.rs index 4825778..f70715e 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sthr15.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sthr15.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sthr2.rs b/jh7110-vf2-13b-pac/src/uart5/sthr2.rs index d390f10..f1a9c77 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sthr2.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sthr2.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sthr3.rs b/jh7110-vf2-13b-pac/src/uart5/sthr3.rs index a74fdf0..06aab9e 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sthr3.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sthr3.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sthr4.rs b/jh7110-vf2-13b-pac/src/uart5/sthr4.rs index 1ee6b87..f6e7944 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sthr4.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sthr4.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sthr5.rs b/jh7110-vf2-13b-pac/src/uart5/sthr5.rs index ca360fe..7873a53 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sthr5.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sthr5.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sthr6.rs b/jh7110-vf2-13b-pac/src/uart5/sthr6.rs index 18e6fac..87c81df 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sthr6.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sthr6.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sthr7.rs b/jh7110-vf2-13b-pac/src/uart5/sthr7.rs index 27072a3..9928b3d 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sthr7.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sthr7.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sthr8.rs b/jh7110-vf2-13b-pac/src/uart5/sthr8.rs index 15060b8..565cb1d 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sthr8.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sthr8.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/sthr9.rs b/jh7110-vf2-13b-pac/src/uart5/sthr9.rs index 58af642..e64fece 100644 --- a/jh7110-vf2-13b-pac/src/uart5/sthr9.rs +++ b/jh7110-vf2-13b-pac/src/uart5/sthr9.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `sthr` writer - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type STHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type STHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn sthr(&mut self) -> STHR_W { - STHR_W::new(self) + pub fn sthr(&mut self) -> STHR_W { + STHR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/tfl.rs b/jh7110-vf2-13b-pac/src/uart5/tfl.rs index e1faba6..db09fe3 100644 --- a/jh7110-vf2-13b-pac/src/uart5/tfl.rs +++ b/jh7110-vf2-13b-pac/src/uart5/tfl.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/tfr.rs b/jh7110-vf2-13b-pac/src/uart5/tfr.rs index 8e9ad91..714deff 100644 --- a/jh7110-vf2-13b-pac/src/uart5/tfr.rs +++ b/jh7110-vf2-13b-pac/src/uart5/tfr.rs @@ -14,7 +14,11 @@ is set to one). When FIFOs are implemented and enabled, reading this register gi } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/thr.rs b/jh7110-vf2-13b-pac/src/uart5/thr.rs index f910bd8..7845232 100644 --- a/jh7110-vf2-13b-pac/src/uart5/thr.rs +++ b/jh7110-vf2-13b-pac/src/uart5/thr.rs @@ -5,17 +5,21 @@ pub type W = crate::W; #[doc = "Field `thr` writer - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] -pub type THR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; +pub type THR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl W { #[doc = "Bits 0:7 - Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR\\[5\\]) is set. If in non-FIFO mode or FIFOs are disabled (FCR\\[0\\] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR\\[0\\] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost."] #[inline(always)] #[must_use] - pub fn thr(&mut self) -> THR_W { - THR_W::new(self) + pub fn thr(&mut self) -> THR_W { + THR_W::new(self, 0) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/ucv.rs b/jh7110-vf2-13b-pac/src/uart5/ucv.rs index 8a3be91..6497a08 100644 --- a/jh7110-vf2-13b-pac/src/uart5/ucv.rs +++ b/jh7110-vf2-13b-pac/src/uart5/ucv.rs @@ -12,7 +12,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; diff --git a/jh7110-vf2-13b-pac/src/uart5/usr.rs b/jh7110-vf2-13b-pac/src/uart5/usr.rs index 445a085..b96417d 100644 --- a/jh7110-vf2-13b-pac/src/uart5/usr.rs +++ b/jh7110-vf2-13b-pac/src/uart5/usr.rs @@ -40,7 +40,11 @@ impl R { } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits;